blob: 95673fd79feff392db01724968ebe6017b8b0047 [file] [log] [blame]
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001/*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Zhenyu Wang <zhenyu.z.wang@intel.com>
25 * Wu Fengguang <fengguang.wu@intel.com>
26 *
27 */
28
Wu Fengguang020abdb2010-04-19 13:13:06 +080029#define _GNU_SOURCE
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080030#include <unistd.h>
Wu Fengguang020abdb2010-04-19 13:13:06 +080031#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <err.h>
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080035#include <arpa/inet.h>
36#include "intel_gpu_tools.h"
37
Wu Fengguang020abdb2010-04-19 13:13:06 +080038static uint32_t devid;
39
40
41#define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
42#define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low))
43#define BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low))
44#define BIT(reg, n) BITS(reg, n, n)
45
46#define min_t(type, x, y) ({ \
47 type __min1 = (x); \
48 type __min2 = (y); \
49 __min1 < __min2 ? __min1: __min2; })
50
51#define OPNAME(names, index) \
52 names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)]
53
54#define dump_reg(reg, desc) \
55 do { \
56 dword = INREG(reg); \
57 printf("%-21s 0x%08x %s\n", # reg, dword, desc); \
58 } while (0)
59
60
61static char *pixel_clock[] = {
62 [0] = "25.2 / 1.001 MHz",
63 [1] = "25.2 MHz",
64 [2] = "27 MHz",
65 [3] = "27 * 1.001 MHz",
66 [4] = "54 MHz",
67 [5] = "54 * 1.001 MHz",
68 [6] = "74.25 / 1.001 MHz",
69 [7] = "74.25 MHz",
70 [8] = "148.5 / 1.001 MHz",
71 [9] = "148.5 MHz",
72 [10] = "Reserved",
73};
74
75static char *power_state[] = {
76 [0] = "D0",
77 [1] = "D1",
78 [2] = "D2",
79 [3] = "D3",
80};
81
82static char *stream_type[] = {
83 [0] = "default samples",
84 [1] = "one bit stream",
85 [2] = "DST stream",
86 [3] = "MLP stream",
87 [4] = "Reserved",
88};
89
90static char *dip_port[] = {
91 [0] = "Reserved",
92 [1] = "Digital Port B",
93 [2] = "Digital Port C",
94 [3] = "Digital Port D",
95};
96
97static char *dip_index[] = {
98 [0] = "Audio DIP",
99 [1] = "ACP DIP",
100 [2] = "ISRC1 DIP",
101 [3] = "ISRC2 DIP",
102 [4] = "Reserved",
103};
104
105static char *dip_trans[] = {
106 [0] = "disabled",
107 [1] = "reserved",
108 [2] = "send once",
109 [3] = "best effort",
110};
111
112static char *video_dip_index[] = {
113 [0] = "AVI DIP",
114 [1] = "Vendor-specific DIP",
Wu Fengguangf3f84bb2011-11-12 11:12:55 +0800115 [2] = "Gamut Metadata DIP",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800116 [3] = "Source Product Description DIP",
117};
118
119static char *video_dip_trans[] = {
120 [0] = "send once",
121 [1] = "send every vsync",
122 [2] = "send at least every other vsync",
123 [3] = "reserved",
124};
125
126static char *trans_to_port_sel[] = {
127 [0] = "no port",
128 [1] = "Digital Port B",
129 [2] = "Digital Port B",
130 [3] = "Digital Port B",
131 [4] = "Digital Port B",
132 [5 ... 7] = "reserved",
133};
134
135static char *transcoder_select[] = {
136 [0] = "Transcoder A",
137 [1] = "Transcoder B",
138 [2] = "Transcoder C",
139 [3] = "reserved",
140};
141
142static char *dp_port_width[] = {
143 [0] = "x1 mode",
144 [1] = "x2 mode",
Wu Fengguangcf4c12f2011-11-12 11:12:46 +0800145 [2] = "reserved",
146 [3] = "x4 mode",
147 [4 ... 7] = "reserved",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800148};
149
Wu Fengguang12861a92011-11-12 11:12:47 +0800150static char *bits_per_sample[] = {
151 [0] = "reserved",
152 [1] = "16 bits",
153 [2] = "24 bits",
154 [3] = "32 bits",
155 [4] = "20 bits",
156 [5] = "reserved",
157};
158
Wu Fengguangee949582011-11-12 11:12:53 +0800159static char *sdvo_hdmi_encoding[] = {
160 [0] = "SDVO",
161 [1] = "reserved",
162 [2] = "TMDS",
163 [3] = "reserved",
164};
Wu Fengguang12861a92011-11-12 11:12:47 +0800165
Wu Fengguang020abdb2010-04-19 13:13:06 +0800166static void do_self_tests(void)
167{
168 if (BIT(1, 0) != 1)
169 exit(1);
170 if (BIT(0x80000000, 31) != 1)
171 exit(2);
172 if (BITS(0xc0000000, 31, 30) != 3)
173 exit(3);
174}
175
176/*
177 * EagleLake registers
178 */
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800179#define AUD_CONFIG 0x62000
180#define AUD_DEBUG 0x62010
181#define AUD_VID_DID 0x62020
182#define AUD_RID 0x62024
183#define AUD_SUBN_CNT 0x62028
184#define AUD_FUNC_GRP 0x62040
185#define AUD_SUBN_CNT2 0x62044
186#define AUD_GRP_CAP 0x62048
187#define AUD_PWRST 0x6204c
188#define AUD_SUPPWR 0x62050
189#define AUD_SID 0x62054
190#define AUD_OUT_CWCAP 0x62070
191#define AUD_OUT_PCMSIZE 0x62074
192#define AUD_OUT_STR 0x62078
193#define AUD_OUT_DIG_CNVT 0x6207c
194#define AUD_OUT_CH_STR 0x62080
195#define AUD_OUT_STR_DESC 0x62084
196#define AUD_PINW_CAP 0x620a0
197#define AUD_PIN_CAP 0x620a4
198#define AUD_PINW_CONNLNG 0x620a8
199#define AUD_PINW_CONNLST 0x620ac
200#define AUD_PINW_CNTR 0x620b0
201#define AUD_PINW_UNSOLRESP 0x620b8
202#define AUD_CNTL_ST 0x620b4
203#define AUD_PINW_CONFIG 0x620bc
204#define AUD_HDMIW_STATUS 0x620d4
205#define AUD_HDMIW_HDMIEDID 0x6210c
206#define AUD_HDMIW_INFOFR 0x62118
207#define AUD_CONV_CHCNT 0x62120
208#define AUD_CTS_ENABLE 0x62128
209
210#define VIDEO_DIP_CTL 0x61170
211#define VIDEO_DIP_ENABLE (1<<31)
212#define VIDEO_DIP_ENABLE_AVI (1<<21)
213#define VIDEO_DIP_ENABLE_VENDOR (1<<22)
214#define VIDEO_DIP_ENABLE_SPD (1<<24)
215#define VIDEO_DIP_BUF_AVI (0<<19)
216#define VIDEO_DIP_BUF_VENDOR (1<<19)
217#define VIDEO_DIP_BUF_SPD (3<<19)
218#define VIDEO_DIP_TRANS_ONCE (0<<16)
219#define VIDEO_DIP_TRANS_1 (1<<16)
220#define VIDEO_DIP_TRANS_2 (2<<16)
221
222#define AUDIO_HOTPLUG_EN (1<<24)
223
224
Wu Fengguang020abdb2010-04-19 13:13:06 +0800225static void dump_eaglelake(void)
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800226{
227 uint32_t dword;
228 int i;
229
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800230 /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
231
232 dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
233 dump_reg(SDVOB, "Digital Display Port B Control Register");
234 dump_reg(SDVOC, "Digital Display Port C Control Register");
235 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
236
237 dump_reg(AUD_CONFIG, "Audio Configuration");
238 dump_reg(AUD_DEBUG, "Audio Debug");
239 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
240 dump_reg(AUD_RID, "Audio Revision ID");
241 dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
242 dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
243 dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
244 dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
245 dump_reg(AUD_PWRST, "Audio Power State");
246 dump_reg(AUD_SUPPWR, "Audio Supported Power States");
247 dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
248 dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
249 dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
250 dump_reg(AUD_OUT_STR, "Audio Stream Formats");
251 dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
252 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
253 dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
254 dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
255 dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
256 dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
257 dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
258 dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
259 dump_reg(AUD_PINW_UNSOLRESP,"Audio Unsolicited Response Enable");
260 dump_reg(AUD_CNTL_ST, "Audio Control State Register");
261 dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
262 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
263 dump_reg(AUD_HDMIW_HDMIEDID,"Audio HDMI Data EDID Block");
264 dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
265 dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
266 dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
267
268 printf("\nDetails:\n\n");
269
270 dword = INREG(AUD_VID_DID);
271 printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
272 printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
273
274 dword = INREG(AUD_RID);
275 printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
276 printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
277 printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8));
278 printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0));
279
280 dword = INREG(SDVOB);
281 printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
282 printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
283 printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
284 printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
285 printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
286
287 dword = INREG(SDVOC);
288 printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
289 printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
290 printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
291 printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
292 printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
293
294 dword = INREG(PORT_HOTPLUG_EN);
295 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)),
296 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)),
297 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
298 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
299 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
300 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
301 printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)),
302 printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)),
303
304 dword = INREG(VIDEO_DIP_CTL);
305 printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)),
306 printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
307 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
308 printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
309 printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21));
310 printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22));
311 printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24));
312 printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
313 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
314 printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
315 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
316 printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
317 printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
318
319 dword = INREG(AUD_CONFIG);
320 printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
321 OPNAME(pixel_clock, BITS(dword, 19, 16)));
322 printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
323 printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
324 printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
325
326 dword = INREG(AUD_DEBUG);
327 printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
328
329 dword = INREG(AUD_SUBN_CNT);
330 printf("AUD_SUBN_CNT starting node number\t0x%lx\n", BITS(dword, 23, 16));
331 printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
332
333 dword = INREG(AUD_SUBN_CNT2);
334 printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", BITS(dword, 24, 16));
335 printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
336
337 dword = INREG(AUD_FUNC_GRP);
338 printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
339 printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
340
341 dword = INREG(AUD_GRP_CAP);
342 printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16));
343 printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8));
344 printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0));
345
346 dword = INREG(AUD_PWRST);
347 printf("AUD_PWRST device power state\t\t%s\n",
348 power_state[BITS(dword, 5, 4)]);
349 printf("AUD_PWRST device power state setting\t%s\n",
350 power_state[BITS(dword, 1, 0)]);
351
352 dword = INREG(AUD_SUPPWR);
353 printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
354 printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
355 printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
356 printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
357
358 dword = INREG(AUD_OUT_CWCAP);
359 printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
360 printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
361 printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
362 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
363 printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
364 printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10));
365 printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9));
366 printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8));
367 printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7));
368 printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5));
369 printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4));
370 printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
371 printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2));
372 printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1));
373
374 dword = INREG(AUD_OUT_DIG_CNVT);
375 printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8));
376 printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7));
377 printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6));
378 printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5));
379 printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
380 printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
381 printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2));
382 printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1));
383 printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0));
384
385 dword = INREG(AUD_OUT_CH_STR);
386 printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4));
Wu Fengguang5032f682011-11-12 11:12:41 +0800387 printf("AUD_OUT_CH_STR lowest channel\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800388
389 dword = INREG(AUD_OUT_STR_DESC);
Wu Fengguang5032f682011-11-12 11:12:41 +0800390 printf("AUD_OUT_STR_DESC stream channels\t%lu\n", BITS(dword, 3, 0) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800391 printf("AUD_OUT_STR_DESC Bits per Sample\t[%#lx] %s\n",
392 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800393
394 dword = INREG(AUD_PINW_CAP);
395 printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
396 printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
Wu Fengguang5032f682011-11-12 11:12:41 +0800397 printf("AUD_PINW_CAP channel count\t\t%lu\n",
398 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800399 printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12));
400 printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
401 printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10));
402 printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9));
403 printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8));
404 printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7));
405 printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5));
406 printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4));
407 printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3));
408 printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2));
409 printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1));
410
411
412 dword = INREG(AUD_PIN_CAP);
413 printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16));
414 printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7));
415 printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4));
416 printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
417
418 dword = INREG(AUD_PINW_CNTR);
419 printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8));
420 printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6));
421 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
422 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
423 printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
424 BITS(dword, 2, 0),
425 OPNAME(stream_type, BITS(dword, 2, 0)));
426
427 dword = INREG(AUD_PINW_UNSOLRESP);
428 printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
429
430 dword = INREG(AUD_CNTL_ST);
431 printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
432 printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22));
433 printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
434 printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
435 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
436 printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
437 BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
438 printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
439 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
440 printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
441 printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15));
442 printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14));
443 printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4));
444 printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
445 printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
446
447 dword = INREG(AUD_HDMIW_STATUS);
448 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
449 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30));
450 printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29));
451 printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28));
452
453 dword = INREG(AUD_CONV_CHCNT);
454 printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
455 printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1);
456
457 printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
458 for (i = 0; i < 8; i++) {
459 OUTREG(AUD_CONV_CHCNT, i);
460 dword = INREG(AUD_CONV_CHCNT);
461 printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i, BITS(dword, 7, 4));
462 }
463
Wu Fengguangf32aecb2011-11-12 11:12:50 +0800464 printf("AUD_HDMIW_HDMIEDID HDMI ELD:\n\t");
465 dword = INREG(AUD_CNTL_ST);
466 dword &= ~BITMASK(8, 5);
467 OUTREG(AUD_CNTL_ST, dword);
468 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
469 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID)));
470 printf("\n");
471
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800472 printf("AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t");
473 dword = INREG(AUD_CNTL_ST);
474 dword &= ~BITMASK(20, 18);
475 dword &= ~BITMASK(3, 0);
476 OUTREG(AUD_CNTL_ST, dword);
477 for (i = 0; i < 8; i++)
478 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR)));
479 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800480}
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800481
Wu Fengguang020abdb2010-04-19 13:13:06 +0800482#undef AUD_RID
483#undef AUD_VID_DID
484#undef AUD_PWRST
485#undef AUD_OUT_CH_STR
486#undef AUD_HDMIW_STATUS
487
488/*
489 * IronLake registers
490 */
491#define AUD_CONFIG_A 0xE2000
492#define AUD_CONFIG_B 0xE2100
493#define AUD_CTS_ENABLE_A 0xE2028
494#define AUD_CTS_ENABLE_B 0xE2128
495#define AUD_MISC_CTRL_A 0xE2010
496#define AUD_MISC_CTRL_B 0xE2110
497#define AUD_VID_DID 0xE2020
498#define AUD_RID 0xE2024
499#define AUD_PWRST 0xE204C
500#define AUD_PORT_EN_HD_CFG 0xE207C
501#define AUD_OUT_DIG_CNVT_A 0xE2080
502#define AUD_OUT_DIG_CNVT_B 0xE2180
503#define AUD_OUT_CH_STR 0xE2088
504#define AUD_OUT_STR_DESC_A 0xE2084
505#define AUD_OUT_STR_DESC_B 0xE2184
506#define AUD_PINW_CONNLNG_LIST 0xE20A8
507#define AUD_PINW_CONNLNG_SEL 0xE20AC
508#define AUD_CNTL_ST_A 0xE20B4
509#define AUD_CNTL_ST_B 0xE21B4
510#define AUD_CNTL_ST2 0xE20C0
511#define AUD_HDMIW_STATUS 0xE20D4
512#define AUD_HDMIW_HDMIEDID_A 0xE2050
513#define AUD_HDMIW_HDMIEDID_B 0xE2150
514#define AUD_HDMIW_INFOFR_A 0xE2054
515#define AUD_HDMIW_INFOFR_B 0xE2154
516
517static void dump_ironlake(void)
518{
519 uint32_t dword;
520 int i;
521
522 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
523 dump_reg(HDMIC, "HDMI Port C Control");
524 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguangb5ca6b42011-11-12 11:12:48 +0800525 dump_reg(PCH_DP_B, "DisplayPort B Control Register");
526 dump_reg(PCH_DP_C, "DisplayPort C Control Register");
527 dump_reg(PCH_DP_D, "DisplayPort D Control Register");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800528 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
529 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
530 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
531 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800532 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
533 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
534 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
535 dump_reg(AUD_RID, "Audio Revision ID");
536 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
537 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800538 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
539 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800540 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800541 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
542 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800543 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
544 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800545 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
546 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800547 dump_reg(AUD_CNTL_ST2, "Audio Control State 2");
548 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800549 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
550 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
551 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
552 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800553
554 printf("\nDetails:\n\n");
555
556 dword = INREG(AUD_VID_DID);
557 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
558 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
559
560 dword = INREG(AUD_RID);
561 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
562 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
563 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
564 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
565
566 dword = INREG(HDMIB);
567 printf("HDMIB HDMIB_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
568 printf("HDMIB Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
569 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang821e07d2011-11-12 11:12:54 +0800570 printf("HDMIB SDVOB Hot Plug Interrupt Detect Enable\t\t%lu\n", BIT(dword, 23));
Wu Fengguang305443c2011-11-12 11:12:43 +0800571 printf("HDMIB Digital_Port_B_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +0800572 printf("HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n",
573 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +0800574 printf("HDMIB Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
575 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
576
577 dword = INREG(HDMIC);
578 printf("HDMIC HDMIC_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
579 printf("HDMIC Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
580 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang305443c2011-11-12 11:12:43 +0800581 printf("HDMIC Digital_Port_C_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +0800582 printf("HDMIC Encoding\t\t\t\t\t\t[0x%lx] %s\n",
583 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +0800584 printf("HDMIC Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
585 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
586
587 dword = INREG(HDMID);
588 printf("HDMID HDMID_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
589 printf("HDMID Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
590 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
591 printf("HDMID Digital_Port_D_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +0800592 printf("HDMID Encoding\t\t\t\t\t\t[0x%lx] %s\n",
593 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +0800594 printf("HDMID Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
595 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
596
Wu Fengguangb5ca6b42011-11-12 11:12:48 +0800597 dword = INREG(PCH_DP_B);
598 printf("PCH_DP_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
599 printf("PCH_DP_B Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
600 printf("PCH_DP_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
601 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
602 printf("PCH_DP_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
603 printf("PCH_DP_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
604 printf("PCH_DP_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
605
606 dword = INREG(PCH_DP_C);
607 printf("PCH_DP_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
608 printf("PCH_DP_C Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
609 printf("PCH_DP_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
610 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
611 printf("PCH_DP_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
612 printf("PCH_DP_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
613 printf("PCH_DP_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
614
615 dword = INREG(PCH_DP_D);
616 printf("PCH_DP_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
617 printf("PCH_DP_D Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
618 printf("PCH_DP_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
619 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
620 printf("PCH_DP_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
621 printf("PCH_DP_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
622 printf("PCH_DP_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
623
Wu Fengguang020abdb2010-04-19 13:13:06 +0800624 dword = INREG(AUD_CONFIG_A);
625 printf("AUD_CONFIG_A Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
626 OPNAME(pixel_clock, BITS(dword, 19, 16)));
627 dword = INREG(AUD_CONFIG_B);
628 printf("AUD_CONFIG_B Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
629 OPNAME(pixel_clock, BITS(dword, 19, 16)));
630
631 dword = INREG(AUD_CTS_ENABLE_A);
632 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
633 printf("AUD_CTS_ENABLE_A CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
634 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
635 dword = INREG(AUD_CTS_ENABLE_B);
636 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
637 printf("AUD_CTS_ENABLE_B CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
638 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
639
640 dword = INREG(AUD_MISC_CTRL_A);
641 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
642 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
643 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
644 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
645 dword = INREG(AUD_MISC_CTRL_B);
646 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
647 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
648 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
649 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
650
651 dword = INREG(AUD_PWRST);
652 printf("AUD_PWRST Function_Group_Device_Power_State_Current\t%s\n", power_state[BITS(dword, 23, 22)]);
653 printf("AUD_PWRST Function_Group_Device_Power_State_Set \t%s\n", power_state[BITS(dword, 21, 20)]);
654 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
655 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
656 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
657 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
658 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
659 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
660 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
661 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
662 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
663 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
664
665 dword = INREG(AUD_PORT_EN_HD_CFG);
666 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
667 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
668 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
669 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
670 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 12));
671 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 13));
672 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 14));
673 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 16));
674 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 17));
675 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 18));
676
677 dword = INREG(AUD_OUT_DIG_CNVT_A);
678 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
679 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
680 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
681 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800682 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800683 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
684 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
685 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
686 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800687 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800688
689 dword = INREG(AUD_OUT_DIG_CNVT_B);
690 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
691 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
692 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
693 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800694 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800695 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
696 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
697 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
698 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800699 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800700
701 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
702 for (i = 0; i < 8; i++) {
703 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
704 dword = INREG(AUD_OUT_CH_STR);
705 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
706 1 + BITS(dword, 3, 0),
707 1 + BITS(dword, 7, 4),
708 1 + BITS(dword, 15, 12),
709 1 + BITS(dword, 23, 20));
710 }
711
712 dword = INREG(AUD_OUT_STR_DESC_A);
713 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800714 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800715 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
716 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800717 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
718
719 dword = INREG(AUD_OUT_STR_DESC_B);
720 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800721 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800722 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
723 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800724 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
725
726 dword = INREG(AUD_PINW_CONNLNG_SEL);
727 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%lu\n", BITS(dword, 7, 0));
728 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%lu\n", BITS(dword, 15, 8));
729 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%lu\n", BITS(dword, 23, 16));
730
731 dword = INREG(AUD_CNTL_ST_A);
732 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
733 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
734 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800735 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800736 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
737 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
738 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
739 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
740 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
Wu Fengguangc0635c32011-11-12 11:12:51 +0800741 printf("AUD_CNTL_ST_A ELD_access_address\t\t\t%lu\n", BITS(dword, 9, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800742
743 dword = INREG(AUD_CNTL_ST_B);
744 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
745 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
746 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800747 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800748 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
749 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
750 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
751 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
752 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
Wu Fengguangc0635c32011-11-12 11:12:51 +0800753 printf("AUD_CNTL_ST_B ELD_access_address\t\t\t%lu\n", BITS(dword, 9, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800754
755 dword = INREG(AUD_CNTL_ST2);
756 printf("AUD_CNTL_ST2 CP_ReadyB\t\t\t\t\t%lu\n", BIT(dword, 1));
757 printf("AUD_CNTL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
758 printf("AUD_CNTL_ST2 CP_ReadyC\t\t\t\t\t%lu\n", BIT(dword, 5));
759 printf("AUD_CNTL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
760 printf("AUD_CNTL_ST2 CP_ReadyD\t\t\t\t\t%lu\n", BIT(dword, 9));
761 printf("AUD_CNTL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
762
763 dword = INREG(AUD_HDMIW_STATUS);
764 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
765 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
766 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
767 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
768 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
769 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 29));
770
771 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
772 dword = INREG(AUD_CNTL_ST_A);
773 dword &= ~BITMASK(9, 5);
774 OUTREG(AUD_CNTL_ST_A, dword);
775 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
776 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
777 printf("\n");
778
779 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
780 dword = INREG(AUD_CNTL_ST_B);
781 dword &= ~BITMASK(9, 5);
782 OUTREG(AUD_CNTL_ST_B, dword);
783 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
784 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
785 printf("\n");
786
787 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
788 dword = INREG(AUD_CNTL_ST_A);
789 dword &= ~BITMASK(20, 18);
790 dword &= ~BITMASK(3, 0);
791 OUTREG(AUD_CNTL_ST_A, dword);
792 for (i = 0; i < 8; i++)
793 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
794 printf("\n");
795
796 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
797 dword = INREG(AUD_CNTL_ST_B);
798 dword &= ~BITMASK(20, 18);
799 dword &= ~BITMASK(3, 0);
800 OUTREG(AUD_CNTL_ST_B, dword);
801 for (i = 0; i < 8; i++)
802 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
803 printf("\n");
804
805}
806
807
808#undef AUD_CONFIG_A
809#undef AUD_MISC_CTRL_A
810#undef AUD_VID_DID
811#undef AUD_RID
812#undef AUD_CTS_ENABLE_A
813#undef AUD_PWRST
814#undef AUD_HDMIW_HDMIEDID_A
815#undef AUD_HDMIW_INFOFR_A
816#undef AUD_PORT_EN_HD_CFG
817#undef AUD_OUT_DIG_CNVT_A
818#undef AUD_OUT_STR_DESC_A
819#undef AUD_OUT_CH_STR
820#undef AUD_PINW_CONNLNG_LIST
821#undef AUD_CNTL_ST_A
822#undef AUD_HDMIW_STATUS
823#undef AUD_CONFIG_B
824#undef AUD_MISC_CTRL_B
825#undef AUD_CTS_ENABLE_B
826#undef AUD_HDMIW_HDMIEDID_B
827#undef AUD_HDMIW_INFOFR_B
828#undef AUD_OUT_DIG_CNVT_B
829#undef AUD_OUT_STR_DESC_B
830#undef AUD_CNTL_ST_B
831
832/*
833 * CougarPoint registers
834 */
Wu Fengguang97d20312011-11-12 11:12:45 +0800835#define DP_CTL_B 0xE4100
Wu Fengguang020abdb2010-04-19 13:13:06 +0800836#define DP_CTL_C 0xE4200
837#define DP_AUX_CTL_C 0xE4210
838#define DP_AUX_TST_C 0xE4228
839#define SPORT_DDI_CRC_C 0xE4250
840#define SPORT_DDI_CRC_R 0xE4264
841#define DP_CTL_D 0xE4300
842#define DP_AUX_CTL_D 0xE4310
843#define DP_AUX_TST_D 0xE4328
844#define SPORT_DDI_CRC_CTL_D 0xE4350
845#define AUD_CONFIG_A 0xE5000
846#define AUD_MISC_CTRL_A 0xE5010
847#define AUD_VID_DID 0xE5020
848#define AUD_RID 0xE5024
849#define AUD_CTS_ENABLE_A 0xE5028
850#define AUD_PWRST 0xE504C
851#define AUD_HDMIW_HDMIEDID_A 0xE5050
852#define AUD_HDMIW_INFOFR_A 0xE5054
853#define AUD_PORT_EN_HD_CFG 0xE507C
854#define AUD_OUT_DIG_CNVT_A 0xE5080
855#define AUD_OUT_STR_DESC_A 0xE5084
856#define AUD_OUT_CH_STR 0xE5088
857#define AUD_PINW_CONNLNG_LIST 0xE50A8
858#define AUD_PINW_CONNLNG_SELA 0xE50AC
859#define AUD_CNTL_ST_A 0xE50B4
860#define AUD_CNTRL_ST2 0xE50C0
861#define AUD_CNTRL_ST3 0xE50C4
862#define AUD_HDMIW_STATUS 0xE50D4
863#define AUD_CONFIG_B 0xE5100
864#define AUD_MISC_CTRL_B 0xE5110
865#define AUD_CTS_ENABLE_B 0xE5128
866#define AUD_HDMIW_HDMIEDID_B 0xE5150
867#define AUD_HDMIW_INFOFR_B 0xE5154
868#define AUD_OUT_DIG_CNVT_B 0xE5180
869#define AUD_OUT_STR_DESC_B 0xE5184
870#define AUD_CNTL_ST_B 0xE51B4
871#define AUD_CONFIG_C 0xE5200
872#define AUD_MISC_CTRL_C 0xE5210
873#define AUD_CTS_ENABLE_C 0xE5228
874#define AUD_HDMIW_HDMIEDID_C 0xE5250
875#define AUD_HDMIW_INFOFR_C 0xE5254
876#define AUD_OUT_DIG_CNVT_C 0xE5280
877#define AUD_OUT_STR_DESC_C 0xE5284
878#define AUD_CNTL_ST_C 0xE52B4
879#define AUD_CONFIG_D 0xE5300
880#define AUD_MISC_CTRL_D 0xE5310
881#define AUD_CTS_ENABLE_D 0xE5328
882#define AUD_HDMIW_HDMIEDID_D 0xE5350
883#define AUD_HDMIW_INFOFR_D 0xE5354
884#define AUD_OUT_DIG_CNVT_D 0xE5380
885#define AUD_OUT_STR_DESC_D 0xE5384
886#define AUD_CNTL_ST_D 0xE53B4
887
Wu Fengguange321f132011-11-12 11:12:52 +0800888#define VIDEO_DIP_CTL_A 0xE0200
889#define VIDEO_DIP_CTL_B 0xE1200
890#define VIDEO_DIP_CTL_C 0xE2200
891#define VIDEO_DIP_CTL_D 0xE3200
892
Wu Fengguang020abdb2010-04-19 13:13:06 +0800893
894static void dump_cpt(void)
895{
896 uint32_t dword;
897 int i;
898
899 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
900 dump_reg(HDMIC, "HDMI Port C Control");
901 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguang97d20312011-11-12 11:12:45 +0800902 dump_reg(DP_CTL_B, "DisplayPort B Control");
903 dump_reg(DP_CTL_C, "DisplayPort C Control");
904 dump_reg(DP_CTL_D, "DisplayPort D Control");
905 dump_reg(TRANS_DP_CTL_A, "Transcoder A DisplayPort Control");
906 dump_reg(TRANS_DP_CTL_B, "Transcoder B DisplayPort Control");
907 dump_reg(TRANS_DP_CTL_C, "Transcoder C DisplayPort Control");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800908 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
909 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
910 dump_reg(AUD_CONFIG_C, "Audio Configuration - Transcoder C");
911 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
912 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
913 dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800914 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
915 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
916 dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C");
917 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
918 dump_reg(AUD_RID, "Audio Revision ID");
919 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
920 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800921 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
922 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
923 dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800924 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800925 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
926 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
927 dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800928 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
929 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800930 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
931 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
932 dump_reg(AUD_CNTL_ST_C, "Audio Control State Register - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800933 dump_reg(AUD_CNTRL_ST2, "Audio Control State 2");
934 dump_reg(AUD_CNTRL_ST3, "Audio Control State 3");
935 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800936 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
937 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
938 dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block - Transcoder C");
939 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
940 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
941 dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800942
943 printf("\nDetails:\n\n");
944
Wu Fengguange321f132011-11-12 11:12:52 +0800945 dword = INREG(VIDEO_DIP_CTL_A);
946 printf("VIDEO_DIP_CTL_A Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
947 printf("VIDEO_DIP_CTL_A GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
948 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
949 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
950 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
951 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
952 printf("VIDEO_DIP_CTL_A Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
953 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
954 printf("VIDEO_DIP_CTL_A Video_DIP_frequency\t\t\t[0x%lx] %s\n",
955 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
956 printf("VIDEO_DIP_CTL_A Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
957 printf("VIDEO_DIP_CTL_A Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
958
959 dword = INREG(VIDEO_DIP_CTL_B);
960 printf("VIDEO_DIP_CTL_B Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
961 printf("VIDEO_DIP_CTL_B GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
962 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
963 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
964 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
965 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
966 printf("VIDEO_DIP_CTL_B Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
967 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
968 printf("VIDEO_DIP_CTL_B Video_DIP_frequency\t\t\t[0x%lx] %s\n",
969 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
970 printf("VIDEO_DIP_CTL_B Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
971 printf("VIDEO_DIP_CTL_B Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
972
973 dword = INREG(VIDEO_DIP_CTL_C);
974 printf("VIDEO_DIP_CTL_C Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
975 printf("VIDEO_DIP_CTL_C GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
976 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
977 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
978 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
979 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
980 printf("VIDEO_DIP_CTL_C Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
981 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
982 printf("VIDEO_DIP_CTL_C Video_DIP_frequency\t\t\t[0x%lx] %s\n",
983 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
984 printf("VIDEO_DIP_CTL_C Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
985 printf("VIDEO_DIP_CTL_C Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
986
Wu Fengguang020abdb2010-04-19 13:13:06 +0800987 dword = INREG(AUD_VID_DID);
988 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
989 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
990
991 dword = INREG(AUD_RID);
992 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
993 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
994 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
995 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
996
997 dword = INREG(HDMIB);
998 printf("HDMIB Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
999 printf("HDMIB Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
1000 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
1001 printf("HDMIB sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
1002 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang821e07d2011-11-12 11:12:54 +08001003 printf("HDMIB SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001004 printf("HDMIB Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +08001005 printf("HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n",
1006 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001007 printf("HDMIB HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
1008 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
1009
1010 dword = INREG(HDMIC);
1011 printf("HDMIC Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
1012 printf("HDMIC Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
1013 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
1014 printf("HDMIC sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
1015 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang821e07d2011-11-12 11:12:54 +08001016 printf("HDMIC SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001017 printf("HDMIC Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +08001018 printf("HDMIC Encoding\t\t\t\t\t\t[0x%lx] %s\n",
1019 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001020 printf("HDMIC HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
1021 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
1022
1023 dword = INREG(HDMID);
1024 printf("HDMID Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
1025 printf("HDMID Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
1026 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
1027 printf("HDMID sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
1028 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang821e07d2011-11-12 11:12:54 +08001029 printf("HDMID SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001030 printf("HDMID Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguangee949582011-11-12 11:12:53 +08001031 printf("HDMID Encoding\t\t\t\t\t\t[0x%lx] %s\n",
1032 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001033 printf("HDMID HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
1034 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
1035
Wu Fengguang97d20312011-11-12 11:12:45 +08001036 dword = INREG(DP_CTL_B);
1037 printf("DP_CTL_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1038 printf("DP_CTL_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +08001039 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +08001040 printf("DP_CTL_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1041 printf("DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1042 printf("DP_CTL_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001043
Wu Fengguang97d20312011-11-12 11:12:45 +08001044 dword = INREG(DP_CTL_C);
1045 printf("DP_CTL_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1046 printf("DP_CTL_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +08001047 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +08001048 printf("DP_CTL_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1049 printf("DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1050 printf("DP_CTL_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001051
Wu Fengguang97d20312011-11-12 11:12:45 +08001052 dword = INREG(DP_CTL_D);
1053 printf("DP_CTL_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1054 printf("DP_CTL_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +08001055 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +08001056 printf("DP_CTL_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1057 printf("DP_CTL_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1058 printf("DP_CTL_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001059
1060 dword = INREG(AUD_CONFIG_A);
1061 printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1062 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1063 dword = INREG(AUD_CONFIG_B);
1064 printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1065 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1066 dword = INREG(AUD_CONFIG_C);
1067 printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1068 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1069
1070 dword = INREG(AUD_CTS_ENABLE_A);
1071 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1072 printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1073 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1074 dword = INREG(AUD_CTS_ENABLE_B);
1075 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1076 printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1077 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1078 dword = INREG(AUD_CTS_ENABLE_C);
1079 printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1080 printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1081 printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1082
1083 dword = INREG(AUD_MISC_CTRL_A);
1084 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1085 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1086 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1087 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1088 dword = INREG(AUD_MISC_CTRL_B);
1089 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1090 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1091 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1092 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1093 dword = INREG(AUD_MISC_CTRL_C);
1094 printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1095 printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1096 printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1097 printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1098
1099 dword = INREG(AUD_PWRST);
1100 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]);
1101 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]);
1102 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
1103 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
1104 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
1105 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
1106 printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]);
1107 printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[BITS(dword, 21, 20)]);
1108 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
1109 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
1110 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
1111 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
1112 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
1113 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
1114
1115 dword = INREG(AUD_PORT_EN_HD_CFG);
1116 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
1117 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
1118 printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2));
1119 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
1120 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
1121 printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", BITS(dword, 15, 12));
1122 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16));
1123 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17));
1124 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18));
1125 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20));
1126 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21));
1127 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22));
1128
1129 dword = INREG(AUD_OUT_DIG_CNVT_A);
1130 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
1131 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1132 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1133 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001134 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001135 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1136 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
1137 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1138 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1139 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1140
1141 dword = INREG(AUD_OUT_DIG_CNVT_B);
1142 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
1143 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1144 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1145 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001146 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001147 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1148 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
1149 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1150 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1151 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1152
1153 dword = INREG(AUD_OUT_DIG_CNVT_C);
1154 printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", BIT(dword, 1));
1155 printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1156 printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1157 printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001158 printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001159 printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1160 printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", BIT(dword, 7));
1161 printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1162 printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1163 printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1164
1165 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
1166 for (i = 0; i < 8; i++) {
1167 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
1168 dword = INREG(AUD_OUT_CH_STR);
1169 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
1170 1 + BITS(dword, 3, 0),
1171 1 + BITS(dword, 7, 4),
1172 1 + BITS(dword, 15, 12),
1173 1 + BITS(dword, 23, 20));
1174 }
1175
1176 dword = INREG(AUD_OUT_STR_DESC_A);
1177 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001178 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001179 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
1180 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001181 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1182
1183 dword = INREG(AUD_OUT_STR_DESC_B);
1184 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001185 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001186 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
1187 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001188 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1189
1190 dword = INREG(AUD_OUT_STR_DESC_C);
1191 printf("AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001192 printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001193 printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t[%#lx] %s\n",
1194 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001195 printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1196
1197 dword = INREG(AUD_PINW_CONNLNG_SEL);
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001198 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n", BITS(dword, 7, 0));
1199 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n", BITS(dword, 15, 8));
1200 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n", BITS(dword, 23, 16));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001201
1202 dword = INREG(AUD_CNTL_ST_A);
1203 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1204 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001205 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1206 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001207 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1208 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
1209 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1210 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1211 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1212
1213 dword = INREG(AUD_CNTL_ST_B);
1214 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1215 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001216 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1217 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001218 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1219 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
1220 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1221 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1222 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1223
1224 dword = INREG(AUD_CNTL_ST_C);
1225 printf("AUD_CNTL_ST_C DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1226 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001227 printf("AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1228 printf("AUD_CNTL_ST_C DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001229 printf("AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1230 printf("AUD_CNTL_ST_C DIP_transmission_frequency\t\t[0x%lx] %s\n",
1231 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1232 printf("AUD_CNTL_ST_C ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1233 printf("AUD_CNTL_ST_C ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1234
1235 dword = INREG(AUD_CNTRL_ST2);
1236 printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", BIT(dword, 1));
1237 printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
1238 printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", BIT(dword, 5));
1239 printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
1240 printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", BIT(dword, 9));
1241 printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
1242
1243 dword = INREG(AUD_CNTRL_ST3);
1244 printf("AUD_CNTRL_ST3 TransA_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 3));
1245 printf("AUD_CNTRL_ST3 TransA_to_Port_Sel\t\t\t[%#lx] %s\n",
1246 BITS(dword, 2, 0), trans_to_port_sel[BITS(dword, 2, 0)]);
1247 printf("AUD_CNTRL_ST3 TransB_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 7));
1248 printf("AUD_CNTRL_ST3 TransB_to_Port_Sel\t\t\t[%#lx] %s\n",
1249 BITS(dword, 6, 4), trans_to_port_sel[BITS(dword, 6, 4)]);
1250 printf("AUD_CNTRL_ST3 TransC_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 11));
1251 printf("AUD_CNTRL_ST3 TransC_to_Port_Sel\t\t\t[%#lx] %s\n",
1252 BITS(dword, 10, 8), trans_to_port_sel[BITS(dword, 10, 8)]);
1253
1254 dword = INREG(AUD_HDMIW_STATUS);
1255 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27));
1256 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26));
1257 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
1258 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
1259 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
1260 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
1261 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
1262 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24));
1263
1264 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
1265 dword = INREG(AUD_CNTL_ST_A);
1266 dword &= ~BITMASK(9, 5);
1267 OUTREG(AUD_CNTL_ST_A, dword);
1268 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1269 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
1270 printf("\n");
1271
1272 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
1273 dword = INREG(AUD_CNTL_ST_B);
1274 dword &= ~BITMASK(9, 5);
1275 OUTREG(AUD_CNTL_ST_B, dword);
1276 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1277 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
1278 printf("\n");
1279
1280 printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
1281 dword = INREG(AUD_CNTL_ST_C);
1282 dword &= ~BITMASK(9, 5);
1283 OUTREG(AUD_CNTL_ST_C, dword);
1284 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1285 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
1286 printf("\n");
1287
1288 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
1289 dword = INREG(AUD_CNTL_ST_A);
1290 dword &= ~BITMASK(20, 18);
1291 dword &= ~BITMASK(3, 0);
1292 OUTREG(AUD_CNTL_ST_A, dword);
1293 for (i = 0; i < 8; i++)
1294 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
1295 printf("\n");
1296
1297 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
1298 dword = INREG(AUD_CNTL_ST_B);
1299 dword &= ~BITMASK(20, 18);
1300 dword &= ~BITMASK(3, 0);
1301 OUTREG(AUD_CNTL_ST_B, dword);
1302 for (i = 0; i < 8; i++)
1303 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
1304 printf("\n");
1305
1306 printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
1307 dword = INREG(AUD_CNTL_ST_C);
1308 dword &= ~BITMASK(20, 18);
1309 dword &= ~BITMASK(3, 0);
1310 OUTREG(AUD_CNTL_ST_C, dword);
1311 for (i = 0; i < 8; i++)
1312 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
1313 printf("\n");
1314
1315}
1316
1317int main(int argc, char **argv)
1318{
1319 struct pci_device *pci_dev;
1320
1321 pci_dev = intel_get_pci_device();
1322 devid = pci_dev->device_id; /* XXX not true when mapping! */
1323
1324 do_self_tests();
1325
1326 if (argc == 2)
1327 intel_map_file(argv[1]);
1328 else
1329 intel_get_mmio(pci_dev);
1330
Wu Fengguang63e3c372011-11-12 11:12:44 +08001331 if (IS_GEN6(devid) || IS_GEN7(devid) || getenv("HAS_PCH_SPLIT")) {
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001332 printf("%s audio registers:\n\n",
1333 IS_GEN6(devid) ? "SandyBridge" : "IvyBridge");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001334 intel_check_pch();
1335 dump_cpt();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001336 } else if (IS_GEN5(devid)) {
1337 printf("Ironlake audio registers:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001338 dump_ironlake();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001339 } else if (IS_G4X(devid)) {
1340 printf("G45 audio registers:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001341 dump_eaglelake();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001342 }
Wu Fengguang020abdb2010-04-19 13:13:06 +08001343
1344 return 0;
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001345}