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Arnold Schwaighofer92226dd2007-10-12 21:53:12 +00001//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that X86 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
Evan Cheng0cc39452006-01-16 21:21:29 +000016#include "X86InstrBuilder.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000017#include "X86ISelLowering.h"
Evan Chenge8bd0a32006-06-06 23:30:24 +000018#include "X86MachineFunctionInfo.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000019#include "X86TargetMachine.h"
20#include "llvm/CallingConv.h"
Evan Cheng223547a2006-01-31 22:28:30 +000021#include "llvm/Constants.h"
Evan Cheng347d5f72006-04-28 21:29:37 +000022#include "llvm/DerivedTypes.h"
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +000023#include "llvm/GlobalVariable.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000024#include "llvm/Function.h"
Evan Cheng6be2c582006-04-05 23:38:46 +000025#include "llvm/Intrinsics.h"
Evan Cheng14b32e12007-12-11 01:46:18 +000026#include "llvm/ADT/BitVector.h"
Evan Cheng30b37b52006-03-13 23:18:16 +000027#include "llvm/ADT/VectorExtras.h"
Chris Lattner362e98a2007-02-27 04:43:02 +000028#include "llvm/CodeGen/CallingConvLower.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000029#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Cheng4a460802006-01-11 00:33:36 +000030#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
Evan Chenga844bde2008-02-02 04:07:54 +000032#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000033#include "llvm/CodeGen/MachineRegisterInfo.h"
Dan Gohman69de1932008-02-06 22:27:42 +000034#include "llvm/CodeGen/PseudoSourceValue.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000035#include "llvm/CodeGen/SelectionDAG.h"
Evan Chengef6ffb12006-01-31 03:14:29 +000036#include "llvm/Support/MathExtras.h"
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +000037#include "llvm/Support/Debug.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000038#include "llvm/Target/TargetOptions.h"
Evan Cheng14b32e12007-12-11 01:46:18 +000039#include "llvm/ADT/SmallSet.h"
Chris Lattner1a60aa72006-10-31 19:42:44 +000040#include "llvm/ADT/StringExtras.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000041using namespace llvm;
42
Evan Cheng10e86422008-04-25 19:11:04 +000043// Forward declarations.
Dan Gohman475871a2008-07-27 21:46:04 +000044static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
Evan Cheng10e86422008-04-25 19:11:04 +000045
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +000046X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000047 : TargetLowering(TM) {
Evan Cheng559806f2006-01-27 08:10:46 +000048 Subtarget = &TM.getSubtarget<X86Subtarget>();
Dale Johannesenf1fc3a82007-09-23 14:52:20 +000049 X86ScalarSSEf64 = Subtarget->hasSSE2();
50 X86ScalarSSEf32 = Subtarget->hasSSE1();
Evan Cheng25ab6902006-09-08 06:48:29 +000051 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
Anton Korobeynikovbff66b02008-09-09 18:22:57 +000052
Chris Lattnerd43d00c2008-01-24 08:07:48 +000053 bool Fast = false;
Evan Cheng559806f2006-01-27 08:10:46 +000054
Anton Korobeynikov2365f512007-07-14 14:06:15 +000055 RegInfo = TM.getRegisterInfo();
Anton Korobeynikovbff66b02008-09-09 18:22:57 +000056 TD = getTargetData();
Anton Korobeynikov2365f512007-07-14 14:06:15 +000057
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000058 // Set up the TargetLowering object.
59
60 // X86 is weird, it always uses i8 for shift amounts and setcc results.
61 setShiftAmountType(MVT::i8);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000062 setSetCCResultContents(ZeroOrOneSetCCResult);
Evan Cheng0b2afbd2006-01-25 09:15:17 +000063 setSchedulingPreference(SchedulingForRegPressure);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000064 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
Evan Cheng25ab6902006-09-08 06:48:29 +000065 setStackPointerRegisterToSaveRestore(X86StackPtr);
Evan Cheng714554d2006-03-16 21:47:42 +000066
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000067 if (Subtarget->isTargetDarwin()) {
Evan Chengdf57fa02006-03-17 20:31:41 +000068 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000069 setUseUnderscoreSetJmp(false);
70 setUseUnderscoreLongJmp(false);
Anton Korobeynikov317848f2007-01-03 11:43:14 +000071 } else if (Subtarget->isTargetMingw()) {
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000072 // MS runtime is weird: it exports _setjmp, but longjmp!
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(false);
75 } else {
76 setUseUnderscoreSetJmp(true);
77 setUseUnderscoreLongJmp(true);
78 }
79
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000080 // Set up the register classes.
Evan Cheng069287d2006-05-16 07:21:53 +000081 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
82 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
83 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
Evan Cheng25ab6902006-09-08 06:48:29 +000084 if (Subtarget->is64Bit())
85 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000086
Duncan Sandsf9c98e62008-01-23 20:39:46 +000087 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
Evan Chengc5484282006-10-04 00:56:09 +000088
Chris Lattnerddf89562008-01-17 19:59:44 +000089 // We don't accept any truncstore of integer registers.
90 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
91 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
92 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
93 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
94 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
95 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
96
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000097 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
98 // operation.
99 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
100 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
101 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
Evan Cheng6892f282006-01-17 02:32:49 +0000102
Evan Cheng25ab6902006-09-08 06:48:29 +0000103 if (Subtarget->is64Bit()) {
104 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
Evan Cheng6892f282006-01-17 02:32:49 +0000105 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
Evan Cheng25ab6902006-09-08 06:48:29 +0000106 } else {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000107 if (X86ScalarSSEf64)
Evan Cheng25ab6902006-09-08 06:48:29 +0000108 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
109 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
110 else
111 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
112 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000113
114 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
115 // this operation.
116 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
117 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000118 // SSE has no i16 to fp conversion, only i32
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000119 if (X86ScalarSSEf32) {
Evan Cheng02568ff2006-01-30 22:13:22 +0000120 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000121 // f32 and f64 cases are Legal, f80 case is not
122 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
123 } else {
Evan Cheng5298bcc2006-02-17 07:01:52 +0000124 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
125 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
126 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000127
Dale Johannesen73328d12007-09-19 23:55:34 +0000128 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
129 // are Legal, f80 is custom lowered.
130 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
131 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
Evan Cheng6dab0532006-01-30 08:02:57 +0000132
Evan Cheng02568ff2006-01-30 22:13:22 +0000133 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
134 // this operation.
135 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
136 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
137
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000138 if (X86ScalarSSEf32) {
Evan Cheng02568ff2006-01-30 22:13:22 +0000139 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000140 // f32 and f64 cases are Legal, f80 case is not
141 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
Evan Cheng02568ff2006-01-30 22:13:22 +0000142 } else {
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000143 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
Evan Cheng02568ff2006-01-30 22:13:22 +0000144 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000145 }
146
147 // Handle FP_TO_UINT by promoting the destination to a larger signed
148 // conversion.
149 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
150 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
151 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
152
Evan Cheng25ab6902006-09-08 06:48:29 +0000153 if (Subtarget->is64Bit()) {
154 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000155 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
Evan Cheng25ab6902006-09-08 06:48:29 +0000156 } else {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000157 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
Evan Cheng25ab6902006-09-08 06:48:29 +0000158 // Expand FP_TO_UINT into a select.
159 // FIXME: We would like to use a Custom expander here eventually to do
160 // the optimal thing for SSE vs. the default expansion in the legalizer.
161 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
162 else
163 // With SSE3 we can use fisttpll to convert to a signed i64.
164 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
165 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000166
Chris Lattner399610a2006-12-05 18:22:22 +0000167 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000168 if (!X86ScalarSSEf64) {
Chris Lattnerf3597a12006-12-05 18:45:06 +0000169 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
170 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
171 }
Chris Lattner21f66852005-12-23 05:15:23 +0000172
Dan Gohmanb00ee212008-02-18 19:34:53 +0000173 // Scalar integer divide and remainder are lowered to use operations that
174 // produce two results, to match the available instructions. This exposes
175 // the two-result form to trivial CSE, which is able to combine x/y and x%y
176 // into a single instruction.
177 //
178 // Scalar integer multiply-high is also lowered to use two-result
179 // operations, to match the available instructions. However, plain multiply
180 // (low) operations are left as Legal, as there are single-result
181 // instructions for this in x86. Using the two-result multiply instructions
182 // when both high and low results are needed must be arranged by dagcombine.
Dan Gohman525178c2007-10-08 18:33:35 +0000183 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
184 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
185 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
186 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
187 setOperationAction(ISD::SREM , MVT::i8 , Expand);
188 setOperationAction(ISD::UREM , MVT::i8 , Expand);
Dan Gohman525178c2007-10-08 18:33:35 +0000189 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
190 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
191 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
192 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
193 setOperationAction(ISD::SREM , MVT::i16 , Expand);
194 setOperationAction(ISD::UREM , MVT::i16 , Expand);
Dan Gohman525178c2007-10-08 18:33:35 +0000195 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
196 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
197 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
198 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
199 setOperationAction(ISD::SREM , MVT::i32 , Expand);
200 setOperationAction(ISD::UREM , MVT::i32 , Expand);
Dan Gohman525178c2007-10-08 18:33:35 +0000201 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
202 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
203 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
204 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
205 setOperationAction(ISD::SREM , MVT::i64 , Expand);
206 setOperationAction(ISD::UREM , MVT::i64 , Expand);
Dan Gohmana37c9f72007-09-25 18:23:27 +0000207
Evan Chengc35497f2006-10-30 08:02:39 +0000208 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000209 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
Nate Begeman750ac1b2006-02-01 07:19:44 +0000210 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
211 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
Evan Cheng25ab6902006-09-08 06:48:29 +0000212 if (Subtarget->is64Bit())
Christopher Lambc59e5212007-08-10 21:48:46 +0000213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
217 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
Chris Lattnerd1108222008-03-07 06:36:32 +0000218 setOperationAction(ISD::FREM , MVT::f32 , Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000219 setOperationAction(ISD::FREM , MVT::f64 , Expand);
Chris Lattnerd1108222008-03-07 06:36:32 +0000220 setOperationAction(ISD::FREM , MVT::f80 , Expand);
Dan Gohman1a024862008-01-31 00:41:03 +0000221 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +0000222
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000223 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000224 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
225 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000226 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000227 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
228 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000229 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000230 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
231 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000232 if (Subtarget->is64Bit()) {
233 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000234 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
235 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000236 }
237
Andrew Lenharthb873ff32005-11-20 21:41:10 +0000238 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
Nate Begemand88fc032006-01-14 03:14:10 +0000239 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
Nate Begeman35ef9132006-01-11 21:21:00 +0000240
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000241 // These should be promoted to a larger select which is supported.
242 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
243 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000244 // X86 wants to expand cmov itself.
Evan Cheng5298bcc2006-02-17 07:01:52 +0000245 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
246 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
247 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
248 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000249 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000250 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
251 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
252 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
253 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
254 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000255 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
258 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
259 }
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000260 // X86 ret instruction may pop stack.
Evan Cheng5298bcc2006-02-17 07:01:52 +0000261 setOperationAction(ISD::RET , MVT::Other, Custom);
Anton Korobeynikov260a6b82008-09-08 21:12:11 +0000262 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
Anton Korobeynikov2365f512007-07-14 14:06:15 +0000263
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000264 // Darwin ABI issue.
Evan Cheng7ccced62006-02-18 00:15:05 +0000265 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
Nate Begeman37efe672006-04-22 18:53:45 +0000266 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000267 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +0000268 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
Anton Korobeynikov6625eff2008-05-04 21:36:32 +0000269 if (Subtarget->is64Bit())
270 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
Evan Cheng020d2e82006-02-23 20:41:18 +0000271 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000272 if (Subtarget->is64Bit()) {
273 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
274 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
275 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
276 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
277 }
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000278 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
Evan Cheng5298bcc2006-02-17 07:01:52 +0000279 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
280 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
281 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
Dan Gohman4c1fa612008-03-03 22:22:09 +0000282 if (Subtarget->is64Bit()) {
283 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
284 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
285 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
286 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000287
Evan Chengd2cde682008-03-10 19:38:10 +0000288 if (Subtarget->hasSSE1())
289 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
Evan Cheng27b7db52008-03-08 00:58:38 +0000290
Andrew Lenharthd497d9f2008-02-16 14:46:26 +0000291 if (!Subtarget->hasSSE2())
292 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
293
Mon P Wang63307c32008-05-05 19:05:59 +0000294 // Expand certain atomics
Dale Johannesene00a8a22008-08-28 02:44:49 +0000295 setOperationAction(ISD::ATOMIC_CMP_SWAP_8 , MVT::i8, Custom);
296 setOperationAction(ISD::ATOMIC_CMP_SWAP_16, MVT::i16, Custom);
297 setOperationAction(ISD::ATOMIC_CMP_SWAP_32, MVT::i32, Custom);
298 setOperationAction(ISD::ATOMIC_CMP_SWAP_64, MVT::i64, Custom);
Bill Wendling5bf1b4e2008-08-20 00:28:16 +0000299
Dale Johannesene00a8a22008-08-28 02:44:49 +0000300 setOperationAction(ISD::ATOMIC_LOAD_SUB_8, MVT::i8, Expand);
301 setOperationAction(ISD::ATOMIC_LOAD_SUB_16, MVT::i16, Expand);
302 setOperationAction(ISD::ATOMIC_LOAD_SUB_32, MVT::i32, Expand);
303 setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Expand);
Andrew Lenharthd497d9f2008-02-16 14:46:26 +0000304
Dan Gohman7f460202008-06-30 20:59:49 +0000305 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
306 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
Evan Cheng3c992d22006-03-07 02:02:57 +0000307 // FIXME - use subtarget debug flags
Anton Korobeynikovab4022f2006-10-31 08:31:24 +0000308 if (!Subtarget->isTargetDarwin() &&
309 !Subtarget->isTargetELF() &&
Dan Gohman44066042008-07-01 00:05:16 +0000310 !Subtarget->isTargetCygMing()) {
311 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
312 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
313 }
Chris Lattnerf73bae12005-11-29 06:16:21 +0000314
Anton Korobeynikovce3b4652007-05-02 19:53:33 +0000315 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
316 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
317 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
318 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
319 if (Subtarget->is64Bit()) {
Anton Korobeynikovce3b4652007-05-02 19:53:33 +0000320 setExceptionPointerRegister(X86::RAX);
321 setExceptionSelectorRegister(X86::RDX);
322 } else {
323 setExceptionPointerRegister(X86::EAX);
324 setExceptionSelectorRegister(X86::EDX);
325 }
Anton Korobeynikov38252622007-09-03 00:36:06 +0000326 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
Anton Korobeynikov260a6b82008-09-08 21:12:11 +0000327 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
328
Duncan Sandsf7331b32007-09-11 14:10:23 +0000329 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
Duncan Sandsb116fac2007-07-27 20:02:49 +0000330
Chris Lattnerda68d302008-01-15 21:58:22 +0000331 setOperationAction(ISD::TRAP, MVT::Other, Legal);
Anton Korobeynikov66fac792008-01-15 07:02:33 +0000332
Nate Begemanacc398c2006-01-25 18:21:52 +0000333 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
334 setOperationAction(ISD::VASTART , MVT::Other, Custom);
Nate Begemanacc398c2006-01-25 18:21:52 +0000335 setOperationAction(ISD::VAEND , MVT::Other, Expand);
Dan Gohman9018e832008-05-10 01:26:14 +0000336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::VAARG , MVT::Other, Custom);
Evan Chengae642192007-03-02 23:16:35 +0000338 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
Dan Gohman9018e832008-05-10 01:26:14 +0000339 } else {
340 setOperationAction(ISD::VAARG , MVT::Other, Expand);
Evan Chengae642192007-03-02 23:16:35 +0000341 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
Dan Gohman9018e832008-05-10 01:26:14 +0000342 }
Evan Chengae642192007-03-02 23:16:35 +0000343
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000344 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
Chris Lattnere1125522006-01-15 09:00:21 +0000345 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Evan Cheng25ab6902006-09-08 06:48:29 +0000346 if (Subtarget->is64Bit())
347 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +0000348 if (Subtarget->isTargetCygMing())
349 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
350 else
351 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
Chris Lattnerb99329e2006-01-13 02:42:53 +0000352
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000353 if (X86ScalarSSEf64) {
354 // f32 and f64 use SSE.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000355 // Set up the FP register classes.
Evan Cheng5ee4ccc2006-01-12 08:27:59 +0000356 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
357 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000358
Evan Cheng223547a2006-01-31 22:28:30 +0000359 // Use ANDPD to simulate FABS.
360 setOperationAction(ISD::FABS , MVT::f64, Custom);
361 setOperationAction(ISD::FABS , MVT::f32, Custom);
362
363 // Use XORP to simulate FNEG.
364 setOperationAction(ISD::FNEG , MVT::f64, Custom);
365 setOperationAction(ISD::FNEG , MVT::f32, Custom);
366
Evan Cheng68c47cb2007-01-05 07:55:56 +0000367 // Use ANDPD and ORPD to simulate FCOPYSIGN.
368 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
369 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
370
Evan Chengd25e9e82006-02-02 00:28:23 +0000371 // We don't support sin/cos/fmod
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000372 setOperationAction(ISD::FSIN , MVT::f64, Expand);
373 setOperationAction(ISD::FCOS , MVT::f64, Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000374 setOperationAction(ISD::FSIN , MVT::f32, Expand);
375 setOperationAction(ISD::FCOS , MVT::f32, Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000376
Chris Lattnera54aa942006-01-29 06:26:08 +0000377 // Expand FP immediates into loads from the stack, except for the special
378 // cases we handle.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000379 addLegalFPImmediate(APFloat(+0.0)); // xorpd
380 addLegalFPImmediate(APFloat(+0.0f)); // xorps
Dale Johannesen5411a392007-08-09 01:04:01 +0000381
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000382 // Floating truncations from f80 and extensions to f80 go through memory.
383 // If optimizing, we lie about this though and handle it in
384 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
385 if (Fast) {
386 setConvertAction(MVT::f32, MVT::f80, Expand);
387 setConvertAction(MVT::f64, MVT::f80, Expand);
388 setConvertAction(MVT::f80, MVT::f32, Expand);
389 setConvertAction(MVT::f80, MVT::f64, Expand);
390 }
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000391 } else if (X86ScalarSSEf32) {
392 // Use SSE for f32, x87 for f64.
393 // Set up the FP register classes.
394 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
395 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
396
397 // Use ANDPS to simulate FABS.
398 setOperationAction(ISD::FABS , MVT::f32, Custom);
399
400 // Use XORP to simulate FNEG.
401 setOperationAction(ISD::FNEG , MVT::f32, Custom);
402
403 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
404
405 // Use ANDPS and ORPS to simulate FCOPYSIGN.
406 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
407 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
408
409 // We don't support sin/cos/fmod
410 setOperationAction(ISD::FSIN , MVT::f32, Expand);
411 setOperationAction(ISD::FCOS , MVT::f32, Expand);
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000412
Nate Begemane1795842008-02-14 08:57:00 +0000413 // Special cases we handle for FP constants.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000414 addLegalFPImmediate(APFloat(+0.0f)); // xorps
415 addLegalFPImmediate(APFloat(+0.0)); // FLD0
416 addLegalFPImmediate(APFloat(+1.0)); // FLD1
417 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
418 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
419
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000420 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
421 // this though and handle it in InstructionSelectPreprocess so that
422 // dagcombine2 can hack on these.
423 if (Fast) {
424 setConvertAction(MVT::f32, MVT::f64, Expand);
425 setConvertAction(MVT::f32, MVT::f80, Expand);
426 setConvertAction(MVT::f80, MVT::f32, Expand);
427 setConvertAction(MVT::f64, MVT::f32, Expand);
428 // And x87->x87 truncations also.
429 setConvertAction(MVT::f80, MVT::f64, Expand);
430 }
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000431
432 if (!UnsafeFPMath) {
433 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
434 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
435 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000436 } else {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000437 // f32 and f64 in x87.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000438 // Set up the FP register classes.
Dale Johannesen849f2142007-07-03 00:53:03 +0000439 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
440 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000441
Evan Cheng68c47cb2007-01-05 07:55:56 +0000442 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
Dale Johannesen849f2142007-07-03 00:53:03 +0000443 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
Evan Cheng68c47cb2007-01-05 07:55:56 +0000444 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
445 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
Dale Johannesen5411a392007-08-09 01:04:01 +0000446
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000447 // Floating truncations go through memory. If optimizing, we lie about
448 // this though and handle it in InstructionSelectPreprocess so that
449 // dagcombine2 can hack on these.
450 if (Fast) {
451 setConvertAction(MVT::f80, MVT::f32, Expand);
452 setConvertAction(MVT::f64, MVT::f32, Expand);
453 setConvertAction(MVT::f80, MVT::f64, Expand);
454 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000455
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000456 if (!UnsafeFPMath) {
457 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
458 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
459 }
Dale Johannesenf04afdb2007-08-30 00:23:21 +0000460 addLegalFPImmediate(APFloat(+0.0)); // FLD0
461 addLegalFPImmediate(APFloat(+1.0)); // FLD1
462 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
463 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000464 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
465 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
466 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
467 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000468 }
Evan Cheng470a6ad2006-02-22 02:26:30 +0000469
Dale Johannesen59a58732007-08-05 18:49:15 +0000470 // Long double always uses X87.
471 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000472 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
473 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
Chris Lattner71d07a02008-01-27 06:19:31 +0000474 {
Chris Lattner71d07a02008-01-27 06:19:31 +0000475 APFloat TmpFlt(+0.0);
476 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
477 addLegalFPImmediate(TmpFlt); // FLD0
478 TmpFlt.changeSign();
479 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
480 APFloat TmpFlt2(+1.0);
481 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
482 addLegalFPImmediate(TmpFlt2); // FLD1
483 TmpFlt2.changeSign();
484 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
485 }
486
Dale Johannesen2f429012007-09-26 21:10:55 +0000487 if (!UnsafeFPMath) {
488 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
489 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
490 }
Dale Johannesen59a58732007-08-05 18:49:15 +0000491
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000492 // Always use a library call for pow.
493 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
494 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
495 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
496
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000497 setOperationAction(ISD::FLOG, MVT::f32, Expand);
498 setOperationAction(ISD::FLOG, MVT::f64, Expand);
499 setOperationAction(ISD::FLOG, MVT::f80, Expand);
500 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
501 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
502 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
503 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
504 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
505 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
506 setOperationAction(ISD::FEXP, MVT::f32, Expand);
507 setOperationAction(ISD::FEXP, MVT::f64, Expand);
508 setOperationAction(ISD::FEXP, MVT::f80, Expand);
509 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
510 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
511 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
512
Evan Chengd30bf012006-03-01 01:11:20 +0000513 // First set operation action for all vector types to expand. Then we
514 // will selectively turn on ones that can be effectively codegen'd.
Dan Gohmanfa0f77d2007-05-18 18:44:07 +0000515 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
516 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000517 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
518 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
519 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
520 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
521 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
522 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
523 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
524 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
525 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
526 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
527 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
528 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
529 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
Gabor Greif327ef032008-08-28 23:19:51 +0000530 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
532 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
Duncan Sands83ec4b62008-06-06 12:08:01 +0000533 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
Dale Johannesenfb0e1322008-09-10 17:31:40 +0000555 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
Evan Chengd30bf012006-03-01 01:11:20 +0000560 }
561
Evan Chenga88973f2006-03-22 19:22:18 +0000562 if (Subtarget->hasMMX()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000563 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
564 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
565 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
Dale Johannesena68f9012008-06-24 22:01:44 +0000566 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000567 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000568
Evan Chengd30bf012006-03-01 01:11:20 +0000569 // FIXME: add MMX packed arithmetics
Bill Wendlingbc9bffa2007-03-07 05:43:18 +0000570
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000571 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
572 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
573 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
Chris Lattner6c284d72007-04-12 04:14:49 +0000574 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000575
Bill Wendlingc1fb0472007-03-10 09:57:05 +0000576 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
577 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
578 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
Dale Johannesen8d26e592007-10-30 01:18:38 +0000579 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
Bill Wendlingc1fb0472007-03-10 09:57:05 +0000580
Bill Wendling74027e92007-03-15 21:24:36 +0000581 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
582 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
583
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000584 setOperationAction(ISD::AND, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000585 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000586 setOperationAction(ISD::AND, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000587 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
588 setOperationAction(ISD::AND, MVT::v2i32, Promote);
589 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
590 setOperationAction(ISD::AND, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000591
592 setOperationAction(ISD::OR, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000593 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000594 setOperationAction(ISD::OR, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000595 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
596 setOperationAction(ISD::OR, MVT::v2i32, Promote);
597 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
598 setOperationAction(ISD::OR, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000599
600 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000601 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000602 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000603 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
604 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
605 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
606 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000607
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000608 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000609 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000610 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000611 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
612 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
613 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
Dale Johannesena68f9012008-06-24 22:01:44 +0000614 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
615 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000616 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000617
Bill Wendlingccc44ad2007-03-27 20:22:40 +0000618 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
619 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
620 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
Dale Johannesena68f9012008-06-24 22:01:44 +0000621 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
Bill Wendlingccc44ad2007-03-27 20:22:40 +0000622 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
Bill Wendlinga348c562007-03-22 18:42:45 +0000623
624 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
625 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
Bill Wendlingccc44ad2007-03-27 20:22:40 +0000627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
Bill Wendling826f36f2007-03-28 00:57:11 +0000628
Evan Cheng52672b82008-07-22 18:39:19 +0000629 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
Bill Wendling826f36f2007-03-28 00:57:11 +0000630 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
631 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
Bill Wendling2f9bb1a2007-04-24 21:16:55 +0000632 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
Bill Wendling3180e202008-07-20 02:32:23 +0000633
634 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000635 }
636
Evan Chenga88973f2006-03-22 19:22:18 +0000637 if (Subtarget->hasSSE1()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000638 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
639
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000640 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
641 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
642 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
643 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
Dan Gohman20382522007-07-10 00:05:58 +0000644 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
645 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000646 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
647 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
648 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
Evan Cheng11e15b32006-04-03 20:53:28 +0000649 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000650 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
Nate Begeman30a0de92008-07-17 16:51:19 +0000651 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000652 }
653
Evan Chenga88973f2006-03-22 19:22:18 +0000654 if (Subtarget->hasSSE2()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000655 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
656 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
657 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
658 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
659 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
660
Evan Chengf7c378e2006-04-10 07:23:14 +0000661 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
662 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
663 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
Evan Cheng37e88562007-03-12 22:58:52 +0000664 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
Evan Chengf7c378e2006-04-10 07:23:14 +0000665 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
666 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
667 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
Evan Cheng37e88562007-03-12 22:58:52 +0000668 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
Evan Chengf9989842006-04-13 05:10:25 +0000669 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000670 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
671 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
672 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
673 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
Dan Gohman20382522007-07-10 00:05:58 +0000674 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
675 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000676
Nate Begeman30a0de92008-07-17 16:51:19 +0000677 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
678 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
679 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
680 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
Nate Begemanc2616e42008-05-12 20:34:32 +0000681
Evan Chengf7c378e2006-04-10 07:23:14 +0000682 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
683 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
Evan Chengb067a1e2006-03-31 19:22:53 +0000684 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
Evan Cheng5edb8d22006-04-17 22:04:06 +0000685 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
Evan Cheng5edb8d22006-04-17 22:04:06 +0000686 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000687
Evan Cheng2c3ae372006-04-12 21:21:57 +0000688 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000689 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
690 MVT VT = (MVT::SimpleValueType)i;
Nate Begeman844e0f92007-12-11 01:41:33 +0000691 // Do not attempt to custom lower non-power-of-2 vectors
Duncan Sands83ec4b62008-06-06 12:08:01 +0000692 if (!isPowerOf2_32(VT.getVectorNumElements()))
Nate Begeman844e0f92007-12-11 01:41:33 +0000693 continue;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000694 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
695 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
696 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000697 }
698 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
699 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
700 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
701 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
Nate Begemancdd1eec2008-02-12 22:51:28 +0000702 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000703 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
Nate Begemancdd1eec2008-02-12 22:51:28 +0000704 if (Subtarget->is64Bit()) {
705 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
Dale Johannesen25f1d082007-10-31 00:32:36 +0000706 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
Nate Begemancdd1eec2008-02-12 22:51:28 +0000707 }
Evan Cheng2c3ae372006-04-12 21:21:57 +0000708
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000709 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
Evan Cheng2c3ae372006-04-12 21:21:57 +0000710 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000711 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
712 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
713 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
714 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
715 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
716 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
717 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
718 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
719 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
720 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
Evan Chengf7c378e2006-04-10 07:23:14 +0000721 }
Evan Cheng2c3ae372006-04-12 21:21:57 +0000722
Chris Lattnerddf89562008-01-17 19:59:44 +0000723 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Chris Lattnerd43d00c2008-01-24 08:07:48 +0000724
Evan Cheng2c3ae372006-04-12 21:21:57 +0000725 // Custom lower v2i64 and v2f64 selects.
726 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
Evan Cheng91b740d2006-04-12 17:12:36 +0000727 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
Evan Chengf7c378e2006-04-10 07:23:14 +0000728 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000729 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
Nate Begemanc2616e42008-05-12 20:34:32 +0000730
Evan Cheng470a6ad2006-02-22 02:26:30 +0000731 }
Nate Begeman14d12ca2008-02-11 04:19:36 +0000732
733 if (Subtarget->hasSSE41()) {
734 // FIXME: Do we need to handle scalar-to-vector here?
735 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
Dan Gohman0b924dc2008-05-23 17:49:40 +0000736 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
Nate Begeman14d12ca2008-02-11 04:19:36 +0000737
738 // i8 and i16 vectors are custom , because the source register and source
739 // source memory operand types are not the same width. f32 vectors are
740 // custom since the immediate controlling the insert encodes additional
741 // information.
742 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
743 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
744 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
745 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
746
747 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
748 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
749 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
Evan Cheng62a3f152008-03-24 21:52:23 +0000750 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
Nate Begeman14d12ca2008-02-11 04:19:36 +0000751
752 if (Subtarget->is64Bit()) {
Nate Begemancdd1eec2008-02-12 22:51:28 +0000753 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
754 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
Nate Begeman14d12ca2008-02-11 04:19:36 +0000755 }
756 }
Evan Cheng470a6ad2006-02-22 02:26:30 +0000757
Nate Begeman30a0de92008-07-17 16:51:19 +0000758 if (Subtarget->hasSSE42()) {
759 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
760 }
761
Evan Cheng6be2c582006-04-05 23:38:46 +0000762 // We want to custom lower some of our intrinsics.
763 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
764
Evan Cheng206ee9d2006-07-07 08:33:52 +0000765 // We have target-specific dag combine patterns for the following nodes:
766 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
Evan Chengd880b972008-05-09 21:53:03 +0000767 setTargetDAGCombine(ISD::BUILD_VECTOR);
Chris Lattner83e6c992006-10-04 06:57:07 +0000768 setTargetDAGCombine(ISD::SELECT);
Chris Lattner149a4e52008-02-22 02:09:43 +0000769 setTargetDAGCombine(ISD::STORE);
Evan Cheng206ee9d2006-07-07 08:33:52 +0000770
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000771 computeRegisterProperties();
772
Evan Cheng87ed7162006-02-14 08:25:08 +0000773 // FIXME: These should be based on subtarget info. Plus, the values should
774 // be smaller when we are in optimizing for size mode.
Dan Gohman87060f52008-06-30 21:00:56 +0000775 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
776 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
777 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000778 allowUnalignedMemoryAccesses = true; // x86 supports it!
Evan Chengfb8075d2008-02-28 00:43:03 +0000779 setPrefLoopAlignment(16);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000780}
781
Scott Michel5b8f82e2008-03-10 15:42:14 +0000782
Dan Gohman475871a2008-07-27 21:46:04 +0000783MVT X86TargetLowering::getSetCCResultType(const SDValue &) const {
Scott Michel5b8f82e2008-03-10 15:42:14 +0000784 return MVT::i8;
785}
786
787
Evan Cheng29286502008-01-23 23:17:41 +0000788/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
789/// the desired ByVal argument alignment.
790static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
791 if (MaxAlign == 16)
792 return;
793 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
794 if (VTy->getBitWidth() == 128)
795 MaxAlign = 16;
Evan Cheng29286502008-01-23 23:17:41 +0000796 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
797 unsigned EltAlign = 0;
798 getMaxByValAlign(ATy->getElementType(), EltAlign);
799 if (EltAlign > MaxAlign)
800 MaxAlign = EltAlign;
801 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
802 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
803 unsigned EltAlign = 0;
804 getMaxByValAlign(STy->getElementType(i), EltAlign);
805 if (EltAlign > MaxAlign)
806 MaxAlign = EltAlign;
807 if (MaxAlign == 16)
808 break;
809 }
810 }
811 return;
812}
813
814/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
815/// function arguments in the caller parameter area. For X86, aggregates
Dale Johannesen0c191872008-02-08 19:48:20 +0000816/// that contain SSE vectors are placed at 16-byte boundaries while the rest
817/// are at 4-byte boundaries.
Evan Cheng29286502008-01-23 23:17:41 +0000818unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
Evan Cheng1887c1c2008-08-21 21:00:15 +0000819 if (Subtarget->is64Bit()) {
820 // Max of 8 and alignment of type.
Anton Korobeynikovbff66b02008-09-09 18:22:57 +0000821 unsigned TyAlign = TD->getABITypeAlignment(Ty);
Evan Cheng1887c1c2008-08-21 21:00:15 +0000822 if (TyAlign > 8)
823 return TyAlign;
824 return 8;
825 }
826
Evan Cheng29286502008-01-23 23:17:41 +0000827 unsigned Align = 4;
Dale Johannesen0c191872008-02-08 19:48:20 +0000828 if (Subtarget->hasSSE1())
829 getMaxByValAlign(Ty, Align);
Evan Cheng29286502008-01-23 23:17:41 +0000830 return Align;
831}
Chris Lattner2b02a442007-02-25 08:29:00 +0000832
Evan Chengf0df0312008-05-15 08:39:06 +0000833/// getOptimalMemOpType - Returns the target specific optimal type for load
Evan Cheng0ef8de32008-05-15 22:13:02 +0000834/// and store operations as a result of memset, memcpy, and memmove
835/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
Evan Chengf0df0312008-05-15 08:39:06 +0000836/// determining it.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000837MVT
Evan Chengf0df0312008-05-15 08:39:06 +0000838X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
839 bool isSrcConst, bool isSrcStr) const {
840 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
841 return MVT::v4i32;
842 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
843 return MVT::v4f32;
844 if (Subtarget->is64Bit() && Size >= 8)
845 return MVT::i64;
846 return MVT::i32;
847}
848
849
Evan Chengcc415862007-11-09 01:32:10 +0000850/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
851/// jumptable.
Dan Gohman475871a2008-07-27 21:46:04 +0000852SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
Evan Chengcc415862007-11-09 01:32:10 +0000853 SelectionDAG &DAG) const {
854 if (usesGlobalOffsetTable())
855 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
856 if (!Subtarget->isPICStyleRIPRel())
857 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
858 return Table;
859}
860
Chris Lattner2b02a442007-02-25 08:29:00 +0000861//===----------------------------------------------------------------------===//
862// Return Value Calling Convention Implementation
863//===----------------------------------------------------------------------===//
864
Chris Lattner59ed56b2007-02-28 04:55:35 +0000865#include "X86GenCallingConv.inc"
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000866
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000867/// LowerRET - Lower an ISD::RET node.
Dan Gohman475871a2008-07-27 21:46:04 +0000868SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000869 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
870
Chris Lattner9774c912007-02-27 05:28:59 +0000871 SmallVector<CCValAssign, 16> RVLocs;
872 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
Chris Lattner52387be2007-06-19 00:13:10 +0000873 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
874 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
Gabor Greifba36cb52008-08-28 21:40:38 +0000875 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000876
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000877 // If this is the first return lowered for this function, add the regs to the
878 // liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +0000879 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Chris Lattner9774c912007-02-27 05:28:59 +0000880 for (unsigned i = 0; i != RVLocs.size(); ++i)
881 if (RVLocs[i].isRegLoc())
Chris Lattner84bc5422007-12-31 04:13:23 +0000882 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000883 }
Dan Gohman475871a2008-07-27 21:46:04 +0000884 SDValue Chain = Op.getOperand(0);
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000885
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000886 // Handle tail call return.
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000887 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000888 if (Chain.getOpcode() == X86ISD::TAILCALL) {
Dan Gohman475871a2008-07-27 21:46:04 +0000889 SDValue TailCall = Chain;
890 SDValue TargetAddress = TailCall.getOperand(1);
891 SDValue StackAdjustment = TailCall.getOperand(2);
Chris Lattnerb4a6eaa2008-01-16 05:52:18 +0000892 assert(((TargetAddress.getOpcode() == ISD::Register &&
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000893 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
894 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
895 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
896 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
897 "Expecting an global address, external symbol, or register");
Chris Lattnerb4a6eaa2008-01-16 05:52:18 +0000898 assert(StackAdjustment.getOpcode() == ISD::Constant &&
899 "Expecting a const value");
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000900
Dan Gohman475871a2008-07-27 21:46:04 +0000901 SmallVector<SDValue,8> Operands;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000902 Operands.push_back(Chain.getOperand(0));
903 Operands.push_back(TargetAddress);
904 Operands.push_back(StackAdjustment);
905 // Copy registers used by the call. Last operand is a flag so it is not
906 // copied.
Arnold Schwaighofer448175f2007-10-16 09:05:00 +0000907 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000908 Operands.push_back(Chain.getOperand(i));
909 }
Arnold Schwaighofer448175f2007-10-16 09:05:00 +0000910 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
911 Operands.size());
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000912 }
913
914 // Regular return.
Dan Gohman475871a2008-07-27 21:46:04 +0000915 SDValue Flag;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000916
Dan Gohman475871a2008-07-27 21:46:04 +0000917 SmallVector<SDValue, 6> RetOps;
Chris Lattner447ff682008-03-11 03:23:40 +0000918 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
919 // Operand #1 = Bytes To Pop
920 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
921
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000922 // Copy the result values into the output registers.
Chris Lattner8e6da152008-03-10 21:08:41 +0000923 for (unsigned i = 0; i != RVLocs.size(); ++i) {
924 CCValAssign &VA = RVLocs[i];
925 assert(VA.isRegLoc() && "Can only return in registers!");
Dan Gohman475871a2008-07-27 21:46:04 +0000926 SDValue ValToCopy = Op.getOperand(i*2+1);
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000927
Chris Lattner447ff682008-03-11 03:23:40 +0000928 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
929 // the RET instruction and handled by the FP Stackifier.
930 if (RVLocs[i].getLocReg() == X86::ST0 ||
931 RVLocs[i].getLocReg() == X86::ST1) {
932 // If this is a copy from an xmm register to ST(0), use an FPExtend to
933 // change the value to the FP stack register class.
934 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
935 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
936 RetOps.push_back(ValToCopy);
937 // Don't emit a copytoreg.
938 continue;
939 }
Dale Johannesena68f9012008-06-24 22:01:44 +0000940
Chris Lattner8e6da152008-03-10 21:08:41 +0000941 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000942 Flag = Chain.getValue(1);
943 }
Dan Gohman61a92132008-04-21 23:59:07 +0000944
945 // The x86-64 ABI for returning structs by value requires that we copy
946 // the sret argument into %rax for the return. We saved the argument into
947 // a virtual register in the entry block, so now we copy the value out
948 // and into %rax.
949 if (Subtarget->is64Bit() &&
950 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
951 MachineFunction &MF = DAG.getMachineFunction();
952 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
953 unsigned Reg = FuncInfo->getSRetReturnReg();
954 if (!Reg) {
955 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
956 FuncInfo->setSRetReturnReg(Reg);
957 }
Dan Gohman475871a2008-07-27 21:46:04 +0000958 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
Dan Gohman61a92132008-04-21 23:59:07 +0000959
960 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
961 Flag = Chain.getValue(1);
962 }
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000963
Chris Lattner447ff682008-03-11 03:23:40 +0000964 RetOps[0] = Chain; // Update chain.
965
966 // Add the flag if we have it.
Gabor Greifba36cb52008-08-28 21:40:38 +0000967 if (Flag.getNode())
Chris Lattner447ff682008-03-11 03:23:40 +0000968 RetOps.push_back(Flag);
969
970 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000971}
972
973
Chris Lattner3085e152007-02-25 08:59:22 +0000974/// LowerCallResult - Lower the result values of an ISD::CALL into the
975/// appropriate copies out of appropriate physical registers. This assumes that
976/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
977/// being lowered. The returns a SDNode with the same number of values as the
978/// ISD::CALL.
979SDNode *X86TargetLowering::
Dan Gohman475871a2008-07-27 21:46:04 +0000980LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
Chris Lattner3085e152007-02-25 08:59:22 +0000981 unsigned CallingConv, SelectionDAG &DAG) {
Chris Lattnere32bbf62007-02-28 07:09:55 +0000982
983 // Assign locations to each value returned by this call.
Chris Lattner9774c912007-02-27 05:28:59 +0000984 SmallVector<CCValAssign, 16> RVLocs;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000985 bool isVarArg =
986 cast<ConstantSDNode>(TheCall->getOperand(2))->getZExtValue() != 0;
Chris Lattner52387be2007-06-19 00:13:10 +0000987 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
Chris Lattnere32bbf62007-02-28 07:09:55 +0000988 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
989
Dan Gohman475871a2008-07-27 21:46:04 +0000990 SmallVector<SDValue, 8> ResultVals;
Chris Lattner3085e152007-02-25 08:59:22 +0000991
992 // Copy all of the result registers out of their specified physreg.
Chris Lattner8e6da152008-03-10 21:08:41 +0000993 for (unsigned i = 0; i != RVLocs.size(); ++i) {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000994 MVT CopyVT = RVLocs[i].getValVT();
Chris Lattner8e6da152008-03-10 21:08:41 +0000995
996 // If this is a call to a function that returns an fp value on the floating
997 // point stack, but where we prefer to use the value in xmm registers, copy
998 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
Mon P Wang7e665102008-08-21 19:54:16 +0000999 if ((RVLocs[i].getLocReg() == X86::ST0 ||
1000 RVLocs[i].getLocReg() == X86::ST1) &&
Chris Lattner8e6da152008-03-10 21:08:41 +00001001 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
1002 CopyVT = MVT::f80;
Chris Lattner3085e152007-02-25 08:59:22 +00001003 }
Chris Lattner3085e152007-02-25 08:59:22 +00001004
Chris Lattner8e6da152008-03-10 21:08:41 +00001005 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
1006 CopyVT, InFlag).getValue(1);
Dan Gohman475871a2008-07-27 21:46:04 +00001007 SDValue Val = Chain.getValue(0);
Chris Lattner8e6da152008-03-10 21:08:41 +00001008 InFlag = Chain.getValue(2);
Chris Lattner112dedc2007-12-29 06:41:28 +00001009
Chris Lattner8e6da152008-03-10 21:08:41 +00001010 if (CopyVT != RVLocs[i].getValVT()) {
1011 // Round the F80 the right size, which also moves to the appropriate xmm
1012 // register.
1013 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
1014 // This truncation won't change the value.
1015 DAG.getIntPtrConstant(1));
1016 }
Chris Lattnerd43d00c2008-01-24 08:07:48 +00001017
Chris Lattner8e6da152008-03-10 21:08:41 +00001018 ResultVals.push_back(Val);
Chris Lattner3085e152007-02-25 08:59:22 +00001019 }
Duncan Sands4bdcb612008-07-02 17:40:58 +00001020
Chris Lattner3085e152007-02-25 08:59:22 +00001021 // Merge everything together with a MERGE_VALUES node.
1022 ResultVals.push_back(Chain);
Duncan Sandsf9516202008-06-30 10:19:09 +00001023 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
Gabor Greifba36cb52008-08-28 21:40:38 +00001024 ResultVals.size()).getNode();
Chris Lattner2b02a442007-02-25 08:29:00 +00001025}
1026
1027
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001028//===----------------------------------------------------------------------===//
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001029// C & StdCall & Fast Calling Convention implementation
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001030//===----------------------------------------------------------------------===//
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001031// StdCall calling convention seems to be standard for many Windows' API
1032// routines and around. It differs from C calling convention just a little:
1033// callee should clean up the stack, not caller. Symbols should be also
1034// decorated in some fancy way :) It doesn't support any vector arguments.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001035// For info on fast calling convention see Fast Calling Convention (tail call)
1036// implementation LowerX86_32FastCCCallTo.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001037
Evan Cheng85e38002006-04-27 05:35:28 +00001038/// AddLiveIn - This helper function adds the specified physical register to the
1039/// MachineFunction as a live in value. It also creates a corresponding virtual
1040/// register for it.
1041static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001042 const TargetRegisterClass *RC) {
Evan Cheng85e38002006-04-27 05:35:28 +00001043 assert(RC->contains(PReg) && "Not the correct regclass!");
Chris Lattner84bc5422007-12-31 04:13:23 +00001044 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1045 MF.getRegInfo().addLiveIn(PReg, VReg);
Evan Cheng85e38002006-04-27 05:35:28 +00001046 return VReg;
1047}
1048
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001049/// CallIsStructReturn - Determines whether a CALL node uses struct return
1050/// semantics.
Dan Gohman475871a2008-07-27 21:46:04 +00001051static bool CallIsStructReturn(SDValue Op) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001052 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1053 if (!NumOps)
1054 return false;
Duncan Sands276dcbd2008-03-21 09:14:45 +00001055
1056 return cast<ARG_FLAGSSDNode>(Op.getOperand(6))->getArgFlags().isSRet();
Gordon Henriksen86737662008-01-05 16:56:59 +00001057}
1058
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001059/// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1060/// return semantics.
Dan Gohman475871a2008-07-27 21:46:04 +00001061static bool ArgsAreStructReturn(SDValue Op) {
Gabor Greifba36cb52008-08-28 21:40:38 +00001062 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
Gordon Henriksen86737662008-01-05 16:56:59 +00001063 if (!NumArgs)
1064 return false;
Duncan Sands276dcbd2008-03-21 09:14:45 +00001065
1066 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
Gordon Henriksen86737662008-01-05 16:56:59 +00001067}
1068
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001069/// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1070/// the callee to pop its own arguments. Callee pop is necessary to support tail
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001071/// calls.
Dan Gohman475871a2008-07-27 21:46:04 +00001072bool X86TargetLowering::IsCalleePop(SDValue Op) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001073 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
Gordon Henriksen86737662008-01-05 16:56:59 +00001074 if (IsVarArg)
1075 return false;
1076
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001077 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001078 default:
1079 return false;
1080 case CallingConv::X86_StdCall:
1081 return !Subtarget->is64Bit();
1082 case CallingConv::X86_FastCall:
1083 return !Subtarget->is64Bit();
1084 case CallingConv::Fast:
1085 return PerformTailCallOpt;
1086 }
1087}
1088
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001089/// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or
1090/// FORMAL_ARGUMENTS node.
Dan Gohman475871a2008-07-27 21:46:04 +00001091CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDValue Op) const {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001092 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
Gordon Henriksen86737662008-01-05 16:56:59 +00001093
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00001094 if (Subtarget->is64Bit()) {
Anton Korobeynikov1a979d92008-03-22 20:57:27 +00001095 if (Subtarget->isTargetWin64())
Anton Korobeynikov8f88cb02008-03-22 20:37:30 +00001096 return CC_X86_Win64_C;
Evan Chenge9ac9e62008-09-07 09:07:23 +00001097 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1098 return CC_X86_64_TailCall;
1099 else
1100 return CC_X86_64_C;
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00001101 }
1102
Gordon Henriksen86737662008-01-05 16:56:59 +00001103 if (CC == CallingConv::X86_FastCall)
1104 return CC_X86_32_FastCall;
1105 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1106 return CC_X86_32_TailCall;
Evan Chengb188dd92008-09-10 18:25:29 +00001107 else if (CC == CallingConv::Fast)
1108 return CC_X86_32_FastCC;
Gordon Henriksen86737662008-01-05 16:56:59 +00001109 else
1110 return CC_X86_32_C;
1111}
1112
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001113/// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1114/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
Gordon Henriksen86737662008-01-05 16:56:59 +00001115NameDecorationStyle
Dan Gohman475871a2008-07-27 21:46:04 +00001116X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001117 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
Gordon Henriksen86737662008-01-05 16:56:59 +00001118 if (CC == CallingConv::X86_FastCall)
1119 return FastCall;
1120 else if (CC == CallingConv::X86_StdCall)
1121 return StdCall;
1122 return None;
1123}
1124
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001125
Arnold Schwaighofer258bb1b2008-02-26 22:21:54 +00001126/// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1127/// in a register before calling.
1128bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1129 return !IsTailCall && !Is64Bit &&
1130 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1131 Subtarget->isPICStyleGOT();
1132}
1133
Arnold Schwaighofer258bb1b2008-02-26 22:21:54 +00001134/// CallRequiresFnAddressInReg - Check whether the call requires the function
1135/// address to be loaded in a register.
1136bool
1137X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1138 return !Is64Bit && IsTailCall &&
1139 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1140 Subtarget->isPICStyleGOT();
1141}
1142
Arnold Schwaighofer16a3e522008-02-26 17:50:59 +00001143/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1144/// by "Src" to address "Dst" with size and alignment information specified by
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001145/// the specific parameter attribute. The copy will be passed as a byval
1146/// function parameter.
Dan Gohman475871a2008-07-27 21:46:04 +00001147static SDValue
1148CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
Duncan Sands276dcbd2008-03-21 09:14:45 +00001149 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
Dan Gohman475871a2008-07-27 21:46:04 +00001150 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
Dan Gohman707e0182008-04-12 04:36:06 +00001151 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001152 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001153}
1154
Dan Gohman475871a2008-07-27 21:46:04 +00001155SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
Rafael Espindola7effac52007-09-14 15:48:13 +00001156 const CCValAssign &VA,
1157 MachineFrameInfo *MFI,
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001158 unsigned CC,
Dan Gohman475871a2008-07-27 21:46:04 +00001159 SDValue Root, unsigned i) {
Rafael Espindola7effac52007-09-14 15:48:13 +00001160 // Create the nodes corresponding to a load from this parameter slot.
Duncan Sands276dcbd2008-03-21 09:14:45 +00001161 ISD::ArgFlagsTy Flags =
1162 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001163 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
Duncan Sands276dcbd2008-03-21 09:14:45 +00001164 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
Evan Chenge70bb592008-01-10 02:24:25 +00001165
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001166 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1167 // changed with more analysis.
1168 // In case of tail call optimization mark all arguments mutable. Since they
1169 // could be overwritten by lowering of arguments in case of a tail call.
Duncan Sands83ec4b62008-06-06 12:08:01 +00001170 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001171 VA.getLocMemOffset(), isImmutable);
Dan Gohman475871a2008-07-27 21:46:04 +00001172 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
Duncan Sands276dcbd2008-03-21 09:14:45 +00001173 if (Flags.isByVal())
Rafael Espindola7effac52007-09-14 15:48:13 +00001174 return FIN;
Dan Gohman69de1932008-02-06 22:27:42 +00001175 return DAG.getLoad(VA.getValVT(), Root, FIN,
Dan Gohmana54cf172008-07-11 22:44:52 +00001176 PseudoSourceValue::getFixedStack(FI), 0);
Rafael Espindola7effac52007-09-14 15:48:13 +00001177}
1178
Dan Gohman475871a2008-07-27 21:46:04 +00001179SDValue
1180X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
Evan Cheng1bc78042006-04-26 01:20:17 +00001181 MachineFunction &MF = DAG.getMachineFunction();
Gordon Henriksen86737662008-01-05 16:56:59 +00001182 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1183
1184 const Function* Fn = MF.getFunction();
1185 if (Fn->hasExternalLinkage() &&
1186 Subtarget->isTargetCygMing() &&
1187 Fn->getName() == "main")
1188 FuncInfo->setForceFramePointer(true);
1189
1190 // Decorate the function name.
1191 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1192
Evan Cheng1bc78042006-04-26 01:20:17 +00001193 MachineFrameInfo *MFI = MF.getFrameInfo();
Dan Gohman475871a2008-07-27 21:46:04 +00001194 SDValue Root = Op.getOperand(0);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001195 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001196 unsigned CC = MF.getFunction()->getCallingConv();
Gordon Henriksen86737662008-01-05 16:56:59 +00001197 bool Is64Bit = Subtarget->is64Bit();
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001198 bool IsWin64 = Subtarget->isTargetWin64();
Gordon Henriksenae636f82008-01-03 16:47:34 +00001199
1200 assert(!(isVarArg && CC == CallingConv::Fast) &&
1201 "Var args not supported with calling convention fastcc");
1202
Chris Lattner638402b2007-02-28 07:00:42 +00001203 // Assign locations to all of the incoming arguments.
Chris Lattnerf39f7712007-02-28 05:46:49 +00001204 SmallVector<CCValAssign, 16> ArgLocs;
Gordon Henriksenae636f82008-01-03 16:47:34 +00001205 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
Gabor Greifba36cb52008-08-28 21:40:38 +00001206 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(Op));
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001207
Dan Gohman475871a2008-07-27 21:46:04 +00001208 SmallVector<SDValue, 8> ArgValues;
Chris Lattnerf39f7712007-02-28 05:46:49 +00001209 unsigned LastVal = ~0U;
1210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1211 CCValAssign &VA = ArgLocs[i];
1212 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1213 // places.
1214 assert(VA.getValNo() != LastVal &&
1215 "Don't support value assigned to multiple locs yet");
1216 LastVal = VA.getValNo();
1217
1218 if (VA.isRegLoc()) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00001219 MVT RegVT = VA.getLocVT();
Chris Lattnerf39f7712007-02-28 05:46:49 +00001220 TargetRegisterClass *RC;
1221 if (RegVT == MVT::i32)
1222 RC = X86::GR32RegisterClass;
Gordon Henriksen86737662008-01-05 16:56:59 +00001223 else if (Is64Bit && RegVT == MVT::i64)
1224 RC = X86::GR64RegisterClass;
Dale Johannesene672af12008-02-05 20:46:33 +00001225 else if (RegVT == MVT::f32)
Gordon Henriksen86737662008-01-05 16:56:59 +00001226 RC = X86::FR32RegisterClass;
Dale Johannesene672af12008-02-05 20:46:33 +00001227 else if (RegVT == MVT::f64)
Gordon Henriksen86737662008-01-05 16:56:59 +00001228 RC = X86::FR64RegisterClass;
Duncan Sands83ec4b62008-06-06 12:08:01 +00001229 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
Evan Chengee472b12008-04-25 07:56:45 +00001230 RC = X86::VR128RegisterClass;
Duncan Sands83ec4b62008-06-06 12:08:01 +00001231 else if (RegVT.isVector()) {
1232 assert(RegVT.getSizeInBits() == 64);
Evan Chengee472b12008-04-25 07:56:45 +00001233 if (!Is64Bit)
1234 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1235 else {
1236 // Darwin calling convention passes MMX values in either GPRs or
1237 // XMMs in x86-64. Other targets pass them in memory.
1238 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1239 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1240 RegVT = MVT::v2i64;
1241 } else {
1242 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1243 RegVT = MVT::i64;
1244 }
1245 }
1246 } else {
1247 assert(0 && "Unknown argument type!");
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001248 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001249
Chris Lattner82932a52007-03-02 05:12:29 +00001250 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
Dan Gohman475871a2008-07-27 21:46:04 +00001251 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
Chris Lattnerf39f7712007-02-28 05:46:49 +00001252
1253 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1254 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1255 // right size.
1256 if (VA.getLocInfo() == CCValAssign::SExt)
1257 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1258 DAG.getValueType(VA.getValVT()));
1259 else if (VA.getLocInfo() == CCValAssign::ZExt)
1260 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1261 DAG.getValueType(VA.getValVT()));
1262
1263 if (VA.getLocInfo() != CCValAssign::Full)
1264 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1265
Gordon Henriksen86737662008-01-05 16:56:59 +00001266 // Handle MMX values passed in GPRs.
Evan Cheng44c0fd12008-04-25 20:13:28 +00001267 if (Is64Bit && RegVT != VA.getLocVT()) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00001268 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
Evan Cheng44c0fd12008-04-25 20:13:28 +00001269 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1270 else if (RC == X86::VR128RegisterClass) {
1271 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1272 DAG.getConstant(0, MVT::i64));
1273 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1274 }
1275 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001276
Chris Lattnerf39f7712007-02-28 05:46:49 +00001277 ArgValues.push_back(ArgValue);
1278 } else {
1279 assert(VA.isMemLoc());
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001280 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
Evan Cheng1bc78042006-04-26 01:20:17 +00001281 }
Evan Cheng1bc78042006-04-26 01:20:17 +00001282 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001283
Dan Gohman61a92132008-04-21 23:59:07 +00001284 // The x86-64 ABI for returning structs by value requires that we copy
1285 // the sret argument into %rax for the return. Save the argument into
1286 // a virtual register so that we can access it from the return points.
1287 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1288 MachineFunction &MF = DAG.getMachineFunction();
1289 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1290 unsigned Reg = FuncInfo->getSRetReturnReg();
1291 if (!Reg) {
1292 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1293 FuncInfo->setSRetReturnReg(Reg);
1294 }
Dan Gohman475871a2008-07-27 21:46:04 +00001295 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
Dan Gohman61a92132008-04-21 23:59:07 +00001296 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1297 }
1298
Chris Lattnerf39f7712007-02-28 05:46:49 +00001299 unsigned StackSize = CCInfo.getNextStackOffset();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001300 // align stack specially for tail calls
Evan Chenge9ac9e62008-09-07 09:07:23 +00001301 if (PerformTailCallOpt && CC == CallingConv::Fast)
Gordon Henriksenae636f82008-01-03 16:47:34 +00001302 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
Evan Cheng25caf632006-05-23 21:06:34 +00001303
Evan Cheng1bc78042006-04-26 01:20:17 +00001304 // If the function takes variable number of arguments, make a frame index for
1305 // the start of the first vararg value... for expansion of llvm.va_start.
Gordon Henriksenae636f82008-01-03 16:47:34 +00001306 if (isVarArg) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001307 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1308 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1309 }
1310 if (Is64Bit) {
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001311 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1312
1313 // FIXME: We should really autogenerate these arrays
1314 static const unsigned GPR64ArgRegsWin64[] = {
1315 X86::RCX, X86::RDX, X86::R8, X86::R9
Gordon Henriksen86737662008-01-05 16:56:59 +00001316 };
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001317 static const unsigned XMMArgRegsWin64[] = {
1318 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1319 };
1320 static const unsigned GPR64ArgRegs64Bit[] = {
1321 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1322 };
1323 static const unsigned XMMArgRegs64Bit[] = {
Gordon Henriksen86737662008-01-05 16:56:59 +00001324 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1325 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1326 };
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001327 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1328
1329 if (IsWin64) {
1330 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1331 GPR64ArgRegs = GPR64ArgRegsWin64;
1332 XMMArgRegs = XMMArgRegsWin64;
1333 } else {
1334 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1335 GPR64ArgRegs = GPR64ArgRegs64Bit;
1336 XMMArgRegs = XMMArgRegs64Bit;
1337 }
1338 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1339 TotalNumIntRegs);
1340 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1341 TotalNumXMMRegs);
1342
Gordon Henriksen86737662008-01-05 16:56:59 +00001343 // For X86-64, if there are vararg parameters that are passed via
1344 // registers, then we must store them to their spots on the stack so they
1345 // may be loaded by deferencing the result of va_next.
1346 VarArgsGPOffset = NumIntRegs * 8;
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001347 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1348 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1349 TotalNumXMMRegs * 16, 16);
1350
Gordon Henriksen86737662008-01-05 16:56:59 +00001351 // Store the integer parameter registers.
Dan Gohman475871a2008-07-27 21:46:04 +00001352 SmallVector<SDValue, 8> MemOps;
1353 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1354 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001355 DAG.getIntPtrConstant(VarArgsGPOffset));
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001356 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001357 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1358 X86::GR64RegisterClass);
Dan Gohman475871a2008-07-27 21:46:04 +00001359 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1360 SDValue Store =
Dan Gohman69de1932008-02-06 22:27:42 +00001361 DAG.getStore(Val.getValue(1), Val, FIN,
Dan Gohmana54cf172008-07-11 22:44:52 +00001362 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
Gordon Henriksen86737662008-01-05 16:56:59 +00001363 MemOps.push_back(Store);
1364 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001365 DAG.getIntPtrConstant(8));
Gordon Henriksen86737662008-01-05 16:56:59 +00001366 }
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001367
Gordon Henriksen86737662008-01-05 16:56:59 +00001368 // Now store the XMM (fp + vector) parameter registers.
1369 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001370 DAG.getIntPtrConstant(VarArgsFPOffset));
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001371 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001372 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1373 X86::VR128RegisterClass);
Dan Gohman475871a2008-07-27 21:46:04 +00001374 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1375 SDValue Store =
Dan Gohman69de1932008-02-06 22:27:42 +00001376 DAG.getStore(Val.getValue(1), Val, FIN,
Dan Gohmana54cf172008-07-11 22:44:52 +00001377 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
Gordon Henriksen86737662008-01-05 16:56:59 +00001378 MemOps.push_back(Store);
1379 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
Chris Lattner0bd48932008-01-17 07:00:52 +00001380 DAG.getIntPtrConstant(16));
Gordon Henriksen86737662008-01-05 16:56:59 +00001381 }
1382 if (!MemOps.empty())
1383 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1384 &MemOps[0], MemOps.size());
1385 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001386 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001387
Gordon Henriksenae636f82008-01-03 16:47:34 +00001388 ArgValues.push_back(Root);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001389
Gordon Henriksen86737662008-01-05 16:56:59 +00001390 // Some CCs need callee pop.
1391 if (IsCalleePop(Op)) {
1392 BytesToPopOnReturn = StackSize; // Callee pops everything.
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001393 BytesCallerReserves = 0;
1394 } else {
Anton Korobeynikov1d9bacc2007-03-06 08:12:33 +00001395 BytesToPopOnReturn = 0; // Callee pops nothing.
Chris Lattnerf39f7712007-02-28 05:46:49 +00001396 // If this is an sret function, the return should pop the hidden pointer.
Evan Chengb188dd92008-09-10 18:25:29 +00001397 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
Chris Lattnerf39f7712007-02-28 05:46:49 +00001398 BytesToPopOnReturn = 4;
Chris Lattnerf39f7712007-02-28 05:46:49 +00001399 BytesCallerReserves = StackSize;
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001400 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001401
Gordon Henriksen86737662008-01-05 16:56:59 +00001402 if (!Is64Bit) {
1403 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1404 if (CC == CallingConv::X86_FastCall)
1405 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1406 }
Evan Cheng25caf632006-05-23 21:06:34 +00001407
Anton Korobeynikova2780e12007-08-15 17:12:32 +00001408 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
Evan Cheng1bc78042006-04-26 01:20:17 +00001409
Evan Cheng25caf632006-05-23 21:06:34 +00001410 // Return the new list of results.
Gabor Greifba36cb52008-08-28 21:40:38 +00001411 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
Gabor Greif99a6cb92008-08-26 22:36:50 +00001412 ArgValues.size()).getValue(Op.getResNo());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001413}
1414
Dan Gohman475871a2008-07-27 21:46:04 +00001415SDValue
1416X86TargetLowering::LowerMemOpCallTo(SDValue Op, SelectionDAG &DAG,
1417 const SDValue &StackPtr,
Evan Chengdffbd832008-01-10 00:09:10 +00001418 const CCValAssign &VA,
Dan Gohman475871a2008-07-27 21:46:04 +00001419 SDValue Chain,
1420 SDValue Arg) {
Dan Gohman4fdad172008-02-07 16:28:05 +00001421 unsigned LocMemOffset = VA.getLocMemOffset();
Dan Gohman475871a2008-07-27 21:46:04 +00001422 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
Evan Chengdffbd832008-01-10 00:09:10 +00001423 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
Duncan Sands276dcbd2008-03-21 09:14:45 +00001424 ISD::ArgFlagsTy Flags =
1425 cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags();
1426 if (Flags.isByVal()) {
Evan Cheng8e5712b2008-01-12 01:08:07 +00001427 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
Evan Chengdffbd832008-01-10 00:09:10 +00001428 }
Dan Gohman4fdad172008-02-07 16:28:05 +00001429 return DAG.getStore(Chain, Arg, PtrOff,
Dan Gohman3069b872008-02-07 18:41:25 +00001430 PseudoSourceValue::getStack(), LocMemOffset);
Evan Chengdffbd832008-01-10 00:09:10 +00001431}
1432
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001433/// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
1434/// optimization is performed and it is required.
Dan Gohman475871a2008-07-27 21:46:04 +00001435SDValue
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001436X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
Dan Gohman475871a2008-07-27 21:46:04 +00001437 SDValue &OutRetAddr,
1438 SDValue Chain,
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001439 bool IsTailCall,
1440 bool Is64Bit,
1441 int FPDiff) {
1442 if (!IsTailCall || FPDiff==0) return Chain;
1443
1444 // Adjust the Return address stack slot.
Duncan Sands83ec4b62008-06-06 12:08:01 +00001445 MVT VT = getPointerTy();
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001446 OutRetAddr = getReturnAddressFrameIndex(DAG);
1447 // Load the "old" Return address.
1448 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
Gabor Greifba36cb52008-08-28 21:40:38 +00001449 return SDValue(OutRetAddr.getNode(), 1);
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001450}
1451
1452/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1453/// optimization is performed and it is required (FPDiff!=0).
Dan Gohman475871a2008-07-27 21:46:04 +00001454static SDValue
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001455EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
Dan Gohman475871a2008-07-27 21:46:04 +00001456 SDValue Chain, SDValue RetAddrFrIdx,
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001457 bool Is64Bit, int FPDiff) {
1458 // Store the return address to the appropriate stack slot.
1459 if (!FPDiff) return Chain;
1460 // Calculate the new stack slot for the return address.
1461 int SlotSize = Is64Bit ? 8 : 4;
1462 int NewReturnAddrFI =
1463 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
Duncan Sands83ec4b62008-06-06 12:08:01 +00001464 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
Dan Gohman475871a2008-07-27 21:46:04 +00001465 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001466 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
Dan Gohmana54cf172008-07-11 22:44:52 +00001467 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001468 return Chain;
1469}
1470
Dan Gohman475871a2008-07-27 21:46:04 +00001471SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001472 MachineFunction &MF = DAG.getMachineFunction();
Evan Chengab6c3bb2008-08-25 21:27:18 +00001473 SDValue Chain = Op.getOperand(0);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001474 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1475 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1476 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue() != 0
Gordon Henriksen86737662008-01-05 16:56:59 +00001477 && CC == CallingConv::Fast && PerformTailCallOpt;
Evan Chengab6c3bb2008-08-25 21:27:18 +00001478 SDValue Callee = Op.getOperand(4);
Gordon Henriksen86737662008-01-05 16:56:59 +00001479 bool Is64Bit = Subtarget->is64Bit();
Evan Cheng0d9e9762008-01-29 19:34:22 +00001480 bool IsStructRet = CallIsStructReturn(Op);
Gordon Henriksenae636f82008-01-03 16:47:34 +00001481
1482 assert(!(isVarArg && CC == CallingConv::Fast) &&
1483 "Var args not supported with calling convention fastcc");
1484
Chris Lattner638402b2007-02-28 07:00:42 +00001485 // Analyze operands of the call, assigning locations to each operand.
Chris Lattner423c5f42007-02-28 05:31:48 +00001486 SmallVector<CCValAssign, 16> ArgLocs;
Chris Lattner52387be2007-06-19 00:13:10 +00001487 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
Gabor Greifba36cb52008-08-28 21:40:38 +00001488 CCInfo.AnalyzeCallOperands(Op.getNode(), CCAssignFnForNode(Op));
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001489
Chris Lattner423c5f42007-02-28 05:31:48 +00001490 // Get a count of how many bytes are to be pushed on the stack.
1491 unsigned NumBytes = CCInfo.getNextStackOffset();
Arnold Schwaighofer1fdc40f2008-09-11 20:28:43 +00001492 if (PerformTailCallOpt && CC == CallingConv::Fast)
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001493 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001494
Gordon Henriksen86737662008-01-05 16:56:59 +00001495 int FPDiff = 0;
1496 if (IsTailCall) {
1497 // Lower arguments at fp - stackoffset + fpdiff.
1498 unsigned NumBytesCallerPushed =
1499 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1500 FPDiff = NumBytesCallerPushed - NumBytes;
1501
1502 // Set the delta of movement of the returnaddr stackslot.
1503 // But only set if delta is greater than previous delta.
1504 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1505 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1506 }
1507
Chris Lattner0bd48932008-01-17 07:00:52 +00001508 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001509
Dan Gohman475871a2008-07-27 21:46:04 +00001510 SDValue RetAddrFrIdx;
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001511 // Load return adress for tail calls.
1512 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1513 FPDiff);
Gordon Henriksen86737662008-01-05 16:56:59 +00001514
Dan Gohman475871a2008-07-27 21:46:04 +00001515 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1516 SmallVector<SDValue, 8> MemOpChains;
1517 SDValue StackPtr;
Chris Lattner423c5f42007-02-28 05:31:48 +00001518
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001519 // Walk the register/memloc assignments, inserting copies/loads. In the case
1520 // of tail call optimization arguments are handle later.
Chris Lattner423c5f42007-02-28 05:31:48 +00001521 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1522 CCValAssign &VA = ArgLocs[i];
Dan Gohman475871a2008-07-27 21:46:04 +00001523 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001524 bool isByVal = cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->
1525 getArgFlags().isByVal();
1526
Chris Lattner423c5f42007-02-28 05:31:48 +00001527 // Promote the value if needed.
1528 switch (VA.getLocInfo()) {
1529 default: assert(0 && "Unknown loc info!");
1530 case CCValAssign::Full: break;
1531 case CCValAssign::SExt:
1532 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1533 break;
1534 case CCValAssign::ZExt:
1535 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1536 break;
1537 case CCValAssign::AExt:
1538 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1539 break;
Evan Cheng6b5783d2006-05-25 18:56:34 +00001540 }
Chris Lattner423c5f42007-02-28 05:31:48 +00001541
1542 if (VA.isRegLoc()) {
Evan Cheng10e86422008-04-25 19:11:04 +00001543 if (Is64Bit) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00001544 MVT RegVT = VA.getLocVT();
1545 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
Evan Cheng10e86422008-04-25 19:11:04 +00001546 switch (VA.getLocReg()) {
1547 default:
1548 break;
1549 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1550 case X86::R8: {
1551 // Special case: passing MMX values in GPR registers.
1552 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1553 break;
1554 }
1555 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1556 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1557 // Special case: passing MMX values in XMM registers.
1558 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1559 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1560 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1561 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1562 getMOVLMask(2, DAG));
1563 break;
1564 }
1565 }
1566 }
Chris Lattner423c5f42007-02-28 05:31:48 +00001567 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1568 } else {
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001569 if (!IsTailCall || (IsTailCall && isByVal)) {
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001570 assert(VA.isMemLoc());
Gabor Greifba36cb52008-08-28 21:40:38 +00001571 if (StackPtr.getNode() == 0)
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001572 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1573
1574 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1575 Arg));
1576 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001577 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001578 }
Chris Lattnerc0bdf342007-02-28 05:39:26 +00001579
Evan Cheng32fe1032006-05-25 00:59:30 +00001580 if (!MemOpChains.empty())
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001581 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1582 &MemOpChains[0], MemOpChains.size());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001583
Evan Cheng347d5f72006-04-28 21:29:37 +00001584 // Build a sequence of copy-to-reg nodes chained together with token chain
1585 // and flag operands which copy the outgoing args into registers.
Dan Gohman475871a2008-07-27 21:46:04 +00001586 SDValue InFlag;
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001587 // Tail call byval lowering might overwrite argument registers so in case of
1588 // tail call optimization the copies to registers are lowered later.
1589 if (!IsTailCall)
1590 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1591 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1592 InFlag);
1593 InFlag = Chain.getValue(1);
1594 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001595
Evan Chengf4684712007-02-21 21:18:14 +00001596 // ELF / PIC requires GOT in the EBX register before function calls via PLT
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001597 // GOT pointer.
Arnold Schwaighofer258bb1b2008-02-26 22:21:54 +00001598 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1599 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1600 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1601 InFlag);
1602 InFlag = Chain.getValue(1);
1603 }
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001604 // If we are tail calling and generating PIC/GOT style code load the address
1605 // of the callee into ecx. The value in ecx is used as target of the tail
1606 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1607 // calls on PIC/GOT architectures. Normally we would just put the address of
1608 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1609 // restored (since ebx is callee saved) before jumping to the target@PLT.
Arnold Schwaighofer258bb1b2008-02-26 22:21:54 +00001610 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001611 // Note: The actual moving to ecx is done further down.
1612 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1613 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1614 !G->getGlobal()->hasProtectedVisibility())
1615 Callee = LowerGlobalAddress(Callee, DAG);
1616 else if (isa<ExternalSymbolSDNode>(Callee))
1617 Callee = LowerExternalSymbol(Callee,DAG);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00001618 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001619
Gordon Henriksen86737662008-01-05 16:56:59 +00001620 if (Is64Bit && isVarArg) {
1621 // From AMD64 ABI document:
1622 // For calls that may call functions that use varargs or stdargs
1623 // (prototype-less calls or calls to functions containing ellipsis (...) in
1624 // the declaration) %al is used as hidden argument to specify the number
1625 // of SSE registers used. The contents of %al do not need to match exactly
1626 // the number of registers, but must be an ubound on the number of SSE
1627 // registers used and is in the range 0 - 8 inclusive.
Anton Korobeynikov998a5bc2008-04-27 23:15:03 +00001628
1629 // FIXME: Verify this on Win64
Gordon Henriksen86737662008-01-05 16:56:59 +00001630 // Count the number of XMM registers allocated.
1631 static const unsigned XMMArgRegs[] = {
1632 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1633 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1634 };
1635 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1636
1637 Chain = DAG.getCopyToReg(Chain, X86::AL,
1638 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1639 InFlag = Chain.getValue(1);
1640 }
1641
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001642
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001643 // For tail calls lower the arguments to the 'real' stack slot.
Gordon Henriksen86737662008-01-05 16:56:59 +00001644 if (IsTailCall) {
Dan Gohman475871a2008-07-27 21:46:04 +00001645 SmallVector<SDValue, 8> MemOpChains2;
1646 SDValue FIN;
Gordon Henriksen86737662008-01-05 16:56:59 +00001647 int FI = 0;
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001648 // Do not flag preceeding copytoreg stuff together with the following stuff.
Dan Gohman475871a2008-07-27 21:46:04 +00001649 InFlag = SDValue();
Gordon Henriksen86737662008-01-05 16:56:59 +00001650 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1651 CCValAssign &VA = ArgLocs[i];
1652 if (!VA.isRegLoc()) {
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001653 assert(VA.isMemLoc());
Dan Gohman475871a2008-07-27 21:46:04 +00001654 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
1655 SDValue FlagsOp = Op.getOperand(6+2*VA.getValNo());
Duncan Sands276dcbd2008-03-21 09:14:45 +00001656 ISD::ArgFlagsTy Flags =
1657 cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags();
Gordon Henriksen86737662008-01-05 16:56:59 +00001658 // Create frame index.
1659 int32_t Offset = VA.getLocMemOffset()+FPDiff;
Duncan Sands83ec4b62008-06-06 12:08:01 +00001660 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
Gordon Henriksen86737662008-01-05 16:56:59 +00001661 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001662 FIN = DAG.getFrameIndex(FI, getPointerTy());
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001663
Duncan Sands276dcbd2008-03-21 09:14:45 +00001664 if (Flags.isByVal()) {
Evan Cheng8e5712b2008-01-12 01:08:07 +00001665 // Copy relative to framepointer.
Dan Gohman475871a2008-07-27 21:46:04 +00001666 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
Gabor Greifba36cb52008-08-28 21:40:38 +00001667 if (StackPtr.getNode() == 0)
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001668 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1669 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1670
1671 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
Evan Cheng8e5712b2008-01-12 01:08:07 +00001672 Flags, DAG));
Gordon Henriksen86737662008-01-05 16:56:59 +00001673 } else {
Evan Cheng8e5712b2008-01-12 01:08:07 +00001674 // Store relative to framepointer.
Dan Gohman69de1932008-02-06 22:27:42 +00001675 MemOpChains2.push_back(
Arnold Schwaighofer865c6812008-02-26 09:19:59 +00001676 DAG.getStore(Chain, Arg, FIN,
Dan Gohmana54cf172008-07-11 22:44:52 +00001677 PseudoSourceValue::getFixedStack(FI), 0));
Arnold Schwaighoferc8ab8cd2008-01-11 16:49:42 +00001678 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001679 }
1680 }
1681
1682 if (!MemOpChains2.empty())
1683 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
Arnold Schwaighofer719eb022008-01-11 14:34:56 +00001684 &MemOpChains2[0], MemOpChains2.size());
Gordon Henriksen86737662008-01-05 16:56:59 +00001685
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001686 // Copy arguments to their registers.
1687 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1688 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1689 InFlag);
1690 InFlag = Chain.getValue(1);
1691 }
Dan Gohman475871a2008-07-27 21:46:04 +00001692 InFlag =SDValue();
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001693
Gordon Henriksen86737662008-01-05 16:56:59 +00001694 // Store the return address to the appropriate stack slot.
Arnold Schwaighofer4b5324a2008-04-12 18:11:06 +00001695 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1696 FPDiff);
Gordon Henriksen86737662008-01-05 16:56:59 +00001697 }
1698
Evan Cheng32fe1032006-05-25 00:59:30 +00001699 // If the callee is a GlobalAddress node (quite common, every direct call is)
1700 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
Anton Korobeynikova5986852006-11-20 10:46:14 +00001701 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Anton Korobeynikov2b2bc682006-12-22 22:29:05 +00001702 // We should use extra load for direct calls to dllimported functions in
1703 // non-JIT mode.
Evan Cheng817a6a92008-07-16 01:34:02 +00001704 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1705 getTargetMachine(), true))
Anton Korobeynikova5986852006-11-20 10:46:14 +00001706 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
Gordon Henriksenae636f82008-01-03 16:47:34 +00001707 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Evan Cheng817a6a92008-07-16 01:34:02 +00001708 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
Gordon Henriksen86737662008-01-05 16:56:59 +00001709 } else if (IsTailCall) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001710 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1711
1712 Chain = DAG.getCopyToReg(Chain,
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001713 DAG.getRegister(Opc, getPointerTy()),
Gordon Henriksen86737662008-01-05 16:56:59 +00001714 Callee,InFlag);
1715 Callee = DAG.getRegister(Opc, getPointerTy());
1716 // Add register as live out.
1717 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
Gordon Henriksenae636f82008-01-03 16:47:34 +00001718 }
1719
Chris Lattnerd96d0722007-02-25 06:40:16 +00001720 // Returns a chain & a flag for retval copy to use.
1721 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00001722 SmallVector<SDValue, 8> Ops;
Gordon Henriksen86737662008-01-05 16:56:59 +00001723
1724 if (IsTailCall) {
1725 Ops.push_back(Chain);
Chris Lattner0bd48932008-01-17 07:00:52 +00001726 Ops.push_back(DAG.getIntPtrConstant(NumBytes));
1727 Ops.push_back(DAG.getIntPtrConstant(0));
Gabor Greifba36cb52008-08-28 21:40:38 +00001728 if (InFlag.getNode())
Gordon Henriksen86737662008-01-05 16:56:59 +00001729 Ops.push_back(InFlag);
1730 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1731 InFlag = Chain.getValue(1);
1732
1733 // Returns a chain & a flag for retval copy to use.
1734 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1735 Ops.clear();
1736 }
1737
Nate Begeman4c5dcf52006-02-17 00:03:04 +00001738 Ops.push_back(Chain);
1739 Ops.push_back(Callee);
Evan Chengb69d1132006-06-14 18:17:40 +00001740
Gordon Henriksen86737662008-01-05 16:56:59 +00001741 if (IsTailCall)
1742 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
Evan Chengf4684712007-02-21 21:18:14 +00001743
Gordon Henriksen86737662008-01-05 16:56:59 +00001744 // Add argument registers to the end of the list so that they are known live
1745 // into the call.
Evan Cheng9b449442008-01-07 23:08:23 +00001746 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1747 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1748 RegsToPass[i].second.getValueType()));
Gordon Henriksen86737662008-01-05 16:56:59 +00001749
Evan Cheng586ccac2008-03-18 23:36:35 +00001750 // Add an implicit use GOT pointer in EBX.
1751 if (!IsTailCall && !Is64Bit &&
1752 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1753 Subtarget->isPICStyleGOT())
1754 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1755
1756 // Add an implicit use of AL for x86 vararg functions.
1757 if (Is64Bit && isVarArg)
1758 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1759
Gabor Greifba36cb52008-08-28 21:40:38 +00001760 if (InFlag.getNode())
Evan Cheng347d5f72006-04-28 21:29:37 +00001761 Ops.push_back(InFlag);
Gordon Henriksenae636f82008-01-03 16:47:34 +00001762
Gordon Henriksen86737662008-01-05 16:56:59 +00001763 if (IsTailCall) {
Gabor Greifba36cb52008-08-28 21:40:38 +00001764 assert(InFlag.getNode() &&
Gordon Henriksen86737662008-01-05 16:56:59 +00001765 "Flag must be set. Depend on flag being set in LowerRET");
1766 Chain = DAG.getNode(X86ISD::TAILCALL,
Gabor Greifba36cb52008-08-28 21:40:38 +00001767 Op.getNode()->getVTList(), &Ops[0], Ops.size());
Gordon Henriksen86737662008-01-05 16:56:59 +00001768
Gabor Greifba36cb52008-08-28 21:40:38 +00001769 return SDValue(Chain.getNode(), Op.getResNo());
Gordon Henriksen86737662008-01-05 16:56:59 +00001770 }
1771
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001772 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
Evan Cheng347d5f72006-04-28 21:29:37 +00001773 InFlag = Chain.getValue(1);
Evan Chengd90eb7f2006-01-05 00:27:02 +00001774
Chris Lattner2d297092006-05-23 18:50:38 +00001775 // Create the CALLSEQ_END node.
Gordon Henriksen86737662008-01-05 16:56:59 +00001776 unsigned NumBytesForCalleeToPush;
1777 if (IsCalleePop(Op))
1778 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
Evan Chengb188dd92008-09-10 18:25:29 +00001779 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001780 // If this is is a call to a struct-return function, the callee
1781 // pops the hidden struct pointer, so we have to push it back.
1782 // This is common for Darwin/X86, Linux & Mingw32 targets.
Gordon Henriksenae636f82008-01-03 16:47:34 +00001783 NumBytesForCalleeToPush = 4;
Gordon Henriksen86737662008-01-05 16:56:59 +00001784 else
Gordon Henriksenae636f82008-01-03 16:47:34 +00001785 NumBytesForCalleeToPush = 0; // Callee pops nothing.
Gordon Henriksen86737662008-01-05 16:56:59 +00001786
Gordon Henriksenae636f82008-01-03 16:47:34 +00001787 // Returns a flag for retval copy to use.
Bill Wendling0f8d9c02007-11-13 00:44:25 +00001788 Chain = DAG.getCALLSEQ_END(Chain,
Chris Lattner0bd48932008-01-17 07:00:52 +00001789 DAG.getIntPtrConstant(NumBytes),
1790 DAG.getIntPtrConstant(NumBytesForCalleeToPush),
Bill Wendling0f8d9c02007-11-13 00:44:25 +00001791 InFlag);
Chris Lattner3085e152007-02-25 08:59:22 +00001792 InFlag = Chain.getValue(1);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00001793
Chris Lattner3085e152007-02-25 08:59:22 +00001794 // Handle result values, copying them out of physregs into vregs that we
1795 // return.
Gabor Greif327ef032008-08-28 23:19:51 +00001796 return SDValue(LowerCallResult(Chain, InFlag, Op.getNode(), CC, DAG),
1797 Op.getResNo());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001798}
1799
Evan Cheng25ab6902006-09-08 06:48:29 +00001800
1801//===----------------------------------------------------------------------===//
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001802// Fast Calling Convention (tail call) implementation
1803//===----------------------------------------------------------------------===//
1804
1805// Like std call, callee cleans arguments, convention except that ECX is
1806// reserved for storing the tail called function address. Only 2 registers are
1807// free for argument passing (inreg). Tail call optimization is performed
1808// provided:
1809// * tailcallopt is enabled
1810// * caller/callee are fastcc
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001811// On X86_64 architecture with GOT-style position independent code only local
1812// (within module) calls are supported at the moment.
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00001813// To keep the stack aligned according to platform abi the function
1814// GetAlignedArgumentStackSize ensures that argument delta is always multiples
1815// of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001816// If a tail called function callee has more arguments than the caller the
1817// caller needs to make sure that there is room to move the RETADDR to. This is
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00001818// achieved by reserving an area the size of the argument delta right after the
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001819// original REtADDR, but before the saved framepointer or the spilled registers
1820// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1821// stack layout:
1822// arg1
1823// arg2
1824// RETADDR
1825// [ new RETADDR
1826// move area ]
1827// (possible EBP)
1828// ESI
1829// EDI
1830// local1 ..
1831
1832/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1833/// for a 16 byte align requirement.
1834unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1835 SelectionDAG& DAG) {
Evan Chenge9ac9e62008-09-07 09:07:23 +00001836 MachineFunction &MF = DAG.getMachineFunction();
1837 const TargetMachine &TM = MF.getTarget();
1838 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1839 unsigned StackAlignment = TFI.getStackAlignment();
1840 uint64_t AlignMask = StackAlignment - 1;
1841 int64_t Offset = StackSize;
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00001842 uint64_t SlotSize = TD->getPointerSize();
Evan Chenge9ac9e62008-09-07 09:07:23 +00001843 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1844 // Number smaller than 12 so just add the difference.
1845 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1846 } else {
1847 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1848 Offset = ((~AlignMask) & Offset) + StackAlignment +
1849 (StackAlignment-SlotSize);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001850 }
Evan Chenge9ac9e62008-09-07 09:07:23 +00001851 return Offset;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001852}
1853
1854/// IsEligibleForTailCallElimination - Check to see whether the next instruction
Evan Cheng9df7dc52007-11-02 01:26:22 +00001855/// following the call is a return. A function is eligible if caller/callee
1856/// calling conventions match, currently only fastcc supports tail calls, and
1857/// the function CALL is immediatly followed by a RET.
Dan Gohman475871a2008-07-27 21:46:04 +00001858bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Call,
1859 SDValue Ret,
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001860 SelectionDAG& DAG) const {
Evan Cheng9df7dc52007-11-02 01:26:22 +00001861 if (!PerformTailCallOpt)
1862 return false;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001863
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +00001864 if (CheckTailCallReturnConstraints(Call, Ret)) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001865 MachineFunction &MF = DAG.getMachineFunction();
1866 unsigned CallerCC = MF.getFunction()->getCallingConv();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001867 unsigned CalleeCC= cast<ConstantSDNode>(Call.getOperand(1))->getZExtValue();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001868 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
Dan Gohman475871a2008-07-27 21:46:04 +00001869 SDValue Callee = Call.getOperand(4);
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001870 // On x86/32Bit PIC/GOT tail calls are supported.
Evan Cheng9df7dc52007-11-02 01:26:22 +00001871 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001872 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
Evan Cheng9df7dc52007-11-02 01:26:22 +00001873 return true;
1874
Arnold Schwaighofera2a4b472008-02-26 10:21:54 +00001875 // Can only do local tail calls (in same module, hidden or protected) on
1876 // x86_64 PIC/GOT at the moment.
Gordon Henriksen86737662008-01-05 16:56:59 +00001877 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1878 return G->getGlobal()->hasHiddenVisibility()
1879 || G->getGlobal()->hasProtectedVisibility();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001880 }
1881 }
Evan Cheng9df7dc52007-11-02 01:26:22 +00001882
1883 return false;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001884}
1885
Dan Gohman3df24e62008-09-03 23:12:08 +00001886FastISel *
1887X86TargetLowering::createFastISel(MachineFunction &mf,
1888 DenseMap<const Value *, unsigned> &vm,
1889 DenseMap<const BasicBlock *,
Dan Gohman0586d912008-09-10 20:11:02 +00001890 MachineBasicBlock *> &bm,
1891 DenseMap<const AllocaInst *, int> &am) {
1892
1893 return X86::createFastISel(mf, vm, bm, am);
Dan Gohmand9f3c482008-08-19 21:32:53 +00001894}
1895
1896
Chris Lattnerfcf1a3d2007-02-28 06:10:12 +00001897//===----------------------------------------------------------------------===//
1898// Other Lowering Hooks
1899//===----------------------------------------------------------------------===//
1900
1901
Dan Gohman475871a2008-07-27 21:46:04 +00001902SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
Anton Korobeynikova2780e12007-08-15 17:12:32 +00001903 MachineFunction &MF = DAG.getMachineFunction();
1904 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1905 int ReturnAddrIndex = FuncInfo->getRAIndex();
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00001906 uint64_t SlotSize = TD->getPointerSize();
Anton Korobeynikova2780e12007-08-15 17:12:32 +00001907
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001908 if (ReturnAddrIndex == 0) {
1909 // Set up a frame object for the return address.
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00001910 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
Anton Korobeynikova2780e12007-08-15 17:12:32 +00001911 FuncInfo->setRAIndex(ReturnAddrIndex);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001912 }
1913
Evan Cheng25ab6902006-09-08 06:48:29 +00001914 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001915}
1916
1917
Evan Cheng6dfa9992006-01-30 23:41:35 +00001918/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1919/// specific condition code. It returns a false if it cannot do a direct
Chris Lattnerf9570512006-09-13 03:22:10 +00001920/// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1921/// needed.
Evan Cheng6be2c582006-04-05 23:38:46 +00001922static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
Dan Gohman475871a2008-07-27 21:46:04 +00001923 unsigned &X86CC, SDValue &LHS, SDValue &RHS,
Chris Lattnerf9570512006-09-13 03:22:10 +00001924 SelectionDAG &DAG) {
Chris Lattner7fbe9722006-10-20 17:42:20 +00001925 X86CC = X86::COND_INVALID;
Evan Chengd9558e02006-01-06 00:43:03 +00001926 if (!isFP) {
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001927 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1928 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1929 // X > -1 -> X == 0, jump !sign.
1930 RHS = DAG.getConstant(0, RHS.getValueType());
Chris Lattner7fbe9722006-10-20 17:42:20 +00001931 X86CC = X86::COND_NS;
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001932 return true;
1933 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1934 // X < 0 -> X == 0, jump on sign.
Chris Lattner7fbe9722006-10-20 17:42:20 +00001935 X86CC = X86::COND_S;
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001936 return true;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001937 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
Dan Gohman5f6913c2007-09-17 14:49:27 +00001938 // X < 1 -> X <= 0
1939 RHS = DAG.getConstant(0, RHS.getValueType());
1940 X86CC = X86::COND_LE;
1941 return true;
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001942 }
Chris Lattnerf9570512006-09-13 03:22:10 +00001943 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00001944
Evan Chengd9558e02006-01-06 00:43:03 +00001945 switch (SetCCOpcode) {
1946 default: break;
Chris Lattner7fbe9722006-10-20 17:42:20 +00001947 case ISD::SETEQ: X86CC = X86::COND_E; break;
1948 case ISD::SETGT: X86CC = X86::COND_G; break;
1949 case ISD::SETGE: X86CC = X86::COND_GE; break;
1950 case ISD::SETLT: X86CC = X86::COND_L; break;
1951 case ISD::SETLE: X86CC = X86::COND_LE; break;
1952 case ISD::SETNE: X86CC = X86::COND_NE; break;
1953 case ISD::SETULT: X86CC = X86::COND_B; break;
1954 case ISD::SETUGT: X86CC = X86::COND_A; break;
1955 case ISD::SETULE: X86CC = X86::COND_BE; break;
1956 case ISD::SETUGE: X86CC = X86::COND_AE; break;
Evan Chengd9558e02006-01-06 00:43:03 +00001957 }
1958 } else {
Evan Cheng45670442008-08-29 23:22:12 +00001959 // First determine if it requires or is profitable to flip the operands.
1960 bool Flip = false;
1961 switch (SetCCOpcode) {
1962 default: break;
1963 case ISD::SETOLT:
1964 case ISD::SETOLE:
1965 case ISD::SETUGT:
1966 case ISD::SETUGE:
1967 Flip = true;
1968 break;
1969 }
1970
1971 // If LHS is a foldable load, but RHS is not, flip the condition.
1972 if (!Flip &&
1973 (ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
1974 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
1975 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
1976 Flip = true;
1977 }
1978 if (Flip)
1979 std::swap(LHS, RHS);
1980
Evan Chengd9558e02006-01-06 00:43:03 +00001981 // On a floating point condition, the flags are set as follows:
1982 // ZF PF CF op
1983 // 0 | 0 | 0 | X > Y
1984 // 0 | 0 | 1 | X < Y
1985 // 1 | 0 | 0 | X == Y
1986 // 1 | 1 | 1 | unordered
1987 switch (SetCCOpcode) {
1988 default: break;
1989 case ISD::SETUEQ:
Evan Cheng45670442008-08-29 23:22:12 +00001990 case ISD::SETEQ:
1991 X86CC = X86::COND_E;
1992 break;
1993 case ISD::SETOLT: // flipped
Evan Chengd9558e02006-01-06 00:43:03 +00001994 case ISD::SETOGT:
Evan Cheng45670442008-08-29 23:22:12 +00001995 case ISD::SETGT:
1996 X86CC = X86::COND_A;
1997 break;
1998 case ISD::SETOLE: // flipped
Evan Chengd9558e02006-01-06 00:43:03 +00001999 case ISD::SETOGE:
Evan Cheng45670442008-08-29 23:22:12 +00002000 case ISD::SETGE:
2001 X86CC = X86::COND_AE;
2002 break;
2003 case ISD::SETUGT: // flipped
Evan Chengd9558e02006-01-06 00:43:03 +00002004 case ISD::SETULT:
Evan Cheng45670442008-08-29 23:22:12 +00002005 case ISD::SETLT:
2006 X86CC = X86::COND_B;
2007 break;
2008 case ISD::SETUGE: // flipped
Evan Chengd9558e02006-01-06 00:43:03 +00002009 case ISD::SETULE:
Evan Cheng45670442008-08-29 23:22:12 +00002010 case ISD::SETLE:
2011 X86CC = X86::COND_BE;
2012 break;
Evan Chengd9558e02006-01-06 00:43:03 +00002013 case ISD::SETONE:
Evan Cheng45670442008-08-29 23:22:12 +00002014 case ISD::SETNE:
2015 X86CC = X86::COND_NE;
2016 break;
2017 case ISD::SETUO:
2018 X86CC = X86::COND_P;
2019 break;
2020 case ISD::SETO:
2021 X86CC = X86::COND_NP;
2022 break;
Evan Chengd9558e02006-01-06 00:43:03 +00002023 }
Evan Cheng4d46d0a2008-08-28 23:48:31 +00002024 }
2025
Evan Cheng94a50da2008-08-29 22:13:21 +00002026 return X86CC != X86::COND_INVALID;
Evan Chengd9558e02006-01-06 00:43:03 +00002027}
2028
Evan Cheng4a460802006-01-11 00:33:36 +00002029/// hasFPCMov - is there a floating point cmov for the specific X86 condition
2030/// code. Current x86 isa includes the following FP cmov instructions:
Evan Chengaaca22c2006-01-10 20:26:56 +00002031/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
Evan Cheng4a460802006-01-11 00:33:36 +00002032static bool hasFPCMov(unsigned X86CC) {
Evan Chengaaca22c2006-01-10 20:26:56 +00002033 switch (X86CC) {
2034 default:
2035 return false;
Chris Lattner7fbe9722006-10-20 17:42:20 +00002036 case X86::COND_B:
2037 case X86::COND_BE:
2038 case X86::COND_E:
2039 case X86::COND_P:
2040 case X86::COND_A:
2041 case X86::COND_AE:
2042 case X86::COND_NE:
2043 case X86::COND_NP:
Evan Chengaaca22c2006-01-10 20:26:56 +00002044 return true;
2045 }
2046}
2047
Evan Cheng5ced1d82006-04-06 23:23:56 +00002048/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
Evan Chengc5cdff22006-04-07 21:53:05 +00002049/// true if Op is undef or if its value falls within the specified range (L, H].
Dan Gohman475871a2008-07-27 21:46:04 +00002050static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
Evan Cheng5ced1d82006-04-06 23:23:56 +00002051 if (Op.getOpcode() == ISD::UNDEF)
2052 return true;
2053
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002054 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
Evan Chengc5cdff22006-04-07 21:53:05 +00002055 return (Val >= Low && Val < Hi);
2056}
2057
2058/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2059/// true if Op is undef or if its value equal to the specified value.
Dan Gohman475871a2008-07-27 21:46:04 +00002060static bool isUndefOrEqual(SDValue Op, unsigned Val) {
Evan Chengc5cdff22006-04-07 21:53:05 +00002061 if (Op.getOpcode() == ISD::UNDEF)
2062 return true;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002063 return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002064}
2065
Evan Cheng0188ecb2006-03-22 18:59:22 +00002066/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2067/// specifies a shuffle of elements that is suitable for input to PSHUFD.
2068bool X86::isPSHUFDMask(SDNode *N) {
2069 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2070
Dan Gohman7f55fcb2007-08-02 21:17:01 +00002071 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
Evan Cheng0188ecb2006-03-22 18:59:22 +00002072 return false;
2073
2074 // Check if the value doesn't reference the second vector.
Evan Cheng506d3df2006-03-29 23:07:14 +00002075 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002076 SDValue Arg = N->getOperand(i);
Evan Chengef698ca2006-03-31 00:30:29 +00002077 if (Arg.getOpcode() == ISD::UNDEF) continue;
2078 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002079 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
Evan Cheng506d3df2006-03-29 23:07:14 +00002080 return false;
2081 }
2082
2083 return true;
2084}
2085
2086/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
Evan Chengc21a0532006-04-05 01:47:37 +00002087/// specifies a shuffle of elements that is suitable for input to PSHUFHW.
Evan Cheng506d3df2006-03-29 23:07:14 +00002088bool X86::isPSHUFHWMask(SDNode *N) {
2089 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2090
2091 if (N->getNumOperands() != 8)
2092 return false;
2093
2094 // Lower quadword copied in order.
2095 for (unsigned i = 0; i != 4; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002096 SDValue Arg = N->getOperand(i);
Evan Chengef698ca2006-03-31 00:30:29 +00002097 if (Arg.getOpcode() == ISD::UNDEF) continue;
2098 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002099 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
Evan Cheng506d3df2006-03-29 23:07:14 +00002100 return false;
2101 }
2102
2103 // Upper quadword shuffled.
2104 for (unsigned i = 4; i != 8; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002105 SDValue Arg = N->getOperand(i);
Evan Chengef698ca2006-03-31 00:30:29 +00002106 if (Arg.getOpcode() == ISD::UNDEF) continue;
2107 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002108 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Cheng506d3df2006-03-29 23:07:14 +00002109 if (Val < 4 || Val > 7)
2110 return false;
2111 }
2112
2113 return true;
2114}
2115
2116/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
Evan Chengc21a0532006-04-05 01:47:37 +00002117/// specifies a shuffle of elements that is suitable for input to PSHUFLW.
Evan Cheng506d3df2006-03-29 23:07:14 +00002118bool X86::isPSHUFLWMask(SDNode *N) {
2119 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2120
2121 if (N->getNumOperands() != 8)
2122 return false;
2123
2124 // Upper quadword copied in order.
Evan Chengc5cdff22006-04-07 21:53:05 +00002125 for (unsigned i = 4; i != 8; ++i)
2126 if (!isUndefOrEqual(N->getOperand(i), i))
Evan Cheng506d3df2006-03-29 23:07:14 +00002127 return false;
Evan Cheng506d3df2006-03-29 23:07:14 +00002128
2129 // Lower quadword shuffled.
Evan Chengc5cdff22006-04-07 21:53:05 +00002130 for (unsigned i = 0; i != 4; ++i)
2131 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
Evan Cheng506d3df2006-03-29 23:07:14 +00002132 return false;
Evan Cheng0188ecb2006-03-22 18:59:22 +00002133
2134 return true;
2135}
2136
Evan Cheng14aed5e2006-03-24 01:18:28 +00002137/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2138/// specifies a shuffle of elements that is suitable for input to SHUFP*.
Roman Levenstein9cac5252008-04-16 16:15:27 +00002139static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
Evan Cheng39623da2006-04-20 08:58:49 +00002140 if (NumElems != 2 && NumElems != 4) return false;
Evan Cheng14aed5e2006-03-24 01:18:28 +00002141
Evan Cheng39623da2006-04-20 08:58:49 +00002142 unsigned Half = NumElems / 2;
2143 for (unsigned i = 0; i < Half; ++i)
Chris Lattner5a88b832007-02-25 07:10:00 +00002144 if (!isUndefOrInRange(Elems[i], 0, NumElems))
Evan Cheng39623da2006-04-20 08:58:49 +00002145 return false;
2146 for (unsigned i = Half; i < NumElems; ++i)
Chris Lattner5a88b832007-02-25 07:10:00 +00002147 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
Evan Cheng39623da2006-04-20 08:58:49 +00002148 return false;
Evan Cheng14aed5e2006-03-24 01:18:28 +00002149
2150 return true;
2151}
2152
Evan Cheng39623da2006-04-20 08:58:49 +00002153bool X86::isSHUFPMask(SDNode *N) {
2154 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002155 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
Evan Cheng39623da2006-04-20 08:58:49 +00002156}
2157
Evan Cheng213d2cf2007-05-17 18:45:50 +00002158/// isCommutedSHUFP - Returns true if the shuffle mask is exactly
Evan Cheng39623da2006-04-20 08:58:49 +00002159/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2160/// half elements to come from vector 1 (which would equal the dest.) and
2161/// the upper half to come from vector 2.
Roman Levenstein9cac5252008-04-16 16:15:27 +00002162static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
Chris Lattner5a88b832007-02-25 07:10:00 +00002163 if (NumOps != 2 && NumOps != 4) return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002164
Chris Lattner5a88b832007-02-25 07:10:00 +00002165 unsigned Half = NumOps / 2;
Evan Cheng39623da2006-04-20 08:58:49 +00002166 for (unsigned i = 0; i < Half; ++i)
Chris Lattner5a88b832007-02-25 07:10:00 +00002167 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
Evan Cheng39623da2006-04-20 08:58:49 +00002168 return false;
Chris Lattner5a88b832007-02-25 07:10:00 +00002169 for (unsigned i = Half; i < NumOps; ++i)
2170 if (!isUndefOrInRange(Ops[i], 0, NumOps))
Evan Cheng39623da2006-04-20 08:58:49 +00002171 return false;
2172 return true;
2173}
2174
2175static bool isCommutedSHUFP(SDNode *N) {
2176 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002177 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
Evan Cheng39623da2006-04-20 08:58:49 +00002178}
2179
Evan Cheng2c0dbd02006-03-24 02:58:06 +00002180/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2181/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2182bool X86::isMOVHLPSMask(SDNode *N) {
2183 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2184
Evan Cheng2064a2b2006-03-28 06:50:32 +00002185 if (N->getNumOperands() != 4)
Evan Cheng2c0dbd02006-03-24 02:58:06 +00002186 return false;
2187
Evan Cheng2064a2b2006-03-28 06:50:32 +00002188 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
Evan Chengc5cdff22006-04-07 21:53:05 +00002189 return isUndefOrEqual(N->getOperand(0), 6) &&
2190 isUndefOrEqual(N->getOperand(1), 7) &&
2191 isUndefOrEqual(N->getOperand(2), 2) &&
2192 isUndefOrEqual(N->getOperand(3), 3);
Evan Cheng2064a2b2006-03-28 06:50:32 +00002193}
2194
Evan Cheng6e56e2c2006-11-07 22:14:24 +00002195/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2196/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2197/// <2, 3, 2, 3>
2198bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2199 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2200
2201 if (N->getNumOperands() != 4)
2202 return false;
2203
2204 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2205 return isUndefOrEqual(N->getOperand(0), 2) &&
2206 isUndefOrEqual(N->getOperand(1), 3) &&
2207 isUndefOrEqual(N->getOperand(2), 2) &&
2208 isUndefOrEqual(N->getOperand(3), 3);
2209}
2210
Evan Cheng5ced1d82006-04-06 23:23:56 +00002211/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2212/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2213bool X86::isMOVLPMask(SDNode *N) {
2214 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2215
2216 unsigned NumElems = N->getNumOperands();
2217 if (NumElems != 2 && NumElems != 4)
2218 return false;
2219
Evan Chengc5cdff22006-04-07 21:53:05 +00002220 for (unsigned i = 0; i < NumElems/2; ++i)
2221 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2222 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002223
Evan Chengc5cdff22006-04-07 21:53:05 +00002224 for (unsigned i = NumElems/2; i < NumElems; ++i)
2225 if (!isUndefOrEqual(N->getOperand(i), i))
2226 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002227
2228 return true;
2229}
2230
2231/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
Evan Cheng533a0aa2006-04-19 20:35:22 +00002232/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2233/// and MOVLHPS.
Evan Cheng5ced1d82006-04-06 23:23:56 +00002234bool X86::isMOVHPMask(SDNode *N) {
2235 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2236
2237 unsigned NumElems = N->getNumOperands();
2238 if (NumElems != 2 && NumElems != 4)
2239 return false;
2240
Evan Chengc5cdff22006-04-07 21:53:05 +00002241 for (unsigned i = 0; i < NumElems/2; ++i)
2242 if (!isUndefOrEqual(N->getOperand(i), i))
2243 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002244
2245 for (unsigned i = 0; i < NumElems/2; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002246 SDValue Arg = N->getOperand(i + NumElems/2);
Evan Chengc5cdff22006-04-07 21:53:05 +00002247 if (!isUndefOrEqual(Arg, i + NumElems))
2248 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002249 }
2250
2251 return true;
2252}
2253
Evan Cheng0038e592006-03-28 00:39:58 +00002254/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2255/// specifies a shuffle of elements that is suitable for input to UNPCKL.
Roman Levenstein9cac5252008-04-16 16:15:27 +00002256bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
Chris Lattner5a88b832007-02-25 07:10:00 +00002257 bool V2IsSplat = false) {
2258 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
Evan Cheng0038e592006-03-28 00:39:58 +00002259 return false;
2260
Chris Lattner5a88b832007-02-25 07:10:00 +00002261 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
Dan Gohman475871a2008-07-27 21:46:04 +00002262 SDValue BitI = Elts[i];
2263 SDValue BitI1 = Elts[i+1];
Evan Chengc5cdff22006-04-07 21:53:05 +00002264 if (!isUndefOrEqual(BitI, j))
2265 return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002266 if (V2IsSplat) {
Chris Lattner5a88b832007-02-25 07:10:00 +00002267 if (isUndefOrEqual(BitI1, NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002268 return false;
2269 } else {
Chris Lattner5a88b832007-02-25 07:10:00 +00002270 if (!isUndefOrEqual(BitI1, j + NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002271 return false;
2272 }
Evan Cheng0038e592006-03-28 00:39:58 +00002273 }
2274
2275 return true;
2276}
2277
Evan Cheng39623da2006-04-20 08:58:49 +00002278bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2279 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002280 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
Evan Cheng39623da2006-04-20 08:58:49 +00002281}
2282
Evan Cheng4fcb9222006-03-28 02:43:26 +00002283/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2284/// specifies a shuffle of elements that is suitable for input to UNPCKH.
Roman Levenstein9cac5252008-04-16 16:15:27 +00002285bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
Chris Lattner5a88b832007-02-25 07:10:00 +00002286 bool V2IsSplat = false) {
2287 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
Evan Cheng4fcb9222006-03-28 02:43:26 +00002288 return false;
2289
Chris Lattner5a88b832007-02-25 07:10:00 +00002290 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
Dan Gohman475871a2008-07-27 21:46:04 +00002291 SDValue BitI = Elts[i];
2292 SDValue BitI1 = Elts[i+1];
Chris Lattner5a88b832007-02-25 07:10:00 +00002293 if (!isUndefOrEqual(BitI, j + NumElts/2))
Evan Chengc5cdff22006-04-07 21:53:05 +00002294 return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002295 if (V2IsSplat) {
Chris Lattner5a88b832007-02-25 07:10:00 +00002296 if (isUndefOrEqual(BitI1, NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002297 return false;
2298 } else {
Chris Lattner5a88b832007-02-25 07:10:00 +00002299 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002300 return false;
2301 }
Evan Cheng4fcb9222006-03-28 02:43:26 +00002302 }
2303
2304 return true;
2305}
2306
Evan Cheng39623da2006-04-20 08:58:49 +00002307bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2308 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002309 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
Evan Cheng39623da2006-04-20 08:58:49 +00002310}
2311
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002312/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2313/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2314/// <0, 0, 1, 1>
2315bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2316 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2317
2318 unsigned NumElems = N->getNumOperands();
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002319 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002320 return false;
2321
2322 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
Dan Gohman475871a2008-07-27 21:46:04 +00002323 SDValue BitI = N->getOperand(i);
2324 SDValue BitI1 = N->getOperand(i+1);
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002325
Evan Chengc5cdff22006-04-07 21:53:05 +00002326 if (!isUndefOrEqual(BitI, j))
2327 return false;
2328 if (!isUndefOrEqual(BitI1, j))
2329 return false;
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002330 }
2331
2332 return true;
2333}
2334
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002335/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2336/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2337/// <2, 2, 3, 3>
2338bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2339 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2340
2341 unsigned NumElems = N->getNumOperands();
2342 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2343 return false;
2344
2345 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
Dan Gohman475871a2008-07-27 21:46:04 +00002346 SDValue BitI = N->getOperand(i);
2347 SDValue BitI1 = N->getOperand(i + 1);
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002348
2349 if (!isUndefOrEqual(BitI, j))
2350 return false;
2351 if (!isUndefOrEqual(BitI1, j))
2352 return false;
2353 }
2354
2355 return true;
2356}
2357
Evan Cheng017dcc62006-04-21 01:05:10 +00002358/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2359/// specifies a shuffle of elements that is suitable for input to MOVSS,
2360/// MOVSD, and MOVD, i.e. setting the lowest element.
Roman Levenstein9cac5252008-04-16 16:15:27 +00002361static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
Evan Cheng10762102007-12-06 22:14:22 +00002362 if (NumElts != 2 && NumElts != 4)
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002363 return false;
2364
Chris Lattner5a88b832007-02-25 07:10:00 +00002365 if (!isUndefOrEqual(Elts[0], NumElts))
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002366 return false;
2367
Chris Lattner5a88b832007-02-25 07:10:00 +00002368 for (unsigned i = 1; i < NumElts; ++i) {
2369 if (!isUndefOrEqual(Elts[i], i))
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002370 return false;
2371 }
2372
2373 return true;
2374}
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002375
Evan Cheng017dcc62006-04-21 01:05:10 +00002376bool X86::isMOVLMask(SDNode *N) {
Evan Cheng39623da2006-04-20 08:58:49 +00002377 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002378 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
Evan Cheng39623da2006-04-20 08:58:49 +00002379}
2380
Evan Cheng017dcc62006-04-21 01:05:10 +00002381/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2382/// of what x86 movss want. X86 movs requires the lowest element to be lowest
Evan Cheng39623da2006-04-20 08:58:49 +00002383/// element of vector 2 and the other elements to come from vector 1 in order.
Roman Levenstein9cac5252008-04-16 16:15:27 +00002384static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
Chris Lattner5a88b832007-02-25 07:10:00 +00002385 bool V2IsSplat = false,
Evan Cheng8cf723d2006-09-08 01:50:06 +00002386 bool V2IsUndef = false) {
Chris Lattner5a88b832007-02-25 07:10:00 +00002387 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
Evan Cheng39623da2006-04-20 08:58:49 +00002388 return false;
2389
2390 if (!isUndefOrEqual(Ops[0], 0))
2391 return false;
2392
Chris Lattner5a88b832007-02-25 07:10:00 +00002393 for (unsigned i = 1; i < NumOps; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002394 SDValue Arg = Ops[i];
Chris Lattner5a88b832007-02-25 07:10:00 +00002395 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2396 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2397 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
Evan Cheng8cf723d2006-09-08 01:50:06 +00002398 return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002399 }
2400
2401 return true;
2402}
2403
Evan Cheng8cf723d2006-09-08 01:50:06 +00002404static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2405 bool V2IsUndef = false) {
Evan Cheng39623da2006-04-20 08:58:49 +00002406 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002407 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2408 V2IsSplat, V2IsUndef);
Evan Cheng39623da2006-04-20 08:58:49 +00002409}
2410
Evan Chengd9539472006-04-14 21:59:03 +00002411/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2412/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2413bool X86::isMOVSHDUPMask(SDNode *N) {
2414 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2415
2416 if (N->getNumOperands() != 4)
2417 return false;
2418
2419 // Expect 1, 1, 3, 3
2420 for (unsigned i = 0; i < 2; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002421 SDValue Arg = N->getOperand(i);
Evan Chengd9539472006-04-14 21:59:03 +00002422 if (Arg.getOpcode() == ISD::UNDEF) continue;
2423 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002424 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Chengd9539472006-04-14 21:59:03 +00002425 if (Val != 1) return false;
2426 }
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002427
2428 bool HasHi = false;
Evan Chengd9539472006-04-14 21:59:03 +00002429 for (unsigned i = 2; i < 4; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002430 SDValue Arg = N->getOperand(i);
Evan Chengd9539472006-04-14 21:59:03 +00002431 if (Arg.getOpcode() == ISD::UNDEF) continue;
2432 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002433 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Chengd9539472006-04-14 21:59:03 +00002434 if (Val != 3) return false;
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002435 HasHi = true;
Evan Chengd9539472006-04-14 21:59:03 +00002436 }
Evan Cheng39fc1452006-04-15 03:13:24 +00002437
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002438 // Don't use movshdup if it can be done with a shufps.
2439 return HasHi;
Evan Chengd9539472006-04-14 21:59:03 +00002440}
2441
2442/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2443/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2444bool X86::isMOVSLDUPMask(SDNode *N) {
2445 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2446
2447 if (N->getNumOperands() != 4)
2448 return false;
2449
2450 // Expect 0, 0, 2, 2
2451 for (unsigned i = 0; i < 2; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002452 SDValue Arg = N->getOperand(i);
Evan Chengd9539472006-04-14 21:59:03 +00002453 if (Arg.getOpcode() == ISD::UNDEF) continue;
2454 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002455 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Chengd9539472006-04-14 21:59:03 +00002456 if (Val != 0) return false;
2457 }
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002458
2459 bool HasHi = false;
Evan Chengd9539472006-04-14 21:59:03 +00002460 for (unsigned i = 2; i < 4; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002461 SDValue Arg = N->getOperand(i);
Evan Chengd9539472006-04-14 21:59:03 +00002462 if (Arg.getOpcode() == ISD::UNDEF) continue;
2463 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002464 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Chengd9539472006-04-14 21:59:03 +00002465 if (Val != 2) return false;
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002466 HasHi = true;
Evan Chengd9539472006-04-14 21:59:03 +00002467 }
Evan Cheng39fc1452006-04-15 03:13:24 +00002468
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002469 // Don't use movshdup if it can be done with a shufps.
2470 return HasHi;
Evan Chengd9539472006-04-14 21:59:03 +00002471}
2472
Evan Cheng49892af2007-06-19 00:02:56 +00002473/// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2474/// specifies a identity operation on the LHS or RHS.
2475static bool isIdentityMask(SDNode *N, bool RHS = false) {
2476 unsigned NumElems = N->getNumOperands();
2477 for (unsigned i = 0; i < NumElems; ++i)
2478 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2479 return false;
2480 return true;
2481}
2482
Evan Chengb9df0ca2006-03-22 02:53:00 +00002483/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2484/// a splat of a single element.
Evan Chengc575ca22006-04-17 20:43:08 +00002485static bool isSplatMask(SDNode *N) {
Evan Chengb9df0ca2006-03-22 02:53:00 +00002486 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2487
Evan Chengb9df0ca2006-03-22 02:53:00 +00002488 // This is a splat operation if each element of the permute is the same, and
2489 // if the value doesn't reference the second vector.
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002490 unsigned NumElems = N->getNumOperands();
Dan Gohman475871a2008-07-27 21:46:04 +00002491 SDValue ElementBase;
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002492 unsigned i = 0;
2493 for (; i != NumElems; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002494 SDValue Elt = N->getOperand(i);
Reid Spencer3ed469c2006-11-02 20:25:50 +00002495 if (isa<ConstantSDNode>(Elt)) {
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002496 ElementBase = Elt;
2497 break;
2498 }
2499 }
2500
Gabor Greifba36cb52008-08-28 21:40:38 +00002501 if (!ElementBase.getNode())
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002502 return false;
2503
2504 for (; i != NumElems; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002505 SDValue Arg = N->getOperand(i);
Evan Chengef698ca2006-03-31 00:30:29 +00002506 if (Arg.getOpcode() == ISD::UNDEF) continue;
2507 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002508 if (Arg != ElementBase) return false;
Evan Chengb9df0ca2006-03-22 02:53:00 +00002509 }
2510
2511 // Make sure it is a splat of the first vector operand.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002512 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
Evan Chengb9df0ca2006-03-22 02:53:00 +00002513}
2514
Evan Chengc575ca22006-04-17 20:43:08 +00002515/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2516/// a splat of a single element and it's a 2 or 4 element mask.
2517bool X86::isSplatMask(SDNode *N) {
2518 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2519
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002520 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
Evan Chengc575ca22006-04-17 20:43:08 +00002521 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2522 return false;
2523 return ::isSplatMask(N);
2524}
2525
Evan Chengf686d9b2006-10-27 21:08:32 +00002526/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2527/// specifies a splat of zero element.
2528bool X86::isSplatLoMask(SDNode *N) {
2529 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2530
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00002531 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
Evan Chengf686d9b2006-10-27 21:08:32 +00002532 if (!isUndefOrEqual(N->getOperand(i), 0))
2533 return false;
2534 return true;
2535}
2536
Evan Cheng63d33002006-03-22 08:01:21 +00002537/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2538/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2539/// instructions.
2540unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
Evan Chengb9df0ca2006-03-22 02:53:00 +00002541 unsigned NumOperands = N->getNumOperands();
2542 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2543 unsigned Mask = 0;
Evan Cheng36b27f32006-03-28 23:41:33 +00002544 for (unsigned i = 0; i < NumOperands; ++i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002545 unsigned Val = 0;
Dan Gohman475871a2008-07-27 21:46:04 +00002546 SDValue Arg = N->getOperand(NumOperands-i-1);
Evan Chengef698ca2006-03-31 00:30:29 +00002547 if (Arg.getOpcode() != ISD::UNDEF)
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002548 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Cheng14aed5e2006-03-24 01:18:28 +00002549 if (Val >= NumOperands) Val -= NumOperands;
Evan Cheng63d33002006-03-22 08:01:21 +00002550 Mask |= Val;
Evan Cheng36b27f32006-03-28 23:41:33 +00002551 if (i != NumOperands - 1)
2552 Mask <<= Shift;
2553 }
Evan Cheng63d33002006-03-22 08:01:21 +00002554
2555 return Mask;
2556}
2557
Evan Cheng506d3df2006-03-29 23:07:14 +00002558/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2559/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2560/// instructions.
2561unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2562 unsigned Mask = 0;
2563 // 8 nodes, but we only care about the last 4.
2564 for (unsigned i = 7; i >= 4; --i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002565 unsigned Val = 0;
Dan Gohman475871a2008-07-27 21:46:04 +00002566 SDValue Arg = N->getOperand(i);
Evan Chengef698ca2006-03-31 00:30:29 +00002567 if (Arg.getOpcode() != ISD::UNDEF)
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002568 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Cheng506d3df2006-03-29 23:07:14 +00002569 Mask |= (Val - 4);
2570 if (i != 4)
2571 Mask <<= 2;
2572 }
2573
2574 return Mask;
2575}
2576
2577/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2578/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2579/// instructions.
2580unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2581 unsigned Mask = 0;
2582 // 8 nodes, but we only care about the first 4.
2583 for (int i = 3; i >= 0; --i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002584 unsigned Val = 0;
Dan Gohman475871a2008-07-27 21:46:04 +00002585 SDValue Arg = N->getOperand(i);
Evan Chengef698ca2006-03-31 00:30:29 +00002586 if (Arg.getOpcode() != ISD::UNDEF)
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002587 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Cheng506d3df2006-03-29 23:07:14 +00002588 Mask |= Val;
2589 if (i != 0)
2590 Mask <<= 2;
2591 }
2592
2593 return Mask;
2594}
2595
Evan Chengc21a0532006-04-05 01:47:37 +00002596/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2597/// specifies a 8 element shuffle that can be broken into a pair of
2598/// PSHUFHW and PSHUFLW.
2599static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2600 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2601
2602 if (N->getNumOperands() != 8)
2603 return false;
2604
2605 // Lower quadword shuffled.
2606 for (unsigned i = 0; i != 4; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002607 SDValue Arg = N->getOperand(i);
Evan Chengc21a0532006-04-05 01:47:37 +00002608 if (Arg.getOpcode() == ISD::UNDEF) continue;
2609 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002610 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00002611 if (Val >= 4)
Evan Chengc21a0532006-04-05 01:47:37 +00002612 return false;
2613 }
2614
2615 // Upper quadword shuffled.
2616 for (unsigned i = 4; i != 8; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002617 SDValue Arg = N->getOperand(i);
Evan Chengc21a0532006-04-05 01:47:37 +00002618 if (Arg.getOpcode() == ISD::UNDEF) continue;
2619 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002620 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Chengc21a0532006-04-05 01:47:37 +00002621 if (Val < 4 || Val > 7)
2622 return false;
2623 }
2624
2625 return true;
2626}
2627
Chris Lattner8a594482007-11-25 00:24:49 +00002628/// CommuteVectorShuffle - Swap vector_shuffle operands as well as
Evan Cheng5ced1d82006-04-06 23:23:56 +00002629/// values in ther permute mask.
Dan Gohman475871a2008-07-27 21:46:04 +00002630static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2631 SDValue &V2, SDValue &Mask,
Evan Cheng9eca5e82006-10-25 21:49:50 +00002632 SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002633 MVT VT = Op.getValueType();
2634 MVT MaskVT = Mask.getValueType();
2635 MVT EltVT = MaskVT.getVectorElementType();
Evan Cheng5ced1d82006-04-06 23:23:56 +00002636 unsigned NumElems = Mask.getNumOperands();
Dan Gohman475871a2008-07-27 21:46:04 +00002637 SmallVector<SDValue, 8> MaskVec;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002638
2639 for (unsigned i = 0; i != NumElems; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002640 SDValue Arg = Mask.getOperand(i);
Evan Cheng80d428c2006-04-19 22:48:17 +00002641 if (Arg.getOpcode() == ISD::UNDEF) {
2642 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2643 continue;
2644 }
Evan Cheng5ced1d82006-04-06 23:23:56 +00002645 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002646 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Cheng5ced1d82006-04-06 23:23:56 +00002647 if (Val < NumElems)
2648 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2649 else
2650 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2651 }
2652
Evan Cheng9eca5e82006-10-25 21:49:50 +00002653 std::swap(V1, V2);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002654 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
Evan Cheng9eca5e82006-10-25 21:49:50 +00002655 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
Evan Cheng5ced1d82006-04-06 23:23:56 +00002656}
2657
Evan Cheng779ccea2007-12-07 21:30:01 +00002658/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2659/// the two vector operands have swapped position.
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002660static
Dan Gohman475871a2008-07-27 21:46:04 +00002661SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002662 MVT MaskVT = Mask.getValueType();
2663 MVT EltVT = MaskVT.getVectorElementType();
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002664 unsigned NumElems = Mask.getNumOperands();
Dan Gohman475871a2008-07-27 21:46:04 +00002665 SmallVector<SDValue, 8> MaskVec;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002666 for (unsigned i = 0; i != NumElems; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002667 SDValue Arg = Mask.getOperand(i);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002668 if (Arg.getOpcode() == ISD::UNDEF) {
2669 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2670 continue;
2671 }
2672 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002673 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002674 if (Val < NumElems)
2675 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2676 else
2677 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2678 }
2679 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2680}
2681
2682
Evan Cheng533a0aa2006-04-19 20:35:22 +00002683/// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2684/// match movhlps. The lower half elements should come from upper half of
2685/// V1 (and in order), and the upper half elements should come from the upper
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00002686/// half of V2 (and in order).
Evan Cheng533a0aa2006-04-19 20:35:22 +00002687static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2688 unsigned NumElems = Mask->getNumOperands();
2689 if (NumElems != 4)
2690 return false;
2691 for (unsigned i = 0, e = 2; i != e; ++i)
2692 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2693 return false;
2694 for (unsigned i = 2; i != 4; ++i)
2695 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2696 return false;
2697 return true;
2698}
2699
Evan Cheng5ced1d82006-04-06 23:23:56 +00002700/// isScalarLoadToVector - Returns true if the node is a scalar load that
Evan Cheng7e2ff772008-05-08 00:57:18 +00002701/// is promoted to a vector. It also returns the LoadSDNode by reference if
2702/// required.
2703static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
Evan Cheng533a0aa2006-04-19 20:35:22 +00002704 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
Gabor Greifba36cb52008-08-28 21:40:38 +00002705 N = N->getOperand(0).getNode();
Evan Cheng7e2ff772008-05-08 00:57:18 +00002706 if (ISD::isNON_EXTLoad(N)) {
2707 if (LD)
2708 *LD = cast<LoadSDNode>(N);
2709 return true;
2710 }
Evan Cheng5ced1d82006-04-06 23:23:56 +00002711 }
2712 return false;
2713}
2714
Evan Cheng533a0aa2006-04-19 20:35:22 +00002715/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2716/// match movlp{s|d}. The lower half elements should come from lower half of
2717/// V1 (and in order), and the upper half elements should come from the upper
2718/// half of V2 (and in order). And since V1 will become the source of the
2719/// MOVLP, it must be either a vector load or a scalar load to vector.
Evan Cheng23425f52006-10-09 21:39:25 +00002720static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
Evan Cheng466685d2006-10-09 20:57:25 +00002721 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
Evan Cheng533a0aa2006-04-19 20:35:22 +00002722 return false;
Evan Cheng23425f52006-10-09 21:39:25 +00002723 // Is V2 is a vector load, don't do this transformation. We will try to use
2724 // load folding shufps op.
2725 if (ISD::isNON_EXTLoad(V2))
2726 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002727
Evan Cheng533a0aa2006-04-19 20:35:22 +00002728 unsigned NumElems = Mask->getNumOperands();
2729 if (NumElems != 2 && NumElems != 4)
2730 return false;
2731 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2732 if (!isUndefOrEqual(Mask->getOperand(i), i))
2733 return false;
2734 for (unsigned i = NumElems/2; i != NumElems; ++i)
2735 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2736 return false;
2737 return true;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002738}
2739
Evan Cheng39623da2006-04-20 08:58:49 +00002740/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2741/// all the same.
2742static bool isSplatVector(SDNode *N) {
2743 if (N->getOpcode() != ISD::BUILD_VECTOR)
2744 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002745
Dan Gohman475871a2008-07-27 21:46:04 +00002746 SDValue SplatValue = N->getOperand(0);
Evan Cheng39623da2006-04-20 08:58:49 +00002747 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2748 if (N->getOperand(i) != SplatValue)
Evan Cheng5ced1d82006-04-06 23:23:56 +00002749 return false;
2750 return true;
2751}
2752
Evan Cheng8cf723d2006-09-08 01:50:06 +00002753/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2754/// to an undef.
2755static bool isUndefShuffle(SDNode *N) {
Evan Cheng213d2cf2007-05-17 18:45:50 +00002756 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
Evan Cheng8cf723d2006-09-08 01:50:06 +00002757 return false;
2758
Dan Gohman475871a2008-07-27 21:46:04 +00002759 SDValue V1 = N->getOperand(0);
2760 SDValue V2 = N->getOperand(1);
2761 SDValue Mask = N->getOperand(2);
Evan Cheng8cf723d2006-09-08 01:50:06 +00002762 unsigned NumElems = Mask.getNumOperands();
2763 for (unsigned i = 0; i != NumElems; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002764 SDValue Arg = Mask.getOperand(i);
Evan Cheng8cf723d2006-09-08 01:50:06 +00002765 if (Arg.getOpcode() != ISD::UNDEF) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002766 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Cheng8cf723d2006-09-08 01:50:06 +00002767 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2768 return false;
2769 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2770 return false;
2771 }
2772 }
2773 return true;
2774}
2775
Evan Cheng213d2cf2007-05-17 18:45:50 +00002776/// isZeroNode - Returns true if Elt is a constant zero or a floating point
2777/// constant +0.0.
Dan Gohman475871a2008-07-27 21:46:04 +00002778static inline bool isZeroNode(SDValue Elt) {
Evan Cheng213d2cf2007-05-17 18:45:50 +00002779 return ((isa<ConstantSDNode>(Elt) &&
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002780 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
Evan Cheng213d2cf2007-05-17 18:45:50 +00002781 (isa<ConstantFPSDNode>(Elt) &&
Dale Johanneseneaf08942007-08-31 04:03:46 +00002782 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
Evan Cheng213d2cf2007-05-17 18:45:50 +00002783}
2784
2785/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2786/// to an zero vector.
2787static bool isZeroShuffle(SDNode *N) {
2788 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2789 return false;
2790
Dan Gohman475871a2008-07-27 21:46:04 +00002791 SDValue V1 = N->getOperand(0);
2792 SDValue V2 = N->getOperand(1);
2793 SDValue Mask = N->getOperand(2);
Evan Cheng213d2cf2007-05-17 18:45:50 +00002794 unsigned NumElems = Mask.getNumOperands();
2795 for (unsigned i = 0; i != NumElems; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002796 SDValue Arg = Mask.getOperand(i);
Chris Lattner8a594482007-11-25 00:24:49 +00002797 if (Arg.getOpcode() == ISD::UNDEF)
2798 continue;
2799
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002800 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
Chris Lattner8a594482007-11-25 00:24:49 +00002801 if (Idx < NumElems) {
Gabor Greifba36cb52008-08-28 21:40:38 +00002802 unsigned Opc = V1.getNode()->getOpcode();
2803 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
Chris Lattner8a594482007-11-25 00:24:49 +00002804 continue;
2805 if (Opc != ISD::BUILD_VECTOR ||
Gabor Greifba36cb52008-08-28 21:40:38 +00002806 !isZeroNode(V1.getNode()->getOperand(Idx)))
Chris Lattner8a594482007-11-25 00:24:49 +00002807 return false;
2808 } else if (Idx >= NumElems) {
Gabor Greifba36cb52008-08-28 21:40:38 +00002809 unsigned Opc = V2.getNode()->getOpcode();
2810 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
Chris Lattner8a594482007-11-25 00:24:49 +00002811 continue;
2812 if (Opc != ISD::BUILD_VECTOR ||
Gabor Greifba36cb52008-08-28 21:40:38 +00002813 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
Chris Lattner8a594482007-11-25 00:24:49 +00002814 return false;
Evan Cheng213d2cf2007-05-17 18:45:50 +00002815 }
2816 }
2817 return true;
2818}
2819
2820/// getZeroVector - Returns a vector of specified type with all zero elements.
2821///
Dan Gohman475871a2008-07-27 21:46:04 +00002822static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002823 assert(VT.isVector() && "Expected a vector type");
Chris Lattner8a594482007-11-25 00:24:49 +00002824
2825 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2826 // type. This ensures they get CSE'd.
Dan Gohman475871a2008-07-27 21:46:04 +00002827 SDValue Vec;
Duncan Sands83ec4b62008-06-06 12:08:01 +00002828 if (VT.getSizeInBits() == 64) { // MMX
Dan Gohman475871a2008-07-27 21:46:04 +00002829 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
Chris Lattner8a594482007-11-25 00:24:49 +00002830 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
Evan Chengf0df0312008-05-15 08:39:06 +00002831 } else if (HasSSE2) { // SSE2
Dan Gohman475871a2008-07-27 21:46:04 +00002832 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
Chris Lattner8a594482007-11-25 00:24:49 +00002833 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
Evan Chengf0df0312008-05-15 08:39:06 +00002834 } else { // SSE1
Dan Gohman475871a2008-07-27 21:46:04 +00002835 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
Evan Chengf0df0312008-05-15 08:39:06 +00002836 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2837 }
Chris Lattner8a594482007-11-25 00:24:49 +00002838 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
Evan Cheng213d2cf2007-05-17 18:45:50 +00002839}
2840
Chris Lattner8a594482007-11-25 00:24:49 +00002841/// getOnesVector - Returns a vector of specified type with all bits set.
2842///
Dan Gohman475871a2008-07-27 21:46:04 +00002843static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002844 assert(VT.isVector() && "Expected a vector type");
Chris Lattner8a594482007-11-25 00:24:49 +00002845
2846 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2847 // type. This ensures they get CSE'd.
Dan Gohman475871a2008-07-27 21:46:04 +00002848 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2849 SDValue Vec;
Duncan Sands83ec4b62008-06-06 12:08:01 +00002850 if (VT.getSizeInBits() == 64) // MMX
Chris Lattner8a594482007-11-25 00:24:49 +00002851 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2852 else // SSE
2853 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2854 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2855}
2856
2857
Evan Cheng39623da2006-04-20 08:58:49 +00002858/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2859/// that point to V2 points to its first element.
Dan Gohman475871a2008-07-27 21:46:04 +00002860static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
Evan Cheng39623da2006-04-20 08:58:49 +00002861 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2862
2863 bool Changed = false;
Dan Gohman475871a2008-07-27 21:46:04 +00002864 SmallVector<SDValue, 8> MaskVec;
Evan Cheng39623da2006-04-20 08:58:49 +00002865 unsigned NumElems = Mask.getNumOperands();
2866 for (unsigned i = 0; i != NumElems; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00002867 SDValue Arg = Mask.getOperand(i);
Evan Cheng39623da2006-04-20 08:58:49 +00002868 if (Arg.getOpcode() != ISD::UNDEF) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002869 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Evan Cheng39623da2006-04-20 08:58:49 +00002870 if (Val > NumElems) {
2871 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2872 Changed = true;
2873 }
2874 }
2875 MaskVec.push_back(Arg);
2876 }
2877
2878 if (Changed)
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002879 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2880 &MaskVec[0], MaskVec.size());
Evan Cheng39623da2006-04-20 08:58:49 +00002881 return Mask;
2882}
2883
Evan Cheng017dcc62006-04-21 01:05:10 +00002884/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2885/// operation of specified width.
Dan Gohman475871a2008-07-27 21:46:04 +00002886static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002887 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2888 MVT BaseVT = MaskVT.getVectorElementType();
Evan Cheng39623da2006-04-20 08:58:49 +00002889
Dan Gohman475871a2008-07-27 21:46:04 +00002890 SmallVector<SDValue, 8> MaskVec;
Evan Cheng39623da2006-04-20 08:58:49 +00002891 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2892 for (unsigned i = 1; i != NumElems; ++i)
2893 MaskVec.push_back(DAG.getConstant(i, BaseVT));
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002894 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
Evan Cheng39623da2006-04-20 08:58:49 +00002895}
2896
Evan Chengc575ca22006-04-17 20:43:08 +00002897/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2898/// of specified width.
Dan Gohman475871a2008-07-27 21:46:04 +00002899static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002900 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2901 MVT BaseVT = MaskVT.getVectorElementType();
Dan Gohman475871a2008-07-27 21:46:04 +00002902 SmallVector<SDValue, 8> MaskVec;
Evan Chengc575ca22006-04-17 20:43:08 +00002903 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2904 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2905 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2906 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002907 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
Evan Chengc575ca22006-04-17 20:43:08 +00002908}
2909
Evan Cheng39623da2006-04-20 08:58:49 +00002910/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2911/// of specified width.
Dan Gohman475871a2008-07-27 21:46:04 +00002912static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002913 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2914 MVT BaseVT = MaskVT.getVectorElementType();
Evan Cheng39623da2006-04-20 08:58:49 +00002915 unsigned Half = NumElems/2;
Dan Gohman475871a2008-07-27 21:46:04 +00002916 SmallVector<SDValue, 8> MaskVec;
Evan Cheng39623da2006-04-20 08:58:49 +00002917 for (unsigned i = 0; i != Half; ++i) {
2918 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2919 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2920 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002921 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
Evan Cheng39623da2006-04-20 08:58:49 +00002922}
2923
Chris Lattner62098042008-03-09 01:05:04 +00002924/// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2925/// element #0 of a vector with the specified index, leaving the rest of the
2926/// elements in place.
Dan Gohman475871a2008-07-27 21:46:04 +00002927static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
Chris Lattner62098042008-03-09 01:05:04 +00002928 SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002929 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2930 MVT BaseVT = MaskVT.getVectorElementType();
Dan Gohman475871a2008-07-27 21:46:04 +00002931 SmallVector<SDValue, 8> MaskVec;
Chris Lattner62098042008-03-09 01:05:04 +00002932 // Element #0 of the result gets the elt we are replacing.
2933 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2934 for (unsigned i = 1; i != NumElems; ++i)
2935 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2936 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2937}
2938
Evan Cheng0c0f83f2008-04-05 00:30:36 +00002939/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
Dan Gohman475871a2008-07-27 21:46:04 +00002940static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002941 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2942 MVT VT = Op.getValueType();
Evan Cheng0c0f83f2008-04-05 00:30:36 +00002943 if (PVT == VT)
2944 return Op;
Dan Gohman475871a2008-07-27 21:46:04 +00002945 SDValue V1 = Op.getOperand(0);
2946 SDValue Mask = Op.getOperand(2);
Evan Cheng017dcc62006-04-21 01:05:10 +00002947 unsigned NumElems = Mask.getNumOperands();
Evan Cheng0c0f83f2008-04-05 00:30:36 +00002948 // Special handling of v4f32 -> v4i32.
2949 if (VT != MVT::v4f32) {
2950 Mask = getUnpacklMask(NumElems, DAG);
2951 while (NumElems > 4) {
2952 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2953 NumElems >>= 1;
2954 }
Evan Chengf0df0312008-05-15 08:39:06 +00002955 Mask = getZeroVector(MVT::v4i32, true, DAG);
Evan Chengc575ca22006-04-17 20:43:08 +00002956 }
Evan Chengc575ca22006-04-17 20:43:08 +00002957
Evan Cheng0c0f83f2008-04-05 00:30:36 +00002958 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
Dan Gohman475871a2008-07-27 21:46:04 +00002959 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
Evan Cheng0c0f83f2008-04-05 00:30:36 +00002960 DAG.getNode(ISD::UNDEF, PVT), Mask);
Evan Chengc575ca22006-04-17 20:43:08 +00002961 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2962}
2963
Evan Chengba05f722006-04-21 23:03:30 +00002964/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
Chris Lattner8a594482007-11-25 00:24:49 +00002965/// vector of zero or undef vector. This produces a shuffle where the low
2966/// element of V2 is swizzled into the zero/undef vector, landing at element
2967/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
Dan Gohman475871a2008-07-27 21:46:04 +00002968static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
Evan Chengf0df0312008-05-15 08:39:06 +00002969 bool isZero, bool HasSSE2,
2970 SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00002971 MVT VT = V2.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +00002972 SDValue V1 = isZero
Evan Chengf0df0312008-05-15 08:39:06 +00002973 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
Duncan Sands83ec4b62008-06-06 12:08:01 +00002974 unsigned NumElems = V2.getValueType().getVectorNumElements();
2975 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2976 MVT EVT = MaskVT.getVectorElementType();
Dan Gohman475871a2008-07-27 21:46:04 +00002977 SmallVector<SDValue, 16> MaskVec;
Chris Lattner8a594482007-11-25 00:24:49 +00002978 for (unsigned i = 0; i != NumElems; ++i)
2979 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2980 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2981 else
2982 MaskVec.push_back(DAG.getConstant(i, EVT));
Dan Gohman475871a2008-07-27 21:46:04 +00002983 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002984 &MaskVec[0], MaskVec.size());
Evan Chengba05f722006-04-21 23:03:30 +00002985 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
Evan Cheng017dcc62006-04-21 01:05:10 +00002986}
2987
Evan Chengf26ffe92008-05-29 08:22:04 +00002988/// getNumOfConsecutiveZeros - Return the number of elements in a result of
2989/// a shuffle that is zero.
2990static
Dan Gohman475871a2008-07-27 21:46:04 +00002991unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
Evan Chengf26ffe92008-05-29 08:22:04 +00002992 unsigned NumElems, bool Low,
2993 SelectionDAG &DAG) {
2994 unsigned NumZeros = 0;
2995 for (unsigned i = 0; i < NumElems; ++i) {
Evan Chengab262272008-06-25 20:52:59 +00002996 unsigned Index = Low ? i : NumElems-i-1;
Dan Gohman475871a2008-07-27 21:46:04 +00002997 SDValue Idx = Mask.getOperand(Index);
Evan Chengf26ffe92008-05-29 08:22:04 +00002998 if (Idx.getOpcode() == ISD::UNDEF) {
2999 ++NumZeros;
3000 continue;
3001 }
Gabor Greifba36cb52008-08-28 21:40:38 +00003002 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
3003 if (Elt.getNode() && isZeroNode(Elt))
Evan Chengf26ffe92008-05-29 08:22:04 +00003004 ++NumZeros;
3005 else
3006 break;
3007 }
3008 return NumZeros;
3009}
3010
3011/// isVectorShift - Returns true if the shuffle can be implemented as a
3012/// logical left or right shift of a vector.
Dan Gohman475871a2008-07-27 21:46:04 +00003013static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3014 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
Evan Chengf26ffe92008-05-29 08:22:04 +00003015 unsigned NumElems = Mask.getNumOperands();
3016
3017 isLeft = true;
3018 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3019 if (!NumZeros) {
3020 isLeft = false;
3021 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3022 if (!NumZeros)
3023 return false;
3024 }
3025
3026 bool SeenV1 = false;
3027 bool SeenV2 = false;
3028 for (unsigned i = NumZeros; i < NumElems; ++i) {
3029 unsigned Val = isLeft ? (i - NumZeros) : i;
Dan Gohman475871a2008-07-27 21:46:04 +00003030 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
Evan Chengf26ffe92008-05-29 08:22:04 +00003031 if (Idx.getOpcode() == ISD::UNDEF)
3032 continue;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003033 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
Evan Chengf26ffe92008-05-29 08:22:04 +00003034 if (Index < NumElems)
3035 SeenV1 = true;
3036 else {
3037 Index -= NumElems;
3038 SeenV2 = true;
3039 }
3040 if (Index != Val)
3041 return false;
3042 }
3043 if (SeenV1 && SeenV2)
3044 return false;
3045
3046 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3047 ShAmt = NumZeros;
3048 return true;
3049}
3050
3051
Evan Chengc78d3b42006-04-24 18:01:45 +00003052/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3053///
Dan Gohman475871a2008-07-27 21:46:04 +00003054static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
Evan Chengc78d3b42006-04-24 18:01:45 +00003055 unsigned NumNonZero, unsigned NumZero,
Evan Cheng25ab6902006-09-08 06:48:29 +00003056 SelectionDAG &DAG, TargetLowering &TLI) {
Evan Chengc78d3b42006-04-24 18:01:45 +00003057 if (NumNonZero > 8)
Dan Gohman475871a2008-07-27 21:46:04 +00003058 return SDValue();
Evan Chengc78d3b42006-04-24 18:01:45 +00003059
Dan Gohman475871a2008-07-27 21:46:04 +00003060 SDValue V(0, 0);
Evan Chengc78d3b42006-04-24 18:01:45 +00003061 bool First = true;
3062 for (unsigned i = 0; i < 16; ++i) {
3063 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3064 if (ThisIsNonZero && First) {
3065 if (NumZero)
Evan Chengf0df0312008-05-15 08:39:06 +00003066 V = getZeroVector(MVT::v8i16, true, DAG);
Evan Chengc78d3b42006-04-24 18:01:45 +00003067 else
3068 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3069 First = false;
3070 }
3071
3072 if ((i & 1) != 0) {
Dan Gohman475871a2008-07-27 21:46:04 +00003073 SDValue ThisElt(0, 0), LastElt(0, 0);
Evan Chengc78d3b42006-04-24 18:01:45 +00003074 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3075 if (LastIsNonZero) {
3076 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3077 }
3078 if (ThisIsNonZero) {
3079 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3080 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3081 ThisElt, DAG.getConstant(8, MVT::i8));
3082 if (LastIsNonZero)
3083 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3084 } else
3085 ThisElt = LastElt;
3086
Gabor Greifba36cb52008-08-28 21:40:38 +00003087 if (ThisElt.getNode())
Evan Chengc78d3b42006-04-24 18:01:45 +00003088 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
Chris Lattner0bd48932008-01-17 07:00:52 +00003089 DAG.getIntPtrConstant(i/2));
Evan Chengc78d3b42006-04-24 18:01:45 +00003090 }
3091 }
3092
3093 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3094}
3095
Bill Wendlinga348c562007-03-22 18:42:45 +00003096/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
Evan Chengc78d3b42006-04-24 18:01:45 +00003097///
Dan Gohman475871a2008-07-27 21:46:04 +00003098static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
Evan Chengc78d3b42006-04-24 18:01:45 +00003099 unsigned NumNonZero, unsigned NumZero,
Evan Cheng25ab6902006-09-08 06:48:29 +00003100 SelectionDAG &DAG, TargetLowering &TLI) {
Evan Chengc78d3b42006-04-24 18:01:45 +00003101 if (NumNonZero > 4)
Dan Gohman475871a2008-07-27 21:46:04 +00003102 return SDValue();
Evan Chengc78d3b42006-04-24 18:01:45 +00003103
Dan Gohman475871a2008-07-27 21:46:04 +00003104 SDValue V(0, 0);
Evan Chengc78d3b42006-04-24 18:01:45 +00003105 bool First = true;
3106 for (unsigned i = 0; i < 8; ++i) {
3107 bool isNonZero = (NonZeros & (1 << i)) != 0;
3108 if (isNonZero) {
3109 if (First) {
3110 if (NumZero)
Evan Chengf0df0312008-05-15 08:39:06 +00003111 V = getZeroVector(MVT::v8i16, true, DAG);
Evan Chengc78d3b42006-04-24 18:01:45 +00003112 else
3113 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3114 First = false;
3115 }
3116 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
Chris Lattner0bd48932008-01-17 07:00:52 +00003117 DAG.getIntPtrConstant(i));
Evan Chengc78d3b42006-04-24 18:01:45 +00003118 }
3119 }
3120
3121 return V;
3122}
3123
Evan Chengf26ffe92008-05-29 08:22:04 +00003124/// getVShift - Return a vector logical shift node.
3125///
Dan Gohman475871a2008-07-27 21:46:04 +00003126static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
Evan Chengf26ffe92008-05-29 08:22:04 +00003127 unsigned NumBits, SelectionDAG &DAG,
3128 const TargetLowering &TLI) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003129 bool isMMX = VT.getSizeInBits() == 64;
3130 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
Evan Chengf26ffe92008-05-29 08:22:04 +00003131 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3132 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3133 return DAG.getNode(ISD::BIT_CONVERT, VT,
3134 DAG.getNode(Opc, ShVT, SrcOp,
Gabor Greif327ef032008-08-28 23:19:51 +00003135 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
Evan Chengf26ffe92008-05-29 08:22:04 +00003136}
3137
Dan Gohman475871a2008-07-27 21:46:04 +00003138SDValue
3139X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
Chris Lattner8a594482007-11-25 00:24:49 +00003140 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
Gabor Greif327ef032008-08-28 23:19:51 +00003141 if (ISD::isBuildVectorAllZeros(Op.getNode())
3142 || ISD::isBuildVectorAllOnes(Op.getNode())) {
Chris Lattner8a594482007-11-25 00:24:49 +00003143 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3144 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3145 // eliminated on x86-32 hosts.
3146 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3147 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003148
Gabor Greifba36cb52008-08-28 21:40:38 +00003149 if (ISD::isBuildVectorAllOnes(Op.getNode()))
Chris Lattner8a594482007-11-25 00:24:49 +00003150 return getOnesVector(Op.getValueType(), DAG);
Evan Chengf0df0312008-05-15 08:39:06 +00003151 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
Chris Lattner8a594482007-11-25 00:24:49 +00003152 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003153
Duncan Sands83ec4b62008-06-06 12:08:01 +00003154 MVT VT = Op.getValueType();
3155 MVT EVT = VT.getVectorElementType();
3156 unsigned EVTBits = EVT.getSizeInBits();
Evan Cheng0db9fe62006-04-25 20:13:52 +00003157
3158 unsigned NumElems = Op.getNumOperands();
3159 unsigned NumZero = 0;
3160 unsigned NumNonZero = 0;
3161 unsigned NonZeros = 0;
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003162 bool IsAllConstants = true;
Dan Gohman475871a2008-07-27 21:46:04 +00003163 SmallSet<SDValue, 8> Values;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003164 for (unsigned i = 0; i < NumElems; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003165 SDValue Elt = Op.getOperand(i);
Evan Chengdb2d5242007-12-12 06:45:40 +00003166 if (Elt.getOpcode() == ISD::UNDEF)
3167 continue;
3168 Values.insert(Elt);
3169 if (Elt.getOpcode() != ISD::Constant &&
3170 Elt.getOpcode() != ISD::ConstantFP)
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003171 IsAllConstants = false;
Evan Chengdb2d5242007-12-12 06:45:40 +00003172 if (isZeroNode(Elt))
3173 NumZero++;
3174 else {
3175 NonZeros |= (1 << i);
3176 NumNonZero++;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003177 }
3178 }
3179
Dan Gohman7f321562007-06-25 16:23:39 +00003180 if (NumNonZero == 0) {
Chris Lattner8a594482007-11-25 00:24:49 +00003181 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3182 return DAG.getNode(ISD::UNDEF, VT);
Dan Gohman7f321562007-06-25 16:23:39 +00003183 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003184
Chris Lattner67f453a2008-03-09 05:42:06 +00003185 // Special case for single non-zero, non-undef, element.
Evan Chengdb2d5242007-12-12 06:45:40 +00003186 if (NumNonZero == 1 && NumElems <= 4) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00003187 unsigned Idx = CountTrailingZeros_32(NonZeros);
Dan Gohman475871a2008-07-27 21:46:04 +00003188 SDValue Item = Op.getOperand(Idx);
Chris Lattner19f79692008-03-08 22:59:52 +00003189
Chris Lattner62098042008-03-09 01:05:04 +00003190 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3191 // the value are obviously zero, truncate the value to i32 and do the
3192 // insertion that way. Only do this if the value is non-constant or if the
3193 // value is a constant being inserted into element 0. It is cheaper to do
3194 // a constant pool load than it is to do a movd + shuffle.
3195 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3196 (!IsAllConstants || Idx == 0)) {
3197 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3198 // Handle MMX and SSE both.
Duncan Sands83ec4b62008-06-06 12:08:01 +00003199 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3200 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
Chris Lattner62098042008-03-09 01:05:04 +00003201
3202 // Truncate the value (which may itself be a constant) to i32, and
3203 // convert it to a vector with movd (S2V+shuffle to zero extend).
3204 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3205 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
Evan Chengf0df0312008-05-15 08:39:06 +00003206 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3207 Subtarget->hasSSE2(), DAG);
Chris Lattner62098042008-03-09 01:05:04 +00003208
3209 // Now we have our 32-bit value zero extended in the low element of
3210 // a vector. If Idx != 0, swizzle it into place.
3211 if (Idx != 0) {
Dan Gohman475871a2008-07-27 21:46:04 +00003212 SDValue Ops[] = {
Chris Lattner62098042008-03-09 01:05:04 +00003213 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3214 getSwapEltZeroMask(VecElts, Idx, DAG)
3215 };
3216 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3217 }
3218 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3219 }
3220 }
3221
Chris Lattner19f79692008-03-08 22:59:52 +00003222 // If we have a constant or non-constant insertion into the low element of
3223 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3224 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3225 // depending on what the source datatype is. Because we can only get here
3226 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3227 if (Idx == 0 &&
3228 // Don't do this for i64 values on x86-32.
3229 (EVT != MVT::i64 || Subtarget->is64Bit())) {
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003230 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003231 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
Evan Chengf0df0312008-05-15 08:39:06 +00003232 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3233 Subtarget->hasSSE2(), DAG);
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003234 }
Evan Chengf26ffe92008-05-29 08:22:04 +00003235
3236 // Is it a vector logical left shift?
3237 if (NumElems == 2 && Idx == 1 &&
3238 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003239 unsigned NumBits = VT.getSizeInBits();
Evan Chengf26ffe92008-05-29 08:22:04 +00003240 return getVShift(true, VT,
3241 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3242 NumBits/2, DAG, *this);
3243 }
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003244
3245 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
Dan Gohman475871a2008-07-27 21:46:04 +00003246 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00003247
Chris Lattner19f79692008-03-08 22:59:52 +00003248 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3249 // is a non-constant being inserted into an element other than the low one,
3250 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3251 // movd/movss) to move this into the low element, then shuffle it into
3252 // place.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003253 if (EVTBits == 32) {
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003254 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3255
Evan Cheng0db9fe62006-04-25 20:13:52 +00003256 // Turn it into a shuffle of zero and zero-extended scalar to vector.
Evan Chengf0df0312008-05-15 08:39:06 +00003257 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3258 Subtarget->hasSSE2(), DAG);
Duncan Sands83ec4b62008-06-06 12:08:01 +00003259 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3260 MVT MaskEVT = MaskVT.getVectorElementType();
Dan Gohman475871a2008-07-27 21:46:04 +00003261 SmallVector<SDValue, 8> MaskVec;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003262 for (unsigned i = 0; i < NumElems; i++)
3263 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
Dan Gohman475871a2008-07-27 21:46:04 +00003264 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
Chris Lattnerbd564bf2006-08-08 02:23:42 +00003265 &MaskVec[0], MaskVec.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00003266 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3267 DAG.getNode(ISD::UNDEF, VT), Mask);
3268 }
3269 }
3270
Chris Lattner67f453a2008-03-09 05:42:06 +00003271 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3272 if (Values.size() == 1)
Dan Gohman475871a2008-07-27 21:46:04 +00003273 return SDValue();
Chris Lattner67f453a2008-03-09 05:42:06 +00003274
Dan Gohmana3941172007-07-24 22:55:08 +00003275 // A vector full of immediates; various special cases are already
3276 // handled, so this is best done with a single constant-pool load.
Chris Lattnerc9517fb2008-03-08 22:48:29 +00003277 if (IsAllConstants)
Dan Gohman475871a2008-07-27 21:46:04 +00003278 return SDValue();
Dan Gohmana3941172007-07-24 22:55:08 +00003279
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00003280 // Let legalizer expand 2-wide build_vectors.
Evan Cheng7e2ff772008-05-08 00:57:18 +00003281 if (EVTBits == 64) {
3282 if (NumNonZero == 1) {
3283 // One half is zero or undef.
3284 unsigned Idx = CountTrailingZeros_32(NonZeros);
Dan Gohman475871a2008-07-27 21:46:04 +00003285 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
Evan Cheng7e2ff772008-05-08 00:57:18 +00003286 Op.getOperand(Idx));
Evan Chengf0df0312008-05-15 08:39:06 +00003287 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3288 Subtarget->hasSSE2(), DAG);
Evan Cheng7e2ff772008-05-08 00:57:18 +00003289 }
Dan Gohman475871a2008-07-27 21:46:04 +00003290 return SDValue();
Evan Cheng7e2ff772008-05-08 00:57:18 +00003291 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003292
3293 // If element VT is < 32 bits, convert it to inserts into a zero vector.
Bill Wendling826f36f2007-03-28 00:57:11 +00003294 if (EVTBits == 8 && NumElems == 16) {
Dan Gohman475871a2008-07-27 21:46:04 +00003295 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
Evan Cheng25ab6902006-09-08 06:48:29 +00003296 *this);
Gabor Greifba36cb52008-08-28 21:40:38 +00003297 if (V.getNode()) return V;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003298 }
3299
Bill Wendling826f36f2007-03-28 00:57:11 +00003300 if (EVTBits == 16 && NumElems == 8) {
Dan Gohman475871a2008-07-27 21:46:04 +00003301 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
Evan Cheng25ab6902006-09-08 06:48:29 +00003302 *this);
Gabor Greifba36cb52008-08-28 21:40:38 +00003303 if (V.getNode()) return V;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003304 }
3305
3306 // If element VT is == 32 bits, turn it into a number of shuffles.
Dan Gohman475871a2008-07-27 21:46:04 +00003307 SmallVector<SDValue, 8> V;
Chris Lattner5a88b832007-02-25 07:10:00 +00003308 V.resize(NumElems);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003309 if (NumElems == 4 && NumZero > 0) {
3310 for (unsigned i = 0; i < 4; ++i) {
3311 bool isZero = !(NonZeros & (1 << i));
3312 if (isZero)
Evan Chengf0df0312008-05-15 08:39:06 +00003313 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003314 else
3315 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3316 }
3317
3318 for (unsigned i = 0; i < 2; ++i) {
3319 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3320 default: break;
3321 case 0:
3322 V[i] = V[i*2]; // Must be a zero vector.
3323 break;
3324 case 1:
3325 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3326 getMOVLMask(NumElems, DAG));
3327 break;
3328 case 2:
3329 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3330 getMOVLMask(NumElems, DAG));
3331 break;
3332 case 3:
3333 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3334 getUnpacklMask(NumElems, DAG));
3335 break;
3336 }
3337 }
3338
Duncan Sands83ec4b62008-06-06 12:08:01 +00003339 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3340 MVT EVT = MaskVT.getVectorElementType();
Dan Gohman475871a2008-07-27 21:46:04 +00003341 SmallVector<SDValue, 8> MaskVec;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003342 bool Reverse = (NonZeros & 0x3) == 2;
3343 for (unsigned i = 0; i < 2; ++i)
3344 if (Reverse)
3345 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3346 else
3347 MaskVec.push_back(DAG.getConstant(i, EVT));
3348 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3349 for (unsigned i = 0; i < 2; ++i)
3350 if (Reverse)
3351 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3352 else
3353 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
Dan Gohman475871a2008-07-27 21:46:04 +00003354 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
Chris Lattnere2199452006-08-11 17:38:39 +00003355 &MaskVec[0], MaskVec.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00003356 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3357 }
3358
3359 if (Values.size() > 2) {
3360 // Expand into a number of unpckl*.
3361 // e.g. for v4f32
3362 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3363 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3364 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
Dan Gohman475871a2008-07-27 21:46:04 +00003365 SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003366 for (unsigned i = 0; i < NumElems; ++i)
3367 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3368 NumElems >>= 1;
3369 while (NumElems != 0) {
3370 for (unsigned i = 0; i < NumElems; ++i)
3371 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3372 UnpckMask);
3373 NumElems >>= 1;
3374 }
3375 return V[0];
3376 }
3377
Dan Gohman475871a2008-07-27 21:46:04 +00003378 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00003379}
3380
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003381static
Dan Gohman475871a2008-07-27 21:46:04 +00003382SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
Bill Wendlinge85dc492008-08-21 22:35:37 +00003383 SDValue PermMask, SelectionDAG &DAG,
3384 TargetLowering &TLI) {
Dan Gohman475871a2008-07-27 21:46:04 +00003385 SDValue NewV;
Duncan Sands83ec4b62008-06-06 12:08:01 +00003386 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3387 MVT MaskEVT = MaskVT.getVectorElementType();
3388 MVT PtrVT = TLI.getPointerTy();
Gabor Greifba36cb52008-08-28 21:40:38 +00003389 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3390 PermMask.getNode()->op_end());
Evan Cheng14b32e12007-12-11 01:46:18 +00003391
3392 // First record which half of which vector the low elements come from.
3393 SmallVector<unsigned, 4> LowQuad(4);
3394 for (unsigned i = 0; i < 4; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003395 SDValue Elt = MaskElts[i];
Evan Cheng14b32e12007-12-11 01:46:18 +00003396 if (Elt.getOpcode() == ISD::UNDEF)
3397 continue;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003398 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00003399 int QuadIdx = EltIdx / 4;
3400 ++LowQuad[QuadIdx];
3401 }
Bill Wendlinge85dc492008-08-21 22:35:37 +00003402
Evan Cheng14b32e12007-12-11 01:46:18 +00003403 int BestLowQuad = -1;
3404 unsigned MaxQuad = 1;
3405 for (unsigned i = 0; i < 4; ++i) {
3406 if (LowQuad[i] > MaxQuad) {
3407 BestLowQuad = i;
3408 MaxQuad = LowQuad[i];
3409 }
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003410 }
3411
Evan Cheng14b32e12007-12-11 01:46:18 +00003412 // Record which half of which vector the high elements come from.
3413 SmallVector<unsigned, 4> HighQuad(4);
3414 for (unsigned i = 4; i < 8; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003415 SDValue Elt = MaskElts[i];
Evan Cheng14b32e12007-12-11 01:46:18 +00003416 if (Elt.getOpcode() == ISD::UNDEF)
3417 continue;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003418 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00003419 int QuadIdx = EltIdx / 4;
3420 ++HighQuad[QuadIdx];
3421 }
Bill Wendlinge85dc492008-08-21 22:35:37 +00003422
Evan Cheng14b32e12007-12-11 01:46:18 +00003423 int BestHighQuad = -1;
3424 MaxQuad = 1;
3425 for (unsigned i = 0; i < 4; ++i) {
3426 if (HighQuad[i] > MaxQuad) {
3427 BestHighQuad = i;
3428 MaxQuad = HighQuad[i];
3429 }
3430 }
3431
3432 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3433 if (BestLowQuad != -1 || BestHighQuad != -1) {
3434 // First sort the 4 chunks in order using shufpd.
Dan Gohman475871a2008-07-27 21:46:04 +00003435 SmallVector<SDValue, 8> MaskVec;
Bill Wendlinge85dc492008-08-21 22:35:37 +00003436
Evan Cheng14b32e12007-12-11 01:46:18 +00003437 if (BestLowQuad != -1)
3438 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3439 else
3440 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
Bill Wendlinge85dc492008-08-21 22:35:37 +00003441
Evan Cheng14b32e12007-12-11 01:46:18 +00003442 if (BestHighQuad != -1)
3443 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3444 else
3445 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
Bill Wendlinge85dc492008-08-21 22:35:37 +00003446
Dan Gohman475871a2008-07-27 21:46:04 +00003447 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
Evan Cheng14b32e12007-12-11 01:46:18 +00003448 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3449 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3450 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3451 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3452
3453 // Now sort high and low parts separately.
3454 BitVector InOrder(8);
3455 if (BestLowQuad != -1) {
3456 // Sort lower half in order using PSHUFLW.
3457 MaskVec.clear();
3458 bool AnyOutOrder = false;
Bill Wendlinge85dc492008-08-21 22:35:37 +00003459
Evan Cheng14b32e12007-12-11 01:46:18 +00003460 for (unsigned i = 0; i != 4; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003461 SDValue Elt = MaskElts[i];
Evan Cheng14b32e12007-12-11 01:46:18 +00003462 if (Elt.getOpcode() == ISD::UNDEF) {
3463 MaskVec.push_back(Elt);
3464 InOrder.set(i);
3465 } else {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003466 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00003467 if (EltIdx != i)
3468 AnyOutOrder = true;
Bill Wendlinge85dc492008-08-21 22:35:37 +00003469
Evan Cheng14b32e12007-12-11 01:46:18 +00003470 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
Bill Wendlinge85dc492008-08-21 22:35:37 +00003471
Evan Cheng14b32e12007-12-11 01:46:18 +00003472 // If this element is in the right place after this shuffle, then
3473 // remember it.
3474 if ((int)(EltIdx / 4) == BestLowQuad)
3475 InOrder.set(i);
3476 }
3477 }
3478 if (AnyOutOrder) {
3479 for (unsigned i = 4; i != 8; ++i)
3480 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
Dan Gohman475871a2008-07-27 21:46:04 +00003481 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
Evan Cheng14b32e12007-12-11 01:46:18 +00003482 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3483 }
3484 }
3485
3486 if (BestHighQuad != -1) {
3487 // Sort high half in order using PSHUFHW if possible.
3488 MaskVec.clear();
Bill Wendlinge85dc492008-08-21 22:35:37 +00003489
Evan Cheng14b32e12007-12-11 01:46:18 +00003490 for (unsigned i = 0; i != 4; ++i)
3491 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
Bill Wendlinge85dc492008-08-21 22:35:37 +00003492
Evan Cheng14b32e12007-12-11 01:46:18 +00003493 bool AnyOutOrder = false;
3494 for (unsigned i = 4; i != 8; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003495 SDValue Elt = MaskElts[i];
Evan Cheng14b32e12007-12-11 01:46:18 +00003496 if (Elt.getOpcode() == ISD::UNDEF) {
3497 MaskVec.push_back(Elt);
3498 InOrder.set(i);
3499 } else {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003500 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00003501 if (EltIdx != i)
3502 AnyOutOrder = true;
Bill Wendlinge85dc492008-08-21 22:35:37 +00003503
Evan Cheng14b32e12007-12-11 01:46:18 +00003504 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
Bill Wendlinge85dc492008-08-21 22:35:37 +00003505
Evan Cheng14b32e12007-12-11 01:46:18 +00003506 // If this element is in the right place after this shuffle, then
3507 // remember it.
3508 if ((int)(EltIdx / 4) == BestHighQuad)
3509 InOrder.set(i);
3510 }
3511 }
Bill Wendlinge85dc492008-08-21 22:35:37 +00003512
Evan Cheng14b32e12007-12-11 01:46:18 +00003513 if (AnyOutOrder) {
Dan Gohman475871a2008-07-27 21:46:04 +00003514 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
Evan Cheng14b32e12007-12-11 01:46:18 +00003515 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3516 }
3517 }
3518
3519 // The other elements are put in the right place using pextrw and pinsrw.
3520 for (unsigned i = 0; i != 8; ++i) {
3521 if (InOrder[i])
3522 continue;
Dan Gohman475871a2008-07-27 21:46:04 +00003523 SDValue Elt = MaskElts[i];
Bill Wendlingae0218c2008-08-21 22:36:36 +00003524 if (Elt.getOpcode() == ISD::UNDEF)
3525 continue;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003526 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +00003527 SDValue ExtOp = (EltIdx < 8)
Evan Cheng14b32e12007-12-11 01:46:18 +00003528 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3529 DAG.getConstant(EltIdx, PtrVT))
3530 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3531 DAG.getConstant(EltIdx - 8, PtrVT));
3532 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3533 DAG.getConstant(i, PtrVT));
3534 }
Bill Wendlinge85dc492008-08-21 22:35:37 +00003535
Evan Cheng14b32e12007-12-11 01:46:18 +00003536 return NewV;
3537 }
3538
Bill Wendlinge85dc492008-08-21 22:35:37 +00003539 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as
3540 // few as possible. First, let's find out how many elements are already in the
3541 // right order.
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003542 unsigned V1InOrder = 0;
3543 unsigned V1FromV1 = 0;
3544 unsigned V2InOrder = 0;
3545 unsigned V2FromV2 = 0;
Dan Gohman475871a2008-07-27 21:46:04 +00003546 SmallVector<SDValue, 8> V1Elts;
3547 SmallVector<SDValue, 8> V2Elts;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003548 for (unsigned i = 0; i < 8; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003549 SDValue Elt = MaskElts[i];
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003550 if (Elt.getOpcode() == ISD::UNDEF) {
Evan Cheng14b32e12007-12-11 01:46:18 +00003551 V1Elts.push_back(Elt);
3552 V2Elts.push_back(Elt);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003553 ++V1InOrder;
3554 ++V2InOrder;
Evan Cheng14b32e12007-12-11 01:46:18 +00003555 continue;
3556 }
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003557 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00003558 if (EltIdx == i) {
3559 V1Elts.push_back(Elt);
3560 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3561 ++V1InOrder;
3562 } else if (EltIdx == i+8) {
3563 V1Elts.push_back(Elt);
3564 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3565 ++V2InOrder;
3566 } else if (EltIdx < 8) {
3567 V1Elts.push_back(Elt);
3568 ++V1FromV1;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003569 } else {
Evan Cheng14b32e12007-12-11 01:46:18 +00003570 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3571 ++V2FromV2;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003572 }
3573 }
3574
3575 if (V2InOrder > V1InOrder) {
3576 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3577 std::swap(V1, V2);
3578 std::swap(V1Elts, V2Elts);
3579 std::swap(V1FromV1, V2FromV2);
3580 }
3581
Evan Cheng14b32e12007-12-11 01:46:18 +00003582 if ((V1FromV1 + V1InOrder) != 8) {
3583 // Some elements are from V2.
3584 if (V1FromV1) {
3585 // If there are elements that are from V1 but out of place,
3586 // then first sort them in place
Dan Gohman475871a2008-07-27 21:46:04 +00003587 SmallVector<SDValue, 8> MaskVec;
Evan Cheng14b32e12007-12-11 01:46:18 +00003588 for (unsigned i = 0; i < 8; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003589 SDValue Elt = V1Elts[i];
Evan Cheng14b32e12007-12-11 01:46:18 +00003590 if (Elt.getOpcode() == ISD::UNDEF) {
3591 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3592 continue;
3593 }
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003594 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00003595 if (EltIdx >= 8)
3596 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3597 else
3598 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3599 }
Dan Gohman475871a2008-07-27 21:46:04 +00003600 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
Evan Cheng14b32e12007-12-11 01:46:18 +00003601 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003602 }
Evan Cheng14b32e12007-12-11 01:46:18 +00003603
3604 NewV = V1;
3605 for (unsigned i = 0; i < 8; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003606 SDValue Elt = V1Elts[i];
Evan Cheng14b32e12007-12-11 01:46:18 +00003607 if (Elt.getOpcode() == ISD::UNDEF)
3608 continue;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003609 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00003610 if (EltIdx < 8)
3611 continue;
Dan Gohman475871a2008-07-27 21:46:04 +00003612 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
Evan Cheng14b32e12007-12-11 01:46:18 +00003613 DAG.getConstant(EltIdx - 8, PtrVT));
3614 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3615 DAG.getConstant(i, PtrVT));
3616 }
3617 return NewV;
3618 } else {
3619 // All elements are from V1.
3620 NewV = V1;
3621 for (unsigned i = 0; i < 8; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003622 SDValue Elt = V1Elts[i];
Evan Cheng14b32e12007-12-11 01:46:18 +00003623 if (Elt.getOpcode() == ISD::UNDEF)
3624 continue;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003625 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +00003626 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
Evan Cheng14b32e12007-12-11 01:46:18 +00003627 DAG.getConstant(EltIdx, PtrVT));
3628 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3629 DAG.getConstant(i, PtrVT));
3630 }
3631 return NewV;
3632 }
3633}
3634
Evan Cheng7a831ce2007-12-15 03:00:47 +00003635/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3636/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3637/// done when every pair / quad of shuffle mask elements point to elements in
3638/// the right sequence. e.g.
Evan Cheng14b32e12007-12-11 01:46:18 +00003639/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3640static
Dan Gohman475871a2008-07-27 21:46:04 +00003641SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
Duncan Sands83ec4b62008-06-06 12:08:01 +00003642 MVT VT,
Dan Gohman475871a2008-07-27 21:46:04 +00003643 SDValue PermMask, SelectionDAG &DAG,
Evan Cheng14b32e12007-12-11 01:46:18 +00003644 TargetLowering &TLI) {
3645 unsigned NumElems = PermMask.getNumOperands();
Evan Cheng7a831ce2007-12-15 03:00:47 +00003646 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
Duncan Sands83ec4b62008-06-06 12:08:01 +00003647 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
Duncan Sandsd038e042008-07-21 10:20:31 +00003648 MVT MaskEltVT = MaskVT.getVectorElementType();
Duncan Sands83ec4b62008-06-06 12:08:01 +00003649 MVT NewVT = MaskVT;
3650 switch (VT.getSimpleVT()) {
3651 default: assert(false && "Unexpected!");
Evan Cheng7a831ce2007-12-15 03:00:47 +00003652 case MVT::v4f32: NewVT = MVT::v2f64; break;
3653 case MVT::v4i32: NewVT = MVT::v2i64; break;
3654 case MVT::v8i16: NewVT = MVT::v4i32; break;
3655 case MVT::v16i8: NewVT = MVT::v4i32; break;
Evan Cheng7a831ce2007-12-15 03:00:47 +00003656 }
3657
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00003658 if (NewWidth == 2) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00003659 if (VT.isInteger())
Evan Cheng7a831ce2007-12-15 03:00:47 +00003660 NewVT = MVT::v2i64;
3661 else
3662 NewVT = MVT::v2f64;
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00003663 }
Evan Cheng7a831ce2007-12-15 03:00:47 +00003664 unsigned Scale = NumElems / NewWidth;
Dan Gohman475871a2008-07-27 21:46:04 +00003665 SmallVector<SDValue, 8> MaskVec;
Evan Cheng14b32e12007-12-11 01:46:18 +00003666 for (unsigned i = 0; i < NumElems; i += Scale) {
3667 unsigned StartIdx = ~0U;
3668 for (unsigned j = 0; j < Scale; ++j) {
Dan Gohman475871a2008-07-27 21:46:04 +00003669 SDValue Elt = PermMask.getOperand(i+j);
Evan Cheng14b32e12007-12-11 01:46:18 +00003670 if (Elt.getOpcode() == ISD::UNDEF)
3671 continue;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003672 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00003673 if (StartIdx == ~0U)
3674 StartIdx = EltIdx - (EltIdx % Scale);
3675 if (EltIdx != StartIdx + j)
Dan Gohman475871a2008-07-27 21:46:04 +00003676 return SDValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00003677 }
3678 if (StartIdx == ~0U)
Duncan Sandsd038e042008-07-21 10:20:31 +00003679 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
Evan Cheng14b32e12007-12-11 01:46:18 +00003680 else
Duncan Sandsd038e042008-07-21 10:20:31 +00003681 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003682 }
3683
Evan Cheng7a831ce2007-12-15 03:00:47 +00003684 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3685 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3686 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3687 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3688 &MaskVec[0], MaskVec.size()));
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003689}
3690
Evan Chengd880b972008-05-09 21:53:03 +00003691/// getVZextMovL - Return a zero-extending vector move low node.
Evan Cheng7e2ff772008-05-08 00:57:18 +00003692///
Dan Gohman475871a2008-07-27 21:46:04 +00003693static SDValue getVZextMovL(MVT VT, MVT OpVT,
3694 SDValue SrcOp, SelectionDAG &DAG,
Duncan Sands83ec4b62008-06-06 12:08:01 +00003695 const X86Subtarget *Subtarget) {
Evan Cheng7e2ff772008-05-08 00:57:18 +00003696 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3697 LoadSDNode *LD = NULL;
Gabor Greifba36cb52008-08-28 21:40:38 +00003698 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
Evan Cheng7e2ff772008-05-08 00:57:18 +00003699 LD = dyn_cast<LoadSDNode>(SrcOp);
3700 if (!LD) {
3701 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3702 // instead.
Duncan Sands83ec4b62008-06-06 12:08:01 +00003703 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
Evan Cheng7e2ff772008-05-08 00:57:18 +00003704 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3705 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3706 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3707 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3708 // PR2108
3709 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3710 return DAG.getNode(ISD::BIT_CONVERT, VT,
Evan Chengd880b972008-05-09 21:53:03 +00003711 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
Evan Cheng7e2ff772008-05-08 00:57:18 +00003712 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
Gabor Greif327ef032008-08-28 23:19:51 +00003713 SrcOp.getOperand(0)
3714 .getOperand(0))));
Evan Cheng7e2ff772008-05-08 00:57:18 +00003715 }
3716 }
3717 }
3718
3719 return DAG.getNode(ISD::BIT_CONVERT, VT,
Evan Chengd880b972008-05-09 21:53:03 +00003720 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
Evan Cheng7e2ff772008-05-08 00:57:18 +00003721 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3722}
3723
Evan Chengace3c172008-07-22 21:13:36 +00003724/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3725/// shuffles.
Dan Gohman475871a2008-07-27 21:46:04 +00003726static SDValue
3727LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
3728 SDValue PermMask, MVT VT, SelectionDAG &DAG) {
Evan Chengace3c172008-07-22 21:13:36 +00003729 MVT MaskVT = PermMask.getValueType();
3730 MVT MaskEVT = MaskVT.getVectorElementType();
3731 SmallVector<std::pair<int, int>, 8> Locs;
Rafael Espindola833a9902008-08-28 18:32:53 +00003732 Locs.resize(4);
Dan Gohman475871a2008-07-27 21:46:04 +00003733 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
Evan Chengace3c172008-07-22 21:13:36 +00003734 unsigned NumHi = 0;
3735 unsigned NumLo = 0;
Evan Chengace3c172008-07-22 21:13:36 +00003736 for (unsigned i = 0; i != 4; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00003737 SDValue Elt = PermMask.getOperand(i);
Evan Chengace3c172008-07-22 21:13:36 +00003738 if (Elt.getOpcode() == ISD::UNDEF) {
3739 Locs[i] = std::make_pair(-1, -1);
3740 } else {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003741 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
Dan Gohmand0859942008-08-04 23:09:15 +00003742 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
Evan Chengace3c172008-07-22 21:13:36 +00003743 if (Val < 4) {
3744 Locs[i] = std::make_pair(0, NumLo);
3745 Mask1[NumLo] = Elt;
3746 NumLo++;
3747 } else {
3748 Locs[i] = std::make_pair(1, NumHi);
3749 if (2+NumHi < 4)
3750 Mask1[2+NumHi] = Elt;
3751 NumHi++;
3752 }
3753 }
3754 }
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003755
Evan Chengace3c172008-07-22 21:13:36 +00003756 if (NumLo <= 2 && NumHi <= 2) {
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003757 // If no more than two elements come from either vector. This can be
3758 // implemented with two shuffles. First shuffle gather the elements.
3759 // The second shuffle, which takes the first shuffle as both of its
3760 // vector operands, put the elements into the right order.
Evan Chengace3c172008-07-22 21:13:36 +00003761 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3762 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3763 &Mask1[0], Mask1.size()));
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003764
Dan Gohman475871a2008-07-27 21:46:04 +00003765 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
Evan Chengace3c172008-07-22 21:13:36 +00003766 for (unsigned i = 0; i != 4; ++i) {
3767 if (Locs[i].first == -1)
3768 continue;
3769 else {
3770 unsigned Idx = (i < 2) ? 0 : 4;
3771 Idx += Locs[i].first * 2 + Locs[i].second;
3772 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3773 }
3774 }
3775
3776 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3777 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3778 &Mask2[0], Mask2.size()));
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003779 } else if (NumLo == 3 || NumHi == 3) {
3780 // Otherwise, we must have three elements from one vector, call it X, and
3781 // one element from the other, call it Y. First, use a shufps to build an
3782 // intermediate vector with the one element from Y and the element from X
3783 // that will be in the same half in the final destination (the indexes don't
3784 // matter). Then, use a shufps to build the final vector, taking the half
3785 // containing the element from Y from the intermediate, and the other half
3786 // from X.
3787 if (NumHi == 3) {
3788 // Normalize it so the 3 elements come from V1.
3789 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3790 std::swap(V1, V2);
3791 }
3792
3793 // Find the element from V2.
3794 unsigned HiIndex;
3795 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
Dan Gohman475871a2008-07-27 21:46:04 +00003796 SDValue Elt = PermMask.getOperand(HiIndex);
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003797 if (Elt.getOpcode() == ISD::UNDEF)
3798 continue;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003799 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003800 if (Val >= 4)
3801 break;
3802 }
3803
3804 Mask1[0] = PermMask.getOperand(HiIndex);
3805 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT);
3806 Mask1[2] = PermMask.getOperand(HiIndex^1);
3807 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT);
3808 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3809 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3810
3811 if (HiIndex >= 2) {
3812 Mask1[0] = PermMask.getOperand(0);
3813 Mask1[1] = PermMask.getOperand(1);
3814 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
3815 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
3816 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3817 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3818 } else {
3819 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
3820 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
3821 Mask1[2] = PermMask.getOperand(2);
3822 Mask1[3] = PermMask.getOperand(3);
3823 if (Mask1[2].getOpcode() != ISD::UNDEF)
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003824 Mask1[2] =
3825 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
3826 MaskEVT);
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003827 if (Mask1[3].getOpcode() != ISD::UNDEF)
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003828 Mask1[3] =
3829 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
3830 MaskEVT);
Evan Cheng5e6ebaf2008-07-23 00:22:17 +00003831 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
3832 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3833 }
Evan Chengace3c172008-07-22 21:13:36 +00003834 }
3835
3836 // Break it into (shuffle shuffle_hi, shuffle_lo).
3837 Locs.clear();
Dan Gohman475871a2008-07-27 21:46:04 +00003838 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3839 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3840 SmallVector<SDValue,8> *MaskPtr = &LoMask;
Evan Chengace3c172008-07-22 21:13:36 +00003841 unsigned MaskIdx = 0;
3842 unsigned LoIdx = 0;
3843 unsigned HiIdx = 2;
3844 for (unsigned i = 0; i != 4; ++i) {
3845 if (i == 2) {
3846 MaskPtr = &HiMask;
3847 MaskIdx = 1;
3848 LoIdx = 0;
3849 HiIdx = 2;
3850 }
Dan Gohman475871a2008-07-27 21:46:04 +00003851 SDValue Elt = PermMask.getOperand(i);
Evan Chengace3c172008-07-22 21:13:36 +00003852 if (Elt.getOpcode() == ISD::UNDEF) {
3853 Locs[i] = std::make_pair(-1, -1);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003854 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
Evan Chengace3c172008-07-22 21:13:36 +00003855 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3856 (*MaskPtr)[LoIdx] = Elt;
3857 LoIdx++;
3858 } else {
3859 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3860 (*MaskPtr)[HiIdx] = Elt;
3861 HiIdx++;
3862 }
3863 }
3864
Dan Gohman475871a2008-07-27 21:46:04 +00003865 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
Evan Chengace3c172008-07-22 21:13:36 +00003866 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3867 &LoMask[0], LoMask.size()));
Dan Gohman475871a2008-07-27 21:46:04 +00003868 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
Evan Chengace3c172008-07-22 21:13:36 +00003869 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3870 &HiMask[0], HiMask.size()));
Dan Gohman475871a2008-07-27 21:46:04 +00003871 SmallVector<SDValue, 8> MaskOps;
Evan Chengace3c172008-07-22 21:13:36 +00003872 for (unsigned i = 0; i != 4; ++i) {
3873 if (Locs[i].first == -1) {
3874 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3875 } else {
3876 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
3877 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3878 }
3879 }
3880 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3881 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3882 &MaskOps[0], MaskOps.size()));
3883}
3884
Dan Gohman475871a2008-07-27 21:46:04 +00003885SDValue
3886X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3887 SDValue V1 = Op.getOperand(0);
3888 SDValue V2 = Op.getOperand(1);
3889 SDValue PermMask = Op.getOperand(2);
Duncan Sands83ec4b62008-06-06 12:08:01 +00003890 MVT VT = Op.getValueType();
Evan Cheng0db9fe62006-04-25 20:13:52 +00003891 unsigned NumElems = PermMask.getNumOperands();
Duncan Sands83ec4b62008-06-06 12:08:01 +00003892 bool isMMX = VT.getSizeInBits() == 64;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003893 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3894 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
Evan Chengd9b8e402006-10-16 06:36:00 +00003895 bool V1IsSplat = false;
3896 bool V2IsSplat = false;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003897
Gabor Greifba36cb52008-08-28 21:40:38 +00003898 if (isUndefShuffle(Op.getNode()))
Evan Cheng8cf723d2006-09-08 01:50:06 +00003899 return DAG.getNode(ISD::UNDEF, VT);
3900
Gabor Greifba36cb52008-08-28 21:40:38 +00003901 if (isZeroShuffle(Op.getNode()))
Evan Chengf0df0312008-05-15 08:39:06 +00003902 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
Evan Cheng213d2cf2007-05-17 18:45:50 +00003903
Gabor Greifba36cb52008-08-28 21:40:38 +00003904 if (isIdentityMask(PermMask.getNode()))
Evan Cheng49892af2007-06-19 00:02:56 +00003905 return V1;
Gabor Greifba36cb52008-08-28 21:40:38 +00003906 else if (isIdentityMask(PermMask.getNode(), true))
Evan Cheng49892af2007-06-19 00:02:56 +00003907 return V2;
3908
Gabor Greifba36cb52008-08-28 21:40:38 +00003909 if (isSplatMask(PermMask.getNode())) {
Evan Cheng0c0f83f2008-04-05 00:30:36 +00003910 if (isMMX || NumElems < 4) return Op;
3911 // Promote it to a v4{if}32 splat.
3912 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
Evan Cheng0db9fe62006-04-25 20:13:52 +00003913 }
3914
Evan Cheng7a831ce2007-12-15 03:00:47 +00003915 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3916 // do it!
3917 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
Dan Gohman475871a2008-07-27 21:46:04 +00003918 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
Gabor Greifba36cb52008-08-28 21:40:38 +00003919 if (NewOp.getNode())
Evan Cheng7a831ce2007-12-15 03:00:47 +00003920 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3921 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3922 // FIXME: Figure out a cleaner way to do this.
3923 // Try to make use of movq to zero out the top part.
Gabor Greifba36cb52008-08-28 21:40:38 +00003924 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
Dan Gohman475871a2008-07-27 21:46:04 +00003925 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
Evan Cheng7e2ff772008-05-08 00:57:18 +00003926 DAG, *this);
Gabor Greifba36cb52008-08-28 21:40:38 +00003927 if (NewOp.getNode()) {
Dan Gohman475871a2008-07-27 21:46:04 +00003928 SDValue NewV1 = NewOp.getOperand(0);
3929 SDValue NewV2 = NewOp.getOperand(1);
3930 SDValue NewMask = NewOp.getOperand(2);
Gabor Greifba36cb52008-08-28 21:40:38 +00003931 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
Evan Cheng7a831ce2007-12-15 03:00:47 +00003932 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
Evan Chengd880b972008-05-09 21:53:03 +00003933 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
Evan Cheng7a831ce2007-12-15 03:00:47 +00003934 }
3935 }
Gabor Greifba36cb52008-08-28 21:40:38 +00003936 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
Dan Gohman475871a2008-07-27 21:46:04 +00003937 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
Evan Cheng7e2ff772008-05-08 00:57:18 +00003938 DAG, *this);
Gabor Greifba36cb52008-08-28 21:40:38 +00003939 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
Evan Chengd880b972008-05-09 21:53:03 +00003940 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
Evan Cheng7e2ff772008-05-08 00:57:18 +00003941 DAG, Subtarget);
Evan Cheng7a831ce2007-12-15 03:00:47 +00003942 }
3943 }
3944
Evan Chengf26ffe92008-05-29 08:22:04 +00003945 // Check if this can be converted into a logical shift.
3946 bool isLeft = false;
3947 unsigned ShAmt = 0;
Dan Gohman475871a2008-07-27 21:46:04 +00003948 SDValue ShVal;
Evan Chengf26ffe92008-05-29 08:22:04 +00003949 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
3950 if (isShift && ShVal.hasOneUse()) {
3951 // If the shifted value has multiple uses, it may be cheaper to use
3952 // v_set0 + movlhps or movhlps, etc.
Duncan Sands83ec4b62008-06-06 12:08:01 +00003953 MVT EVT = VT.getVectorElementType();
3954 ShAmt *= EVT.getSizeInBits();
Evan Chengf26ffe92008-05-29 08:22:04 +00003955 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3956 }
3957
Gabor Greifba36cb52008-08-28 21:40:38 +00003958 if (X86::isMOVLMask(PermMask.getNode())) {
Evan Cheng7e2ff772008-05-08 00:57:18 +00003959 if (V1IsUndef)
3960 return V2;
Gabor Greifba36cb52008-08-28 21:40:38 +00003961 if (ISD::isBuildVectorAllZeros(V1.getNode()))
Evan Chengd880b972008-05-09 21:53:03 +00003962 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
Nate Begemanfb8ead02008-07-25 19:05:58 +00003963 if (!isMMX)
3964 return Op;
Evan Cheng7e2ff772008-05-08 00:57:18 +00003965 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00003966
Gabor Greifba36cb52008-08-28 21:40:38 +00003967 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
3968 X86::isMOVSLDUPMask(PermMask.getNode()) ||
3969 X86::isMOVHLPSMask(PermMask.getNode()) ||
3970 X86::isMOVHPMask(PermMask.getNode()) ||
3971 X86::isMOVLPMask(PermMask.getNode())))
Evan Cheng9bbbb982006-10-25 20:48:19 +00003972 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003973
Gabor Greifba36cb52008-08-28 21:40:38 +00003974 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
3975 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
Evan Cheng9eca5e82006-10-25 21:49:50 +00003976 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003977
Evan Chengf26ffe92008-05-29 08:22:04 +00003978 if (isShift) {
3979 // No better options. Use a vshl / vsrl.
Duncan Sands83ec4b62008-06-06 12:08:01 +00003980 MVT EVT = VT.getVectorElementType();
3981 ShAmt *= EVT.getSizeInBits();
Evan Chengf26ffe92008-05-29 08:22:04 +00003982 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3983 }
3984
Evan Cheng9eca5e82006-10-25 21:49:50 +00003985 bool Commuted = false;
Chris Lattner8a594482007-11-25 00:24:49 +00003986 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3987 // 1,1,1,1 -> v8i16 though.
Gabor Greifba36cb52008-08-28 21:40:38 +00003988 V1IsSplat = isSplatVector(V1.getNode());
3989 V2IsSplat = isSplatVector(V2.getNode());
Chris Lattner8a594482007-11-25 00:24:49 +00003990
3991 // Canonicalize the splat or undef, if present, to be on the RHS.
Evan Cheng9bbbb982006-10-25 20:48:19 +00003992 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
Evan Cheng9eca5e82006-10-25 21:49:50 +00003993 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
Evan Cheng9bbbb982006-10-25 20:48:19 +00003994 std::swap(V1IsSplat, V2IsSplat);
3995 std::swap(V1IsUndef, V2IsUndef);
Evan Cheng9eca5e82006-10-25 21:49:50 +00003996 Commuted = true;
Evan Cheng9bbbb982006-10-25 20:48:19 +00003997 }
3998
Evan Cheng7a831ce2007-12-15 03:00:47 +00003999 // FIXME: Figure out a cleaner way to do this.
Gabor Greifba36cb52008-08-28 21:40:38 +00004000 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
Evan Cheng9bbbb982006-10-25 20:48:19 +00004001 if (V2IsUndef) return V1;
Evan Cheng9eca5e82006-10-25 21:49:50 +00004002 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
Evan Cheng9bbbb982006-10-25 20:48:19 +00004003 if (V2IsSplat) {
4004 // V2 is a splat, so the mask may be malformed. That is, it may point
4005 // to any V2 element. The instruction selectior won't like this. Get
4006 // a corrected mask and commute to form a proper MOVS{S|D}.
Dan Gohman475871a2008-07-27 21:46:04 +00004007 SDValue NewMask = getMOVLMask(NumElems, DAG);
Gabor Greifba36cb52008-08-28 21:40:38 +00004008 if (NewMask.getNode() != PermMask.getNode())
Evan Cheng9bbbb982006-10-25 20:48:19 +00004009 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004010 }
Evan Cheng9bbbb982006-10-25 20:48:19 +00004011 return Op;
Evan Chengd9b8e402006-10-16 06:36:00 +00004012 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004013
Gabor Greifba36cb52008-08-28 21:40:38 +00004014 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4015 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4016 X86::isUNPCKLMask(PermMask.getNode()) ||
4017 X86::isUNPCKHMask(PermMask.getNode()))
Evan Chengd9b8e402006-10-16 06:36:00 +00004018 return Op;
Evan Chenge1113032006-10-04 18:33:38 +00004019
Evan Cheng9bbbb982006-10-25 20:48:19 +00004020 if (V2IsSplat) {
4021 // Normalize mask so all entries that point to V2 points to its first
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00004022 // element then try to match unpck{h|l} again. If match, return a
Evan Cheng9bbbb982006-10-25 20:48:19 +00004023 // new vector_shuffle with the corrected mask.
Dan Gohman475871a2008-07-27 21:46:04 +00004024 SDValue NewMask = NormalizeMask(PermMask, DAG);
Gabor Greifba36cb52008-08-28 21:40:38 +00004025 if (NewMask.getNode() != PermMask.getNode()) {
4026 if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
Dan Gohman475871a2008-07-27 21:46:04 +00004027 SDValue NewMask = getUnpacklMask(NumElems, DAG);
Evan Cheng9bbbb982006-10-25 20:48:19 +00004028 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
Gabor Greifba36cb52008-08-28 21:40:38 +00004029 } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
Dan Gohman475871a2008-07-27 21:46:04 +00004030 SDValue NewMask = getUnpackhMask(NumElems, DAG);
Evan Cheng9bbbb982006-10-25 20:48:19 +00004031 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004032 }
4033 }
4034 }
4035
4036 // Normalize the node to match x86 shuffle ops if needed
Gabor Greifba36cb52008-08-28 21:40:38 +00004037 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
Evan Cheng9eca5e82006-10-25 21:49:50 +00004038 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4039
4040 if (Commuted) {
4041 // Commute is back and try unpck* again.
4042 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
Gabor Greifba36cb52008-08-28 21:40:38 +00004043 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4044 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4045 X86::isUNPCKLMask(PermMask.getNode()) ||
4046 X86::isUNPCKHMask(PermMask.getNode()))
Evan Cheng9eca5e82006-10-25 21:49:50 +00004047 return Op;
4048 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004049
Evan Cheng0c0f83f2008-04-05 00:30:36 +00004050 // Try PSHUF* first, then SHUFP*.
4051 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4052 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
Gabor Greifba36cb52008-08-28 21:40:38 +00004053 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
Evan Cheng0c0f83f2008-04-05 00:30:36 +00004054 if (V2.getOpcode() != ISD::UNDEF)
4055 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
4056 DAG.getNode(ISD::UNDEF, VT), PermMask);
4057 return Op;
4058 }
4059
4060 if (!isMMX) {
4061 if (Subtarget->hasSSE2() &&
Gabor Greifba36cb52008-08-28 21:40:38 +00004062 (X86::isPSHUFDMask(PermMask.getNode()) ||
4063 X86::isPSHUFHWMask(PermMask.getNode()) ||
4064 X86::isPSHUFLWMask(PermMask.getNode()))) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004065 MVT RVT = VT;
Evan Cheng0c0f83f2008-04-05 00:30:36 +00004066 if (VT == MVT::v4f32) {
4067 RVT = MVT::v4i32;
4068 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
4069 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
4070 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4071 } else if (V2.getOpcode() != ISD::UNDEF)
4072 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
4073 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4074 if (RVT != VT)
4075 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004076 return Op;
4077 }
4078
Evan Cheng0c0f83f2008-04-05 00:30:36 +00004079 // Binary or unary shufps.
Gabor Greifba36cb52008-08-28 21:40:38 +00004080 if (X86::isSHUFPMask(PermMask.getNode()) ||
4081 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
Evan Cheng0db9fe62006-04-25 20:13:52 +00004082 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004083 }
4084
Evan Cheng14b32e12007-12-11 01:46:18 +00004085 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4086 if (VT == MVT::v8i16) {
Dan Gohman475871a2008-07-27 21:46:04 +00004087 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
Gabor Greifba36cb52008-08-28 21:40:38 +00004088 if (NewOp.getNode())
Evan Cheng14b32e12007-12-11 01:46:18 +00004089 return NewOp;
4090 }
4091
Evan Chengace3c172008-07-22 21:13:36 +00004092 // Handle all 4 wide cases with a number of shuffles except for MMX.
4093 if (NumElems == 4 && !isMMX)
4094 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004095
Dan Gohman475871a2008-07-27 21:46:04 +00004096 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004097}
4098
Dan Gohman475871a2008-07-27 21:46:04 +00004099SDValue
4100X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
Nate Begeman14d12ca2008-02-11 04:19:36 +00004101 SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004102 MVT VT = Op.getValueType();
4103 if (VT.getSizeInBits() == 8) {
Dan Gohman475871a2008-07-27 21:46:04 +00004104 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
Nate Begeman14d12ca2008-02-11 04:19:36 +00004105 Op.getOperand(0), Op.getOperand(1));
Dan Gohman475871a2008-07-27 21:46:04 +00004106 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
Nate Begeman14d12ca2008-02-11 04:19:36 +00004107 DAG.getValueType(VT));
4108 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
Duncan Sands83ec4b62008-06-06 12:08:01 +00004109 } else if (VT.getSizeInBits() == 16) {
Dan Gohman475871a2008-07-27 21:46:04 +00004110 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
Nate Begeman14d12ca2008-02-11 04:19:36 +00004111 Op.getOperand(0), Op.getOperand(1));
Dan Gohman475871a2008-07-27 21:46:04 +00004112 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
Nate Begeman14d12ca2008-02-11 04:19:36 +00004113 DAG.getValueType(VT));
4114 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
Evan Cheng62a3f152008-03-24 21:52:23 +00004115 } else if (VT == MVT::f32) {
4116 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4117 // the result back to FR32 register. It's only worth matching if the
Dan Gohman171c11e2008-04-16 02:32:24 +00004118 // result has a single use which is a store or a bitcast to i32.
Evan Cheng62a3f152008-03-24 21:52:23 +00004119 if (!Op.hasOneUse())
Dan Gohman475871a2008-07-27 21:46:04 +00004120 return SDValue();
Gabor Greifba36cb52008-08-28 21:40:38 +00004121 SDNode *User = *Op.getNode()->use_begin();
Dan Gohman171c11e2008-04-16 02:32:24 +00004122 if (User->getOpcode() != ISD::STORE &&
4123 (User->getOpcode() != ISD::BIT_CONVERT ||
4124 User->getValueType(0) != MVT::i32))
Dan Gohman475871a2008-07-27 21:46:04 +00004125 return SDValue();
4126 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
Evan Cheng62a3f152008-03-24 21:52:23 +00004127 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
4128 Op.getOperand(1));
4129 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
Nate Begeman14d12ca2008-02-11 04:19:36 +00004130 }
Dan Gohman475871a2008-07-27 21:46:04 +00004131 return SDValue();
Nate Begeman14d12ca2008-02-11 04:19:36 +00004132}
4133
4134
Dan Gohman475871a2008-07-27 21:46:04 +00004135SDValue
4136X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004137 if (!isa<ConstantSDNode>(Op.getOperand(1)))
Dan Gohman475871a2008-07-27 21:46:04 +00004138 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004139
Evan Cheng62a3f152008-03-24 21:52:23 +00004140 if (Subtarget->hasSSE41()) {
Dan Gohman475871a2008-07-27 21:46:04 +00004141 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
Gabor Greifba36cb52008-08-28 21:40:38 +00004142 if (Res.getNode())
Evan Cheng62a3f152008-03-24 21:52:23 +00004143 return Res;
4144 }
Nate Begeman14d12ca2008-02-11 04:19:36 +00004145
Duncan Sands83ec4b62008-06-06 12:08:01 +00004146 MVT VT = Op.getValueType();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004147 // TODO: handle v16i8.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004148 if (VT.getSizeInBits() == 16) {
Dan Gohman475871a2008-07-27 21:46:04 +00004149 SDValue Vec = Op.getOperand(0);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004150 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00004151 if (Idx == 0)
4152 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4153 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4154 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4155 Op.getOperand(1)));
Evan Cheng0db9fe62006-04-25 20:13:52 +00004156 // Transform it so it match pextrw which produces a 32-bit result.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004157 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
Dan Gohman475871a2008-07-27 21:46:04 +00004158 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
Evan Cheng0db9fe62006-04-25 20:13:52 +00004159 Op.getOperand(0), Op.getOperand(1));
Dan Gohman475871a2008-07-27 21:46:04 +00004160 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
Evan Cheng0db9fe62006-04-25 20:13:52 +00004161 DAG.getValueType(VT));
4162 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
Duncan Sands83ec4b62008-06-06 12:08:01 +00004163 } else if (VT.getSizeInBits() == 32) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004164 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004165 if (Idx == 0)
4166 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004167 // SHUFPS the element to the lowest double word, then movss.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004168 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
Dan Gohman475871a2008-07-27 21:46:04 +00004169 SmallVector<SDValue, 8> IdxVec;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00004170 IdxVec.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004171 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00004172 IdxVec.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004173 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00004174 IdxVec.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004175 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00004176 IdxVec.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004177 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
Dan Gohman475871a2008-07-27 21:46:04 +00004178 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
Chris Lattnere2199452006-08-11 17:38:39 +00004179 &IdxVec[0], IdxVec.size());
Dan Gohman475871a2008-07-27 21:46:04 +00004180 SDValue Vec = Op.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004181 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
Evan Cheng6e56e2c2006-11-07 22:14:24 +00004182 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004183 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
Chris Lattner0bd48932008-01-17 07:00:52 +00004184 DAG.getIntPtrConstant(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00004185 } else if (VT.getSizeInBits() == 64) {
Nate Begeman14d12ca2008-02-11 04:19:36 +00004186 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4187 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4188 // to match extract_elt for f64.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004189 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004190 if (Idx == 0)
4191 return Op;
4192
4193 // UNPCKHPD the element to the lowest double word, then movsd.
4194 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4195 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
Duncan Sandsd038e042008-07-21 10:20:31 +00004196 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
Dan Gohman475871a2008-07-27 21:46:04 +00004197 SmallVector<SDValue, 8> IdxVec;
Duncan Sands83ec4b62008-06-06 12:08:01 +00004198 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00004199 IdxVec.
Duncan Sands83ec4b62008-06-06 12:08:01 +00004200 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
Dan Gohman475871a2008-07-27 21:46:04 +00004201 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
Chris Lattnere2199452006-08-11 17:38:39 +00004202 &IdxVec[0], IdxVec.size());
Dan Gohman475871a2008-07-27 21:46:04 +00004203 SDValue Vec = Op.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004204 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4205 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4206 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
Chris Lattner0bd48932008-01-17 07:00:52 +00004207 DAG.getIntPtrConstant(0));
Evan Cheng0db9fe62006-04-25 20:13:52 +00004208 }
4209
Dan Gohman475871a2008-07-27 21:46:04 +00004210 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004211}
4212
Dan Gohman475871a2008-07-27 21:46:04 +00004213SDValue
4214X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
Duncan Sands83ec4b62008-06-06 12:08:01 +00004215 MVT VT = Op.getValueType();
4216 MVT EVT = VT.getVectorElementType();
Nate Begeman14d12ca2008-02-11 04:19:36 +00004217
Dan Gohman475871a2008-07-27 21:46:04 +00004218 SDValue N0 = Op.getOperand(0);
4219 SDValue N1 = Op.getOperand(1);
4220 SDValue N2 = Op.getOperand(2);
Nate Begeman14d12ca2008-02-11 04:19:36 +00004221
Dan Gohmanef521f12008-08-14 22:53:18 +00004222 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4223 isa<ConstantSDNode>(N2)) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004224 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
Nate Begeman14d12ca2008-02-11 04:19:36 +00004225 : X86ISD::PINSRW;
4226 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4227 // argument.
4228 if (N1.getValueType() != MVT::i32)
4229 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4230 if (N2.getValueType() != MVT::i32)
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004231 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
Nate Begeman14d12ca2008-02-11 04:19:36 +00004232 return DAG.getNode(Opc, VT, N0, N1, N2);
Dan Gohmanc0573b12008-08-14 22:43:26 +00004233 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
Nate Begeman14d12ca2008-02-11 04:19:36 +00004234 // Bits [7:6] of the constant are the source select. This will always be
4235 // zero here. The DAG Combiner may combine an extract_elt index into these
4236 // bits. For example (insert (extract, 3), 2) could be matched by putting
4237 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4238 // Bits [5:4] of the constant are the destination select. This is the
4239 // value of the incoming immediate.
4240 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4241 // combine either bitwise AND or insert of float 0.0 to set these bits.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004242 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
Nate Begeman14d12ca2008-02-11 04:19:36 +00004243 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4244 }
Dan Gohman475871a2008-07-27 21:46:04 +00004245 return SDValue();
Nate Begeman14d12ca2008-02-11 04:19:36 +00004246}
4247
Dan Gohman475871a2008-07-27 21:46:04 +00004248SDValue
4249X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004250 MVT VT = Op.getValueType();
4251 MVT EVT = VT.getVectorElementType();
Nate Begeman14d12ca2008-02-11 04:19:36 +00004252
4253 if (Subtarget->hasSSE41())
4254 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4255
Evan Cheng794405e2007-12-12 07:55:34 +00004256 if (EVT == MVT::i8)
Dan Gohman475871a2008-07-27 21:46:04 +00004257 return SDValue();
Evan Cheng794405e2007-12-12 07:55:34 +00004258
Dan Gohman475871a2008-07-27 21:46:04 +00004259 SDValue N0 = Op.getOperand(0);
4260 SDValue N1 = Op.getOperand(1);
4261 SDValue N2 = Op.getOperand(2);
Evan Cheng794405e2007-12-12 07:55:34 +00004262
Duncan Sands83ec4b62008-06-06 12:08:01 +00004263 if (EVT.getSizeInBits() == 16) {
Evan Cheng794405e2007-12-12 07:55:34 +00004264 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4265 // as its second argument.
Evan Cheng0db9fe62006-04-25 20:13:52 +00004266 if (N1.getValueType() != MVT::i32)
4267 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4268 if (N2.getValueType() != MVT::i32)
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004269 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004270 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004271 }
Dan Gohman475871a2008-07-27 21:46:04 +00004272 return SDValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004273}
4274
Dan Gohman475871a2008-07-27 21:46:04 +00004275SDValue
4276X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
Evan Cheng52672b82008-07-22 18:39:19 +00004277 if (Op.getValueType() == MVT::v2f32)
4278 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
4279 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
4280 DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
4281 Op.getOperand(0))));
4282
Dan Gohman475871a2008-07-27 21:46:04 +00004283 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +00004284 MVT VT = MVT::v2i32;
4285 switch (Op.getValueType().getSimpleVT()) {
Evan Chengefec7512008-02-18 23:04:32 +00004286 default: break;
4287 case MVT::v16i8:
4288 case MVT::v8i16:
4289 VT = MVT::v4i32;
4290 break;
4291 }
4292 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4293 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
Evan Cheng0db9fe62006-04-25 20:13:52 +00004294}
4295
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00004296// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
Evan Cheng0db9fe62006-04-25 20:13:52 +00004297// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4298// one of the above mentioned nodes. It has to be wrapped because otherwise
4299// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4300// be used to form addressing mode. These wrapped nodes will be selected
4301// into MOV32ri.
Dan Gohman475871a2008-07-27 21:46:04 +00004302SDValue
4303X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004304 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Dan Gohman475871a2008-07-27 21:46:04 +00004305 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
Evan Chengd0ff02c2006-11-29 23:19:46 +00004306 getPointerTy(),
4307 CP->getAlignment());
Evan Cheng19f2ffc2006-12-05 04:01:03 +00004308 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004309 // With PIC, the address is actually $g + Offset.
4310 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4311 !Subtarget->isPICStyleRIPRel()) {
4312 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4313 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4314 Result);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004315 }
4316
4317 return Result;
4318}
4319
Dan Gohman475871a2008-07-27 21:46:04 +00004320SDValue
4321X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004322 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Dan Gohman475871a2008-07-27 21:46:04 +00004323 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
Evan Cheng19f2ffc2006-12-05 04:01:03 +00004324 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004325 // With PIC, the address is actually $g + Offset.
4326 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4327 !Subtarget->isPICStyleRIPRel()) {
4328 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4329 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4330 Result);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004331 }
Anton Korobeynikov2b2bc682006-12-22 22:29:05 +00004332
4333 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4334 // load the value at address GV, not the value of GV itself. This means that
4335 // the GlobalAddress must be in the base or index register of the address, not
4336 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004337 // The same applies for external symbols during PIC codegen
Anton Korobeynikov2b2bc682006-12-22 22:29:05 +00004338 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
Dan Gohman69de1932008-02-06 22:27:42 +00004339 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
Dan Gohman3069b872008-02-07 18:41:25 +00004340 PseudoSourceValue::getGOT(), 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004341
4342 return Result;
4343}
4344
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004345// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
Dan Gohman475871a2008-07-27 21:46:04 +00004346static SDValue
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004347LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
Duncan Sands83ec4b62008-06-06 12:08:01 +00004348 const MVT PtrVT) {
Dan Gohman475871a2008-07-27 21:46:04 +00004349 SDValue InFlag;
4350 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004351 DAG.getNode(X86ISD::GlobalBaseReg,
4352 PtrVT), InFlag);
4353 InFlag = Chain.getValue(1);
4354
4355 // emit leal symbol@TLSGD(,%ebx,1), %eax
4356 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00004357 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004358 GA->getValueType(0),
4359 GA->getOffset());
Dan Gohman475871a2008-07-27 21:46:04 +00004360 SDValue Ops[] = { Chain, TGA, InFlag };
4361 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004362 InFlag = Result.getValue(2);
4363 Chain = Result.getValue(1);
4364
4365 // call ___tls_get_addr. This function receives its argument in
4366 // the register EAX.
4367 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4368 InFlag = Chain.getValue(1);
4369
4370 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00004371 SDValue Ops1[] = { Chain,
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004372 DAG.getTargetExternalSymbol("___tls_get_addr",
4373 PtrVT),
4374 DAG.getRegister(X86::EAX, PtrVT),
4375 DAG.getRegister(X86::EBX, PtrVT),
4376 InFlag };
4377 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4378 InFlag = Chain.getValue(1);
4379
4380 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4381}
4382
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004383// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
Dan Gohman475871a2008-07-27 21:46:04 +00004384static SDValue
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004385LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
Duncan Sands83ec4b62008-06-06 12:08:01 +00004386 const MVT PtrVT) {
Dan Gohman475871a2008-07-27 21:46:04 +00004387 SDValue InFlag, Chain;
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004388
4389 // emit leaq symbol@TLSGD(%rip), %rdi
4390 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00004391 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004392 GA->getValueType(0),
4393 GA->getOffset());
Dan Gohman475871a2008-07-27 21:46:04 +00004394 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4395 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004396 Chain = Result.getValue(1);
4397 InFlag = Result.getValue(2);
4398
Anton Korobeynikovd97f2952008-08-16 12:58:29 +00004399 // call __tls_get_addr. This function receives its argument in
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004400 // the register RDI.
4401 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4402 InFlag = Chain.getValue(1);
4403
4404 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00004405 SDValue Ops1[] = { Chain,
Anton Korobeynikovd97f2952008-08-16 12:58:29 +00004406 DAG.getTargetExternalSymbol("__tls_get_addr",
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004407 PtrVT),
4408 DAG.getRegister(X86::RDI, PtrVT),
4409 InFlag };
4410 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4411 InFlag = Chain.getValue(1);
4412
4413 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4414}
4415
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004416// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4417// "local exec" model.
Dan Gohman475871a2008-07-27 21:46:04 +00004418static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
Duncan Sands83ec4b62008-06-06 12:08:01 +00004419 const MVT PtrVT) {
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004420 // Get the Thread Pointer
Dan Gohman475871a2008-07-27 21:46:04 +00004421 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004422 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4423 // exec)
Dan Gohman475871a2008-07-27 21:46:04 +00004424 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004425 GA->getValueType(0),
4426 GA->getOffset());
Dan Gohman475871a2008-07-27 21:46:04 +00004427 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
Lauro Ramos Venancio7d2cc2b2007-04-22 22:50:52 +00004428
4429 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
Dan Gohman69de1932008-02-06 22:27:42 +00004430 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
Dan Gohman3069b872008-02-07 18:41:25 +00004431 PseudoSourceValue::getGOT(), 0);
Lauro Ramos Venancio7d2cc2b2007-04-22 22:50:52 +00004432
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004433 // The address of the thread local variable is the add of the thread
4434 // pointer with the offset of the variable.
4435 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4436}
4437
Dan Gohman475871a2008-07-27 21:46:04 +00004438SDValue
4439X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004440 // TODO: implement the "local dynamic" model
Lauro Ramos Venancio2c5c1112007-04-21 20:56:26 +00004441 // TODO: implement the "initial exec"model for pic executables
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004442 assert(Subtarget->isTargetELF() &&
4443 "TLS not implemented for non-ELF targets");
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004444 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4445 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4446 // otherwise use the "Local Exec"TLS Model
Anton Korobeynikov6625eff2008-05-04 21:36:32 +00004447 if (Subtarget->is64Bit()) {
4448 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4449 } else {
4450 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4451 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4452 else
4453 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4454 }
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00004455}
4456
Dan Gohman475871a2008-07-27 21:46:04 +00004457SDValue
4458X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004459 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
Dan Gohman475871a2008-07-27 21:46:04 +00004460 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
Evan Cheng19f2ffc2006-12-05 04:01:03 +00004461 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004462 // With PIC, the address is actually $g + Offset.
4463 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4464 !Subtarget->isPICStyleRIPRel()) {
4465 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4466 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4467 Result);
4468 }
4469
4470 return Result;
4471}
4472
Dan Gohman475871a2008-07-27 21:46:04 +00004473SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004474 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
Dan Gohman475871a2008-07-27 21:46:04 +00004475 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
Anton Korobeynikov7f705592007-01-12 19:20:47 +00004476 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4477 // With PIC, the address is actually $g + Offset.
4478 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4479 !Subtarget->isPICStyleRIPRel()) {
4480 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4481 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4482 Result);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004483 }
4484
4485 return Result;
4486}
4487
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004488/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4489/// take a 2 x i32 value to shift plus a shift amount.
Dan Gohman475871a2008-07-27 21:46:04 +00004490SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
Dan Gohman4c1fa612008-03-03 22:22:09 +00004491 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
Duncan Sands83ec4b62008-06-06 12:08:01 +00004492 MVT VT = Op.getValueType();
4493 unsigned VTBits = VT.getSizeInBits();
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004494 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
Dan Gohman475871a2008-07-27 21:46:04 +00004495 SDValue ShOpLo = Op.getOperand(0);
4496 SDValue ShOpHi = Op.getOperand(1);
4497 SDValue ShAmt = Op.getOperand(2);
4498 SDValue Tmp1 = isSRA ?
Dan Gohman4c1fa612008-03-03 22:22:09 +00004499 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4500 DAG.getConstant(0, VT);
Evan Chenge3413162006-01-09 18:33:28 +00004501
Dan Gohman475871a2008-07-27 21:46:04 +00004502 SDValue Tmp2, Tmp3;
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004503 if (Op.getOpcode() == ISD::SHL_PARTS) {
Dan Gohman4c1fa612008-03-03 22:22:09 +00004504 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4505 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004506 } else {
Dan Gohman4c1fa612008-03-03 22:22:09 +00004507 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4508 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004509 }
Evan Chenge3413162006-01-09 18:33:28 +00004510
Dan Gohman475871a2008-07-27 21:46:04 +00004511 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
Dan Gohman4c1fa612008-03-03 22:22:09 +00004512 DAG.getConstant(VTBits, MVT::i8));
Dan Gohman475871a2008-07-27 21:46:04 +00004513 SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004514 AndNode, DAG.getConstant(0, MVT::i8));
Evan Chenge3413162006-01-09 18:33:28 +00004515
Dan Gohman475871a2008-07-27 21:46:04 +00004516 SDValue Hi, Lo;
4517 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4518 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4519 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
Duncan Sandsf9516202008-06-30 10:19:09 +00004520
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004521 if (Op.getOpcode() == ISD::SHL_PARTS) {
Duncan Sandsf9516202008-06-30 10:19:09 +00004522 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4523 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004524 } else {
Duncan Sandsf9516202008-06-30 10:19:09 +00004525 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4526 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
Chris Lattner2ff75ee2007-10-17 06:02:13 +00004527 }
4528
Dan Gohman475871a2008-07-27 21:46:04 +00004529 SDValue Ops[2] = { Lo, Hi };
Duncan Sands4bdcb612008-07-02 17:40:58 +00004530 return DAG.getMergeValues(Ops, 2);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004531}
Evan Chenga3195e82006-01-12 22:54:21 +00004532
Dan Gohman475871a2008-07-27 21:46:04 +00004533SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004534 MVT SrcVT = Op.getOperand(0).getValueType();
Duncan Sands8e4eb092008-06-08 20:54:56 +00004535 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
Chris Lattnerb09916b2008-02-27 05:57:41 +00004536 "Unknown SINT_TO_FP to lower!");
4537
4538 // These are really Legal; caller falls through into that case.
4539 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
Dan Gohman475871a2008-07-27 21:46:04 +00004540 return SDValue();
Chris Lattnerb09916b2008-02-27 05:57:41 +00004541 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4542 Subtarget->is64Bit())
Dan Gohman475871a2008-07-27 21:46:04 +00004543 return SDValue();
Chris Lattnerb09916b2008-02-27 05:57:41 +00004544
Duncan Sands83ec4b62008-06-06 12:08:01 +00004545 unsigned Size = SrcVT.getSizeInBits()/8;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004546 MachineFunction &MF = DAG.getMachineFunction();
4547 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
Dan Gohman475871a2008-07-27 21:46:04 +00004548 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4549 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
Dan Gohman69de1932008-02-06 22:27:42 +00004550 StackSlot,
Dan Gohmana54cf172008-07-11 22:44:52 +00004551 PseudoSourceValue::getFixedStack(SSFI), 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004552
4553 // Build the FILD
Chris Lattner5a88b832007-02-25 07:10:00 +00004554 SDVTList Tys;
Chris Lattner78631162008-01-16 06:24:21 +00004555 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00004556 if (useSSE)
Chris Lattner5a88b832007-02-25 07:10:00 +00004557 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4558 else
Dale Johannesen849f2142007-07-03 00:53:03 +00004559 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
Dan Gohman475871a2008-07-27 21:46:04 +00004560 SmallVector<SDValue, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004561 Ops.push_back(Chain);
4562 Ops.push_back(StackSlot);
4563 Ops.push_back(DAG.getValueType(SrcVT));
Dan Gohman475871a2008-07-27 21:46:04 +00004564 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
Chris Lattnerb09916b2008-02-27 05:57:41 +00004565 Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004566
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00004567 if (useSSE) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004568 Chain = Result.getValue(1);
Dan Gohman475871a2008-07-27 21:46:04 +00004569 SDValue InFlag = Result.getValue(2);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004570
4571 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4572 // shouldn't be necessary except that RFP cannot be live across
4573 // multiple blocks. When stackifier is fixed, they can be uncoupled.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004574 MachineFunction &MF = DAG.getMachineFunction();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004575 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
Dan Gohman475871a2008-07-27 21:46:04 +00004576 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Chris Lattner5a88b832007-02-25 07:10:00 +00004577 Tys = DAG.getVTList(MVT::Other);
Dan Gohman475871a2008-07-27 21:46:04 +00004578 SmallVector<SDValue, 8> Ops;
Evan Chenga3195e82006-01-12 22:54:21 +00004579 Ops.push_back(Chain);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004580 Ops.push_back(Result);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004581 Ops.push_back(StackSlot);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004582 Ops.push_back(DAG.getValueType(Op.getValueType()));
4583 Ops.push_back(InFlag);
Chris Lattnerbd564bf2006-08-08 02:23:42 +00004584 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
Dan Gohman69de1932008-02-06 22:27:42 +00004585 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
Dan Gohmana54cf172008-07-11 22:44:52 +00004586 PseudoSourceValue::getFixedStack(SSFI), 0);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004587 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004588
Evan Cheng0db9fe62006-04-25 20:13:52 +00004589 return Result;
4590}
4591
Dan Gohman475871a2008-07-27 21:46:04 +00004592std::pair<SDValue,SDValue> X86TargetLowering::
4593FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
Duncan Sands8e4eb092008-06-08 20:54:56 +00004594 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4595 Op.getValueType().getSimpleVT() >= MVT::i16 &&
Evan Cheng0db9fe62006-04-25 20:13:52 +00004596 "Unknown FP_TO_SINT to lower!");
Evan Cheng0db9fe62006-04-25 20:13:52 +00004597
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00004598 // These are really Legal.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +00004599 if (Op.getValueType() == MVT::i32 &&
Chris Lattner78631162008-01-16 06:24:21 +00004600 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
Dan Gohman475871a2008-07-27 21:46:04 +00004601 return std::make_pair(SDValue(), SDValue());
Dale Johannesen73328d12007-09-19 23:55:34 +00004602 if (Subtarget->is64Bit() &&
4603 Op.getValueType() == MVT::i64 &&
4604 Op.getOperand(0).getValueType() != MVT::f80)
Dan Gohman475871a2008-07-27 21:46:04 +00004605 return std::make_pair(SDValue(), SDValue());
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00004606
Evan Cheng87c89352007-10-15 20:11:21 +00004607 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4608 // stack slot.
4609 MachineFunction &MF = DAG.getMachineFunction();
Duncan Sands83ec4b62008-06-06 12:08:01 +00004610 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
Evan Cheng87c89352007-10-15 20:11:21 +00004611 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
Dan Gohman475871a2008-07-27 21:46:04 +00004612 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004613 unsigned Opc;
Duncan Sands83ec4b62008-06-06 12:08:01 +00004614 switch (Op.getValueType().getSimpleVT()) {
Chris Lattner27a6c732007-11-24 07:07:01 +00004615 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4616 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4617 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4618 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004619 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004620
Dan Gohman475871a2008-07-27 21:46:04 +00004621 SDValue Chain = DAG.getEntryNode();
4622 SDValue Value = Op.getOperand(0);
Chris Lattner78631162008-01-16 06:24:21 +00004623 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004624 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
Dan Gohman69de1932008-02-06 22:27:42 +00004625 Chain = DAG.getStore(Chain, Value, StackSlot,
Dan Gohmana54cf172008-07-11 22:44:52 +00004626 PseudoSourceValue::getFixedStack(SSFI), 0);
Dale Johannesen849f2142007-07-03 00:53:03 +00004627 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
Dan Gohman475871a2008-07-27 21:46:04 +00004628 SDValue Ops[] = {
Chris Lattner5a88b832007-02-25 07:10:00 +00004629 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4630 };
4631 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004632 Chain = Value.getValue(1);
4633 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4634 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4635 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004636
Evan Cheng0db9fe62006-04-25 20:13:52 +00004637 // Build the FP_TO_INT*_IN_MEM
Dan Gohman475871a2008-07-27 21:46:04 +00004638 SDValue Ops[] = { Chain, Value, StackSlot };
4639 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
Evan Chengd9558e02006-01-06 00:43:03 +00004640
Chris Lattner27a6c732007-11-24 07:07:01 +00004641 return std::make_pair(FIST, StackSlot);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004642}
4643
Dan Gohman475871a2008-07-27 21:46:04 +00004644SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
4645 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
4646 SDValue FIST = Vals.first, StackSlot = Vals.second;
Gabor Greifba36cb52008-08-28 21:40:38 +00004647 if (FIST.getNode() == 0) return SDValue();
Chris Lattner27a6c732007-11-24 07:07:01 +00004648
4649 // Load the result.
4650 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4651}
4652
4653SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
Dan Gohman475871a2008-07-27 21:46:04 +00004654 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
4655 SDValue FIST = Vals.first, StackSlot = Vals.second;
Gabor Greifba36cb52008-08-28 21:40:38 +00004656 if (FIST.getNode() == 0) return 0;
Duncan Sandsf9516202008-06-30 10:19:09 +00004657
4658 MVT VT = N->getValueType(0);
4659
4660 // Return a load from the stack slot.
Dan Gohman475871a2008-07-27 21:46:04 +00004661 SDValue Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0);
Chris Lattner27a6c732007-11-24 07:07:01 +00004662
Duncan Sands4bdcb612008-07-02 17:40:58 +00004663 // Use MERGE_VALUES to drop the chain result value and get a node with one
4664 // result. This requires turning off getMergeValues simplification, since
4665 // otherwise it will give us Res back.
Gabor Greifba36cb52008-08-28 21:40:38 +00004666 return DAG.getMergeValues(&Res, 1, false).getNode();
Duncan Sandsf9516202008-06-30 10:19:09 +00004667}
Chris Lattner27a6c732007-11-24 07:07:01 +00004668
Dan Gohman475871a2008-07-27 21:46:04 +00004669SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004670 MVT VT = Op.getValueType();
4671 MVT EltVT = VT;
4672 if (VT.isVector())
4673 EltVT = VT.getVectorElementType();
Evan Cheng0db9fe62006-04-25 20:13:52 +00004674 std::vector<Constant*> CV;
Dan Gohman20382522007-07-10 00:05:58 +00004675 if (EltVT == MVT::f64) {
Chris Lattner02a260a2008-04-20 00:41:09 +00004676 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
Dan Gohman20382522007-07-10 00:05:58 +00004677 CV.push_back(C);
4678 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004679 } else {
Chris Lattner02a260a2008-04-20 00:41:09 +00004680 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
Dan Gohman20382522007-07-10 00:05:58 +00004681 CV.push_back(C);
4682 CV.push_back(C);
4683 CV.push_back(C);
4684 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004685 }
Dan Gohmand3006222007-07-27 17:16:43 +00004686 Constant *C = ConstantVector::get(CV);
Dan Gohman475871a2008-07-27 21:46:04 +00004687 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4688 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00004689 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00004690 false, 16);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004691 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4692}
4693
Dan Gohman475871a2008-07-27 21:46:04 +00004694SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00004695 MVT VT = Op.getValueType();
4696 MVT EltVT = VT;
Evan Chengd4d01b72007-07-19 23:36:01 +00004697 unsigned EltNum = 1;
Duncan Sands83ec4b62008-06-06 12:08:01 +00004698 if (VT.isVector()) {
4699 EltVT = VT.getVectorElementType();
4700 EltNum = VT.getVectorNumElements();
Evan Chengd4d01b72007-07-19 23:36:01 +00004701 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004702 std::vector<Constant*> CV;
Dan Gohman20382522007-07-10 00:05:58 +00004703 if (EltVT == MVT::f64) {
Chris Lattner02a260a2008-04-20 00:41:09 +00004704 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
Dan Gohman20382522007-07-10 00:05:58 +00004705 CV.push_back(C);
4706 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004707 } else {
Chris Lattner02a260a2008-04-20 00:41:09 +00004708 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
Dan Gohman20382522007-07-10 00:05:58 +00004709 CV.push_back(C);
4710 CV.push_back(C);
4711 CV.push_back(C);
4712 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004713 }
Dan Gohmand3006222007-07-27 17:16:43 +00004714 Constant *C = ConstantVector::get(CV);
Dan Gohman475871a2008-07-27 21:46:04 +00004715 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4716 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00004717 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00004718 false, 16);
Duncan Sands83ec4b62008-06-06 12:08:01 +00004719 if (VT.isVector()) {
Evan Chengd4d01b72007-07-19 23:36:01 +00004720 return DAG.getNode(ISD::BIT_CONVERT, VT,
4721 DAG.getNode(ISD::XOR, MVT::v2i64,
4722 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4723 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4724 } else {
Evan Chengd4d01b72007-07-19 23:36:01 +00004725 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4726 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004727}
4728
Dan Gohman475871a2008-07-27 21:46:04 +00004729SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
4730 SDValue Op0 = Op.getOperand(0);
4731 SDValue Op1 = Op.getOperand(1);
Duncan Sands83ec4b62008-06-06 12:08:01 +00004732 MVT VT = Op.getValueType();
4733 MVT SrcVT = Op1.getValueType();
Evan Cheng73d6cf12007-01-05 21:37:56 +00004734
4735 // If second operand is smaller, extend it first.
Duncan Sands8e4eb092008-06-08 20:54:56 +00004736 if (SrcVT.bitsLT(VT)) {
Evan Cheng73d6cf12007-01-05 21:37:56 +00004737 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4738 SrcVT = VT;
4739 }
Dale Johannesen61c7ef32007-10-21 01:07:44 +00004740 // And if it is bigger, shrink it first.
Duncan Sands8e4eb092008-06-08 20:54:56 +00004741 if (SrcVT.bitsGT(VT)) {
Chris Lattner0bd48932008-01-17 07:00:52 +00004742 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
Dale Johannesen61c7ef32007-10-21 01:07:44 +00004743 SrcVT = VT;
Dale Johannesen61c7ef32007-10-21 01:07:44 +00004744 }
4745
4746 // At this point the operands and the result should have the same
4747 // type, and that won't be f80 since that is not custom lowered.
Evan Cheng73d6cf12007-01-05 21:37:56 +00004748
Evan Cheng68c47cb2007-01-05 07:55:56 +00004749 // First get the sign bit of second operand.
4750 std::vector<Constant*> CV;
4751 if (SrcVT == MVT::f64) {
Chris Lattner02a260a2008-04-20 00:41:09 +00004752 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
4753 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
Evan Cheng68c47cb2007-01-05 07:55:56 +00004754 } else {
Chris Lattner02a260a2008-04-20 00:41:09 +00004755 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
4756 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4757 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4758 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
Evan Cheng68c47cb2007-01-05 07:55:56 +00004759 }
Dan Gohmand3006222007-07-27 17:16:43 +00004760 Constant *C = ConstantVector::get(CV);
Dan Gohman475871a2008-07-27 21:46:04 +00004761 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4762 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00004763 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00004764 false, 16);
Dan Gohman475871a2008-07-27 21:46:04 +00004765 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
Evan Cheng68c47cb2007-01-05 07:55:56 +00004766
4767 // Shift sign bit right or left if the two operands have different types.
Duncan Sands8e4eb092008-06-08 20:54:56 +00004768 if (SrcVT.bitsGT(VT)) {
Evan Cheng68c47cb2007-01-05 07:55:56 +00004769 // Op0 is MVT::f32, Op1 is MVT::f64.
4770 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4771 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4772 DAG.getConstant(32, MVT::i32));
4773 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4774 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
Chris Lattner0bd48932008-01-17 07:00:52 +00004775 DAG.getIntPtrConstant(0));
Evan Cheng68c47cb2007-01-05 07:55:56 +00004776 }
4777
Evan Cheng73d6cf12007-01-05 21:37:56 +00004778 // Clear first operand sign bit.
4779 CV.clear();
4780 if (VT == MVT::f64) {
Chris Lattner02a260a2008-04-20 00:41:09 +00004781 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
4782 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
Evan Cheng73d6cf12007-01-05 21:37:56 +00004783 } else {
Chris Lattner02a260a2008-04-20 00:41:09 +00004784 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
4785 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4786 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4787 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
Evan Cheng73d6cf12007-01-05 21:37:56 +00004788 }
Dan Gohmand3006222007-07-27 17:16:43 +00004789 C = ConstantVector::get(CV);
4790 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
Dan Gohman475871a2008-07-27 21:46:04 +00004791 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
Dan Gohman3069b872008-02-07 18:41:25 +00004792 PseudoSourceValue::getConstantPool(), 0,
Dan Gohmand3006222007-07-27 17:16:43 +00004793 false, 16);
Dan Gohman475871a2008-07-27 21:46:04 +00004794 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
Evan Cheng73d6cf12007-01-05 21:37:56 +00004795
4796 // Or the value with the sign bit.
4797 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
Evan Cheng68c47cb2007-01-05 07:55:56 +00004798}
4799
Dan Gohman475871a2008-07-27 21:46:04 +00004800SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
Evan Cheng0488db92007-09-25 01:57:46 +00004801 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
Dan Gohman475871a2008-07-27 21:46:04 +00004802 SDValue Cond;
4803 SDValue Op0 = Op.getOperand(0);
4804 SDValue Op1 = Op.getOperand(1);
4805 SDValue CC = Op.getOperand(2);
Evan Cheng0488db92007-09-25 01:57:46 +00004806 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
Duncan Sands83ec4b62008-06-06 12:08:01 +00004807 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
Evan Cheng0488db92007-09-25 01:57:46 +00004808 unsigned X86CC;
4809
Evan Cheng0488db92007-09-25 01:57:46 +00004810 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
Evan Cheng1a35edb2007-09-26 00:45:55 +00004811 Op0, Op1, DAG)) {
Evan Chenge5f62042007-09-29 00:00:36 +00004812 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4813 return DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004814 DAG.getConstant(X86CC, MVT::i8), Cond);
Evan Cheng1a35edb2007-09-26 00:45:55 +00004815 }
Evan Cheng0488db92007-09-25 01:57:46 +00004816
4817 assert(isFP && "Illegal integer SetCC!");
4818
Evan Chenge5f62042007-09-29 00:00:36 +00004819 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
Evan Cheng0488db92007-09-25 01:57:46 +00004820 switch (SetCCOpcode) {
4821 default: assert(false && "Illegal floating point SetCC!");
4822 case ISD::SETOEQ: { // !PF & ZF
Dan Gohman475871a2008-07-27 21:46:04 +00004823 SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004824 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
Dan Gohman475871a2008-07-27 21:46:04 +00004825 SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004826 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4827 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4828 }
4829 case ISD::SETUNE: { // PF | !ZF
Dan Gohman475871a2008-07-27 21:46:04 +00004830 SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004831 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
Dan Gohman475871a2008-07-27 21:46:04 +00004832 SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004833 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4834 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4835 }
4836 }
4837}
4838
Dan Gohman475871a2008-07-27 21:46:04 +00004839SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4840 SDValue Cond;
4841 SDValue Op0 = Op.getOperand(0);
4842 SDValue Op1 = Op.getOperand(1);
4843 SDValue CC = Op.getOperand(2);
Nate Begeman30a0de92008-07-17 16:51:19 +00004844 MVT VT = Op.getValueType();
4845 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4846 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
4847
4848 if (isFP) {
4849 unsigned SSECC = 8;
Evan Chenge9d50352008-08-05 22:19:15 +00004850 MVT VT0 = Op0.getValueType();
4851 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
4852 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
Nate Begeman30a0de92008-07-17 16:51:19 +00004853 bool Swap = false;
4854
4855 switch (SetCCOpcode) {
4856 default: break;
Nate Begemanfb8ead02008-07-25 19:05:58 +00004857 case ISD::SETOEQ:
Nate Begeman30a0de92008-07-17 16:51:19 +00004858 case ISD::SETEQ: SSECC = 0; break;
4859 case ISD::SETOGT:
4860 case ISD::SETGT: Swap = true; // Fallthrough
4861 case ISD::SETLT:
4862 case ISD::SETOLT: SSECC = 1; break;
4863 case ISD::SETOGE:
4864 case ISD::SETGE: Swap = true; // Fallthrough
4865 case ISD::SETLE:
4866 case ISD::SETOLE: SSECC = 2; break;
4867 case ISD::SETUO: SSECC = 3; break;
Nate Begemanfb8ead02008-07-25 19:05:58 +00004868 case ISD::SETUNE:
Nate Begeman30a0de92008-07-17 16:51:19 +00004869 case ISD::SETNE: SSECC = 4; break;
4870 case ISD::SETULE: Swap = true;
4871 case ISD::SETUGE: SSECC = 5; break;
4872 case ISD::SETULT: Swap = true;
4873 case ISD::SETUGT: SSECC = 6; break;
4874 case ISD::SETO: SSECC = 7; break;
4875 }
4876 if (Swap)
4877 std::swap(Op0, Op1);
4878
Nate Begemanfb8ead02008-07-25 19:05:58 +00004879 // In the two special cases we can't handle, emit two comparisons.
Nate Begeman30a0de92008-07-17 16:51:19 +00004880 if (SSECC == 8) {
Nate Begemanfb8ead02008-07-25 19:05:58 +00004881 if (SetCCOpcode == ISD::SETUEQ) {
Dan Gohman475871a2008-07-27 21:46:04 +00004882 SDValue UNORD, EQ;
Nate Begemanfb8ead02008-07-25 19:05:58 +00004883 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
4884 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
4885 return DAG.getNode(ISD::OR, VT, UNORD, EQ);
4886 }
4887 else if (SetCCOpcode == ISD::SETONE) {
Dan Gohman475871a2008-07-27 21:46:04 +00004888 SDValue ORD, NEQ;
Nate Begemanfb8ead02008-07-25 19:05:58 +00004889 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
4890 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
4891 return DAG.getNode(ISD::AND, VT, ORD, NEQ);
4892 }
4893 assert(0 && "Illegal FP comparison");
Nate Begeman30a0de92008-07-17 16:51:19 +00004894 }
4895 // Handle all other FP comparisons here.
4896 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
4897 }
4898
4899 // We are handling one of the integer comparisons here. Since SSE only has
4900 // GT and EQ comparisons for integer, swapping operands and multiple
4901 // operations may be required for some comparisons.
4902 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
4903 bool Swap = false, Invert = false, FlipSigns = false;
4904
4905 switch (VT.getSimpleVT()) {
4906 default: break;
4907 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
4908 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
4909 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
4910 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
4911 }
4912
4913 switch (SetCCOpcode) {
4914 default: break;
4915 case ISD::SETNE: Invert = true;
4916 case ISD::SETEQ: Opc = EQOpc; break;
4917 case ISD::SETLT: Swap = true;
4918 case ISD::SETGT: Opc = GTOpc; break;
4919 case ISD::SETGE: Swap = true;
4920 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
4921 case ISD::SETULT: Swap = true;
4922 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
4923 case ISD::SETUGE: Swap = true;
4924 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
4925 }
4926 if (Swap)
4927 std::swap(Op0, Op1);
4928
4929 // Since SSE has no unsigned integer comparisons, we need to flip the sign
4930 // bits of the inputs before performing those operations.
4931 if (FlipSigns) {
4932 MVT EltVT = VT.getVectorElementType();
Dan Gohman475871a2008-07-27 21:46:04 +00004933 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
4934 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
4935 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
Nate Begeman30a0de92008-07-17 16:51:19 +00004936 SignBits.size());
4937 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
4938 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
4939 }
4940
Dan Gohman475871a2008-07-27 21:46:04 +00004941 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
Nate Begeman30a0de92008-07-17 16:51:19 +00004942
4943 // If the logical-not of the result is required, perform that now.
4944 if (Invert) {
4945 MVT EltVT = VT.getVectorElementType();
Dan Gohman475871a2008-07-27 21:46:04 +00004946 SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
4947 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne);
4948 SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
Nate Begeman30a0de92008-07-17 16:51:19 +00004949 NegOnes.size());
4950 Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
4951 }
4952 return Result;
4953}
Evan Cheng0488db92007-09-25 01:57:46 +00004954
Dan Gohman475871a2008-07-27 21:46:04 +00004955SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
Evan Cheng734503b2006-09-11 02:19:56 +00004956 bool addTest = true;
Dan Gohman475871a2008-07-27 21:46:04 +00004957 SDValue Cond = Op.getOperand(0);
4958 SDValue CC;
Evan Cheng9bba8942006-01-26 02:13:10 +00004959
Evan Cheng734503b2006-09-11 02:19:56 +00004960 if (Cond.getOpcode() == ISD::SETCC)
Evan Chenge5f62042007-09-29 00:00:36 +00004961 Cond = LowerSETCC(Cond, DAG);
Evan Cheng734503b2006-09-11 02:19:56 +00004962
Evan Cheng3f41d662007-10-08 22:16:29 +00004963 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4964 // setting operand in place of the X86ISD::SETCC.
Evan Cheng734503b2006-09-11 02:19:56 +00004965 if (Cond.getOpcode() == X86ISD::SETCC) {
4966 CC = Cond.getOperand(0);
4967
Dan Gohman475871a2008-07-27 21:46:04 +00004968 SDValue Cmp = Cond.getOperand(1);
Evan Cheng734503b2006-09-11 02:19:56 +00004969 unsigned Opc = Cmp.getOpcode();
Duncan Sands83ec4b62008-06-06 12:08:01 +00004970 MVT VT = Op.getValueType();
Chris Lattner1956d152008-01-16 06:19:45 +00004971
Evan Cheng3f41d662007-10-08 22:16:29 +00004972 bool IllegalFPCMov = false;
Duncan Sands83ec4b62008-06-06 12:08:01 +00004973 if (VT.isFloatingPoint() && !VT.isVector() &&
Chris Lattner78631162008-01-16 06:24:21 +00004974 !isScalarFPTypeInSSEReg(VT)) // FPStack?
Evan Cheng3f41d662007-10-08 22:16:29 +00004975 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
Chris Lattner1956d152008-01-16 06:19:45 +00004976
Evan Chenge5f62042007-09-29 00:00:36 +00004977 if ((Opc == X86ISD::CMP ||
4978 Opc == X86ISD::COMI ||
4979 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
Evan Cheng3f41d662007-10-08 22:16:29 +00004980 Cond = Cmp;
Evan Cheng0488db92007-09-25 01:57:46 +00004981 addTest = false;
4982 }
4983 }
4984
4985 if (addTest) {
4986 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
Evan Cheng3f41d662007-10-08 22:16:29 +00004987 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
Evan Cheng0488db92007-09-25 01:57:46 +00004988 }
4989
Duncan Sands83ec4b62008-06-06 12:08:01 +00004990 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
Evan Cheng0488db92007-09-25 01:57:46 +00004991 MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00004992 SmallVector<SDValue, 4> Ops;
Evan Cheng0488db92007-09-25 01:57:46 +00004993 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4994 // condition is true.
4995 Ops.push_back(Op.getOperand(2));
4996 Ops.push_back(Op.getOperand(1));
4997 Ops.push_back(CC);
4998 Ops.push_back(Cond);
Evan Chenge5f62042007-09-29 00:00:36 +00004999 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
Evan Cheng0488db92007-09-25 01:57:46 +00005000}
5001
Dan Gohman475871a2008-07-27 21:46:04 +00005002SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
Evan Cheng734503b2006-09-11 02:19:56 +00005003 bool addTest = true;
Dan Gohman475871a2008-07-27 21:46:04 +00005004 SDValue Chain = Op.getOperand(0);
5005 SDValue Cond = Op.getOperand(1);
5006 SDValue Dest = Op.getOperand(2);
5007 SDValue CC;
Evan Cheng734503b2006-09-11 02:19:56 +00005008
Evan Cheng0db9fe62006-04-25 20:13:52 +00005009 if (Cond.getOpcode() == ISD::SETCC)
Evan Chenge5f62042007-09-29 00:00:36 +00005010 Cond = LowerSETCC(Cond, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005011
Evan Cheng3f41d662007-10-08 22:16:29 +00005012 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5013 // setting operand in place of the X86ISD::SETCC.
Evan Cheng0db9fe62006-04-25 20:13:52 +00005014 if (Cond.getOpcode() == X86ISD::SETCC) {
Evan Cheng734503b2006-09-11 02:19:56 +00005015 CC = Cond.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005016
Dan Gohman475871a2008-07-27 21:46:04 +00005017 SDValue Cmp = Cond.getOperand(1);
Evan Cheng734503b2006-09-11 02:19:56 +00005018 unsigned Opc = Cmp.getOpcode();
Evan Chenge5f62042007-09-29 00:00:36 +00005019 if (Opc == X86ISD::CMP ||
5020 Opc == X86ISD::COMI ||
5021 Opc == X86ISD::UCOMI) {
Evan Cheng3f41d662007-10-08 22:16:29 +00005022 Cond = Cmp;
Evan Cheng0488db92007-09-25 01:57:46 +00005023 addTest = false;
5024 }
5025 }
5026
5027 if (addTest) {
5028 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
Evan Chenge5f62042007-09-29 00:00:36 +00005029 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
Evan Cheng0488db92007-09-25 01:57:46 +00005030 }
Evan Chenge5f62042007-09-29 00:00:36 +00005031 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
Evan Cheng0488db92007-09-25 01:57:46 +00005032 Chain, Op.getOperand(2), CC, Cond);
5033}
5034
Anton Korobeynikove060b532007-04-17 19:34:00 +00005035
5036// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5037// Calls to _alloca is needed to probe the stack when allocating more than 4k
5038// bytes in one go. Touching the stack at 4K increments is necessary to ensure
5039// that the guard pages used by the OS virtual memory manager are allocated in
5040// correct sequence.
Dan Gohman475871a2008-07-27 21:46:04 +00005041SDValue
5042X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00005043 SelectionDAG &DAG) {
Anton Korobeynikove060b532007-04-17 19:34:00 +00005044 assert(Subtarget->isTargetCygMing() &&
5045 "This should be used only on Cygwin/Mingw targets");
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005046
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00005047 // Get the inputs.
Dan Gohman475871a2008-07-27 21:46:04 +00005048 SDValue Chain = Op.getOperand(0);
5049 SDValue Size = Op.getOperand(1);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00005050 // FIXME: Ensure alignment here
5051
Dan Gohman475871a2008-07-27 21:46:04 +00005052 SDValue Flag;
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005053
Duncan Sands83ec4b62008-06-06 12:08:01 +00005054 MVT IntPtr = getPointerTy();
5055 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00005056
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005057 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0));
5058
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00005059 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
5060 Flag = Chain.getValue(1);
5061
5062 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00005063 SDValue Ops[] = { Chain,
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00005064 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5065 DAG.getRegister(X86::EAX, IntPtr),
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005066 DAG.getRegister(X86StackPtr, SPTy),
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00005067 Flag };
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005068 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00005069 Flag = Chain.getValue(1);
5070
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005071 Chain = DAG.getCALLSEQ_END(Chain,
5072 DAG.getIntPtrConstant(0),
5073 DAG.getIntPtrConstant(0),
5074 Flag);
5075
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00005076 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
Anton Korobeynikov096b4612008-06-11 20:16:42 +00005077
Dan Gohman475871a2008-07-27 21:46:04 +00005078 SDValue Ops1[2] = { Chain.getValue(0), Chain };
Duncan Sands4bdcb612008-07-02 17:40:58 +00005079 return DAG.getMergeValues(Ops1, 2);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00005080}
5081
Dan Gohman475871a2008-07-27 21:46:04 +00005082SDValue
Dan Gohman707e0182008-04-12 04:36:06 +00005083X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
Evan Cheng1887c1c2008-08-21 21:00:15 +00005084 SDValue Chain,
5085 SDValue Dst, SDValue Src,
5086 SDValue Size, unsigned Align,
Dan Gohman1f13c682008-04-28 17:15:20 +00005087 const Value *DstSV, uint64_t DstSVOff) {
Dan Gohman707e0182008-04-12 04:36:06 +00005088 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005089
Dan Gohman707e0182008-04-12 04:36:06 +00005090 /// If not DWORD aligned or size is more than the threshold, call the library.
5091 /// The libc version is likely to be faster for these cases. It can use the
5092 /// address value and run time information about the CPU.
Evan Cheng1887c1c2008-08-21 21:00:15 +00005093 if ((Align & 3) != 0 ||
Dan Gohman707e0182008-04-12 04:36:06 +00005094 !ConstantSize ||
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005095 ConstantSize->getZExtValue() >
5096 getSubtarget()->getMaxInlineSizeThreshold()) {
Dan Gohman475871a2008-07-27 21:46:04 +00005097 SDValue InFlag(0, 0);
Dan Gohman68d599d2008-04-01 20:38:36 +00005098
5099 // Check to see if there is a specialized entry-point for memory zeroing.
Dan Gohman707e0182008-04-12 04:36:06 +00005100 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5101 if (const char *bzeroEntry =
5102 V && V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00005103 MVT IntPtr = getPointerTy();
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00005104 const Type *IntPtrTy = TD->getIntPtrType();
Dan Gohman707e0182008-04-12 04:36:06 +00005105 TargetLowering::ArgListTy Args;
5106 TargetLowering::ArgListEntry Entry;
5107 Entry.Node = Dst;
Dan Gohman68d599d2008-04-01 20:38:36 +00005108 Entry.Ty = IntPtrTy;
5109 Args.push_back(Entry);
Dan Gohman707e0182008-04-12 04:36:06 +00005110 Entry.Node = Size;
5111 Args.push_back(Entry);
Dan Gohman475871a2008-07-27 21:46:04 +00005112 std::pair<SDValue,SDValue> CallResult =
Dan Gohman707e0182008-04-12 04:36:06 +00005113 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C,
5114 false, DAG.getExternalSymbol(bzeroEntry, IntPtr),
5115 Args, DAG);
5116 return CallResult.second;
Dan Gohman68d599d2008-04-01 20:38:36 +00005117 }
5118
Dan Gohman707e0182008-04-12 04:36:06 +00005119 // Otherwise have the target-independent code call memset.
Dan Gohman475871a2008-07-27 21:46:04 +00005120 return SDValue();
Evan Cheng48090aa2006-03-21 23:01:21 +00005121 }
Evan Chengb9df0ca2006-03-22 02:53:00 +00005122
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005123 uint64_t SizeVal = ConstantSize->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +00005124 SDValue InFlag(0, 0);
Duncan Sands83ec4b62008-06-06 12:08:01 +00005125 MVT AVT;
Dan Gohman475871a2008-07-27 21:46:04 +00005126 SDValue Count;
Dan Gohman707e0182008-04-12 04:36:06 +00005127 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005128 unsigned BytesLeft = 0;
5129 bool TwoRepStos = false;
5130 if (ValC) {
5131 unsigned ValReg;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005132 uint64_t Val = ValC->getZExtValue() & 255;
Evan Cheng5ced1d82006-04-06 23:23:56 +00005133
Evan Cheng0db9fe62006-04-25 20:13:52 +00005134 // If the value is a constant, then we can potentially use larger sets.
5135 switch (Align & 3) {
Evan Cheng1887c1c2008-08-21 21:00:15 +00005136 case 2: // WORD aligned
5137 AVT = MVT::i16;
5138 ValReg = X86::AX;
5139 Val = (Val << 8) | Val;
5140 break;
5141 case 0: // DWORD aligned
5142 AVT = MVT::i32;
5143 ValReg = X86::EAX;
5144 Val = (Val << 8) | Val;
5145 Val = (Val << 16) | Val;
5146 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5147 AVT = MVT::i64;
5148 ValReg = X86::RAX;
5149 Val = (Val << 32) | Val;
5150 }
5151 break;
5152 default: // Byte aligned
5153 AVT = MVT::i8;
5154 ValReg = X86::AL;
5155 Count = DAG.getIntPtrConstant(SizeVal);
5156 break;
Evan Cheng80d428c2006-04-19 22:48:17 +00005157 }
5158
Duncan Sands8e4eb092008-06-08 20:54:56 +00005159 if (AVT.bitsGT(MVT::i8)) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00005160 unsigned UBytes = AVT.getSizeInBits() / 8;
Dan Gohman707e0182008-04-12 04:36:06 +00005161 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5162 BytesLeft = SizeVal % UBytes;
Evan Cheng25ab6902006-09-08 06:48:29 +00005163 }
5164
Evan Cheng0db9fe62006-04-25 20:13:52 +00005165 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
5166 InFlag);
5167 InFlag = Chain.getValue(1);
5168 } else {
5169 AVT = MVT::i8;
Dan Gohmanbcda2852008-04-16 01:32:32 +00005170 Count = DAG.getIntPtrConstant(SizeVal);
Dan Gohman707e0182008-04-12 04:36:06 +00005171 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005172 InFlag = Chain.getValue(1);
Evan Chengb9df0ca2006-03-22 02:53:00 +00005173 }
Evan Chengc78d3b42006-04-24 18:01:45 +00005174
Evan Cheng25ab6902006-09-08 06:48:29 +00005175 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5176 Count, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005177 InFlag = Chain.getValue(1);
Evan Cheng25ab6902006-09-08 06:48:29 +00005178 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
Dan Gohman707e0182008-04-12 04:36:06 +00005179 Dst, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005180 InFlag = Chain.getValue(1);
Evan Chenga0b3afb2006-03-27 07:00:16 +00005181
Chris Lattnerd96d0722007-02-25 06:40:16 +00005182 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00005183 SmallVector<SDValue, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00005184 Ops.push_back(Chain);
5185 Ops.push_back(DAG.getValueType(AVT));
5186 Ops.push_back(InFlag);
Evan Cheng311ace02006-08-11 07:35:45 +00005187 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
Evan Chengc78d3b42006-04-24 18:01:45 +00005188
Evan Cheng0db9fe62006-04-25 20:13:52 +00005189 if (TwoRepStos) {
5190 InFlag = Chain.getValue(1);
Dan Gohman707e0182008-04-12 04:36:06 +00005191 Count = Size;
Duncan Sands83ec4b62008-06-06 12:08:01 +00005192 MVT CVT = Count.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +00005193 SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
Evan Cheng25ab6902006-09-08 06:48:29 +00005194 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5195 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
5196 Left, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005197 InFlag = Chain.getValue(1);
Chris Lattnerd96d0722007-02-25 06:40:16 +00005198 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005199 Ops.clear();
5200 Ops.push_back(Chain);
5201 Ops.push_back(DAG.getValueType(MVT::i8));
5202 Ops.push_back(InFlag);
Evan Cheng311ace02006-08-11 07:35:45 +00005203 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00005204 } else if (BytesLeft) {
Dan Gohman707e0182008-04-12 04:36:06 +00005205 // Handle the last 1 - 7 bytes.
5206 unsigned Offset = SizeVal - BytesLeft;
Duncan Sands83ec4b62008-06-06 12:08:01 +00005207 MVT AddrVT = Dst.getValueType();
5208 MVT SizeVT = Size.getValueType();
Dan Gohman707e0182008-04-12 04:36:06 +00005209
5210 Chain = DAG.getMemset(Chain,
5211 DAG.getNode(ISD::ADD, AddrVT, Dst,
5212 DAG.getConstant(Offset, AddrVT)),
5213 Src,
5214 DAG.getConstant(BytesLeft, SizeVT),
Dan Gohman1f13c682008-04-28 17:15:20 +00005215 Align, DstSV, DstSVOff + Offset);
Evan Cheng386031a2006-03-24 07:29:27 +00005216 }
Evan Cheng11e15b32006-04-03 20:53:28 +00005217
Dan Gohman707e0182008-04-12 04:36:06 +00005218 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
Evan Cheng0db9fe62006-04-25 20:13:52 +00005219 return Chain;
5220}
Evan Cheng11e15b32006-04-03 20:53:28 +00005221
Dan Gohman475871a2008-07-27 21:46:04 +00005222SDValue
Dan Gohman707e0182008-04-12 04:36:06 +00005223X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
Evan Cheng1887c1c2008-08-21 21:00:15 +00005224 SDValue Chain, SDValue Dst, SDValue Src,
5225 SDValue Size, unsigned Align,
5226 bool AlwaysInline,
5227 const Value *DstSV, uint64_t DstSVOff,
5228 const Value *SrcSV, uint64_t SrcSVOff) {
Dan Gohman707e0182008-04-12 04:36:06 +00005229 // This requires the copy size to be a constant, preferrably
5230 // within a subtarget-specific limit.
5231 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5232 if (!ConstantSize)
Dan Gohman475871a2008-07-27 21:46:04 +00005233 return SDValue();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005234 uint64_t SizeVal = ConstantSize->getZExtValue();
Dan Gohman707e0182008-04-12 04:36:06 +00005235 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
Dan Gohman475871a2008-07-27 21:46:04 +00005236 return SDValue();
Dan Gohman707e0182008-04-12 04:36:06 +00005237
Evan Cheng1887c1c2008-08-21 21:00:15 +00005238 /// If not DWORD aligned, call the library.
5239 if ((Align & 3) != 0)
5240 return SDValue();
5241
5242 // DWORD aligned
5243 MVT AVT = MVT::i32;
5244 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
Dan Gohman707e0182008-04-12 04:36:06 +00005245 AVT = MVT::i64;
Evan Cheng0db9fe62006-04-25 20:13:52 +00005246
Duncan Sands83ec4b62008-06-06 12:08:01 +00005247 unsigned UBytes = AVT.getSizeInBits() / 8;
Dan Gohman707e0182008-04-12 04:36:06 +00005248 unsigned CountVal = SizeVal / UBytes;
Dan Gohman475871a2008-07-27 21:46:04 +00005249 SDValue Count = DAG.getIntPtrConstant(CountVal);
Evan Cheng1887c1c2008-08-21 21:00:15 +00005250 unsigned BytesLeft = SizeVal % UBytes;
Evan Cheng25ab6902006-09-08 06:48:29 +00005251
Dan Gohman475871a2008-07-27 21:46:04 +00005252 SDValue InFlag(0, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00005253 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5254 Count, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005255 InFlag = Chain.getValue(1);
Evan Cheng25ab6902006-09-08 06:48:29 +00005256 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
Dan Gohman707e0182008-04-12 04:36:06 +00005257 Dst, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005258 InFlag = Chain.getValue(1);
Evan Cheng25ab6902006-09-08 06:48:29 +00005259 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
Dan Gohman707e0182008-04-12 04:36:06 +00005260 Src, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005261 InFlag = Chain.getValue(1);
5262
Chris Lattnerd96d0722007-02-25 06:40:16 +00005263 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00005264 SmallVector<SDValue, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00005265 Ops.push_back(Chain);
5266 Ops.push_back(DAG.getValueType(AVT));
5267 Ops.push_back(InFlag);
Dan Gohman475871a2008-07-27 21:46:04 +00005268 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00005269
Dan Gohman475871a2008-07-27 21:46:04 +00005270 SmallVector<SDValue, 4> Results;
Evan Cheng2749c722008-04-25 00:26:43 +00005271 Results.push_back(RepMovs);
Rafael Espindola068317b2007-09-28 12:53:01 +00005272 if (BytesLeft) {
Dan Gohman707e0182008-04-12 04:36:06 +00005273 // Handle the last 1 - 7 bytes.
5274 unsigned Offset = SizeVal - BytesLeft;
Duncan Sands83ec4b62008-06-06 12:08:01 +00005275 MVT DstVT = Dst.getValueType();
5276 MVT SrcVT = Src.getValueType();
5277 MVT SizeVT = Size.getValueType();
Evan Cheng2749c722008-04-25 00:26:43 +00005278 Results.push_back(DAG.getMemcpy(Chain,
Dan Gohman707e0182008-04-12 04:36:06 +00005279 DAG.getNode(ISD::ADD, DstVT, Dst,
Evan Cheng2749c722008-04-25 00:26:43 +00005280 DAG.getConstant(Offset, DstVT)),
Dan Gohman707e0182008-04-12 04:36:06 +00005281 DAG.getNode(ISD::ADD, SrcVT, Src,
Evan Cheng2749c722008-04-25 00:26:43 +00005282 DAG.getConstant(Offset, SrcVT)),
Dan Gohman707e0182008-04-12 04:36:06 +00005283 DAG.getConstant(BytesLeft, SizeVT),
5284 Align, AlwaysInline,
Dan Gohman1f13c682008-04-28 17:15:20 +00005285 DstSV, DstSVOff + Offset,
5286 SrcSV, SrcSVOff + Offset));
Evan Chengb067a1e2006-03-31 19:22:53 +00005287 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00005288
Dan Gohman707e0182008-04-12 04:36:06 +00005289 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00005290}
5291
Chris Lattner27a6c732007-11-24 07:07:01 +00005292/// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
5293SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
Chris Lattnerd96d0722007-02-25 06:40:16 +00005294 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00005295 SDValue TheChain = N->getOperand(0);
5296 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
Evan Cheng3fa9dff2006-11-29 08:28:13 +00005297 if (Subtarget->is64Bit()) {
Dan Gohman475871a2008-07-27 21:46:04 +00005298 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
5299 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
Chris Lattner27a6c732007-11-24 07:07:01 +00005300 MVT::i64, rax.getValue(2));
Dan Gohman475871a2008-07-27 21:46:04 +00005301 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
Evan Cheng3fa9dff2006-11-29 08:28:13 +00005302 DAG.getConstant(32, MVT::i8));
Dan Gohman475871a2008-07-27 21:46:04 +00005303 SDValue Ops[] = {
Chris Lattner27a6c732007-11-24 07:07:01 +00005304 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
Chris Lattner5a88b832007-02-25 07:10:00 +00005305 };
Chris Lattnerd96d0722007-02-25 06:40:16 +00005306
Gabor Greifba36cb52008-08-28 21:40:38 +00005307 return DAG.getMergeValues(Ops, 2).getNode();
Evan Cheng3fa9dff2006-11-29 08:28:13 +00005308 }
Chris Lattner5a88b832007-02-25 07:10:00 +00005309
Dan Gohman475871a2008-07-27 21:46:04 +00005310 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
5311 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
Chris Lattner27a6c732007-11-24 07:07:01 +00005312 MVT::i32, eax.getValue(2));
5313 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
Dan Gohman475871a2008-07-27 21:46:04 +00005314 SDValue Ops[] = { eax, edx };
Chris Lattner27a6c732007-11-24 07:07:01 +00005315 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
5316
5317 // Use a MERGE_VALUES to return the value and chain.
5318 Ops[1] = edx.getValue(1);
Gabor Greifba36cb52008-08-28 21:40:38 +00005319 return DAG.getMergeValues(Ops, 2).getNode();
Evan Cheng0db9fe62006-04-25 20:13:52 +00005320}
5321
Dan Gohman475871a2008-07-27 21:46:04 +00005322SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
Dan Gohman69de1932008-02-06 22:27:42 +00005323 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Evan Cheng8b2794a2006-10-13 21:14:26 +00005324
Evan Cheng25ab6902006-09-08 06:48:29 +00005325 if (!Subtarget->is64Bit()) {
5326 // vastart just stores the address of the VarArgsFrameIndex slot into the
5327 // memory location argument.
Dan Gohman475871a2008-07-27 21:46:04 +00005328 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Dan Gohman69de1932008-02-06 22:27:42 +00005329 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00005330 }
5331
5332 // __va_list_tag:
5333 // gp_offset (0 - 6 * 8)
5334 // fp_offset (48 - 48 + 8 * 16)
5335 // overflow_arg_area (point to parameters coming in memory).
5336 // reg_save_area
Dan Gohman475871a2008-07-27 21:46:04 +00005337 SmallVector<SDValue, 8> MemOps;
5338 SDValue FIN = Op.getOperand(1);
Evan Cheng25ab6902006-09-08 06:48:29 +00005339 // Store gp_offset
Dan Gohman475871a2008-07-27 21:46:04 +00005340 SDValue Store = DAG.getStore(Op.getOperand(0),
Evan Cheng786225a2006-10-05 23:01:46 +00005341 DAG.getConstant(VarArgsGPOffset, MVT::i32),
Dan Gohman69de1932008-02-06 22:27:42 +00005342 FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00005343 MemOps.push_back(Store);
5344
5345 // Store fp_offset
Chris Lattner0bd48932008-01-17 07:00:52 +00005346 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
Evan Cheng786225a2006-10-05 23:01:46 +00005347 Store = DAG.getStore(Op.getOperand(0),
5348 DAG.getConstant(VarArgsFPOffset, MVT::i32),
Dan Gohman69de1932008-02-06 22:27:42 +00005349 FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00005350 MemOps.push_back(Store);
5351
5352 // Store ptr to overflow_arg_area
Chris Lattner0bd48932008-01-17 07:00:52 +00005353 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
Dan Gohman475871a2008-07-27 21:46:04 +00005354 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Dan Gohman69de1932008-02-06 22:27:42 +00005355 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00005356 MemOps.push_back(Store);
5357
5358 // Store ptr to reg_save_area.
Chris Lattner0bd48932008-01-17 07:00:52 +00005359 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
Dan Gohman475871a2008-07-27 21:46:04 +00005360 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
Dan Gohman69de1932008-02-06 22:27:42 +00005361 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00005362 MemOps.push_back(Store);
5363 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00005364}
5365
Dan Gohman475871a2008-07-27 21:46:04 +00005366SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
Dan Gohman9018e832008-05-10 01:26:14 +00005367 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5368 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
Dan Gohman475871a2008-07-27 21:46:04 +00005369 SDValue Chain = Op.getOperand(0);
5370 SDValue SrcPtr = Op.getOperand(1);
5371 SDValue SrcSV = Op.getOperand(2);
Dan Gohman9018e832008-05-10 01:26:14 +00005372
5373 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5374 abort();
Dan Gohman475871a2008-07-27 21:46:04 +00005375 return SDValue();
Dan Gohman9018e832008-05-10 01:26:14 +00005376}
5377
Dan Gohman475871a2008-07-27 21:46:04 +00005378SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
Evan Chengae642192007-03-02 23:16:35 +00005379 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
Dan Gohman28269132008-04-18 20:55:41 +00005380 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
Dan Gohman475871a2008-07-27 21:46:04 +00005381 SDValue Chain = Op.getOperand(0);
5382 SDValue DstPtr = Op.getOperand(1);
5383 SDValue SrcPtr = Op.getOperand(2);
Dan Gohman69de1932008-02-06 22:27:42 +00005384 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5385 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
Evan Chengae642192007-03-02 23:16:35 +00005386
Dan Gohman28269132008-04-18 20:55:41 +00005387 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5388 DAG.getIntPtrConstant(24), 8, false,
5389 DstSV, 0, SrcSV, 0);
Evan Chengae642192007-03-02 23:16:35 +00005390}
5391
Dan Gohman475871a2008-07-27 21:46:04 +00005392SDValue
5393X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005394 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
Evan Cheng0db9fe62006-04-25 20:13:52 +00005395 switch (IntNo) {
Dan Gohman475871a2008-07-27 21:46:04 +00005396 default: return SDValue(); // Don't custom lower most intrinsics.
Evan Cheng5759f972008-05-04 09:15:50 +00005397 // Comparison intrinsics.
Evan Cheng0db9fe62006-04-25 20:13:52 +00005398 case Intrinsic::x86_sse_comieq_ss:
5399 case Intrinsic::x86_sse_comilt_ss:
5400 case Intrinsic::x86_sse_comile_ss:
5401 case Intrinsic::x86_sse_comigt_ss:
5402 case Intrinsic::x86_sse_comige_ss:
5403 case Intrinsic::x86_sse_comineq_ss:
5404 case Intrinsic::x86_sse_ucomieq_ss:
5405 case Intrinsic::x86_sse_ucomilt_ss:
5406 case Intrinsic::x86_sse_ucomile_ss:
5407 case Intrinsic::x86_sse_ucomigt_ss:
5408 case Intrinsic::x86_sse_ucomige_ss:
5409 case Intrinsic::x86_sse_ucomineq_ss:
5410 case Intrinsic::x86_sse2_comieq_sd:
5411 case Intrinsic::x86_sse2_comilt_sd:
5412 case Intrinsic::x86_sse2_comile_sd:
5413 case Intrinsic::x86_sse2_comigt_sd:
5414 case Intrinsic::x86_sse2_comige_sd:
5415 case Intrinsic::x86_sse2_comineq_sd:
5416 case Intrinsic::x86_sse2_ucomieq_sd:
5417 case Intrinsic::x86_sse2_ucomilt_sd:
5418 case Intrinsic::x86_sse2_ucomile_sd:
5419 case Intrinsic::x86_sse2_ucomigt_sd:
5420 case Intrinsic::x86_sse2_ucomige_sd:
5421 case Intrinsic::x86_sse2_ucomineq_sd: {
5422 unsigned Opc = 0;
5423 ISD::CondCode CC = ISD::SETCC_INVALID;
5424 switch (IntNo) {
5425 default: break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005426 case Intrinsic::x86_sse_comieq_ss:
5427 case Intrinsic::x86_sse2_comieq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005428 Opc = X86ISD::COMI;
5429 CC = ISD::SETEQ;
5430 break;
Evan Cheng6be2c582006-04-05 23:38:46 +00005431 case Intrinsic::x86_sse_comilt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005432 case Intrinsic::x86_sse2_comilt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005433 Opc = X86ISD::COMI;
5434 CC = ISD::SETLT;
5435 break;
5436 case Intrinsic::x86_sse_comile_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005437 case Intrinsic::x86_sse2_comile_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005438 Opc = X86ISD::COMI;
5439 CC = ISD::SETLE;
5440 break;
5441 case Intrinsic::x86_sse_comigt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005442 case Intrinsic::x86_sse2_comigt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005443 Opc = X86ISD::COMI;
5444 CC = ISD::SETGT;
5445 break;
5446 case Intrinsic::x86_sse_comige_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005447 case Intrinsic::x86_sse2_comige_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005448 Opc = X86ISD::COMI;
5449 CC = ISD::SETGE;
5450 break;
5451 case Intrinsic::x86_sse_comineq_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005452 case Intrinsic::x86_sse2_comineq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005453 Opc = X86ISD::COMI;
5454 CC = ISD::SETNE;
5455 break;
5456 case Intrinsic::x86_sse_ucomieq_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005457 case Intrinsic::x86_sse2_ucomieq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005458 Opc = X86ISD::UCOMI;
5459 CC = ISD::SETEQ;
5460 break;
5461 case Intrinsic::x86_sse_ucomilt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005462 case Intrinsic::x86_sse2_ucomilt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005463 Opc = X86ISD::UCOMI;
5464 CC = ISD::SETLT;
5465 break;
5466 case Intrinsic::x86_sse_ucomile_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005467 case Intrinsic::x86_sse2_ucomile_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005468 Opc = X86ISD::UCOMI;
5469 CC = ISD::SETLE;
5470 break;
5471 case Intrinsic::x86_sse_ucomigt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005472 case Intrinsic::x86_sse2_ucomigt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005473 Opc = X86ISD::UCOMI;
5474 CC = ISD::SETGT;
5475 break;
5476 case Intrinsic::x86_sse_ucomige_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00005477 case Intrinsic::x86_sse2_ucomige_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00005478 Opc = X86ISD::UCOMI;
5479 CC = ISD::SETGE;
5480 break;
5481 case Intrinsic::x86_sse_ucomineq_ss:
5482 case Intrinsic::x86_sse2_ucomineq_sd:
5483 Opc = X86ISD::UCOMI;
5484 CC = ISD::SETNE;
5485 break;
Evan Cheng6be2c582006-04-05 23:38:46 +00005486 }
Evan Cheng734503b2006-09-11 02:19:56 +00005487
Evan Cheng0db9fe62006-04-25 20:13:52 +00005488 unsigned X86CC;
Dan Gohman475871a2008-07-27 21:46:04 +00005489 SDValue LHS = Op.getOperand(1);
5490 SDValue RHS = Op.getOperand(2);
Chris Lattnerf9570512006-09-13 03:22:10 +00005491 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
Evan Cheng734503b2006-09-11 02:19:56 +00005492
Dan Gohman475871a2008-07-27 21:46:04 +00005493 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5494 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0ac3fc22008-08-17 19:22:34 +00005495 DAG.getConstant(X86CC, MVT::i8), Cond);
5496 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC);
Evan Cheng6be2c582006-04-05 23:38:46 +00005497 }
Evan Cheng5759f972008-05-04 09:15:50 +00005498
5499 // Fix vector shift instructions where the last operand is a non-immediate
5500 // i32 value.
5501 case Intrinsic::x86_sse2_pslli_w:
5502 case Intrinsic::x86_sse2_pslli_d:
5503 case Intrinsic::x86_sse2_pslli_q:
5504 case Intrinsic::x86_sse2_psrli_w:
5505 case Intrinsic::x86_sse2_psrli_d:
5506 case Intrinsic::x86_sse2_psrli_q:
5507 case Intrinsic::x86_sse2_psrai_w:
5508 case Intrinsic::x86_sse2_psrai_d:
5509 case Intrinsic::x86_mmx_pslli_w:
5510 case Intrinsic::x86_mmx_pslli_d:
5511 case Intrinsic::x86_mmx_pslli_q:
5512 case Intrinsic::x86_mmx_psrli_w:
5513 case Intrinsic::x86_mmx_psrli_d:
5514 case Intrinsic::x86_mmx_psrli_q:
5515 case Intrinsic::x86_mmx_psrai_w:
5516 case Intrinsic::x86_mmx_psrai_d: {
Dan Gohman475871a2008-07-27 21:46:04 +00005517 SDValue ShAmt = Op.getOperand(2);
Evan Cheng5759f972008-05-04 09:15:50 +00005518 if (isa<ConstantSDNode>(ShAmt))
Dan Gohman475871a2008-07-27 21:46:04 +00005519 return SDValue();
Evan Cheng5759f972008-05-04 09:15:50 +00005520
5521 unsigned NewIntNo = 0;
Duncan Sands83ec4b62008-06-06 12:08:01 +00005522 MVT ShAmtVT = MVT::v4i32;
Evan Cheng5759f972008-05-04 09:15:50 +00005523 switch (IntNo) {
5524 case Intrinsic::x86_sse2_pslli_w:
5525 NewIntNo = Intrinsic::x86_sse2_psll_w;
5526 break;
5527 case Intrinsic::x86_sse2_pslli_d:
5528 NewIntNo = Intrinsic::x86_sse2_psll_d;
5529 break;
5530 case Intrinsic::x86_sse2_pslli_q:
5531 NewIntNo = Intrinsic::x86_sse2_psll_q;
5532 break;
5533 case Intrinsic::x86_sse2_psrli_w:
5534 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5535 break;
5536 case Intrinsic::x86_sse2_psrli_d:
5537 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5538 break;
5539 case Intrinsic::x86_sse2_psrli_q:
5540 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5541 break;
5542 case Intrinsic::x86_sse2_psrai_w:
5543 NewIntNo = Intrinsic::x86_sse2_psra_w;
5544 break;
5545 case Intrinsic::x86_sse2_psrai_d:
5546 NewIntNo = Intrinsic::x86_sse2_psra_d;
5547 break;
5548 default: {
5549 ShAmtVT = MVT::v2i32;
5550 switch (IntNo) {
5551 case Intrinsic::x86_mmx_pslli_w:
5552 NewIntNo = Intrinsic::x86_mmx_psll_w;
5553 break;
5554 case Intrinsic::x86_mmx_pslli_d:
5555 NewIntNo = Intrinsic::x86_mmx_psll_d;
5556 break;
5557 case Intrinsic::x86_mmx_pslli_q:
5558 NewIntNo = Intrinsic::x86_mmx_psll_q;
5559 break;
5560 case Intrinsic::x86_mmx_psrli_w:
5561 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5562 break;
5563 case Intrinsic::x86_mmx_psrli_d:
5564 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5565 break;
5566 case Intrinsic::x86_mmx_psrli_q:
5567 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5568 break;
5569 case Intrinsic::x86_mmx_psrai_w:
5570 NewIntNo = Intrinsic::x86_mmx_psra_w;
5571 break;
5572 case Intrinsic::x86_mmx_psrai_d:
5573 NewIntNo = Intrinsic::x86_mmx_psra_d;
5574 break;
5575 default: abort(); // Can't reach here.
5576 }
5577 break;
5578 }
5579 }
Duncan Sands83ec4b62008-06-06 12:08:01 +00005580 MVT VT = Op.getValueType();
Evan Cheng5759f972008-05-04 09:15:50 +00005581 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5582 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5583 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5584 DAG.getConstant(NewIntNo, MVT::i32),
5585 Op.getOperand(1), ShAmt);
5586 }
Evan Cheng38bcbaf2005-12-23 07:31:11 +00005587 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00005588}
Evan Cheng72261582005-12-20 06:22:03 +00005589
Dan Gohman475871a2008-07-27 21:46:04 +00005590SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
Nate Begemanbcc5f362007-01-29 22:58:52 +00005591 // Depths > 0 not supported yet!
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005592 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
Dan Gohman475871a2008-07-27 21:46:04 +00005593 return SDValue();
Nate Begemanbcc5f362007-01-29 22:58:52 +00005594
5595 // Just load the return address
Dan Gohman475871a2008-07-27 21:46:04 +00005596 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
Nate Begemanbcc5f362007-01-29 22:58:52 +00005597 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5598}
5599
Dan Gohman475871a2008-07-27 21:46:04 +00005600SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
Nate Begemanbcc5f362007-01-29 22:58:52 +00005601 // Depths > 0 not supported yet!
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005602 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
Dan Gohman475871a2008-07-27 21:46:04 +00005603 return SDValue();
Anton Korobeynikov260a6b82008-09-08 21:12:11 +00005604
Dan Gohman475871a2008-07-27 21:46:04 +00005605 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
Anton Korobeynikov260a6b82008-09-08 21:12:11 +00005606 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00005607 DAG.getIntPtrConstant(TD->getPointerSize()));
Nate Begemanbcc5f362007-01-29 22:58:52 +00005608}
5609
Dan Gohman475871a2008-07-27 21:46:04 +00005610SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
Anton Korobeynikov260a6b82008-09-08 21:12:11 +00005611 SelectionDAG &DAG) {
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00005612 return DAG.getIntPtrConstant(2*TD->getPointerSize());
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005613}
5614
Dan Gohman475871a2008-07-27 21:46:04 +00005615SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005616{
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005617 MachineFunction &MF = DAG.getMachineFunction();
Dan Gohman475871a2008-07-27 21:46:04 +00005618 SDValue Chain = Op.getOperand(0);
5619 SDValue Offset = Op.getOperand(1);
5620 SDValue Handler = Op.getOperand(2);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005621
Anton Korobeynikovb84c1672008-09-08 21:12:47 +00005622 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
5623 getPointerTy());
5624 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005625
Dan Gohman475871a2008-07-27 21:46:04 +00005626 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00005627 DAG.getIntPtrConstant(-TD->getPointerSize()));
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005628 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5629 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
Anton Korobeynikovb84c1672008-09-08 21:12:47 +00005630 Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr);
5631 MF.getRegInfo().addLiveOut(StoreAddrReg);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005632
Anton Korobeynikovb84c1672008-09-08 21:12:47 +00005633 return DAG.getNode(X86ISD::EH_RETURN,
5634 MVT::Other,
5635 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005636}
5637
Dan Gohman475871a2008-07-27 21:46:04 +00005638SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
Duncan Sandsb116fac2007-07-27 20:02:49 +00005639 SelectionDAG &DAG) {
Dan Gohman475871a2008-07-27 21:46:04 +00005640 SDValue Root = Op.getOperand(0);
5641 SDValue Trmp = Op.getOperand(1); // trampoline
5642 SDValue FPtr = Op.getOperand(2); // nested function
5643 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
Duncan Sandsb116fac2007-07-27 20:02:49 +00005644
Dan Gohman69de1932008-02-06 22:27:42 +00005645 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
Duncan Sandsb116fac2007-07-27 20:02:49 +00005646
Duncan Sands339e14f2008-01-16 22:55:25 +00005647 const X86InstrInfo *TII =
5648 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5649
Duncan Sandsb116fac2007-07-27 20:02:49 +00005650 if (Subtarget->is64Bit()) {
Dan Gohman475871a2008-07-27 21:46:04 +00005651 SDValue OutChains[6];
Duncan Sands339e14f2008-01-16 22:55:25 +00005652
5653 // Large code-model.
5654
5655 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5656 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5657
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +00005658 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
5659 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
Duncan Sands339e14f2008-01-16 22:55:25 +00005660
5661 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5662
5663 // Load the pointer to the nested function into R11.
5664 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
Dan Gohman475871a2008-07-27 21:46:04 +00005665 SDValue Addr = Trmp;
Duncan Sands339e14f2008-01-16 22:55:25 +00005666 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00005667 TrmpAddr, 0);
Duncan Sands339e14f2008-01-16 22:55:25 +00005668
5669 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
Dan Gohman69de1932008-02-06 22:27:42 +00005670 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
Duncan Sands339e14f2008-01-16 22:55:25 +00005671
5672 // Load the 'nest' parameter value into R10.
5673 // R10 is specified in X86CallingConv.td
5674 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5675 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5676 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00005677 TrmpAddr, 10);
Duncan Sands339e14f2008-01-16 22:55:25 +00005678
5679 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
Dan Gohman69de1932008-02-06 22:27:42 +00005680 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
Duncan Sands339e14f2008-01-16 22:55:25 +00005681
5682 // Jump to the nested function.
5683 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5684 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5685 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00005686 TrmpAddr, 20);
Duncan Sands339e14f2008-01-16 22:55:25 +00005687
5688 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5689 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5690 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00005691 TrmpAddr, 22);
Duncan Sands339e14f2008-01-16 22:55:25 +00005692
Dan Gohman475871a2008-07-27 21:46:04 +00005693 SDValue Ops[] =
Duncan Sands339e14f2008-01-16 22:55:25 +00005694 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
Duncan Sands4bdcb612008-07-02 17:40:58 +00005695 return DAG.getMergeValues(Ops, 2);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005696 } else {
Dan Gohmanbbfb9c52008-01-31 01:01:48 +00005697 const Function *Func =
Duncan Sandsb116fac2007-07-27 20:02:49 +00005698 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5699 unsigned CC = Func->getCallingConv();
Duncan Sandsee465742007-08-29 19:01:20 +00005700 unsigned NestReg;
Duncan Sandsb116fac2007-07-27 20:02:49 +00005701
5702 switch (CC) {
5703 default:
5704 assert(0 && "Unsupported calling convention");
5705 case CallingConv::C:
Duncan Sandsb116fac2007-07-27 20:02:49 +00005706 case CallingConv::X86_StdCall: {
5707 // Pass 'nest' parameter in ECX.
5708 // Must be kept in sync with X86CallingConv.td
Duncan Sandsee465742007-08-29 19:01:20 +00005709 NestReg = X86::ECX;
Duncan Sandsb116fac2007-07-27 20:02:49 +00005710
5711 // Check that ECX wasn't needed by an 'inreg' parameter.
5712 const FunctionType *FTy = Func->getFunctionType();
Chris Lattner58d74912008-03-12 17:45:29 +00005713 const PAListPtr &Attrs = Func->getParamAttrs();
Duncan Sandsb116fac2007-07-27 20:02:49 +00005714
Chris Lattner58d74912008-03-12 17:45:29 +00005715 if (!Attrs.isEmpty() && !Func->isVarArg()) {
Duncan Sandsb116fac2007-07-27 20:02:49 +00005716 unsigned InRegCount = 0;
5717 unsigned Idx = 1;
5718
5719 for (FunctionType::param_iterator I = FTy->param_begin(),
5720 E = FTy->param_end(); I != E; ++I, ++Idx)
Chris Lattner58d74912008-03-12 17:45:29 +00005721 if (Attrs.paramHasAttr(Idx, ParamAttr::InReg))
Duncan Sandsb116fac2007-07-27 20:02:49 +00005722 // FIXME: should only count parameters that are lowered to integers.
Anton Korobeynikovbff66b02008-09-09 18:22:57 +00005723 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
Duncan Sandsb116fac2007-07-27 20:02:49 +00005724
5725 if (InRegCount > 2) {
5726 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5727 abort();
5728 }
5729 }
5730 break;
5731 }
5732 case CallingConv::X86_FastCall:
Duncan Sandsbf53c292008-09-10 13:22:10 +00005733 case CallingConv::Fast:
Duncan Sandsb116fac2007-07-27 20:02:49 +00005734 // Pass 'nest' parameter in EAX.
5735 // Must be kept in sync with X86CallingConv.td
Duncan Sandsee465742007-08-29 19:01:20 +00005736 NestReg = X86::EAX;
Duncan Sandsb116fac2007-07-27 20:02:49 +00005737 break;
5738 }
5739
Dan Gohman475871a2008-07-27 21:46:04 +00005740 SDValue OutChains[4];
5741 SDValue Addr, Disp;
Duncan Sandsb116fac2007-07-27 20:02:49 +00005742
5743 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
5744 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
5745
Duncan Sands339e14f2008-01-16 22:55:25 +00005746 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +00005747 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
Duncan Sandsee465742007-08-29 19:01:20 +00005748 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
Dan Gohman69de1932008-02-06 22:27:42 +00005749 Trmp, TrmpAddr, 0);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005750
5751 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
Dan Gohman69de1932008-02-06 22:27:42 +00005752 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005753
Duncan Sands339e14f2008-01-16 22:55:25 +00005754 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005755 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
5756 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
Dan Gohman69de1932008-02-06 22:27:42 +00005757 TrmpAddr, 5, false, 1);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005758
5759 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
Dan Gohman69de1932008-02-06 22:27:42 +00005760 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005761
Dan Gohman475871a2008-07-27 21:46:04 +00005762 SDValue Ops[] =
Duncan Sandsf7331b32007-09-11 14:10:23 +00005763 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
Duncan Sands4bdcb612008-07-02 17:40:58 +00005764 return DAG.getMergeValues(Ops, 2);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005765 }
5766}
5767
Dan Gohman475871a2008-07-27 21:46:04 +00005768SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005769 /*
5770 The rounding mode is in bits 11:10 of FPSR, and has the following
5771 settings:
5772 00 Round to nearest
5773 01 Round to -inf
5774 10 Round to +inf
5775 11 Round to 0
5776
5777 FLT_ROUNDS, on the other hand, expects the following:
5778 -1 Undefined
5779 0 Round to 0
5780 1 Round to nearest
5781 2 Round to +inf
5782 3 Round to -inf
5783
5784 To perform the conversion, we do:
5785 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
5786 */
5787
5788 MachineFunction &MF = DAG.getMachineFunction();
5789 const TargetMachine &TM = MF.getTarget();
5790 const TargetFrameInfo &TFI = *TM.getFrameInfo();
5791 unsigned StackAlignment = TFI.getStackAlignment();
Duncan Sands83ec4b62008-06-06 12:08:01 +00005792 MVT VT = Op.getValueType();
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005793
5794 // Save FP Control Word to stack slot
5795 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
Dan Gohman475871a2008-07-27 21:46:04 +00005796 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005797
Dan Gohman475871a2008-07-27 21:46:04 +00005798 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005799 DAG.getEntryNode(), StackSlot);
5800
5801 // Load FP Control Word from stack slot
Dan Gohman475871a2008-07-27 21:46:04 +00005802 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005803
5804 // Transform as necessary
Dan Gohman475871a2008-07-27 21:46:04 +00005805 SDValue CWD1 =
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005806 DAG.getNode(ISD::SRL, MVT::i16,
5807 DAG.getNode(ISD::AND, MVT::i16,
5808 CWD, DAG.getConstant(0x800, MVT::i16)),
5809 DAG.getConstant(11, MVT::i8));
Dan Gohman475871a2008-07-27 21:46:04 +00005810 SDValue CWD2 =
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005811 DAG.getNode(ISD::SRL, MVT::i16,
5812 DAG.getNode(ISD::AND, MVT::i16,
5813 CWD, DAG.getConstant(0x400, MVT::i16)),
5814 DAG.getConstant(9, MVT::i8));
5815
Dan Gohman475871a2008-07-27 21:46:04 +00005816 SDValue RetVal =
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005817 DAG.getNode(ISD::AND, MVT::i16,
5818 DAG.getNode(ISD::ADD, MVT::i16,
5819 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
5820 DAG.getConstant(1, MVT::i16)),
5821 DAG.getConstant(3, MVT::i16));
5822
5823
Duncan Sands83ec4b62008-06-06 12:08:01 +00005824 return DAG.getNode((VT.getSizeInBits() < 16 ?
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005825 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
5826}
5827
Dan Gohman475871a2008-07-27 21:46:04 +00005828SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00005829 MVT VT = Op.getValueType();
5830 MVT OpVT = VT;
5831 unsigned NumBits = VT.getSizeInBits();
Evan Cheng18efe262007-12-14 02:13:44 +00005832
5833 Op = Op.getOperand(0);
5834 if (VT == MVT::i8) {
Evan Cheng152804e2007-12-14 08:30:15 +00005835 // Zero extend to i32 since there is not an i8 bsr.
Evan Cheng18efe262007-12-14 02:13:44 +00005836 OpVT = MVT::i32;
5837 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5838 }
Evan Cheng18efe262007-12-14 02:13:44 +00005839
Evan Cheng152804e2007-12-14 08:30:15 +00005840 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
5841 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5842 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
5843
5844 // If src is zero (i.e. bsr sets ZF), returns NumBits.
Dan Gohman475871a2008-07-27 21:46:04 +00005845 SmallVector<SDValue, 4> Ops;
Evan Cheng152804e2007-12-14 08:30:15 +00005846 Ops.push_back(Op);
5847 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
5848 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5849 Ops.push_back(Op.getValue(1));
5850 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5851
5852 // Finally xor with NumBits-1.
5853 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5854
Evan Cheng18efe262007-12-14 02:13:44 +00005855 if (VT == MVT::i8)
5856 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5857 return Op;
5858}
5859
Dan Gohman475871a2008-07-27 21:46:04 +00005860SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
Duncan Sands83ec4b62008-06-06 12:08:01 +00005861 MVT VT = Op.getValueType();
5862 MVT OpVT = VT;
5863 unsigned NumBits = VT.getSizeInBits();
Evan Cheng18efe262007-12-14 02:13:44 +00005864
5865 Op = Op.getOperand(0);
5866 if (VT == MVT::i8) {
5867 OpVT = MVT::i32;
5868 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5869 }
Evan Cheng152804e2007-12-14 08:30:15 +00005870
5871 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5872 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5873 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5874
5875 // If src is zero (i.e. bsf sets ZF), returns NumBits.
Dan Gohman475871a2008-07-27 21:46:04 +00005876 SmallVector<SDValue, 4> Ops;
Evan Cheng152804e2007-12-14 08:30:15 +00005877 Ops.push_back(Op);
5878 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5879 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5880 Ops.push_back(Op.getValue(1));
5881 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5882
Evan Cheng18efe262007-12-14 02:13:44 +00005883 if (VT == MVT::i8)
5884 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5885 return Op;
5886}
5887
Dan Gohman475871a2008-07-27 21:46:04 +00005888SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
Dan Gohmanfd4418f2008-06-25 16:07:49 +00005889 MVT T = Op.getValueType();
Andrew Lenhartha76e2f02008-03-04 21:13:33 +00005890 unsigned Reg = 0;
5891 unsigned size = 0;
Duncan Sands83ec4b62008-06-06 12:08:01 +00005892 switch(T.getSimpleVT()) {
5893 default:
5894 assert(false && "Invalid value type!");
Andrew Lenharth26ed8692008-03-01 21:52:34 +00005895 case MVT::i8: Reg = X86::AL; size = 1; break;
5896 case MVT::i16: Reg = X86::AX; size = 2; break;
5897 case MVT::i32: Reg = X86::EAX; size = 4; break;
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005898 case MVT::i64:
5899 if (Subtarget->is64Bit()) {
5900 Reg = X86::RAX; size = 8;
5901 } else //Should go away when LowerType stuff lands
Gabor Greifba36cb52008-08-28 21:40:38 +00005902 return SDValue(ExpandATOMIC_CMP_SWAP(Op.getNode(), DAG), 0);
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005903 break;
Andrew Lenharth26ed8692008-03-01 21:52:34 +00005904 };
Dan Gohman475871a2008-07-27 21:46:04 +00005905 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
Dale Johannesend18a4622008-09-11 03:12:59 +00005906 Op.getOperand(2), SDValue());
Dan Gohman475871a2008-07-27 21:46:04 +00005907 SDValue Ops[] = { cpIn.getValue(0),
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005908 Op.getOperand(1),
Dale Johannesend18a4622008-09-11 03:12:59 +00005909 Op.getOperand(3),
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005910 DAG.getTargetConstant(size, MVT::i8),
5911 cpIn.getValue(1) };
Andrew Lenharth26ed8692008-03-01 21:52:34 +00005912 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00005913 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
5914 SDValue cpOut =
Andrew Lenharth26ed8692008-03-01 21:52:34 +00005915 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
5916 return cpOut;
5917}
5918
Gabor Greif327ef032008-08-28 23:19:51 +00005919SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op,
5920 SelectionDAG &DAG) {
Dan Gohmanfd4418f2008-06-25 16:07:49 +00005921 MVT T = Op->getValueType(0);
Mon P Wang28873102008-06-25 08:15:39 +00005922 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
Dan Gohman475871a2008-07-27 21:46:04 +00005923 SDValue cpInL, cpInH;
Dale Johannesend18a4622008-09-11 03:12:59 +00005924 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005925 DAG.getConstant(0, MVT::i32));
Dale Johannesend18a4622008-09-11 03:12:59 +00005926 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005927 DAG.getConstant(1, MVT::i32));
5928 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
Dan Gohman475871a2008-07-27 21:46:04 +00005929 cpInL, SDValue());
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005930 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
5931 cpInH, cpInL.getValue(1));
Dan Gohman475871a2008-07-27 21:46:04 +00005932 SDValue swapInL, swapInH;
Dale Johannesend18a4622008-09-11 03:12:59 +00005933 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005934 DAG.getConstant(0, MVT::i32));
Dale Johannesend18a4622008-09-11 03:12:59 +00005935 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005936 DAG.getConstant(1, MVT::i32));
5937 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX,
5938 swapInL, cpInH.getValue(1));
5939 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
5940 swapInH, swapInL.getValue(1));
Dan Gohman475871a2008-07-27 21:46:04 +00005941 SDValue Ops[] = { swapInH.getValue(0),
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005942 Op->getOperand(1),
5943 swapInH.getValue(1)};
5944 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00005945 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
5946 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005947 Result.getValue(1));
Dan Gohman475871a2008-07-27 21:46:04 +00005948 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005949 cpOutL.getValue(2));
Dan Gohman475871a2008-07-27 21:46:04 +00005950 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
5951 SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
5952 SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) };
Gabor Greifba36cb52008-08-28 21:40:38 +00005953 return DAG.getMergeValues(Vals, 2).getNode();
Andrew Lenharthd19189e2008-03-05 01:15:49 +00005954}
5955
Gabor Greif327ef032008-08-28 23:19:51 +00005956SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op,
5957 SelectionDAG &DAG) {
Dan Gohmanfd4418f2008-06-25 16:07:49 +00005958 MVT T = Op->getValueType(0);
Dan Gohman475871a2008-07-27 21:46:04 +00005959 SDValue negOp = DAG.getNode(ISD::SUB, T,
Mon P Wang63307c32008-05-05 19:05:59 +00005960 DAG.getConstant(0, T), Op->getOperand(2));
Dale Johannesene00a8a22008-08-28 02:44:49 +00005961 return DAG.getAtomic((T==MVT::i8 ? ISD::ATOMIC_LOAD_ADD_8:
5962 T==MVT::i16 ? ISD::ATOMIC_LOAD_ADD_16:
5963 T==MVT::i32 ? ISD::ATOMIC_LOAD_ADD_32:
5964 T==MVT::i64 ? ISD::ATOMIC_LOAD_ADD_64: 0),
5965 Op->getOperand(0), Op->getOperand(1), negOp,
Mon P Wang28873102008-06-25 08:15:39 +00005966 cast<AtomicSDNode>(Op)->getSrcValue(),
Gabor Greifba36cb52008-08-28 21:40:38 +00005967 cast<AtomicSDNode>(Op)->getAlignment()).getNode();
Mon P Wang63307c32008-05-05 19:05:59 +00005968}
5969
Evan Cheng0db9fe62006-04-25 20:13:52 +00005970/// LowerOperation - Provide custom lowering hooks for some operations.
5971///
Dan Gohman475871a2008-07-27 21:46:04 +00005972SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00005973 switch (Op.getOpcode()) {
5974 default: assert(0 && "Should not custom lower this!");
Dale Johannesene00a8a22008-08-28 02:44:49 +00005975 case ISD::ATOMIC_CMP_SWAP_8: return LowerCMP_SWAP(Op,DAG);
5976 case ISD::ATOMIC_CMP_SWAP_16: return LowerCMP_SWAP(Op,DAG);
5977 case ISD::ATOMIC_CMP_SWAP_32: return LowerCMP_SWAP(Op,DAG);
5978 case ISD::ATOMIC_CMP_SWAP_64: return LowerCMP_SWAP(Op,DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005979 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5980 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5981 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5982 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5983 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5984 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5985 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00005986 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005987 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5988 case ISD::SHL_PARTS:
5989 case ISD::SRA_PARTS:
5990 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5991 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5992 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5993 case ISD::FABS: return LowerFABS(Op, DAG);
5994 case ISD::FNEG: return LowerFNEG(Op, DAG);
Evan Cheng68c47cb2007-01-05 07:55:56 +00005995 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Evan Chenge5f62042007-09-29 00:00:36 +00005996 case ISD::SETCC: return LowerSETCC(Op, DAG);
Nate Begeman30a0de92008-07-17 16:51:19 +00005997 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
Evan Chenge5f62042007-09-29 00:00:36 +00005998 case ISD::SELECT: return LowerSELECT(Op, DAG);
5999 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006000 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Evan Cheng32fe1032006-05-25 00:59:30 +00006001 case ISD::CALL: return LowerCALL(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006002 case ISD::RET: return LowerRET(Op, DAG);
Evan Cheng1bc78042006-04-26 01:20:17 +00006003 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006004 case ISD::VASTART: return LowerVASTART(Op, DAG);
Dan Gohman9018e832008-05-10 01:26:14 +00006005 case ISD::VAARG: return LowerVAARG(Op, DAG);
Evan Chengae642192007-03-02 23:16:35 +00006006 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006007 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
Nate Begemanbcc5f362007-01-29 22:58:52 +00006008 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6009 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006010 case ISD::FRAME_TO_ARGS_OFFSET:
6011 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00006012 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006013 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
Duncan Sandsb116fac2007-07-27 20:02:49 +00006014 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
Dan Gohman1a024862008-01-31 00:41:03 +00006015 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
Evan Cheng18efe262007-12-14 02:13:44 +00006016 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6017 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
Chris Lattner27a6c732007-11-24 07:07:01 +00006018
6019 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
6020 case ISD::READCYCLECOUNTER:
Gabor Greifba36cb52008-08-28 21:40:38 +00006021 return SDValue(ExpandREADCYCLECOUNTER(Op.getNode(), DAG), 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00006022 }
Chris Lattner27a6c732007-11-24 07:07:01 +00006023}
6024
Duncan Sands126d9072008-07-04 11:47:58 +00006025/// ReplaceNodeResults - Replace a node with an illegal result type
6026/// with a new node built out of custom code.
6027SDNode *X86TargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
Chris Lattner27a6c732007-11-24 07:07:01 +00006028 switch (N->getOpcode()) {
6029 default: assert(0 && "Should not custom lower this!");
6030 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
6031 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
Dale Johannesene00a8a22008-08-28 02:44:49 +00006032 case ISD::ATOMIC_CMP_SWAP_64: return ExpandATOMIC_CMP_SWAP(N, DAG);
6033 case ISD::ATOMIC_LOAD_SUB_8: return ExpandATOMIC_LOAD_SUB(N,DAG);
6034 case ISD::ATOMIC_LOAD_SUB_16: return ExpandATOMIC_LOAD_SUB(N,DAG);
6035 case ISD::ATOMIC_LOAD_SUB_32: return ExpandATOMIC_LOAD_SUB(N,DAG);
6036 case ISD::ATOMIC_LOAD_SUB_64: return ExpandATOMIC_LOAD_SUB(N,DAG);
Chris Lattner27a6c732007-11-24 07:07:01 +00006037 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00006038}
6039
Evan Cheng72261582005-12-20 06:22:03 +00006040const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6041 switch (Opcode) {
6042 default: return NULL;
Evan Cheng18efe262007-12-14 02:13:44 +00006043 case X86ISD::BSF: return "X86ISD::BSF";
6044 case X86ISD::BSR: return "X86ISD::BSR";
Evan Chenge3413162006-01-09 18:33:28 +00006045 case X86ISD::SHLD: return "X86ISD::SHLD";
6046 case X86ISD::SHRD: return "X86ISD::SHRD";
Evan Chengef6ffb12006-01-31 03:14:29 +00006047 case X86ISD::FAND: return "X86ISD::FAND";
Evan Cheng68c47cb2007-01-05 07:55:56 +00006048 case X86ISD::FOR: return "X86ISD::FOR";
Evan Cheng223547a2006-01-31 22:28:30 +00006049 case X86ISD::FXOR: return "X86ISD::FXOR";
Evan Cheng68c47cb2007-01-05 07:55:56 +00006050 case X86ISD::FSRL: return "X86ISD::FSRL";
Evan Chenga3195e82006-01-12 22:54:21 +00006051 case X86ISD::FILD: return "X86ISD::FILD";
Evan Chenge3de85b2006-02-04 02:20:30 +00006052 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
Evan Cheng72261582005-12-20 06:22:03 +00006053 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6054 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6055 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
Evan Chengb077b842005-12-21 02:39:21 +00006056 case X86ISD::FLD: return "X86ISD::FLD";
Evan Chengd90eb7f2006-01-05 00:27:02 +00006057 case X86ISD::FST: return "X86ISD::FST";
Evan Cheng72261582005-12-20 06:22:03 +00006058 case X86ISD::CALL: return "X86ISD::CALL";
6059 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6060 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6061 case X86ISD::CMP: return "X86ISD::CMP";
Evan Cheng6be2c582006-04-05 23:38:46 +00006062 case X86ISD::COMI: return "X86ISD::COMI";
6063 case X86ISD::UCOMI: return "X86ISD::UCOMI";
Evan Chengd5781fc2005-12-21 20:21:51 +00006064 case X86ISD::SETCC: return "X86ISD::SETCC";
Evan Cheng72261582005-12-20 06:22:03 +00006065 case X86ISD::CMOV: return "X86ISD::CMOV";
6066 case X86ISD::BRCOND: return "X86ISD::BRCOND";
Evan Chengb077b842005-12-21 02:39:21 +00006067 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
Evan Cheng8df346b2006-03-04 01:12:00 +00006068 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6069 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
Evan Cheng7ccced62006-02-18 00:15:05 +00006070 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
Evan Cheng020d2e82006-02-23 20:41:18 +00006071 case X86ISD::Wrapper: return "X86ISD::Wrapper";
Nate Begeman14d12ca2008-02-11 04:19:36 +00006072 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
Evan Chengb067a1e2006-03-31 19:22:53 +00006073 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
Nate Begeman14d12ca2008-02-11 04:19:36 +00006074 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6075 case X86ISD::PINSRB: return "X86ISD::PINSRB";
Evan Cheng653159f2006-03-31 21:55:24 +00006076 case X86ISD::PINSRW: return "X86ISD::PINSRW";
Evan Cheng8ca29322006-11-10 21:43:37 +00006077 case X86ISD::FMAX: return "X86ISD::FMAX";
6078 case X86ISD::FMIN: return "X86ISD::FMIN";
Dan Gohman20382522007-07-10 00:05:58 +00006079 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6080 case X86ISD::FRCP: return "X86ISD::FRCP";
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00006081 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6082 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
Anton Korobeynikov2365f512007-07-14 14:06:15 +00006083 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00006084 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00006085 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
Evan Cheng7e2ff772008-05-08 00:57:18 +00006086 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6087 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
Evan Chengd880b972008-05-09 21:53:03 +00006088 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6089 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
Evan Chengf26ffe92008-05-29 08:22:04 +00006090 case X86ISD::VSHL: return "X86ISD::VSHL";
6091 case X86ISD::VSRL: return "X86ISD::VSRL";
Nate Begeman30a0de92008-07-17 16:51:19 +00006092 case X86ISD::CMPPD: return "X86ISD::CMPPD";
6093 case X86ISD::CMPPS: return "X86ISD::CMPPS";
6094 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
6095 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
6096 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
6097 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
6098 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
6099 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
6100 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
6101 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
Evan Cheng72261582005-12-20 06:22:03 +00006102 }
6103}
Evan Cheng3a03ebb2005-12-21 23:05:39 +00006104
Chris Lattnerc9addb72007-03-30 23:15:24 +00006105// isLegalAddressingMode - Return true if the addressing mode represented
6106// by AM is legal for this target, for a load/store of the specified type.
6107bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6108 const Type *Ty) const {
6109 // X86 supports extremely general addressing modes.
6110
6111 // X86 allows a sign-extended 32-bit immediate field as a displacement.
6112 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
6113 return false;
6114
6115 if (AM.BaseGV) {
Evan Cheng52787842007-08-01 23:46:47 +00006116 // We can only fold this if we don't need an extra load.
Chris Lattnerc9addb72007-03-30 23:15:24 +00006117 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
6118 return false;
Evan Cheng52787842007-08-01 23:46:47 +00006119
6120 // X86-64 only supports addr of globals in small code model.
6121 if (Subtarget->is64Bit()) {
6122 if (getTargetMachine().getCodeModel() != CodeModel::Small)
6123 return false;
6124 // If lower 4G is not available, then we must use rip-relative addressing.
6125 if (AM.BaseOffs || AM.Scale > 1)
6126 return false;
6127 }
Chris Lattnerc9addb72007-03-30 23:15:24 +00006128 }
6129
6130 switch (AM.Scale) {
6131 case 0:
6132 case 1:
6133 case 2:
6134 case 4:
6135 case 8:
6136 // These scales always work.
6137 break;
6138 case 3:
6139 case 5:
6140 case 9:
6141 // These scales are formed with basereg+scalereg. Only accept if there is
6142 // no basereg yet.
6143 if (AM.HasBaseReg)
6144 return false;
6145 break;
6146 default: // Other stuff never works.
6147 return false;
6148 }
6149
6150 return true;
6151}
6152
6153
Evan Cheng2bd122c2007-10-26 01:56:11 +00006154bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
6155 if (!Ty1->isInteger() || !Ty2->isInteger())
6156 return false;
Evan Chenge127a732007-10-29 07:57:50 +00006157 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6158 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
Evan Cheng260e07e2008-03-20 02:18:41 +00006159 if (NumBits1 <= NumBits2)
Evan Chenge127a732007-10-29 07:57:50 +00006160 return false;
6161 return Subtarget->is64Bit() || NumBits1 < 64;
Evan Cheng2bd122c2007-10-26 01:56:11 +00006162}
6163
Duncan Sands83ec4b62008-06-06 12:08:01 +00006164bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
6165 if (!VT1.isInteger() || !VT2.isInteger())
Evan Cheng3c3ddb32007-10-29 19:58:20 +00006166 return false;
Duncan Sands83ec4b62008-06-06 12:08:01 +00006167 unsigned NumBits1 = VT1.getSizeInBits();
6168 unsigned NumBits2 = VT2.getSizeInBits();
Evan Cheng260e07e2008-03-20 02:18:41 +00006169 if (NumBits1 <= NumBits2)
Evan Cheng3c3ddb32007-10-29 19:58:20 +00006170 return false;
6171 return Subtarget->is64Bit() || NumBits1 < 64;
6172}
Evan Cheng2bd122c2007-10-26 01:56:11 +00006173
Evan Cheng60c07e12006-07-05 22:17:51 +00006174/// isShuffleMaskLegal - Targets can use this to indicate that they only
6175/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6176/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6177/// are assumed to be legal.
6178bool
Dan Gohman475871a2008-07-27 21:46:04 +00006179X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
Evan Cheng60c07e12006-07-05 22:17:51 +00006180 // Only do shuffles on 128-bit vector types for now.
Duncan Sands83ec4b62008-06-06 12:08:01 +00006181 if (VT.getSizeInBits() == 64) return false;
Gabor Greifba36cb52008-08-28 21:40:38 +00006182 return (Mask.getNode()->getNumOperands() <= 4 ||
6183 isIdentityMask(Mask.getNode()) ||
6184 isIdentityMask(Mask.getNode(), true) ||
6185 isSplatMask(Mask.getNode()) ||
6186 isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
6187 X86::isUNPCKLMask(Mask.getNode()) ||
6188 X86::isUNPCKHMask(Mask.getNode()) ||
6189 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
6190 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
Evan Cheng60c07e12006-07-05 22:17:51 +00006191}
6192
Dan Gohman7d8143f2008-04-09 20:09:42 +00006193bool
Dan Gohman475871a2008-07-27 21:46:04 +00006194X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
Duncan Sands83ec4b62008-06-06 12:08:01 +00006195 MVT EVT, SelectionDAG &DAG) const {
Evan Cheng60c07e12006-07-05 22:17:51 +00006196 unsigned NumElts = BVOps.size();
6197 // Only do shuffles on 128-bit vector types for now.
Duncan Sands83ec4b62008-06-06 12:08:01 +00006198 if (EVT.getSizeInBits() * NumElts == 64) return false;
Evan Cheng60c07e12006-07-05 22:17:51 +00006199 if (NumElts == 2) return true;
6200 if (NumElts == 4) {
Chris Lattner5a88b832007-02-25 07:10:00 +00006201 return (isMOVLMask(&BVOps[0], 4) ||
6202 isCommutedMOVL(&BVOps[0], 4, true) ||
6203 isSHUFPMask(&BVOps[0], 4) ||
6204 isCommutedSHUFP(&BVOps[0], 4));
Evan Cheng60c07e12006-07-05 22:17:51 +00006205 }
6206 return false;
6207}
6208
6209//===----------------------------------------------------------------------===//
6210// X86 Scheduler Hooks
6211//===----------------------------------------------------------------------===//
6212
Mon P Wang63307c32008-05-05 19:05:59 +00006213// private utility function
6214MachineBasicBlock *
6215X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
6216 MachineBasicBlock *MBB,
6217 unsigned regOpc,
Andrew Lenharth507a58a2008-06-14 05:48:15 +00006218 unsigned immOpc,
Dale Johannesen140be2d2008-08-19 18:47:28 +00006219 unsigned LoadOpc,
6220 unsigned CXchgOpc,
6221 unsigned copyOpc,
6222 unsigned notOpc,
6223 unsigned EAXreg,
6224 TargetRegisterClass *RC,
Andrew Lenharth507a58a2008-06-14 05:48:15 +00006225 bool invSrc) {
Mon P Wang63307c32008-05-05 19:05:59 +00006226 // For the atomic bitwise operator, we generate
6227 // thisMBB:
6228 // newMBB:
Mon P Wangab3e7472008-05-05 22:56:23 +00006229 // ld t1 = [bitinstr.addr]
6230 // op t2 = t1, [bitinstr.val]
6231 // mov EAX = t1
Mon P Wang63307c32008-05-05 19:05:59 +00006232 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6233 // bz newMBB
6234 // fallthrough -->nextMBB
6235 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6236 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
Dan Gohman8e5f2c62008-07-07 23:14:23 +00006237 MachineFunction::iterator MBBIter = MBB;
Mon P Wang63307c32008-05-05 19:05:59 +00006238 ++MBBIter;
6239
6240 /// First build the CFG
6241 MachineFunction *F = MBB->getParent();
6242 MachineBasicBlock *thisMBB = MBB;
Dan Gohman8e5f2c62008-07-07 23:14:23 +00006243 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6244 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6245 F->insert(MBBIter, newMBB);
6246 F->insert(MBBIter, nextMBB);
Mon P Wang63307c32008-05-05 19:05:59 +00006247
6248 // Move all successors to thisMBB to nextMBB
6249 nextMBB->transferSuccessors(thisMBB);
6250
6251 // Update thisMBB to fall through to newMBB
6252 thisMBB->addSuccessor(newMBB);
6253
6254 // newMBB jumps to itself and fall through to nextMBB
6255 newMBB->addSuccessor(nextMBB);
6256 newMBB->addSuccessor(newMBB);
6257
6258 // Insert instructions into newMBB based on incoming instruction
6259 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
6260 MachineOperand& destOper = bInstr->getOperand(0);
6261 MachineOperand* argOpers[6];
6262 int numArgs = bInstr->getNumOperands() - 1;
6263 for (int i=0; i < numArgs; ++i)
6264 argOpers[i] = &bInstr->getOperand(i+1);
6265
6266 // x86 address has 4 operands: base, index, scale, and displacement
6267 int lastAddrIndx = 3; // [0,3]
6268 int valArgIndx = 4;
6269
Dale Johannesen140be2d2008-08-19 18:47:28 +00006270 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6271 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1);
Mon P Wang63307c32008-05-05 19:05:59 +00006272 for (int i=0; i <= lastAddrIndx; ++i)
6273 (*MIB).addOperand(*argOpers[i]);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00006274
Dale Johannesen140be2d2008-08-19 18:47:28 +00006275 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00006276 if (invSrc) {
Dale Johannesen140be2d2008-08-19 18:47:28 +00006277 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00006278 }
6279 else
6280 tt = t1;
6281
Dale Johannesen140be2d2008-08-19 18:47:28 +00006282 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
Mon P Wang63307c32008-05-05 19:05:59 +00006283 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
6284 && "invalid operand");
6285 if (argOpers[valArgIndx]->isReg())
6286 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6287 else
6288 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00006289 MIB.addReg(tt);
Mon P Wang63307c32008-05-05 19:05:59 +00006290 (*MIB).addOperand(*argOpers[valArgIndx]);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00006291
Dale Johannesen140be2d2008-08-19 18:47:28 +00006292 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg);
Mon P Wangab3e7472008-05-05 22:56:23 +00006293 MIB.addReg(t1);
6294
Dale Johannesen140be2d2008-08-19 18:47:28 +00006295 MIB = BuildMI(newMBB, TII->get(CXchgOpc));
Mon P Wang63307c32008-05-05 19:05:59 +00006296 for (int i=0; i <= lastAddrIndx; ++i)
6297 (*MIB).addOperand(*argOpers[i]);
6298 MIB.addReg(t2);
Mon P Wangf5952662008-07-17 04:54:06 +00006299 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6300 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6301
Dale Johannesen140be2d2008-08-19 18:47:28 +00006302 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
6303 MIB.addReg(EAXreg);
Mon P Wang63307c32008-05-05 19:05:59 +00006304
6305 // insert branch
6306 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6307
Dan Gohman8e5f2c62008-07-07 23:14:23 +00006308 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
Mon P Wang63307c32008-05-05 19:05:59 +00006309 return nextMBB;
6310}
6311
6312// private utility function
6313MachineBasicBlock *
6314X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
6315 MachineBasicBlock *MBB,
6316 unsigned cmovOpc) {
6317 // For the atomic min/max operator, we generate
6318 // thisMBB:
6319 // newMBB:
Mon P Wangab3e7472008-05-05 22:56:23 +00006320 // ld t1 = [min/max.addr]
Mon P Wang63307c32008-05-05 19:05:59 +00006321 // mov t2 = [min/max.val]
6322 // cmp t1, t2
6323 // cmov[cond] t2 = t1
Mon P Wangab3e7472008-05-05 22:56:23 +00006324 // mov EAX = t1
Mon P Wang63307c32008-05-05 19:05:59 +00006325 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6326 // bz newMBB
6327 // fallthrough -->nextMBB
6328 //
6329 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6330 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
Dan Gohman8e5f2c62008-07-07 23:14:23 +00006331 MachineFunction::iterator MBBIter = MBB;
Mon P Wang63307c32008-05-05 19:05:59 +00006332 ++MBBIter;
6333
6334 /// First build the CFG
6335 MachineFunction *F = MBB->getParent();
6336 MachineBasicBlock *thisMBB = MBB;
Dan Gohman8e5f2c62008-07-07 23:14:23 +00006337 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6338 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6339 F->insert(MBBIter, newMBB);
6340 F->insert(MBBIter, nextMBB);
Mon P Wang63307c32008-05-05 19:05:59 +00006341
6342 // Move all successors to thisMBB to nextMBB
6343 nextMBB->transferSuccessors(thisMBB);
6344
6345 // Update thisMBB to fall through to newMBB
6346 thisMBB->addSuccessor(newMBB);
6347
6348 // newMBB jumps to newMBB and fall through to nextMBB
6349 newMBB->addSuccessor(nextMBB);
6350 newMBB->addSuccessor(newMBB);
6351
6352 // Insert instructions into newMBB based on incoming instruction
6353 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
6354 MachineOperand& destOper = mInstr->getOperand(0);
6355 MachineOperand* argOpers[6];
6356 int numArgs = mInstr->getNumOperands() - 1;
6357 for (int i=0; i < numArgs; ++i)
6358 argOpers[i] = &mInstr->getOperand(i+1);
6359
6360 // x86 address has 4 operands: base, index, scale, and displacement
6361 int lastAddrIndx = 3; // [0,3]
6362 int valArgIndx = 4;
6363
Mon P Wangab3e7472008-05-05 22:56:23 +00006364 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6365 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
Mon P Wang63307c32008-05-05 19:05:59 +00006366 for (int i=0; i <= lastAddrIndx; ++i)
6367 (*MIB).addOperand(*argOpers[i]);
Mon P Wangab3e7472008-05-05 22:56:23 +00006368
Mon P Wang63307c32008-05-05 19:05:59 +00006369 // We only support register and immediate values
6370 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
6371 && "invalid operand");
6372
6373 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6374 if (argOpers[valArgIndx]->isReg())
6375 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6376 else
6377 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6378 (*MIB).addOperand(*argOpers[valArgIndx]);
6379
Mon P Wangab3e7472008-05-05 22:56:23 +00006380 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6381 MIB.addReg(t1);
6382
Mon P Wang63307c32008-05-05 19:05:59 +00006383 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
6384 MIB.addReg(t1);
6385 MIB.addReg(t2);
6386
6387 // Generate movc
6388 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6389 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
6390 MIB.addReg(t2);
6391 MIB.addReg(t1);
6392
6393 // Cmp and exchange if none has modified the memory location
6394 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6395 for (int i=0; i <= lastAddrIndx; ++i)
6396 (*MIB).addOperand(*argOpers[i]);
6397 MIB.addReg(t3);
Mon P Wangf5952662008-07-17 04:54:06 +00006398 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6399 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
Mon P Wang63307c32008-05-05 19:05:59 +00006400
6401 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6402 MIB.addReg(X86::EAX);
6403
6404 // insert branch
6405 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6406
Dan Gohman8e5f2c62008-07-07 23:14:23 +00006407 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
Mon P Wang63307c32008-05-05 19:05:59 +00006408 return nextMBB;
6409}
6410
6411
Evan Cheng60c07e12006-07-05 22:17:51 +00006412MachineBasicBlock *
Evan Chengff9b3732008-01-30 18:18:23 +00006413X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6414 MachineBasicBlock *BB) {
Evan Chengc0f64ff2006-11-27 23:37:22 +00006415 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Evan Cheng60c07e12006-07-05 22:17:51 +00006416 switch (MI->getOpcode()) {
6417 default: assert(false && "Unexpected instr type to insert");
6418 case X86::CMOV_FR32:
6419 case X86::CMOV_FR64:
6420 case X86::CMOV_V4F32:
6421 case X86::CMOV_V2F64:
Evan Chenge5f62042007-09-29 00:00:36 +00006422 case X86::CMOV_V2I64: {
Evan Cheng60c07e12006-07-05 22:17:51 +00006423 // To "insert" a SELECT_CC instruction, we actually have to insert the
6424 // diamond control-flow pattern. The incoming instruction knows the
6425 // destination vreg to set, the condition code register to branch on, the
6426 // true/false values to select between, and a branch opcode to use.
6427 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Dan Gohman8e5f2c62008-07-07 23:14:23 +00006428 MachineFunction::iterator It = BB;
Evan Cheng60c07e12006-07-05 22:17:51 +00006429 ++It;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006430
Evan Cheng60c07e12006-07-05 22:17:51 +00006431 // thisMBB:
6432 // ...
6433 // TrueVal = ...
6434 // cmpTY ccX, r1, r2
6435 // bCC copy1MBB
6436 // fallthrough --> copy0MBB
6437 MachineBasicBlock *thisMBB = BB;
Dan Gohman8e5f2c62008-07-07 23:14:23 +00006438 MachineFunction *F = BB->getParent();
6439 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6440 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006441 unsigned Opc =
Chris Lattner7fbe9722006-10-20 17:42:20 +00006442 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
Evan Chengc0f64ff2006-11-27 23:37:22 +00006443 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
Dan Gohman8e5f2c62008-07-07 23:14:23 +00006444 F->insert(It, copy0MBB);
6445 F->insert(It, sinkMBB);
Mon P Wang63307c32008-05-05 19:05:59 +00006446 // Update machine-CFG edges by transferring all successors of the current
Evan Cheng60c07e12006-07-05 22:17:51 +00006447 // block to the new block which will contain the Phi node for the select.
Mon P Wang63307c32008-05-05 19:05:59 +00006448 sinkMBB->transferSuccessors(BB);
6449
6450 // Add the true and fallthrough blocks as its successors.
Evan Cheng60c07e12006-07-05 22:17:51 +00006451 BB->addSuccessor(copy0MBB);
6452 BB->addSuccessor(sinkMBB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006453
Evan Cheng60c07e12006-07-05 22:17:51 +00006454 // copy0MBB:
6455 // %FalseValue = ...
6456 // # fallthrough to sinkMBB
6457 BB = copy0MBB;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006458
Evan Cheng60c07e12006-07-05 22:17:51 +00006459 // Update machine-CFG edges
6460 BB->addSuccessor(sinkMBB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006461
Evan Cheng60c07e12006-07-05 22:17:51 +00006462 // sinkMBB:
6463 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6464 // ...
6465 BB = sinkMBB;
Evan Chengc0f64ff2006-11-27 23:37:22 +00006466 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
Evan Cheng60c07e12006-07-05 22:17:51 +00006467 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6468 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6469
Dan Gohman8e5f2c62008-07-07 23:14:23 +00006470 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
Evan Cheng60c07e12006-07-05 22:17:51 +00006471 return BB;
6472 }
6473
Dale Johannesen849f2142007-07-03 00:53:03 +00006474 case X86::FP32_TO_INT16_IN_MEM:
6475 case X86::FP32_TO_INT32_IN_MEM:
6476 case X86::FP32_TO_INT64_IN_MEM:
6477 case X86::FP64_TO_INT16_IN_MEM:
6478 case X86::FP64_TO_INT32_IN_MEM:
Dale Johannesena996d522007-08-07 01:17:37 +00006479 case X86::FP64_TO_INT64_IN_MEM:
6480 case X86::FP80_TO_INT16_IN_MEM:
6481 case X86::FP80_TO_INT32_IN_MEM:
6482 case X86::FP80_TO_INT64_IN_MEM: {
Evan Cheng60c07e12006-07-05 22:17:51 +00006483 // Change the floating point control register to use "round towards zero"
6484 // mode when truncating to an integer value.
6485 MachineFunction *F = BB->getParent();
6486 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
Evan Chengc0f64ff2006-11-27 23:37:22 +00006487 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00006488
6489 // Load the old value of the high byte of the control word...
6490 unsigned OldCW =
Chris Lattner84bc5422007-12-31 04:13:23 +00006491 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
Evan Chengc0f64ff2006-11-27 23:37:22 +00006492 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00006493
6494 // Set the high part to be round to zero...
Evan Chengc0f64ff2006-11-27 23:37:22 +00006495 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
6496 .addImm(0xC7F);
Evan Cheng60c07e12006-07-05 22:17:51 +00006497
6498 // Reload the modified control word now...
Evan Chengc0f64ff2006-11-27 23:37:22 +00006499 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00006500
6501 // Restore the memory image of control word to original value
Evan Chengc0f64ff2006-11-27 23:37:22 +00006502 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
6503 .addReg(OldCW);
Evan Cheng60c07e12006-07-05 22:17:51 +00006504
6505 // Get the X86 opcode to use.
6506 unsigned Opc;
6507 switch (MI->getOpcode()) {
6508 default: assert(0 && "illegal opcode!");
Dale Johannesene377d4d2007-07-04 21:07:47 +00006509 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
6510 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
6511 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
6512 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
6513 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
6514 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
Dale Johannesena996d522007-08-07 01:17:37 +00006515 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
6516 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
6517 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
Evan Cheng60c07e12006-07-05 22:17:51 +00006518 }
6519
6520 X86AddressMode AM;
6521 MachineOperand &Op = MI->getOperand(0);
6522 if (Op.isRegister()) {
6523 AM.BaseType = X86AddressMode::RegBase;
6524 AM.Base.Reg = Op.getReg();
6525 } else {
6526 AM.BaseType = X86AddressMode::FrameIndexBase;
Chris Lattner8aa797a2007-12-30 23:10:15 +00006527 AM.Base.FrameIndex = Op.getIndex();
Evan Cheng60c07e12006-07-05 22:17:51 +00006528 }
6529 Op = MI->getOperand(1);
6530 if (Op.isImmediate())
Chris Lattner7fbe9722006-10-20 17:42:20 +00006531 AM.Scale = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00006532 Op = MI->getOperand(2);
6533 if (Op.isImmediate())
Chris Lattner7fbe9722006-10-20 17:42:20 +00006534 AM.IndexReg = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00006535 Op = MI->getOperand(3);
6536 if (Op.isGlobalAddress()) {
6537 AM.GV = Op.getGlobal();
6538 } else {
Chris Lattner7fbe9722006-10-20 17:42:20 +00006539 AM.Disp = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00006540 }
Evan Chengc0f64ff2006-11-27 23:37:22 +00006541 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
6542 .addReg(MI->getOperand(4).getReg());
Evan Cheng60c07e12006-07-05 22:17:51 +00006543
6544 // Reload the original control word now.
Evan Chengc0f64ff2006-11-27 23:37:22 +00006545 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00006546
Dan Gohman8e5f2c62008-07-07 23:14:23 +00006547 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
Evan Cheng60c07e12006-07-05 22:17:51 +00006548 return BB;
6549 }
Mon P Wang63307c32008-05-05 19:05:59 +00006550 case X86::ATOMAND32:
6551 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
Dale Johannesen140be2d2008-08-19 18:47:28 +00006552 X86::AND32ri, X86::MOV32rm,
6553 X86::LCMPXCHG32, X86::MOV32rr,
6554 X86::NOT32r, X86::EAX,
6555 X86::GR32RegisterClass);
Mon P Wang63307c32008-05-05 19:05:59 +00006556 case X86::ATOMOR32:
6557 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
Dale Johannesen140be2d2008-08-19 18:47:28 +00006558 X86::OR32ri, X86::MOV32rm,
6559 X86::LCMPXCHG32, X86::MOV32rr,
6560 X86::NOT32r, X86::EAX,
6561 X86::GR32RegisterClass);
Mon P Wang63307c32008-05-05 19:05:59 +00006562 case X86::ATOMXOR32:
6563 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
Dale Johannesen140be2d2008-08-19 18:47:28 +00006564 X86::XOR32ri, X86::MOV32rm,
6565 X86::LCMPXCHG32, X86::MOV32rr,
6566 X86::NOT32r, X86::EAX,
6567 X86::GR32RegisterClass);
Andrew Lenharth507a58a2008-06-14 05:48:15 +00006568 case X86::ATOMNAND32:
6569 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
Dale Johannesen140be2d2008-08-19 18:47:28 +00006570 X86::AND32ri, X86::MOV32rm,
6571 X86::LCMPXCHG32, X86::MOV32rr,
6572 X86::NOT32r, X86::EAX,
6573 X86::GR32RegisterClass, true);
Mon P Wang63307c32008-05-05 19:05:59 +00006574 case X86::ATOMMIN32:
6575 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
6576 case X86::ATOMMAX32:
6577 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
6578 case X86::ATOMUMIN32:
6579 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
6580 case X86::ATOMUMAX32:
6581 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
Dale Johannesen140be2d2008-08-19 18:47:28 +00006582
6583 case X86::ATOMAND16:
6584 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
6585 X86::AND16ri, X86::MOV16rm,
6586 X86::LCMPXCHG16, X86::MOV16rr,
6587 X86::NOT16r, X86::AX,
6588 X86::GR16RegisterClass);
6589 case X86::ATOMOR16:
6590 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
6591 X86::OR16ri, X86::MOV16rm,
6592 X86::LCMPXCHG16, X86::MOV16rr,
6593 X86::NOT16r, X86::AX,
6594 X86::GR16RegisterClass);
6595 case X86::ATOMXOR16:
6596 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
6597 X86::XOR16ri, X86::MOV16rm,
6598 X86::LCMPXCHG16, X86::MOV16rr,
6599 X86::NOT16r, X86::AX,
6600 X86::GR16RegisterClass);
6601 case X86::ATOMNAND16:
6602 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
6603 X86::AND16ri, X86::MOV16rm,
6604 X86::LCMPXCHG16, X86::MOV16rr,
6605 X86::NOT16r, X86::AX,
6606 X86::GR16RegisterClass, true);
6607 case X86::ATOMMIN16:
6608 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
6609 case X86::ATOMMAX16:
6610 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
6611 case X86::ATOMUMIN16:
6612 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
6613 case X86::ATOMUMAX16:
6614 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
6615
6616 case X86::ATOMAND8:
6617 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
6618 X86::AND8ri, X86::MOV8rm,
6619 X86::LCMPXCHG8, X86::MOV8rr,
6620 X86::NOT8r, X86::AL,
6621 X86::GR8RegisterClass);
6622 case X86::ATOMOR8:
6623 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
6624 X86::OR8ri, X86::MOV8rm,
6625 X86::LCMPXCHG8, X86::MOV8rr,
6626 X86::NOT8r, X86::AL,
6627 X86::GR8RegisterClass);
6628 case X86::ATOMXOR8:
6629 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
6630 X86::XOR8ri, X86::MOV8rm,
6631 X86::LCMPXCHG8, X86::MOV8rr,
6632 X86::NOT8r, X86::AL,
6633 X86::GR8RegisterClass);
6634 case X86::ATOMNAND8:
6635 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
6636 X86::AND8ri, X86::MOV8rm,
6637 X86::LCMPXCHG8, X86::MOV8rr,
6638 X86::NOT8r, X86::AL,
6639 X86::GR8RegisterClass, true);
6640 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
Dale Johannesena99e3842008-08-20 00:48:50 +00006641 case X86::ATOMAND64:
6642 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
6643 X86::AND64ri32, X86::MOV64rm,
6644 X86::LCMPXCHG64, X86::MOV64rr,
6645 X86::NOT64r, X86::RAX,
6646 X86::GR64RegisterClass);
6647 case X86::ATOMOR64:
6648 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
6649 X86::OR64ri32, X86::MOV64rm,
6650 X86::LCMPXCHG64, X86::MOV64rr,
6651 X86::NOT64r, X86::RAX,
6652 X86::GR64RegisterClass);
6653 case X86::ATOMXOR64:
6654 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
6655 X86::XOR64ri32, X86::MOV64rm,
6656 X86::LCMPXCHG64, X86::MOV64rr,
6657 X86::NOT64r, X86::RAX,
6658 X86::GR64RegisterClass);
6659 case X86::ATOMNAND64:
6660 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
6661 X86::AND64ri32, X86::MOV64rm,
6662 X86::LCMPXCHG64, X86::MOV64rr,
6663 X86::NOT64r, X86::RAX,
6664 X86::GR64RegisterClass, true);
6665 case X86::ATOMMIN64:
6666 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
6667 case X86::ATOMMAX64:
6668 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
6669 case X86::ATOMUMIN64:
6670 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
6671 case X86::ATOMUMAX64:
6672 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
Evan Cheng60c07e12006-07-05 22:17:51 +00006673 }
6674}
6675
6676//===----------------------------------------------------------------------===//
6677// X86 Optimization Hooks
6678//===----------------------------------------------------------------------===//
6679
Dan Gohman475871a2008-07-27 21:46:04 +00006680void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +00006681 const APInt &Mask,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00006682 APInt &KnownZero,
6683 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +00006684 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +00006685 unsigned Depth) const {
Evan Cheng3a03ebb2005-12-21 23:05:39 +00006686 unsigned Opc = Op.getOpcode();
Evan Cheng865f0602006-04-05 06:11:20 +00006687 assert((Opc >= ISD::BUILTIN_OP_END ||
6688 Opc == ISD::INTRINSIC_WO_CHAIN ||
6689 Opc == ISD::INTRINSIC_W_CHAIN ||
6690 Opc == ISD::INTRINSIC_VOID) &&
6691 "Should use MaskedValueIsZero if you don't know whether Op"
6692 " is a target node!");
Evan Cheng3a03ebb2005-12-21 23:05:39 +00006693
Dan Gohmanf4f92f52008-02-13 23:07:24 +00006694 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
Evan Cheng3a03ebb2005-12-21 23:05:39 +00006695 switch (Opc) {
Evan Cheng865f0602006-04-05 06:11:20 +00006696 default: break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006697 case X86ISD::SETCC:
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00006698 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
6699 Mask.getBitWidth() - 1);
Nate Begeman368e18d2006-02-16 21:11:51 +00006700 break;
Evan Cheng3a03ebb2005-12-21 23:05:39 +00006701 }
Evan Cheng3a03ebb2005-12-21 23:05:39 +00006702}
Chris Lattner259e97c2006-01-31 19:43:35 +00006703
Evan Cheng206ee9d2006-07-07 08:33:52 +00006704/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
Evan Chengad4196b2008-05-12 19:56:52 +00006705/// node is a GlobalAddress + offset.
6706bool X86TargetLowering::isGAPlusOffset(SDNode *N,
6707 GlobalValue* &GA, int64_t &Offset) const{
6708 if (N->getOpcode() == X86ISD::Wrapper) {
6709 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00006710 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
6711 return true;
6712 }
Evan Cheng206ee9d2006-07-07 08:33:52 +00006713 }
Evan Chengad4196b2008-05-12 19:56:52 +00006714 return TargetLowering::isGAPlusOffset(N, GA, Offset);
Evan Cheng206ee9d2006-07-07 08:33:52 +00006715}
6716
Evan Chengad4196b2008-05-12 19:56:52 +00006717static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
6718 const TargetLowering &TLI) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00006719 GlobalValue *GV;
Nick Lewycky916a9f02008-02-02 08:29:58 +00006720 int64_t Offset = 0;
Evan Chengad4196b2008-05-12 19:56:52 +00006721 if (TLI.isGAPlusOffset(Base, GV, Offset))
Evan Cheng7e2ff772008-05-08 00:57:18 +00006722 return (GV->getAlignment() >= N && (Offset % N) == 0);
Chris Lattnerba96fbc2008-01-26 20:07:42 +00006723 // DAG combine handles the stack object case.
Evan Cheng206ee9d2006-07-07 08:33:52 +00006724 return false;
6725}
6726
Dan Gohman475871a2008-07-27 21:46:04 +00006727static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
Duncan Sands83ec4b62008-06-06 12:08:01 +00006728 unsigned NumElems, MVT EVT,
Evan Chengad4196b2008-05-12 19:56:52 +00006729 SDNode *&Base,
6730 SelectionDAG &DAG, MachineFrameInfo *MFI,
6731 const TargetLowering &TLI) {
Evan Cheng7e2ff772008-05-08 00:57:18 +00006732 Base = NULL;
6733 for (unsigned i = 0; i < NumElems; ++i) {
Dan Gohman475871a2008-07-27 21:46:04 +00006734 SDValue Idx = PermMask.getOperand(i);
Evan Cheng7e2ff772008-05-08 00:57:18 +00006735 if (Idx.getOpcode() == ISD::UNDEF) {
6736 if (!Base)
6737 return false;
6738 continue;
6739 }
6740
Dan Gohman475871a2008-07-27 21:46:04 +00006741 SDValue Elt = DAG.getShuffleScalarElt(N, i);
Gabor Greifba36cb52008-08-28 21:40:38 +00006742 if (!Elt.getNode() ||
6743 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
Evan Cheng7e2ff772008-05-08 00:57:18 +00006744 return false;
6745 if (!Base) {
Gabor Greifba36cb52008-08-28 21:40:38 +00006746 Base = Elt.getNode();
Evan Cheng50d9e722008-05-10 06:46:49 +00006747 if (Base->getOpcode() == ISD::UNDEF)
6748 return false;
Evan Cheng7e2ff772008-05-08 00:57:18 +00006749 continue;
6750 }
6751 if (Elt.getOpcode() == ISD::UNDEF)
6752 continue;
6753
Gabor Greifba36cb52008-08-28 21:40:38 +00006754 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
Duncan Sands83ec4b62008-06-06 12:08:01 +00006755 EVT.getSizeInBits()/8, i, MFI))
Evan Cheng7e2ff772008-05-08 00:57:18 +00006756 return false;
6757 }
6758 return true;
6759}
Evan Cheng206ee9d2006-07-07 08:33:52 +00006760
6761/// PerformShuffleCombine - Combine a vector_shuffle that is equal to
6762/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
6763/// if the load addresses are consecutive, non-overlapping, and in the right
6764/// order.
Dan Gohman475871a2008-07-27 21:46:04 +00006765static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
Evan Chengad4196b2008-05-12 19:56:52 +00006766 const TargetLowering &TLI) {
Evan Cheng7e2ff772008-05-08 00:57:18 +00006767 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
Duncan Sands83ec4b62008-06-06 12:08:01 +00006768 MVT VT = N->getValueType(0);
6769 MVT EVT = VT.getVectorElementType();
Dan Gohman475871a2008-07-27 21:46:04 +00006770 SDValue PermMask = N->getOperand(2);
Evan Cheng71f489d2008-05-05 22:12:23 +00006771 unsigned NumElems = PermMask.getNumOperands();
Evan Cheng206ee9d2006-07-07 08:33:52 +00006772 SDNode *Base = NULL;
Evan Chengad4196b2008-05-12 19:56:52 +00006773 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
6774 DAG, MFI, TLI))
Dan Gohman475871a2008-07-27 21:46:04 +00006775 return SDValue();
Evan Cheng206ee9d2006-07-07 08:33:52 +00006776
Dan Gohmand3006222007-07-27 17:16:43 +00006777 LoadSDNode *LD = cast<LoadSDNode>(Base);
Gabor Greifba36cb52008-08-28 21:40:38 +00006778 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
Evan Cheng466685d2006-10-09 20:57:25 +00006779 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
Dan Gohmand3006222007-07-27 17:16:43 +00006780 LD->getSrcValueOffset(), LD->isVolatile());
Evan Cheng71f489d2008-05-05 22:12:23 +00006781 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6782 LD->getSrcValueOffset(), LD->isVolatile(),
6783 LD->getAlignment());
Evan Cheng206ee9d2006-07-07 08:33:52 +00006784}
6785
Evan Cheng9bfa03c2008-05-12 23:04:07 +00006786/// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
Dan Gohman475871a2008-07-27 21:46:04 +00006787static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
Evan Chengad4196b2008-05-12 19:56:52 +00006788 const X86Subtarget *Subtarget,
6789 const TargetLowering &TLI) {
Evan Chengf26ffe92008-05-29 08:22:04 +00006790 unsigned NumOps = N->getNumOperands();
6791
Evan Chengd880b972008-05-09 21:53:03 +00006792 // Ignore single operand BUILD_VECTOR.
Evan Chengf26ffe92008-05-29 08:22:04 +00006793 if (NumOps == 1)
Dan Gohman475871a2008-07-27 21:46:04 +00006794 return SDValue();
Evan Chengd880b972008-05-09 21:53:03 +00006795
Duncan Sands83ec4b62008-06-06 12:08:01 +00006796 MVT VT = N->getValueType(0);
6797 MVT EVT = VT.getVectorElementType();
Evan Chengd880b972008-05-09 21:53:03 +00006798 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
6799 // We are looking for load i64 and zero extend. We want to transform
6800 // it before legalizer has a chance to expand it. Also look for i64
6801 // BUILD_PAIR bit casted to f64.
Dan Gohman475871a2008-07-27 21:46:04 +00006802 return SDValue();
Evan Chengd880b972008-05-09 21:53:03 +00006803 // This must be an insertion into a zero vector.
Dan Gohman475871a2008-07-27 21:46:04 +00006804 SDValue HighElt = N->getOperand(1);
Evan Cheng25210da2008-05-10 00:58:41 +00006805 if (!isZeroNode(HighElt))
Dan Gohman475871a2008-07-27 21:46:04 +00006806 return SDValue();
Evan Chengd880b972008-05-09 21:53:03 +00006807
6808 // Value must be a load.
Gabor Greifba36cb52008-08-28 21:40:38 +00006809 SDNode *Base = N->getOperand(0).getNode();
Evan Chengd880b972008-05-09 21:53:03 +00006810 if (!isa<LoadSDNode>(Base)) {
Evan Cheng9bfa03c2008-05-12 23:04:07 +00006811 if (Base->getOpcode() != ISD::BIT_CONVERT)
Dan Gohman475871a2008-07-27 21:46:04 +00006812 return SDValue();
Gabor Greifba36cb52008-08-28 21:40:38 +00006813 Base = Base->getOperand(0).getNode();
Evan Cheng9bfa03c2008-05-12 23:04:07 +00006814 if (!isa<LoadSDNode>(Base))
Dan Gohman475871a2008-07-27 21:46:04 +00006815 return SDValue();
Evan Chengd880b972008-05-09 21:53:03 +00006816 }
Evan Chengd880b972008-05-09 21:53:03 +00006817
6818 // Transform it into VZEXT_LOAD addr.
Evan Cheng9bfa03c2008-05-12 23:04:07 +00006819 LoadSDNode *LD = cast<LoadSDNode>(Base);
Nate Begemanf7333bf2008-05-28 00:24:25 +00006820
6821 // Load must not be an extload.
6822 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
Dan Gohman475871a2008-07-27 21:46:04 +00006823 return SDValue();
Nate Begemanf7333bf2008-05-28 00:24:25 +00006824
Evan Chengd880b972008-05-09 21:53:03 +00006825 return DAG.getNode(X86ISD::VZEXT_LOAD, VT, LD->getChain(), LD->getBasePtr());
6826}
6827
Chris Lattner83e6c992006-10-04 06:57:07 +00006828/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
Dan Gohman475871a2008-07-27 21:46:04 +00006829static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
Chris Lattner83e6c992006-10-04 06:57:07 +00006830 const X86Subtarget *Subtarget) {
Dan Gohman475871a2008-07-27 21:46:04 +00006831 SDValue Cond = N->getOperand(0);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006832
Chris Lattner83e6c992006-10-04 06:57:07 +00006833 // If we have SSE[12] support, try to form min/max nodes.
6834 if (Subtarget->hasSSE2() &&
6835 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
6836 if (Cond.getOpcode() == ISD::SETCC) {
6837 // Get the LHS/RHS of the select.
Dan Gohman475871a2008-07-27 21:46:04 +00006838 SDValue LHS = N->getOperand(1);
6839 SDValue RHS = N->getOperand(2);
Chris Lattner83e6c992006-10-04 06:57:07 +00006840 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006841
Evan Cheng8ca29322006-11-10 21:43:37 +00006842 unsigned Opcode = 0;
Chris Lattner83e6c992006-10-04 06:57:07 +00006843 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
Chris Lattner1907a7b2006-10-05 04:11:26 +00006844 switch (CC) {
6845 default: break;
6846 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
6847 case ISD::SETULE:
6848 case ISD::SETLE:
6849 if (!UnsafeFPMath) break;
6850 // FALL THROUGH.
6851 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
6852 case ISD::SETLT:
Evan Cheng8ca29322006-11-10 21:43:37 +00006853 Opcode = X86ISD::FMIN;
Chris Lattner1907a7b2006-10-05 04:11:26 +00006854 break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006855
Chris Lattner1907a7b2006-10-05 04:11:26 +00006856 case ISD::SETOGT: // (X > Y) ? X : Y -> max
6857 case ISD::SETUGT:
6858 case ISD::SETGT:
6859 if (!UnsafeFPMath) break;
6860 // FALL THROUGH.
6861 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
6862 case ISD::SETGE:
Evan Cheng8ca29322006-11-10 21:43:37 +00006863 Opcode = X86ISD::FMAX;
Chris Lattner1907a7b2006-10-05 04:11:26 +00006864 break;
6865 }
Chris Lattner83e6c992006-10-04 06:57:07 +00006866 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
Chris Lattner1907a7b2006-10-05 04:11:26 +00006867 switch (CC) {
6868 default: break;
6869 case ISD::SETOGT: // (X > Y) ? Y : X -> min
6870 case ISD::SETUGT:
6871 case ISD::SETGT:
6872 if (!UnsafeFPMath) break;
6873 // FALL THROUGH.
6874 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
6875 case ISD::SETGE:
Evan Cheng8ca29322006-11-10 21:43:37 +00006876 Opcode = X86ISD::FMIN;
Chris Lattner1907a7b2006-10-05 04:11:26 +00006877 break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006878
Chris Lattner1907a7b2006-10-05 04:11:26 +00006879 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
6880 case ISD::SETULE:
6881 case ISD::SETLE:
6882 if (!UnsafeFPMath) break;
6883 // FALL THROUGH.
6884 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
6885 case ISD::SETLT:
Evan Cheng8ca29322006-11-10 21:43:37 +00006886 Opcode = X86ISD::FMAX;
Chris Lattner1907a7b2006-10-05 04:11:26 +00006887 break;
6888 }
Chris Lattner83e6c992006-10-04 06:57:07 +00006889 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006890
Evan Cheng8ca29322006-11-10 21:43:37 +00006891 if (Opcode)
6892 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
Chris Lattner83e6c992006-10-04 06:57:07 +00006893 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00006894
Chris Lattner83e6c992006-10-04 06:57:07 +00006895 }
6896
Dan Gohman475871a2008-07-27 21:46:04 +00006897 return SDValue();
Chris Lattner83e6c992006-10-04 06:57:07 +00006898}
6899
Chris Lattner149a4e52008-02-22 02:09:43 +00006900/// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
Dan Gohman475871a2008-07-27 21:46:04 +00006901static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
Chris Lattner149a4e52008-02-22 02:09:43 +00006902 const X86Subtarget *Subtarget) {
6903 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
6904 // the FP state in cases where an emms may be missing.
Dale Johannesen079f2a62008-02-25 19:20:14 +00006905 // A preferable solution to the general problem is to figure out the right
6906 // places to insert EMMS. This qualifies as a quick hack.
Evan Cheng7e2ff772008-05-08 00:57:18 +00006907 StoreSDNode *St = cast<StoreSDNode>(N);
Duncan Sands83ec4b62008-06-06 12:08:01 +00006908 if (St->getValue().getValueType().isVector() &&
6909 St->getValue().getValueType().getSizeInBits() == 64 &&
Dale Johannesen079f2a62008-02-25 19:20:14 +00006910 isa<LoadSDNode>(St->getValue()) &&
6911 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
6912 St->getChain().hasOneUse() && !St->isVolatile()) {
Gabor Greifba36cb52008-08-28 21:40:38 +00006913 SDNode* LdVal = St->getValue().getNode();
Dale Johannesen079f2a62008-02-25 19:20:14 +00006914 LoadSDNode *Ld = 0;
6915 int TokenFactorIndex = -1;
Dan Gohman475871a2008-07-27 21:46:04 +00006916 SmallVector<SDValue, 8> Ops;
Gabor Greifba36cb52008-08-28 21:40:38 +00006917 SDNode* ChainVal = St->getChain().getNode();
Dale Johannesen079f2a62008-02-25 19:20:14 +00006918 // Must be a store of a load. We currently handle two cases: the load
6919 // is a direct child, and it's under an intervening TokenFactor. It is
6920 // possible to dig deeper under nested TokenFactors.
Dale Johannesen14e2ea92008-02-25 22:29:22 +00006921 if (ChainVal == LdVal)
Dale Johannesen079f2a62008-02-25 19:20:14 +00006922 Ld = cast<LoadSDNode>(St->getChain());
6923 else if (St->getValue().hasOneUse() &&
6924 ChainVal->getOpcode() == ISD::TokenFactor) {
6925 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
Gabor Greifba36cb52008-08-28 21:40:38 +00006926 if (ChainVal->getOperand(i).getNode() == LdVal) {
Dale Johannesen079f2a62008-02-25 19:20:14 +00006927 TokenFactorIndex = i;
6928 Ld = cast<LoadSDNode>(St->getValue());
6929 } else
6930 Ops.push_back(ChainVal->getOperand(i));
6931 }
6932 }
6933 if (Ld) {
6934 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
6935 if (Subtarget->is64Bit()) {
Dan Gohman475871a2008-07-27 21:46:04 +00006936 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
Dale Johannesen079f2a62008-02-25 19:20:14 +00006937 Ld->getBasePtr(), Ld->getSrcValue(),
6938 Ld->getSrcValueOffset(), Ld->isVolatile(),
6939 Ld->getAlignment());
Dan Gohman475871a2008-07-27 21:46:04 +00006940 SDValue NewChain = NewLd.getValue(1);
Dale Johannesen079f2a62008-02-25 19:20:14 +00006941 if (TokenFactorIndex != -1) {
Dan Gohmand4a2ad32008-03-28 23:45:16 +00006942 Ops.push_back(NewChain);
Dale Johannesen079f2a62008-02-25 19:20:14 +00006943 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6944 Ops.size());
6945 }
6946 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
6947 St->getSrcValue(), St->getSrcValueOffset(),
6948 St->isVolatile(), St->getAlignment());
6949 }
6950
6951 // Otherwise, lower to two 32-bit copies.
Dan Gohman475871a2008-07-27 21:46:04 +00006952 SDValue LoAddr = Ld->getBasePtr();
6953 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
Duncan Sands83ec4b62008-06-06 12:08:01 +00006954 DAG.getConstant(4, MVT::i32));
Dale Johannesen079f2a62008-02-25 19:20:14 +00006955
Dan Gohman475871a2008-07-27 21:46:04 +00006956 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
Dale Johannesen079f2a62008-02-25 19:20:14 +00006957 Ld->getSrcValue(), Ld->getSrcValueOffset(),
6958 Ld->isVolatile(), Ld->getAlignment());
Dan Gohman475871a2008-07-27 21:46:04 +00006959 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
Dale Johannesen079f2a62008-02-25 19:20:14 +00006960 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
6961 Ld->isVolatile(),
6962 MinAlign(Ld->getAlignment(), 4));
6963
Dan Gohman475871a2008-07-27 21:46:04 +00006964 SDValue NewChain = LoLd.getValue(1);
Dale Johannesen079f2a62008-02-25 19:20:14 +00006965 if (TokenFactorIndex != -1) {
6966 Ops.push_back(LoLd);
6967 Ops.push_back(HiLd);
6968 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6969 Ops.size());
6970 }
6971
6972 LoAddr = St->getBasePtr();
6973 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
Duncan Sands83ec4b62008-06-06 12:08:01 +00006974 DAG.getConstant(4, MVT::i32));
Dale Johannesen079f2a62008-02-25 19:20:14 +00006975
Dan Gohman475871a2008-07-27 21:46:04 +00006976 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
Chris Lattner149a4e52008-02-22 02:09:43 +00006977 St->getSrcValue(), St->getSrcValueOffset(),
6978 St->isVolatile(), St->getAlignment());
Dan Gohman475871a2008-07-27 21:46:04 +00006979 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
Gabor Greif327ef032008-08-28 23:19:51 +00006980 St->getSrcValue(),
6981 St->getSrcValueOffset() + 4,
Dale Johannesen079f2a62008-02-25 19:20:14 +00006982 St->isVolatile(),
6983 MinAlign(St->getAlignment(), 4));
6984 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
Chris Lattner149a4e52008-02-22 02:09:43 +00006985 }
Chris Lattner149a4e52008-02-22 02:09:43 +00006986 }
Dan Gohman475871a2008-07-27 21:46:04 +00006987 return SDValue();
Chris Lattner149a4e52008-02-22 02:09:43 +00006988}
6989
Chris Lattner6cf73262008-01-25 06:14:17 +00006990/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
6991/// X86ISD::FXOR nodes.
Dan Gohman475871a2008-07-27 21:46:04 +00006992static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
Chris Lattner6cf73262008-01-25 06:14:17 +00006993 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
6994 // F[X]OR(0.0, x) -> x
6995 // F[X]OR(x, 0.0) -> x
Chris Lattneraf723b92008-01-25 05:46:26 +00006996 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6997 if (C->getValueAPF().isPosZero())
6998 return N->getOperand(1);
6999 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7000 if (C->getValueAPF().isPosZero())
7001 return N->getOperand(0);
Dan Gohman475871a2008-07-27 21:46:04 +00007002 return SDValue();
Chris Lattneraf723b92008-01-25 05:46:26 +00007003}
7004
7005/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
Dan Gohman475871a2008-07-27 21:46:04 +00007006static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
Chris Lattneraf723b92008-01-25 05:46:26 +00007007 // FAND(0.0, x) -> 0.0
7008 // FAND(x, 0.0) -> 0.0
7009 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7010 if (C->getValueAPF().isPosZero())
7011 return N->getOperand(0);
7012 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7013 if (C->getValueAPF().isPosZero())
7014 return N->getOperand(1);
Dan Gohman475871a2008-07-27 21:46:04 +00007015 return SDValue();
Chris Lattneraf723b92008-01-25 05:46:26 +00007016}
7017
Chris Lattner83e6c992006-10-04 06:57:07 +00007018
Dan Gohman475871a2008-07-27 21:46:04 +00007019SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
Evan Cheng206ee9d2006-07-07 08:33:52 +00007020 DAGCombinerInfo &DCI) const {
Evan Cheng206ee9d2006-07-07 08:33:52 +00007021 SelectionDAG &DAG = DCI.DAG;
7022 switch (N->getOpcode()) {
7023 default: break;
Evan Chengad4196b2008-05-12 19:56:52 +00007024 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
7025 case ISD::BUILD_VECTOR:
7026 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
Chris Lattneraf723b92008-01-25 05:46:26 +00007027 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
Evan Cheng7e2ff772008-05-08 00:57:18 +00007028 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
Chris Lattner6cf73262008-01-25 06:14:17 +00007029 case X86ISD::FXOR:
Chris Lattneraf723b92008-01-25 05:46:26 +00007030 case X86ISD::FOR: return PerformFORCombine(N, DAG);
7031 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
Evan Cheng206ee9d2006-07-07 08:33:52 +00007032 }
7033
Dan Gohman475871a2008-07-27 21:46:04 +00007034 return SDValue();
Evan Cheng206ee9d2006-07-07 08:33:52 +00007035}
7036
Evan Cheng60c07e12006-07-05 22:17:51 +00007037//===----------------------------------------------------------------------===//
7038// X86 Inline Assembly Support
7039//===----------------------------------------------------------------------===//
7040
Chris Lattnerf4dff842006-07-11 02:54:03 +00007041/// getConstraintType - Given a constraint letter, return the type of
7042/// constraint it is for this target.
7043X86TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +00007044X86TargetLowering::getConstraintType(const std::string &Constraint) const {
7045 if (Constraint.size() == 1) {
7046 switch (Constraint[0]) {
7047 case 'A':
Chris Lattnerfce84ac2008-03-11 19:06:29 +00007048 case 'f':
Chris Lattner4234f572007-03-25 02:14:49 +00007049 case 'r':
7050 case 'R':
7051 case 'l':
7052 case 'q':
7053 case 'Q':
7054 case 'x':
Dale Johannesen2ffbcac2008-04-01 00:57:48 +00007055 case 'y':
Chris Lattner4234f572007-03-25 02:14:49 +00007056 case 'Y':
7057 return C_RegisterClass;
7058 default:
7059 break;
7060 }
Chris Lattnerf4dff842006-07-11 02:54:03 +00007061 }
Chris Lattner4234f572007-03-25 02:14:49 +00007062 return TargetLowering::getConstraintType(Constraint);
Chris Lattnerf4dff842006-07-11 02:54:03 +00007063}
7064
Dale Johannesenba2a0b92008-01-29 02:21:21 +00007065/// LowerXConstraint - try to replace an X constraint, which matches anything,
7066/// with another that has more specific requirements based on the type of the
7067/// corresponding operand.
Chris Lattner5e764232008-04-26 23:02:14 +00007068const char *X86TargetLowering::
Duncan Sands83ec4b62008-06-06 12:08:01 +00007069LowerXConstraint(MVT ConstraintVT) const {
Chris Lattner5e764232008-04-26 23:02:14 +00007070 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
7071 // 'f' like normal targets.
Duncan Sands83ec4b62008-06-06 12:08:01 +00007072 if (ConstraintVT.isFloatingPoint()) {
Dale Johannesenba2a0b92008-01-29 02:21:21 +00007073 if (Subtarget->hasSSE2())
Chris Lattner5e764232008-04-26 23:02:14 +00007074 return "Y";
7075 if (Subtarget->hasSSE1())
7076 return "x";
7077 }
7078
7079 return TargetLowering::LowerXConstraint(ConstraintVT);
Dale Johannesenba2a0b92008-01-29 02:21:21 +00007080}
7081
Chris Lattner48884cd2007-08-25 00:47:38 +00007082/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7083/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +00007084void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Chris Lattner48884cd2007-08-25 00:47:38 +00007085 char Constraint,
Dan Gohman475871a2008-07-27 21:46:04 +00007086 std::vector<SDValue>&Ops,
Chris Lattner5e764232008-04-26 23:02:14 +00007087 SelectionDAG &DAG) const {
Dan Gohman475871a2008-07-27 21:46:04 +00007088 SDValue Result(0, 0);
Chris Lattner48884cd2007-08-25 00:47:38 +00007089
Chris Lattner22aaf1d2006-10-31 20:13:11 +00007090 switch (Constraint) {
7091 default: break;
Devang Patel84f7fd22007-03-17 00:13:28 +00007092 case 'I':
Chris Lattner188b9fe2007-03-25 01:57:35 +00007093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00007094 if (C->getZExtValue() <= 31) {
7095 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
Chris Lattner48884cd2007-08-25 00:47:38 +00007096 break;
7097 }
Devang Patel84f7fd22007-03-17 00:13:28 +00007098 }
Chris Lattner48884cd2007-08-25 00:47:38 +00007099 return;
Chris Lattner188b9fe2007-03-25 01:57:35 +00007100 case 'N':
7101 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00007102 if (C->getZExtValue() <= 255) {
7103 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
Chris Lattner48884cd2007-08-25 00:47:38 +00007104 break;
7105 }
Chris Lattner188b9fe2007-03-25 01:57:35 +00007106 }
Chris Lattner48884cd2007-08-25 00:47:38 +00007107 return;
Chris Lattnerdc43a882007-05-03 16:52:29 +00007108 case 'i': {
Chris Lattner22aaf1d2006-10-31 20:13:11 +00007109 // Literal immediates are always ok.
Chris Lattner48884cd2007-08-25 00:47:38 +00007110 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00007111 Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType());
Chris Lattner48884cd2007-08-25 00:47:38 +00007112 break;
7113 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007114
Chris Lattnerdc43a882007-05-03 16:52:29 +00007115 // If we are in non-pic codegen mode, we allow the address of a global (with
7116 // an optional displacement) to be used with 'i'.
7117 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
7118 int64_t Offset = 0;
7119
7120 // Match either (GA) or (GA+C)
7121 if (GA) {
7122 Offset = GA->getOffset();
7123 } else if (Op.getOpcode() == ISD::ADD) {
7124 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7125 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7126 if (C && GA) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00007127 Offset = GA->getOffset()+C->getZExtValue();
Chris Lattnerdc43a882007-05-03 16:52:29 +00007128 } else {
7129 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7130 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7131 if (C && GA)
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00007132 Offset = GA->getOffset()+C->getZExtValue();
Chris Lattnerdc43a882007-05-03 16:52:29 +00007133 else
7134 C = 0, GA = 0;
7135 }
7136 }
7137
7138 if (GA) {
7139 // If addressing this global requires a load (e.g. in PIC mode), we can't
7140 // match.
7141 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
7142 false))
Chris Lattner48884cd2007-08-25 00:47:38 +00007143 return;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007144
Chris Lattnerdc43a882007-05-03 16:52:29 +00007145 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
7146 Offset);
Chris Lattner48884cd2007-08-25 00:47:38 +00007147 Result = Op;
7148 break;
Chris Lattner22aaf1d2006-10-31 20:13:11 +00007149 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007150
Chris Lattner22aaf1d2006-10-31 20:13:11 +00007151 // Otherwise, not valid for this mode.
Chris Lattner48884cd2007-08-25 00:47:38 +00007152 return;
Chris Lattner22aaf1d2006-10-31 20:13:11 +00007153 }
Chris Lattnerdc43a882007-05-03 16:52:29 +00007154 }
Chris Lattner48884cd2007-08-25 00:47:38 +00007155
Gabor Greifba36cb52008-08-28 21:40:38 +00007156 if (Result.getNode()) {
Chris Lattner48884cd2007-08-25 00:47:38 +00007157 Ops.push_back(Result);
7158 return;
7159 }
7160 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
Chris Lattner22aaf1d2006-10-31 20:13:11 +00007161}
7162
Chris Lattner259e97c2006-01-31 19:43:35 +00007163std::vector<unsigned> X86TargetLowering::
Chris Lattner1efa40f2006-02-22 00:56:39 +00007164getRegClassForInlineAsmConstraint(const std::string &Constraint,
Duncan Sands83ec4b62008-06-06 12:08:01 +00007165 MVT VT) const {
Chris Lattner259e97c2006-01-31 19:43:35 +00007166 if (Constraint.size() == 1) {
7167 // FIXME: not handling fp-stack yet!
Chris Lattner259e97c2006-01-31 19:43:35 +00007168 switch (Constraint[0]) { // GCC X86 Constraint Letters
Chris Lattnerf4dff842006-07-11 02:54:03 +00007169 default: break; // Unknown constraint letter
7170 case 'A': // EAX/EDX
7171 if (VT == MVT::i32 || VT == MVT::i64)
7172 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
7173 break;
Chris Lattner259e97c2006-01-31 19:43:35 +00007174 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
7175 case 'Q': // Q_REGS
Chris Lattner80a7ecc2006-05-06 00:29:37 +00007176 if (VT == MVT::i32)
7177 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
7178 else if (VT == MVT::i16)
7179 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
7180 else if (VT == MVT::i8)
Evan Cheng12914382007-08-13 23:27:11 +00007181 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
Chris Lattner03e6c702007-11-04 06:51:12 +00007182 else if (VT == MVT::i64)
7183 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
7184 break;
Chris Lattner259e97c2006-01-31 19:43:35 +00007185 }
7186 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007187
Chris Lattner1efa40f2006-02-22 00:56:39 +00007188 return std::vector<unsigned>();
Chris Lattner259e97c2006-01-31 19:43:35 +00007189}
Chris Lattnerf76d1802006-07-31 23:26:50 +00007190
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007191std::pair<unsigned, const TargetRegisterClass*>
Chris Lattnerf76d1802006-07-31 23:26:50 +00007192X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Duncan Sands83ec4b62008-06-06 12:08:01 +00007193 MVT VT) const {
Chris Lattnerad043e82007-04-09 05:11:28 +00007194 // First, see if this is a constraint that directly corresponds to an LLVM
7195 // register class.
7196 if (Constraint.size() == 1) {
7197 // GCC Constraint Letters
7198 switch (Constraint[0]) {
7199 default: break;
Chris Lattner0f65cad2007-04-09 05:49:22 +00007200 case 'r': // GENERAL_REGS
7201 case 'R': // LEGACY_REGS
7202 case 'l': // INDEX_REGS
7203 if (VT == MVT::i64 && Subtarget->is64Bit())
7204 return std::make_pair(0U, X86::GR64RegisterClass);
7205 if (VT == MVT::i32)
7206 return std::make_pair(0U, X86::GR32RegisterClass);
7207 else if (VT == MVT::i16)
7208 return std::make_pair(0U, X86::GR16RegisterClass);
7209 else if (VT == MVT::i8)
7210 return std::make_pair(0U, X86::GR8RegisterClass);
7211 break;
Chris Lattnerfce84ac2008-03-11 19:06:29 +00007212 case 'f': // FP Stack registers.
7213 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
7214 // value to the correct fpstack register class.
7215 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
7216 return std::make_pair(0U, X86::RFP32RegisterClass);
7217 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
7218 return std::make_pair(0U, X86::RFP64RegisterClass);
7219 return std::make_pair(0U, X86::RFP80RegisterClass);
Chris Lattner6c284d72007-04-12 04:14:49 +00007220 case 'y': // MMX_REGS if MMX allowed.
7221 if (!Subtarget->hasMMX()) break;
7222 return std::make_pair(0U, X86::VR64RegisterClass);
7223 break;
Chris Lattner0f65cad2007-04-09 05:49:22 +00007224 case 'Y': // SSE_REGS if SSE2 allowed
7225 if (!Subtarget->hasSSE2()) break;
7226 // FALL THROUGH.
7227 case 'x': // SSE_REGS if SSE1 allowed
7228 if (!Subtarget->hasSSE1()) break;
Duncan Sands83ec4b62008-06-06 12:08:01 +00007229
7230 switch (VT.getSimpleVT()) {
Chris Lattner0f65cad2007-04-09 05:49:22 +00007231 default: break;
7232 // Scalar SSE types.
7233 case MVT::f32:
7234 case MVT::i32:
Chris Lattnerad043e82007-04-09 05:11:28 +00007235 return std::make_pair(0U, X86::FR32RegisterClass);
Chris Lattner0f65cad2007-04-09 05:49:22 +00007236 case MVT::f64:
7237 case MVT::i64:
Chris Lattnerad043e82007-04-09 05:11:28 +00007238 return std::make_pair(0U, X86::FR64RegisterClass);
Chris Lattner0f65cad2007-04-09 05:49:22 +00007239 // Vector types.
Chris Lattner0f65cad2007-04-09 05:49:22 +00007240 case MVT::v16i8:
7241 case MVT::v8i16:
7242 case MVT::v4i32:
7243 case MVT::v2i64:
7244 case MVT::v4f32:
7245 case MVT::v2f64:
7246 return std::make_pair(0U, X86::VR128RegisterClass);
7247 }
Chris Lattnerad043e82007-04-09 05:11:28 +00007248 break;
7249 }
7250 }
7251
Chris Lattnerf76d1802006-07-31 23:26:50 +00007252 // Use the default implementation in TargetLowering to convert the register
7253 // constraint into a member of a register class.
7254 std::pair<unsigned, const TargetRegisterClass*> Res;
7255 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
Chris Lattner1a60aa72006-10-31 19:42:44 +00007256
7257 // Not found as a standard register?
7258 if (Res.second == 0) {
7259 // GCC calls "st(0)" just plain "st".
7260 if (StringsEqualNoCase("{st}", Constraint)) {
7261 Res.first = X86::ST0;
Chris Lattner9b4baf12007-09-24 05:27:37 +00007262 Res.second = X86::RFP80RegisterClass;
Chris Lattner1a60aa72006-10-31 19:42:44 +00007263 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007264
Chris Lattner1a60aa72006-10-31 19:42:44 +00007265 return Res;
7266 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007267
Chris Lattnerf76d1802006-07-31 23:26:50 +00007268 // Otherwise, check to see if this is a register class of the wrong value
7269 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
7270 // turn into {ax},{dx}.
7271 if (Res.second->hasType(VT))
7272 return Res; // Correct type already, nothing to do.
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007273
Chris Lattnerf76d1802006-07-31 23:26:50 +00007274 // All of the single-register GCC register classes map their values onto
7275 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
7276 // really want an 8-bit or 32-bit register, map to the appropriate register
7277 // class and return the appropriate register.
Chris Lattner6ba50a92008-08-26 06:19:02 +00007278 if (Res.second == X86::GR16RegisterClass) {
7279 if (VT == MVT::i8) {
7280 unsigned DestReg = 0;
7281 switch (Res.first) {
7282 default: break;
7283 case X86::AX: DestReg = X86::AL; break;
7284 case X86::DX: DestReg = X86::DL; break;
7285 case X86::CX: DestReg = X86::CL; break;
7286 case X86::BX: DestReg = X86::BL; break;
7287 }
7288 if (DestReg) {
7289 Res.first = DestReg;
7290 Res.second = Res.second = X86::GR8RegisterClass;
7291 }
7292 } else if (VT == MVT::i32) {
7293 unsigned DestReg = 0;
7294 switch (Res.first) {
7295 default: break;
7296 case X86::AX: DestReg = X86::EAX; break;
7297 case X86::DX: DestReg = X86::EDX; break;
7298 case X86::CX: DestReg = X86::ECX; break;
7299 case X86::BX: DestReg = X86::EBX; break;
7300 case X86::SI: DestReg = X86::ESI; break;
7301 case X86::DI: DestReg = X86::EDI; break;
7302 case X86::BP: DestReg = X86::EBP; break;
7303 case X86::SP: DestReg = X86::ESP; break;
7304 }
7305 if (DestReg) {
7306 Res.first = DestReg;
7307 Res.second = Res.second = X86::GR32RegisterClass;
7308 }
7309 } else if (VT == MVT::i64) {
7310 unsigned DestReg = 0;
7311 switch (Res.first) {
7312 default: break;
7313 case X86::AX: DestReg = X86::RAX; break;
7314 case X86::DX: DestReg = X86::RDX; break;
7315 case X86::CX: DestReg = X86::RCX; break;
7316 case X86::BX: DestReg = X86::RBX; break;
7317 case X86::SI: DestReg = X86::RSI; break;
7318 case X86::DI: DestReg = X86::RDI; break;
7319 case X86::BP: DestReg = X86::RBP; break;
7320 case X86::SP: DestReg = X86::RSP; break;
7321 }
7322 if (DestReg) {
7323 Res.first = DestReg;
7324 Res.second = Res.second = X86::GR64RegisterClass;
7325 }
Chris Lattnerf76d1802006-07-31 23:26:50 +00007326 }
Chris Lattner6ba50a92008-08-26 06:19:02 +00007327 } else if (Res.second == X86::FR32RegisterClass ||
7328 Res.second == X86::FR64RegisterClass ||
7329 Res.second == X86::VR128RegisterClass) {
7330 // Handle references to XMM physical registers that got mapped into the
7331 // wrong class. This can happen with constraints like {xmm0} where the
7332 // target independent register mapper will just pick the first match it can
7333 // find, ignoring the required type.
7334 if (VT == MVT::f32)
7335 Res.second = X86::FR32RegisterClass;
7336 else if (VT == MVT::f64)
7337 Res.second = X86::FR64RegisterClass;
7338 else if (X86::VR128RegisterClass->hasType(VT))
7339 Res.second = X86::VR128RegisterClass;
Chris Lattnerf76d1802006-07-31 23:26:50 +00007340 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00007341
Chris Lattnerf76d1802006-07-31 23:26:50 +00007342 return Res;
7343}