sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1 | |
| 2 | /*--------------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin guest_x86_toIR.c ---*/ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 4 | /*--------------------------------------------------------------------*/ |
| 5 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | |
sewardj | 785952d | 2015-08-21 11:29:16 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2015 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 11 | info@open-works.net |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 36 | /* Translates x86 code to IR. */ |
| 37 | |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 38 | /* TODO: |
sewardj | 45f1ff8 | 2005-05-05 12:04:14 +0000 | [diff] [blame] | 39 | |
sewardj | 3b3eacd | 2005-08-24 10:01:36 +0000 | [diff] [blame] | 40 | All Puts to CC_OP/CC_DEP1/CC_DEP2/CC_NDEP should really be checked |
| 41 | to ensure a 32-bit value is being written. |
| 42 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 43 | FUCOMI(P): what happens to A and S flags? Currently are forced |
| 44 | to zero. |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 45 | |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 46 | x87 FP Limitations: |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 47 | |
| 48 | * all arithmetic done at 64 bits |
| 49 | |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 50 | * no FP exceptions, except for handling stack over/underflow |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 51 | |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 52 | * FP rounding mode observed only for float->int conversions |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 53 | and int->float conversions which could lose accuracy, and |
| 54 | for float-to-float rounding. For all other operations, |
| 55 | round-to-nearest is used, regardless. |
| 56 | |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 57 | * some of the FCOM cases could do with testing -- not convinced |
| 58 | that the args are the right way round. |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 59 | |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 60 | * FSAVE does not re-initialise the FPU; it should do |
| 61 | |
| 62 | * FINIT not only initialises the FPU environment, it also |
| 63 | zeroes all the FP registers. It should leave the registers |
| 64 | unchanged. |
| 65 | |
sewardj | cb2c99d | 2004-12-17 19:14:24 +0000 | [diff] [blame] | 66 | SAHF should cause eflags[1] == 1, and in fact it produces 0. As |
| 67 | per Intel docs this bit has no meaning anyway. Since PUSHF is the |
| 68 | only way to observe eflags[1], a proper fix would be to make that |
| 69 | bit be set by PUSHF. |
| 70 | |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 71 | The state of %eflags.AC (alignment check, bit 18) is recorded by |
| 72 | the simulation (viz, if you set it with popf then a pushf produces |
| 73 | the value you set it to), but it is otherwise ignored. In |
| 74 | particular, setting it to 1 does NOT cause alignment checking to |
| 75 | happen. Programs that set it to 1 and then rely on the resulting |
| 76 | SIGBUSs to inform them of misaligned accesses will not work. |
| 77 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 78 | Implementation of sysenter is necessarily partial. sysenter is a |
| 79 | kind of system call entry. When doing a sysenter, the return |
| 80 | address is not known -- that is something that is beyond Vex's |
| 81 | knowledge. So the generated IR forces a return to the scheduler, |
| 82 | which can do what it likes to simulate the systenter, but it MUST |
| 83 | set this thread's guest_EIP field with the continuation address |
| 84 | before resuming execution. If that doesn't happen, the thread will |
| 85 | jump to address zero, which is probably fatal. |
sewardj | f07ed03 | 2005-08-07 14:48:03 +0000 | [diff] [blame] | 86 | |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 87 | This module uses global variables and so is not MT-safe (if that |
sewardj | e395ae8 | 2005-02-26 02:00:50 +0000 | [diff] [blame] | 88 | should ever become relevant). |
| 89 | |
| 90 | The delta values are 32-bit ints, not 64-bit ints. That means |
| 91 | this module may not work right if run on a 64-bit host. That should |
| 92 | be fixed properly, really -- if anyone ever wants to use Vex to |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 93 | translate x86 code for execution on a 64-bit host. |
| 94 | |
| 95 | casLE (implementation of lock-prefixed insns) and rep-prefixed |
| 96 | insns: the side-exit back to the start of the insn is done with |
| 97 | Ijk_Boring. This is quite wrong, it should be done with |
| 98 | Ijk_NoRedir, since otherwise the side exit, which is intended to |
| 99 | restart the instruction for whatever reason, could go somewhere |
| 100 | entirely else. Doing it right (with Ijk_NoRedir jumps) would make |
| 101 | no-redir jumps performance critical, at least for rep-prefixed |
| 102 | instructions, since all iterations thereof would involve such a |
| 103 | jump. It's not such a big deal with casLE since the side exit is |
| 104 | only taken if the CAS fails, that is, the location is contended, |
| 105 | which is relatively unlikely. |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 106 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 107 | XXXX: Nov 2009: handling of SWP on ARM suffers from the same |
| 108 | problem. |
| 109 | |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 110 | Note also, the test for CAS success vs failure is done using |
| 111 | Iop_CasCmp{EQ,NE}{8,16,32,64} rather than the ordinary |
| 112 | Iop_Cmp{EQ,NE} equivalents. This is so as to tell Memcheck that it |
| 113 | shouldn't definedness-check these comparisons. See |
| 114 | COMMENT_ON_CasCmpEQ in memcheck/mc_translate.c for |
| 115 | background/rationale. |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 116 | */ |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 117 | |
sewardj | 9f8a395 | 2005-04-06 10:27:11 +0000 | [diff] [blame] | 118 | /* Performance holes: |
| 119 | |
| 120 | - fcom ; fstsw %ax ; sahf |
| 121 | sahf does not update the O flag (sigh) and so O needs to |
| 122 | be computed. This is done expensively; it would be better |
| 123 | to have a calculate_eflags_o helper. |
| 124 | |
| 125 | - emwarns; some FP codes can generate huge numbers of these |
| 126 | if the fpucw is changed in an inner loop. It would be |
| 127 | better for the guest state to have an emwarn-enable reg |
| 128 | which can be set zero or nonzero. If it is zero, emwarns |
| 129 | are not flagged, and instead control just flows all the |
| 130 | way through bbs as usual. |
| 131 | */ |
| 132 | |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 133 | /* "Special" instructions. |
| 134 | |
| 135 | This instruction decoder can decode three special instructions |
| 136 | which mean nothing natively (are no-ops as far as regs/mem are |
| 137 | concerned) but have meaning for supporting Valgrind. A special |
| 138 | instruction is flagged by the 12-byte preamble C1C703 C1C70D C1C71D |
| 139 | C1C713 (in the standard interpretation, that means: roll $3, %edi; |
| 140 | roll $13, %edi; roll $29, %edi; roll $19, %edi). Following that, |
| 141 | one of the following 3 are allowed (standard interpretation in |
| 142 | parentheses): |
| 143 | |
| 144 | 87DB (xchgl %ebx,%ebx) %EDX = client_request ( %EAX ) |
| 145 | 87C9 (xchgl %ecx,%ecx) %EAX = guest_NRADDR |
| 146 | 87D2 (xchgl %edx,%edx) call-noredir *%EAX |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 147 | 87FF (xchgl %edi,%edi) IR injection |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 148 | |
| 149 | Any other bytes following the 12-byte preamble are illegal and |
| 150 | constitute a failure in instruction decoding. This all assumes |
| 151 | that the preamble will never occur except in specific code |
| 152 | fragments designed for Valgrind to catch. |
| 153 | |
| 154 | No prefixes may precede a "Special" instruction. |
| 155 | */ |
| 156 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 157 | /* LOCK prefixed instructions. These are translated using IR-level |
| 158 | CAS statements (IRCAS) and are believed to preserve atomicity, even |
| 159 | from the point of view of some other process racing against a |
| 160 | simulated one (presumably they communicate via a shared memory |
| 161 | segment). |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 162 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 163 | Handlers which are aware of LOCK prefixes are: |
| 164 | dis_op2_G_E (add, or, adc, sbb, and, sub, xor) |
| 165 | dis_cmpxchg_G_E (cmpxchg) |
| 166 | dis_Grp1 (add, or, adc, sbb, and, sub, xor) |
| 167 | dis_Grp3 (not, neg) |
| 168 | dis_Grp4 (inc, dec) |
| 169 | dis_Grp5 (inc, dec) |
| 170 | dis_Grp8_Imm (bts, btc, btr) |
| 171 | dis_bt_G_E (bts, btc, btr) |
| 172 | dis_xadd_G_E (xadd) |
| 173 | */ |
| 174 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 175 | |
| 176 | #include "libvex_basictypes.h" |
| 177 | #include "libvex_ir.h" |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 178 | #include "libvex.h" |
sewardj | f6dc3ce | 2004-10-19 01:03:46 +0000 | [diff] [blame] | 179 | #include "libvex_guest_x86.h" |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 180 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 181 | #include "main_util.h" |
| 182 | #include "main_globals.h" |
| 183 | #include "guest_generic_bb_to_IR.h" |
| 184 | #include "guest_generic_x87.h" |
| 185 | #include "guest_x86_defs.h" |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 186 | |
| 187 | |
| 188 | /*------------------------------------------------------------*/ |
| 189 | /*--- Globals ---*/ |
| 190 | /*------------------------------------------------------------*/ |
| 191 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 192 | /* These are set at the start of the translation of an insn, right |
| 193 | down in disInstr_X86, so that we don't have to pass them around |
| 194 | endlessly. They are all constant during the translation of any |
| 195 | given insn. */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 196 | |
| 197 | /* We need to know this to do sub-register accesses correctly. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 198 | static VexEndness host_endness; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 199 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 200 | /* Pointer to the guest code area (points to start of BB, not to the |
| 201 | insn being processed). */ |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 202 | static const UChar* guest_code; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 203 | |
| 204 | /* The guest address corresponding to guest_code[0]. */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 205 | static Addr32 guest_EIP_bbstart; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 206 | |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 207 | /* The guest address for the instruction currently being |
| 208 | translated. */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 209 | static Addr32 guest_EIP_curr_instr; |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 210 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 211 | /* The IRSB* into which we're generating code. */ |
| 212 | static IRSB* irsb; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 213 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 214 | |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 215 | /*------------------------------------------------------------*/ |
| 216 | /*--- Debugging output ---*/ |
| 217 | /*------------------------------------------------------------*/ |
| 218 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 219 | #define DIP(format, args...) \ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 220 | if (vex_traceflags & VEX_TRACE_FE) \ |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 221 | vex_printf(format, ## args) |
| 222 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 223 | #define DIS(buf, format, args...) \ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 224 | if (vex_traceflags & VEX_TRACE_FE) \ |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 225 | vex_sprintf(buf, format, ## args) |
| 226 | |
| 227 | |
| 228 | /*------------------------------------------------------------*/ |
sewardj | dcc85fc | 2004-10-26 13:26:20 +0000 | [diff] [blame] | 229 | /*--- Offsets of various parts of the x86 guest state. ---*/ |
| 230 | /*------------------------------------------------------------*/ |
| 231 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 232 | #define OFFB_EAX offsetof(VexGuestX86State,guest_EAX) |
| 233 | #define OFFB_EBX offsetof(VexGuestX86State,guest_EBX) |
| 234 | #define OFFB_ECX offsetof(VexGuestX86State,guest_ECX) |
| 235 | #define OFFB_EDX offsetof(VexGuestX86State,guest_EDX) |
| 236 | #define OFFB_ESP offsetof(VexGuestX86State,guest_ESP) |
| 237 | #define OFFB_EBP offsetof(VexGuestX86State,guest_EBP) |
| 238 | #define OFFB_ESI offsetof(VexGuestX86State,guest_ESI) |
| 239 | #define OFFB_EDI offsetof(VexGuestX86State,guest_EDI) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 240 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 241 | #define OFFB_EIP offsetof(VexGuestX86State,guest_EIP) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 242 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 243 | #define OFFB_CC_OP offsetof(VexGuestX86State,guest_CC_OP) |
| 244 | #define OFFB_CC_DEP1 offsetof(VexGuestX86State,guest_CC_DEP1) |
| 245 | #define OFFB_CC_DEP2 offsetof(VexGuestX86State,guest_CC_DEP2) |
| 246 | #define OFFB_CC_NDEP offsetof(VexGuestX86State,guest_CC_NDEP) |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 247 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 248 | #define OFFB_FPREGS offsetof(VexGuestX86State,guest_FPREG[0]) |
| 249 | #define OFFB_FPTAGS offsetof(VexGuestX86State,guest_FPTAG[0]) |
| 250 | #define OFFB_DFLAG offsetof(VexGuestX86State,guest_DFLAG) |
| 251 | #define OFFB_IDFLAG offsetof(VexGuestX86State,guest_IDFLAG) |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 252 | #define OFFB_ACFLAG offsetof(VexGuestX86State,guest_ACFLAG) |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 253 | #define OFFB_FTOP offsetof(VexGuestX86State,guest_FTOP) |
| 254 | #define OFFB_FC3210 offsetof(VexGuestX86State,guest_FC3210) |
| 255 | #define OFFB_FPROUND offsetof(VexGuestX86State,guest_FPROUND) |
| 256 | |
| 257 | #define OFFB_CS offsetof(VexGuestX86State,guest_CS) |
| 258 | #define OFFB_DS offsetof(VexGuestX86State,guest_DS) |
| 259 | #define OFFB_ES offsetof(VexGuestX86State,guest_ES) |
| 260 | #define OFFB_FS offsetof(VexGuestX86State,guest_FS) |
| 261 | #define OFFB_GS offsetof(VexGuestX86State,guest_GS) |
| 262 | #define OFFB_SS offsetof(VexGuestX86State,guest_SS) |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 263 | #define OFFB_LDT offsetof(VexGuestX86State,guest_LDT) |
| 264 | #define OFFB_GDT offsetof(VexGuestX86State,guest_GDT) |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 265 | |
| 266 | #define OFFB_SSEROUND offsetof(VexGuestX86State,guest_SSEROUND) |
| 267 | #define OFFB_XMM0 offsetof(VexGuestX86State,guest_XMM0) |
| 268 | #define OFFB_XMM1 offsetof(VexGuestX86State,guest_XMM1) |
| 269 | #define OFFB_XMM2 offsetof(VexGuestX86State,guest_XMM2) |
| 270 | #define OFFB_XMM3 offsetof(VexGuestX86State,guest_XMM3) |
| 271 | #define OFFB_XMM4 offsetof(VexGuestX86State,guest_XMM4) |
| 272 | #define OFFB_XMM5 offsetof(VexGuestX86State,guest_XMM5) |
| 273 | #define OFFB_XMM6 offsetof(VexGuestX86State,guest_XMM6) |
| 274 | #define OFFB_XMM7 offsetof(VexGuestX86State,guest_XMM7) |
| 275 | |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 276 | #define OFFB_EMNOTE offsetof(VexGuestX86State,guest_EMNOTE) |
sewardj | dcc85fc | 2004-10-26 13:26:20 +0000 | [diff] [blame] | 277 | |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 278 | #define OFFB_CMSTART offsetof(VexGuestX86State,guest_CMSTART) |
| 279 | #define OFFB_CMLEN offsetof(VexGuestX86State,guest_CMLEN) |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 280 | #define OFFB_NRADDR offsetof(VexGuestX86State,guest_NRADDR) |
| 281 | |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 282 | #define OFFB_IP_AT_SYSCALL offsetof(VexGuestX86State,guest_IP_AT_SYSCALL) |
| 283 | |
sewardj | dcc85fc | 2004-10-26 13:26:20 +0000 | [diff] [blame] | 284 | |
| 285 | /*------------------------------------------------------------*/ |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 286 | /*--- Helper bits and pieces for deconstructing the ---*/ |
| 287 | /*--- x86 insn stream. ---*/ |
| 288 | /*------------------------------------------------------------*/ |
| 289 | |
| 290 | /* This is the Intel register encoding -- integer regs. */ |
| 291 | #define R_EAX 0 |
| 292 | #define R_ECX 1 |
| 293 | #define R_EDX 2 |
| 294 | #define R_EBX 3 |
| 295 | #define R_ESP 4 |
| 296 | #define R_EBP 5 |
| 297 | #define R_ESI 6 |
| 298 | #define R_EDI 7 |
| 299 | |
| 300 | #define R_AL (0+R_EAX) |
| 301 | #define R_AH (4+R_EAX) |
| 302 | |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 303 | /* This is the Intel register encoding -- segment regs. */ |
| 304 | #define R_ES 0 |
| 305 | #define R_CS 1 |
| 306 | #define R_SS 2 |
| 307 | #define R_DS 3 |
| 308 | #define R_FS 4 |
| 309 | #define R_GS 5 |
| 310 | |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 311 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 312 | /* Add a statement to the list held by "irbb". */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 313 | static void stmt ( IRStmt* st ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 314 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 315 | addStmtToIRSB( irsb, st ); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 316 | } |
| 317 | |
| 318 | /* Generate a new temporary of the given type. */ |
| 319 | static IRTemp newTemp ( IRType ty ) |
| 320 | { |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 321 | vassert(isPlausibleIRType(ty)); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 322 | return newIRTemp( irsb->tyenv, ty ); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 323 | } |
| 324 | |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 325 | /* Various simple conversions */ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 326 | |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 327 | static UInt extend_s_8to32( UInt x ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 328 | { |
florian | 108e03f | 2015-03-10 16:11:58 +0000 | [diff] [blame] | 329 | return (UInt)((Int)(x << 24) >> 24); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 330 | } |
| 331 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 332 | static UInt extend_s_16to32 ( UInt x ) |
| 333 | { |
florian | 108e03f | 2015-03-10 16:11:58 +0000 | [diff] [blame] | 334 | return (UInt)((Int)(x << 16) >> 16); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 335 | } |
| 336 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 337 | /* Fetch a byte from the guest insn stream. */ |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 338 | static UChar getIByte ( Int delta ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 339 | { |
| 340 | return guest_code[delta]; |
| 341 | } |
| 342 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 343 | /* Extract the reg field from a modRM byte. */ |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 344 | static Int gregOfRM ( UChar mod_reg_rm ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 345 | { |
| 346 | return (Int)( (mod_reg_rm >> 3) & 7 ); |
| 347 | } |
| 348 | |
| 349 | /* Figure out whether the mod and rm parts of a modRM byte refer to a |
| 350 | register or memory. If so, the byte will have the form 11XXXYYY, |
| 351 | where YYY is the register number. */ |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 352 | static Bool epartIsReg ( UChar mod_reg_rm ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 353 | { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 354 | return toBool(0xC0 == (mod_reg_rm & 0xC0)); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 355 | } |
| 356 | |
| 357 | /* ... and extract the register number ... */ |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 358 | static Int eregOfRM ( UChar mod_reg_rm ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 359 | { |
| 360 | return (Int)(mod_reg_rm & 0x7); |
| 361 | } |
| 362 | |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 363 | /* Get a 8/16/32-bit unsigned value out of the insn stream. */ |
| 364 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 365 | static UChar getUChar ( Int delta ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 366 | { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 367 | UChar v = guest_code[delta+0]; |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 368 | return toUChar(v); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 369 | } |
| 370 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 371 | static UInt getUDisp16 ( Int delta ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 372 | { |
| 373 | UInt v = guest_code[delta+1]; v <<= 8; |
| 374 | v |= guest_code[delta+0]; |
| 375 | return v & 0xFFFF; |
| 376 | } |
| 377 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 378 | static UInt getUDisp32 ( Int delta ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 379 | { |
| 380 | UInt v = guest_code[delta+3]; v <<= 8; |
| 381 | v |= guest_code[delta+2]; v <<= 8; |
| 382 | v |= guest_code[delta+1]; v <<= 8; |
| 383 | v |= guest_code[delta+0]; |
| 384 | return v; |
| 385 | } |
| 386 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 387 | static UInt getUDisp ( Int size, Int delta ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 388 | { |
| 389 | switch (size) { |
| 390 | case 4: return getUDisp32(delta); |
| 391 | case 2: return getUDisp16(delta); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 392 | case 1: return (UInt)getUChar(delta); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 393 | default: vpanic("getUDisp(x86)"); |
| 394 | } |
| 395 | return 0; /*notreached*/ |
| 396 | } |
| 397 | |
| 398 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 399 | /* Get a byte value out of the insn stream and sign-extend to 32 |
| 400 | bits. */ |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 401 | static UInt getSDisp8 ( Int delta ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 402 | { |
| 403 | return extend_s_8to32( (UInt) (guest_code[delta]) ); |
| 404 | } |
| 405 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 406 | static UInt getSDisp16 ( Int delta0 ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 407 | { |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 408 | const UChar* eip = &guest_code[delta0]; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 409 | UInt d = *eip++; |
| 410 | d |= ((*eip++) << 8); |
| 411 | return extend_s_16to32(d); |
| 412 | } |
| 413 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 414 | static UInt getSDisp ( Int size, Int delta ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 415 | { |
| 416 | switch (size) { |
| 417 | case 4: return getUDisp32(delta); |
| 418 | case 2: return getSDisp16(delta); |
| 419 | case 1: return getSDisp8(delta); |
| 420 | default: vpanic("getSDisp(x86)"); |
| 421 | } |
| 422 | return 0; /*notreached*/ |
| 423 | } |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 424 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 425 | |
| 426 | /*------------------------------------------------------------*/ |
| 427 | /*--- Helpers for constructing IR. ---*/ |
| 428 | /*------------------------------------------------------------*/ |
| 429 | |
| 430 | /* Create a 1/2/4 byte read of an x86 integer registers. For 16/8 bit |
| 431 | register references, we need to take the host endianness into |
| 432 | account. Supplied value is 0 .. 7 and in the Intel instruction |
| 433 | encoding. */ |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 434 | |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 435 | static IRType szToITy ( Int n ) |
| 436 | { |
| 437 | switch (n) { |
| 438 | case 1: return Ity_I8; |
| 439 | case 2: return Ity_I16; |
| 440 | case 4: return Ity_I32; |
| 441 | default: vpanic("szToITy(x86)"); |
| 442 | } |
| 443 | } |
| 444 | |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 445 | /* On a little-endian host, less significant bits of the guest |
| 446 | registers are at lower addresses. Therefore, if a reference to a |
| 447 | register low half has the safe guest state offset as a reference to |
| 448 | the full register. |
| 449 | */ |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 450 | static Int integerGuestRegOffset ( Int sz, UInt archreg ) |
| 451 | { |
| 452 | vassert(archreg < 8); |
| 453 | |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 454 | /* Correct for little-endian host only. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 455 | vassert(host_endness == VexEndnessLE); |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 456 | |
| 457 | if (sz == 4 || sz == 2 || (sz == 1 && archreg < 4)) { |
| 458 | switch (archreg) { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 459 | case R_EAX: return OFFB_EAX; |
| 460 | case R_EBX: return OFFB_EBX; |
| 461 | case R_ECX: return OFFB_ECX; |
| 462 | case R_EDX: return OFFB_EDX; |
| 463 | case R_ESI: return OFFB_ESI; |
| 464 | case R_EDI: return OFFB_EDI; |
| 465 | case R_ESP: return OFFB_ESP; |
| 466 | case R_EBP: return OFFB_EBP; |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 467 | default: vpanic("integerGuestRegOffset(x86,le)(4,2)"); |
| 468 | } |
| 469 | } |
| 470 | |
| 471 | vassert(archreg >= 4 && archreg < 8 && sz == 1); |
| 472 | switch (archreg-4) { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 473 | case R_EAX: return 1+ OFFB_EAX; |
| 474 | case R_EBX: return 1+ OFFB_EBX; |
| 475 | case R_ECX: return 1+ OFFB_ECX; |
| 476 | case R_EDX: return 1+ OFFB_EDX; |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 477 | default: vpanic("integerGuestRegOffset(x86,le)(1h)"); |
| 478 | } |
| 479 | |
| 480 | /* NOTREACHED */ |
| 481 | vpanic("integerGuestRegOffset(x86,le)"); |
| 482 | } |
| 483 | |
| 484 | static Int segmentGuestRegOffset ( UInt sreg ) |
| 485 | { |
| 486 | switch (sreg) { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 487 | case R_ES: return OFFB_ES; |
| 488 | case R_CS: return OFFB_CS; |
| 489 | case R_SS: return OFFB_SS; |
| 490 | case R_DS: return OFFB_DS; |
| 491 | case R_FS: return OFFB_FS; |
| 492 | case R_GS: return OFFB_GS; |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 493 | default: vpanic("segmentGuestRegOffset(x86)"); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 494 | } |
| 495 | } |
| 496 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 497 | static Int xmmGuestRegOffset ( UInt xmmreg ) |
| 498 | { |
| 499 | switch (xmmreg) { |
| 500 | case 0: return OFFB_XMM0; |
| 501 | case 1: return OFFB_XMM1; |
| 502 | case 2: return OFFB_XMM2; |
| 503 | case 3: return OFFB_XMM3; |
| 504 | case 4: return OFFB_XMM4; |
| 505 | case 5: return OFFB_XMM5; |
| 506 | case 6: return OFFB_XMM6; |
| 507 | case 7: return OFFB_XMM7; |
| 508 | default: vpanic("xmmGuestRegOffset"); |
| 509 | } |
| 510 | } |
| 511 | |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 512 | /* Lanes of vector registers are always numbered from zero being the |
| 513 | least significant lane (rightmost in the register). */ |
| 514 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 515 | static Int xmmGuestRegLane16offset ( UInt xmmreg, Int laneno ) |
| 516 | { |
| 517 | /* Correct for little-endian host only. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 518 | vassert(host_endness == VexEndnessLE); |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 519 | vassert(laneno >= 0 && laneno < 8); |
| 520 | return xmmGuestRegOffset( xmmreg ) + 2 * laneno; |
| 521 | } |
| 522 | |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 523 | static Int xmmGuestRegLane32offset ( UInt xmmreg, Int laneno ) |
| 524 | { |
| 525 | /* Correct for little-endian host only. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 526 | vassert(host_endness == VexEndnessLE); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 527 | vassert(laneno >= 0 && laneno < 4); |
| 528 | return xmmGuestRegOffset( xmmreg ) + 4 * laneno; |
| 529 | } |
| 530 | |
| 531 | static Int xmmGuestRegLane64offset ( UInt xmmreg, Int laneno ) |
| 532 | { |
| 533 | /* Correct for little-endian host only. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 534 | vassert(host_endness == VexEndnessLE); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 535 | vassert(laneno >= 0 && laneno < 2); |
| 536 | return xmmGuestRegOffset( xmmreg ) + 8 * laneno; |
| 537 | } |
| 538 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 539 | static IRExpr* getIReg ( Int sz, UInt archreg ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 540 | { |
| 541 | vassert(sz == 1 || sz == 2 || sz == 4); |
| 542 | vassert(archreg < 8); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 543 | return IRExpr_Get( integerGuestRegOffset(sz,archreg), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 544 | szToITy(sz) ); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 545 | } |
| 546 | |
| 547 | /* Ditto, but write to a reg instead. */ |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 548 | static void putIReg ( Int sz, UInt archreg, IRExpr* e ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 549 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 550 | IRType ty = typeOfIRExpr(irsb->tyenv, e); |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 551 | switch (sz) { |
| 552 | case 1: vassert(ty == Ity_I8); break; |
| 553 | case 2: vassert(ty == Ity_I16); break; |
| 554 | case 4: vassert(ty == Ity_I32); break; |
| 555 | default: vpanic("putIReg(x86)"); |
| 556 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 557 | vassert(archreg < 8); |
sewardj | eeb9ef8 | 2004-07-15 12:39:03 +0000 | [diff] [blame] | 558 | stmt( IRStmt_Put(integerGuestRegOffset(sz,archreg), e) ); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 559 | } |
| 560 | |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 561 | static IRExpr* getSReg ( UInt sreg ) |
| 562 | { |
| 563 | return IRExpr_Get( segmentGuestRegOffset(sreg), Ity_I16 ); |
| 564 | } |
| 565 | |
| 566 | static void putSReg ( UInt sreg, IRExpr* e ) |
| 567 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 568 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I16); |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 569 | stmt( IRStmt_Put( segmentGuestRegOffset(sreg), e ) ); |
| 570 | } |
| 571 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 572 | static IRExpr* getXMMReg ( UInt xmmreg ) |
| 573 | { |
| 574 | return IRExpr_Get( xmmGuestRegOffset(xmmreg), Ity_V128 ); |
| 575 | } |
| 576 | |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 577 | static IRExpr* getXMMRegLane64 ( UInt xmmreg, Int laneno ) |
| 578 | { |
| 579 | return IRExpr_Get( xmmGuestRegLane64offset(xmmreg,laneno), Ity_I64 ); |
| 580 | } |
| 581 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 582 | static IRExpr* getXMMRegLane64F ( UInt xmmreg, Int laneno ) |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 583 | { |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 584 | return IRExpr_Get( xmmGuestRegLane64offset(xmmreg,laneno), Ity_F64 ); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 585 | } |
| 586 | |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 587 | static IRExpr* getXMMRegLane32 ( UInt xmmreg, Int laneno ) |
| 588 | { |
| 589 | return IRExpr_Get( xmmGuestRegLane32offset(xmmreg,laneno), Ity_I32 ); |
| 590 | } |
| 591 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 592 | static IRExpr* getXMMRegLane32F ( UInt xmmreg, Int laneno ) |
| 593 | { |
| 594 | return IRExpr_Get( xmmGuestRegLane32offset(xmmreg,laneno), Ity_F32 ); |
| 595 | } |
| 596 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 597 | static void putXMMReg ( UInt xmmreg, IRExpr* e ) |
| 598 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 599 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_V128); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 600 | stmt( IRStmt_Put( xmmGuestRegOffset(xmmreg), e ) ); |
| 601 | } |
| 602 | |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 603 | static void putXMMRegLane64 ( UInt xmmreg, Int laneno, IRExpr* e ) |
| 604 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 605 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I64); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 606 | stmt( IRStmt_Put( xmmGuestRegLane64offset(xmmreg,laneno), e ) ); |
| 607 | } |
| 608 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 609 | static void putXMMRegLane64F ( UInt xmmreg, Int laneno, IRExpr* e ) |
| 610 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 611 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_F64); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 612 | stmt( IRStmt_Put( xmmGuestRegLane64offset(xmmreg,laneno), e ) ); |
| 613 | } |
| 614 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 615 | static void putXMMRegLane32F ( UInt xmmreg, Int laneno, IRExpr* e ) |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 616 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 617 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_F32); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 618 | stmt( IRStmt_Put( xmmGuestRegLane32offset(xmmreg,laneno), e ) ); |
| 619 | } |
| 620 | |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 621 | static void putXMMRegLane32 ( UInt xmmreg, Int laneno, IRExpr* e ) |
| 622 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 623 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I32); |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 624 | stmt( IRStmt_Put( xmmGuestRegLane32offset(xmmreg,laneno), e ) ); |
| 625 | } |
| 626 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 627 | static void putXMMRegLane16 ( UInt xmmreg, Int laneno, IRExpr* e ) |
| 628 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 629 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I16); |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 630 | stmt( IRStmt_Put( xmmGuestRegLane16offset(xmmreg,laneno), e ) ); |
| 631 | } |
| 632 | |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 633 | static void assign ( IRTemp dst, IRExpr* e ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 634 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 635 | stmt( IRStmt_WrTmp(dst, e) ); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 636 | } |
| 637 | |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 638 | static void storeLE ( IRExpr* addr, IRExpr* data ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 639 | { |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 640 | stmt( IRStmt_Store(Iend_LE, addr, data) ); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 641 | } |
| 642 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 643 | static IRExpr* unop ( IROp op, IRExpr* a ) |
| 644 | { |
| 645 | return IRExpr_Unop(op, a); |
| 646 | } |
| 647 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 648 | static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) |
| 649 | { |
| 650 | return IRExpr_Binop(op, a1, a2); |
| 651 | } |
| 652 | |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 653 | static IRExpr* triop ( IROp op, IRExpr* a1, IRExpr* a2, IRExpr* a3 ) |
| 654 | { |
| 655 | return IRExpr_Triop(op, a1, a2, a3); |
| 656 | } |
| 657 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 658 | static IRExpr* mkexpr ( IRTemp tmp ) |
| 659 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 660 | return IRExpr_RdTmp(tmp); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 661 | } |
| 662 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 663 | static IRExpr* mkU8 ( UInt i ) |
| 664 | { |
| 665 | vassert(i < 256); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 666 | return IRExpr_Const(IRConst_U8( (UChar)i )); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 667 | } |
| 668 | |
| 669 | static IRExpr* mkU16 ( UInt i ) |
| 670 | { |
| 671 | vassert(i < 65536); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 672 | return IRExpr_Const(IRConst_U16( (UShort)i )); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 673 | } |
| 674 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 675 | static IRExpr* mkU32 ( UInt i ) |
| 676 | { |
| 677 | return IRExpr_Const(IRConst_U32(i)); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 678 | } |
| 679 | |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 680 | static IRExpr* mkU64 ( ULong i ) |
| 681 | { |
| 682 | return IRExpr_Const(IRConst_U64(i)); |
| 683 | } |
| 684 | |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 685 | static IRExpr* mkU ( IRType ty, UInt i ) |
| 686 | { |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 687 | if (ty == Ity_I8) return mkU8(i); |
| 688 | if (ty == Ity_I16) return mkU16(i); |
| 689 | if (ty == Ity_I32) return mkU32(i); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 690 | /* If this panics, it usually means you passed a size (1,2,4) |
| 691 | value as the IRType, rather than a real IRType. */ |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 692 | vpanic("mkU(x86)"); |
| 693 | } |
| 694 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 695 | static IRExpr* mkV128 ( UShort mask ) |
| 696 | { |
| 697 | return IRExpr_Const(IRConst_V128(mask)); |
| 698 | } |
| 699 | |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 700 | static IRExpr* loadLE ( IRType ty, IRExpr* addr ) |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 701 | { |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 702 | return IRExpr_Load(Iend_LE, ty, addr); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 703 | } |
| 704 | |
| 705 | static IROp mkSizedOp ( IRType ty, IROp op8 ) |
| 706 | { |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 707 | Int adj; |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 708 | vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); |
| 709 | vassert(op8 == Iop_Add8 || op8 == Iop_Sub8 |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 710 | || op8 == Iop_Mul8 |
| 711 | || op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 712 | || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 713 | || op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 714 | || op8 == Iop_CasCmpNE8 |
sewardj | e13074c | 2012-11-08 10:57:08 +0000 | [diff] [blame] | 715 | || op8 == Iop_ExpCmpNE8 |
sewardj | eb17e49 | 2007-08-25 23:07:44 +0000 | [diff] [blame] | 716 | || op8 == Iop_Not8); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 717 | adj = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); |
| 718 | return adj + op8; |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 719 | } |
| 720 | |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 721 | static IROp mkWidenOp ( Int szSmall, Int szBig, Bool signd ) |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 722 | { |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 723 | if (szSmall == 1 && szBig == 4) { |
| 724 | return signd ? Iop_8Sto32 : Iop_8Uto32; |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 725 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 726 | if (szSmall == 1 && szBig == 2) { |
| 727 | return signd ? Iop_8Sto16 : Iop_8Uto16; |
| 728 | } |
| 729 | if (szSmall == 2 && szBig == 4) { |
| 730 | return signd ? Iop_16Sto32 : Iop_16Uto32; |
| 731 | } |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 732 | vpanic("mkWidenOp(x86,guest)"); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 733 | } |
| 734 | |
sewardj | baa6608 | 2005-08-23 17:29:27 +0000 | [diff] [blame] | 735 | static IRExpr* mkAnd1 ( IRExpr* x, IRExpr* y ) |
| 736 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 737 | vassert(typeOfIRExpr(irsb->tyenv,x) == Ity_I1); |
| 738 | vassert(typeOfIRExpr(irsb->tyenv,y) == Ity_I1); |
sewardj | baa6608 | 2005-08-23 17:29:27 +0000 | [diff] [blame] | 739 | return unop(Iop_32to1, |
| 740 | binop(Iop_And32, |
| 741 | unop(Iop_1Uto32,x), |
| 742 | unop(Iop_1Uto32,y))); |
| 743 | } |
| 744 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 745 | /* Generate a compare-and-swap operation, operating on memory at |
| 746 | 'addr'. The expected value is 'expVal' and the new value is |
| 747 | 'newVal'. If the operation fails, then transfer control (with a |
| 748 | no-redir jump (XXX no -- see comment at top of this file)) to |
| 749 | 'restart_point', which is presumably the address of the guest |
| 750 | instruction again -- retrying, essentially. */ |
| 751 | static void casLE ( IRExpr* addr, IRExpr* expVal, IRExpr* newVal, |
| 752 | Addr32 restart_point ) |
| 753 | { |
| 754 | IRCAS* cas; |
| 755 | IRType tyE = typeOfIRExpr(irsb->tyenv, expVal); |
| 756 | IRType tyN = typeOfIRExpr(irsb->tyenv, newVal); |
| 757 | IRTemp oldTmp = newTemp(tyE); |
| 758 | IRTemp expTmp = newTemp(tyE); |
| 759 | vassert(tyE == tyN); |
| 760 | vassert(tyE == Ity_I32 || tyE == Ity_I16 || tyE == Ity_I8); |
| 761 | assign(expTmp, expVal); |
| 762 | cas = mkIRCAS( IRTemp_INVALID, oldTmp, Iend_LE, addr, |
| 763 | NULL, mkexpr(expTmp), NULL, newVal ); |
| 764 | stmt( IRStmt_CAS(cas) ); |
| 765 | stmt( IRStmt_Exit( |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 766 | binop( mkSizedOp(tyE,Iop_CasCmpNE8), |
| 767 | mkexpr(oldTmp), mkexpr(expTmp) ), |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 768 | Ijk_Boring, /*Ijk_NoRedir*/ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 769 | IRConst_U32( restart_point ), |
| 770 | OFFB_EIP |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 771 | )); |
| 772 | } |
| 773 | |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 774 | |
| 775 | /*------------------------------------------------------------*/ |
| 776 | /*--- Helpers for %eflags. ---*/ |
| 777 | /*------------------------------------------------------------*/ |
| 778 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 779 | /* -------------- Evaluating the flags-thunk. -------------- */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 780 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 781 | /* Build IR to calculate all the eflags from stored |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 782 | CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: |
| 783 | Ity_I32. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 784 | static IRExpr* mk_x86g_calculate_eflags_all ( void ) |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 785 | { |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 786 | IRExpr** args |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 787 | = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32), |
| 788 | IRExpr_Get(OFFB_CC_DEP1, Ity_I32), |
| 789 | IRExpr_Get(OFFB_CC_DEP2, Ity_I32), |
| 790 | IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 791 | IRExpr* call |
| 792 | = mkIRExprCCall( |
| 793 | Ity_I32, |
| 794 | 0/*regparm*/, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 795 | "x86g_calculate_eflags_all", &x86g_calculate_eflags_all, |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 796 | args |
| 797 | ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 798 | /* Exclude OP and NDEP from definedness checking. We're only |
| 799 | interested in DEP1 and DEP2. */ |
| 800 | call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 801 | return call; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 802 | } |
| 803 | |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 804 | /* Build IR to calculate some particular condition from stored |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 805 | CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: |
| 806 | Ity_Bit. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 807 | static IRExpr* mk_x86g_calculate_condition ( X86Condcode cond ) |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 808 | { |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 809 | IRExpr** args |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 810 | = mkIRExprVec_5( mkU32(cond), |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 811 | IRExpr_Get(OFFB_CC_OP, Ity_I32), |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 812 | IRExpr_Get(OFFB_CC_DEP1, Ity_I32), |
| 813 | IRExpr_Get(OFFB_CC_DEP2, Ity_I32), |
| 814 | IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 815 | IRExpr* call |
| 816 | = mkIRExprCCall( |
| 817 | Ity_I32, |
| 818 | 0/*regparm*/, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 819 | "x86g_calculate_condition", &x86g_calculate_condition, |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 820 | args |
| 821 | ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 822 | /* Exclude the requested condition, OP and NDEP from definedness |
| 823 | checking. We're only interested in DEP1 and DEP2. */ |
| 824 | call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<1) | (1<<4); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 825 | return unop(Iop_32to1, call); |
| 826 | } |
| 827 | |
| 828 | /* Build IR to calculate just the carry flag from stored |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 829 | CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: Ity_I32. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 830 | static IRExpr* mk_x86g_calculate_eflags_c ( void ) |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 831 | { |
| 832 | IRExpr** args |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 833 | = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32), |
| 834 | IRExpr_Get(OFFB_CC_DEP1, Ity_I32), |
| 835 | IRExpr_Get(OFFB_CC_DEP2, Ity_I32), |
| 836 | IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 837 | IRExpr* call |
| 838 | = mkIRExprCCall( |
| 839 | Ity_I32, |
sewardj | 893a330 | 2005-01-24 10:49:02 +0000 | [diff] [blame] | 840 | 3/*regparm*/, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 841 | "x86g_calculate_eflags_c", &x86g_calculate_eflags_c, |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 842 | args |
| 843 | ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 844 | /* Exclude OP and NDEP from definedness checking. We're only |
| 845 | interested in DEP1 and DEP2. */ |
| 846 | call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 847 | return call; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 848 | } |
| 849 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 850 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 851 | /* -------------- Building the flags-thunk. -------------- */ |
| 852 | |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 853 | /* The machinery in this section builds the flag-thunk following a |
| 854 | flag-setting operation. Hence the various setFlags_* functions. |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 855 | */ |
| 856 | |
| 857 | static Bool isAddSub ( IROp op8 ) |
| 858 | { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 859 | return toBool(op8 == Iop_Add8 || op8 == Iop_Sub8); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 860 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 861 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 862 | static Bool isLogic ( IROp op8 ) |
| 863 | { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 864 | return toBool(op8 == Iop_And8 || op8 == Iop_Or8 || op8 == Iop_Xor8); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 865 | } |
| 866 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 867 | /* U-widen 8/16/32 bit int expr to 32. */ |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 868 | static IRExpr* widenUto32 ( IRExpr* e ) |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 869 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 870 | switch (typeOfIRExpr(irsb->tyenv,e)) { |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 871 | case Ity_I32: return e; |
| 872 | case Ity_I16: return unop(Iop_16Uto32,e); |
| 873 | case Ity_I8: return unop(Iop_8Uto32,e); |
| 874 | default: vpanic("widenUto32"); |
| 875 | } |
| 876 | } |
| 877 | |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 878 | /* S-widen 8/16/32 bit int expr to 32. */ |
| 879 | static IRExpr* widenSto32 ( IRExpr* e ) |
| 880 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 881 | switch (typeOfIRExpr(irsb->tyenv,e)) { |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 882 | case Ity_I32: return e; |
| 883 | case Ity_I16: return unop(Iop_16Sto32,e); |
| 884 | case Ity_I8: return unop(Iop_8Sto32,e); |
| 885 | default: vpanic("widenSto32"); |
| 886 | } |
| 887 | } |
| 888 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 889 | /* Narrow 8/16/32 bit int expr to 8/16/32. Clearly only some |
| 890 | of these combinations make sense. */ |
| 891 | static IRExpr* narrowTo ( IRType dst_ty, IRExpr* e ) |
| 892 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 893 | IRType src_ty = typeOfIRExpr(irsb->tyenv,e); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 894 | if (src_ty == dst_ty) |
| 895 | return e; |
| 896 | if (src_ty == Ity_I32 && dst_ty == Ity_I16) |
| 897 | return unop(Iop_32to16, e); |
| 898 | if (src_ty == Ity_I32 && dst_ty == Ity_I8) |
| 899 | return unop(Iop_32to8, e); |
| 900 | |
| 901 | vex_printf("\nsrc, dst tys are: "); |
| 902 | ppIRType(src_ty); |
| 903 | vex_printf(", "); |
| 904 | ppIRType(dst_ty); |
| 905 | vex_printf("\n"); |
| 906 | vpanic("narrowTo(x86)"); |
| 907 | } |
| 908 | |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 909 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 910 | /* Set the flags thunk OP, DEP1 and DEP2 fields. The supplied op is |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 911 | auto-sized up to the real op. */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 912 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 913 | static |
| 914 | void setFlags_DEP1_DEP2 ( IROp op8, IRTemp dep1, IRTemp dep2, IRType ty ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 915 | { |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 916 | Int ccOp = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); |
| 917 | |
| 918 | vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); |
| 919 | |
| 920 | switch (op8) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 921 | case Iop_Add8: ccOp += X86G_CC_OP_ADDB; break; |
| 922 | case Iop_Sub8: ccOp += X86G_CC_OP_SUBB; break; |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 923 | default: ppIROp(op8); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 924 | vpanic("setFlags_DEP1_DEP2(x86)"); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 925 | } |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 926 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(ccOp)) ); |
| 927 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(dep1))) ); |
| 928 | stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(mkexpr(dep2))) ); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 929 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 930 | elimination of previous stores to this field work better. */ |
| 931 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 932 | } |
| 933 | |
| 934 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 935 | /* Set the OP and DEP1 fields only, and write zero to DEP2. */ |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 936 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 937 | static |
| 938 | void setFlags_DEP1 ( IROp op8, IRTemp dep1, IRType ty ) |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 939 | { |
| 940 | Int ccOp = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 941 | |
| 942 | vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); |
| 943 | |
| 944 | switch (op8) { |
| 945 | case Iop_Or8: |
| 946 | case Iop_And8: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 947 | case Iop_Xor8: ccOp += X86G_CC_OP_LOGICB; break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 948 | default: ppIROp(op8); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 949 | vpanic("setFlags_DEP1(x86)"); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 950 | } |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 951 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(ccOp)) ); |
| 952 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(dep1))) ); |
| 953 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0)) ); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 954 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 955 | elimination of previous stores to this field work better. */ |
| 956 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 957 | } |
| 958 | |
| 959 | |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 960 | /* For shift operations, we put in the result and the undershifted |
| 961 | result. Except if the shift amount is zero, the thunk is left |
| 962 | unchanged. */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 963 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 964 | static void setFlags_DEP1_DEP2_shift ( IROp op32, |
| 965 | IRTemp res, |
| 966 | IRTemp resUS, |
| 967 | IRType ty, |
| 968 | IRTemp guard ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 969 | { |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 970 | Int ccOp = ty==Ity_I8 ? 2 : (ty==Ity_I16 ? 1 : 0); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 971 | |
| 972 | vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); |
| 973 | vassert(guard); |
| 974 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 975 | /* Both kinds of right shifts are handled by the same thunk |
| 976 | operation. */ |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 977 | switch (op32) { |
| 978 | case Iop_Shr32: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 979 | case Iop_Sar32: ccOp = X86G_CC_OP_SHRL - ccOp; break; |
| 980 | case Iop_Shl32: ccOp = X86G_CC_OP_SHLL - ccOp; break; |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 981 | default: ppIROp(op32); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 982 | vpanic("setFlags_DEP1_DEP2_shift(x86)"); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 983 | } |
| 984 | |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 985 | /* guard :: Ity_I8. We need to convert it to I1. */ |
| 986 | IRTemp guardB = newTemp(Ity_I1); |
| 987 | assign( guardB, binop(Iop_CmpNE8, mkexpr(guard), mkU8(0)) ); |
| 988 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 989 | /* DEP1 contains the result, DEP2 contains the undershifted value. */ |
sewardj | eeb9ef8 | 2004-07-15 12:39:03 +0000 | [diff] [blame] | 990 | stmt( IRStmt_Put( OFFB_CC_OP, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 991 | IRExpr_ITE( mkexpr(guardB), |
| 992 | mkU32(ccOp), |
| 993 | IRExpr_Get(OFFB_CC_OP,Ity_I32) ) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 994 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 995 | IRExpr_ITE( mkexpr(guardB), |
| 996 | widenUto32(mkexpr(res)), |
| 997 | IRExpr_Get(OFFB_CC_DEP1,Ity_I32) ) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 998 | stmt( IRStmt_Put( OFFB_CC_DEP2, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 999 | IRExpr_ITE( mkexpr(guardB), |
| 1000 | widenUto32(mkexpr(resUS)), |
| 1001 | IRExpr_Get(OFFB_CC_DEP2,Ity_I32) ) )); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 1002 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 1003 | elimination of previous stores to this field work better. */ |
sewardj | 17b0e21 | 2011-03-26 07:28:51 +0000 | [diff] [blame] | 1004 | stmt( IRStmt_Put( OFFB_CC_NDEP, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 1005 | IRExpr_ITE( mkexpr(guardB), |
| 1006 | mkU32(0), |
| 1007 | IRExpr_Get(OFFB_CC_NDEP,Ity_I32) ) )); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1008 | } |
| 1009 | |
| 1010 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1011 | /* For the inc/dec case, we store in DEP1 the result value and in NDEP |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 1012 | the former value of the carry flag, which unfortunately we have to |
| 1013 | compute. */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1014 | |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 1015 | static void setFlags_INC_DEC ( Bool inc, IRTemp res, IRType ty ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1016 | { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1017 | Int ccOp = inc ? X86G_CC_OP_INCB : X86G_CC_OP_DECB; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1018 | |
| 1019 | ccOp += ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); |
| 1020 | vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); |
| 1021 | |
| 1022 | /* This has to come first, because calculating the C flag |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1023 | may require reading all four thunk fields. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1024 | stmt( IRStmt_Put( OFFB_CC_NDEP, mk_x86g_calculate_eflags_c()) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1025 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(ccOp)) ); |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 1026 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(res))) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1027 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0)) ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1028 | } |
| 1029 | |
| 1030 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1031 | /* Multiplies are pretty much like add and sub: DEP1 and DEP2 hold the |
| 1032 | two arguments. */ |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 1033 | |
| 1034 | static |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1035 | void setFlags_MUL ( IRType ty, IRTemp arg1, IRTemp arg2, UInt base_op ) |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 1036 | { |
| 1037 | switch (ty) { |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1038 | case Ity_I8: |
| 1039 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(base_op+0) ) ); |
| 1040 | break; |
| 1041 | case Ity_I16: |
| 1042 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(base_op+1) ) ); |
| 1043 | break; |
| 1044 | case Ity_I32: |
| 1045 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(base_op+2) ) ); |
| 1046 | break; |
| 1047 | default: |
| 1048 | vpanic("setFlags_MUL(x86)"); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 1049 | } |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1050 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(arg1)) )); |
| 1051 | stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(mkexpr(arg2)) )); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 1052 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 1053 | elimination of previous stores to this field work better. */ |
| 1054 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 1055 | } |
| 1056 | |
| 1057 | |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1058 | /* -------------- Condition codes. -------------- */ |
| 1059 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1060 | /* Condition codes, using the Intel encoding. */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1061 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1062 | static const HChar* name_X86Condcode ( X86Condcode cond ) |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1063 | { |
| 1064 | switch (cond) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1065 | case X86CondO: return "o"; |
| 1066 | case X86CondNO: return "no"; |
| 1067 | case X86CondB: return "b"; |
| 1068 | case X86CondNB: return "nb"; |
| 1069 | case X86CondZ: return "z"; |
| 1070 | case X86CondNZ: return "nz"; |
| 1071 | case X86CondBE: return "be"; |
| 1072 | case X86CondNBE: return "nbe"; |
| 1073 | case X86CondS: return "s"; |
| 1074 | case X86CondNS: return "ns"; |
| 1075 | case X86CondP: return "p"; |
| 1076 | case X86CondNP: return "np"; |
| 1077 | case X86CondL: return "l"; |
| 1078 | case X86CondNL: return "nl"; |
| 1079 | case X86CondLE: return "le"; |
| 1080 | case X86CondNLE: return "nle"; |
| 1081 | case X86CondAlways: return "ALWAYS"; |
| 1082 | default: vpanic("name_X86Condcode"); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1083 | } |
| 1084 | } |
| 1085 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1086 | static |
| 1087 | X86Condcode positiveIse_X86Condcode ( X86Condcode cond, |
sewardj | dbf550c | 2005-01-24 11:54:11 +0000 | [diff] [blame] | 1088 | Bool* needInvert ) |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1089 | { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1090 | vassert(cond >= X86CondO && cond <= X86CondNLE); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1091 | if (cond & 1) { |
| 1092 | *needInvert = True; |
| 1093 | return cond-1; |
| 1094 | } else { |
| 1095 | *needInvert = False; |
| 1096 | return cond; |
| 1097 | } |
| 1098 | } |
| 1099 | |
| 1100 | |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1101 | /* -------------- Helpers for ADD/SUB with carry. -------------- */ |
| 1102 | |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 1103 | /* Given ta1, ta2 and tres, compute tres = ADC(ta1,ta2) and set flags |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1104 | appropriately. |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1105 | |
| 1106 | Optionally, generate a store for the 'tres' value. This can either |
| 1107 | be a normal store, or it can be a cas-with-possible-failure style |
| 1108 | store: |
| 1109 | |
| 1110 | if taddr is IRTemp_INVALID, then no store is generated. |
| 1111 | |
| 1112 | if taddr is not IRTemp_INVALID, then a store (using taddr as |
| 1113 | the address) is generated: |
| 1114 | |
| 1115 | if texpVal is IRTemp_INVALID then a normal store is |
| 1116 | generated, and restart_point must be zero (it is irrelevant). |
| 1117 | |
| 1118 | if texpVal is not IRTemp_INVALID then a cas-style store is |
| 1119 | generated. texpVal is the expected value, restart_point |
| 1120 | is the restart point if the store fails, and texpVal must |
| 1121 | have the same type as tres. |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1122 | */ |
| 1123 | static void helper_ADC ( Int sz, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1124 | IRTemp tres, IRTemp ta1, IRTemp ta2, |
| 1125 | /* info about optional store: */ |
| 1126 | IRTemp taddr, IRTemp texpVal, Addr32 restart_point ) |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1127 | { |
| 1128 | UInt thunkOp; |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1129 | IRType ty = szToITy(sz); |
| 1130 | IRTemp oldc = newTemp(Ity_I32); |
| 1131 | IRTemp oldcn = newTemp(ty); |
| 1132 | IROp plus = mkSizedOp(ty, Iop_Add8); |
| 1133 | IROp xor = mkSizedOp(ty, Iop_Xor8); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 1134 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1135 | vassert(typeOfIRTemp(irsb->tyenv, tres) == ty); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 1136 | vassert(sz == 1 || sz == 2 || sz == 4); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1137 | thunkOp = sz==4 ? X86G_CC_OP_ADCL |
| 1138 | : (sz==2 ? X86G_CC_OP_ADCW : X86G_CC_OP_ADCB); |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1139 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1140 | /* oldc = old carry flag, 0 or 1 */ |
| 1141 | assign( oldc, binop(Iop_And32, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1142 | mk_x86g_calculate_eflags_c(), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1143 | mkU32(1)) ); |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1144 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1145 | assign( oldcn, narrowTo(ty, mkexpr(oldc)) ); |
| 1146 | |
| 1147 | assign( tres, binop(plus, |
| 1148 | binop(plus,mkexpr(ta1),mkexpr(ta2)), |
| 1149 | mkexpr(oldcn)) ); |
| 1150 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1151 | /* Possibly generate a store of 'tres' to 'taddr'. See comment at |
| 1152 | start of this function. */ |
| 1153 | if (taddr != IRTemp_INVALID) { |
| 1154 | if (texpVal == IRTemp_INVALID) { |
| 1155 | vassert(restart_point == 0); |
| 1156 | storeLE( mkexpr(taddr), mkexpr(tres) ); |
| 1157 | } else { |
| 1158 | vassert(typeOfIRTemp(irsb->tyenv, texpVal) == ty); |
| 1159 | /* .. and hence 'texpVal' has the same type as 'tres'. */ |
| 1160 | casLE( mkexpr(taddr), |
| 1161 | mkexpr(texpVal), mkexpr(tres), restart_point ); |
| 1162 | } |
| 1163 | } |
| 1164 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1165 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(thunkOp) ) ); |
sewardj | 3b3eacd | 2005-08-24 10:01:36 +0000 | [diff] [blame] | 1166 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(ta1)) )); |
| 1167 | stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(binop(xor, mkexpr(ta2), |
| 1168 | mkexpr(oldcn)) )) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1169 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(oldc) ) ); |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 1170 | } |
| 1171 | |
| 1172 | |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 1173 | /* Given ta1, ta2 and tres, compute tres = SBB(ta1,ta2) and set flags |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1174 | appropriately. As with helper_ADC, possibly generate a store of |
| 1175 | the result -- see comments on helper_ADC for details. |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1176 | */ |
| 1177 | static void helper_SBB ( Int sz, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1178 | IRTemp tres, IRTemp ta1, IRTemp ta2, |
| 1179 | /* info about optional store: */ |
| 1180 | IRTemp taddr, IRTemp texpVal, Addr32 restart_point ) |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1181 | { |
| 1182 | UInt thunkOp; |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1183 | IRType ty = szToITy(sz); |
| 1184 | IRTemp oldc = newTemp(Ity_I32); |
| 1185 | IRTemp oldcn = newTemp(ty); |
| 1186 | IROp minus = mkSizedOp(ty, Iop_Sub8); |
| 1187 | IROp xor = mkSizedOp(ty, Iop_Xor8); |
| 1188 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1189 | vassert(typeOfIRTemp(irsb->tyenv, tres) == ty); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1190 | vassert(sz == 1 || sz == 2 || sz == 4); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1191 | thunkOp = sz==4 ? X86G_CC_OP_SBBL |
| 1192 | : (sz==2 ? X86G_CC_OP_SBBW : X86G_CC_OP_SBBB); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1193 | |
| 1194 | /* oldc = old carry flag, 0 or 1 */ |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 1195 | assign( oldc, binop(Iop_And32, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1196 | mk_x86g_calculate_eflags_c(), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1197 | mkU32(1)) ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1198 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1199 | assign( oldcn, narrowTo(ty, mkexpr(oldc)) ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 1200 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1201 | assign( tres, binop(minus, |
| 1202 | binop(minus,mkexpr(ta1),mkexpr(ta2)), |
| 1203 | mkexpr(oldcn)) ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1204 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1205 | /* Possibly generate a store of 'tres' to 'taddr'. See comment at |
| 1206 | start of this function. */ |
| 1207 | if (taddr != IRTemp_INVALID) { |
| 1208 | if (texpVal == IRTemp_INVALID) { |
| 1209 | vassert(restart_point == 0); |
| 1210 | storeLE( mkexpr(taddr), mkexpr(tres) ); |
| 1211 | } else { |
| 1212 | vassert(typeOfIRTemp(irsb->tyenv, texpVal) == ty); |
| 1213 | /* .. and hence 'texpVal' has the same type as 'tres'. */ |
| 1214 | casLE( mkexpr(taddr), |
| 1215 | mkexpr(texpVal), mkexpr(tres), restart_point ); |
| 1216 | } |
| 1217 | } |
| 1218 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1219 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(thunkOp) ) ); |
sewardj | 3b3eacd | 2005-08-24 10:01:36 +0000 | [diff] [blame] | 1220 | stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(ta1) )) ); |
| 1221 | stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(binop(xor, mkexpr(ta2), |
| 1222 | mkexpr(oldcn)) )) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1223 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(oldc) ) ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1224 | } |
| 1225 | |
| 1226 | |
sewardj | 7dd2eb2 | 2005-01-05 10:38:54 +0000 | [diff] [blame] | 1227 | /* -------------- Helpers for disassembly printing. -------------- */ |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 1228 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1229 | static const HChar* nameGrp1 ( Int opc_aux ) |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 1230 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1231 | static const HChar* grp1_names[8] |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 1232 | = { "add", "or", "adc", "sbb", "and", "sub", "xor", "cmp" }; |
| 1233 | if (opc_aux < 0 || opc_aux > 7) vpanic("nameGrp1(x86)"); |
| 1234 | return grp1_names[opc_aux]; |
| 1235 | } |
| 1236 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1237 | static const HChar* nameGrp2 ( Int opc_aux ) |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 1238 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1239 | static const HChar* grp2_names[8] |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 1240 | = { "rol", "ror", "rcl", "rcr", "shl", "shr", "shl", "sar" }; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 1241 | if (opc_aux < 0 || opc_aux > 7) vpanic("nameGrp2(x86)"); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 1242 | return grp2_names[opc_aux]; |
| 1243 | } |
| 1244 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1245 | static const HChar* nameGrp4 ( Int opc_aux ) |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 1246 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1247 | static const HChar* grp4_names[8] |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 1248 | = { "inc", "dec", "???", "???", "???", "???", "???", "???" }; |
| 1249 | if (opc_aux < 0 || opc_aux > 1) vpanic("nameGrp4(x86)"); |
| 1250 | return grp4_names[opc_aux]; |
| 1251 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1252 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1253 | static const HChar* nameGrp5 ( Int opc_aux ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1254 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1255 | static const HChar* grp5_names[8] |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 1256 | = { "inc", "dec", "call*", "call*", "jmp*", "jmp*", "push", "???" }; |
| 1257 | if (opc_aux < 0 || opc_aux > 6) vpanic("nameGrp5(x86)"); |
| 1258 | return grp5_names[opc_aux]; |
| 1259 | } |
| 1260 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1261 | static const HChar* nameGrp8 ( Int opc_aux ) |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 1262 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1263 | static const HChar* grp8_names[8] |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 1264 | = { "???", "???", "???", "???", "bt", "bts", "btr", "btc" }; |
| 1265 | if (opc_aux < 4 || opc_aux > 7) vpanic("nameGrp8(x86)"); |
| 1266 | return grp8_names[opc_aux]; |
| 1267 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1268 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1269 | static const HChar* nameIReg ( Int size, Int reg ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1270 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1271 | static const HChar* ireg32_names[8] |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1272 | = { "%eax", "%ecx", "%edx", "%ebx", |
| 1273 | "%esp", "%ebp", "%esi", "%edi" }; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1274 | static const HChar* ireg16_names[8] |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1275 | = { "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di" }; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1276 | static const HChar* ireg8_names[8] |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1277 | = { "%al", "%cl", "%dl", "%bl", |
| 1278 | "%ah{sp}", "%ch{bp}", "%dh{si}", "%bh{di}" }; |
| 1279 | if (reg < 0 || reg > 7) goto bad; |
| 1280 | switch (size) { |
| 1281 | case 4: return ireg32_names[reg]; |
| 1282 | case 2: return ireg16_names[reg]; |
| 1283 | case 1: return ireg8_names[reg]; |
| 1284 | } |
| 1285 | bad: |
| 1286 | vpanic("nameIReg(X86)"); |
| 1287 | return NULL; /*notreached*/ |
| 1288 | } |
| 1289 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1290 | static const HChar* nameSReg ( UInt sreg ) |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 1291 | { |
| 1292 | switch (sreg) { |
| 1293 | case R_ES: return "%es"; |
| 1294 | case R_CS: return "%cs"; |
| 1295 | case R_SS: return "%ss"; |
| 1296 | case R_DS: return "%ds"; |
| 1297 | case R_FS: return "%fs"; |
| 1298 | case R_GS: return "%gs"; |
| 1299 | default: vpanic("nameSReg(x86)"); |
| 1300 | } |
| 1301 | } |
| 1302 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1303 | static const HChar* nameMMXReg ( Int mmxreg ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 1304 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1305 | static const HChar* mmx_names[8] |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 1306 | = { "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" }; |
| 1307 | if (mmxreg < 0 || mmxreg > 7) vpanic("nameMMXReg(x86,guest)"); |
| 1308 | return mmx_names[mmxreg]; |
| 1309 | } |
| 1310 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1311 | static const HChar* nameXMMReg ( Int xmmreg ) |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1312 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1313 | static const HChar* xmm_names[8] |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1314 | = { "%xmm0", "%xmm1", "%xmm2", "%xmm3", |
| 1315 | "%xmm4", "%xmm5", "%xmm6", "%xmm7" }; |
| 1316 | if (xmmreg < 0 || xmmreg > 7) vpanic("name_of_xmm_reg"); |
| 1317 | return xmm_names[xmmreg]; |
| 1318 | } |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 1319 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1320 | static const HChar* nameMMXGran ( Int gran ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 1321 | { |
| 1322 | switch (gran) { |
| 1323 | case 0: return "b"; |
| 1324 | case 1: return "w"; |
| 1325 | case 2: return "d"; |
| 1326 | case 3: return "q"; |
| 1327 | default: vpanic("nameMMXGran(x86,guest)"); |
| 1328 | } |
| 1329 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1330 | |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1331 | static HChar nameISize ( Int size ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1332 | { |
| 1333 | switch (size) { |
| 1334 | case 4: return 'l'; |
| 1335 | case 2: return 'w'; |
| 1336 | case 1: return 'b'; |
| 1337 | default: vpanic("nameISize(x86)"); |
| 1338 | } |
| 1339 | } |
| 1340 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1341 | |
| 1342 | /*------------------------------------------------------------*/ |
| 1343 | /*--- JMP helpers ---*/ |
| 1344 | /*------------------------------------------------------------*/ |
| 1345 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1346 | static void jmp_lit( /*MOD*/DisResult* dres, |
| 1347 | IRJumpKind kind, Addr32 d32 ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1348 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1349 | vassert(dres->whatNext == Dis_Continue); |
| 1350 | vassert(dres->len == 0); |
| 1351 | vassert(dres->continueAt == 0); |
| 1352 | vassert(dres->jk_StopHere == Ijk_INVALID); |
| 1353 | dres->whatNext = Dis_StopHere; |
| 1354 | dres->jk_StopHere = kind; |
| 1355 | stmt( IRStmt_Put( OFFB_EIP, mkU32(d32) ) ); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1356 | } |
| 1357 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1358 | static void jmp_treg( /*MOD*/DisResult* dres, |
| 1359 | IRJumpKind kind, IRTemp t ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1360 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1361 | vassert(dres->whatNext == Dis_Continue); |
| 1362 | vassert(dres->len == 0); |
| 1363 | vassert(dres->continueAt == 0); |
| 1364 | vassert(dres->jk_StopHere == Ijk_INVALID); |
| 1365 | dres->whatNext = Dis_StopHere; |
| 1366 | dres->jk_StopHere = kind; |
| 1367 | stmt( IRStmt_Put( OFFB_EIP, mkexpr(t) ) ); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1368 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1369 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1370 | static |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1371 | void jcc_01( /*MOD*/DisResult* dres, |
| 1372 | X86Condcode cond, Addr32 d32_false, Addr32 d32_true ) |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1373 | { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1374 | Bool invert; |
| 1375 | X86Condcode condPos; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1376 | vassert(dres->whatNext == Dis_Continue); |
| 1377 | vassert(dres->len == 0); |
| 1378 | vassert(dres->continueAt == 0); |
| 1379 | vassert(dres->jk_StopHere == Ijk_INVALID); |
| 1380 | dres->whatNext = Dis_StopHere; |
| 1381 | dres->jk_StopHere = Ijk_Boring; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1382 | condPos = positiveIse_X86Condcode ( cond, &invert ); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1383 | if (invert) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1384 | stmt( IRStmt_Exit( mk_x86g_calculate_condition(condPos), |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1385 | Ijk_Boring, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1386 | IRConst_U32(d32_false), |
| 1387 | OFFB_EIP ) ); |
| 1388 | stmt( IRStmt_Put( OFFB_EIP, mkU32(d32_true) ) ); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1389 | } else { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1390 | stmt( IRStmt_Exit( mk_x86g_calculate_condition(condPos), |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1391 | Ijk_Boring, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1392 | IRConst_U32(d32_true), |
| 1393 | OFFB_EIP ) ); |
| 1394 | stmt( IRStmt_Put( OFFB_EIP, mkU32(d32_false) ) ); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1395 | } |
| 1396 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1397 | |
| 1398 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1399 | /*------------------------------------------------------------*/ |
| 1400 | /*--- Disassembling addressing modes ---*/ |
| 1401 | /*------------------------------------------------------------*/ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 1402 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1403 | static |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1404 | const HChar* sorbTxt ( UChar sorb ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1405 | { |
| 1406 | switch (sorb) { |
| 1407 | case 0: return ""; /* no override */ |
| 1408 | case 0x3E: return "%ds"; |
| 1409 | case 0x26: return "%es:"; |
| 1410 | case 0x64: return "%fs:"; |
| 1411 | case 0x65: return "%gs:"; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 1412 | default: vpanic("sorbTxt(x86,guest)"); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1413 | } |
| 1414 | } |
| 1415 | |
| 1416 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 1417 | /* 'virtual' is an IRExpr* holding a virtual address. Convert it to a |
| 1418 | linear address by adding any required segment override as indicated |
| 1419 | by sorb. */ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1420 | static |
| 1421 | IRExpr* handleSegOverride ( UChar sorb, IRExpr* virtual ) |
| 1422 | { |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1423 | Int sreg; |
| 1424 | IRType hWordTy; |
| 1425 | IRTemp ldt_ptr, gdt_ptr, seg_selector, r64; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1426 | |
| 1427 | if (sorb == 0) |
| 1428 | /* the common case - no override */ |
| 1429 | return virtual; |
| 1430 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1431 | switch (sorb) { |
| 1432 | case 0x3E: sreg = R_DS; break; |
| 1433 | case 0x26: sreg = R_ES; break; |
| 1434 | case 0x64: sreg = R_FS; break; |
| 1435 | case 0x65: sreg = R_GS; break; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 1436 | default: vpanic("handleSegOverride(x86,guest)"); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1437 | } |
| 1438 | |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1439 | hWordTy = sizeof(HWord)==4 ? Ity_I32 : Ity_I64; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1440 | |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1441 | seg_selector = newTemp(Ity_I32); |
| 1442 | ldt_ptr = newTemp(hWordTy); |
| 1443 | gdt_ptr = newTemp(hWordTy); |
| 1444 | r64 = newTemp(Ity_I64); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1445 | |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1446 | assign( seg_selector, unop(Iop_16Uto32, getSReg(sreg)) ); |
| 1447 | assign( ldt_ptr, IRExpr_Get( OFFB_LDT, hWordTy )); |
| 1448 | assign( gdt_ptr, IRExpr_Get( OFFB_GDT, hWordTy )); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 1449 | |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1450 | /* |
| 1451 | Call this to do the translation and limit checks: |
| 1452 | ULong x86g_use_seg_selector ( HWord ldt, HWord gdt, |
| 1453 | UInt seg_selector, UInt virtual_addr ) |
| 1454 | */ |
| 1455 | assign( |
| 1456 | r64, |
| 1457 | mkIRExprCCall( |
| 1458 | Ity_I64, |
| 1459 | 0/*regparms*/, |
| 1460 | "x86g_use_seg_selector", |
| 1461 | &x86g_use_seg_selector, |
| 1462 | mkIRExprVec_4( mkexpr(ldt_ptr), mkexpr(gdt_ptr), |
| 1463 | mkexpr(seg_selector), virtual) |
| 1464 | ) |
| 1465 | ); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 1466 | |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 1467 | /* If the high 32 of the result are non-zero, there was a |
| 1468 | failure in address translation. In which case, make a |
| 1469 | quick exit. |
| 1470 | */ |
| 1471 | stmt( |
| 1472 | IRStmt_Exit( |
| 1473 | binop(Iop_CmpNE32, unop(Iop_64HIto32, mkexpr(r64)), mkU32(0)), |
| 1474 | Ijk_MapFail, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1475 | IRConst_U32( guest_EIP_curr_instr ), |
| 1476 | OFFB_EIP |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 1477 | ) |
| 1478 | ); |
| 1479 | |
| 1480 | /* otherwise, here's the translated result. */ |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 1481 | return unop(Iop_64to32, mkexpr(r64)); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1482 | } |
| 1483 | |
| 1484 | |
| 1485 | /* Generate IR to calculate an address indicated by a ModRM and |
| 1486 | following SIB bytes. The expression, and the number of bytes in |
| 1487 | the address mode, are returned. Note that this fn should not be |
| 1488 | called if the R/M part of the address denotes a register instead of |
| 1489 | memory. If print_codegen is true, text of the addressing mode is |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1490 | placed in buf. |
| 1491 | |
| 1492 | The computed address is stored in a new tempreg, and the |
| 1493 | identity of the tempreg is returned. */ |
| 1494 | |
| 1495 | static IRTemp disAMode_copy2tmp ( IRExpr* addr32 ) |
| 1496 | { |
| 1497 | IRTemp tmp = newTemp(Ity_I32); |
| 1498 | assign( tmp, addr32 ); |
| 1499 | return tmp; |
| 1500 | } |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1501 | |
| 1502 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 1503 | IRTemp disAMode ( Int* len, UChar sorb, Int delta, HChar* buf ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1504 | { |
| 1505 | UChar mod_reg_rm = getIByte(delta); |
| 1506 | delta++; |
| 1507 | |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 1508 | buf[0] = (UChar)0; |
| 1509 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1510 | /* squeeze out the reg field from mod_reg_rm, since a 256-entry |
| 1511 | jump table seems a bit excessive. |
| 1512 | */ |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1513 | mod_reg_rm &= 0xC7; /* is now XX000YYY */ |
| 1514 | mod_reg_rm = toUChar(mod_reg_rm | (mod_reg_rm >> 3)); |
| 1515 | /* is now XX0XXYYY */ |
| 1516 | mod_reg_rm &= 0x1F; /* is now 000XXYYY */ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1517 | switch (mod_reg_rm) { |
| 1518 | |
| 1519 | /* (%eax) .. (%edi), not including (%esp) or (%ebp). |
| 1520 | --> GET %reg, t |
| 1521 | */ |
| 1522 | case 0x00: case 0x01: case 0x02: case 0x03: |
| 1523 | /* ! 04 */ /* ! 05 */ case 0x06: case 0x07: |
| 1524 | { UChar rm = mod_reg_rm; |
| 1525 | DIS(buf, "%s(%s)", sorbTxt(sorb), nameIReg(4,rm)); |
| 1526 | *len = 1; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1527 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1528 | handleSegOverride(sorb, getIReg(4,rm))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1529 | } |
| 1530 | |
| 1531 | /* d8(%eax) ... d8(%edi), not including d8(%esp) |
| 1532 | --> GET %reg, t ; ADDL d8, t |
| 1533 | */ |
| 1534 | case 0x08: case 0x09: case 0x0A: case 0x0B: |
| 1535 | /* ! 0C */ case 0x0D: case 0x0E: case 0x0F: |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1536 | { UChar rm = toUChar(mod_reg_rm & 7); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1537 | UInt d = getSDisp8(delta); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1538 | DIS(buf, "%s%d(%s)", sorbTxt(sorb), (Int)d, nameIReg(4,rm)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1539 | *len = 2; |
| 1540 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1541 | handleSegOverride(sorb, |
| 1542 | binop(Iop_Add32,getIReg(4,rm),mkU32(d)))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1543 | } |
| 1544 | |
| 1545 | /* d32(%eax) ... d32(%edi), not including d32(%esp) |
| 1546 | --> GET %reg, t ; ADDL d8, t |
| 1547 | */ |
| 1548 | case 0x10: case 0x11: case 0x12: case 0x13: |
| 1549 | /* ! 14 */ case 0x15: case 0x16: case 0x17: |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1550 | { UChar rm = toUChar(mod_reg_rm & 7); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1551 | UInt d = getUDisp32(delta); |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 1552 | DIS(buf, "%s0x%x(%s)", sorbTxt(sorb), d, nameIReg(4,rm)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1553 | *len = 5; |
| 1554 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1555 | handleSegOverride(sorb, |
| 1556 | binop(Iop_Add32,getIReg(4,rm),mkU32(d)))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1557 | } |
| 1558 | |
| 1559 | /* a register, %eax .. %edi. This shouldn't happen. */ |
| 1560 | case 0x18: case 0x19: case 0x1A: case 0x1B: |
| 1561 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: |
| 1562 | vpanic("disAMode(x86): not an addr!"); |
| 1563 | |
| 1564 | /* a 32-bit literal address |
| 1565 | --> MOV d32, tmp |
| 1566 | */ |
| 1567 | case 0x05: |
| 1568 | { UInt d = getUDisp32(delta); |
| 1569 | *len = 5; |
| 1570 | DIS(buf, "%s(0x%x)", sorbTxt(sorb), d); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1571 | return disAMode_copy2tmp( |
| 1572 | handleSegOverride(sorb, mkU32(d))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1573 | } |
| 1574 | |
| 1575 | case 0x04: { |
| 1576 | /* SIB, with no displacement. Special cases: |
| 1577 | -- %esp cannot act as an index value. |
| 1578 | If index_r indicates %esp, zero is used for the index. |
| 1579 | -- when mod is zero and base indicates EBP, base is instead |
| 1580 | a 32-bit literal. |
| 1581 | It's all madness, I tell you. Extract %index, %base and |
| 1582 | scale from the SIB byte. The value denoted is then: |
| 1583 | | %index == %ESP && %base == %EBP |
| 1584 | = d32 following SIB byte |
| 1585 | | %index == %ESP && %base != %EBP |
| 1586 | = %base |
| 1587 | | %index != %ESP && %base == %EBP |
| 1588 | = d32 following SIB byte + (%index << scale) |
| 1589 | | %index != %ESP && %base != %ESP |
| 1590 | = %base + (%index << scale) |
| 1591 | |
| 1592 | What happens to the souls of CPU architects who dream up such |
| 1593 | horrendous schemes, do you suppose? |
| 1594 | */ |
| 1595 | UChar sib = getIByte(delta); |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1596 | UChar scale = toUChar((sib >> 6) & 3); |
| 1597 | UChar index_r = toUChar((sib >> 3) & 7); |
| 1598 | UChar base_r = toUChar(sib & 7); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1599 | delta++; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1600 | |
| 1601 | if (index_r != R_ESP && base_r != R_EBP) { |
| 1602 | DIS(buf, "%s(%s,%s,%d)", sorbTxt(sorb), |
| 1603 | nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1604 | *len = 2; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1605 | return |
| 1606 | disAMode_copy2tmp( |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1607 | handleSegOverride(sorb, |
| 1608 | binop(Iop_Add32, |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1609 | getIReg(4,base_r), |
| 1610 | binop(Iop_Shl32, getIReg(4,index_r), |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 1611 | mkU8(scale))))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1612 | } |
| 1613 | |
| 1614 | if (index_r != R_ESP && base_r == R_EBP) { |
| 1615 | UInt d = getUDisp32(delta); |
| 1616 | DIS(buf, "%s0x%x(,%s,%d)", sorbTxt(sorb), d, |
| 1617 | nameIReg(4,index_r), 1<<scale); |
| 1618 | *len = 6; |
| 1619 | return |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1620 | disAMode_copy2tmp( |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1621 | handleSegOverride(sorb, |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1622 | binop(Iop_Add32, |
| 1623 | binop(Iop_Shl32, getIReg(4,index_r), mkU8(scale)), |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1624 | mkU32(d)))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1625 | } |
| 1626 | |
| 1627 | if (index_r == R_ESP && base_r != R_EBP) { |
| 1628 | DIS(buf, "%s(%s,,)", sorbTxt(sorb), nameIReg(4,base_r)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1629 | *len = 2; |
| 1630 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1631 | handleSegOverride(sorb, getIReg(4,base_r))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1632 | } |
| 1633 | |
| 1634 | if (index_r == R_ESP && base_r == R_EBP) { |
| 1635 | UInt d = getUDisp32(delta); |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 1636 | DIS(buf, "%s0x%x(,,)", sorbTxt(sorb), d); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1637 | *len = 6; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1638 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1639 | handleSegOverride(sorb, mkU32(d))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1640 | } |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 1641 | /*NOTREACHED*/ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1642 | vassert(0); |
| 1643 | } |
| 1644 | |
| 1645 | /* SIB, with 8-bit displacement. Special cases: |
| 1646 | -- %esp cannot act as an index value. |
| 1647 | If index_r indicates %esp, zero is used for the index. |
| 1648 | Denoted value is: |
| 1649 | | %index == %ESP |
| 1650 | = d8 + %base |
| 1651 | | %index != %ESP |
| 1652 | = d8 + %base + (%index << scale) |
| 1653 | */ |
| 1654 | case 0x0C: { |
| 1655 | UChar sib = getIByte(delta); |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1656 | UChar scale = toUChar((sib >> 6) & 3); |
| 1657 | UChar index_r = toUChar((sib >> 3) & 7); |
| 1658 | UChar base_r = toUChar(sib & 7); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1659 | UInt d = getSDisp8(delta+1); |
| 1660 | |
| 1661 | if (index_r == R_ESP) { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1662 | DIS(buf, "%s%d(%s,,)", sorbTxt(sorb), |
| 1663 | (Int)d, nameIReg(4,base_r)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1664 | *len = 3; |
| 1665 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1666 | handleSegOverride(sorb, |
| 1667 | binop(Iop_Add32, getIReg(4,base_r), mkU32(d)) )); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1668 | } else { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1669 | DIS(buf, "%s%d(%s,%s,%d)", sorbTxt(sorb), (Int)d, |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1670 | nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1671 | *len = 3; |
| 1672 | return |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1673 | disAMode_copy2tmp( |
| 1674 | handleSegOverride(sorb, |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 1675 | binop(Iop_Add32, |
| 1676 | binop(Iop_Add32, |
| 1677 | getIReg(4,base_r), |
| 1678 | binop(Iop_Shl32, |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 1679 | getIReg(4,index_r), mkU8(scale))), |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1680 | mkU32(d)))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1681 | } |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 1682 | /*NOTREACHED*/ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1683 | vassert(0); |
| 1684 | } |
| 1685 | |
| 1686 | /* SIB, with 32-bit displacement. Special cases: |
| 1687 | -- %esp cannot act as an index value. |
| 1688 | If index_r indicates %esp, zero is used for the index. |
| 1689 | Denoted value is: |
| 1690 | | %index == %ESP |
| 1691 | = d32 + %base |
| 1692 | | %index != %ESP |
| 1693 | = d32 + %base + (%index << scale) |
| 1694 | */ |
| 1695 | case 0x14: { |
| 1696 | UChar sib = getIByte(delta); |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1697 | UChar scale = toUChar((sib >> 6) & 3); |
| 1698 | UChar index_r = toUChar((sib >> 3) & 7); |
| 1699 | UChar base_r = toUChar(sib & 7); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1700 | UInt d = getUDisp32(delta+1); |
| 1701 | |
| 1702 | if (index_r == R_ESP) { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1703 | DIS(buf, "%s%d(%s,,)", sorbTxt(sorb), |
| 1704 | (Int)d, nameIReg(4,base_r)); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1705 | *len = 6; |
| 1706 | return disAMode_copy2tmp( |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1707 | handleSegOverride(sorb, |
| 1708 | binop(Iop_Add32, getIReg(4,base_r), mkU32(d)) )); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1709 | } else { |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 1710 | DIS(buf, "%s%d(%s,%s,%d)", sorbTxt(sorb), (Int)d, |
| 1711 | nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1712 | *len = 6; |
| 1713 | return |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1714 | disAMode_copy2tmp( |
| 1715 | handleSegOverride(sorb, |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1716 | binop(Iop_Add32, |
| 1717 | binop(Iop_Add32, |
| 1718 | getIReg(4,base_r), |
| 1719 | binop(Iop_Shl32, |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 1720 | getIReg(4,index_r), mkU8(scale))), |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1721 | mkU32(d)))); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1722 | } |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 1723 | /*NOTREACHED*/ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1724 | vassert(0); |
| 1725 | } |
| 1726 | |
| 1727 | default: |
| 1728 | vpanic("disAMode(x86)"); |
| 1729 | return 0; /*notreached*/ |
| 1730 | } |
| 1731 | } |
| 1732 | |
| 1733 | |
| 1734 | /* Figure out the number of (insn-stream) bytes constituting the amode |
| 1735 | beginning at delta. Is useful for getting hold of literals beyond |
| 1736 | the end of the amode before it has been disassembled. */ |
| 1737 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 1738 | static UInt lengthAMode ( Int delta ) |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1739 | { |
| 1740 | UChar mod_reg_rm = getIByte(delta); delta++; |
| 1741 | |
| 1742 | /* squeeze out the reg field from mod_reg_rm, since a 256-entry |
| 1743 | jump table seems a bit excessive. |
| 1744 | */ |
| 1745 | mod_reg_rm &= 0xC7; /* is now XX000YYY */ |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1746 | mod_reg_rm = toUChar(mod_reg_rm | (mod_reg_rm >> 3)); |
| 1747 | /* is now XX0XXYYY */ |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1748 | mod_reg_rm &= 0x1F; /* is now 000XXYYY */ |
| 1749 | switch (mod_reg_rm) { |
| 1750 | |
| 1751 | /* (%eax) .. (%edi), not including (%esp) or (%ebp). */ |
| 1752 | case 0x00: case 0x01: case 0x02: case 0x03: |
| 1753 | /* ! 04 */ /* ! 05 */ case 0x06: case 0x07: |
| 1754 | return 1; |
| 1755 | |
| 1756 | /* d8(%eax) ... d8(%edi), not including d8(%esp). */ |
| 1757 | case 0x08: case 0x09: case 0x0A: case 0x0B: |
| 1758 | /* ! 0C */ case 0x0D: case 0x0E: case 0x0F: |
| 1759 | return 2; |
| 1760 | |
| 1761 | /* d32(%eax) ... d32(%edi), not including d32(%esp). */ |
| 1762 | case 0x10: case 0x11: case 0x12: case 0x13: |
| 1763 | /* ! 14 */ case 0x15: case 0x16: case 0x17: |
| 1764 | return 5; |
| 1765 | |
| 1766 | /* a register, %eax .. %edi. (Not an addr, but still handled.) */ |
| 1767 | case 0x18: case 0x19: case 0x1A: case 0x1B: |
| 1768 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: |
| 1769 | return 1; |
| 1770 | |
| 1771 | /* a 32-bit literal address. */ |
| 1772 | case 0x05: return 5; |
| 1773 | |
| 1774 | /* SIB, no displacement. */ |
| 1775 | case 0x04: { |
| 1776 | UChar sib = getIByte(delta); |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 1777 | UChar base_r = toUChar(sib & 7); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 1778 | if (base_r == R_EBP) return 6; else return 2; |
| 1779 | } |
| 1780 | /* SIB, with 8-bit displacement. */ |
| 1781 | case 0x0C: return 3; |
| 1782 | |
| 1783 | /* SIB, with 32-bit displacement. */ |
| 1784 | case 0x14: return 6; |
| 1785 | |
| 1786 | default: |
| 1787 | vpanic("lengthAMode"); |
| 1788 | return 0; /*notreached*/ |
| 1789 | } |
| 1790 | } |
| 1791 | |
| 1792 | /*------------------------------------------------------------*/ |
| 1793 | /*--- Disassembling common idioms ---*/ |
| 1794 | /*------------------------------------------------------------*/ |
| 1795 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1796 | /* Handle binary integer instructions of the form |
| 1797 | op E, G meaning |
| 1798 | op reg-or-mem, reg |
| 1799 | Is passed the a ptr to the modRM byte, the actual operation, and the |
| 1800 | data size. Returns the address advanced completely over this |
| 1801 | instruction. |
| 1802 | |
| 1803 | E(src) is reg-or-mem |
| 1804 | G(dst) is reg. |
| 1805 | |
| 1806 | If E is reg, --> GET %G, tmp |
| 1807 | OP %E, tmp |
| 1808 | PUT tmp, %G |
| 1809 | |
| 1810 | If E is mem and OP is not reversible, |
| 1811 | --> (getAddr E) -> tmpa |
| 1812 | LD (tmpa), tmpa |
| 1813 | GET %G, tmp2 |
| 1814 | OP tmpa, tmp2 |
| 1815 | PUT tmp2, %G |
| 1816 | |
| 1817 | If E is mem and OP is reversible |
| 1818 | --> (getAddr E) -> tmpa |
| 1819 | LD (tmpa), tmpa |
| 1820 | OP %G, tmpa |
| 1821 | PUT tmpa, %G |
| 1822 | */ |
| 1823 | static |
| 1824 | UInt dis_op2_E_G ( UChar sorb, |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1825 | Bool addSubCarry, |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1826 | IROp op8, |
| 1827 | Bool keep, |
| 1828 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 1829 | Int delta0, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1830 | const HChar* t_x86opc ) |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1831 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1832 | HChar dis_buf[50]; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1833 | Int len; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1834 | IRType ty = szToITy(size); |
| 1835 | IRTemp dst1 = newTemp(ty); |
| 1836 | IRTemp src = newTemp(ty); |
| 1837 | IRTemp dst0 = newTemp(ty); |
| 1838 | UChar rm = getUChar(delta0); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 1839 | IRTemp addr = IRTemp_INVALID; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1840 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1841 | /* addSubCarry == True indicates the intended operation is |
| 1842 | add-with-carry or subtract-with-borrow. */ |
| 1843 | if (addSubCarry) { |
| 1844 | vassert(op8 == Iop_Add8 || op8 == Iop_Sub8); |
| 1845 | vassert(keep); |
| 1846 | } |
| 1847 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1848 | if (epartIsReg(rm)) { |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1849 | /* Specially handle XOR reg,reg, because that doesn't really |
| 1850 | depend on reg, and doing the obvious thing potentially |
| 1851 | generates a spurious value check failure due to the bogus |
sewardj | 55efbdf | 2005-05-02 17:07:02 +0000 | [diff] [blame] | 1852 | dependency. Ditto SBB reg,reg. */ |
| 1853 | if ((op8 == Iop_Xor8 || (op8 == Iop_Sub8 && addSubCarry)) |
| 1854 | && gregOfRM(rm) == eregOfRM(rm)) { |
| 1855 | putIReg(size, gregOfRM(rm), mkU(ty,0)); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1856 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1857 | assign( dst0, getIReg(size,gregOfRM(rm)) ); |
| 1858 | assign( src, getIReg(size,eregOfRM(rm)) ); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1859 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1860 | if (addSubCarry && op8 == Iop_Add8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1861 | helper_ADC( size, dst1, dst0, src, |
| 1862 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1863 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1864 | } else |
| 1865 | if (addSubCarry && op8 == Iop_Sub8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1866 | helper_SBB( size, dst1, dst0, src, |
| 1867 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1868 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
| 1869 | } else { |
| 1870 | assign( dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1871 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1872 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 1873 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1874 | setFlags_DEP1(op8, dst1, ty); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1875 | if (keep) |
| 1876 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
| 1877 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1878 | |
| 1879 | DIP("%s%c %s,%s\n", t_x86opc, nameISize(size), |
| 1880 | nameIReg(size,eregOfRM(rm)), |
| 1881 | nameIReg(size,gregOfRM(rm))); |
| 1882 | return 1+delta0; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1883 | } else { |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1884 | /* E refers to memory */ |
| 1885 | addr = disAMode ( &len, sorb, delta0, dis_buf); |
| 1886 | assign( dst0, getIReg(size,gregOfRM(rm)) ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 1887 | assign( src, loadLE(szToITy(size), mkexpr(addr)) ); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1888 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1889 | if (addSubCarry && op8 == Iop_Add8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1890 | helper_ADC( size, dst1, dst0, src, |
| 1891 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1892 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1893 | } else |
| 1894 | if (addSubCarry && op8 == Iop_Sub8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1895 | helper_SBB( size, dst1, dst0, src, |
| 1896 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1897 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
| 1898 | } else { |
| 1899 | assign( dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1900 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1901 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 1902 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1903 | setFlags_DEP1(op8, dst1, ty); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 1904 | if (keep) |
| 1905 | putIReg(size, gregOfRM(rm), mkexpr(dst1)); |
| 1906 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1907 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1908 | DIP("%s%c %s,%s\n", t_x86opc, nameISize(size), |
| 1909 | dis_buf,nameIReg(size,gregOfRM(rm))); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 1910 | return len+delta0; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1911 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1912 | } |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1913 | |
| 1914 | |
| 1915 | |
| 1916 | /* Handle binary integer instructions of the form |
| 1917 | op G, E meaning |
| 1918 | op reg, reg-or-mem |
| 1919 | Is passed the a ptr to the modRM byte, the actual operation, and the |
| 1920 | data size. Returns the address advanced completely over this |
| 1921 | instruction. |
| 1922 | |
| 1923 | G(src) is reg. |
| 1924 | E(dst) is reg-or-mem |
| 1925 | |
| 1926 | If E is reg, --> GET %E, tmp |
| 1927 | OP %G, tmp |
| 1928 | PUT tmp, %E |
| 1929 | |
| 1930 | If E is mem, --> (getAddr E) -> tmpa |
| 1931 | LD (tmpa), tmpv |
| 1932 | OP %G, tmpv |
| 1933 | ST tmpv, (tmpa) |
| 1934 | */ |
| 1935 | static |
| 1936 | UInt dis_op2_G_E ( UChar sorb, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1937 | Bool locked, |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1938 | Bool addSubCarry, |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1939 | IROp op8, |
| 1940 | Bool keep, |
| 1941 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 1942 | Int delta0, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1943 | const HChar* t_x86opc ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1944 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1945 | HChar dis_buf[50]; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1946 | Int len; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1947 | IRType ty = szToITy(size); |
| 1948 | IRTemp dst1 = newTemp(ty); |
| 1949 | IRTemp src = newTemp(ty); |
| 1950 | IRTemp dst0 = newTemp(ty); |
| 1951 | UChar rm = getIByte(delta0); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 1952 | IRTemp addr = IRTemp_INVALID; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1953 | |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1954 | /* addSubCarry == True indicates the intended operation is |
| 1955 | add-with-carry or subtract-with-borrow. */ |
| 1956 | if (addSubCarry) { |
| 1957 | vassert(op8 == Iop_Add8 || op8 == Iop_Sub8); |
| 1958 | vassert(keep); |
| 1959 | } |
| 1960 | |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1961 | if (epartIsReg(rm)) { |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1962 | /* Specially handle XOR reg,reg, because that doesn't really |
| 1963 | depend on reg, and doing the obvious thing potentially |
| 1964 | generates a spurious value check failure due to the bogus |
sewardj | 55efbdf | 2005-05-02 17:07:02 +0000 | [diff] [blame] | 1965 | dependency. Ditto SBB reg,reg.*/ |
| 1966 | if ((op8 == Iop_Xor8 || (op8 == Iop_Sub8 && addSubCarry)) |
| 1967 | && gregOfRM(rm) == eregOfRM(rm)) { |
| 1968 | putIReg(size, eregOfRM(rm), mkU(ty,0)); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1969 | } |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1970 | assign(dst0, getIReg(size,eregOfRM(rm))); |
| 1971 | assign(src, getIReg(size,gregOfRM(rm))); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1972 | |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1973 | if (addSubCarry && op8 == Iop_Add8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1974 | helper_ADC( size, dst1, dst0, src, |
| 1975 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 1976 | putIReg(size, eregOfRM(rm), mkexpr(dst1)); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1977 | } else |
| 1978 | if (addSubCarry && op8 == Iop_Sub8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1979 | helper_SBB( size, dst1, dst0, src, |
| 1980 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1981 | putIReg(size, eregOfRM(rm), mkexpr(dst1)); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1982 | } else { |
| 1983 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src))); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 1984 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1985 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 1986 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 1987 | setFlags_DEP1(op8, dst1, ty); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 1988 | if (keep) |
| 1989 | putIReg(size, eregOfRM(rm), mkexpr(dst1)); |
| 1990 | } |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 1991 | |
| 1992 | DIP("%s%c %s,%s\n", t_x86opc, nameISize(size), |
| 1993 | nameIReg(size,gregOfRM(rm)), |
| 1994 | nameIReg(size,eregOfRM(rm))); |
| 1995 | return 1+delta0; |
| 1996 | } |
| 1997 | |
| 1998 | /* E refers to memory */ |
| 1999 | { |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 2000 | addr = disAMode ( &len, sorb, delta0, dis_buf); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2001 | assign(dst0, loadLE(ty,mkexpr(addr))); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 2002 | assign(src, getIReg(size,gregOfRM(rm))); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2003 | |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2004 | if (addSubCarry && op8 == Iop_Add8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2005 | if (locked) { |
| 2006 | /* cas-style store */ |
| 2007 | helper_ADC( size, dst1, dst0, src, |
| 2008 | /*store*/addr, dst0/*expVal*/, guest_EIP_curr_instr ); |
| 2009 | } else { |
| 2010 | /* normal store */ |
| 2011 | helper_ADC( size, dst1, dst0, src, |
| 2012 | /*store*/addr, IRTemp_INVALID, 0 ); |
| 2013 | } |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2014 | } else |
| 2015 | if (addSubCarry && op8 == Iop_Sub8) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2016 | if (locked) { |
| 2017 | /* cas-style store */ |
| 2018 | helper_SBB( size, dst1, dst0, src, |
| 2019 | /*store*/addr, dst0/*expVal*/, guest_EIP_curr_instr ); |
| 2020 | } else { |
| 2021 | /* normal store */ |
| 2022 | helper_SBB( size, dst1, dst0, src, |
| 2023 | /*store*/addr, IRTemp_INVALID, 0 ); |
| 2024 | } |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2025 | } else { |
| 2026 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2027 | if (keep) { |
| 2028 | if (locked) { |
| 2029 | if (0) vex_printf("locked case\n" ); |
| 2030 | casLE( mkexpr(addr), |
| 2031 | mkexpr(dst0)/*expval*/, |
| 2032 | mkexpr(dst1)/*newval*/, guest_EIP_curr_instr ); |
| 2033 | } else { |
| 2034 | if (0) vex_printf("nonlocked case\n"); |
| 2035 | storeLE(mkexpr(addr), mkexpr(dst1)); |
| 2036 | } |
| 2037 | } |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2038 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2039 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 2040 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2041 | setFlags_DEP1(op8, dst1, ty); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2042 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 2043 | |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2044 | DIP("%s%c %s,%s\n", t_x86opc, nameISize(size), |
| 2045 | nameIReg(size,gregOfRM(rm)), dis_buf); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 2046 | return len+delta0; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2047 | } |
| 2048 | } |
| 2049 | |
| 2050 | |
| 2051 | /* Handle move instructions of the form |
| 2052 | mov E, G meaning |
| 2053 | mov reg-or-mem, reg |
| 2054 | Is passed the a ptr to the modRM byte, and the data size. Returns |
| 2055 | the address advanced completely over this instruction. |
| 2056 | |
| 2057 | E(src) is reg-or-mem |
| 2058 | G(dst) is reg. |
| 2059 | |
| 2060 | If E is reg, --> GET %E, tmpv |
| 2061 | PUT tmpv, %G |
| 2062 | |
| 2063 | If E is mem --> (getAddr E) -> tmpa |
| 2064 | LD (tmpa), tmpb |
| 2065 | PUT tmpb, %G |
| 2066 | */ |
| 2067 | static |
| 2068 | UInt dis_mov_E_G ( UChar sorb, |
| 2069 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2070 | Int delta0 ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2071 | { |
| 2072 | Int len; |
| 2073 | UChar rm = getIByte(delta0); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2074 | HChar dis_buf[50]; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2075 | |
| 2076 | if (epartIsReg(rm)) { |
sewardj | 7ca37d9 | 2004-10-25 02:58:30 +0000 | [diff] [blame] | 2077 | putIReg(size, gregOfRM(rm), getIReg(size, eregOfRM(rm))); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2078 | DIP("mov%c %s,%s\n", nameISize(size), |
| 2079 | nameIReg(size,eregOfRM(rm)), |
| 2080 | nameIReg(size,gregOfRM(rm))); |
sewardj | 7ca37d9 | 2004-10-25 02:58:30 +0000 | [diff] [blame] | 2081 | return 1+delta0; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2082 | } |
| 2083 | |
| 2084 | /* E refers to memory */ |
| 2085 | { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2086 | IRTemp addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 2087 | putIReg(size, gregOfRM(rm), loadLE(szToITy(size), mkexpr(addr))); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2088 | DIP("mov%c %s,%s\n", nameISize(size), |
| 2089 | dis_buf,nameIReg(size,gregOfRM(rm))); |
| 2090 | return delta0+len; |
| 2091 | } |
| 2092 | } |
| 2093 | |
| 2094 | |
| 2095 | /* Handle move instructions of the form |
| 2096 | mov G, E meaning |
| 2097 | mov reg, reg-or-mem |
| 2098 | Is passed the a ptr to the modRM byte, and the data size. Returns |
| 2099 | the address advanced completely over this instruction. |
| 2100 | |
| 2101 | G(src) is reg. |
| 2102 | E(dst) is reg-or-mem |
| 2103 | |
| 2104 | If E is reg, --> GET %G, tmp |
| 2105 | PUT tmp, %E |
| 2106 | |
| 2107 | If E is mem, --> (getAddr E) -> tmpa |
| 2108 | GET %G, tmpv |
| 2109 | ST tmpv, (tmpa) |
| 2110 | */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2111 | static |
| 2112 | UInt dis_mov_G_E ( UChar sorb, |
| 2113 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2114 | Int delta0 ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2115 | { |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2116 | Int len; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2117 | UChar rm = getIByte(delta0); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2118 | HChar dis_buf[50]; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2119 | |
| 2120 | if (epartIsReg(rm)) { |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2121 | putIReg(size, eregOfRM(rm), getIReg(size, gregOfRM(rm))); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2122 | DIP("mov%c %s,%s\n", nameISize(size), |
| 2123 | nameIReg(size,gregOfRM(rm)), |
| 2124 | nameIReg(size,eregOfRM(rm))); |
| 2125 | return 1+delta0; |
| 2126 | } |
| 2127 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2128 | /* E refers to memory */ |
| 2129 | { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2130 | IRTemp addr = disAMode ( &len, sorb, delta0, dis_buf); |
| 2131 | storeLE( mkexpr(addr), getIReg(size, gregOfRM(rm)) ); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2132 | DIP("mov%c %s,%s\n", nameISize(size), |
| 2133 | nameIReg(size,gregOfRM(rm)), dis_buf); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2134 | return len+delta0; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2135 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 2136 | } |
| 2137 | |
| 2138 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 2139 | /* op $immediate, AL/AX/EAX. */ |
| 2140 | static |
| 2141 | UInt dis_op_imm_A ( Int size, |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2142 | Bool carrying, |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 2143 | IROp op8, |
| 2144 | Bool keep, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2145 | Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 2146 | const HChar* t_x86opc ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 2147 | { |
| 2148 | IRType ty = szToITy(size); |
| 2149 | IRTemp dst0 = newTemp(ty); |
| 2150 | IRTemp src = newTemp(ty); |
| 2151 | IRTemp dst1 = newTemp(ty); |
| 2152 | UInt lit = getUDisp(size,delta); |
| 2153 | assign(dst0, getIReg(size,R_EAX)); |
| 2154 | assign(src, mkU(ty,lit)); |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2155 | |
| 2156 | if (isAddSub(op8) && !carrying) { |
| 2157 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2158 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2159 | } |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 2160 | else |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2161 | if (isLogic(op8)) { |
| 2162 | vassert(!carrying); |
| 2163 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2164 | setFlags_DEP1(op8, dst1, ty); |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2165 | } |
| 2166 | else |
| 2167 | if (op8 == Iop_Add8 && carrying) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2168 | helper_ADC( size, dst1, dst0, src, |
| 2169 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 2170 | } |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2171 | else |
sewardj | 2fbae08 | 2005-10-03 02:07:08 +0000 | [diff] [blame] | 2172 | if (op8 == Iop_Sub8 && carrying) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2173 | helper_SBB( size, dst1, dst0, src, |
| 2174 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 2fbae08 | 2005-10-03 02:07:08 +0000 | [diff] [blame] | 2175 | } |
| 2176 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2177 | vpanic("dis_op_imm_A(x86,guest)"); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 2178 | |
| 2179 | if (keep) |
| 2180 | putIReg(size, R_EAX, mkexpr(dst1)); |
| 2181 | |
| 2182 | DIP("%s%c $0x%x, %s\n", t_x86opc, nameISize(size), |
| 2183 | lit, nameIReg(size,R_EAX)); |
| 2184 | return delta+size; |
| 2185 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2186 | |
| 2187 | |
| 2188 | /* Sign- and Zero-extending moves. */ |
| 2189 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2190 | UInt dis_movx_E_G ( UChar sorb, |
| 2191 | Int delta, Int szs, Int szd, Bool sign_extend ) |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2192 | { |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2193 | UChar rm = getIByte(delta); |
| 2194 | if (epartIsReg(rm)) { |
sewardj | 33ca4ac | 2010-09-30 13:37:31 +0000 | [diff] [blame] | 2195 | if (szd == szs) { |
| 2196 | // mutant case. See #250799 |
| 2197 | putIReg(szd, gregOfRM(rm), |
| 2198 | getIReg(szs,eregOfRM(rm))); |
| 2199 | } else { |
| 2200 | // normal case |
| 2201 | putIReg(szd, gregOfRM(rm), |
| 2202 | unop(mkWidenOp(szs,szd,sign_extend), |
| 2203 | getIReg(szs,eregOfRM(rm)))); |
| 2204 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2205 | DIP("mov%c%c%c %s,%s\n", sign_extend ? 's' : 'z', |
| 2206 | nameISize(szs), nameISize(szd), |
| 2207 | nameIReg(szs,eregOfRM(rm)), |
| 2208 | nameIReg(szd,gregOfRM(rm))); |
| 2209 | return 1+delta; |
| 2210 | } |
| 2211 | |
| 2212 | /* E refers to memory */ |
| 2213 | { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2214 | Int len; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2215 | HChar dis_buf[50]; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2216 | IRTemp addr = disAMode ( &len, sorb, delta, dis_buf ); |
sewardj | 33ca4ac | 2010-09-30 13:37:31 +0000 | [diff] [blame] | 2217 | if (szd == szs) { |
| 2218 | // mutant case. See #250799 |
| 2219 | putIReg(szd, gregOfRM(rm), |
| 2220 | loadLE(szToITy(szs),mkexpr(addr))); |
| 2221 | } else { |
| 2222 | // normal case |
| 2223 | putIReg(szd, gregOfRM(rm), |
| 2224 | unop(mkWidenOp(szs,szd,sign_extend), |
| 2225 | loadLE(szToITy(szs),mkexpr(addr)))); |
| 2226 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2227 | DIP("mov%c%c%c %s,%s\n", sign_extend ? 's' : 'z', |
| 2228 | nameISize(szs), nameISize(szd), |
| 2229 | dis_buf, nameIReg(szd,gregOfRM(rm))); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 2230 | return len+delta; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 2231 | } |
| 2232 | } |
| 2233 | |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2234 | |
| 2235 | /* Generate code to divide ArchRegs EDX:EAX / DX:AX / AX by the 32 / |
| 2236 | 16 / 8 bit quantity in the given IRTemp. */ |
| 2237 | static |
| 2238 | void codegen_div ( Int sz, IRTemp t, Bool signed_divide ) |
| 2239 | { |
sewardj | e5427e8 | 2004-09-11 19:43:51 +0000 | [diff] [blame] | 2240 | IROp op = signed_divide ? Iop_DivModS64to32 : Iop_DivModU64to32; |
| 2241 | IRTemp src64 = newTemp(Ity_I64); |
| 2242 | IRTemp dst64 = newTemp(Ity_I64); |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2243 | switch (sz) { |
sewardj | e5427e8 | 2004-09-11 19:43:51 +0000 | [diff] [blame] | 2244 | case 4: |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2245 | assign( src64, binop(Iop_32HLto64, |
sewardj | e5427e8 | 2004-09-11 19:43:51 +0000 | [diff] [blame] | 2246 | getIReg(4,R_EDX), getIReg(4,R_EAX)) ); |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2247 | assign( dst64, binop(op, mkexpr(src64), mkexpr(t)) ); |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 2248 | putIReg( 4, R_EAX, unop(Iop_64to32,mkexpr(dst64)) ); |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2249 | putIReg( 4, R_EDX, unop(Iop_64HIto32,mkexpr(dst64)) ); |
| 2250 | break; |
sewardj | e5427e8 | 2004-09-11 19:43:51 +0000 | [diff] [blame] | 2251 | case 2: { |
| 2252 | IROp widen3264 = signed_divide ? Iop_32Sto64 : Iop_32Uto64; |
| 2253 | IROp widen1632 = signed_divide ? Iop_16Sto32 : Iop_16Uto32; |
| 2254 | assign( src64, unop(widen3264, |
| 2255 | binop(Iop_16HLto32, |
| 2256 | getIReg(2,R_EDX), getIReg(2,R_EAX))) ); |
| 2257 | assign( dst64, binop(op, mkexpr(src64), unop(widen1632,mkexpr(t))) ); |
| 2258 | putIReg( 2, R_EAX, unop(Iop_32to16,unop(Iop_64to32,mkexpr(dst64))) ); |
| 2259 | putIReg( 2, R_EDX, unop(Iop_32to16,unop(Iop_64HIto32,mkexpr(dst64))) ); |
| 2260 | break; |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2261 | } |
sewardj | 4e82db7 | 2004-10-16 11:32:15 +0000 | [diff] [blame] | 2262 | case 1: { |
| 2263 | IROp widen3264 = signed_divide ? Iop_32Sto64 : Iop_32Uto64; |
| 2264 | IROp widen1632 = signed_divide ? Iop_16Sto32 : Iop_16Uto32; |
| 2265 | IROp widen816 = signed_divide ? Iop_8Sto16 : Iop_8Uto16; |
| 2266 | assign( src64, unop(widen3264, unop(widen1632, getIReg(2,R_EAX))) ); |
| 2267 | assign( dst64, |
| 2268 | binop(op, mkexpr(src64), |
| 2269 | unop(widen1632, unop(widen816, mkexpr(t)))) ); |
| 2270 | putIReg( 1, R_AL, unop(Iop_16to8, unop(Iop_32to16, |
| 2271 | unop(Iop_64to32,mkexpr(dst64)))) ); |
| 2272 | putIReg( 1, R_AH, unop(Iop_16to8, unop(Iop_32to16, |
| 2273 | unop(Iop_64HIto32,mkexpr(dst64)))) ); |
| 2274 | break; |
| 2275 | } |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2276 | default: vpanic("codegen_div(x86)"); |
| 2277 | } |
| 2278 | } |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2279 | |
| 2280 | |
| 2281 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2282 | UInt dis_Grp1 ( UChar sorb, Bool locked, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2283 | Int delta, UChar modrm, |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2284 | Int am_sz, Int d_sz, Int sz, UInt d32 ) |
| 2285 | { |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2286 | Int len; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2287 | HChar dis_buf[50]; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2288 | IRType ty = szToITy(sz); |
| 2289 | IRTemp dst1 = newTemp(ty); |
| 2290 | IRTemp src = newTemp(ty); |
| 2291 | IRTemp dst0 = newTemp(ty); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 2292 | IRTemp addr = IRTemp_INVALID; |
sewardj | 66de227 | 2004-07-16 21:19:05 +0000 | [diff] [blame] | 2293 | IROp op8 = Iop_INVALID; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2294 | UInt mask = sz==1 ? 0xFF : (sz==2 ? 0xFFFF : 0xFFFFFFFF); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2295 | |
| 2296 | switch (gregOfRM(modrm)) { |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2297 | case 0: op8 = Iop_Add8; break; case 1: op8 = Iop_Or8; break; |
sewardj | 66de227 | 2004-07-16 21:19:05 +0000 | [diff] [blame] | 2298 | case 2: break; // ADC |
| 2299 | case 3: break; // SBB |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2300 | case 4: op8 = Iop_And8; break; case 5: op8 = Iop_Sub8; break; |
| 2301 | case 6: op8 = Iop_Xor8; break; case 7: op8 = Iop_Sub8; break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2302 | /*NOTREACHED*/ |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2303 | default: vpanic("dis_Grp1: unhandled case"); |
| 2304 | } |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2305 | |
| 2306 | if (epartIsReg(modrm)) { |
| 2307 | vassert(am_sz == 1); |
| 2308 | |
| 2309 | assign(dst0, getIReg(sz,eregOfRM(modrm))); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2310 | assign(src, mkU(ty,d32 & mask)); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2311 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2312 | if (gregOfRM(modrm) == 2 /* ADC */) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2313 | helper_ADC( sz, dst1, dst0, src, |
| 2314 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2315 | } else |
| 2316 | if (gregOfRM(modrm) == 3 /* SBB */) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2317 | helper_SBB( sz, dst1, dst0, src, |
| 2318 | /*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2319 | } else { |
| 2320 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src))); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2321 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2322 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 2323 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2324 | setFlags_DEP1(op8, dst1, ty); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2325 | } |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2326 | |
| 2327 | if (gregOfRM(modrm) < 7) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 2328 | putIReg(sz, eregOfRM(modrm), mkexpr(dst1)); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2329 | |
| 2330 | delta += (am_sz + d_sz); |
| 2331 | DIP("%s%c $0x%x, %s\n", nameGrp1(gregOfRM(modrm)), nameISize(sz), d32, |
| 2332 | nameIReg(sz,eregOfRM(modrm))); |
| 2333 | } else { |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 2334 | addr = disAMode ( &len, sorb, delta, dis_buf); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2335 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2336 | assign(dst0, loadLE(ty,mkexpr(addr))); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 2337 | assign(src, mkU(ty,d32 & mask)); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2338 | |
sewardj | 66de227 | 2004-07-16 21:19:05 +0000 | [diff] [blame] | 2339 | if (gregOfRM(modrm) == 2 /* ADC */) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2340 | if (locked) { |
| 2341 | /* cas-style store */ |
| 2342 | helper_ADC( sz, dst1, dst0, src, |
| 2343 | /*store*/addr, dst0/*expVal*/, guest_EIP_curr_instr ); |
| 2344 | } else { |
| 2345 | /* normal store */ |
| 2346 | helper_ADC( sz, dst1, dst0, src, |
| 2347 | /*store*/addr, IRTemp_INVALID, 0 ); |
| 2348 | } |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 2349 | } else |
sewardj | 66de227 | 2004-07-16 21:19:05 +0000 | [diff] [blame] | 2350 | if (gregOfRM(modrm) == 3 /* SBB */) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2351 | if (locked) { |
| 2352 | /* cas-style store */ |
| 2353 | helper_SBB( sz, dst1, dst0, src, |
| 2354 | /*store*/addr, dst0/*expVal*/, guest_EIP_curr_instr ); |
| 2355 | } else { |
| 2356 | /* normal store */ |
| 2357 | helper_SBB( sz, dst1, dst0, src, |
| 2358 | /*store*/addr, IRTemp_INVALID, 0 ); |
| 2359 | } |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 2360 | } else { |
| 2361 | assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2362 | if (gregOfRM(modrm) < 7) { |
| 2363 | if (locked) { |
| 2364 | casLE( mkexpr(addr), mkexpr(dst0)/*expVal*/, |
| 2365 | mkexpr(dst1)/*newVal*/, |
| 2366 | guest_EIP_curr_instr ); |
| 2367 | } else { |
| 2368 | storeLE(mkexpr(addr), mkexpr(dst1)); |
| 2369 | } |
| 2370 | } |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2371 | if (isAddSub(op8)) |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2372 | setFlags_DEP1_DEP2(op8, dst0, src, ty); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 2373 | else |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2374 | setFlags_DEP1(op8, dst1, ty); |
sewardj | 3af115f | 2004-07-14 02:46:52 +0000 | [diff] [blame] | 2375 | } |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2376 | |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 2377 | delta += (len+d_sz); |
| 2378 | DIP("%s%c $0x%x, %s\n", nameGrp1(gregOfRM(modrm)), nameISize(sz), |
| 2379 | d32, dis_buf); |
| 2380 | } |
| 2381 | return delta; |
| 2382 | } |
| 2383 | |
| 2384 | |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2385 | /* Group 2 extended opcodes. shift_expr must be an 8-bit typed |
| 2386 | expression. */ |
| 2387 | |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2388 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2389 | UInt dis_Grp2 ( UChar sorb, |
| 2390 | Int delta, UChar modrm, |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2391 | Int am_sz, Int d_sz, Int sz, IRExpr* shift_expr, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 2392 | const HChar* shift_expr_txt, Bool* decode_OK ) |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2393 | { |
| 2394 | /* delta on entry points at the modrm byte. */ |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2395 | HChar dis_buf[50]; |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2396 | Int len; |
sewardj | 2eef773 | 2005-08-23 15:41:14 +0000 | [diff] [blame] | 2397 | Bool isShift, isRotate, isRotateC; |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2398 | IRType ty = szToITy(sz); |
| 2399 | IRTemp dst0 = newTemp(ty); |
| 2400 | IRTemp dst1 = newTemp(ty); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 2401 | IRTemp addr = IRTemp_INVALID; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2402 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2403 | *decode_OK = True; |
| 2404 | |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2405 | vassert(sz == 1 || sz == 2 || sz == 4); |
| 2406 | |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2407 | /* Put value to shift/rotate in dst0. */ |
| 2408 | if (epartIsReg(modrm)) { |
| 2409 | assign(dst0, getIReg(sz, eregOfRM(modrm))); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2410 | delta += (am_sz + d_sz); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2411 | } else { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2412 | addr = disAMode ( &len, sorb, delta, dis_buf); |
| 2413 | assign(dst0, loadLE(ty,mkexpr(addr))); |
| 2414 | delta += len + d_sz; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2415 | } |
| 2416 | |
| 2417 | isShift = False; |
tom | d6b43fd | 2011-08-19 16:06:52 +0000 | [diff] [blame] | 2418 | switch (gregOfRM(modrm)) { case 4: case 5: case 6: case 7: isShift = True; } |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2419 | |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2420 | isRotate = False; |
| 2421 | switch (gregOfRM(modrm)) { case 0: case 1: isRotate = True; } |
| 2422 | |
sewardj | 2eef773 | 2005-08-23 15:41:14 +0000 | [diff] [blame] | 2423 | isRotateC = False; |
| 2424 | switch (gregOfRM(modrm)) { case 2: case 3: isRotateC = True; } |
sewardj | 9aebb0c | 2004-10-24 19:20:43 +0000 | [diff] [blame] | 2425 | |
sewardj | 2eef773 | 2005-08-23 15:41:14 +0000 | [diff] [blame] | 2426 | if (!isShift && !isRotate && !isRotateC) { |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2427 | /*NOTREACHED*/ |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 2428 | vpanic("dis_Grp2(Reg): unhandled case(x86)"); |
| 2429 | } |
| 2430 | |
sewardj | 2eef773 | 2005-08-23 15:41:14 +0000 | [diff] [blame] | 2431 | if (isRotateC) { |
| 2432 | /* call a helper; these insns are so ridiculous they do not |
| 2433 | deserve better */ |
| 2434 | Bool left = toBool(gregOfRM(modrm) == 2); |
sewardj | 9aebb0c | 2004-10-24 19:20:43 +0000 | [diff] [blame] | 2435 | IRTemp r64 = newTemp(Ity_I64); |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2436 | IRExpr** args |
| 2437 | = mkIRExprVec_4( widenUto32(mkexpr(dst0)), /* thing to rotate */ |
| 2438 | widenUto32(shift_expr), /* rotate amount */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2439 | widenUto32(mk_x86g_calculate_eflags_all()), |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2440 | mkU32(sz) ); |
| 2441 | assign( r64, mkIRExprCCall( |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 2442 | Ity_I64, |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2443 | 0/*regparm*/, |
sewardj | 2eef773 | 2005-08-23 15:41:14 +0000 | [diff] [blame] | 2444 | left ? "x86g_calculate_RCL" : "x86g_calculate_RCR", |
| 2445 | left ? &x86g_calculate_RCL : &x86g_calculate_RCR, |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 2446 | args |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2447 | ) |
| 2448 | ); |
sewardj | 9aebb0c | 2004-10-24 19:20:43 +0000 | [diff] [blame] | 2449 | /* new eflags in hi half r64; new value in lo half r64 */ |
| 2450 | assign( dst1, narrowTo(ty, unop(Iop_64to32, mkexpr(r64))) ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2451 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2452 | stmt( IRStmt_Put( OFFB_CC_DEP1, unop(Iop_64HIto32, mkexpr(r64)) )); |
| 2453 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 2454 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 2455 | elimination of previous stores to this field work better. */ |
| 2456 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 9aebb0c | 2004-10-24 19:20:43 +0000 | [diff] [blame] | 2457 | } |
| 2458 | |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2459 | if (isShift) { |
| 2460 | |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2461 | IRTemp pre32 = newTemp(Ity_I32); |
| 2462 | IRTemp res32 = newTemp(Ity_I32); |
| 2463 | IRTemp res32ss = newTemp(Ity_I32); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2464 | IRTemp shift_amt = newTemp(Ity_I8); |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2465 | IROp op32; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2466 | |
| 2467 | switch (gregOfRM(modrm)) { |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2468 | case 4: op32 = Iop_Shl32; break; |
| 2469 | case 5: op32 = Iop_Shr32; break; |
tom | d6b43fd | 2011-08-19 16:06:52 +0000 | [diff] [blame] | 2470 | case 6: op32 = Iop_Shl32; break; |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2471 | case 7: op32 = Iop_Sar32; break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2472 | /*NOTREACHED*/ |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2473 | default: vpanic("dis_Grp2:shift"); break; |
| 2474 | } |
| 2475 | |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2476 | /* Widen the value to be shifted to 32 bits, do the shift, and |
| 2477 | narrow back down. This seems surprisingly long-winded, but |
| 2478 | unfortunately the Intel semantics requires that 8/16-bit |
| 2479 | shifts give defined results for shift values all the way up |
| 2480 | to 31, and this seems the simplest way to do it. It has the |
| 2481 | advantage that the only IR level shifts generated are of 32 |
| 2482 | bit values, and the shift amount is guaranteed to be in the |
| 2483 | range 0 .. 31, thereby observing the IR semantics requiring |
| 2484 | all shift values to be in the range 0 .. 2^word_size-1. */ |
| 2485 | |
| 2486 | /* shift_amt = shift_expr & 31, regardless of operation size */ |
| 2487 | assign( shift_amt, binop(Iop_And8, shift_expr, mkU8(31)) ); |
| 2488 | |
| 2489 | /* suitably widen the value to be shifted to 32 bits. */ |
| 2490 | assign( pre32, op32==Iop_Sar32 ? widenSto32(mkexpr(dst0)) |
| 2491 | : widenUto32(mkexpr(dst0)) ); |
| 2492 | |
| 2493 | /* res32 = pre32 `shift` shift_amt */ |
| 2494 | assign( res32, binop(op32, mkexpr(pre32), mkexpr(shift_amt)) ); |
| 2495 | |
| 2496 | /* res32ss = pre32 `shift` ((shift_amt - 1) & 31) */ |
| 2497 | assign( res32ss, |
| 2498 | binop(op32, |
| 2499 | mkexpr(pre32), |
| 2500 | binop(Iop_And8, |
| 2501 | binop(Iop_Sub8, |
| 2502 | mkexpr(shift_amt), mkU8(1)), |
| 2503 | mkU8(31))) ); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2504 | |
| 2505 | /* Build the flags thunk. */ |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2506 | setFlags_DEP1_DEP2_shift(op32, res32, res32ss, ty, shift_amt); |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2507 | |
| 2508 | /* Narrow the result back down. */ |
| 2509 | assign( dst1, narrowTo(ty, mkexpr(res32)) ); |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2510 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2511 | } /* if (isShift) */ |
| 2512 | |
| 2513 | else |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2514 | if (isRotate) { |
sewardj | 7ebbdae | 2004-08-26 12:30:48 +0000 | [diff] [blame] | 2515 | Int ccOp = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 2516 | Bool left = toBool(gregOfRM(modrm) == 0); |
sewardj | 7ebbdae | 2004-08-26 12:30:48 +0000 | [diff] [blame] | 2517 | IRTemp rot_amt = newTemp(Ity_I8); |
| 2518 | IRTemp rot_amt32 = newTemp(Ity_I8); |
| 2519 | IRTemp oldFlags = newTemp(Ity_I32); |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2520 | |
| 2521 | /* rot_amt = shift_expr & mask */ |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2522 | /* By masking the rotate amount thusly, the IR-level Shl/Shr |
| 2523 | expressions never shift beyond the word size and thus remain |
| 2524 | well defined. */ |
sewardj | 7ebbdae | 2004-08-26 12:30:48 +0000 | [diff] [blame] | 2525 | assign(rot_amt32, binop(Iop_And8, shift_expr, mkU8(31))); |
| 2526 | |
| 2527 | if (ty == Ity_I32) |
| 2528 | assign(rot_amt, mkexpr(rot_amt32)); |
| 2529 | else |
| 2530 | assign(rot_amt, binop(Iop_And8, mkexpr(rot_amt32), mkU8(8*sz-1))); |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2531 | |
| 2532 | if (left) { |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2533 | |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2534 | /* dst1 = (dst0 << rot_amt) | (dst0 >>u (wordsize-rot_amt)) */ |
| 2535 | assign(dst1, |
| 2536 | binop( mkSizedOp(ty,Iop_Or8), |
| 2537 | binop( mkSizedOp(ty,Iop_Shl8), |
| 2538 | mkexpr(dst0), |
| 2539 | mkexpr(rot_amt) |
| 2540 | ), |
| 2541 | binop( mkSizedOp(ty,Iop_Shr8), |
| 2542 | mkexpr(dst0), |
| 2543 | binop(Iop_Sub8,mkU8(8*sz), mkexpr(rot_amt)) |
| 2544 | ) |
| 2545 | ) |
| 2546 | ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2547 | ccOp += X86G_CC_OP_ROLB; |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2548 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2549 | } else { /* right */ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2550 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2551 | /* dst1 = (dst0 >>u rot_amt) | (dst0 << (wordsize-rot_amt)) */ |
| 2552 | assign(dst1, |
| 2553 | binop( mkSizedOp(ty,Iop_Or8), |
| 2554 | binop( mkSizedOp(ty,Iop_Shr8), |
| 2555 | mkexpr(dst0), |
| 2556 | mkexpr(rot_amt) |
| 2557 | ), |
| 2558 | binop( mkSizedOp(ty,Iop_Shl8), |
| 2559 | mkexpr(dst0), |
| 2560 | binop(Iop_Sub8,mkU8(8*sz), mkexpr(rot_amt)) |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2561 | ) |
| 2562 | ) |
| 2563 | ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2564 | ccOp += X86G_CC_OP_RORB; |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2565 | |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2566 | } |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 2567 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2568 | /* dst1 now holds the rotated value. Build flag thunk. We |
| 2569 | need the resulting value for this, and the previous flags. |
| 2570 | Except don't set it if the rotate count is zero. */ |
| 2571 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2572 | assign(oldFlags, mk_x86g_calculate_eflags_all()); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2573 | |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 2574 | /* rot_amt32 :: Ity_I8. We need to convert it to I1. */ |
| 2575 | IRTemp rot_amt32b = newTemp(Ity_I1); |
| 2576 | assign(rot_amt32b, binop(Iop_CmpNE8, mkexpr(rot_amt32), mkU8(0)) ); |
| 2577 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2578 | /* CC_DEP1 is the rotated value. CC_NDEP is flags before. */ |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2579 | stmt( IRStmt_Put( OFFB_CC_OP, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 2580 | IRExpr_ITE( mkexpr(rot_amt32b), |
| 2581 | mkU32(ccOp), |
| 2582 | IRExpr_Get(OFFB_CC_OP,Ity_I32) ) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2583 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 2584 | IRExpr_ITE( mkexpr(rot_amt32b), |
| 2585 | widenUto32(mkexpr(dst1)), |
| 2586 | IRExpr_Get(OFFB_CC_DEP1,Ity_I32) ) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2587 | stmt( IRStmt_Put( OFFB_CC_DEP2, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 2588 | IRExpr_ITE( mkexpr(rot_amt32b), |
| 2589 | mkU32(0), |
| 2590 | IRExpr_Get(OFFB_CC_DEP2,Ity_I32) ) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2591 | stmt( IRStmt_Put( OFFB_CC_NDEP, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 2592 | IRExpr_ITE( mkexpr(rot_amt32b), |
| 2593 | mkexpr(oldFlags), |
| 2594 | IRExpr_Get(OFFB_CC_NDEP,Ity_I32) ) )); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2595 | } /* if (isRotate) */ |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2596 | |
| 2597 | /* Save result, and finish up. */ |
| 2598 | if (epartIsReg(modrm)) { |
| 2599 | putIReg(sz, eregOfRM(modrm), mkexpr(dst1)); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 2600 | if (vex_traceflags & VEX_TRACE_FE) { |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2601 | vex_printf("%s%c ", |
| 2602 | nameGrp2(gregOfRM(modrm)), nameISize(sz) ); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2603 | if (shift_expr_txt) |
| 2604 | vex_printf("%s", shift_expr_txt); |
| 2605 | else |
| 2606 | ppIRExpr(shift_expr); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2607 | vex_printf(", %s\n", nameIReg(sz,eregOfRM(modrm))); |
| 2608 | } |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2609 | } else { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2610 | storeLE(mkexpr(addr), mkexpr(dst1)); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 2611 | if (vex_traceflags & VEX_TRACE_FE) { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2612 | vex_printf("%s%c ", |
| 2613 | nameGrp2(gregOfRM(modrm)), nameISize(sz) ); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2614 | if (shift_expr_txt) |
| 2615 | vex_printf("%s", shift_expr_txt); |
| 2616 | else |
| 2617 | ppIRExpr(shift_expr); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2618 | vex_printf(", %s\n", dis_buf); |
| 2619 | } |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2620 | } |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2621 | return delta; |
| 2622 | } |
| 2623 | |
| 2624 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2625 | /* Group 8 extended opcodes (but BT/BTS/BTC/BTR only). */ |
| 2626 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2627 | UInt dis_Grp8_Imm ( UChar sorb, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2628 | Bool locked, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 2629 | Int delta, UChar modrm, |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2630 | Int am_sz, Int sz, UInt src_val, |
| 2631 | Bool* decode_OK ) |
| 2632 | { |
| 2633 | /* src_val denotes a d8. |
| 2634 | And delta on entry points at the modrm byte. */ |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 2635 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2636 | IRType ty = szToITy(sz); |
| 2637 | IRTemp t2 = newTemp(Ity_I32); |
| 2638 | IRTemp t2m = newTemp(Ity_I32); |
| 2639 | IRTemp t_addr = IRTemp_INVALID; |
| 2640 | HChar dis_buf[50]; |
| 2641 | UInt mask; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 2642 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2643 | /* we're optimists :-) */ |
| 2644 | *decode_OK = True; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 2645 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2646 | /* Limit src_val -- the bit offset -- to something within a word. |
| 2647 | The Intel docs say that literal offsets larger than a word are |
| 2648 | masked in this way. */ |
| 2649 | switch (sz) { |
| 2650 | case 2: src_val &= 15; break; |
| 2651 | case 4: src_val &= 31; break; |
| 2652 | default: *decode_OK = False; return delta; |
| 2653 | } |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2654 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2655 | /* Invent a mask suitable for the operation. */ |
| 2656 | switch (gregOfRM(modrm)) { |
| 2657 | case 4: /* BT */ mask = 0; break; |
| 2658 | case 5: /* BTS */ mask = 1 << src_val; break; |
| 2659 | case 6: /* BTR */ mask = ~(1 << src_val); break; |
| 2660 | case 7: /* BTC */ mask = 1 << src_val; break; |
| 2661 | /* If this needs to be extended, probably simplest to make a |
| 2662 | new function to handle the other cases (0 .. 3). The |
| 2663 | Intel docs do however not indicate any use for 0 .. 3, so |
| 2664 | we don't expect this to happen. */ |
| 2665 | default: *decode_OK = False; return delta; |
| 2666 | } |
| 2667 | |
| 2668 | /* Fetch the value to be tested and modified into t2, which is |
| 2669 | 32-bits wide regardless of sz. */ |
| 2670 | if (epartIsReg(modrm)) { |
| 2671 | vassert(am_sz == 1); |
sewardj | 5a8334e | 2005-03-13 19:52:45 +0000 | [diff] [blame] | 2672 | assign( t2, widenUto32(getIReg(sz, eregOfRM(modrm))) ); |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2673 | delta += (am_sz + 1); |
| 2674 | DIP("%s%c $0x%x, %s\n", nameGrp8(gregOfRM(modrm)), nameISize(sz), |
| 2675 | src_val, nameIReg(sz,eregOfRM(modrm))); |
| 2676 | } else { |
| 2677 | Int len; |
| 2678 | t_addr = disAMode ( &len, sorb, delta, dis_buf); |
| 2679 | delta += (len+1); |
| 2680 | assign( t2, widenUto32(loadLE(ty, mkexpr(t_addr))) ); |
| 2681 | DIP("%s%c $0x%x, %s\n", nameGrp8(gregOfRM(modrm)), nameISize(sz), |
| 2682 | src_val, dis_buf); |
| 2683 | } |
| 2684 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2685 | /* Compute the new value into t2m, if non-BT. */ |
| 2686 | switch (gregOfRM(modrm)) { |
| 2687 | case 4: /* BT */ |
| 2688 | break; |
| 2689 | case 5: /* BTS */ |
| 2690 | assign( t2m, binop(Iop_Or32, mkU32(mask), mkexpr(t2)) ); |
| 2691 | break; |
| 2692 | case 6: /* BTR */ |
| 2693 | assign( t2m, binop(Iop_And32, mkU32(mask), mkexpr(t2)) ); |
| 2694 | break; |
| 2695 | case 7: /* BTC */ |
| 2696 | assign( t2m, binop(Iop_Xor32, mkU32(mask), mkexpr(t2)) ); |
| 2697 | break; |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 2698 | default: |
| 2699 | /*NOTREACHED*/ /*the previous switch guards this*/ |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2700 | vassert(0); |
| 2701 | } |
| 2702 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2703 | /* Write the result back, if non-BT. If the CAS fails then we |
| 2704 | side-exit from the trace at this point, and so the flag state is |
| 2705 | not affected. This is of course as required. */ |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2706 | if (gregOfRM(modrm) != 4 /* BT */) { |
| 2707 | if (epartIsReg(modrm)) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2708 | putIReg(sz, eregOfRM(modrm), narrowTo(ty, mkexpr(t2m))); |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2709 | } else { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2710 | if (locked) { |
| 2711 | casLE( mkexpr(t_addr), |
| 2712 | narrowTo(ty, mkexpr(t2))/*expd*/, |
| 2713 | narrowTo(ty, mkexpr(t2m))/*new*/, |
| 2714 | guest_EIP_curr_instr ); |
| 2715 | } else { |
| 2716 | storeLE(mkexpr(t_addr), narrowTo(ty, mkexpr(t2m))); |
| 2717 | } |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2718 | } |
| 2719 | } |
| 2720 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2721 | /* Copy relevant bit from t2 into the carry flag. */ |
| 2722 | /* Flags: C=selected bit, O,S,Z,A,P undefined, so are set to zero. */ |
| 2723 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 2724 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 2725 | stmt( IRStmt_Put( |
| 2726 | OFFB_CC_DEP1, |
| 2727 | binop(Iop_And32, |
| 2728 | binop(Iop_Shr32, mkexpr(t2), mkU8(src_val)), |
| 2729 | mkU32(1)) |
| 2730 | )); |
| 2731 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 2732 | elimination of previous stores to this field work better. */ |
| 2733 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 2734 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 2735 | return delta; |
| 2736 | } |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2737 | |
| 2738 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2739 | /* Signed/unsigned widening multiply. Generate IR to multiply the |
| 2740 | value in EAX/AX/AL by the given IRTemp, and park the result in |
| 2741 | EDX:EAX/DX:AX/AX. |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2742 | */ |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2743 | static void codegen_mulL_A_D ( Int sz, Bool syned, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 2744 | IRTemp tmp, const HChar* tmp_txt ) |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2745 | { |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2746 | IRType ty = szToITy(sz); |
| 2747 | IRTemp t1 = newTemp(ty); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2748 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2749 | assign( t1, getIReg(sz, R_EAX) ); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2750 | |
| 2751 | switch (ty) { |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2752 | case Ity_I32: { |
| 2753 | IRTemp res64 = newTemp(Ity_I64); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2754 | IRTemp resHi = newTemp(Ity_I32); |
| 2755 | IRTemp resLo = newTemp(Ity_I32); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2756 | IROp mulOp = syned ? Iop_MullS32 : Iop_MullU32; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2757 | UInt tBaseOp = syned ? X86G_CC_OP_SMULB : X86G_CC_OP_UMULB; |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2758 | setFlags_MUL ( Ity_I32, t1, tmp, tBaseOp ); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2759 | assign( res64, binop(mulOp, mkexpr(t1), mkexpr(tmp)) ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2760 | assign( resHi, unop(Iop_64HIto32,mkexpr(res64))); |
| 2761 | assign( resLo, unop(Iop_64to32,mkexpr(res64))); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2762 | putIReg(4, R_EDX, mkexpr(resHi)); |
| 2763 | putIReg(4, R_EAX, mkexpr(resLo)); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2764 | break; |
| 2765 | } |
| 2766 | case Ity_I16: { |
| 2767 | IRTemp res32 = newTemp(Ity_I32); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2768 | IRTemp resHi = newTemp(Ity_I16); |
| 2769 | IRTemp resLo = newTemp(Ity_I16); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2770 | IROp mulOp = syned ? Iop_MullS16 : Iop_MullU16; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2771 | UInt tBaseOp = syned ? X86G_CC_OP_SMULB : X86G_CC_OP_UMULB; |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2772 | setFlags_MUL ( Ity_I16, t1, tmp, tBaseOp ); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2773 | assign( res32, binop(mulOp, mkexpr(t1), mkexpr(tmp)) ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2774 | assign( resHi, unop(Iop_32HIto16,mkexpr(res32))); |
| 2775 | assign( resLo, unop(Iop_32to16,mkexpr(res32))); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2776 | putIReg(2, R_EDX, mkexpr(resHi)); |
| 2777 | putIReg(2, R_EAX, mkexpr(resLo)); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2778 | break; |
| 2779 | } |
| 2780 | case Ity_I8: { |
| 2781 | IRTemp res16 = newTemp(Ity_I16); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2782 | IRTemp resHi = newTemp(Ity_I8); |
| 2783 | IRTemp resLo = newTemp(Ity_I8); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2784 | IROp mulOp = syned ? Iop_MullS8 : Iop_MullU8; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 2785 | UInt tBaseOp = syned ? X86G_CC_OP_SMULB : X86G_CC_OP_UMULB; |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2786 | setFlags_MUL ( Ity_I8, t1, tmp, tBaseOp ); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2787 | assign( res16, binop(mulOp, mkexpr(t1), mkexpr(tmp)) ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 2788 | assign( resHi, unop(Iop_16HIto8,mkexpr(res16))); |
| 2789 | assign( resLo, unop(Iop_16to8,mkexpr(res16))); |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 2790 | putIReg(2, R_EAX, mkexpr(res16)); |
| 2791 | break; |
| 2792 | } |
| 2793 | default: |
| 2794 | vpanic("codegen_mulL_A_D(x86)"); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2795 | } |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2796 | DIP("%s%c %s\n", syned ? "imul" : "mul", nameISize(sz), tmp_txt); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2797 | } |
| 2798 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2799 | |
| 2800 | /* Group 3 extended opcodes. */ |
| 2801 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2802 | UInt dis_Grp3 ( UChar sorb, Bool locked, Int sz, Int delta, Bool* decode_OK ) |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2803 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2804 | UInt d32; |
| 2805 | UChar modrm; |
| 2806 | HChar dis_buf[50]; |
| 2807 | Int len; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2808 | IRTemp addr; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2809 | IRType ty = szToITy(sz); |
| 2810 | IRTemp t1 = newTemp(ty); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2811 | IRTemp dst1, src, dst0; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2812 | |
| 2813 | *decode_OK = True; /* may change this later */ |
| 2814 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2815 | modrm = getIByte(delta); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2816 | |
| 2817 | if (locked && (gregOfRM(modrm) != 2 && gregOfRM(modrm) != 3)) { |
| 2818 | /* LOCK prefix only allowed with not and neg subopcodes */ |
| 2819 | *decode_OK = False; |
| 2820 | return delta; |
| 2821 | } |
| 2822 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2823 | if (epartIsReg(modrm)) { |
| 2824 | switch (gregOfRM(modrm)) { |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2825 | case 0: { /* TEST */ |
| 2826 | delta++; d32 = getUDisp(sz, delta); delta += sz; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2827 | dst1 = newTemp(ty); |
| 2828 | assign(dst1, binop(mkSizedOp(ty,Iop_And8), |
| 2829 | getIReg(sz,eregOfRM(modrm)), |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2830 | mkU(ty,d32))); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2831 | setFlags_DEP1( Iop_And8, dst1, ty ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2832 | DIP("test%c $0x%x, %s\n", nameISize(sz), d32, |
| 2833 | nameIReg(sz, eregOfRM(modrm))); |
| 2834 | break; |
| 2835 | } |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2836 | case 1: /* UNDEFINED */ |
| 2837 | /* The Intel docs imply this insn is undefined and binutils |
| 2838 | agrees. Unfortunately Core 2 will run it (with who |
| 2839 | knows what result?) sandpile.org reckons it's an alias |
| 2840 | for case 0. We play safe. */ |
| 2841 | *decode_OK = False; |
| 2842 | break; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2843 | case 2: /* NOT */ |
| 2844 | delta++; |
| 2845 | putIReg(sz, eregOfRM(modrm), |
| 2846 | unop(mkSizedOp(ty,Iop_Not8), |
| 2847 | getIReg(sz, eregOfRM(modrm)))); |
| 2848 | DIP("not%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm))); |
| 2849 | break; |
| 2850 | case 3: /* NEG */ |
| 2851 | delta++; |
| 2852 | dst0 = newTemp(ty); |
| 2853 | src = newTemp(ty); |
| 2854 | dst1 = newTemp(ty); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2855 | assign(dst0, mkU(ty,0)); |
sewardj | a511afc | 2004-07-29 22:26:03 +0000 | [diff] [blame] | 2856 | assign(src, getIReg(sz,eregOfRM(modrm))); |
sewardj | eb17e49 | 2007-08-25 23:07:44 +0000 | [diff] [blame] | 2857 | assign(dst1, binop(mkSizedOp(ty,Iop_Sub8), mkexpr(dst0), mkexpr(src))); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2858 | setFlags_DEP1_DEP2(Iop_Sub8, dst0, src, ty); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2859 | putIReg(sz, eregOfRM(modrm), mkexpr(dst1)); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2860 | DIP("neg%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm))); |
| 2861 | break; |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2862 | case 4: /* MUL (unsigned widening) */ |
| 2863 | delta++; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2864 | src = newTemp(ty); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2865 | assign(src, getIReg(sz,eregOfRM(modrm))); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2866 | codegen_mulL_A_D ( sz, False, src, nameIReg(sz,eregOfRM(modrm)) ); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 2867 | break; |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2868 | case 5: /* IMUL (signed widening) */ |
| 2869 | delta++; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2870 | src = newTemp(ty); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2871 | assign(src, getIReg(sz,eregOfRM(modrm))); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2872 | codegen_mulL_A_D ( sz, True, src, nameIReg(sz,eregOfRM(modrm)) ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2873 | break; |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 2874 | case 6: /* DIV */ |
| 2875 | delta++; |
| 2876 | assign( t1, getIReg(sz, eregOfRM(modrm)) ); |
| 2877 | codegen_div ( sz, t1, False ); |
| 2878 | DIP("div%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm))); |
| 2879 | break; |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 2880 | case 7: /* IDIV */ |
| 2881 | delta++; |
| 2882 | assign( t1, getIReg(sz, eregOfRM(modrm)) ); |
| 2883 | codegen_div ( sz, t1, True ); |
| 2884 | DIP("idiv%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm))); |
| 2885 | break; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2886 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2887 | /* This can't happen - gregOfRM should return 0 .. 7 only */ |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2888 | vpanic("Grp3(x86)"); |
| 2889 | } |
| 2890 | } else { |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2891 | addr = disAMode ( &len, sorb, delta, dis_buf ); |
| 2892 | t1 = newTemp(ty); |
| 2893 | delta += len; |
| 2894 | assign(t1, loadLE(ty,mkexpr(addr))); |
| 2895 | switch (gregOfRM(modrm)) { |
| 2896 | case 0: { /* TEST */ |
| 2897 | d32 = getUDisp(sz, delta); delta += sz; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2898 | dst1 = newTemp(ty); |
| 2899 | assign(dst1, binop(mkSizedOp(ty,Iop_And8), |
| 2900 | mkexpr(t1), mkU(ty,d32))); |
| 2901 | setFlags_DEP1( Iop_And8, dst1, ty ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2902 | DIP("test%c $0x%x, %s\n", nameISize(sz), d32, dis_buf); |
| 2903 | break; |
| 2904 | } |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2905 | case 1: /* UNDEFINED */ |
| 2906 | /* See comment above on R case */ |
| 2907 | *decode_OK = False; |
| 2908 | break; |
sewardj | 78fe791 | 2004-08-20 23:38:07 +0000 | [diff] [blame] | 2909 | case 2: /* NOT */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2910 | dst1 = newTemp(ty); |
| 2911 | assign(dst1, unop(mkSizedOp(ty,Iop_Not8), mkexpr(t1))); |
| 2912 | if (locked) { |
| 2913 | casLE( mkexpr(addr), mkexpr(t1)/*expd*/, mkexpr(dst1)/*new*/, |
| 2914 | guest_EIP_curr_instr ); |
| 2915 | } else { |
| 2916 | storeLE( mkexpr(addr), mkexpr(dst1) ); |
| 2917 | } |
sewardj | 78fe791 | 2004-08-20 23:38:07 +0000 | [diff] [blame] | 2918 | DIP("not%c %s\n", nameISize(sz), dis_buf); |
| 2919 | break; |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 2920 | case 3: /* NEG */ |
| 2921 | dst0 = newTemp(ty); |
| 2922 | src = newTemp(ty); |
| 2923 | dst1 = newTemp(ty); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 2924 | assign(dst0, mkU(ty,0)); |
sewardj | a511afc | 2004-07-29 22:26:03 +0000 | [diff] [blame] | 2925 | assign(src, mkexpr(t1)); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2926 | assign(dst1, binop(mkSizedOp(ty,Iop_Sub8), |
| 2927 | mkexpr(dst0), mkexpr(src))); |
| 2928 | if (locked) { |
| 2929 | casLE( mkexpr(addr), mkexpr(t1)/*expd*/, mkexpr(dst1)/*new*/, |
| 2930 | guest_EIP_curr_instr ); |
| 2931 | } else { |
| 2932 | storeLE( mkexpr(addr), mkexpr(dst1) ); |
| 2933 | } |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 2934 | setFlags_DEP1_DEP2(Iop_Sub8, dst0, src, ty); |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 2935 | DIP("neg%c %s\n", nameISize(sz), dis_buf); |
| 2936 | break; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2937 | case 4: /* MUL */ |
| 2938 | codegen_mulL_A_D ( sz, False, t1, dis_buf ); |
| 2939 | break; |
| 2940 | case 5: /* IMUL */ |
| 2941 | codegen_mulL_A_D ( sz, True, t1, dis_buf ); |
| 2942 | break; |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 2943 | case 6: /* DIV */ |
| 2944 | codegen_div ( sz, t1, False ); |
| 2945 | DIP("div%c %s\n", nameISize(sz), dis_buf); |
| 2946 | break; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 2947 | case 7: /* IDIV */ |
| 2948 | codegen_div ( sz, t1, True ); |
| 2949 | DIP("idiv%c %s\n", nameISize(sz), dis_buf); |
| 2950 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2951 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2952 | /* This can't happen - gregOfRM should return 0 .. 7 only */ |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2953 | vpanic("Grp3(x86)"); |
| 2954 | } |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 2955 | } |
| 2956 | return delta; |
| 2957 | } |
| 2958 | |
| 2959 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2960 | /* Group 4 extended opcodes. */ |
| 2961 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2962 | UInt dis_Grp4 ( UChar sorb, Bool locked, Int delta, Bool* decode_OK ) |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2963 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2964 | Int alen; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2965 | UChar modrm; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 2966 | HChar dis_buf[50]; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2967 | IRType ty = Ity_I8; |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 2968 | IRTemp t1 = newTemp(ty); |
| 2969 | IRTemp t2 = newTemp(ty); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2970 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2971 | *decode_OK = True; |
| 2972 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2973 | modrm = getIByte(delta); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2974 | |
| 2975 | if (locked && (gregOfRM(modrm) != 0 && gregOfRM(modrm) != 1)) { |
| 2976 | /* LOCK prefix only allowed with inc and dec subopcodes */ |
| 2977 | *decode_OK = False; |
| 2978 | return delta; |
| 2979 | } |
| 2980 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2981 | if (epartIsReg(modrm)) { |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2982 | assign(t1, getIReg(1, eregOfRM(modrm))); |
| 2983 | switch (gregOfRM(modrm)) { |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 2984 | case 0: /* INC */ |
| 2985 | assign(t2, binop(Iop_Add8, mkexpr(t1), mkU8(1))); |
| 2986 | putIReg(1, eregOfRM(modrm), mkexpr(t2)); |
| 2987 | setFlags_INC_DEC( True, t2, ty ); |
| 2988 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2989 | case 1: /* DEC */ |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2990 | assign(t2, binop(Iop_Sub8, mkexpr(t1), mkU8(1))); |
| 2991 | putIReg(1, eregOfRM(modrm), mkexpr(t2)); |
| 2992 | setFlags_INC_DEC( False, t2, ty ); |
| 2993 | break; |
| 2994 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 2995 | *decode_OK = False; |
| 2996 | return delta; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 2997 | } |
| 2998 | delta++; |
| 2999 | DIP("%sb %s\n", nameGrp4(gregOfRM(modrm)), |
| 3000 | nameIReg(1, eregOfRM(modrm))); |
| 3001 | } else { |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 3002 | IRTemp addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 3003 | assign( t1, loadLE(ty, mkexpr(addr)) ); |
| 3004 | switch (gregOfRM(modrm)) { |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 3005 | case 0: /* INC */ |
| 3006 | assign(t2, binop(Iop_Add8, mkexpr(t1), mkU8(1))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3007 | if (locked) { |
| 3008 | casLE( mkexpr(addr), mkexpr(t1)/*expd*/, mkexpr(t2)/*new*/, |
| 3009 | guest_EIP_curr_instr ); |
| 3010 | } else { |
| 3011 | storeLE( mkexpr(addr), mkexpr(t2) ); |
| 3012 | } |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 3013 | setFlags_INC_DEC( True, t2, ty ); |
| 3014 | break; |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 3015 | case 1: /* DEC */ |
| 3016 | assign(t2, binop(Iop_Sub8, mkexpr(t1), mkU8(1))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3017 | if (locked) { |
| 3018 | casLE( mkexpr(addr), mkexpr(t1)/*expd*/, mkexpr(t2)/*new*/, |
| 3019 | guest_EIP_curr_instr ); |
| 3020 | } else { |
| 3021 | storeLE( mkexpr(addr), mkexpr(t2) ); |
| 3022 | } |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 3023 | setFlags_INC_DEC( False, t2, ty ); |
| 3024 | break; |
| 3025 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 3026 | *decode_OK = False; |
| 3027 | return delta; |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 3028 | } |
| 3029 | delta += alen; |
| 3030 | DIP("%sb %s\n", nameGrp4(gregOfRM(modrm)), dis_buf); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3031 | } |
| 3032 | return delta; |
| 3033 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3034 | |
| 3035 | |
| 3036 | /* Group 5 extended opcodes. */ |
| 3037 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3038 | UInt dis_Grp5 ( UChar sorb, Bool locked, Int sz, Int delta, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3039 | /*MOD*/DisResult* dres, /*OUT*/Bool* decode_OK ) |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3040 | { |
| 3041 | Int len; |
| 3042 | UChar modrm; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 3043 | HChar dis_buf[50]; |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 3044 | IRTemp addr = IRTemp_INVALID; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3045 | IRType ty = szToITy(sz); |
| 3046 | IRTemp t1 = newTemp(ty); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 3047 | IRTemp t2 = IRTemp_INVALID; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3048 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 3049 | *decode_OK = True; |
| 3050 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3051 | modrm = getIByte(delta); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3052 | |
| 3053 | if (locked && (gregOfRM(modrm) != 0 && gregOfRM(modrm) != 1)) { |
| 3054 | /* LOCK prefix only allowed with inc and dec subopcodes */ |
| 3055 | *decode_OK = False; |
| 3056 | return delta; |
| 3057 | } |
| 3058 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3059 | if (epartIsReg(modrm)) { |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 3060 | assign(t1, getIReg(sz,eregOfRM(modrm))); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3061 | switch (gregOfRM(modrm)) { |
sewardj | 59ff5d4 | 2005-10-05 10:39:58 +0000 | [diff] [blame] | 3062 | case 0: /* INC */ |
| 3063 | vassert(sz == 2 || sz == 4); |
| 3064 | t2 = newTemp(ty); |
| 3065 | assign(t2, binop(mkSizedOp(ty,Iop_Add8), |
| 3066 | mkexpr(t1), mkU(ty,1))); |
| 3067 | setFlags_INC_DEC( True, t2, ty ); |
| 3068 | putIReg(sz,eregOfRM(modrm),mkexpr(t2)); |
| 3069 | break; |
| 3070 | case 1: /* DEC */ |
| 3071 | vassert(sz == 2 || sz == 4); |
| 3072 | t2 = newTemp(ty); |
| 3073 | assign(t2, binop(mkSizedOp(ty,Iop_Sub8), |
| 3074 | mkexpr(t1), mkU(ty,1))); |
| 3075 | setFlags_INC_DEC( False, t2, ty ); |
| 3076 | putIReg(sz,eregOfRM(modrm),mkexpr(t2)); |
| 3077 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3078 | case 2: /* call Ev */ |
| 3079 | vassert(sz == 4); |
| 3080 | t2 = newTemp(Ity_I32); |
| 3081 | assign(t2, binop(Iop_Sub32, getIReg(4,R_ESP), mkU32(4))); |
| 3082 | putIReg(4, R_ESP, mkexpr(t2)); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 3083 | storeLE( mkexpr(t2), mkU32(guest_EIP_bbstart+delta+1)); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3084 | jmp_treg(dres, Ijk_Call, t1); |
| 3085 | vassert(dres->whatNext == Dis_StopHere); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3086 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3087 | case 4: /* jmp Ev */ |
| 3088 | vassert(sz == 4); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3089 | jmp_treg(dres, Ijk_Boring, t1); |
| 3090 | vassert(dres->whatNext == Dis_StopHere); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3091 | break; |
sewardj | 2890582 | 2006-11-18 22:56:46 +0000 | [diff] [blame] | 3092 | case 6: /* PUSH Ev */ |
| 3093 | vassert(sz == 4 || sz == 2); |
| 3094 | t2 = newTemp(Ity_I32); |
| 3095 | assign( t2, binop(Iop_Sub32,getIReg(4,R_ESP),mkU32(sz)) ); |
| 3096 | putIReg(4, R_ESP, mkexpr(t2) ); |
| 3097 | storeLE( mkexpr(t2), mkexpr(t1) ); |
| 3098 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3099 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 3100 | *decode_OK = False; |
| 3101 | return delta; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3102 | } |
| 3103 | delta++; |
| 3104 | DIP("%s%c %s\n", nameGrp5(gregOfRM(modrm)), |
| 3105 | nameISize(sz), nameIReg(sz, eregOfRM(modrm))); |
| 3106 | } else { |
| 3107 | addr = disAMode ( &len, sorb, delta, dis_buf ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 3108 | assign(t1, loadLE(ty,mkexpr(addr))); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3109 | switch (gregOfRM(modrm)) { |
| 3110 | case 0: /* INC */ |
| 3111 | t2 = newTemp(ty); |
| 3112 | assign(t2, binop(mkSizedOp(ty,Iop_Add8), |
| 3113 | mkexpr(t1), mkU(ty,1))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3114 | if (locked) { |
| 3115 | casLE( mkexpr(addr), |
| 3116 | mkexpr(t1), mkexpr(t2), guest_EIP_curr_instr ); |
| 3117 | } else { |
| 3118 | storeLE(mkexpr(addr),mkexpr(t2)); |
| 3119 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3120 | setFlags_INC_DEC( True, t2, ty ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3121 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3122 | case 1: /* DEC */ |
| 3123 | t2 = newTemp(ty); |
| 3124 | assign(t2, binop(mkSizedOp(ty,Iop_Sub8), |
| 3125 | mkexpr(t1), mkU(ty,1))); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 3126 | if (locked) { |
| 3127 | casLE( mkexpr(addr), |
| 3128 | mkexpr(t1), mkexpr(t2), guest_EIP_curr_instr ); |
| 3129 | } else { |
| 3130 | storeLE(mkexpr(addr),mkexpr(t2)); |
| 3131 | } |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3132 | setFlags_INC_DEC( False, t2, ty ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 3133 | break; |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 3134 | case 2: /* call Ev */ |
| 3135 | vassert(sz == 4); |
| 3136 | t2 = newTemp(Ity_I32); |
| 3137 | assign(t2, binop(Iop_Sub32, getIReg(4,R_ESP), mkU32(4))); |
| 3138 | putIReg(4, R_ESP, mkexpr(t2)); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 3139 | storeLE( mkexpr(t2), mkU32(guest_EIP_bbstart+delta+len)); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3140 | jmp_treg(dres, Ijk_Call, t1); |
| 3141 | vassert(dres->whatNext == Dis_StopHere); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 3142 | break; |
| 3143 | case 4: /* JMP Ev */ |
| 3144 | vassert(sz == 4); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3145 | jmp_treg(dres, Ijk_Boring, t1); |
| 3146 | vassert(dres->whatNext == Dis_StopHere); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 3147 | break; |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 3148 | case 6: /* PUSH Ev */ |
| 3149 | vassert(sz == 4 || sz == 2); |
| 3150 | t2 = newTemp(Ity_I32); |
| 3151 | assign( t2, binop(Iop_Sub32,getIReg(4,R_ESP),mkU32(sz)) ); |
| 3152 | putIReg(4, R_ESP, mkexpr(t2) ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 3153 | storeLE( mkexpr(t2), mkexpr(t1) ); |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 3154 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3155 | default: |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 3156 | *decode_OK = False; |
| 3157 | return delta; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 3158 | } |
| 3159 | delta += len; |
| 3160 | DIP("%s%c %s\n", nameGrp5(gregOfRM(modrm)), |
| 3161 | nameISize(sz), dis_buf); |
| 3162 | } |
| 3163 | return delta; |
| 3164 | } |
| 3165 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 3166 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3167 | /*------------------------------------------------------------*/ |
| 3168 | /*--- Disassembling string ops (including REP prefixes) ---*/ |
| 3169 | /*------------------------------------------------------------*/ |
| 3170 | |
| 3171 | /* Code shared by all the string ops */ |
| 3172 | static |
| 3173 | void dis_string_op_increment(Int sz, Int t_inc) |
| 3174 | { |
| 3175 | if (sz == 4 || sz == 2) { |
| 3176 | assign( t_inc, |
| 3177 | binop(Iop_Shl32, IRExpr_Get( OFFB_DFLAG, Ity_I32 ), |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 3178 | mkU8(sz/2) ) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3179 | } else { |
| 3180 | assign( t_inc, |
| 3181 | IRExpr_Get( OFFB_DFLAG, Ity_I32 ) ); |
| 3182 | } |
| 3183 | } |
| 3184 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3185 | static |
| 3186 | void dis_string_op( void (*dis_OP)( Int, IRTemp ), |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 3187 | Int sz, const HChar* name, UChar sorb ) |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3188 | { |
| 3189 | IRTemp t_inc = newTemp(Ity_I32); |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 3190 | vassert(sorb == 0); /* hmm. so what was the point of passing it in? */ |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3191 | dis_string_op_increment(sz, t_inc); |
| 3192 | dis_OP( sz, t_inc ); |
| 3193 | DIP("%s%c\n", name, nameISize(sz)); |
| 3194 | } |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3195 | |
| 3196 | static |
| 3197 | void dis_MOVS ( Int sz, IRTemp t_inc ) |
| 3198 | { |
| 3199 | IRType ty = szToITy(sz); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3200 | IRTemp td = newTemp(Ity_I32); /* EDI */ |
| 3201 | IRTemp ts = newTemp(Ity_I32); /* ESI */ |
| 3202 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3203 | assign( td, getIReg(4, R_EDI) ); |
| 3204 | assign( ts, getIReg(4, R_ESI) ); |
| 3205 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3206 | storeLE( mkexpr(td), loadLE(ty,mkexpr(ts)) ); |
| 3207 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3208 | putIReg( 4, R_EDI, binop(Iop_Add32, mkexpr(td), mkexpr(t_inc)) ); |
| 3209 | putIReg( 4, R_ESI, binop(Iop_Add32, mkexpr(ts), mkexpr(t_inc)) ); |
| 3210 | } |
| 3211 | |
sewardj | 10ca4eb | 2005-05-30 11:19:54 +0000 | [diff] [blame] | 3212 | static |
| 3213 | void dis_LODS ( Int sz, IRTemp t_inc ) |
| 3214 | { |
| 3215 | IRType ty = szToITy(sz); |
| 3216 | IRTemp ts = newTemp(Ity_I32); /* ESI */ |
| 3217 | |
| 3218 | assign( ts, getIReg(4, R_ESI) ); |
| 3219 | |
| 3220 | putIReg( sz, R_EAX, loadLE(ty, mkexpr(ts)) ); |
| 3221 | |
| 3222 | putIReg( 4, R_ESI, binop(Iop_Add32, mkexpr(ts), mkexpr(t_inc)) ); |
| 3223 | } |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3224 | |
| 3225 | static |
| 3226 | void dis_STOS ( Int sz, IRTemp t_inc ) |
| 3227 | { |
| 3228 | IRType ty = szToITy(sz); |
| 3229 | IRTemp ta = newTemp(ty); /* EAX */ |
| 3230 | IRTemp td = newTemp(Ity_I32); /* EDI */ |
| 3231 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3232 | assign( ta, getIReg(sz, R_EAX) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3233 | assign( td, getIReg(4, R_EDI) ); |
| 3234 | |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 3235 | storeLE( mkexpr(td), mkexpr(ta) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3236 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3237 | putIReg( 4, R_EDI, binop(Iop_Add32, mkexpr(td), mkexpr(t_inc)) ); |
| 3238 | } |
| 3239 | |
| 3240 | static |
| 3241 | void dis_CMPS ( Int sz, IRTemp t_inc ) |
| 3242 | { |
| 3243 | IRType ty = szToITy(sz); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 3244 | IRTemp tdv = newTemp(ty); /* (EDI) */ |
| 3245 | IRTemp tsv = newTemp(ty); /* (ESI) */ |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3246 | IRTemp td = newTemp(Ity_I32); /* EDI */ |
| 3247 | IRTemp ts = newTemp(Ity_I32); /* ESI */ |
| 3248 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3249 | assign( td, getIReg(4, R_EDI) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3250 | assign( ts, getIReg(4, R_ESI) ); |
| 3251 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3252 | assign( tdv, loadLE(ty,mkexpr(td)) ); |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 3253 | assign( tsv, loadLE(ty,mkexpr(ts)) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3254 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3255 | setFlags_DEP1_DEP2 ( Iop_Sub8, tsv, tdv, ty ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3256 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3257 | putIReg(4, R_EDI, binop(Iop_Add32, mkexpr(td), mkexpr(t_inc)) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3258 | putIReg(4, R_ESI, binop(Iop_Add32, mkexpr(ts), mkexpr(t_inc)) ); |
| 3259 | } |
| 3260 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3261 | static |
| 3262 | void dis_SCAS ( Int sz, IRTemp t_inc ) |
| 3263 | { |
| 3264 | IRType ty = szToITy(sz); |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 3265 | IRTemp ta = newTemp(ty); /* EAX */ |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3266 | IRTemp td = newTemp(Ity_I32); /* EDI */ |
| 3267 | IRTemp tdv = newTemp(ty); /* (EDI) */ |
| 3268 | |
sewardj | b9c5cf6 | 2004-08-24 15:10:38 +0000 | [diff] [blame] | 3269 | assign( ta, getIReg(sz, R_EAX) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3270 | assign( td, getIReg(4, R_EDI) ); |
| 3271 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3272 | assign( tdv, loadLE(ty,mkexpr(td)) ); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3273 | setFlags_DEP1_DEP2 ( Iop_Sub8, ta, tdv, ty ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3274 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3275 | putIReg(4, R_EDI, binop(Iop_Add32, mkexpr(td), mkexpr(t_inc)) ); |
| 3276 | } |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 3277 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3278 | |
| 3279 | /* Wrap the appropriate string op inside a REP/REPE/REPNE. |
| 3280 | We assume the insn is the last one in the basic block, and so emit a jump |
| 3281 | to the next insn, rather than just falling through. */ |
| 3282 | static |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3283 | void dis_REP_op ( /*MOD*/DisResult* dres, |
| 3284 | X86Condcode cond, |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3285 | void (*dis_OP)(Int, IRTemp), |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 3286 | Int sz, Addr32 eip, Addr32 eip_next, const HChar* name ) |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3287 | { |
| 3288 | IRTemp t_inc = newTemp(Ity_I32); |
| 3289 | IRTemp tc = newTemp(Ity_I32); /* ECX */ |
| 3290 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3291 | assign( tc, getIReg(4,R_ECX) ); |
| 3292 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3293 | stmt( IRStmt_Exit( binop(Iop_CmpEQ32,mkexpr(tc),mkU32(0)), |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3294 | Ijk_Boring, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3295 | IRConst_U32(eip_next), OFFB_EIP ) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3296 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3297 | putIReg(4, R_ECX, binop(Iop_Sub32, mkexpr(tc), mkU32(1)) ); |
| 3298 | |
| 3299 | dis_string_op_increment(sz, t_inc); |
| 3300 | dis_OP (sz, t_inc); |
| 3301 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 3302 | if (cond == X86CondAlways) { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3303 | jmp_lit(dres, Ijk_Boring, eip); |
| 3304 | vassert(dres->whatNext == Dis_StopHere); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3305 | } else { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 3306 | stmt( IRStmt_Exit( mk_x86g_calculate_condition(cond), |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3307 | Ijk_Boring, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 3308 | IRConst_U32(eip), OFFB_EIP ) ); |
| 3309 | jmp_lit(dres, Ijk_Boring, eip_next); |
| 3310 | vassert(dres->whatNext == Dis_StopHere); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3311 | } |
| 3312 | DIP("%s%c\n", name, nameISize(sz)); |
| 3313 | } |
| 3314 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 3315 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 3316 | /*------------------------------------------------------------*/ |
| 3317 | /*--- Arithmetic, etc. ---*/ |
| 3318 | /*------------------------------------------------------------*/ |
| 3319 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3320 | /* IMUL E, G. Supplied eip points to the modR/M byte. */ |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3321 | static |
| 3322 | UInt dis_mul_E_G ( UChar sorb, |
| 3323 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 3324 | Int delta0 ) |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3325 | { |
sewardj | 71a6536 | 2004-07-28 01:48:34 +0000 | [diff] [blame] | 3326 | Int alen; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 3327 | HChar dis_buf[50]; |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3328 | UChar rm = getIByte(delta0); |
| 3329 | IRType ty = szToITy(size); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 3330 | IRTemp te = newTemp(ty); |
| 3331 | IRTemp tg = newTemp(ty); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3332 | IRTemp resLo = newTemp(ty); |
sewardj | 71a6536 | 2004-07-28 01:48:34 +0000 | [diff] [blame] | 3333 | |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3334 | assign( tg, getIReg(size, gregOfRM(rm)) ); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3335 | if (epartIsReg(rm)) { |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3336 | assign( te, getIReg(size, eregOfRM(rm)) ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3337 | } else { |
| 3338 | IRTemp addr = disAMode( &alen, sorb, delta0, dis_buf ); |
| 3339 | assign( te, loadLE(ty,mkexpr(addr)) ); |
| 3340 | } |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3341 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 3342 | setFlags_MUL ( ty, te, tg, X86G_CC_OP_SMULB ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3343 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3344 | assign( resLo, binop( mkSizedOp(ty, Iop_Mul8), mkexpr(te), mkexpr(tg) ) ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3345 | |
| 3346 | putIReg(size, gregOfRM(rm), mkexpr(resLo) ); |
| 3347 | |
| 3348 | if (epartIsReg(rm)) { |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3349 | DIP("imul%c %s, %s\n", nameISize(size), |
| 3350 | nameIReg(size,eregOfRM(rm)), |
| 3351 | nameIReg(size,gregOfRM(rm))); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3352 | return 1+delta0; |
| 3353 | } else { |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3354 | DIP("imul%c %s, %s\n", nameISize(size), |
| 3355 | dis_buf, nameIReg(size,gregOfRM(rm))); |
sewardj | 71a6536 | 2004-07-28 01:48:34 +0000 | [diff] [blame] | 3356 | return alen+delta0; |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 3357 | } |
| 3358 | } |
| 3359 | |
| 3360 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3361 | /* IMUL I * E -> G. Supplied eip points to the modR/M byte. */ |
| 3362 | static |
| 3363 | UInt dis_imul_I_E_G ( UChar sorb, |
| 3364 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 3365 | Int delta, |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3366 | Int litsize ) |
| 3367 | { |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 3368 | Int d32, alen; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 3369 | HChar dis_buf[50]; |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 3370 | UChar rm = getIByte(delta); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3371 | IRType ty = szToITy(size); |
| 3372 | IRTemp te = newTemp(ty); |
| 3373 | IRTemp tl = newTemp(ty); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3374 | IRTemp resLo = newTemp(ty); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3375 | |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 3376 | vassert(size == 1 || size == 2 || size == 4); |
| 3377 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3378 | if (epartIsReg(rm)) { |
| 3379 | assign(te, getIReg(size, eregOfRM(rm))); |
| 3380 | delta++; |
| 3381 | } else { |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 3382 | IRTemp addr = disAMode( &alen, sorb, delta, dis_buf ); |
| 3383 | assign(te, loadLE(ty, mkexpr(addr))); |
| 3384 | delta += alen; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3385 | } |
| 3386 | d32 = getSDisp(litsize,delta); |
| 3387 | delta += litsize; |
| 3388 | |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 3389 | if (size == 1) d32 &= 0xFF; |
| 3390 | if (size == 2) d32 &= 0xFFFF; |
| 3391 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3392 | assign(tl, mkU(ty,d32)); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3393 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3394 | assign( resLo, binop( mkSizedOp(ty, Iop_Mul8), mkexpr(te), mkexpr(tl) )); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3395 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 3396 | setFlags_MUL ( ty, te, tl, X86G_CC_OP_SMULB ); |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3397 | |
| 3398 | putIReg(size, gregOfRM(rm), mkexpr(resLo)); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3399 | |
| 3400 | DIP("imul %d, %s, %s\n", d32, |
| 3401 | ( epartIsReg(rm) ? nameIReg(size,eregOfRM(rm)) : dis_buf ), |
| 3402 | nameIReg(size,gregOfRM(rm)) ); |
| 3403 | return delta; |
sewardj | 948d48b | 2004-11-05 19:49:09 +0000 | [diff] [blame] | 3404 | } |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 3405 | |
| 3406 | |
sewardj | 9a660ea | 2010-07-29 11:34:38 +0000 | [diff] [blame] | 3407 | /* Generate an IR sequence to do a count-leading-zeroes operation on |
| 3408 | the supplied IRTemp, and return a new IRTemp holding the result. |
| 3409 | 'ty' may be Ity_I16 or Ity_I32 only. In the case where the |
| 3410 | argument is zero, return the number of bits in the word (the |
| 3411 | natural semantics). */ |
| 3412 | static IRTemp gen_LZCNT ( IRType ty, IRTemp src ) |
| 3413 | { |
| 3414 | vassert(ty == Ity_I32 || ty == Ity_I16); |
| 3415 | |
| 3416 | IRTemp src32 = newTemp(Ity_I32); |
| 3417 | assign(src32, widenUto32( mkexpr(src) )); |
| 3418 | |
| 3419 | IRTemp src32x = newTemp(Ity_I32); |
| 3420 | assign(src32x, |
| 3421 | binop(Iop_Shl32, mkexpr(src32), |
| 3422 | mkU8(32 - 8 * sizeofIRType(ty)))); |
| 3423 | |
| 3424 | // Clz32 has undefined semantics when its input is zero, so |
| 3425 | // special-case around that. |
| 3426 | IRTemp res32 = newTemp(Ity_I32); |
| 3427 | assign(res32, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 3428 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 3429 | binop(Iop_CmpEQ32, mkexpr(src32x), mkU32(0)), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 3430 | mkU32(8 * sizeofIRType(ty)), |
| 3431 | unop(Iop_Clz32, mkexpr(src32x)) |
sewardj | 9a660ea | 2010-07-29 11:34:38 +0000 | [diff] [blame] | 3432 | )); |
| 3433 | |
| 3434 | IRTemp res = newTemp(ty); |
| 3435 | assign(res, narrowTo(ty, mkexpr(res32))); |
| 3436 | return res; |
| 3437 | } |
| 3438 | |
| 3439 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3440 | /*------------------------------------------------------------*/ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 3441 | /*--- ---*/ |
| 3442 | /*--- x87 FLOATING POINT INSTRUCTIONS ---*/ |
| 3443 | /*--- ---*/ |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3444 | /*------------------------------------------------------------*/ |
| 3445 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3446 | /* --- Helper functions for dealing with the register stack. --- */ |
| 3447 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3448 | /* --- Set the emulation-warning pseudo-register. --- */ |
| 3449 | |
| 3450 | static void put_emwarn ( IRExpr* e /* :: Ity_I32 */ ) |
| 3451 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3452 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 3453 | stmt( IRStmt_Put( OFFB_EMNOTE, e ) ); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3454 | } |
| 3455 | |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 3456 | /* --- Produce an IRExpr* denoting a 64-bit QNaN. --- */ |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3457 | |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 3458 | static IRExpr* mkQNaN64 ( void ) |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3459 | { |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 3460 | /* QNaN is 0 2047 1 0(51times) |
| 3461 | == 0b 11111111111b 1 0(51times) |
| 3462 | == 0x7FF8 0000 0000 0000 |
| 3463 | */ |
| 3464 | return IRExpr_Const(IRConst_F64i(0x7FF8000000000000ULL)); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3465 | } |
| 3466 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3467 | /* --------- Get/put the top-of-stack pointer. --------- */ |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3468 | |
| 3469 | static IRExpr* get_ftop ( void ) |
| 3470 | { |
| 3471 | return IRExpr_Get( OFFB_FTOP, Ity_I32 ); |
| 3472 | } |
| 3473 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3474 | static void put_ftop ( IRExpr* e ) |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3475 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3476 | vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3477 | stmt( IRStmt_Put( OFFB_FTOP, e ) ); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3478 | } |
| 3479 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3480 | /* --------- Get/put the C3210 bits. --------- */ |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3481 | |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 3482 | static IRExpr* get_C3210 ( void ) |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3483 | { |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 3484 | return IRExpr_Get( OFFB_FC3210, Ity_I32 ); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3485 | } |
| 3486 | |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 3487 | static void put_C3210 ( IRExpr* e ) |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3488 | { |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 3489 | stmt( IRStmt_Put( OFFB_FC3210, e ) ); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3490 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3491 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3492 | /* --------- Get/put the FPU rounding mode. --------- */ |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3493 | static IRExpr* /* :: Ity_I32 */ get_fpround ( void ) |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3494 | { |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3495 | return IRExpr_Get( OFFB_FPROUND, Ity_I32 ); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3496 | } |
| 3497 | |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3498 | static void put_fpround ( IRExpr* /* :: Ity_I32 */ e ) |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3499 | { |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3500 | stmt( IRStmt_Put( OFFB_FPROUND, e ) ); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3501 | } |
| 3502 | |
| 3503 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 3504 | /* --------- Synthesise a 2-bit FPU rounding mode. --------- */ |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3505 | /* Produces a value in 0 .. 3, which is encoded as per the type |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3506 | IRRoundingMode. Since the guest_FPROUND value is also encoded as |
| 3507 | per IRRoundingMode, we merely need to get it and mask it for |
| 3508 | safety. |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3509 | */ |
| 3510 | static IRExpr* /* :: Ity_I32 */ get_roundingmode ( void ) |
| 3511 | { |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 3512 | return binop( Iop_And32, get_fpround(), mkU32(3) ); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3513 | } |
| 3514 | |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3515 | static IRExpr* /* :: Ity_I32 */ get_FAKE_roundingmode ( void ) |
| 3516 | { |
| 3517 | return mkU32(Irrm_NEAREST); |
| 3518 | } |
| 3519 | |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 3520 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3521 | /* --------- Get/set FP register tag bytes. --------- */ |
| 3522 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3523 | /* Given i, and some expression e, generate 'ST_TAG(i) = e'. */ |
| 3524 | |
| 3525 | static void put_ST_TAG ( Int i, IRExpr* value ) |
| 3526 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3527 | IRRegArray* descr; |
| 3528 | vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_I8); |
| 3529 | descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 ); |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 3530 | stmt( IRStmt_PutI( mkIRPutI(descr, get_ftop(), i, value) ) ); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3531 | } |
| 3532 | |
| 3533 | /* Given i, generate an expression yielding 'ST_TAG(i)'. This will be |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3534 | zero to indicate "Empty" and nonzero to indicate "NonEmpty". */ |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3535 | |
| 3536 | static IRExpr* get_ST_TAG ( Int i ) |
| 3537 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3538 | IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 ); |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3539 | return IRExpr_GetI( descr, get_ftop(), i ); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3540 | } |
| 3541 | |
| 3542 | |
| 3543 | /* --------- Get/set FP registers. --------- */ |
| 3544 | |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3545 | /* Given i, and some expression e, emit 'ST(i) = e' and set the |
| 3546 | register's tag to indicate the register is full. The previous |
| 3547 | state of the register is not checked. */ |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3548 | |
| 3549 | static void put_ST_UNCHECKED ( Int i, IRExpr* value ) |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3550 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3551 | IRRegArray* descr; |
| 3552 | vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_F64); |
| 3553 | descr = mkIRRegArray( OFFB_FPREGS, Ity_F64, 8 ); |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 3554 | stmt( IRStmt_PutI( mkIRPutI(descr, get_ftop(), i, value) ) ); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3555 | /* Mark the register as in-use. */ |
| 3556 | put_ST_TAG(i, mkU8(1)); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3557 | } |
| 3558 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3559 | /* Given i, and some expression e, emit |
| 3560 | ST(i) = is_full(i) ? NaN : e |
| 3561 | and set the tag accordingly. |
| 3562 | */ |
| 3563 | |
| 3564 | static void put_ST ( Int i, IRExpr* value ) |
| 3565 | { |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 3566 | put_ST_UNCHECKED( |
| 3567 | i, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 3568 | IRExpr_ITE( binop(Iop_CmpNE8, get_ST_TAG(i), mkU8(0)), |
| 3569 | /* non-0 means full */ |
| 3570 | mkQNaN64(), |
| 3571 | /* 0 means empty */ |
| 3572 | value |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 3573 | ) |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3574 | ); |
| 3575 | } |
| 3576 | |
| 3577 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3578 | /* Given i, generate an expression yielding 'ST(i)'. */ |
| 3579 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3580 | static IRExpr* get_ST_UNCHECKED ( Int i ) |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3581 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 3582 | IRRegArray* descr = mkIRRegArray( OFFB_FPREGS, Ity_F64, 8 ); |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3583 | return IRExpr_GetI( descr, get_ftop(), i ); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3584 | } |
| 3585 | |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 3586 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3587 | /* Given i, generate an expression yielding |
| 3588 | is_full(i) ? ST(i) : NaN |
| 3589 | */ |
| 3590 | |
| 3591 | static IRExpr* get_ST ( Int i ) |
| 3592 | { |
| 3593 | return |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 3594 | IRExpr_ITE( binop(Iop_CmpNE8, get_ST_TAG(i), mkU8(0)), |
| 3595 | /* non-0 means full */ |
| 3596 | get_ST_UNCHECKED(i), |
| 3597 | /* 0 means empty */ |
| 3598 | mkQNaN64()); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3599 | } |
| 3600 | |
| 3601 | |
sewardj | e9c51c9 | 2014-04-30 22:50:34 +0000 | [diff] [blame] | 3602 | /* Given i, and some expression e, and a condition cond, generate IR |
| 3603 | which has the same effect as put_ST(i,e) when cond is true and has |
| 3604 | no effect when cond is false. Given the lack of proper |
| 3605 | if-then-else in the IR, this is pretty tricky. |
| 3606 | */ |
| 3607 | |
| 3608 | static void maybe_put_ST ( IRTemp cond, Int i, IRExpr* value ) |
| 3609 | { |
| 3610 | // new_tag = if cond then FULL else old_tag |
| 3611 | // new_val = if cond then (if old_tag==FULL then NaN else val) |
| 3612 | // else old_val |
| 3613 | |
| 3614 | IRTemp old_tag = newTemp(Ity_I8); |
| 3615 | assign(old_tag, get_ST_TAG(i)); |
| 3616 | IRTemp new_tag = newTemp(Ity_I8); |
| 3617 | assign(new_tag, |
| 3618 | IRExpr_ITE(mkexpr(cond), mkU8(1)/*FULL*/, mkexpr(old_tag))); |
| 3619 | |
| 3620 | IRTemp old_val = newTemp(Ity_F64); |
| 3621 | assign(old_val, get_ST_UNCHECKED(i)); |
| 3622 | IRTemp new_val = newTemp(Ity_F64); |
| 3623 | assign(new_val, |
| 3624 | IRExpr_ITE(mkexpr(cond), |
| 3625 | IRExpr_ITE(binop(Iop_CmpNE8, mkexpr(old_tag), mkU8(0)), |
| 3626 | /* non-0 means full */ |
| 3627 | mkQNaN64(), |
| 3628 | /* 0 means empty */ |
| 3629 | value), |
| 3630 | mkexpr(old_val))); |
| 3631 | |
| 3632 | put_ST_UNCHECKED(i, mkexpr(new_val)); |
| 3633 | // put_ST_UNCHECKED incorrectly sets tag(i) to always be FULL. So |
| 3634 | // now set it to new_tag instead. |
| 3635 | put_ST_TAG(i, mkexpr(new_tag)); |
| 3636 | } |
| 3637 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3638 | /* Adjust FTOP downwards by one register. */ |
| 3639 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3640 | static void fp_push ( void ) |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3641 | { |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3642 | put_ftop( binop(Iop_Sub32, get_ftop(), mkU32(1)) ); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3643 | } |
| 3644 | |
sewardj | e9c51c9 | 2014-04-30 22:50:34 +0000 | [diff] [blame] | 3645 | /* Adjust FTOP downwards by one register when COND is 1:I1. Else |
| 3646 | don't change it. */ |
| 3647 | |
| 3648 | static void maybe_fp_push ( IRTemp cond ) |
| 3649 | { |
| 3650 | put_ftop( binop(Iop_Sub32, get_ftop(), unop(Iop_1Uto32,mkexpr(cond))) ); |
| 3651 | } |
| 3652 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3653 | /* Adjust FTOP upwards by one register, and mark the vacated register |
| 3654 | as empty. */ |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3655 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3656 | static void fp_pop ( void ) |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3657 | { |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3658 | put_ST_TAG(0, mkU8(0)); |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 3659 | put_ftop( binop(Iop_Add32, get_ftop(), mkU32(1)) ); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3660 | } |
| 3661 | |
sewardj | e9c51c9 | 2014-04-30 22:50:34 +0000 | [diff] [blame] | 3662 | /* Set the C2 bit of the FPU status register to e[0]. Assumes that |
| 3663 | e[31:1] == 0. |
| 3664 | */ |
| 3665 | static void set_C2 ( IRExpr* e ) |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 3666 | { |
sewardj | e9c51c9 | 2014-04-30 22:50:34 +0000 | [diff] [blame] | 3667 | IRExpr* cleared = binop(Iop_And32, get_C3210(), mkU32(~X86G_FC_MASK_C2)); |
| 3668 | put_C3210( binop(Iop_Or32, |
| 3669 | cleared, |
| 3670 | binop(Iop_Shl32, e, mkU8(X86G_FC_SHIFT_C2))) ); |
| 3671 | } |
| 3672 | |
| 3673 | /* Generate code to check that abs(d64) < 2^63 and is finite. This is |
| 3674 | used to do the range checks for FSIN, FCOS, FSINCOS and FPTAN. The |
| 3675 | test is simple, but the derivation of it is not so simple. |
| 3676 | |
| 3677 | The exponent field for an IEEE754 double is 11 bits. That means it |
| 3678 | can take values 0 through 0x7FF. If the exponent has value 0x7FF, |
| 3679 | the number is either a NaN or an Infinity and so is not finite. |
| 3680 | Furthermore, a finite value of exactly 2^63 is the smallest value |
| 3681 | that has exponent value 0x43E. Hence, what we need to do is |
| 3682 | extract the exponent, ignoring the sign bit and mantissa, and check |
| 3683 | it is < 0x43E, or <= 0x43D. |
| 3684 | |
| 3685 | To make this easily applicable to 32- and 64-bit targets, a |
| 3686 | roundabout approach is used. First the number is converted to I64, |
| 3687 | then the top 32 bits are taken. Shifting them right by 20 bits |
| 3688 | places the sign bit and exponent in the bottom 12 bits. Anding |
| 3689 | with 0x7FF gets rid of the sign bit, leaving just the exponent |
| 3690 | available for comparison. |
| 3691 | */ |
| 3692 | static IRTemp math_IS_TRIG_ARG_FINITE_AND_IN_RANGE ( IRTemp d64 ) |
| 3693 | { |
| 3694 | IRTemp i64 = newTemp(Ity_I64); |
| 3695 | assign(i64, unop(Iop_ReinterpF64asI64, mkexpr(d64)) ); |
| 3696 | IRTemp exponent = newTemp(Ity_I32); |
| 3697 | assign(exponent, |
| 3698 | binop(Iop_And32, |
| 3699 | binop(Iop_Shr32, unop(Iop_64HIto32, mkexpr(i64)), mkU8(20)), |
| 3700 | mkU32(0x7FF))); |
| 3701 | IRTemp in_range_and_finite = newTemp(Ity_I1); |
| 3702 | assign(in_range_and_finite, |
| 3703 | binop(Iop_CmpLE32U, mkexpr(exponent), mkU32(0x43D))); |
| 3704 | return in_range_and_finite; |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 3705 | } |
| 3706 | |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 3707 | /* Invent a plausible-looking FPU status word value: |
| 3708 | ((ftop & 7) << 11) | (c3210 & 0x4700) |
| 3709 | */ |
| 3710 | static IRExpr* get_FPU_sw ( void ) |
| 3711 | { |
| 3712 | return |
| 3713 | unop(Iop_32to16, |
| 3714 | binop(Iop_Or32, |
| 3715 | binop(Iop_Shl32, |
| 3716 | binop(Iop_And32, get_ftop(), mkU32(7)), |
| 3717 | mkU8(11)), |
| 3718 | binop(Iop_And32, get_C3210(), mkU32(0x4700)) |
| 3719 | )); |
| 3720 | } |
| 3721 | |
sewardj | 3f61ddb | 2004-10-16 20:51:05 +0000 | [diff] [blame] | 3722 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3723 | /* ------------------------------------------------------- */ |
| 3724 | /* Given all that stack-mangling junk, we can now go ahead |
| 3725 | and describe FP instructions. |
| 3726 | */ |
| 3727 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3728 | /* ST(0) = ST(0) `op` mem64/32(addr) |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 3729 | Need to check ST(0)'s tag on read, but not on write. |
| 3730 | */ |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3731 | static |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 3732 | void fp_do_op_mem_ST_0 ( IRTemp addr, const HChar* op_txt, HChar* dis_buf, |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3733 | IROp op, Bool dbl ) |
| 3734 | { |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 3735 | DIP("f%s%c %s\n", op_txt, dbl?'l':'s', dis_buf); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3736 | if (dbl) { |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3737 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3738 | triop( op, |
| 3739 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3740 | get_ST(0), |
| 3741 | loadLE(Ity_F64,mkexpr(addr)) |
| 3742 | )); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3743 | } else { |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3744 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3745 | triop( op, |
| 3746 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3747 | get_ST(0), |
| 3748 | unop(Iop_F32toF64, loadLE(Ity_F32,mkexpr(addr))) |
| 3749 | )); |
| 3750 | } |
| 3751 | } |
| 3752 | |
| 3753 | |
| 3754 | /* ST(0) = mem64/32(addr) `op` ST(0) |
| 3755 | Need to check ST(0)'s tag on read, but not on write. |
| 3756 | */ |
| 3757 | static |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 3758 | void fp_do_oprev_mem_ST_0 ( IRTemp addr, const HChar* op_txt, HChar* dis_buf, |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 3759 | IROp op, Bool dbl ) |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3760 | { |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 3761 | DIP("f%s%c %s\n", op_txt, dbl?'l':'s', dis_buf); |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3762 | if (dbl) { |
| 3763 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3764 | triop( op, |
| 3765 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3766 | loadLE(Ity_F64,mkexpr(addr)), |
| 3767 | get_ST(0) |
| 3768 | )); |
| 3769 | } else { |
| 3770 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3771 | triop( op, |
| 3772 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3773 | unop(Iop_F32toF64, loadLE(Ity_F32,mkexpr(addr))), |
| 3774 | get_ST(0) |
| 3775 | )); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3776 | } |
| 3777 | } |
| 3778 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3779 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3780 | /* ST(dst) = ST(dst) `op` ST(src). |
| 3781 | Check dst and src tags when reading but not on write. |
| 3782 | */ |
| 3783 | static |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 3784 | void fp_do_op_ST_ST ( const HChar* op_txt, IROp op, UInt st_src, UInt st_dst, |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3785 | Bool pop_after ) |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3786 | { |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 3787 | DIP("f%s%s st(%u), st(%u)\n", op_txt, pop_after?"p":"", |
| 3788 | st_src, st_dst); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3789 | put_ST_UNCHECKED( |
| 3790 | st_dst, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3791 | triop( op, |
| 3792 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 3793 | get_ST(st_dst), |
| 3794 | get_ST(st_src) ) |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3795 | ); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3796 | if (pop_after) |
| 3797 | fp_pop(); |
| 3798 | } |
| 3799 | |
| 3800 | /* ST(dst) = ST(src) `op` ST(dst). |
| 3801 | Check dst and src tags when reading but not on write. |
| 3802 | */ |
| 3803 | static |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 3804 | void fp_do_oprev_ST_ST ( const HChar* op_txt, IROp op, UInt st_src, |
| 3805 | UInt st_dst, Bool pop_after ) |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3806 | { |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 3807 | DIP("f%s%s st(%u), st(%u)\n", op_txt, pop_after?"p":"", |
| 3808 | st_src, st_dst); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3809 | put_ST_UNCHECKED( |
| 3810 | st_dst, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 3811 | triop( op, |
| 3812 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 3813 | get_ST(st_src), |
| 3814 | get_ST(st_dst) ) |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3815 | ); |
| 3816 | if (pop_after) |
| 3817 | fp_pop(); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3818 | } |
| 3819 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3820 | /* %eflags(Z,P,C) = UCOMI( st(0), st(i) ) */ |
| 3821 | static void fp_do_ucomi_ST0_STi ( UInt i, Bool pop_after ) |
| 3822 | { |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 3823 | DIP("fucomi%s %%st(0),%%st(%u)\n", pop_after ? "p" : "", i); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3824 | /* This is a bit of a hack (and isn't really right). It sets |
| 3825 | Z,P,C,O correctly, but forces A and S to zero, whereas the Intel |
| 3826 | documentation implies A and S are unchanged. |
| 3827 | */ |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 3828 | /* It's also fishy in that it is used both for COMIP and |
| 3829 | UCOMIP, and they aren't the same (although similar). */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 3830 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 3831 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 3832 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3833 | binop( Iop_And32, |
| 3834 | binop(Iop_CmpF64, get_ST(0), get_ST(i)), |
| 3835 | mkU32(0x45) |
| 3836 | ))); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 3837 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 3838 | elimination of previous stores to this field work better. */ |
| 3839 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3840 | if (pop_after) |
| 3841 | fp_pop(); |
| 3842 | } |
| 3843 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3844 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3845 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 3846 | UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3847 | { |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 3848 | Int len; |
| 3849 | UInt r_src, r_dst; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 3850 | HChar dis_buf[50]; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3851 | IRTemp t1, t2; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3852 | |
| 3853 | /* On entry, delta points at the second byte of the insn (the modrm |
| 3854 | byte).*/ |
| 3855 | UChar first_opcode = getIByte(delta-1); |
| 3856 | UChar modrm = getIByte(delta+0); |
| 3857 | |
| 3858 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xD8 opcodes +-+-+-+-+-+-+-+ */ |
| 3859 | |
| 3860 | if (first_opcode == 0xD8) { |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3861 | if (modrm < 0xC0) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3862 | |
| 3863 | /* bits 5,4,3 are an opcode extension, and the modRM also |
| 3864 | specifies an address. */ |
| 3865 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 3866 | delta += len; |
| 3867 | |
| 3868 | switch (gregOfRM(modrm)) { |
| 3869 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3870 | case 0: /* FADD single-real */ |
| 3871 | fp_do_op_mem_ST_0 ( addr, "add", dis_buf, Iop_AddF64, False ); |
| 3872 | break; |
| 3873 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3874 | case 1: /* FMUL single-real */ |
| 3875 | fp_do_op_mem_ST_0 ( addr, "mul", dis_buf, Iop_MulF64, False ); |
| 3876 | break; |
| 3877 | |
sewardj | 7ca37d9 | 2004-10-25 02:58:30 +0000 | [diff] [blame] | 3878 | case 2: /* FCOM single-real */ |
| 3879 | DIP("fcoms %s\n", dis_buf); |
| 3880 | /* This forces C1 to zero, which isn't right. */ |
| 3881 | put_C3210( |
| 3882 | binop( Iop_And32, |
| 3883 | binop(Iop_Shl32, |
| 3884 | binop(Iop_CmpF64, |
| 3885 | get_ST(0), |
| 3886 | unop(Iop_F32toF64, |
| 3887 | loadLE(Ity_F32,mkexpr(addr)))), |
| 3888 | mkU8(8)), |
| 3889 | mkU32(0x4500) |
| 3890 | )); |
| 3891 | break; |
| 3892 | |
| 3893 | case 3: /* FCOMP single-real */ |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 3894 | DIP("fcomps %s\n", dis_buf); |
| 3895 | /* This forces C1 to zero, which isn't right. */ |
| 3896 | put_C3210( |
| 3897 | binop( Iop_And32, |
| 3898 | binop(Iop_Shl32, |
| 3899 | binop(Iop_CmpF64, |
| 3900 | get_ST(0), |
| 3901 | unop(Iop_F32toF64, |
| 3902 | loadLE(Ity_F32,mkexpr(addr)))), |
| 3903 | mkU8(8)), |
| 3904 | mkU32(0x4500) |
| 3905 | )); |
| 3906 | fp_pop(); |
| 3907 | break; |
| 3908 | |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 3909 | case 4: /* FSUB single-real */ |
| 3910 | fp_do_op_mem_ST_0 ( addr, "sub", dis_buf, Iop_SubF64, False ); |
| 3911 | break; |
| 3912 | |
| 3913 | case 5: /* FSUBR single-real */ |
| 3914 | fp_do_oprev_mem_ST_0 ( addr, "subr", dis_buf, Iop_SubF64, False ); |
| 3915 | break; |
| 3916 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3917 | case 6: /* FDIV single-real */ |
| 3918 | fp_do_op_mem_ST_0 ( addr, "div", dis_buf, Iop_DivF64, False ); |
| 3919 | break; |
| 3920 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3921 | case 7: /* FDIVR single-real */ |
| 3922 | fp_do_oprev_mem_ST_0 ( addr, "divr", dis_buf, Iop_DivF64, False ); |
| 3923 | break; |
| 3924 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3925 | default: |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 3926 | vex_printf("unhandled opc_aux = 0x%2x\n", (UInt)gregOfRM(modrm)); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3927 | vex_printf("first_opcode == 0xD8\n"); |
| 3928 | goto decode_fail; |
| 3929 | } |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3930 | } else { |
| 3931 | delta++; |
| 3932 | switch (modrm) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3933 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3934 | case 0xC0 ... 0xC7: /* FADD %st(?),%st(0) */ |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3935 | fp_do_op_ST_ST ( "add", Iop_AddF64, modrm - 0xC0, 0, False ); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3936 | break; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3937 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3938 | case 0xC8 ... 0xCF: /* FMUL %st(?),%st(0) */ |
| 3939 | fp_do_op_ST_ST ( "mul", Iop_MulF64, modrm - 0xC8, 0, False ); |
| 3940 | break; |
| 3941 | |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 3942 | /* Dunno if this is right */ |
| 3943 | case 0xD0 ... 0xD7: /* FCOM %st(?),%st(0) */ |
| 3944 | r_dst = (UInt)modrm - 0xD0; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 3945 | DIP("fcom %%st(0),%%st(%u)\n", r_dst); |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 3946 | /* This forces C1 to zero, which isn't right. */ |
| 3947 | put_C3210( |
| 3948 | binop( Iop_And32, |
| 3949 | binop(Iop_Shl32, |
| 3950 | binop(Iop_CmpF64, get_ST(0), get_ST(r_dst)), |
| 3951 | mkU8(8)), |
| 3952 | mkU32(0x4500) |
| 3953 | )); |
| 3954 | break; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3955 | |
sewardj | 98169c5 | 2004-10-24 13:11:39 +0000 | [diff] [blame] | 3956 | /* Dunno if this is right */ |
| 3957 | case 0xD8 ... 0xDF: /* FCOMP %st(?),%st(0) */ |
| 3958 | r_dst = (UInt)modrm - 0xD8; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 3959 | DIP("fcomp %%st(0),%%st(%u)\n", r_dst); |
sewardj | 98169c5 | 2004-10-24 13:11:39 +0000 | [diff] [blame] | 3960 | /* This forces C1 to zero, which isn't right. */ |
| 3961 | put_C3210( |
| 3962 | binop( Iop_And32, |
| 3963 | binop(Iop_Shl32, |
| 3964 | binop(Iop_CmpF64, get_ST(0), get_ST(r_dst)), |
| 3965 | mkU8(8)), |
| 3966 | mkU32(0x4500) |
| 3967 | )); |
| 3968 | fp_pop(); |
| 3969 | break; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 3970 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3971 | case 0xE0 ... 0xE7: /* FSUB %st(?),%st(0) */ |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 3972 | fp_do_op_ST_ST ( "sub", Iop_SubF64, modrm - 0xE0, 0, False ); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3973 | break; |
| 3974 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 3975 | case 0xE8 ... 0xEF: /* FSUBR %st(?),%st(0) */ |
| 3976 | fp_do_oprev_ST_ST ( "subr", Iop_SubF64, modrm - 0xE8, 0, False ); |
| 3977 | break; |
| 3978 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 3979 | case 0xF0 ... 0xF7: /* FDIV %st(?),%st(0) */ |
| 3980 | fp_do_op_ST_ST ( "div", Iop_DivF64, modrm - 0xF0, 0, False ); |
| 3981 | break; |
| 3982 | |
| 3983 | case 0xF8 ... 0xFF: /* FDIVR %st(?),%st(0) */ |
| 3984 | fp_do_oprev_ST_ST ( "divr", Iop_DivF64, modrm - 0xF8, 0, False ); |
| 3985 | break; |
| 3986 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 3987 | default: |
| 3988 | goto decode_fail; |
| 3989 | } |
| 3990 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 3991 | } |
| 3992 | |
| 3993 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xD9 opcodes +-+-+-+-+-+-+-+ */ |
| 3994 | else |
| 3995 | if (first_opcode == 0xD9) { |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 3996 | if (modrm < 0xC0) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 3997 | |
| 3998 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 3999 | specifies an address. */ |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4000 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 4001 | delta += len; |
| 4002 | |
| 4003 | switch (gregOfRM(modrm)) { |
| 4004 | |
| 4005 | case 0: /* FLD single-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4006 | DIP("flds %s\n", dis_buf); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4007 | fp_push(); |
| 4008 | put_ST(0, unop(Iop_F32toF64, |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 4009 | loadLE(Ity_F32, mkexpr(addr)))); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4010 | break; |
| 4011 | |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 4012 | case 2: /* FST single-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4013 | DIP("fsts %s\n", dis_buf); |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 4014 | storeLE(mkexpr(addr), |
| 4015 | binop(Iop_F64toF32, get_roundingmode(), get_ST(0))); |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 4016 | break; |
| 4017 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4018 | case 3: /* FSTP single-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4019 | DIP("fstps %s\n", dis_buf); |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 4020 | storeLE(mkexpr(addr), |
| 4021 | binop(Iop_F64toF32, get_roundingmode(), get_ST(0))); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4022 | fp_pop(); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4023 | break; |
| 4024 | |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 4025 | case 4: { /* FLDENV m28 */ |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4026 | /* Uses dirty helper: |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 4027 | VexEmNote x86g_do_FLDENV ( VexGuestX86State*, HWord ) */ |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4028 | IRTemp ew = newTemp(Ity_I32); |
| 4029 | IRDirty* d = unsafeIRDirty_0_N ( |
| 4030 | 0/*regparms*/, |
| 4031 | "x86g_dirtyhelper_FLDENV", |
| 4032 | &x86g_dirtyhelper_FLDENV, |
florian | 9041956 | 2013-08-15 20:54:52 +0000 | [diff] [blame] | 4033 | mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) ) |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4034 | ); |
sewardj | 74142b8 | 2013-08-08 10:28:59 +0000 | [diff] [blame] | 4035 | d->tmp = ew; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4036 | /* declare we're reading memory */ |
| 4037 | d->mFx = Ifx_Read; |
| 4038 | d->mAddr = mkexpr(addr); |
| 4039 | d->mSize = 28; |
| 4040 | |
| 4041 | /* declare we're writing guest state */ |
sewardj | 46813fc | 2005-06-13 12:33:36 +0000 | [diff] [blame] | 4042 | d->nFxState = 4; |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 4043 | vex_bzero(&d->fxState, sizeof(d->fxState)); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4044 | |
| 4045 | d->fxState[0].fx = Ifx_Write; |
| 4046 | d->fxState[0].offset = OFFB_FTOP; |
| 4047 | d->fxState[0].size = sizeof(UInt); |
| 4048 | |
| 4049 | d->fxState[1].fx = Ifx_Write; |
sewardj | 46813fc | 2005-06-13 12:33:36 +0000 | [diff] [blame] | 4050 | d->fxState[1].offset = OFFB_FPTAGS; |
| 4051 | d->fxState[1].size = 8 * sizeof(UChar); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4052 | |
| 4053 | d->fxState[2].fx = Ifx_Write; |
sewardj | 46813fc | 2005-06-13 12:33:36 +0000 | [diff] [blame] | 4054 | d->fxState[2].offset = OFFB_FPROUND; |
| 4055 | d->fxState[2].size = sizeof(UInt); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4056 | |
| 4057 | d->fxState[3].fx = Ifx_Write; |
sewardj | 46813fc | 2005-06-13 12:33:36 +0000 | [diff] [blame] | 4058 | d->fxState[3].offset = OFFB_FC3210; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4059 | d->fxState[3].size = sizeof(UInt); |
| 4060 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4061 | stmt( IRStmt_Dirty(d) ); |
| 4062 | |
| 4063 | /* ew contains any emulation warning we may need to |
| 4064 | issue. If needed, side-exit to the next insn, |
| 4065 | reporting the warning, so that Valgrind's dispatcher |
| 4066 | sees the warning. */ |
| 4067 | put_emwarn( mkexpr(ew) ); |
| 4068 | stmt( |
| 4069 | IRStmt_Exit( |
| 4070 | binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)), |
| 4071 | Ijk_EmWarn, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 4072 | IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta), |
| 4073 | OFFB_EIP |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4074 | ) |
| 4075 | ); |
| 4076 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4077 | DIP("fldenv %s\n", dis_buf); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4078 | break; |
| 4079 | } |
| 4080 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4081 | case 5: {/* FLDCW */ |
| 4082 | /* The only thing we observe in the control word is the |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 4083 | rounding mode. Therefore, pass the 16-bit value |
| 4084 | (x87 native-format control word) to a clean helper, |
| 4085 | getting back a 64-bit value, the lower half of which |
| 4086 | is the FPROUND value to store, and the upper half of |
| 4087 | which is the emulation-warning token which may be |
| 4088 | generated. |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4089 | */ |
| 4090 | /* ULong x86h_check_fldcw ( UInt ); */ |
| 4091 | IRTemp t64 = newTemp(Ity_I64); |
| 4092 | IRTemp ew = newTemp(Ity_I32); |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4093 | DIP("fldcw %s\n", dis_buf); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4094 | assign( t64, mkIRExprCCall( |
| 4095 | Ity_I64, 0/*regparms*/, |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 4096 | "x86g_check_fldcw", |
| 4097 | &x86g_check_fldcw, |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4098 | mkIRExprVec_1( |
| 4099 | unop( Iop_16Uto32, |
| 4100 | loadLE(Ity_I16, mkexpr(addr))) |
| 4101 | ) |
| 4102 | ) |
| 4103 | ); |
| 4104 | |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 4105 | put_fpround( unop(Iop_64to32, mkexpr(t64)) ); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4106 | assign( ew, unop(Iop_64HIto32, mkexpr(t64) ) ); |
| 4107 | put_emwarn( mkexpr(ew) ); |
| 4108 | /* Finally, if an emulation warning was reported, |
| 4109 | side-exit to the next insn, reporting the warning, |
| 4110 | so that Valgrind's dispatcher sees the warning. */ |
| 4111 | stmt( |
| 4112 | IRStmt_Exit( |
| 4113 | binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)), |
| 4114 | Ijk_EmWarn, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 4115 | IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta), |
| 4116 | OFFB_EIP |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4117 | ) |
| 4118 | ); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4119 | break; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4120 | } |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4121 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4122 | case 6: { /* FNSTENV m28 */ |
| 4123 | /* Uses dirty helper: |
sewardj | 4017a3b | 2005-06-13 12:17:27 +0000 | [diff] [blame] | 4124 | void x86g_do_FSTENV ( VexGuestX86State*, HWord ) */ |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4125 | IRDirty* d = unsafeIRDirty_0_N ( |
| 4126 | 0/*regparms*/, |
| 4127 | "x86g_dirtyhelper_FSTENV", |
| 4128 | &x86g_dirtyhelper_FSTENV, |
florian | 9041956 | 2013-08-15 20:54:52 +0000 | [diff] [blame] | 4129 | mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) ) |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4130 | ); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4131 | /* declare we're writing memory */ |
| 4132 | d->mFx = Ifx_Write; |
| 4133 | d->mAddr = mkexpr(addr); |
| 4134 | d->mSize = 28; |
| 4135 | |
| 4136 | /* declare we're reading guest state */ |
| 4137 | d->nFxState = 4; |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 4138 | vex_bzero(&d->fxState, sizeof(d->fxState)); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4139 | |
| 4140 | d->fxState[0].fx = Ifx_Read; |
| 4141 | d->fxState[0].offset = OFFB_FTOP; |
| 4142 | d->fxState[0].size = sizeof(UInt); |
| 4143 | |
| 4144 | d->fxState[1].fx = Ifx_Read; |
| 4145 | d->fxState[1].offset = OFFB_FPTAGS; |
| 4146 | d->fxState[1].size = 8 * sizeof(UChar); |
| 4147 | |
| 4148 | d->fxState[2].fx = Ifx_Read; |
| 4149 | d->fxState[2].offset = OFFB_FPROUND; |
| 4150 | d->fxState[2].size = sizeof(UInt); |
| 4151 | |
| 4152 | d->fxState[3].fx = Ifx_Read; |
| 4153 | d->fxState[3].offset = OFFB_FC3210; |
| 4154 | d->fxState[3].size = sizeof(UInt); |
| 4155 | |
| 4156 | stmt( IRStmt_Dirty(d) ); |
| 4157 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4158 | DIP("fnstenv %s\n", dis_buf); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4159 | break; |
| 4160 | } |
| 4161 | |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 4162 | case 7: /* FNSTCW */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4163 | /* Fake up a native x87 FPU control word. The only |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 4164 | thing it depends on is FPROUND[1:0], so call a clean |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4165 | helper to cook it up. */ |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 4166 | /* UInt x86h_create_fpucw ( UInt fpround ) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4167 | DIP("fnstcw %s\n", dis_buf); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4168 | storeLE( |
| 4169 | mkexpr(addr), |
| 4170 | unop( Iop_32to16, |
| 4171 | mkIRExprCCall( |
| 4172 | Ity_I32, 0/*regp*/, |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 4173 | "x86g_create_fpucw", &x86g_create_fpucw, |
sewardj | d01a963 | 2004-11-30 13:18:37 +0000 | [diff] [blame] | 4174 | mkIRExprVec_1( get_fpround() ) |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 4175 | ) |
| 4176 | ) |
| 4177 | ); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4178 | break; |
| 4179 | |
| 4180 | default: |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4181 | vex_printf("unhandled opc_aux = 0x%2x\n", (UInt)gregOfRM(modrm)); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4182 | vex_printf("first_opcode == 0xD9\n"); |
| 4183 | goto decode_fail; |
| 4184 | } |
| 4185 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4186 | } else { |
| 4187 | delta++; |
| 4188 | switch (modrm) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4189 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4190 | case 0xC0 ... 0xC7: /* FLD %st(?) */ |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4191 | r_src = (UInt)modrm - 0xC0; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4192 | DIP("fld %%st(%u)\n", r_src); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4193 | t1 = newTemp(Ity_F64); |
| 4194 | assign(t1, get_ST(r_src)); |
| 4195 | fp_push(); |
| 4196 | put_ST(0, mkexpr(t1)); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4197 | break; |
| 4198 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4199 | case 0xC8 ... 0xCF: /* FXCH %st(?) */ |
| 4200 | r_src = (UInt)modrm - 0xC8; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4201 | DIP("fxch %%st(%u)\n", r_src); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4202 | t1 = newTemp(Ity_F64); |
| 4203 | t2 = newTemp(Ity_F64); |
| 4204 | assign(t1, get_ST(0)); |
| 4205 | assign(t2, get_ST(r_src)); |
| 4206 | put_ST_UNCHECKED(0, mkexpr(t2)); |
| 4207 | put_ST_UNCHECKED(r_src, mkexpr(t1)); |
| 4208 | break; |
| 4209 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4210 | case 0xE0: /* FCHS */ |
| 4211 | DIP("fchs\n"); |
| 4212 | put_ST_UNCHECKED(0, unop(Iop_NegF64, get_ST(0))); |
| 4213 | break; |
| 4214 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4215 | case 0xE1: /* FABS */ |
| 4216 | DIP("fabs\n"); |
| 4217 | put_ST_UNCHECKED(0, unop(Iop_AbsF64, get_ST(0))); |
| 4218 | break; |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 4219 | |
sewardj | 1c31877 | 2005-03-19 14:27:04 +0000 | [diff] [blame] | 4220 | case 0xE4: /* FTST */ |
| 4221 | DIP("ftst\n"); |
| 4222 | /* This forces C1 to zero, which isn't right. */ |
| 4223 | /* Well, in fact the Intel docs say (bizarrely): "C1 is |
| 4224 | set to 0 if stack underflow occurred; otherwise, set |
| 4225 | to 0" which is pretty nonsensical. I guess it's a |
| 4226 | typo. */ |
| 4227 | put_C3210( |
| 4228 | binop( Iop_And32, |
| 4229 | binop(Iop_Shl32, |
| 4230 | binop(Iop_CmpF64, |
| 4231 | get_ST(0), |
| 4232 | IRExpr_Const(IRConst_F64i(0x0ULL))), |
| 4233 | mkU8(8)), |
| 4234 | mkU32(0x4500) |
| 4235 | )); |
| 4236 | break; |
| 4237 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4238 | case 0xE5: { /* FXAM */ |
| 4239 | /* This is an interesting one. It examines %st(0), |
| 4240 | regardless of whether the tag says it's empty or not. |
| 4241 | Here, just pass both the tag (in our format) and the |
| 4242 | value (as a double, actually a ULong) to a helper |
| 4243 | function. */ |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 4244 | IRExpr** args |
| 4245 | = mkIRExprVec_2( unop(Iop_8Uto32, get_ST_TAG(0)), |
| 4246 | unop(Iop_ReinterpF64asI64, |
| 4247 | get_ST_UNCHECKED(0)) ); |
| 4248 | put_C3210(mkIRExprCCall( |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4249 | Ity_I32, |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 4250 | 0/*regparm*/, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 4251 | "x86g_calculate_FXAM", &x86g_calculate_FXAM, |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4252 | args |
| 4253 | )); |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4254 | DIP("fxam\n"); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4255 | break; |
| 4256 | } |
| 4257 | |
| 4258 | case 0xE8: /* FLD1 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4259 | DIP("fld1\n"); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4260 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4261 | /* put_ST(0, IRExpr_Const(IRConst_F64(1.0))); */ |
| 4262 | put_ST(0, IRExpr_Const(IRConst_F64i(0x3ff0000000000000ULL))); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4263 | break; |
| 4264 | |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 4265 | case 0xE9: /* FLDL2T */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4266 | DIP("fldl2t\n"); |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 4267 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4268 | /* put_ST(0, IRExpr_Const(IRConst_F64(3.32192809488736234781))); */ |
| 4269 | put_ST(0, IRExpr_Const(IRConst_F64i(0x400a934f0979a371ULL))); |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 4270 | break; |
| 4271 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4272 | case 0xEA: /* FLDL2E */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4273 | DIP("fldl2e\n"); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4274 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4275 | /* put_ST(0, IRExpr_Const(IRConst_F64(1.44269504088896340739))); */ |
| 4276 | put_ST(0, IRExpr_Const(IRConst_F64i(0x3ff71547652b82feULL))); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4277 | break; |
| 4278 | |
sewardj | a0d48d6 | 2004-09-20 21:19:03 +0000 | [diff] [blame] | 4279 | case 0xEB: /* FLDPI */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4280 | DIP("fldpi\n"); |
sewardj | a0d48d6 | 2004-09-20 21:19:03 +0000 | [diff] [blame] | 4281 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4282 | /* put_ST(0, IRExpr_Const(IRConst_F64(3.14159265358979323851))); */ |
| 4283 | put_ST(0, IRExpr_Const(IRConst_F64i(0x400921fb54442d18ULL))); |
sewardj | a0d48d6 | 2004-09-20 21:19:03 +0000 | [diff] [blame] | 4284 | break; |
| 4285 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4286 | case 0xEC: /* FLDLG2 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4287 | DIP("fldlg2\n"); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4288 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4289 | /* put_ST(0, IRExpr_Const(IRConst_F64(0.301029995663981143))); */ |
| 4290 | put_ST(0, IRExpr_Const(IRConst_F64i(0x3fd34413509f79ffULL))); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4291 | break; |
| 4292 | |
| 4293 | case 0xED: /* FLDLN2 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4294 | DIP("fldln2\n"); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4295 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4296 | /* put_ST(0, IRExpr_Const(IRConst_F64(0.69314718055994530942))); */ |
| 4297 | put_ST(0, IRExpr_Const(IRConst_F64i(0x3fe62e42fefa39efULL))); |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4298 | break; |
| 4299 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4300 | case 0xEE: /* FLDZ */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4301 | DIP("fldz\n"); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 4302 | fp_push(); |
sewardj | 9c32376 | 2005-01-10 16:49:19 +0000 | [diff] [blame] | 4303 | /* put_ST(0, IRExpr_Const(IRConst_F64(0.0))); */ |
| 4304 | put_ST(0, IRExpr_Const(IRConst_F64i(0x0000000000000000ULL))); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4305 | break; |
| 4306 | |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 4307 | case 0xF0: /* F2XM1 */ |
| 4308 | DIP("f2xm1\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4309 | put_ST_UNCHECKED(0, |
| 4310 | binop(Iop_2xm1F64, |
| 4311 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4312 | get_ST(0))); |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 4313 | break; |
| 4314 | |
sewardj | 52ace3e | 2004-09-11 17:10:08 +0000 | [diff] [blame] | 4315 | case 0xF1: /* FYL2X */ |
| 4316 | DIP("fyl2x\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4317 | put_ST_UNCHECKED(1, |
| 4318 | triop(Iop_Yl2xF64, |
| 4319 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4320 | get_ST(1), |
| 4321 | get_ST(0))); |
sewardj | 52ace3e | 2004-09-11 17:10:08 +0000 | [diff] [blame] | 4322 | fp_pop(); |
| 4323 | break; |
| 4324 | |
sewardj | e9c51c9 | 2014-04-30 22:50:34 +0000 | [diff] [blame] | 4325 | case 0xF2: { /* FPTAN */ |
| 4326 | DIP("fptan\n"); |
| 4327 | IRTemp argD = newTemp(Ity_F64); |
| 4328 | assign(argD, get_ST(0)); |
| 4329 | IRTemp argOK = math_IS_TRIG_ARG_FINITE_AND_IN_RANGE(argD); |
| 4330 | IRTemp resD = newTemp(Ity_F64); |
| 4331 | assign(resD, |
| 4332 | IRExpr_ITE( |
| 4333 | mkexpr(argOK), |
| 4334 | binop(Iop_TanF64, |
| 4335 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4336 | mkexpr(argD)), |
| 4337 | mkexpr(argD)) |
| 4338 | ); |
| 4339 | put_ST_UNCHECKED(0, mkexpr(resD)); |
| 4340 | /* Conditionally push 1.0 on the stack, if the arg is |
| 4341 | in range */ |
| 4342 | maybe_fp_push(argOK); |
| 4343 | maybe_put_ST(argOK, 0, |
| 4344 | IRExpr_Const(IRConst_F64(1.0))); |
| 4345 | set_C2( binop(Iop_Xor32, |
| 4346 | unop(Iop_1Uto32, mkexpr(argOK)), |
| 4347 | mkU32(1)) ); |
sewardj | 99016a7 | 2004-10-15 22:09:17 +0000 | [diff] [blame] | 4348 | break; |
sewardj | e9c51c9 | 2014-04-30 22:50:34 +0000 | [diff] [blame] | 4349 | } |
sewardj | 99016a7 | 2004-10-15 22:09:17 +0000 | [diff] [blame] | 4350 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4351 | case 0xF3: /* FPATAN */ |
| 4352 | DIP("fpatan\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4353 | put_ST_UNCHECKED(1, |
| 4354 | triop(Iop_AtanF64, |
| 4355 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4356 | get_ST(1), |
| 4357 | get_ST(0))); |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4358 | fp_pop(); |
| 4359 | break; |
| 4360 | |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4361 | case 0xF4: { /* FXTRACT */ |
sewardj | fda10af | 2005-10-03 01:02:40 +0000 | [diff] [blame] | 4362 | IRTemp argF = newTemp(Ity_F64); |
| 4363 | IRTemp sigF = newTemp(Ity_F64); |
| 4364 | IRTemp expF = newTemp(Ity_F64); |
| 4365 | IRTemp argI = newTemp(Ity_I64); |
| 4366 | IRTemp sigI = newTemp(Ity_I64); |
| 4367 | IRTemp expI = newTemp(Ity_I64); |
| 4368 | DIP("fxtract\n"); |
| 4369 | assign( argF, get_ST(0) ); |
| 4370 | assign( argI, unop(Iop_ReinterpF64asI64, mkexpr(argF))); |
| 4371 | assign( sigI, |
sewardj | 879cee0 | 2006-03-07 01:15:50 +0000 | [diff] [blame] | 4372 | mkIRExprCCall( |
| 4373 | Ity_I64, 0/*regparms*/, |
| 4374 | "x86amd64g_calculate_FXTRACT", |
| 4375 | &x86amd64g_calculate_FXTRACT, |
| 4376 | mkIRExprVec_2( mkexpr(argI), |
| 4377 | mkIRExpr_HWord(0)/*sig*/ )) |
| 4378 | ); |
sewardj | fda10af | 2005-10-03 01:02:40 +0000 | [diff] [blame] | 4379 | assign( expI, |
sewardj | 879cee0 | 2006-03-07 01:15:50 +0000 | [diff] [blame] | 4380 | mkIRExprCCall( |
| 4381 | Ity_I64, 0/*regparms*/, |
| 4382 | "x86amd64g_calculate_FXTRACT", |
| 4383 | &x86amd64g_calculate_FXTRACT, |
| 4384 | mkIRExprVec_2( mkexpr(argI), |
| 4385 | mkIRExpr_HWord(1)/*exp*/ )) |
| 4386 | ); |
sewardj | fda10af | 2005-10-03 01:02:40 +0000 | [diff] [blame] | 4387 | assign( sigF, unop(Iop_ReinterpI64asF64, mkexpr(sigI)) ); |
| 4388 | assign( expF, unop(Iop_ReinterpI64asF64, mkexpr(expI)) ); |
| 4389 | /* exponent */ |
| 4390 | put_ST_UNCHECKED(0, mkexpr(expF) ); |
| 4391 | fp_push(); |
| 4392 | /* significand */ |
| 4393 | put_ST(0, mkexpr(sigF) ); |
| 4394 | break; |
| 4395 | } |
| 4396 | |
sewardj | 442d0be | 2004-10-15 22:57:13 +0000 | [diff] [blame] | 4397 | case 0xF5: { /* FPREM1 -- IEEE compliant */ |
| 4398 | IRTemp a1 = newTemp(Ity_F64); |
| 4399 | IRTemp a2 = newTemp(Ity_F64); |
| 4400 | DIP("fprem1\n"); |
| 4401 | /* Do FPREM1 twice, once to get the remainder, and once |
| 4402 | to get the C3210 flag values. */ |
| 4403 | assign( a1, get_ST(0) ); |
| 4404 | assign( a2, get_ST(1) ); |
sewardj | f47286e | 2006-02-04 15:20:13 +0000 | [diff] [blame] | 4405 | put_ST_UNCHECKED(0, |
| 4406 | triop(Iop_PRem1F64, |
| 4407 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4408 | mkexpr(a1), |
| 4409 | mkexpr(a2))); |
| 4410 | put_C3210( |
| 4411 | triop(Iop_PRem1C3210F64, |
| 4412 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4413 | mkexpr(a1), |
| 4414 | mkexpr(a2)) ); |
sewardj | 442d0be | 2004-10-15 22:57:13 +0000 | [diff] [blame] | 4415 | break; |
| 4416 | } |
| 4417 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 4418 | case 0xF7: /* FINCSTP */ |
| 4419 | DIP("fprem\n"); |
| 4420 | put_ftop( binop(Iop_Add32, get_ftop(), mkU32(1)) ); |
| 4421 | break; |
| 4422 | |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 4423 | case 0xF8: { /* FPREM -- not IEEE compliant */ |
| 4424 | IRTemp a1 = newTemp(Ity_F64); |
| 4425 | IRTemp a2 = newTemp(Ity_F64); |
| 4426 | DIP("fprem\n"); |
| 4427 | /* Do FPREM twice, once to get the remainder, and once |
| 4428 | to get the C3210 flag values. */ |
| 4429 | assign( a1, get_ST(0) ); |
| 4430 | assign( a2, get_ST(1) ); |
sewardj | f47286e | 2006-02-04 15:20:13 +0000 | [diff] [blame] | 4431 | put_ST_UNCHECKED(0, |
| 4432 | triop(Iop_PRemF64, |
| 4433 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4434 | mkexpr(a1), |
| 4435 | mkexpr(a2))); |
| 4436 | put_C3210( |
| 4437 | triop(Iop_PRemC3210F64, |
| 4438 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4439 | mkexpr(a1), |
| 4440 | mkexpr(a2)) ); |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 4441 | break; |
| 4442 | } |
| 4443 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4444 | case 0xF9: /* FYL2XP1 */ |
| 4445 | DIP("fyl2xp1\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4446 | put_ST_UNCHECKED(1, |
| 4447 | triop(Iop_Yl2xp1F64, |
| 4448 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4449 | get_ST(1), |
| 4450 | get_ST(0))); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4451 | fp_pop(); |
| 4452 | break; |
| 4453 | |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 4454 | case 0xFA: /* FSQRT */ |
| 4455 | DIP("fsqrt\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4456 | put_ST_UNCHECKED(0, |
| 4457 | binop(Iop_SqrtF64, |
| 4458 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4459 | get_ST(0))); |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 4460 | break; |
| 4461 | |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4462 | case 0xFB: { /* FSINCOS */ |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4463 | DIP("fsincos\n"); |
sewardj | e9c51c9 | 2014-04-30 22:50:34 +0000 | [diff] [blame] | 4464 | IRTemp argD = newTemp(Ity_F64); |
| 4465 | assign(argD, get_ST(0)); |
| 4466 | IRTemp argOK = math_IS_TRIG_ARG_FINITE_AND_IN_RANGE(argD); |
| 4467 | IRTemp resD = newTemp(Ity_F64); |
| 4468 | assign(resD, |
| 4469 | IRExpr_ITE( |
| 4470 | mkexpr(argOK), |
| 4471 | binop(Iop_SinF64, |
| 4472 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4473 | mkexpr(argD)), |
| 4474 | mkexpr(argD)) |
| 4475 | ); |
| 4476 | put_ST_UNCHECKED(0, mkexpr(resD)); |
| 4477 | /* Conditionally push the cos value on the stack, if |
| 4478 | the arg is in range */ |
| 4479 | maybe_fp_push(argOK); |
| 4480 | maybe_put_ST(argOK, 0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4481 | binop(Iop_CosF64, |
| 4482 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | e9c51c9 | 2014-04-30 22:50:34 +0000 | [diff] [blame] | 4483 | mkexpr(argD))); |
| 4484 | set_C2( binop(Iop_Xor32, |
| 4485 | unop(Iop_1Uto32, mkexpr(argOK)), |
| 4486 | mkU32(1)) ); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4487 | break; |
| 4488 | } |
| 4489 | |
sewardj | e670911 | 2004-09-10 18:37:18 +0000 | [diff] [blame] | 4490 | case 0xFC: /* FRNDINT */ |
| 4491 | DIP("frndint\n"); |
| 4492 | put_ST_UNCHECKED(0, |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 4493 | binop(Iop_RoundF64toInt, get_roundingmode(), get_ST(0)) ); |
sewardj | e670911 | 2004-09-10 18:37:18 +0000 | [diff] [blame] | 4494 | break; |
| 4495 | |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 4496 | case 0xFD: /* FSCALE */ |
| 4497 | DIP("fscale\n"); |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4498 | put_ST_UNCHECKED(0, |
| 4499 | triop(Iop_ScaleF64, |
| 4500 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4501 | get_ST(0), |
| 4502 | get_ST(1))); |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 4503 | break; |
| 4504 | |
sewardj | e9c51c9 | 2014-04-30 22:50:34 +0000 | [diff] [blame] | 4505 | case 0xFE: /* FSIN */ |
| 4506 | case 0xFF: { /* FCOS */ |
| 4507 | Bool isSIN = modrm == 0xFE; |
| 4508 | DIP("%s\n", isSIN ? "fsin" : "fcos"); |
| 4509 | IRTemp argD = newTemp(Ity_F64); |
| 4510 | assign(argD, get_ST(0)); |
| 4511 | IRTemp argOK = math_IS_TRIG_ARG_FINITE_AND_IN_RANGE(argD); |
| 4512 | IRTemp resD = newTemp(Ity_F64); |
| 4513 | assign(resD, |
| 4514 | IRExpr_ITE( |
| 4515 | mkexpr(argOK), |
| 4516 | binop(isSIN ? Iop_SinF64 : Iop_CosF64, |
| 4517 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 4518 | mkexpr(argD)), |
| 4519 | mkexpr(argD)) |
| 4520 | ); |
| 4521 | put_ST_UNCHECKED(0, mkexpr(resD)); |
| 4522 | set_C2( binop(Iop_Xor32, |
| 4523 | unop(Iop_1Uto32, mkexpr(argOK)), |
| 4524 | mkU32(1)) ); |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4525 | break; |
sewardj | e9c51c9 | 2014-04-30 22:50:34 +0000 | [diff] [blame] | 4526 | } |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4527 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4528 | default: |
| 4529 | goto decode_fail; |
| 4530 | } |
| 4531 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4532 | } |
| 4533 | |
| 4534 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDA opcodes +-+-+-+-+-+-+-+ */ |
| 4535 | else |
| 4536 | if (first_opcode == 0xDA) { |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4537 | |
| 4538 | if (modrm < 0xC0) { |
| 4539 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 4540 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4541 | specifies an address. */ |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4542 | IROp fop; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4543 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 4544 | delta += len; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4545 | switch (gregOfRM(modrm)) { |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4546 | |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4547 | case 0: /* FIADD m32int */ /* ST(0) += m32int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4548 | DIP("fiaddl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4549 | fop = Iop_AddF64; |
| 4550 | goto do_fop_m32; |
sewardj | db19962 | 2004-09-06 23:19:03 +0000 | [diff] [blame] | 4551 | |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 4552 | case 1: /* FIMUL m32int */ /* ST(0) *= m32int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4553 | DIP("fimull %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4554 | fop = Iop_MulF64; |
| 4555 | goto do_fop_m32; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4556 | |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 4557 | case 2: /* FICOM m32int */ |
| 4558 | DIP("ficoml %s\n", dis_buf); |
| 4559 | /* This forces C1 to zero, which isn't right. */ |
| 4560 | put_C3210( |
| 4561 | binop( Iop_And32, |
| 4562 | binop(Iop_Shl32, |
| 4563 | binop(Iop_CmpF64, |
| 4564 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4565 | unop(Iop_I32StoF64, |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 4566 | loadLE(Ity_I32,mkexpr(addr)))), |
| 4567 | mkU8(8)), |
| 4568 | mkU32(0x4500) |
| 4569 | )); |
| 4570 | break; |
| 4571 | |
| 4572 | case 3: /* FICOMP m32int */ |
| 4573 | DIP("ficompl %s\n", dis_buf); |
| 4574 | /* This forces C1 to zero, which isn't right. */ |
| 4575 | put_C3210( |
| 4576 | binop( Iop_And32, |
| 4577 | binop(Iop_Shl32, |
| 4578 | binop(Iop_CmpF64, |
| 4579 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4580 | unop(Iop_I32StoF64, |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 4581 | loadLE(Ity_I32,mkexpr(addr)))), |
| 4582 | mkU8(8)), |
| 4583 | mkU32(0x4500) |
| 4584 | )); |
| 4585 | fp_pop(); |
| 4586 | break; |
| 4587 | |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4588 | case 4: /* FISUB m32int */ /* ST(0) -= m32int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4589 | DIP("fisubl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4590 | fop = Iop_SubF64; |
| 4591 | goto do_fop_m32; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4592 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4593 | case 5: /* FISUBR m32int */ /* ST(0) = m32int - ST(0) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4594 | DIP("fisubrl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4595 | fop = Iop_SubF64; |
| 4596 | goto do_foprev_m32; |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4597 | |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4598 | case 6: /* FIDIV m32int */ /* ST(0) /= m32int */ |
sewardj | 36917e9 | 2005-03-21 00:12:15 +0000 | [diff] [blame] | 4599 | DIP("fidivl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4600 | fop = Iop_DivF64; |
| 4601 | goto do_fop_m32; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4602 | |
sewardj | c4eaff3 | 2004-09-10 20:25:11 +0000 | [diff] [blame] | 4603 | case 7: /* FIDIVR m32int */ /* ST(0) = m32int / ST(0) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4604 | DIP("fidivrl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4605 | fop = Iop_DivF64; |
| 4606 | goto do_foprev_m32; |
sewardj | c4eaff3 | 2004-09-10 20:25:11 +0000 | [diff] [blame] | 4607 | |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 4608 | do_fop_m32: |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 4609 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4610 | triop(fop, |
| 4611 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 4612 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4613 | unop(Iop_I32StoF64, |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4614 | loadLE(Ity_I32, mkexpr(addr))))); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4615 | break; |
| 4616 | |
sewardj | c4eaff3 | 2004-09-10 20:25:11 +0000 | [diff] [blame] | 4617 | do_foprev_m32: |
| 4618 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 4619 | triop(fop, |
| 4620 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4621 | unop(Iop_I32StoF64, |
sewardj | c4eaff3 | 2004-09-10 20:25:11 +0000 | [diff] [blame] | 4622 | loadLE(Ity_I32, mkexpr(addr))), |
| 4623 | get_ST(0))); |
| 4624 | break; |
| 4625 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4626 | default: |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4627 | vex_printf("unhandled opc_aux = 0x%2x\n", (UInt)gregOfRM(modrm)); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4628 | vex_printf("first_opcode == 0xDA\n"); |
| 4629 | goto decode_fail; |
| 4630 | } |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 4631 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4632 | } else { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4633 | |
| 4634 | delta++; |
| 4635 | switch (modrm) { |
| 4636 | |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4637 | case 0xC0 ... 0xC7: /* FCMOVB ST(i), ST(0) */ |
| 4638 | r_src = (UInt)modrm - 0xC0; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4639 | DIP("fcmovb %%st(%u), %%st(0)\n", r_src); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4640 | put_ST_UNCHECKED(0, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4641 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 4642 | mk_x86g_calculate_condition(X86CondB), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4643 | get_ST(r_src), get_ST(0)) ); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4644 | break; |
| 4645 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 4646 | case 0xC8 ... 0xCF: /* FCMOVE(Z) ST(i), ST(0) */ |
| 4647 | r_src = (UInt)modrm - 0xC8; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4648 | DIP("fcmovz %%st(%u), %%st(0)\n", r_src); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4649 | put_ST_UNCHECKED(0, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4650 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 4651 | mk_x86g_calculate_condition(X86CondZ), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4652 | get_ST(r_src), get_ST(0)) ); |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 4653 | break; |
| 4654 | |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4655 | case 0xD0 ... 0xD7: /* FCMOVBE ST(i), ST(0) */ |
| 4656 | r_src = (UInt)modrm - 0xD0; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4657 | DIP("fcmovbe %%st(%u), %%st(0)\n", r_src); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4658 | put_ST_UNCHECKED(0, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4659 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 4660 | mk_x86g_calculate_condition(X86CondBE), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4661 | get_ST(r_src), get_ST(0)) ); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4662 | break; |
| 4663 | |
sewardj | 8253ad3 | 2005-07-04 10:26:32 +0000 | [diff] [blame] | 4664 | case 0xD8 ... 0xDF: /* FCMOVU ST(i), ST(0) */ |
| 4665 | r_src = (UInt)modrm - 0xD8; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4666 | DIP("fcmovu %%st(%u), %%st(0)\n", r_src); |
sewardj | 8253ad3 | 2005-07-04 10:26:32 +0000 | [diff] [blame] | 4667 | put_ST_UNCHECKED(0, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4668 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 4669 | mk_x86g_calculate_condition(X86CondP), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4670 | get_ST(r_src), get_ST(0)) ); |
sewardj | 8253ad3 | 2005-07-04 10:26:32 +0000 | [diff] [blame] | 4671 | break; |
| 4672 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4673 | case 0xE9: /* FUCOMPP %st(0),%st(1) */ |
| 4674 | DIP("fucompp %%st(0),%%st(1)\n"); |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 4675 | /* This forces C1 to zero, which isn't right. */ |
| 4676 | put_C3210( |
| 4677 | binop( Iop_And32, |
| 4678 | binop(Iop_Shl32, |
| 4679 | binop(Iop_CmpF64, get_ST(0), get_ST(1)), |
| 4680 | mkU8(8)), |
| 4681 | mkU32(0x4500) |
| 4682 | )); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4683 | fp_pop(); |
| 4684 | fp_pop(); |
| 4685 | break; |
| 4686 | |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4687 | default: |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4688 | goto decode_fail; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4689 | } |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4690 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 4691 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4692 | } |
| 4693 | |
| 4694 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDB opcodes +-+-+-+-+-+-+-+ */ |
| 4695 | else |
| 4696 | if (first_opcode == 0xDB) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4697 | if (modrm < 0xC0) { |
| 4698 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 4699 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4700 | specifies an address. */ |
| 4701 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 4702 | delta += len; |
| 4703 | |
| 4704 | switch (gregOfRM(modrm)) { |
| 4705 | |
| 4706 | case 0: /* FILD m32int */ |
| 4707 | DIP("fildl %s\n", dis_buf); |
| 4708 | fp_push(); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4709 | put_ST(0, unop(Iop_I32StoF64, |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4710 | loadLE(Ity_I32, mkexpr(addr)))); |
| 4711 | break; |
| 4712 | |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 4713 | case 1: /* FISTTPL m32 (SSE3) */ |
| 4714 | DIP("fisttpl %s\n", dis_buf); |
| 4715 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4716 | binop(Iop_F64toI32S, mkU32(Irrm_ZERO), get_ST(0)) ); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 4717 | fp_pop(); |
| 4718 | break; |
| 4719 | |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 4720 | case 2: /* FIST m32 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4721 | DIP("fistl %s\n", dis_buf); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 4722 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4723 | binop(Iop_F64toI32S, get_roundingmode(), get_ST(0)) ); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 4724 | break; |
| 4725 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4726 | case 3: /* FISTP m32 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4727 | DIP("fistpl %s\n", dis_buf); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 4728 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 4729 | binop(Iop_F64toI32S, get_roundingmode(), get_ST(0)) ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4730 | fp_pop(); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4731 | break; |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4732 | |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4733 | case 5: { /* FLD extended-real */ |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 4734 | /* Uses dirty helper: |
sewardj | 5657923 | 2005-03-26 21:49:42 +0000 | [diff] [blame] | 4735 | ULong x86g_loadF80le ( UInt ) |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 4736 | addr holds the address. First, do a dirty call to |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4737 | get hold of the data. */ |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4738 | IRTemp val = newTemp(Ity_I64); |
| 4739 | IRExpr** args = mkIRExprVec_1 ( mkexpr(addr) ); |
| 4740 | |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4741 | IRDirty* d = unsafeIRDirty_1_N ( |
| 4742 | val, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 4743 | 0/*regparms*/, |
sewardj | 8f40b07 | 2005-08-23 19:30:58 +0000 | [diff] [blame] | 4744 | "x86g_dirtyhelper_loadF80le", |
| 4745 | &x86g_dirtyhelper_loadF80le, |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4746 | args |
| 4747 | ); |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4748 | /* declare that we're reading memory */ |
| 4749 | d->mFx = Ifx_Read; |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4750 | d->mAddr = mkexpr(addr); |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4751 | d->mSize = 10; |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4752 | |
| 4753 | /* execute the dirty call, dumping the result in val. */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4754 | stmt( IRStmt_Dirty(d) ); |
| 4755 | fp_push(); |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4756 | put_ST(0, unop(Iop_ReinterpI64asF64, mkexpr(val))); |
| 4757 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4758 | DIP("fldt %s\n", dis_buf); |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4759 | break; |
| 4760 | } |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4761 | |
| 4762 | case 7: { /* FSTP extended-real */ |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 4763 | /* Uses dirty helper: void x86g_storeF80le ( UInt, ULong ) */ |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4764 | IRExpr** args |
| 4765 | = mkIRExprVec_2( mkexpr(addr), |
| 4766 | unop(Iop_ReinterpF64asI64, get_ST(0)) ); |
| 4767 | |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4768 | IRDirty* d = unsafeIRDirty_0_N ( |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 4769 | 0/*regparms*/, |
sewardj | 8f40b07 | 2005-08-23 19:30:58 +0000 | [diff] [blame] | 4770 | "x86g_dirtyhelper_storeF80le", |
| 4771 | &x86g_dirtyhelper_storeF80le, |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 4772 | args |
| 4773 | ); |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4774 | /* declare we're writing memory */ |
| 4775 | d->mFx = Ifx_Write; |
| 4776 | d->mAddr = mkexpr(addr); |
| 4777 | d->mSize = 10; |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4778 | |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4779 | /* execute the dirty call. */ |
| 4780 | stmt( IRStmt_Dirty(d) ); |
| 4781 | fp_pop(); |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 4782 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4783 | DIP("fstpt\n %s", dis_buf); |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4784 | break; |
| 4785 | } |
| 4786 | |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 4787 | default: |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4788 | vex_printf("unhandled opc_aux = 0x%2x\n", (UInt)gregOfRM(modrm)); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4789 | vex_printf("first_opcode == 0xDB\n"); |
| 4790 | goto decode_fail; |
| 4791 | } |
| 4792 | |
| 4793 | } else { |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4794 | |
| 4795 | delta++; |
| 4796 | switch (modrm) { |
| 4797 | |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4798 | case 0xC0 ... 0xC7: /* FCMOVNB ST(i), ST(0) */ |
| 4799 | r_src = (UInt)modrm - 0xC0; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4800 | DIP("fcmovnb %%st(%u), %%st(0)\n", r_src); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4801 | put_ST_UNCHECKED(0, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4802 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 4803 | mk_x86g_calculate_condition(X86CondNB), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4804 | get_ST(r_src), get_ST(0)) ); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4805 | break; |
| 4806 | |
sewardj | 4e82db7 | 2004-10-16 11:32:15 +0000 | [diff] [blame] | 4807 | case 0xC8 ... 0xCF: /* FCMOVNE(NZ) ST(i), ST(0) */ |
| 4808 | r_src = (UInt)modrm - 0xC8; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4809 | DIP("fcmovnz %%st(%u), %%st(0)\n", r_src); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4810 | put_ST_UNCHECKED(0, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4811 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 4812 | mk_x86g_calculate_condition(X86CondNZ), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4813 | get_ST(r_src), get_ST(0)) ); |
sewardj | 4e82db7 | 2004-10-16 11:32:15 +0000 | [diff] [blame] | 4814 | break; |
| 4815 | |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4816 | case 0xD0 ... 0xD7: /* FCMOVNBE ST(i), ST(0) */ |
| 4817 | r_src = (UInt)modrm - 0xD0; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4818 | DIP("fcmovnbe %%st(%u), %%st(0)\n", r_src); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4819 | put_ST_UNCHECKED(0, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4820 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 4821 | mk_x86g_calculate_condition(X86CondNBE), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4822 | get_ST(r_src), get_ST(0)) ); |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 4823 | break; |
| 4824 | |
sewardj | 8253ad3 | 2005-07-04 10:26:32 +0000 | [diff] [blame] | 4825 | case 0xD8 ... 0xDF: /* FCMOVNU ST(i), ST(0) */ |
| 4826 | r_src = (UInt)modrm - 0xD8; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4827 | DIP("fcmovnu %%st(%u), %%st(0)\n", r_src); |
sewardj | 8253ad3 | 2005-07-04 10:26:32 +0000 | [diff] [blame] | 4828 | put_ST_UNCHECKED(0, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4829 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 4830 | mk_x86g_calculate_condition(X86CondNP), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 4831 | get_ST(r_src), get_ST(0)) ); |
sewardj | 8253ad3 | 2005-07-04 10:26:32 +0000 | [diff] [blame] | 4832 | break; |
| 4833 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 4834 | case 0xE2: |
| 4835 | DIP("fnclex\n"); |
| 4836 | break; |
| 4837 | |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 4838 | case 0xE3: { |
| 4839 | /* Uses dirty helper: |
| 4840 | void x86g_do_FINIT ( VexGuestX86State* ) */ |
| 4841 | IRDirty* d = unsafeIRDirty_0_N ( |
| 4842 | 0/*regparms*/, |
| 4843 | "x86g_dirtyhelper_FINIT", |
| 4844 | &x86g_dirtyhelper_FINIT, |
florian | 9041956 | 2013-08-15 20:54:52 +0000 | [diff] [blame] | 4845 | mkIRExprVec_1(IRExpr_BBPTR()) |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 4846 | ); |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 4847 | |
| 4848 | /* declare we're writing guest state */ |
| 4849 | d->nFxState = 5; |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 4850 | vex_bzero(&d->fxState, sizeof(d->fxState)); |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 4851 | |
| 4852 | d->fxState[0].fx = Ifx_Write; |
| 4853 | d->fxState[0].offset = OFFB_FTOP; |
| 4854 | d->fxState[0].size = sizeof(UInt); |
| 4855 | |
| 4856 | d->fxState[1].fx = Ifx_Write; |
| 4857 | d->fxState[1].offset = OFFB_FPREGS; |
| 4858 | d->fxState[1].size = 8 * sizeof(ULong); |
| 4859 | |
| 4860 | d->fxState[2].fx = Ifx_Write; |
| 4861 | d->fxState[2].offset = OFFB_FPTAGS; |
| 4862 | d->fxState[2].size = 8 * sizeof(UChar); |
| 4863 | |
| 4864 | d->fxState[3].fx = Ifx_Write; |
| 4865 | d->fxState[3].offset = OFFB_FPROUND; |
| 4866 | d->fxState[3].size = sizeof(UInt); |
| 4867 | |
| 4868 | d->fxState[4].fx = Ifx_Write; |
| 4869 | d->fxState[4].offset = OFFB_FC3210; |
| 4870 | d->fxState[4].size = sizeof(UInt); |
| 4871 | |
| 4872 | stmt( IRStmt_Dirty(d) ); |
| 4873 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 4874 | DIP("fninit\n"); |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 4875 | break; |
| 4876 | } |
| 4877 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4878 | case 0xE8 ... 0xEF: /* FUCOMI %st(0),%st(?) */ |
| 4879 | fp_do_ucomi_ST0_STi( (UInt)modrm - 0xE8, False ); |
| 4880 | break; |
| 4881 | |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 4882 | case 0xF0 ... 0xF7: /* FCOMI %st(0),%st(?) */ |
| 4883 | fp_do_ucomi_ST0_STi( (UInt)modrm - 0xF0, False ); |
| 4884 | break; |
| 4885 | |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 4886 | default: |
| 4887 | goto decode_fail; |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 4888 | } |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4889 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4890 | } |
| 4891 | |
| 4892 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDC opcodes +-+-+-+-+-+-+-+ */ |
| 4893 | else |
| 4894 | if (first_opcode == 0xDC) { |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4895 | if (modrm < 0xC0) { |
| 4896 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 4897 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 4898 | specifies an address. */ |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4899 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 4900 | delta += len; |
| 4901 | |
| 4902 | switch (gregOfRM(modrm)) { |
| 4903 | |
| 4904 | case 0: /* FADD double-real */ |
| 4905 | fp_do_op_mem_ST_0 ( addr, "add", dis_buf, Iop_AddF64, True ); |
| 4906 | break; |
| 4907 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4908 | case 1: /* FMUL double-real */ |
| 4909 | fp_do_op_mem_ST_0 ( addr, "mul", dis_buf, Iop_MulF64, True ); |
| 4910 | break; |
| 4911 | |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 4912 | case 2: /* FCOM double-real */ |
| 4913 | DIP("fcoml %s\n", dis_buf); |
| 4914 | /* This forces C1 to zero, which isn't right. */ |
| 4915 | put_C3210( |
| 4916 | binop( Iop_And32, |
| 4917 | binop(Iop_Shl32, |
| 4918 | binop(Iop_CmpF64, |
| 4919 | get_ST(0), |
| 4920 | loadLE(Ity_F64,mkexpr(addr))), |
| 4921 | mkU8(8)), |
| 4922 | mkU32(0x4500) |
| 4923 | )); |
| 4924 | break; |
| 4925 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4926 | case 3: /* FCOMP double-real */ |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 4927 | DIP("fcompl %s\n", dis_buf); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4928 | /* This forces C1 to zero, which isn't right. */ |
| 4929 | put_C3210( |
| 4930 | binop( Iop_And32, |
| 4931 | binop(Iop_Shl32, |
| 4932 | binop(Iop_CmpF64, |
| 4933 | get_ST(0), |
| 4934 | loadLE(Ity_F64,mkexpr(addr))), |
| 4935 | mkU8(8)), |
| 4936 | mkU32(0x4500) |
| 4937 | )); |
| 4938 | fp_pop(); |
| 4939 | break; |
| 4940 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4941 | case 4: /* FSUB double-real */ |
| 4942 | fp_do_op_mem_ST_0 ( addr, "sub", dis_buf, Iop_SubF64, True ); |
| 4943 | break; |
| 4944 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 4945 | case 5: /* FSUBR double-real */ |
| 4946 | fp_do_oprev_mem_ST_0 ( addr, "subr", dis_buf, Iop_SubF64, True ); |
| 4947 | break; |
| 4948 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4949 | case 6: /* FDIV double-real */ |
| 4950 | fp_do_op_mem_ST_0 ( addr, "div", dis_buf, Iop_DivF64, True ); |
| 4951 | break; |
| 4952 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 4953 | case 7: /* FDIVR double-real */ |
| 4954 | fp_do_oprev_mem_ST_0 ( addr, "divr", dis_buf, Iop_DivF64, True ); |
| 4955 | break; |
| 4956 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4957 | default: |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 4958 | vex_printf("unhandled opc_aux = 0x%2x\n", (UInt)gregOfRM(modrm)); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4959 | vex_printf("first_opcode == 0xDC\n"); |
| 4960 | goto decode_fail; |
| 4961 | } |
| 4962 | |
| 4963 | } else { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4964 | |
| 4965 | delta++; |
| 4966 | switch (modrm) { |
| 4967 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 4968 | case 0xC0 ... 0xC7: /* FADD %st(0),%st(?) */ |
| 4969 | fp_do_op_ST_ST ( "add", Iop_AddF64, 0, modrm - 0xC0, False ); |
| 4970 | break; |
| 4971 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4972 | case 0xC8 ... 0xCF: /* FMUL %st(0),%st(?) */ |
| 4973 | fp_do_op_ST_ST ( "mul", Iop_MulF64, 0, modrm - 0xC8, False ); |
| 4974 | break; |
| 4975 | |
sewardj | 4734104 | 2004-09-19 11:55:46 +0000 | [diff] [blame] | 4976 | case 0xE0 ... 0xE7: /* FSUBR %st(0),%st(?) */ |
| 4977 | fp_do_oprev_ST_ST ( "subr", Iop_SubF64, 0, modrm - 0xE0, False ); |
| 4978 | break; |
| 4979 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 4980 | case 0xE8 ... 0xEF: /* FSUB %st(0),%st(?) */ |
| 4981 | fp_do_op_ST_ST ( "sub", Iop_SubF64, 0, modrm - 0xE8, False ); |
| 4982 | break; |
| 4983 | |
sewardj | a0d48d6 | 2004-09-20 21:19:03 +0000 | [diff] [blame] | 4984 | case 0xF0 ... 0xF7: /* FDIVR %st(0),%st(?) */ |
| 4985 | fp_do_oprev_ST_ST ( "divr", Iop_DivF64, 0, modrm - 0xF0, False ); |
| 4986 | break; |
| 4987 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4988 | case 0xF8 ... 0xFF: /* FDIV %st(0),%st(?) */ |
| 4989 | fp_do_op_ST_ST ( "div", Iop_DivF64, 0, modrm - 0xF8, False ); |
| 4990 | break; |
| 4991 | |
| 4992 | default: |
| 4993 | goto decode_fail; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 4994 | } |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 4995 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 4996 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 4997 | } |
| 4998 | |
| 4999 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDD opcodes +-+-+-+-+-+-+-+ */ |
| 5000 | else |
| 5001 | if (first_opcode == 0xDD) { |
| 5002 | |
| 5003 | if (modrm < 0xC0) { |
| 5004 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5005 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5006 | specifies an address. */ |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 5007 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5008 | delta += len; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5009 | |
| 5010 | switch (gregOfRM(modrm)) { |
| 5011 | |
| 5012 | case 0: /* FLD double-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5013 | DIP("fldl %s\n", dis_buf); |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 5014 | fp_push(); |
sewardj | af1ceca | 2005-06-30 23:31:27 +0000 | [diff] [blame] | 5015 | put_ST(0, loadLE(Ity_F64, mkexpr(addr))); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 5016 | break; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5017 | |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 5018 | case 1: /* FISTTPQ m64 (SSE3) */ |
| 5019 | DIP("fistppll %s\n", dis_buf); |
| 5020 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5021 | binop(Iop_F64toI64S, mkU32(Irrm_ZERO), get_ST(0)) ); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 5022 | fp_pop(); |
| 5023 | break; |
| 5024 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5025 | case 2: /* FST double-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5026 | DIP("fstl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5027 | storeLE(mkexpr(addr), get_ST(0)); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5028 | break; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5029 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 5030 | case 3: /* FSTP double-real */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5031 | DIP("fstpl %s\n", dis_buf); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5032 | storeLE(mkexpr(addr), get_ST(0)); |
| 5033 | fp_pop(); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 5034 | break; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5035 | |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5036 | case 4: { /* FRSTOR m108 */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 5037 | /* Uses dirty helper: |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 5038 | VexEmNote x86g_do_FRSTOR ( VexGuestX86State*, Addr32 ) */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 5039 | IRTemp ew = newTemp(Ity_I32); |
| 5040 | IRDirty* d = unsafeIRDirty_0_N ( |
| 5041 | 0/*regparms*/, |
| 5042 | "x86g_dirtyhelper_FRSTOR", |
| 5043 | &x86g_dirtyhelper_FRSTOR, |
florian | 9041956 | 2013-08-15 20:54:52 +0000 | [diff] [blame] | 5044 | mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) ) |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 5045 | ); |
sewardj | 74142b8 | 2013-08-08 10:28:59 +0000 | [diff] [blame] | 5046 | d->tmp = ew; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5047 | /* declare we're reading memory */ |
| 5048 | d->mFx = Ifx_Read; |
| 5049 | d->mAddr = mkexpr(addr); |
| 5050 | d->mSize = 108; |
| 5051 | |
| 5052 | /* declare we're writing guest state */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 5053 | d->nFxState = 5; |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 5054 | vex_bzero(&d->fxState, sizeof(d->fxState)); |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5055 | |
| 5056 | d->fxState[0].fx = Ifx_Write; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5057 | d->fxState[0].offset = OFFB_FTOP; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5058 | d->fxState[0].size = sizeof(UInt); |
| 5059 | |
| 5060 | d->fxState[1].fx = Ifx_Write; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5061 | d->fxState[1].offset = OFFB_FPREGS; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5062 | d->fxState[1].size = 8 * sizeof(ULong); |
| 5063 | |
| 5064 | d->fxState[2].fx = Ifx_Write; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5065 | d->fxState[2].offset = OFFB_FPTAGS; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5066 | d->fxState[2].size = 8 * sizeof(UChar); |
| 5067 | |
| 5068 | d->fxState[3].fx = Ifx_Write; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5069 | d->fxState[3].offset = OFFB_FPROUND; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5070 | d->fxState[3].size = sizeof(UInt); |
| 5071 | |
| 5072 | d->fxState[4].fx = Ifx_Write; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5073 | d->fxState[4].offset = OFFB_FC3210; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5074 | d->fxState[4].size = sizeof(UInt); |
| 5075 | |
| 5076 | stmt( IRStmt_Dirty(d) ); |
| 5077 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 5078 | /* ew contains any emulation warning we may need to |
| 5079 | issue. If needed, side-exit to the next insn, |
| 5080 | reporting the warning, so that Valgrind's dispatcher |
| 5081 | sees the warning. */ |
| 5082 | put_emwarn( mkexpr(ew) ); |
| 5083 | stmt( |
| 5084 | IRStmt_Exit( |
| 5085 | binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)), |
| 5086 | Ijk_EmWarn, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 5087 | IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta), |
| 5088 | OFFB_EIP |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 5089 | ) |
| 5090 | ); |
| 5091 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5092 | DIP("frstor %s\n", dis_buf); |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5093 | break; |
| 5094 | } |
| 5095 | |
| 5096 | case 6: { /* FNSAVE m108 */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 5097 | /* Uses dirty helper: |
| 5098 | void x86g_do_FSAVE ( VexGuestX86State*, UInt ) */ |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5099 | IRDirty* d = unsafeIRDirty_0_N ( |
| 5100 | 0/*regparms*/, |
| 5101 | "x86g_dirtyhelper_FSAVE", |
| 5102 | &x86g_dirtyhelper_FSAVE, |
florian | 9041956 | 2013-08-15 20:54:52 +0000 | [diff] [blame] | 5103 | mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) ) |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5104 | ); |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5105 | /* declare we're writing memory */ |
| 5106 | d->mFx = Ifx_Write; |
| 5107 | d->mAddr = mkexpr(addr); |
| 5108 | d->mSize = 108; |
| 5109 | |
| 5110 | /* declare we're reading guest state */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 5111 | d->nFxState = 5; |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 5112 | vex_bzero(&d->fxState, sizeof(d->fxState)); |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5113 | |
| 5114 | d->fxState[0].fx = Ifx_Read; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5115 | d->fxState[0].offset = OFFB_FTOP; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5116 | d->fxState[0].size = sizeof(UInt); |
| 5117 | |
| 5118 | d->fxState[1].fx = Ifx_Read; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5119 | d->fxState[1].offset = OFFB_FPREGS; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5120 | d->fxState[1].size = 8 * sizeof(ULong); |
| 5121 | |
| 5122 | d->fxState[2].fx = Ifx_Read; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5123 | d->fxState[2].offset = OFFB_FPTAGS; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5124 | d->fxState[2].size = 8 * sizeof(UChar); |
| 5125 | |
| 5126 | d->fxState[3].fx = Ifx_Read; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5127 | d->fxState[3].offset = OFFB_FPROUND; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5128 | d->fxState[3].size = sizeof(UInt); |
| 5129 | |
| 5130 | d->fxState[4].fx = Ifx_Read; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5131 | d->fxState[4].offset = OFFB_FC3210; |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5132 | d->fxState[4].size = sizeof(UInt); |
| 5133 | |
| 5134 | stmt( IRStmt_Dirty(d) ); |
| 5135 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5136 | DIP("fnsave %s\n", dis_buf); |
sewardj | 9fc9e78 | 2004-11-26 17:57:40 +0000 | [diff] [blame] | 5137 | break; |
| 5138 | } |
| 5139 | |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 5140 | case 7: { /* FNSTSW m16 */ |
| 5141 | IRExpr* sw = get_FPU_sw(); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 5142 | vassert(typeOfIRExpr(irsb->tyenv, sw) == Ity_I16); |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 5143 | storeLE( mkexpr(addr), sw ); |
| 5144 | DIP("fnstsw %s\n", dis_buf); |
| 5145 | break; |
| 5146 | } |
| 5147 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5148 | default: |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 5149 | vex_printf("unhandled opc_aux = 0x%2x\n", (UInt)gregOfRM(modrm)); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 5150 | vex_printf("first_opcode == 0xDD\n"); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5151 | goto decode_fail; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 5152 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5153 | } else { |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 5154 | delta++; |
| 5155 | switch (modrm) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5156 | |
sewardj | 3ddedc4 | 2005-03-25 20:30:00 +0000 | [diff] [blame] | 5157 | case 0xC0 ... 0xC7: /* FFREE %st(?) */ |
| 5158 | r_dst = (UInt)modrm - 0xC0; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 5159 | DIP("ffree %%st(%u)\n", r_dst); |
sewardj | 3ddedc4 | 2005-03-25 20:30:00 +0000 | [diff] [blame] | 5160 | put_ST_TAG ( r_dst, mkU8(0) ); |
| 5161 | break; |
| 5162 | |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 5163 | case 0xD0 ... 0xD7: /* FST %st(0),%st(?) */ |
| 5164 | r_dst = (UInt)modrm - 0xD0; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 5165 | DIP("fst %%st(0),%%st(%u)\n", r_dst); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5166 | /* P4 manual says: "If the destination operand is a |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 5167 | non-empty register, the invalid-operation exception |
| 5168 | is not generated. Hence put_ST_UNCHECKED. */ |
| 5169 | put_ST_UNCHECKED(r_dst, get_ST(0)); |
| 5170 | break; |
| 5171 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 5172 | case 0xD8 ... 0xDF: /* FSTP %st(0),%st(?) */ |
| 5173 | r_dst = (UInt)modrm - 0xD8; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 5174 | DIP("fstp %%st(0),%%st(%u)\n", r_dst); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5175 | /* P4 manual says: "If the destination operand is a |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 5176 | non-empty register, the invalid-operation exception |
| 5177 | is not generated. Hence put_ST_UNCHECKED. */ |
| 5178 | put_ST_UNCHECKED(r_dst, get_ST(0)); |
| 5179 | fp_pop(); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 5180 | break; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5181 | |
| 5182 | case 0xE0 ... 0xE7: /* FUCOM %st(0),%st(?) */ |
| 5183 | r_dst = (UInt)modrm - 0xE0; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 5184 | DIP("fucom %%st(0),%%st(%u)\n", r_dst); |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 5185 | /* This forces C1 to zero, which isn't right. */ |
| 5186 | put_C3210( |
| 5187 | binop( Iop_And32, |
| 5188 | binop(Iop_Shl32, |
| 5189 | binop(Iop_CmpF64, get_ST(0), get_ST(r_dst)), |
| 5190 | mkU8(8)), |
| 5191 | mkU32(0x4500) |
| 5192 | )); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5193 | break; |
| 5194 | |
| 5195 | case 0xE8 ... 0xEF: /* FUCOMP %st(0),%st(?) */ |
| 5196 | r_dst = (UInt)modrm - 0xE8; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 5197 | DIP("fucomp %%st(0),%%st(%u)\n", r_dst); |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 5198 | /* This forces C1 to zero, which isn't right. */ |
| 5199 | put_C3210( |
| 5200 | binop( Iop_And32, |
| 5201 | binop(Iop_Shl32, |
| 5202 | binop(Iop_CmpF64, get_ST(0), get_ST(r_dst)), |
| 5203 | mkU8(8)), |
| 5204 | mkU32(0x4500) |
| 5205 | )); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5206 | fp_pop(); |
| 5207 | break; |
| 5208 | |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5209 | default: |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 5210 | goto decode_fail; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5211 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5212 | } |
| 5213 | } |
| 5214 | |
| 5215 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDE opcodes +-+-+-+-+-+-+-+ */ |
| 5216 | else |
| 5217 | if (first_opcode == 0xDE) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5218 | |
| 5219 | if (modrm < 0xC0) { |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5220 | |
| 5221 | /* bits 5,4,3 are an opcode extension, and the modRM also |
| 5222 | specifies an address. */ |
| 5223 | IROp fop; |
| 5224 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5225 | delta += len; |
| 5226 | |
| 5227 | switch (gregOfRM(modrm)) { |
| 5228 | |
| 5229 | case 0: /* FIADD m16int */ /* ST(0) += m16int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5230 | DIP("fiaddw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5231 | fop = Iop_AddF64; |
| 5232 | goto do_fop_m16; |
| 5233 | |
| 5234 | case 1: /* FIMUL m16int */ /* ST(0) *= m16int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5235 | DIP("fimulw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5236 | fop = Iop_MulF64; |
| 5237 | goto do_fop_m16; |
| 5238 | |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 5239 | case 2: /* FICOM m16int */ |
| 5240 | DIP("ficomw %s\n", dis_buf); |
| 5241 | /* This forces C1 to zero, which isn't right. */ |
| 5242 | put_C3210( |
| 5243 | binop( Iop_And32, |
| 5244 | binop(Iop_Shl32, |
| 5245 | binop(Iop_CmpF64, |
| 5246 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5247 | unop(Iop_I32StoF64, |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 5248 | unop(Iop_16Sto32, |
| 5249 | loadLE(Ity_I16,mkexpr(addr))))), |
| 5250 | mkU8(8)), |
| 5251 | mkU32(0x4500) |
| 5252 | )); |
| 5253 | break; |
| 5254 | |
| 5255 | case 3: /* FICOMP m16int */ |
| 5256 | DIP("ficompw %s\n", dis_buf); |
| 5257 | /* This forces C1 to zero, which isn't right. */ |
| 5258 | put_C3210( |
| 5259 | binop( Iop_And32, |
| 5260 | binop(Iop_Shl32, |
| 5261 | binop(Iop_CmpF64, |
| 5262 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5263 | unop(Iop_I32StoF64, |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 5264 | unop(Iop_16Sto32, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 5265 | loadLE(Ity_I16,mkexpr(addr))))), |
sewardj | 071895f | 2005-07-29 11:28:38 +0000 | [diff] [blame] | 5266 | mkU8(8)), |
| 5267 | mkU32(0x4500) |
| 5268 | )); |
| 5269 | fp_pop(); |
| 5270 | break; |
| 5271 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5272 | case 4: /* FISUB m16int */ /* ST(0) -= m16int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5273 | DIP("fisubw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5274 | fop = Iop_SubF64; |
| 5275 | goto do_fop_m16; |
| 5276 | |
| 5277 | case 5: /* FISUBR m16int */ /* ST(0) = m16int - ST(0) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5278 | DIP("fisubrw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5279 | fop = Iop_SubF64; |
| 5280 | goto do_foprev_m16; |
| 5281 | |
| 5282 | case 6: /* FIDIV m16int */ /* ST(0) /= m16int */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5283 | DIP("fisubw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5284 | fop = Iop_DivF64; |
| 5285 | goto do_fop_m16; |
| 5286 | |
| 5287 | case 7: /* FIDIVR m16int */ /* ST(0) = m16int / ST(0) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5288 | DIP("fidivrw %s\n", dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5289 | fop = Iop_DivF64; |
| 5290 | goto do_foprev_m16; |
| 5291 | |
| 5292 | do_fop_m16: |
| 5293 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 5294 | triop(fop, |
| 5295 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5296 | get_ST(0), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5297 | unop(Iop_I32StoF64, |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5298 | unop(Iop_16Sto32, |
| 5299 | loadLE(Ity_I16, mkexpr(addr)))))); |
| 5300 | break; |
| 5301 | |
| 5302 | do_foprev_m16: |
| 5303 | put_ST_UNCHECKED(0, |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 5304 | triop(fop, |
| 5305 | get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5306 | unop(Iop_I32StoF64, |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5307 | unop(Iop_16Sto32, |
| 5308 | loadLE(Ity_I16, mkexpr(addr)))), |
| 5309 | get_ST(0))); |
| 5310 | break; |
| 5311 | |
| 5312 | default: |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 5313 | vex_printf("unhandled opc_aux = 0x%2x\n", (UInt)gregOfRM(modrm)); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5314 | vex_printf("first_opcode == 0xDE\n"); |
| 5315 | goto decode_fail; |
| 5316 | } |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5317 | |
| 5318 | } else { |
| 5319 | |
| 5320 | delta++; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5321 | switch (modrm) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5322 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 5323 | case 0xC0 ... 0xC7: /* FADDP %st(0),%st(?) */ |
| 5324 | fp_do_op_ST_ST ( "add", Iop_AddF64, 0, modrm - 0xC0, True ); |
| 5325 | break; |
| 5326 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5327 | case 0xC8 ... 0xCF: /* FMULP %st(0),%st(?) */ |
| 5328 | fp_do_op_ST_ST ( "mul", Iop_MulF64, 0, modrm - 0xC8, True ); |
| 5329 | break; |
| 5330 | |
sewardj | e166ed0 | 2004-10-25 02:27:01 +0000 | [diff] [blame] | 5331 | case 0xD9: /* FCOMPP %st(0),%st(1) */ |
| 5332 | DIP("fuompp %%st(0),%%st(1)\n"); |
| 5333 | /* This forces C1 to zero, which isn't right. */ |
| 5334 | put_C3210( |
| 5335 | binop( Iop_And32, |
| 5336 | binop(Iop_Shl32, |
| 5337 | binop(Iop_CmpF64, get_ST(0), get_ST(1)), |
| 5338 | mkU8(8)), |
| 5339 | mkU32(0x4500) |
| 5340 | )); |
| 5341 | fp_pop(); |
| 5342 | fp_pop(); |
| 5343 | break; |
| 5344 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 5345 | case 0xE0 ... 0xE7: /* FSUBRP %st(0),%st(?) */ |
| 5346 | fp_do_oprev_ST_ST ( "subr", Iop_SubF64, 0, modrm - 0xE0, True ); |
| 5347 | break; |
| 5348 | |
sewardj | 3fd5e57 | 2004-09-09 22:43:51 +0000 | [diff] [blame] | 5349 | case 0xE8 ... 0xEF: /* FSUBP %st(0),%st(?) */ |
| 5350 | fp_do_op_ST_ST ( "sub", Iop_SubF64, 0, modrm - 0xE8, True ); |
| 5351 | break; |
| 5352 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5353 | case 0xF0 ... 0xF7: /* FDIVRP %st(0),%st(?) */ |
| 5354 | fp_do_oprev_ST_ST ( "divr", Iop_DivF64, 0, modrm - 0xF0, True ); |
| 5355 | break; |
| 5356 | |
| 5357 | case 0xF8 ... 0xFF: /* FDIVP %st(0),%st(?) */ |
| 5358 | fp_do_op_ST_ST ( "div", Iop_DivF64, 0, modrm - 0xF8, True ); |
| 5359 | break; |
| 5360 | |
| 5361 | default: |
| 5362 | goto decode_fail; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5363 | } |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5364 | |
| 5365 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5366 | } |
| 5367 | |
| 5368 | /* -+-+-+-+-+-+-+-+-+-+-+-+ 0xDF opcodes +-+-+-+-+-+-+-+ */ |
| 5369 | else |
| 5370 | if (first_opcode == 0xDF) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5371 | |
| 5372 | if (modrm < 0xC0) { |
| 5373 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5374 | /* bits 5,4,3 are an opcode extension, and the modRM also |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5375 | specifies an address. */ |
| 5376 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5377 | delta += len; |
| 5378 | |
| 5379 | switch (gregOfRM(modrm)) { |
| 5380 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 5381 | case 0: /* FILD m16int */ |
| 5382 | DIP("fildw %s\n", dis_buf); |
| 5383 | fp_push(); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5384 | put_ST(0, unop(Iop_I32StoF64, |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 5385 | unop(Iop_16Sto32, |
| 5386 | loadLE(Ity_I16, mkexpr(addr))))); |
| 5387 | break; |
| 5388 | |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 5389 | case 1: /* FISTTPS m16 (SSE3) */ |
| 5390 | DIP("fisttps %s\n", dis_buf); |
| 5391 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5392 | binop(Iop_F64toI16S, mkU32(Irrm_ZERO), get_ST(0)) ); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 5393 | fp_pop(); |
| 5394 | break; |
| 5395 | |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 5396 | case 2: /* FIST m16 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5397 | DIP("fistp %s\n", dis_buf); |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 5398 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5399 | binop(Iop_F64toI16S, get_roundingmode(), get_ST(0)) ); |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 5400 | break; |
| 5401 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5402 | case 3: /* FISTP m16 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5403 | DIP("fistps %s\n", dis_buf); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 5404 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5405 | binop(Iop_F64toI16S, get_roundingmode(), get_ST(0)) ); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 5406 | fp_pop(); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5407 | break; |
| 5408 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5409 | case 5: /* FILD m64 */ |
| 5410 | DIP("fildll %s\n", dis_buf); |
| 5411 | fp_push(); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5412 | put_ST(0, binop(Iop_I64StoF64, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 5413 | get_roundingmode(), |
| 5414 | loadLE(Ity_I64, mkexpr(addr)))); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5415 | break; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5416 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 5417 | case 7: /* FISTP m64 */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 5418 | DIP("fistpll %s\n", dis_buf); |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 5419 | storeLE( mkexpr(addr), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 5420 | binop(Iop_F64toI64S, get_roundingmode(), get_ST(0)) ); |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 5421 | fp_pop(); |
| 5422 | break; |
| 5423 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5424 | default: |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 5425 | vex_printf("unhandled opc_aux = 0x%2x\n", (UInt)gregOfRM(modrm)); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5426 | vex_printf("first_opcode == 0xDF\n"); |
| 5427 | goto decode_fail; |
| 5428 | } |
| 5429 | |
| 5430 | } else { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5431 | |
| 5432 | delta++; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5433 | switch (modrm) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5434 | |
sewardj | 8fb8869 | 2005-07-29 11:57:00 +0000 | [diff] [blame] | 5435 | case 0xC0: /* FFREEP %st(0) */ |
| 5436 | DIP("ffreep %%st(%d)\n", 0); |
| 5437 | put_ST_TAG ( 0, mkU8(0) ); |
| 5438 | fp_pop(); |
| 5439 | break; |
| 5440 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5441 | case 0xE0: /* FNSTSW %ax */ |
| 5442 | DIP("fnstsw %%ax\n"); |
sewardj | d24931d | 2005-03-20 12:51:39 +0000 | [diff] [blame] | 5443 | /* Get the FPU status word value and dump it in %AX. */ |
sewardj | 1d2e77f | 2008-06-04 09:10:38 +0000 | [diff] [blame] | 5444 | if (0) { |
| 5445 | /* The obvious thing to do is simply dump the 16-bit |
| 5446 | status word value in %AX. However, due to a |
| 5447 | limitation in Memcheck's origin tracking |
| 5448 | machinery, this causes Memcheck not to track the |
| 5449 | origin of any undefinedness into %AH (only into |
| 5450 | %AL/%AX/%EAX), which means origins are lost in |
| 5451 | the sequence "fnstsw %ax; test $M,%ah; jcond .." */ |
| 5452 | putIReg(2, R_EAX, get_FPU_sw()); |
| 5453 | } else { |
| 5454 | /* So a somewhat lame kludge is to make it very |
| 5455 | clear to Memcheck that the value is written to |
| 5456 | both %AH and %AL. This generates marginally |
| 5457 | worse code, but I don't think it matters much. */ |
| 5458 | IRTemp t16 = newTemp(Ity_I16); |
| 5459 | assign(t16, get_FPU_sw()); |
| 5460 | putIReg( 1, R_AL, unop(Iop_16to8, mkexpr(t16)) ); |
| 5461 | putIReg( 1, R_AH, unop(Iop_16HIto8, mkexpr(t16)) ); |
| 5462 | } |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5463 | break; |
| 5464 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 5465 | case 0xE8 ... 0xEF: /* FUCOMIP %st(0),%st(?) */ |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 5466 | fp_do_ucomi_ST0_STi( (UInt)modrm - 0xE8, True ); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 5467 | break; |
| 5468 | |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 5469 | case 0xF0 ... 0xF7: /* FCOMIP %st(0),%st(?) */ |
| 5470 | /* not really right since COMIP != UCOMIP */ |
| 5471 | fp_do_ucomi_ST0_STi( (UInt)modrm - 0xF0, True ); |
| 5472 | break; |
| 5473 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 5474 | default: |
| 5475 | goto decode_fail; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 5476 | } |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 5477 | } |
| 5478 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5479 | } |
| 5480 | |
| 5481 | else |
| 5482 | vpanic("dis_FPU(x86): invalid primary opcode"); |
| 5483 | |
sewardj | 69d9d66 | 2004-10-14 21:58:52 +0000 | [diff] [blame] | 5484 | *decode_ok = True; |
| 5485 | return delta; |
| 5486 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 5487 | decode_fail: |
| 5488 | *decode_ok = False; |
| 5489 | return delta; |
| 5490 | } |
| 5491 | |
| 5492 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5493 | /*------------------------------------------------------------*/ |
| 5494 | /*--- ---*/ |
| 5495 | /*--- MMX INSTRUCTIONS ---*/ |
| 5496 | /*--- ---*/ |
| 5497 | /*------------------------------------------------------------*/ |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 5498 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5499 | /* Effect of MMX insns on x87 FPU state (table 11-2 of |
| 5500 | IA32 arch manual, volume 3): |
| 5501 | |
| 5502 | Read from, or write to MMX register (viz, any insn except EMMS): |
| 5503 | * All tags set to Valid (non-empty) -- FPTAGS[i] := nonzero |
| 5504 | * FP stack pointer set to zero |
| 5505 | |
| 5506 | EMMS: |
| 5507 | * All tags set to Invalid (empty) -- FPTAGS[i] := zero |
| 5508 | * FP stack pointer set to zero |
| 5509 | */ |
| 5510 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 5511 | static void do_MMX_preamble ( void ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5512 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 5513 | Int i; |
| 5514 | IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 ); |
| 5515 | IRExpr* zero = mkU32(0); |
| 5516 | IRExpr* tag1 = mkU8(1); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5517 | put_ftop(zero); |
| 5518 | for (i = 0; i < 8; i++) |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 5519 | stmt( IRStmt_PutI( mkIRPutI(descr, zero, i, tag1) ) ); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5520 | } |
| 5521 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 5522 | static void do_EMMS_preamble ( void ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5523 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 5524 | Int i; |
| 5525 | IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 ); |
| 5526 | IRExpr* zero = mkU32(0); |
| 5527 | IRExpr* tag0 = mkU8(0); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5528 | put_ftop(zero); |
| 5529 | for (i = 0; i < 8; i++) |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 5530 | stmt( IRStmt_PutI( mkIRPutI(descr, zero, i, tag0) ) ); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5531 | } |
| 5532 | |
| 5533 | |
| 5534 | static IRExpr* getMMXReg ( UInt archreg ) |
| 5535 | { |
| 5536 | vassert(archreg < 8); |
| 5537 | return IRExpr_Get( OFFB_FPREGS + 8 * archreg, Ity_I64 ); |
| 5538 | } |
| 5539 | |
| 5540 | |
| 5541 | static void putMMXReg ( UInt archreg, IRExpr* e ) |
| 5542 | { |
| 5543 | vassert(archreg < 8); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 5544 | vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I64); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5545 | stmt( IRStmt_Put( OFFB_FPREGS + 8 * archreg, e ) ); |
| 5546 | } |
| 5547 | |
| 5548 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5549 | /* Helper for non-shift MMX insns. Note this is incomplete in the |
| 5550 | sense that it does not first call do_MMX_preamble() -- that is the |
| 5551 | responsibility of its caller. */ |
| 5552 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5553 | static |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5554 | UInt dis_MMXop_regmem_to_reg ( UChar sorb, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 5555 | Int delta, |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5556 | UChar opc, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 5557 | const HChar* name, |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5558 | Bool show_granularity ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5559 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5560 | HChar dis_buf[50]; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5561 | UChar modrm = getIByte(delta); |
| 5562 | Bool isReg = epartIsReg(modrm); |
| 5563 | IRExpr* argL = NULL; |
| 5564 | IRExpr* argR = NULL; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5565 | IRExpr* argG = NULL; |
| 5566 | IRExpr* argE = NULL; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5567 | IRTemp res = newTemp(Ity_I64); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5568 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5569 | Bool invG = False; |
| 5570 | IROp op = Iop_INVALID; |
| 5571 | void* hAddr = NULL; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5572 | Bool eLeft = False; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 5573 | const HChar* hName = NULL; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5574 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5575 | # define XXX(_name) do { hAddr = &_name; hName = #_name; } while (0) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5576 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5577 | switch (opc) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 5578 | /* Original MMX ones */ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5579 | case 0xFC: op = Iop_Add8x8; break; |
| 5580 | case 0xFD: op = Iop_Add16x4; break; |
| 5581 | case 0xFE: op = Iop_Add32x2; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5582 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5583 | case 0xEC: op = Iop_QAdd8Sx8; break; |
| 5584 | case 0xED: op = Iop_QAdd16Sx4; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5585 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5586 | case 0xDC: op = Iop_QAdd8Ux8; break; |
| 5587 | case 0xDD: op = Iop_QAdd16Ux4; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5588 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5589 | case 0xF8: op = Iop_Sub8x8; break; |
| 5590 | case 0xF9: op = Iop_Sub16x4; break; |
| 5591 | case 0xFA: op = Iop_Sub32x2; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5592 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5593 | case 0xE8: op = Iop_QSub8Sx8; break; |
| 5594 | case 0xE9: op = Iop_QSub16Sx4; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5595 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5596 | case 0xD8: op = Iop_QSub8Ux8; break; |
| 5597 | case 0xD9: op = Iop_QSub16Ux4; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5598 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5599 | case 0xE5: op = Iop_MulHi16Sx4; break; |
| 5600 | case 0xD5: op = Iop_Mul16x4; break; |
| 5601 | case 0xF5: XXX(x86g_calculate_mmx_pmaddwd); break; |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5602 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5603 | case 0x74: op = Iop_CmpEQ8x8; break; |
| 5604 | case 0x75: op = Iop_CmpEQ16x4; break; |
| 5605 | case 0x76: op = Iop_CmpEQ32x2; break; |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5606 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5607 | case 0x64: op = Iop_CmpGT8Sx8; break; |
| 5608 | case 0x65: op = Iop_CmpGT16Sx4; break; |
| 5609 | case 0x66: op = Iop_CmpGT32Sx2; break; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5610 | |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 5611 | case 0x6B: op = Iop_QNarrowBin32Sto16Sx4; eLeft = True; break; |
| 5612 | case 0x63: op = Iop_QNarrowBin16Sto8Sx8; eLeft = True; break; |
| 5613 | case 0x67: op = Iop_QNarrowBin16Sto8Ux8; eLeft = True; break; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5614 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5615 | case 0x68: op = Iop_InterleaveHI8x8; eLeft = True; break; |
| 5616 | case 0x69: op = Iop_InterleaveHI16x4; eLeft = True; break; |
| 5617 | case 0x6A: op = Iop_InterleaveHI32x2; eLeft = True; break; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5618 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5619 | case 0x60: op = Iop_InterleaveLO8x8; eLeft = True; break; |
| 5620 | case 0x61: op = Iop_InterleaveLO16x4; eLeft = True; break; |
| 5621 | case 0x62: op = Iop_InterleaveLO32x2; eLeft = True; break; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5622 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5623 | case 0xDB: op = Iop_And64; break; |
| 5624 | case 0xDF: op = Iop_And64; invG = True; break; |
| 5625 | case 0xEB: op = Iop_Or64; break; |
| 5626 | case 0xEF: /* Possibly do better here if argL and argR are the |
| 5627 | same reg */ |
| 5628 | op = Iop_Xor64; break; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5629 | |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 5630 | /* Introduced in SSE1 */ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5631 | case 0xE0: op = Iop_Avg8Ux8; break; |
| 5632 | case 0xE3: op = Iop_Avg16Ux4; break; |
| 5633 | case 0xEE: op = Iop_Max16Sx4; break; |
| 5634 | case 0xDE: op = Iop_Max8Ux8; break; |
| 5635 | case 0xEA: op = Iop_Min16Sx4; break; |
| 5636 | case 0xDA: op = Iop_Min8Ux8; break; |
| 5637 | case 0xE4: op = Iop_MulHi16Ux4; break; |
| 5638 | case 0xF6: XXX(x86g_calculate_mmx_psadbw); break; |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 5639 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 5640 | /* Introduced in SSE2 */ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5641 | case 0xD4: op = Iop_Add64; break; |
| 5642 | case 0xFB: op = Iop_Sub64; break; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 5643 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5644 | default: |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 5645 | vex_printf("\n0x%x\n", opc); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5646 | vpanic("dis_MMXop_regmem_to_reg"); |
| 5647 | } |
| 5648 | |
| 5649 | # undef XXX |
| 5650 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5651 | argG = getMMXReg(gregOfRM(modrm)); |
| 5652 | if (invG) |
| 5653 | argG = unop(Iop_Not64, argG); |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5654 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5655 | if (isReg) { |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5656 | delta++; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5657 | argE = getMMXReg(eregOfRM(modrm)); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5658 | } else { |
| 5659 | Int len; |
| 5660 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5661 | delta += len; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5662 | argE = loadLE(Ity_I64, mkexpr(addr)); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5663 | } |
| 5664 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5665 | if (eLeft) { |
| 5666 | argL = argE; |
| 5667 | argR = argG; |
| 5668 | } else { |
| 5669 | argL = argG; |
| 5670 | argR = argE; |
| 5671 | } |
| 5672 | |
| 5673 | if (op != Iop_INVALID) { |
| 5674 | vassert(hName == NULL); |
| 5675 | vassert(hAddr == NULL); |
| 5676 | assign(res, binop(op, argL, argR)); |
| 5677 | } else { |
| 5678 | vassert(hName != NULL); |
| 5679 | vassert(hAddr != NULL); |
| 5680 | assign( res, |
| 5681 | mkIRExprCCall( |
| 5682 | Ity_I64, |
| 5683 | 0/*regparms*/, hName, hAddr, |
| 5684 | mkIRExprVec_2( argL, argR ) |
| 5685 | ) |
| 5686 | ); |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 5687 | } |
| 5688 | |
| 5689 | putMMXReg( gregOfRM(modrm), mkexpr(res) ); |
| 5690 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5691 | DIP("%s%s %s, %s\n", |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5692 | name, show_granularity ? nameMMXGran(opc & 3) : "", |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5693 | ( isReg ? nameMMXReg(eregOfRM(modrm)) : dis_buf ), |
| 5694 | nameMMXReg(gregOfRM(modrm)) ); |
| 5695 | |
| 5696 | return delta; |
| 5697 | } |
| 5698 | |
| 5699 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5700 | /* Vector by scalar shift of G by the amount specified at the bottom |
| 5701 | of E. This is a straight copy of dis_SSE_shiftG_byE. */ |
| 5702 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 5703 | static UInt dis_MMX_shiftG_byE ( UChar sorb, Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 5704 | const HChar* opname, IROp op ) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5705 | { |
| 5706 | HChar dis_buf[50]; |
| 5707 | Int alen, size; |
| 5708 | IRTemp addr; |
| 5709 | Bool shl, shr, sar; |
| 5710 | UChar rm = getIByte(delta); |
| 5711 | IRTemp g0 = newTemp(Ity_I64); |
| 5712 | IRTemp g1 = newTemp(Ity_I64); |
| 5713 | IRTemp amt = newTemp(Ity_I32); |
| 5714 | IRTemp amt8 = newTemp(Ity_I8); |
| 5715 | |
| 5716 | if (epartIsReg(rm)) { |
| 5717 | assign( amt, unop(Iop_64to32, getMMXReg(eregOfRM(rm))) ); |
| 5718 | DIP("%s %s,%s\n", opname, |
| 5719 | nameMMXReg(eregOfRM(rm)), |
| 5720 | nameMMXReg(gregOfRM(rm)) ); |
| 5721 | delta++; |
| 5722 | } else { |
| 5723 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 5724 | assign( amt, loadLE(Ity_I32, mkexpr(addr)) ); |
| 5725 | DIP("%s %s,%s\n", opname, |
| 5726 | dis_buf, |
| 5727 | nameMMXReg(gregOfRM(rm)) ); |
| 5728 | delta += alen; |
| 5729 | } |
| 5730 | assign( g0, getMMXReg(gregOfRM(rm)) ); |
| 5731 | assign( amt8, unop(Iop_32to8, mkexpr(amt)) ); |
| 5732 | |
| 5733 | shl = shr = sar = False; |
| 5734 | size = 0; |
| 5735 | switch (op) { |
| 5736 | case Iop_ShlN16x4: shl = True; size = 32; break; |
| 5737 | case Iop_ShlN32x2: shl = True; size = 32; break; |
| 5738 | case Iop_Shl64: shl = True; size = 64; break; |
| 5739 | case Iop_ShrN16x4: shr = True; size = 16; break; |
| 5740 | case Iop_ShrN32x2: shr = True; size = 32; break; |
| 5741 | case Iop_Shr64: shr = True; size = 64; break; |
| 5742 | case Iop_SarN16x4: sar = True; size = 16; break; |
| 5743 | case Iop_SarN32x2: sar = True; size = 32; break; |
| 5744 | default: vassert(0); |
| 5745 | } |
| 5746 | |
| 5747 | if (shl || shr) { |
| 5748 | assign( |
| 5749 | g1, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 5750 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 5751 | binop(Iop_CmpLT32U,mkexpr(amt),mkU32(size)), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 5752 | binop(op, mkexpr(g0), mkexpr(amt8)), |
| 5753 | mkU64(0) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5754 | ) |
| 5755 | ); |
| 5756 | } else |
| 5757 | if (sar) { |
| 5758 | assign( |
| 5759 | g1, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 5760 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 5761 | binop(Iop_CmpLT32U,mkexpr(amt),mkU32(size)), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 5762 | binop(op, mkexpr(g0), mkexpr(amt8)), |
| 5763 | binop(op, mkexpr(g0), mkU8(size-1)) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5764 | ) |
| 5765 | ); |
| 5766 | } else { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 5767 | /*NOTREACHED*/ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5768 | vassert(0); |
| 5769 | } |
| 5770 | |
| 5771 | putMMXReg( gregOfRM(rm), mkexpr(g1) ); |
| 5772 | return delta; |
| 5773 | } |
| 5774 | |
| 5775 | |
| 5776 | /* Vector by scalar shift of E by an immediate byte. This is a |
| 5777 | straight copy of dis_SSE_shiftE_imm. */ |
| 5778 | |
| 5779 | static |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 5780 | UInt dis_MMX_shiftE_imm ( Int delta, const HChar* opname, IROp op ) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5781 | { |
| 5782 | Bool shl, shr, sar; |
| 5783 | UChar rm = getIByte(delta); |
| 5784 | IRTemp e0 = newTemp(Ity_I64); |
| 5785 | IRTemp e1 = newTemp(Ity_I64); |
| 5786 | UChar amt, size; |
| 5787 | vassert(epartIsReg(rm)); |
| 5788 | vassert(gregOfRM(rm) == 2 |
| 5789 | || gregOfRM(rm) == 4 || gregOfRM(rm) == 6); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 5790 | amt = getIByte(delta+1); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5791 | delta += 2; |
| 5792 | DIP("%s $%d,%s\n", opname, |
| 5793 | (Int)amt, |
| 5794 | nameMMXReg(eregOfRM(rm)) ); |
| 5795 | |
| 5796 | assign( e0, getMMXReg(eregOfRM(rm)) ); |
| 5797 | |
| 5798 | shl = shr = sar = False; |
| 5799 | size = 0; |
| 5800 | switch (op) { |
| 5801 | case Iop_ShlN16x4: shl = True; size = 16; break; |
| 5802 | case Iop_ShlN32x2: shl = True; size = 32; break; |
| 5803 | case Iop_Shl64: shl = True; size = 64; break; |
| 5804 | case Iop_SarN16x4: sar = True; size = 16; break; |
| 5805 | case Iop_SarN32x2: sar = True; size = 32; break; |
| 5806 | case Iop_ShrN16x4: shr = True; size = 16; break; |
| 5807 | case Iop_ShrN32x2: shr = True; size = 32; break; |
| 5808 | case Iop_Shr64: shr = True; size = 64; break; |
| 5809 | default: vassert(0); |
| 5810 | } |
| 5811 | |
| 5812 | if (shl || shr) { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 5813 | assign( e1, amt >= size |
| 5814 | ? mkU64(0) |
| 5815 | : binop(op, mkexpr(e0), mkU8(amt)) |
| 5816 | ); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5817 | } else |
| 5818 | if (sar) { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 5819 | assign( e1, amt >= size |
| 5820 | ? binop(op, mkexpr(e0), mkU8(size-1)) |
| 5821 | : binop(op, mkexpr(e0), mkU8(amt)) |
| 5822 | ); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5823 | } else { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 5824 | /*NOTREACHED*/ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 5825 | vassert(0); |
| 5826 | } |
| 5827 | |
| 5828 | putMMXReg( eregOfRM(rm), mkexpr(e1) ); |
| 5829 | return delta; |
| 5830 | } |
| 5831 | |
| 5832 | |
| 5833 | /* Completely handle all MMX instructions except emms. */ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5834 | |
| 5835 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 5836 | UInt dis_MMX ( Bool* decode_ok, UChar sorb, Int sz, Int delta ) |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5837 | { |
| 5838 | Int len; |
| 5839 | UChar modrm; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 5840 | HChar dis_buf[50]; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5841 | UChar opc = getIByte(delta); |
| 5842 | delta++; |
| 5843 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 5844 | /* dis_MMX handles all insns except emms. */ |
| 5845 | do_MMX_preamble(); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5846 | |
| 5847 | switch (opc) { |
| 5848 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5849 | case 0x6E: |
| 5850 | /* MOVD (src)ireg-or-mem (E), (dst)mmxreg (G)*/ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5851 | if (sz != 4) |
| 5852 | goto mmx_decode_failure; |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5853 | modrm = getIByte(delta); |
| 5854 | if (epartIsReg(modrm)) { |
| 5855 | delta++; |
| 5856 | putMMXReg( |
| 5857 | gregOfRM(modrm), |
| 5858 | binop( Iop_32HLto64, |
| 5859 | mkU32(0), |
| 5860 | getIReg(4, eregOfRM(modrm)) ) ); |
| 5861 | DIP("movd %s, %s\n", |
| 5862 | nameIReg(4,eregOfRM(modrm)), nameMMXReg(gregOfRM(modrm))); |
| 5863 | } else { |
| 5864 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5865 | delta += len; |
| 5866 | putMMXReg( |
| 5867 | gregOfRM(modrm), |
| 5868 | binop( Iop_32HLto64, |
| 5869 | mkU32(0), |
| 5870 | loadLE(Ity_I32, mkexpr(addr)) ) ); |
| 5871 | DIP("movd %s, %s\n", dis_buf, nameMMXReg(gregOfRM(modrm))); |
| 5872 | } |
| 5873 | break; |
| 5874 | |
| 5875 | case 0x7E: /* MOVD (src)mmxreg (G), (dst)ireg-or-mem (E) */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5876 | if (sz != 4) |
| 5877 | goto mmx_decode_failure; |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 5878 | modrm = getIByte(delta); |
| 5879 | if (epartIsReg(modrm)) { |
| 5880 | delta++; |
| 5881 | putIReg( 4, eregOfRM(modrm), |
| 5882 | unop(Iop_64to32, getMMXReg(gregOfRM(modrm)) ) ); |
| 5883 | DIP("movd %s, %s\n", |
| 5884 | nameMMXReg(gregOfRM(modrm)), nameIReg(4,eregOfRM(modrm))); |
| 5885 | } else { |
| 5886 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5887 | delta += len; |
| 5888 | storeLE( mkexpr(addr), |
| 5889 | unop(Iop_64to32, getMMXReg(gregOfRM(modrm)) ) ); |
| 5890 | DIP("movd %s, %s\n", nameMMXReg(gregOfRM(modrm)), dis_buf); |
| 5891 | } |
| 5892 | break; |
| 5893 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5894 | case 0x6F: |
| 5895 | /* MOVQ (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5896 | if (sz != 4) |
| 5897 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5898 | modrm = getIByte(delta); |
| 5899 | if (epartIsReg(modrm)) { |
| 5900 | delta++; |
| 5901 | putMMXReg( gregOfRM(modrm), getMMXReg(eregOfRM(modrm)) ); |
| 5902 | DIP("movq %s, %s\n", |
| 5903 | nameMMXReg(eregOfRM(modrm)), nameMMXReg(gregOfRM(modrm))); |
| 5904 | } else { |
| 5905 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5906 | delta += len; |
| 5907 | putMMXReg( gregOfRM(modrm), loadLE(Ity_I64, mkexpr(addr)) ); |
| 5908 | DIP("movq %s, %s\n", |
| 5909 | dis_buf, nameMMXReg(gregOfRM(modrm))); |
| 5910 | } |
| 5911 | break; |
| 5912 | |
| 5913 | case 0x7F: |
| 5914 | /* MOVQ (src)mmxreg, (dst)mmxreg-or-mem */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5915 | if (sz != 4) |
| 5916 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5917 | modrm = getIByte(delta); |
| 5918 | if (epartIsReg(modrm)) { |
sewardj | 9ca2640 | 2005-10-03 02:44:01 +0000 | [diff] [blame] | 5919 | delta++; |
| 5920 | putMMXReg( eregOfRM(modrm), getMMXReg(gregOfRM(modrm)) ); |
| 5921 | DIP("movq %s, %s\n", |
| 5922 | nameMMXReg(gregOfRM(modrm)), nameMMXReg(eregOfRM(modrm))); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5923 | } else { |
| 5924 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 5925 | delta += len; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 5926 | storeLE( mkexpr(addr), getMMXReg(gregOfRM(modrm)) ); |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5927 | DIP("mov(nt)q %s, %s\n", |
| 5928 | nameMMXReg(gregOfRM(modrm)), dis_buf); |
| 5929 | } |
| 5930 | break; |
| 5931 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5932 | case 0xFC: |
| 5933 | case 0xFD: |
| 5934 | case 0xFE: /* PADDgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5935 | if (sz != 4) |
| 5936 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5937 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "padd", True ); |
| 5938 | break; |
| 5939 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5940 | case 0xEC: |
| 5941 | case 0xED: /* PADDSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5942 | if (sz != 4) |
| 5943 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5944 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "padds", True ); |
| 5945 | break; |
| 5946 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5947 | case 0xDC: |
| 5948 | case 0xDD: /* PADDUSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5949 | if (sz != 4) |
| 5950 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5951 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "paddus", True ); |
| 5952 | break; |
| 5953 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5954 | case 0xF8: |
| 5955 | case 0xF9: |
| 5956 | case 0xFA: /* PSUBgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5957 | if (sz != 4) |
| 5958 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5959 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "psub", True ); |
| 5960 | break; |
| 5961 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5962 | case 0xE8: |
| 5963 | case 0xE9: /* PSUBSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5964 | if (sz != 4) |
| 5965 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5966 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "psubs", True ); |
| 5967 | break; |
| 5968 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5969 | case 0xD8: |
| 5970 | case 0xD9: /* PSUBUSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5971 | if (sz != 4) |
| 5972 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5973 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "psubus", True ); |
| 5974 | break; |
| 5975 | |
| 5976 | case 0xE5: /* PMULHW (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5977 | if (sz != 4) |
| 5978 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5979 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pmulhw", False ); |
| 5980 | break; |
| 5981 | |
| 5982 | case 0xD5: /* PMULLW (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5983 | if (sz != 4) |
| 5984 | goto mmx_decode_failure; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 5985 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pmullw", False ); |
| 5986 | break; |
| 5987 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5988 | case 0xF5: /* PMADDWD (src)mmxreg-or-mem, (dst)mmxreg */ |
| 5989 | vassert(sz == 4); |
| 5990 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pmaddwd", False ); |
| 5991 | break; |
| 5992 | |
| 5993 | case 0x74: |
| 5994 | case 0x75: |
| 5995 | case 0x76: /* PCMPEQgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 5996 | if (sz != 4) |
| 5997 | goto mmx_decode_failure; |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 5998 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pcmpeq", True ); |
| 5999 | break; |
| 6000 | |
| 6001 | case 0x64: |
| 6002 | case 0x65: |
| 6003 | case 0x66: /* PCMPGTgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 6004 | if (sz != 4) |
| 6005 | goto mmx_decode_failure; |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 6006 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pcmpgt", True ); |
| 6007 | break; |
| 6008 | |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 6009 | case 0x6B: /* PACKSSDW (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 6010 | if (sz != 4) |
| 6011 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 6012 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "packssdw", False ); |
| 6013 | break; |
| 6014 | |
| 6015 | case 0x63: /* PACKSSWB (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 6016 | if (sz != 4) |
| 6017 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 6018 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "packsswb", False ); |
| 6019 | break; |
| 6020 | |
| 6021 | case 0x67: /* PACKUSWB (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 6022 | if (sz != 4) |
| 6023 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 6024 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "packuswb", False ); |
| 6025 | break; |
| 6026 | |
| 6027 | case 0x68: |
| 6028 | case 0x69: |
| 6029 | case 0x6A: /* PUNPCKHgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 6030 | if (sz != 4) |
| 6031 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 6032 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "punpckh", True ); |
| 6033 | break; |
| 6034 | |
| 6035 | case 0x60: |
| 6036 | case 0x61: |
| 6037 | case 0x62: /* PUNPCKLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 6038 | if (sz != 4) |
| 6039 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 6040 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "punpckl", True ); |
| 6041 | break; |
| 6042 | |
| 6043 | case 0xDB: /* PAND (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 6044 | if (sz != 4) |
| 6045 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 6046 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pand", False ); |
| 6047 | break; |
| 6048 | |
| 6049 | case 0xDF: /* PANDN (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 6050 | if (sz != 4) |
| 6051 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 6052 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pandn", False ); |
| 6053 | break; |
| 6054 | |
| 6055 | case 0xEB: /* POR (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 6056 | if (sz != 4) |
| 6057 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 6058 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "por", False ); |
| 6059 | break; |
| 6060 | |
| 6061 | case 0xEF: /* PXOR (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 6062 | if (sz != 4) |
| 6063 | goto mmx_decode_failure; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 6064 | delta = dis_MMXop_regmem_to_reg ( sorb, delta, opc, "pxor", False ); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6065 | break; |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 6066 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6067 | # define SHIFT_BY_REG(_name,_op) \ |
| 6068 | delta = dis_MMX_shiftG_byE(sorb, delta, _name, _op); \ |
| 6069 | break; |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 6070 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6071 | /* PSLLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 6072 | case 0xF1: SHIFT_BY_REG("psllw", Iop_ShlN16x4); |
| 6073 | case 0xF2: SHIFT_BY_REG("pslld", Iop_ShlN32x2); |
| 6074 | case 0xF3: SHIFT_BY_REG("psllq", Iop_Shl64); |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 6075 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6076 | /* PSRLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 6077 | case 0xD1: SHIFT_BY_REG("psrlw", Iop_ShrN16x4); |
| 6078 | case 0xD2: SHIFT_BY_REG("psrld", Iop_ShrN32x2); |
| 6079 | case 0xD3: SHIFT_BY_REG("psrlq", Iop_Shr64); |
| 6080 | |
| 6081 | /* PSRAgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 6082 | case 0xE1: SHIFT_BY_REG("psraw", Iop_SarN16x4); |
| 6083 | case 0xE2: SHIFT_BY_REG("psrad", Iop_SarN32x2); |
| 6084 | |
| 6085 | # undef SHIFT_BY_REG |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 6086 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6087 | case 0x71: |
| 6088 | case 0x72: |
| 6089 | case 0x73: { |
| 6090 | /* (sz==4): PSLLgg/PSRAgg/PSRLgg mmxreg by imm8 */ |
sewardj | a8415ff | 2005-01-21 20:55:36 +0000 | [diff] [blame] | 6091 | UChar byte2, subopc; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6092 | if (sz != 4) |
| 6093 | goto mmx_decode_failure; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6094 | byte2 = getIByte(delta); /* amode / sub-opcode */ |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 6095 | subopc = toUChar( (byte2 >> 3) & 7 ); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6096 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6097 | # define SHIFT_BY_IMM(_name,_op) \ |
| 6098 | do { delta = dis_MMX_shiftE_imm(delta,_name,_op); \ |
| 6099 | } while (0) |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6100 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6101 | if (subopc == 2 /*SRL*/ && opc == 0x71) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6102 | SHIFT_BY_IMM("psrlw", Iop_ShrN16x4); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6103 | else if (subopc == 2 /*SRL*/ && opc == 0x72) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6104 | SHIFT_BY_IMM("psrld", Iop_ShrN32x2); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6105 | else if (subopc == 2 /*SRL*/ && opc == 0x73) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6106 | SHIFT_BY_IMM("psrlq", Iop_Shr64); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6107 | |
| 6108 | else if (subopc == 4 /*SAR*/ && opc == 0x71) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6109 | SHIFT_BY_IMM("psraw", Iop_SarN16x4); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6110 | else if (subopc == 4 /*SAR*/ && opc == 0x72) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6111 | SHIFT_BY_IMM("psrad", Iop_SarN32x2); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6112 | |
| 6113 | else if (subopc == 6 /*SHL*/ && opc == 0x71) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6114 | SHIFT_BY_IMM("psllw", Iop_ShlN16x4); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6115 | else if (subopc == 6 /*SHL*/ && opc == 0x72) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6116 | SHIFT_BY_IMM("pslld", Iop_ShlN32x2); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6117 | else if (subopc == 6 /*SHL*/ && opc == 0x73) |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6118 | SHIFT_BY_IMM("psllq", Iop_Shl64); |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6119 | |
| 6120 | else goto mmx_decode_failure; |
| 6121 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 6122 | # undef SHIFT_BY_IMM |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6123 | break; |
| 6124 | } |
| 6125 | |
sewardj | d71ba83 | 2006-12-27 01:15:29 +0000 | [diff] [blame] | 6126 | case 0xF7: { |
| 6127 | IRTemp addr = newTemp(Ity_I32); |
| 6128 | IRTemp regD = newTemp(Ity_I64); |
| 6129 | IRTemp regM = newTemp(Ity_I64); |
| 6130 | IRTemp mask = newTemp(Ity_I64); |
| 6131 | IRTemp olddata = newTemp(Ity_I64); |
| 6132 | IRTemp newdata = newTemp(Ity_I64); |
| 6133 | |
| 6134 | modrm = getIByte(delta); |
| 6135 | if (sz != 4 || (!epartIsReg(modrm))) |
| 6136 | goto mmx_decode_failure; |
| 6137 | delta++; |
| 6138 | |
| 6139 | assign( addr, handleSegOverride( sorb, getIReg(4, R_EDI) )); |
| 6140 | assign( regM, getMMXReg( eregOfRM(modrm) )); |
| 6141 | assign( regD, getMMXReg( gregOfRM(modrm) )); |
| 6142 | assign( mask, binop(Iop_SarN8x8, mkexpr(regM), mkU8(7)) ); |
| 6143 | assign( olddata, loadLE( Ity_I64, mkexpr(addr) )); |
| 6144 | assign( newdata, |
| 6145 | binop(Iop_Or64, |
| 6146 | binop(Iop_And64, |
| 6147 | mkexpr(regD), |
| 6148 | mkexpr(mask) ), |
| 6149 | binop(Iop_And64, |
| 6150 | mkexpr(olddata), |
| 6151 | unop(Iop_Not64, mkexpr(mask)))) ); |
| 6152 | storeLE( mkexpr(addr), mkexpr(newdata) ); |
| 6153 | DIP("maskmovq %s,%s\n", nameMMXReg( eregOfRM(modrm) ), |
| 6154 | nameMMXReg( gregOfRM(modrm) ) ); |
| 6155 | break; |
| 6156 | } |
| 6157 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6158 | /* --- MMX decode failure --- */ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 6159 | default: |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 6160 | mmx_decode_failure: |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 6161 | *decode_ok = False; |
| 6162 | return delta; /* ignored */ |
| 6163 | |
| 6164 | } |
| 6165 | |
| 6166 | *decode_ok = True; |
| 6167 | return delta; |
| 6168 | } |
| 6169 | |
| 6170 | |
| 6171 | /*------------------------------------------------------------*/ |
| 6172 | /*--- More misc arithmetic and other obscure insns. ---*/ |
| 6173 | /*------------------------------------------------------------*/ |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6174 | |
| 6175 | /* Double length left and right shifts. Apparently only required in |
| 6176 | v-size (no b- variant). */ |
| 6177 | static |
| 6178 | UInt dis_SHLRD_Gv_Ev ( UChar sorb, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6179 | Int delta, UChar modrm, |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6180 | Int sz, |
| 6181 | IRExpr* shift_amt, |
| 6182 | Bool amt_is_literal, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 6183 | const HChar* shift_amt_txt, |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6184 | Bool left_shift ) |
| 6185 | { |
| 6186 | /* shift_amt :: Ity_I8 is the amount to shift. shift_amt_txt is used |
| 6187 | for printing it. And eip on entry points at the modrm byte. */ |
| 6188 | Int len; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6189 | HChar dis_buf[50]; |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6190 | |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 6191 | IRType ty = szToITy(sz); |
| 6192 | IRTemp gsrc = newTemp(ty); |
| 6193 | IRTemp esrc = newTemp(ty); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 6194 | IRTemp addr = IRTemp_INVALID; |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 6195 | IRTemp tmpSH = newTemp(Ity_I8); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 6196 | IRTemp tmpL = IRTemp_INVALID; |
| 6197 | IRTemp tmpRes = IRTemp_INVALID; |
| 6198 | IRTemp tmpSubSh = IRTemp_INVALID; |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6199 | IROp mkpair; |
| 6200 | IROp getres; |
| 6201 | IROp shift; |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6202 | IRExpr* mask = NULL; |
| 6203 | |
| 6204 | vassert(sz == 2 || sz == 4); |
| 6205 | |
| 6206 | /* The E-part is the destination; this is shifted. The G-part |
| 6207 | supplies bits to be shifted into the E-part, but is not |
| 6208 | changed. |
| 6209 | |
| 6210 | If shifting left, form a double-length word with E at the top |
| 6211 | and G at the bottom, and shift this left. The result is then in |
| 6212 | the high part. |
| 6213 | |
| 6214 | If shifting right, form a double-length word with G at the top |
| 6215 | and E at the bottom, and shift this right. The result is then |
| 6216 | at the bottom. */ |
| 6217 | |
| 6218 | /* Fetch the operands. */ |
| 6219 | |
| 6220 | assign( gsrc, getIReg(sz, gregOfRM(modrm)) ); |
| 6221 | |
| 6222 | if (epartIsReg(modrm)) { |
| 6223 | delta++; |
| 6224 | assign( esrc, getIReg(sz, eregOfRM(modrm)) ); |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 6225 | DIP("sh%cd%c %s, %s, %s\n", |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6226 | ( left_shift ? 'l' : 'r' ), nameISize(sz), |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 6227 | shift_amt_txt, |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6228 | nameIReg(sz, gregOfRM(modrm)), nameIReg(sz, eregOfRM(modrm))); |
| 6229 | } else { |
| 6230 | addr = disAMode ( &len, sorb, delta, dis_buf ); |
| 6231 | delta += len; |
| 6232 | assign( esrc, loadLE(ty, mkexpr(addr)) ); |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 6233 | DIP("sh%cd%c %s, %s, %s\n", |
| 6234 | ( left_shift ? 'l' : 'r' ), nameISize(sz), |
| 6235 | shift_amt_txt, |
| 6236 | nameIReg(sz, gregOfRM(modrm)), dis_buf); |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6237 | } |
| 6238 | |
| 6239 | /* Round up the relevant primops. */ |
| 6240 | |
| 6241 | if (sz == 4) { |
| 6242 | tmpL = newTemp(Ity_I64); |
| 6243 | tmpRes = newTemp(Ity_I32); |
| 6244 | tmpSubSh = newTemp(Ity_I32); |
sewardj | e539a40 | 2004-07-14 18:24:17 +0000 | [diff] [blame] | 6245 | mkpair = Iop_32HLto64; |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 6246 | getres = left_shift ? Iop_64HIto32 : Iop_64to32; |
sewardj | e539a40 | 2004-07-14 18:24:17 +0000 | [diff] [blame] | 6247 | shift = left_shift ? Iop_Shl64 : Iop_Shr64; |
| 6248 | mask = mkU8(31); |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6249 | } else { |
| 6250 | /* sz == 2 */ |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 6251 | tmpL = newTemp(Ity_I32); |
| 6252 | tmpRes = newTemp(Ity_I16); |
| 6253 | tmpSubSh = newTemp(Ity_I16); |
| 6254 | mkpair = Iop_16HLto32; |
| 6255 | getres = left_shift ? Iop_32HIto16 : Iop_32to16; |
| 6256 | shift = left_shift ? Iop_Shl32 : Iop_Shr32; |
| 6257 | mask = mkU8(15); |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6258 | } |
| 6259 | |
| 6260 | /* Do the shift, calculate the subshift value, and set |
| 6261 | the flag thunk. */ |
| 6262 | |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 6263 | assign( tmpSH, binop(Iop_And8, shift_amt, mask) ); |
| 6264 | |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6265 | if (left_shift) |
| 6266 | assign( tmpL, binop(mkpair, mkexpr(esrc), mkexpr(gsrc)) ); |
| 6267 | else |
| 6268 | assign( tmpL, binop(mkpair, mkexpr(gsrc), mkexpr(esrc)) ); |
| 6269 | |
| 6270 | assign( tmpRes, unop(getres, binop(shift, mkexpr(tmpL), mkexpr(tmpSH)) ) ); |
| 6271 | assign( tmpSubSh, |
| 6272 | unop(getres, |
| 6273 | binop(shift, |
| 6274 | mkexpr(tmpL), |
| 6275 | binop(Iop_And8, |
| 6276 | binop(Iop_Sub8, mkexpr(tmpSH), mkU8(1) ), |
| 6277 | mask))) ); |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6278 | |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6279 | setFlags_DEP1_DEP2_shift ( left_shift ? Iop_Shl32 : Iop_Sar32, |
| 6280 | tmpRes, tmpSubSh, ty, tmpSH ); |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 6281 | |
| 6282 | /* Put result back. */ |
| 6283 | |
| 6284 | if (epartIsReg(modrm)) { |
| 6285 | putIReg(sz, eregOfRM(modrm), mkexpr(tmpRes)); |
| 6286 | } else { |
| 6287 | storeLE( mkexpr(addr), mkexpr(tmpRes) ); |
| 6288 | } |
| 6289 | |
| 6290 | if (amt_is_literal) delta++; |
| 6291 | return delta; |
| 6292 | } |
| 6293 | |
| 6294 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6295 | /* Handle BT/BTS/BTR/BTC Gv, Ev. Apparently b-size is not |
| 6296 | required. */ |
| 6297 | |
| 6298 | typedef enum { BtOpNone, BtOpSet, BtOpReset, BtOpComp } BtOp; |
| 6299 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 6300 | static const HChar* nameBtOp ( BtOp op ) |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6301 | { |
| 6302 | switch (op) { |
| 6303 | case BtOpNone: return ""; |
| 6304 | case BtOpSet: return "s"; |
| 6305 | case BtOpReset: return "r"; |
| 6306 | case BtOpComp: return "c"; |
| 6307 | default: vpanic("nameBtOp(x86)"); |
| 6308 | } |
| 6309 | } |
| 6310 | |
| 6311 | |
| 6312 | static |
florian | cacba8e | 2014-12-15 18:58:07 +0000 | [diff] [blame] | 6313 | UInt dis_bt_G_E ( const VexAbiInfo* vbi, |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 6314 | UChar sorb, Bool locked, Int sz, Int delta, BtOp op ) |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6315 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6316 | HChar dis_buf[50]; |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6317 | UChar modrm; |
| 6318 | Int len; |
| 6319 | IRTemp t_fetched, t_bitno0, t_bitno1, t_bitno2, t_addr0, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6320 | t_addr1, t_esp, t_mask, t_new; |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6321 | |
| 6322 | vassert(sz == 2 || sz == 4); |
| 6323 | |
| 6324 | t_fetched = t_bitno0 = t_bitno1 = t_bitno2 |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6325 | = t_addr0 = t_addr1 = t_esp |
| 6326 | = t_mask = t_new = IRTemp_INVALID; |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6327 | |
| 6328 | t_fetched = newTemp(Ity_I8); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6329 | t_new = newTemp(Ity_I8); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6330 | t_bitno0 = newTemp(Ity_I32); |
| 6331 | t_bitno1 = newTemp(Ity_I32); |
| 6332 | t_bitno2 = newTemp(Ity_I8); |
| 6333 | t_addr1 = newTemp(Ity_I32); |
| 6334 | modrm = getIByte(delta); |
| 6335 | |
sewardj | 9ed1680 | 2005-08-24 10:46:19 +0000 | [diff] [blame] | 6336 | assign( t_bitno0, widenSto32(getIReg(sz, gregOfRM(modrm))) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6337 | |
| 6338 | if (epartIsReg(modrm)) { |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6339 | delta++; |
| 6340 | /* Get it onto the client's stack. */ |
| 6341 | t_esp = newTemp(Ity_I32); |
| 6342 | t_addr0 = newTemp(Ity_I32); |
| 6343 | |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 6344 | /* For the choice of the value 128, see comment in dis_bt_G_E in |
| 6345 | guest_amd64_toIR.c. We point out here only that 128 is |
| 6346 | fast-cased in Memcheck and is > 0, so seems like a good |
| 6347 | choice. */ |
| 6348 | vassert(vbi->guest_stack_redzone_size == 0); |
| 6349 | assign( t_esp, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(128)) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6350 | putIReg(4, R_ESP, mkexpr(t_esp)); |
| 6351 | |
| 6352 | storeLE( mkexpr(t_esp), getIReg(sz, eregOfRM(modrm)) ); |
| 6353 | |
| 6354 | /* Make t_addr0 point at it. */ |
| 6355 | assign( t_addr0, mkexpr(t_esp) ); |
| 6356 | |
| 6357 | /* Mask out upper bits of the shift amount, since we're doing a |
| 6358 | reg. */ |
| 6359 | assign( t_bitno1, binop(Iop_And32, |
| 6360 | mkexpr(t_bitno0), |
| 6361 | mkU32(sz == 4 ? 31 : 15)) ); |
| 6362 | |
| 6363 | } else { |
| 6364 | t_addr0 = disAMode ( &len, sorb, delta, dis_buf ); |
| 6365 | delta += len; |
| 6366 | assign( t_bitno1, mkexpr(t_bitno0) ); |
| 6367 | } |
| 6368 | |
| 6369 | /* At this point: t_addr0 is the address being operated on. If it |
| 6370 | was a reg, we will have pushed it onto the client's stack. |
| 6371 | t_bitno1 is the bit number, suitably masked in the case of a |
| 6372 | reg. */ |
| 6373 | |
| 6374 | /* Now the main sequence. */ |
| 6375 | assign( t_addr1, |
| 6376 | binop(Iop_Add32, |
| 6377 | mkexpr(t_addr0), |
| 6378 | binop(Iop_Sar32, mkexpr(t_bitno1), mkU8(3))) ); |
| 6379 | |
| 6380 | /* t_addr1 now holds effective address */ |
| 6381 | |
| 6382 | assign( t_bitno2, |
| 6383 | unop(Iop_32to8, |
| 6384 | binop(Iop_And32, mkexpr(t_bitno1), mkU32(7))) ); |
| 6385 | |
| 6386 | /* t_bitno2 contains offset of bit within byte */ |
| 6387 | |
| 6388 | if (op != BtOpNone) { |
| 6389 | t_mask = newTemp(Ity_I8); |
| 6390 | assign( t_mask, binop(Iop_Shl8, mkU8(1), mkexpr(t_bitno2)) ); |
| 6391 | } |
sewardj | 4963a42 | 2004-10-14 23:34:03 +0000 | [diff] [blame] | 6392 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6393 | /* t_mask is now a suitable byte mask */ |
| 6394 | |
| 6395 | assign( t_fetched, loadLE(Ity_I8, mkexpr(t_addr1)) ); |
| 6396 | |
| 6397 | if (op != BtOpNone) { |
| 6398 | switch (op) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6399 | case BtOpSet: |
| 6400 | assign( t_new, |
| 6401 | binop(Iop_Or8, mkexpr(t_fetched), mkexpr(t_mask)) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6402 | break; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6403 | case BtOpComp: |
| 6404 | assign( t_new, |
| 6405 | binop(Iop_Xor8, mkexpr(t_fetched), mkexpr(t_mask)) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6406 | break; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6407 | case BtOpReset: |
| 6408 | assign( t_new, |
| 6409 | binop(Iop_And8, mkexpr(t_fetched), |
| 6410 | unop(Iop_Not8, mkexpr(t_mask))) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6411 | break; |
| 6412 | default: |
| 6413 | vpanic("dis_bt_G_E(x86)"); |
| 6414 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6415 | if (locked && !epartIsReg(modrm)) { |
| 6416 | casLE( mkexpr(t_addr1), mkexpr(t_fetched)/*expd*/, |
| 6417 | mkexpr(t_new)/*new*/, |
| 6418 | guest_EIP_curr_instr ); |
| 6419 | } else { |
| 6420 | storeLE( mkexpr(t_addr1), mkexpr(t_new) ); |
| 6421 | } |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6422 | } |
| 6423 | |
| 6424 | /* Side effect done; now get selected bit into Carry flag */ |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6425 | /* Flags: C=selected bit, O,S,Z,A,P undefined, so are set to zero. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6426 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6427 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6428 | stmt( IRStmt_Put( |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6429 | OFFB_CC_DEP1, |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6430 | binop(Iop_And32, |
| 6431 | binop(Iop_Shr32, |
| 6432 | unop(Iop_8Uto32, mkexpr(t_fetched)), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 6433 | mkexpr(t_bitno2)), |
| 6434 | mkU32(1))) |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6435 | ); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 6436 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 6437 | elimination of previous stores to this field work better. */ |
| 6438 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6439 | |
| 6440 | /* Move reg operand from stack back to reg */ |
| 6441 | if (epartIsReg(modrm)) { |
| 6442 | /* t_esp still points at it. */ |
sewardj | 4963a42 | 2004-10-14 23:34:03 +0000 | [diff] [blame] | 6443 | putIReg(sz, eregOfRM(modrm), loadLE(szToITy(sz), mkexpr(t_esp)) ); |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 6444 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t_esp), mkU32(128)) ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 6445 | } |
| 6446 | |
| 6447 | DIP("bt%s%c %s, %s\n", |
| 6448 | nameBtOp(op), nameISize(sz), nameIReg(sz, gregOfRM(modrm)), |
| 6449 | ( epartIsReg(modrm) ? nameIReg(sz, eregOfRM(modrm)) : dis_buf ) ); |
| 6450 | |
| 6451 | return delta; |
| 6452 | } |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6453 | |
| 6454 | |
| 6455 | |
| 6456 | /* Handle BSF/BSR. Only v-size seems necessary. */ |
| 6457 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6458 | UInt dis_bs_E_G ( UChar sorb, Int sz, Int delta, Bool fwds ) |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6459 | { |
| 6460 | Bool isReg; |
| 6461 | UChar modrm; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6462 | HChar dis_buf[50]; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6463 | |
| 6464 | IRType ty = szToITy(sz); |
| 6465 | IRTemp src = newTemp(ty); |
| 6466 | IRTemp dst = newTemp(ty); |
| 6467 | |
| 6468 | IRTemp src32 = newTemp(Ity_I32); |
| 6469 | IRTemp dst32 = newTemp(Ity_I32); |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 6470 | IRTemp srcB = newTemp(Ity_I1); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6471 | |
| 6472 | vassert(sz == 4 || sz == 2); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6473 | |
| 6474 | modrm = getIByte(delta); |
| 6475 | |
| 6476 | isReg = epartIsReg(modrm); |
| 6477 | if (isReg) { |
| 6478 | delta++; |
| 6479 | assign( src, getIReg(sz, eregOfRM(modrm)) ); |
| 6480 | } else { |
| 6481 | Int len; |
| 6482 | IRTemp addr = disAMode( &len, sorb, delta, dis_buf ); |
| 6483 | delta += len; |
| 6484 | assign( src, loadLE(ty, mkexpr(addr)) ); |
| 6485 | } |
| 6486 | |
| 6487 | DIP("bs%c%c %s, %s\n", |
| 6488 | fwds ? 'f' : 'r', nameISize(sz), |
| 6489 | ( isReg ? nameIReg(sz, eregOfRM(modrm)) : dis_buf ), |
| 6490 | nameIReg(sz, gregOfRM(modrm))); |
| 6491 | |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 6492 | /* Generate a bool expression which is zero iff the original is |
sewardj | e13074c | 2012-11-08 10:57:08 +0000 | [diff] [blame] | 6493 | zero, and nonzero otherwise. Ask for a CmpNE version which, if |
| 6494 | instrumented by Memcheck, is instrumented expensively, since |
| 6495 | this may be used on the output of a preceding movmskb insn, |
| 6496 | which has been known to be partially defined, and in need of |
| 6497 | careful handling. */ |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 6498 | assign( srcB, binop(mkSizedOp(ty,Iop_ExpCmpNE8), |
| 6499 | mkexpr(src), mkU(ty,0)) ); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6500 | |
| 6501 | /* Flags: Z is 1 iff source value is zero. All others |
| 6502 | are undefined -- we force them to zero. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6503 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6504 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6505 | stmt( IRStmt_Put( |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6506 | OFFB_CC_DEP1, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6507 | IRExpr_ITE( mkexpr(srcB), |
| 6508 | /* src!=0 */ |
| 6509 | mkU32(0), |
| 6510 | /* src==0 */ |
| 6511 | mkU32(X86G_CC_MASK_Z) |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6512 | ) |
| 6513 | )); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 6514 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 6515 | elimination of previous stores to this field work better. */ |
| 6516 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6517 | |
| 6518 | /* Result: iff source value is zero, we can't use |
| 6519 | Iop_Clz32/Iop_Ctz32 as they have no defined result in that case. |
| 6520 | But anyway, Intel x86 semantics say the result is undefined in |
| 6521 | such situations. Hence handle the zero case specially. */ |
| 6522 | |
| 6523 | /* Bleh. What we compute: |
| 6524 | |
| 6525 | bsf32: if src == 0 then 0 else Ctz32(src) |
| 6526 | bsr32: if src == 0 then 0 else 31 - Clz32(src) |
| 6527 | |
| 6528 | bsf16: if src == 0 then 0 else Ctz32(16Uto32(src)) |
| 6529 | bsr16: if src == 0 then 0 else 31 - Clz32(16Uto32(src)) |
| 6530 | |
| 6531 | First, widen src to 32 bits if it is not already. |
sewardj | 3715871 | 2004-10-15 21:23:12 +0000 | [diff] [blame] | 6532 | |
| 6533 | Postscript 15 Oct 04: it seems that at least VIA Nehemiah leaves the |
| 6534 | dst register unchanged when src == 0. Hence change accordingly. |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6535 | */ |
| 6536 | if (sz == 2) |
| 6537 | assign( src32, unop(Iop_16Uto32, mkexpr(src)) ); |
| 6538 | else |
| 6539 | assign( src32, mkexpr(src) ); |
| 6540 | |
| 6541 | /* The main computation, guarding against zero. */ |
| 6542 | assign( dst32, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6543 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 6544 | mkexpr(srcB), |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6545 | /* src != 0 */ |
| 6546 | fwds ? unop(Iop_Ctz32, mkexpr(src32)) |
| 6547 | : binop(Iop_Sub32, |
| 6548 | mkU32(31), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6549 | unop(Iop_Clz32, mkexpr(src32))), |
| 6550 | /* src == 0 -- leave dst unchanged */ |
| 6551 | widenUto32( getIReg( sz, gregOfRM(modrm) ) ) |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 6552 | ) |
| 6553 | ); |
| 6554 | |
| 6555 | if (sz == 2) |
| 6556 | assign( dst, unop(Iop_32to16, mkexpr(dst32)) ); |
| 6557 | else |
| 6558 | assign( dst, mkexpr(dst32) ); |
| 6559 | |
| 6560 | /* dump result back */ |
| 6561 | putIReg( sz, gregOfRM(modrm), mkexpr(dst) ); |
| 6562 | |
| 6563 | return delta; |
| 6564 | } |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 6565 | |
| 6566 | |
| 6567 | static |
| 6568 | void codegen_xchg_eAX_Reg ( Int sz, Int reg ) |
| 6569 | { |
| 6570 | IRType ty = szToITy(sz); |
| 6571 | IRTemp t1 = newTemp(ty); |
| 6572 | IRTemp t2 = newTemp(ty); |
| 6573 | vassert(sz == 2 || sz == 4); |
| 6574 | assign( t1, getIReg(sz, R_EAX) ); |
| 6575 | assign( t2, getIReg(sz, reg) ); |
| 6576 | putIReg( sz, R_EAX, mkexpr(t2) ); |
| 6577 | putIReg( sz, reg, mkexpr(t1) ); |
| 6578 | DIP("xchg%c %s, %s\n", |
| 6579 | nameISize(sz), nameIReg(sz, R_EAX), nameIReg(sz, reg)); |
| 6580 | } |
| 6581 | |
| 6582 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6583 | static |
| 6584 | void codegen_SAHF ( void ) |
| 6585 | { |
| 6586 | /* Set the flags to: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6587 | (x86g_calculate_flags_all() & X86G_CC_MASK_O) -- retain the old O flag |
| 6588 | | (%AH & (X86G_CC_MASK_S|X86G_CC_MASK_Z|X86G_CC_MASK_A |
| 6589 | |X86G_CC_MASK_P|X86G_CC_MASK_C) |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6590 | */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6591 | UInt mask_SZACP = X86G_CC_MASK_S|X86G_CC_MASK_Z|X86G_CC_MASK_A |
| 6592 | |X86G_CC_MASK_C|X86G_CC_MASK_P; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6593 | IRTemp oldflags = newTemp(Ity_I32); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6594 | assign( oldflags, mk_x86g_calculate_eflags_all() ); |
| 6595 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
sewardj | 905edbd | 2007-04-07 12:25:37 +0000 | [diff] [blame] | 6596 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 6597 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 6598 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6599 | binop(Iop_Or32, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6600 | binop(Iop_And32, mkexpr(oldflags), mkU32(X86G_CC_MASK_O)), |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6601 | binop(Iop_And32, |
| 6602 | binop(Iop_Shr32, getIReg(4, R_EAX), mkU8(8)), |
| 6603 | mkU32(mask_SZACP)) |
| 6604 | ) |
| 6605 | )); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 6606 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 6607 | elimination of previous stores to this field work better. */ |
| 6608 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 6609 | } |
| 6610 | |
| 6611 | |
sewardj | 8dfdc8a | 2005-10-03 11:39:02 +0000 | [diff] [blame] | 6612 | static |
| 6613 | void codegen_LAHF ( void ) |
| 6614 | { |
| 6615 | /* AH <- EFLAGS(SF:ZF:0:AF:0:PF:1:CF) */ |
| 6616 | IRExpr* eax_with_hole; |
| 6617 | IRExpr* new_byte; |
| 6618 | IRExpr* new_eax; |
| 6619 | UInt mask_SZACP = X86G_CC_MASK_S|X86G_CC_MASK_Z|X86G_CC_MASK_A |
| 6620 | |X86G_CC_MASK_C|X86G_CC_MASK_P; |
| 6621 | |
| 6622 | IRTemp flags = newTemp(Ity_I32); |
| 6623 | assign( flags, mk_x86g_calculate_eflags_all() ); |
| 6624 | |
| 6625 | eax_with_hole |
| 6626 | = binop(Iop_And32, getIReg(4, R_EAX), mkU32(0xFFFF00FF)); |
| 6627 | new_byte |
| 6628 | = binop(Iop_Or32, binop(Iop_And32, mkexpr(flags), mkU32(mask_SZACP)), |
| 6629 | mkU32(1<<1)); |
| 6630 | new_eax |
| 6631 | = binop(Iop_Or32, eax_with_hole, |
| 6632 | binop(Iop_Shl32, new_byte, mkU8(8))); |
| 6633 | putIReg(4, R_EAX, new_eax); |
| 6634 | } |
| 6635 | |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6636 | |
| 6637 | static |
| 6638 | UInt dis_cmpxchg_G_E ( UChar sorb, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6639 | Bool locked, |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6640 | Int size, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6641 | Int delta0 ) |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6642 | { |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6643 | HChar dis_buf[50]; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6644 | Int len; |
| 6645 | |
| 6646 | IRType ty = szToITy(size); |
| 6647 | IRTemp acc = newTemp(ty); |
| 6648 | IRTemp src = newTemp(ty); |
| 6649 | IRTemp dest = newTemp(ty); |
| 6650 | IRTemp dest2 = newTemp(ty); |
| 6651 | IRTemp acc2 = newTemp(ty); |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 6652 | IRTemp cond = newTemp(Ity_I1); |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 6653 | IRTemp addr = IRTemp_INVALID; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6654 | UChar rm = getUChar(delta0); |
| 6655 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6656 | /* There are 3 cases to consider: |
| 6657 | |
| 6658 | reg-reg: ignore any lock prefix, generate sequence based |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6659 | on ITE |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6660 | |
| 6661 | reg-mem, not locked: ignore any lock prefix, generate sequence |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6662 | based on ITE |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6663 | |
| 6664 | reg-mem, locked: use IRCAS |
| 6665 | */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6666 | if (epartIsReg(rm)) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6667 | /* case 1 */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6668 | assign( dest, getIReg(size, eregOfRM(rm)) ); |
| 6669 | delta0++; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6670 | assign( src, getIReg(size, gregOfRM(rm)) ); |
| 6671 | assign( acc, getIReg(size, R_EAX) ); |
| 6672 | setFlags_DEP1_DEP2(Iop_Sub8, acc, dest, ty); |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 6673 | assign( cond, mk_x86g_calculate_condition(X86CondZ) ); |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6674 | assign( dest2, IRExpr_ITE(mkexpr(cond), mkexpr(src), mkexpr(dest)) ); |
| 6675 | assign( acc2, IRExpr_ITE(mkexpr(cond), mkexpr(acc), mkexpr(dest)) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6676 | putIReg(size, R_EAX, mkexpr(acc2)); |
| 6677 | putIReg(size, eregOfRM(rm), mkexpr(dest2)); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6678 | DIP("cmpxchg%c %s,%s\n", nameISize(size), |
| 6679 | nameIReg(size,gregOfRM(rm)), |
| 6680 | nameIReg(size,eregOfRM(rm)) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6681 | } |
| 6682 | else if (!epartIsReg(rm) && !locked) { |
| 6683 | /* case 2 */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6684 | addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6685 | assign( dest, loadLE(ty, mkexpr(addr)) ); |
| 6686 | delta0 += len; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6687 | assign( src, getIReg(size, gregOfRM(rm)) ); |
| 6688 | assign( acc, getIReg(size, R_EAX) ); |
| 6689 | setFlags_DEP1_DEP2(Iop_Sub8, acc, dest, ty); |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 6690 | assign( cond, mk_x86g_calculate_condition(X86CondZ) ); |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6691 | assign( dest2, IRExpr_ITE(mkexpr(cond), mkexpr(src), mkexpr(dest)) ); |
| 6692 | assign( acc2, IRExpr_ITE(mkexpr(cond), mkexpr(acc), mkexpr(dest)) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6693 | putIReg(size, R_EAX, mkexpr(acc2)); |
| 6694 | storeLE( mkexpr(addr), mkexpr(dest2) ); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6695 | DIP("cmpxchg%c %s,%s\n", nameISize(size), |
| 6696 | nameIReg(size,gregOfRM(rm)), dis_buf); |
| 6697 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6698 | else if (!epartIsReg(rm) && locked) { |
| 6699 | /* case 3 */ |
| 6700 | /* src is new value. acc is expected value. dest is old value. |
| 6701 | Compute success from the output of the IRCAS, and steer the |
| 6702 | new value for EAX accordingly: in case of success, EAX is |
| 6703 | unchanged. */ |
| 6704 | addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6705 | delta0 += len; |
| 6706 | assign( src, getIReg(size, gregOfRM(rm)) ); |
| 6707 | assign( acc, getIReg(size, R_EAX) ); |
| 6708 | stmt( IRStmt_CAS( |
| 6709 | mkIRCAS( IRTemp_INVALID, dest, Iend_LE, mkexpr(addr), |
| 6710 | NULL, mkexpr(acc), NULL, mkexpr(src) ) |
| 6711 | )); |
| 6712 | setFlags_DEP1_DEP2(Iop_Sub8, acc, dest, ty); |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 6713 | assign( cond, mk_x86g_calculate_condition(X86CondZ) ); |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6714 | assign( acc2, IRExpr_ITE(mkexpr(cond), mkexpr(acc), mkexpr(dest)) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6715 | putIReg(size, R_EAX, mkexpr(acc2)); |
sewardj | 40d1d21 | 2009-07-12 13:01:17 +0000 | [diff] [blame] | 6716 | DIP("cmpxchg%c %s,%s\n", nameISize(size), |
| 6717 | nameIReg(size,gregOfRM(rm)), dis_buf); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6718 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6719 | else vassert(0); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6720 | |
| 6721 | return delta0; |
| 6722 | } |
| 6723 | |
| 6724 | |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6725 | /* Handle conditional move instructions of the form |
| 6726 | cmovcc E(reg-or-mem), G(reg) |
| 6727 | |
| 6728 | E(src) is reg-or-mem |
| 6729 | G(dst) is reg. |
| 6730 | |
| 6731 | If E is reg, --> GET %E, tmps |
| 6732 | GET %G, tmpd |
| 6733 | CMOVcc tmps, tmpd |
| 6734 | PUT tmpd, %G |
| 6735 | |
| 6736 | If E is mem --> (getAddr E) -> tmpa |
| 6737 | LD (tmpa), tmps |
| 6738 | GET %G, tmpd |
| 6739 | CMOVcc tmps, tmpd |
| 6740 | PUT tmpd, %G |
| 6741 | */ |
| 6742 | static |
| 6743 | UInt dis_cmov_E_G ( UChar sorb, |
| 6744 | Int sz, |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6745 | X86Condcode cond, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6746 | Int delta0 ) |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6747 | { |
| 6748 | UChar rm = getIByte(delta0); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6749 | HChar dis_buf[50]; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6750 | Int len; |
| 6751 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6752 | IRType ty = szToITy(sz); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6753 | IRTemp tmps = newTemp(ty); |
| 6754 | IRTemp tmpd = newTemp(ty); |
| 6755 | |
| 6756 | if (epartIsReg(rm)) { |
| 6757 | assign( tmps, getIReg(sz, eregOfRM(rm)) ); |
| 6758 | assign( tmpd, getIReg(sz, gregOfRM(rm)) ); |
| 6759 | |
| 6760 | putIReg(sz, gregOfRM(rm), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6761 | IRExpr_ITE( mk_x86g_calculate_condition(cond), |
| 6762 | mkexpr(tmps), |
| 6763 | mkexpr(tmpd) ) |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6764 | ); |
| 6765 | DIP("cmov%c%s %s,%s\n", nameISize(sz), |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6766 | name_X86Condcode(cond), |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6767 | nameIReg(sz,eregOfRM(rm)), |
| 6768 | nameIReg(sz,gregOfRM(rm))); |
| 6769 | return 1+delta0; |
| 6770 | } |
| 6771 | |
| 6772 | /* E refers to memory */ |
| 6773 | { |
| 6774 | IRTemp addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6775 | assign( tmps, loadLE(ty, mkexpr(addr)) ); |
| 6776 | assign( tmpd, getIReg(sz, gregOfRM(rm)) ); |
| 6777 | |
| 6778 | putIReg(sz, gregOfRM(rm), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 6779 | IRExpr_ITE( mk_x86g_calculate_condition(cond), |
| 6780 | mkexpr(tmps), |
| 6781 | mkexpr(tmpd) ) |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6782 | ); |
| 6783 | |
| 6784 | DIP("cmov%c%s %s,%s\n", nameISize(sz), |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 6785 | name_X86Condcode(cond), |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 6786 | dis_buf, |
| 6787 | nameIReg(sz,gregOfRM(rm))); |
| 6788 | return len+delta0; |
| 6789 | } |
| 6790 | } |
| 6791 | |
| 6792 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6793 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6794 | UInt dis_xadd_G_E ( UChar sorb, Bool locked, Int sz, Int delta0, |
| 6795 | Bool* decodeOK ) |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6796 | { |
| 6797 | Int len; |
| 6798 | UChar rm = getIByte(delta0); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6799 | HChar dis_buf[50]; |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6800 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6801 | IRType ty = szToITy(sz); |
| 6802 | IRTemp tmpd = newTemp(ty); |
| 6803 | IRTemp tmpt0 = newTemp(ty); |
| 6804 | IRTemp tmpt1 = newTemp(ty); |
| 6805 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6806 | /* There are 3 cases to consider: |
| 6807 | |
sewardj | c2433a8 | 2010-05-10 20:51:22 +0000 | [diff] [blame] | 6808 | reg-reg: ignore any lock prefix, |
| 6809 | generate 'naive' (non-atomic) sequence |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6810 | |
| 6811 | reg-mem, not locked: ignore any lock prefix, generate 'naive' |
| 6812 | (non-atomic) sequence |
| 6813 | |
| 6814 | reg-mem, locked: use IRCAS |
| 6815 | */ |
| 6816 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6817 | if (epartIsReg(rm)) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6818 | /* case 1 */ |
sewardj | c2433a8 | 2010-05-10 20:51:22 +0000 | [diff] [blame] | 6819 | assign( tmpd, getIReg(sz, eregOfRM(rm))); |
| 6820 | assign( tmpt0, getIReg(sz, gregOfRM(rm)) ); |
| 6821 | assign( tmpt1, binop(mkSizedOp(ty,Iop_Add8), |
| 6822 | mkexpr(tmpd), mkexpr(tmpt0)) ); |
| 6823 | setFlags_DEP1_DEP2( Iop_Add8, tmpd, tmpt0, ty ); |
| 6824 | putIReg(sz, eregOfRM(rm), mkexpr(tmpt1)); |
| 6825 | putIReg(sz, gregOfRM(rm), mkexpr(tmpd)); |
| 6826 | DIP("xadd%c %s, %s\n", |
| 6827 | nameISize(sz), nameIReg(sz,gregOfRM(rm)), |
| 6828 | nameIReg(sz,eregOfRM(rm))); |
| 6829 | *decodeOK = True; |
| 6830 | return 1+delta0; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6831 | } |
| 6832 | else if (!epartIsReg(rm) && !locked) { |
| 6833 | /* case 2 */ |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6834 | IRTemp addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6835 | assign( tmpd, loadLE(ty, mkexpr(addr)) ); |
| 6836 | assign( tmpt0, getIReg(sz, gregOfRM(rm)) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6837 | assign( tmpt1, binop(mkSizedOp(ty,Iop_Add8), |
| 6838 | mkexpr(tmpd), mkexpr(tmpt0)) ); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6839 | storeLE( mkexpr(addr), mkexpr(tmpt1) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6840 | setFlags_DEP1_DEP2( Iop_Add8, tmpd, tmpt0, ty ); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6841 | putIReg(sz, gregOfRM(rm), mkexpr(tmpd)); |
| 6842 | DIP("xadd%c %s, %s\n", |
| 6843 | nameISize(sz), nameIReg(sz,gregOfRM(rm)), dis_buf); |
sewardj | 0092e0d | 2006-03-06 13:35:42 +0000 | [diff] [blame] | 6844 | *decodeOK = True; |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6845 | return len+delta0; |
| 6846 | } |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 6847 | else if (!epartIsReg(rm) && locked) { |
| 6848 | /* case 3 */ |
| 6849 | IRTemp addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6850 | assign( tmpd, loadLE(ty, mkexpr(addr)) ); |
| 6851 | assign( tmpt0, getIReg(sz, gregOfRM(rm)) ); |
| 6852 | assign( tmpt1, binop(mkSizedOp(ty,Iop_Add8), |
| 6853 | mkexpr(tmpd), mkexpr(tmpt0)) ); |
| 6854 | casLE( mkexpr(addr), mkexpr(tmpd)/*expVal*/, |
| 6855 | mkexpr(tmpt1)/*newVal*/, guest_EIP_curr_instr ); |
| 6856 | setFlags_DEP1_DEP2( Iop_Add8, tmpd, tmpt0, ty ); |
| 6857 | putIReg(sz, gregOfRM(rm), mkexpr(tmpd)); |
| 6858 | DIP("xadd%c %s, %s\n", |
| 6859 | nameISize(sz), nameIReg(sz,gregOfRM(rm)), dis_buf); |
| 6860 | *decodeOK = True; |
| 6861 | return len+delta0; |
| 6862 | } |
| 6863 | /*UNREACHED*/ |
| 6864 | vassert(0); |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 6865 | } |
| 6866 | |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6867 | /* Move 16 bits from Ew (ireg or mem) to G (a segment register). */ |
| 6868 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 6869 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6870 | UInt dis_mov_Ew_Sw ( UChar sorb, Int delta0 ) |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 6871 | { |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6872 | Int len; |
| 6873 | IRTemp addr; |
| 6874 | UChar rm = getIByte(delta0); |
| 6875 | HChar dis_buf[50]; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 6876 | |
| 6877 | if (epartIsReg(rm)) { |
| 6878 | putSReg( gregOfRM(rm), getIReg(2, eregOfRM(rm)) ); |
| 6879 | DIP("movw %s,%s\n", nameIReg(2,eregOfRM(rm)), nameSReg(gregOfRM(rm))); |
| 6880 | return 1+delta0; |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6881 | } else { |
| 6882 | addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6883 | putSReg( gregOfRM(rm), loadLE(Ity_I16, mkexpr(addr)) ); |
| 6884 | DIP("movw %s,%s\n", dis_buf, nameSReg(gregOfRM(rm))); |
| 6885 | return len+delta0; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 6886 | } |
| 6887 | } |
| 6888 | |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6889 | /* Move 16 bits from G (a segment register) to Ew (ireg or mem). If |
| 6890 | dst is ireg and sz==4, zero out top half of it. */ |
| 6891 | |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6892 | static |
| 6893 | UInt dis_mov_Sw_Ew ( UChar sorb, |
| 6894 | Int sz, |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6895 | Int delta0 ) |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6896 | { |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6897 | Int len; |
| 6898 | IRTemp addr; |
| 6899 | UChar rm = getIByte(delta0); |
| 6900 | HChar dis_buf[50]; |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6901 | |
| 6902 | vassert(sz == 2 || sz == 4); |
| 6903 | |
| 6904 | if (epartIsReg(rm)) { |
| 6905 | if (sz == 4) |
| 6906 | putIReg(4, eregOfRM(rm), unop(Iop_16Uto32, getSReg(gregOfRM(rm)))); |
| 6907 | else |
| 6908 | putIReg(2, eregOfRM(rm), getSReg(gregOfRM(rm))); |
| 6909 | |
| 6910 | DIP("mov %s,%s\n", nameSReg(gregOfRM(rm)), nameIReg(sz,eregOfRM(rm))); |
| 6911 | return 1+delta0; |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6912 | } else { |
| 6913 | addr = disAMode ( &len, sorb, delta0, dis_buf ); |
| 6914 | storeLE( mkexpr(addr), getSReg(gregOfRM(rm)) ); |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6915 | DIP("mov %s,%s\n", nameSReg(gregOfRM(rm)), dis_buf); |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6916 | return len+delta0; |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6917 | } |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 6918 | } |
| 6919 | |
| 6920 | |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6921 | static |
| 6922 | void dis_push_segreg ( UInt sreg, Int sz ) |
| 6923 | { |
| 6924 | IRTemp t1 = newTemp(Ity_I16); |
| 6925 | IRTemp ta = newTemp(Ity_I32); |
| 6926 | vassert(sz == 2 || sz == 4); |
| 6927 | |
| 6928 | assign( t1, getSReg(sreg) ); |
| 6929 | assign( ta, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(sz)) ); |
| 6930 | putIReg(4, R_ESP, mkexpr(ta)); |
| 6931 | storeLE( mkexpr(ta), mkexpr(t1) ); |
| 6932 | |
sewardj | 5c5f72c | 2006-03-18 11:29:25 +0000 | [diff] [blame] | 6933 | DIP("push%c %s\n", sz==2 ? 'w' : 'l', nameSReg(sreg)); |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6934 | } |
| 6935 | |
| 6936 | static |
| 6937 | void dis_pop_segreg ( UInt sreg, Int sz ) |
| 6938 | { |
| 6939 | IRTemp t1 = newTemp(Ity_I16); |
| 6940 | IRTemp ta = newTemp(Ity_I32); |
| 6941 | vassert(sz == 2 || sz == 4); |
| 6942 | |
| 6943 | assign( ta, getIReg(4, R_ESP) ); |
| 6944 | assign( t1, loadLE(Ity_I16, mkexpr(ta)) ); |
| 6945 | |
| 6946 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(ta), mkU32(sz)) ); |
| 6947 | putSReg( sreg, mkexpr(t1) ); |
sewardj | 5c5f72c | 2006-03-18 11:29:25 +0000 | [diff] [blame] | 6948 | DIP("pop%c %s\n", sz==2 ? 'w' : 'l', nameSReg(sreg)); |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 6949 | } |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 6950 | |
| 6951 | static |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 6952 | void dis_ret ( /*MOD*/DisResult* dres, UInt d32 ) |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 6953 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 6954 | IRTemp t1 = newTemp(Ity_I32); |
| 6955 | IRTemp t2 = newTemp(Ity_I32); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 6956 | assign(t1, getIReg(4,R_ESP)); |
| 6957 | assign(t2, loadLE(Ity_I32,mkexpr(t1))); |
| 6958 | putIReg(4, R_ESP,binop(Iop_Add32, mkexpr(t1), mkU32(4+d32))); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 6959 | jmp_treg(dres, Ijk_Ret, t2); |
| 6960 | vassert(dres->whatNext == Dis_StopHere); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 6961 | } |
| 6962 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 6963 | /*------------------------------------------------------------*/ |
| 6964 | /*--- SSE/SSE2/SSE3 helpers ---*/ |
| 6965 | /*------------------------------------------------------------*/ |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6966 | |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 6967 | /* Indicates whether the op requires a rounding-mode argument. Note |
| 6968 | that this covers only vector floating point arithmetic ops, and |
| 6969 | omits the scalar ones that need rounding modes. Note also that |
| 6970 | inconsistencies here will get picked up later by the IR sanity |
| 6971 | checker, so this isn't correctness-critical. */ |
| 6972 | static Bool requiresRMode ( IROp op ) |
| 6973 | { |
| 6974 | switch (op) { |
| 6975 | /* 128 bit ops */ |
| 6976 | case Iop_Add32Fx4: case Iop_Sub32Fx4: |
| 6977 | case Iop_Mul32Fx4: case Iop_Div32Fx4: |
| 6978 | case Iop_Add64Fx2: case Iop_Sub64Fx2: |
| 6979 | case Iop_Mul64Fx2: case Iop_Div64Fx2: |
| 6980 | return True; |
| 6981 | default: |
| 6982 | break; |
| 6983 | } |
| 6984 | return False; |
| 6985 | } |
| 6986 | |
| 6987 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 6988 | /* Worker function; do not call directly. |
| 6989 | Handles full width G = G `op` E and G = (not G) `op` E. |
| 6990 | */ |
| 6991 | |
| 6992 | static UInt dis_SSE_E_to_G_all_wrk ( |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 6993 | UChar sorb, Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 6994 | const HChar* opname, IROp op, |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 6995 | Bool invertG |
| 6996 | ) |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 6997 | { |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 6998 | HChar dis_buf[50]; |
| 6999 | Int alen; |
| 7000 | IRTemp addr; |
| 7001 | UChar rm = getIByte(delta); |
| 7002 | IRExpr* gpart |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7003 | = invertG ? unop(Iop_NotV128, getXMMReg(gregOfRM(rm))) |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7004 | : getXMMReg(gregOfRM(rm)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 7005 | if (epartIsReg(rm)) { |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 7006 | putXMMReg( |
| 7007 | gregOfRM(rm), |
| 7008 | requiresRMode(op) |
| 7009 | ? triop(op, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 7010 | gpart, |
| 7011 | getXMMReg(eregOfRM(rm))) |
| 7012 | : binop(op, gpart, |
| 7013 | getXMMReg(eregOfRM(rm))) |
| 7014 | ); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 7015 | DIP("%s %s,%s\n", opname, |
| 7016 | nameXMMReg(eregOfRM(rm)), |
| 7017 | nameXMMReg(gregOfRM(rm)) ); |
| 7018 | return delta+1; |
| 7019 | } else { |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7020 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 7021 | putXMMReg( |
| 7022 | gregOfRM(rm), |
| 7023 | requiresRMode(op) |
| 7024 | ? triop(op, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ |
| 7025 | gpart, |
| 7026 | loadLE(Ity_V128, mkexpr(addr))) |
| 7027 | : binop(op, gpart, |
| 7028 | loadLE(Ity_V128, mkexpr(addr))) |
| 7029 | ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7030 | DIP("%s %s,%s\n", opname, |
| 7031 | dis_buf, |
| 7032 | nameXMMReg(gregOfRM(rm)) ); |
| 7033 | return delta+alen; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 7034 | } |
| 7035 | } |
| 7036 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7037 | |
| 7038 | /* All lanes SSE binary operation, G = G `op` E. */ |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7039 | |
| 7040 | static |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 7041 | UInt dis_SSE_E_to_G_all ( UChar sorb, Int delta, const HChar* opname, IROp op ) |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7042 | { |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7043 | return dis_SSE_E_to_G_all_wrk( sorb, delta, opname, op, False ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7044 | } |
| 7045 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7046 | /* All lanes SSE binary operation, G = (not G) `op` E. */ |
| 7047 | |
| 7048 | static |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7049 | UInt dis_SSE_E_to_G_all_invG ( UChar sorb, Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 7050 | const HChar* opname, IROp op ) |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7051 | { |
| 7052 | return dis_SSE_E_to_G_all_wrk( sorb, delta, opname, op, True ); |
| 7053 | } |
| 7054 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 7055 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7056 | /* Lowest 32-bit lane only SSE binary operation, G = G `op` E. */ |
| 7057 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7058 | static UInt dis_SSE_E_to_G_lo32 ( UChar sorb, Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 7059 | const HChar* opname, IROp op ) |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7060 | { |
| 7061 | HChar dis_buf[50]; |
| 7062 | Int alen; |
| 7063 | IRTemp addr; |
| 7064 | UChar rm = getIByte(delta); |
| 7065 | IRExpr* gpart = getXMMReg(gregOfRM(rm)); |
| 7066 | if (epartIsReg(rm)) { |
| 7067 | putXMMReg( gregOfRM(rm), |
| 7068 | binop(op, gpart, |
| 7069 | getXMMReg(eregOfRM(rm))) ); |
| 7070 | DIP("%s %s,%s\n", opname, |
| 7071 | nameXMMReg(eregOfRM(rm)), |
| 7072 | nameXMMReg(gregOfRM(rm)) ); |
| 7073 | return delta+1; |
| 7074 | } else { |
| 7075 | /* We can only do a 32-bit memory read, so the upper 3/4 of the |
| 7076 | E operand needs to be made simply of zeroes. */ |
| 7077 | IRTemp epart = newTemp(Ity_V128); |
| 7078 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7079 | assign( epart, unop( Iop_32UtoV128, |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7080 | loadLE(Ity_I32, mkexpr(addr))) ); |
| 7081 | putXMMReg( gregOfRM(rm), |
| 7082 | binop(op, gpart, mkexpr(epart)) ); |
| 7083 | DIP("%s %s,%s\n", opname, |
| 7084 | dis_buf, |
| 7085 | nameXMMReg(gregOfRM(rm)) ); |
| 7086 | return delta+alen; |
| 7087 | } |
| 7088 | } |
| 7089 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 7090 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 7091 | /* Lower 64-bit lane only SSE binary operation, G = G `op` E. */ |
| 7092 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7093 | static UInt dis_SSE_E_to_G_lo64 ( UChar sorb, Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 7094 | const HChar* opname, IROp op ) |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 7095 | { |
| 7096 | HChar dis_buf[50]; |
| 7097 | Int alen; |
| 7098 | IRTemp addr; |
| 7099 | UChar rm = getIByte(delta); |
| 7100 | IRExpr* gpart = getXMMReg(gregOfRM(rm)); |
| 7101 | if (epartIsReg(rm)) { |
| 7102 | putXMMReg( gregOfRM(rm), |
| 7103 | binop(op, gpart, |
| 7104 | getXMMReg(eregOfRM(rm))) ); |
| 7105 | DIP("%s %s,%s\n", opname, |
| 7106 | nameXMMReg(eregOfRM(rm)), |
| 7107 | nameXMMReg(gregOfRM(rm)) ); |
| 7108 | return delta+1; |
| 7109 | } else { |
| 7110 | /* We can only do a 64-bit memory read, so the upper half of the |
| 7111 | E operand needs to be made simply of zeroes. */ |
| 7112 | IRTemp epart = newTemp(Ity_V128); |
| 7113 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7114 | assign( epart, unop( Iop_64UtoV128, |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 7115 | loadLE(Ity_I64, mkexpr(addr))) ); |
| 7116 | putXMMReg( gregOfRM(rm), |
| 7117 | binop(op, gpart, mkexpr(epart)) ); |
| 7118 | DIP("%s %s,%s\n", opname, |
| 7119 | dis_buf, |
| 7120 | nameXMMReg(gregOfRM(rm)) ); |
| 7121 | return delta+alen; |
| 7122 | } |
| 7123 | } |
| 7124 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 7125 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7126 | /* All lanes unary SSE operation, G = op(E). */ |
| 7127 | |
| 7128 | static UInt dis_SSE_E_to_G_unary_all ( |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7129 | UChar sorb, Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 7130 | const HChar* opname, IROp op |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 7131 | ) |
| 7132 | { |
| 7133 | HChar dis_buf[50]; |
| 7134 | Int alen; |
| 7135 | IRTemp addr; |
| 7136 | UChar rm = getIByte(delta); |
sewardj | 8bb1c9e | 2015-04-07 09:36:35 +0000 | [diff] [blame] | 7137 | // Sqrt32Fx4 and Sqrt64Fx2 take a rounding mode, which is faked |
| 7138 | // up in the usual way. |
| 7139 | Bool needsIRRM = op == Iop_Sqrt32Fx4 || op == Iop_Sqrt64Fx2; |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 7140 | if (epartIsReg(rm)) { |
sewardj | 8bb1c9e | 2015-04-07 09:36:35 +0000 | [diff] [blame] | 7141 | IRExpr* src = getXMMReg(eregOfRM(rm)); |
| 7142 | /* XXXROUNDINGFIXME */ |
| 7143 | IRExpr* res = needsIRRM ? binop(op, get_FAKE_roundingmode(), src) |
| 7144 | : unop(op, src); |
| 7145 | putXMMReg( gregOfRM(rm), res ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 7146 | DIP("%s %s,%s\n", opname, |
| 7147 | nameXMMReg(eregOfRM(rm)), |
| 7148 | nameXMMReg(gregOfRM(rm)) ); |
| 7149 | return delta+1; |
| 7150 | } else { |
| 7151 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
sewardj | 8bb1c9e | 2015-04-07 09:36:35 +0000 | [diff] [blame] | 7152 | IRExpr* src = loadLE(Ity_V128, mkexpr(addr)); |
| 7153 | /* XXXROUNDINGFIXME */ |
| 7154 | IRExpr* res = needsIRRM ? binop(op, get_FAKE_roundingmode(), src) |
| 7155 | : unop(op, src); |
| 7156 | putXMMReg( gregOfRM(rm), res ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 7157 | DIP("%s %s,%s\n", opname, |
| 7158 | dis_buf, |
| 7159 | nameXMMReg(gregOfRM(rm)) ); |
| 7160 | return delta+alen; |
| 7161 | } |
| 7162 | } |
| 7163 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 7164 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7165 | /* Lowest 32-bit lane only unary SSE operation, G = op(E). */ |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 7166 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7167 | static UInt dis_SSE_E_to_G_unary_lo32 ( |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7168 | UChar sorb, Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 7169 | const HChar* opname, IROp op |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7170 | ) |
| 7171 | { |
| 7172 | /* First we need to get the old G value and patch the low 32 bits |
| 7173 | of the E operand into it. Then apply op and write back to G. */ |
| 7174 | HChar dis_buf[50]; |
| 7175 | Int alen; |
| 7176 | IRTemp addr; |
| 7177 | UChar rm = getIByte(delta); |
| 7178 | IRTemp oldG0 = newTemp(Ity_V128); |
| 7179 | IRTemp oldG1 = newTemp(Ity_V128); |
| 7180 | |
| 7181 | assign( oldG0, getXMMReg(gregOfRM(rm)) ); |
| 7182 | |
| 7183 | if (epartIsReg(rm)) { |
| 7184 | assign( oldG1, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7185 | binop( Iop_SetV128lo32, |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7186 | mkexpr(oldG0), |
sewardj | 35579be | 2004-12-06 00:36:25 +0000 | [diff] [blame] | 7187 | getXMMRegLane32(eregOfRM(rm), 0)) ); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7188 | putXMMReg( gregOfRM(rm), unop(op, mkexpr(oldG1)) ); |
| 7189 | DIP("%s %s,%s\n", opname, |
| 7190 | nameXMMReg(eregOfRM(rm)), |
| 7191 | nameXMMReg(gregOfRM(rm)) ); |
| 7192 | return delta+1; |
| 7193 | } else { |
| 7194 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 7195 | assign( oldG1, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7196 | binop( Iop_SetV128lo32, |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7197 | mkexpr(oldG0), |
| 7198 | loadLE(Ity_I32, mkexpr(addr)) )); |
| 7199 | putXMMReg( gregOfRM(rm), unop(op, mkexpr(oldG1)) ); |
| 7200 | DIP("%s %s,%s\n", opname, |
| 7201 | dis_buf, |
| 7202 | nameXMMReg(gregOfRM(rm)) ); |
| 7203 | return delta+alen; |
| 7204 | } |
| 7205 | } |
| 7206 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 7207 | |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 7208 | /* Lowest 64-bit lane only unary SSE operation, G = op(E). */ |
| 7209 | |
| 7210 | static UInt dis_SSE_E_to_G_unary_lo64 ( |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7211 | UChar sorb, Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 7212 | const HChar* opname, IROp op |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 7213 | ) |
| 7214 | { |
| 7215 | /* First we need to get the old G value and patch the low 64 bits |
| 7216 | of the E operand into it. Then apply op and write back to G. */ |
| 7217 | HChar dis_buf[50]; |
| 7218 | Int alen; |
| 7219 | IRTemp addr; |
| 7220 | UChar rm = getIByte(delta); |
| 7221 | IRTemp oldG0 = newTemp(Ity_V128); |
| 7222 | IRTemp oldG1 = newTemp(Ity_V128); |
| 7223 | |
| 7224 | assign( oldG0, getXMMReg(gregOfRM(rm)) ); |
| 7225 | |
| 7226 | if (epartIsReg(rm)) { |
| 7227 | assign( oldG1, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7228 | binop( Iop_SetV128lo64, |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 7229 | mkexpr(oldG0), |
| 7230 | getXMMRegLane64(eregOfRM(rm), 0)) ); |
| 7231 | putXMMReg( gregOfRM(rm), unop(op, mkexpr(oldG1)) ); |
| 7232 | DIP("%s %s,%s\n", opname, |
| 7233 | nameXMMReg(eregOfRM(rm)), |
| 7234 | nameXMMReg(gregOfRM(rm)) ); |
| 7235 | return delta+1; |
| 7236 | } else { |
| 7237 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 7238 | assign( oldG1, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7239 | binop( Iop_SetV128lo64, |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 7240 | mkexpr(oldG0), |
| 7241 | loadLE(Ity_I64, mkexpr(addr)) )); |
| 7242 | putXMMReg( gregOfRM(rm), unop(op, mkexpr(oldG1)) ); |
| 7243 | DIP("%s %s,%s\n", opname, |
| 7244 | dis_buf, |
| 7245 | nameXMMReg(gregOfRM(rm)) ); |
| 7246 | return delta+alen; |
| 7247 | } |
| 7248 | } |
| 7249 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 7250 | |
| 7251 | /* SSE integer binary operation: |
| 7252 | G = G `op` E (eLeft == False) |
| 7253 | G = E `op` G (eLeft == True) |
| 7254 | */ |
| 7255 | static UInt dis_SSEint_E_to_G( |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7256 | UChar sorb, Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 7257 | const HChar* opname, IROp op, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 7258 | Bool eLeft |
| 7259 | ) |
| 7260 | { |
| 7261 | HChar dis_buf[50]; |
| 7262 | Int alen; |
| 7263 | IRTemp addr; |
| 7264 | UChar rm = getIByte(delta); |
| 7265 | IRExpr* gpart = getXMMReg(gregOfRM(rm)); |
| 7266 | IRExpr* epart = NULL; |
| 7267 | if (epartIsReg(rm)) { |
| 7268 | epart = getXMMReg(eregOfRM(rm)); |
| 7269 | DIP("%s %s,%s\n", opname, |
| 7270 | nameXMMReg(eregOfRM(rm)), |
| 7271 | nameXMMReg(gregOfRM(rm)) ); |
| 7272 | delta += 1; |
| 7273 | } else { |
| 7274 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 7275 | epart = loadLE(Ity_V128, mkexpr(addr)); |
| 7276 | DIP("%s %s,%s\n", opname, |
| 7277 | dis_buf, |
| 7278 | nameXMMReg(gregOfRM(rm)) ); |
| 7279 | delta += alen; |
| 7280 | } |
| 7281 | putXMMReg( gregOfRM(rm), |
| 7282 | eLeft ? binop(op, epart, gpart) |
| 7283 | : binop(op, gpart, epart) ); |
| 7284 | return delta; |
| 7285 | } |
| 7286 | |
| 7287 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 7288 | /* Helper for doing SSE FP comparisons. */ |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 7289 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7290 | static void findSSECmpOp ( Bool* needNot, IROp* op, |
| 7291 | Int imm8, Bool all_lanes, Int sz ) |
| 7292 | { |
| 7293 | imm8 &= 7; |
| 7294 | *needNot = False; |
| 7295 | *op = Iop_INVALID; |
| 7296 | if (imm8 >= 4) { |
| 7297 | *needNot = True; |
| 7298 | imm8 -= 4; |
| 7299 | } |
| 7300 | |
| 7301 | if (sz == 4 && all_lanes) { |
| 7302 | switch (imm8) { |
| 7303 | case 0: *op = Iop_CmpEQ32Fx4; return; |
| 7304 | case 1: *op = Iop_CmpLT32Fx4; return; |
| 7305 | case 2: *op = Iop_CmpLE32Fx4; return; |
| 7306 | case 3: *op = Iop_CmpUN32Fx4; return; |
| 7307 | default: break; |
| 7308 | } |
| 7309 | } |
| 7310 | if (sz == 4 && !all_lanes) { |
| 7311 | switch (imm8) { |
| 7312 | case 0: *op = Iop_CmpEQ32F0x4; return; |
| 7313 | case 1: *op = Iop_CmpLT32F0x4; return; |
| 7314 | case 2: *op = Iop_CmpLE32F0x4; return; |
| 7315 | case 3: *op = Iop_CmpUN32F0x4; return; |
| 7316 | default: break; |
| 7317 | } |
| 7318 | } |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 7319 | if (sz == 8 && all_lanes) { |
| 7320 | switch (imm8) { |
| 7321 | case 0: *op = Iop_CmpEQ64Fx2; return; |
| 7322 | case 1: *op = Iop_CmpLT64Fx2; return; |
| 7323 | case 2: *op = Iop_CmpLE64Fx2; return; |
| 7324 | case 3: *op = Iop_CmpUN64Fx2; return; |
| 7325 | default: break; |
| 7326 | } |
| 7327 | } |
| 7328 | if (sz == 8 && !all_lanes) { |
| 7329 | switch (imm8) { |
| 7330 | case 0: *op = Iop_CmpEQ64F0x2; return; |
| 7331 | case 1: *op = Iop_CmpLT64F0x2; return; |
| 7332 | case 2: *op = Iop_CmpLE64F0x2; return; |
| 7333 | case 3: *op = Iop_CmpUN64F0x2; return; |
| 7334 | default: break; |
| 7335 | } |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7336 | } |
| 7337 | vpanic("findSSECmpOp(x86,guest)"); |
| 7338 | } |
| 7339 | |
sewardj | 33c69e5 | 2006-01-01 17:15:19 +0000 | [diff] [blame] | 7340 | /* Handles SSE 32F/64F comparisons. */ |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 7341 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7342 | static UInt dis_SSEcmp_E_to_G ( UChar sorb, Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 7343 | const HChar* opname, Bool all_lanes, Int sz ) |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7344 | { |
| 7345 | HChar dis_buf[50]; |
| 7346 | Int alen, imm8; |
| 7347 | IRTemp addr; |
| 7348 | Bool needNot = False; |
| 7349 | IROp op = Iop_INVALID; |
| 7350 | IRTemp plain = newTemp(Ity_V128); |
| 7351 | UChar rm = getIByte(delta); |
| 7352 | UShort mask = 0; |
| 7353 | vassert(sz == 4 || sz == 8); |
| 7354 | if (epartIsReg(rm)) { |
| 7355 | imm8 = getIByte(delta+1); |
| 7356 | findSSECmpOp(&needNot, &op, imm8, all_lanes, sz); |
| 7357 | assign( plain, binop(op, getXMMReg(gregOfRM(rm)), |
| 7358 | getXMMReg(eregOfRM(rm))) ); |
| 7359 | delta += 2; |
| 7360 | DIP("%s $%d,%s,%s\n", opname, |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 7361 | imm8, |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7362 | nameXMMReg(eregOfRM(rm)), |
| 7363 | nameXMMReg(gregOfRM(rm)) ); |
| 7364 | } else { |
| 7365 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 7366 | imm8 = getIByte(delta+alen); |
| 7367 | findSSECmpOp(&needNot, &op, imm8, all_lanes, sz); |
sewardj | 33c69e5 | 2006-01-01 17:15:19 +0000 | [diff] [blame] | 7368 | assign( plain, |
| 7369 | binop( |
| 7370 | op, |
| 7371 | getXMMReg(gregOfRM(rm)), |
| 7372 | all_lanes ? loadLE(Ity_V128, mkexpr(addr)) |
| 7373 | : sz == 8 ? unop( Iop_64UtoV128, loadLE(Ity_I64, mkexpr(addr))) |
| 7374 | : /*sz==4*/ unop( Iop_32UtoV128, loadLE(Ity_I32, mkexpr(addr))) |
| 7375 | ) |
| 7376 | ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7377 | delta += alen+1; |
| 7378 | DIP("%s $%d,%s,%s\n", opname, |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 7379 | imm8, |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7380 | dis_buf, |
| 7381 | nameXMMReg(gregOfRM(rm)) ); |
| 7382 | } |
| 7383 | |
sewardj | 2e38386 | 2004-12-12 16:46:47 +0000 | [diff] [blame] | 7384 | if (needNot && all_lanes) { |
| 7385 | putXMMReg( gregOfRM(rm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7386 | unop(Iop_NotV128, mkexpr(plain)) ); |
sewardj | 2e38386 | 2004-12-12 16:46:47 +0000 | [diff] [blame] | 7387 | } |
| 7388 | else |
| 7389 | if (needNot && !all_lanes) { |
sewardj | 9b45b48 | 2005-02-07 01:42:18 +0000 | [diff] [blame] | 7390 | mask = toUShort( sz==4 ? 0x000F : 0x00FF ); |
sewardj | 2e38386 | 2004-12-12 16:46:47 +0000 | [diff] [blame] | 7391 | putXMMReg( gregOfRM(rm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7392 | binop(Iop_XorV128, mkexpr(plain), mkV128(mask)) ); |
sewardj | 2e38386 | 2004-12-12 16:46:47 +0000 | [diff] [blame] | 7393 | } |
| 7394 | else { |
| 7395 | putXMMReg( gregOfRM(rm), mkexpr(plain) ); |
| 7396 | } |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7397 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 7398 | return delta; |
| 7399 | } |
| 7400 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7401 | |
| 7402 | /* Vector by scalar shift of G by the amount specified at the bottom |
| 7403 | of E. */ |
| 7404 | |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 7405 | static UInt dis_SSE_shiftG_byE ( UChar sorb, Int delta, |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 7406 | const HChar* opname, IROp op ) |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7407 | { |
| 7408 | HChar dis_buf[50]; |
| 7409 | Int alen, size; |
| 7410 | IRTemp addr; |
| 7411 | Bool shl, shr, sar; |
| 7412 | UChar rm = getIByte(delta); |
| 7413 | IRTemp g0 = newTemp(Ity_V128); |
| 7414 | IRTemp g1 = newTemp(Ity_V128); |
| 7415 | IRTemp amt = newTemp(Ity_I32); |
| 7416 | IRTemp amt8 = newTemp(Ity_I8); |
| 7417 | if (epartIsReg(rm)) { |
| 7418 | assign( amt, getXMMRegLane32(eregOfRM(rm), 0) ); |
| 7419 | DIP("%s %s,%s\n", opname, |
| 7420 | nameXMMReg(eregOfRM(rm)), |
| 7421 | nameXMMReg(gregOfRM(rm)) ); |
| 7422 | delta++; |
| 7423 | } else { |
| 7424 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 7425 | assign( amt, loadLE(Ity_I32, mkexpr(addr)) ); |
| 7426 | DIP("%s %s,%s\n", opname, |
| 7427 | dis_buf, |
| 7428 | nameXMMReg(gregOfRM(rm)) ); |
| 7429 | delta += alen; |
| 7430 | } |
| 7431 | assign( g0, getXMMReg(gregOfRM(rm)) ); |
| 7432 | assign( amt8, unop(Iop_32to8, mkexpr(amt)) ); |
| 7433 | |
| 7434 | shl = shr = sar = False; |
| 7435 | size = 0; |
| 7436 | switch (op) { |
| 7437 | case Iop_ShlN16x8: shl = True; size = 32; break; |
| 7438 | case Iop_ShlN32x4: shl = True; size = 32; break; |
| 7439 | case Iop_ShlN64x2: shl = True; size = 64; break; |
| 7440 | case Iop_SarN16x8: sar = True; size = 16; break; |
| 7441 | case Iop_SarN32x4: sar = True; size = 32; break; |
| 7442 | case Iop_ShrN16x8: shr = True; size = 16; break; |
| 7443 | case Iop_ShrN32x4: shr = True; size = 32; break; |
| 7444 | case Iop_ShrN64x2: shr = True; size = 64; break; |
| 7445 | default: vassert(0); |
| 7446 | } |
| 7447 | |
| 7448 | if (shl || shr) { |
| 7449 | assign( |
| 7450 | g1, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7451 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 7452 | binop(Iop_CmpLT32U,mkexpr(amt),mkU32(size)), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7453 | binop(op, mkexpr(g0), mkexpr(amt8)), |
| 7454 | mkV128(0x0000) |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7455 | ) |
| 7456 | ); |
| 7457 | } else |
| 7458 | if (sar) { |
| 7459 | assign( |
| 7460 | g1, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7461 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 7462 | binop(Iop_CmpLT32U,mkexpr(amt),mkU32(size)), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7463 | binop(op, mkexpr(g0), mkexpr(amt8)), |
| 7464 | binop(op, mkexpr(g0), mkU8(size-1)) |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7465 | ) |
| 7466 | ); |
| 7467 | } else { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 7468 | /*NOTREACHED*/ |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7469 | vassert(0); |
| 7470 | } |
| 7471 | |
| 7472 | putXMMReg( gregOfRM(rm), mkexpr(g1) ); |
| 7473 | return delta; |
| 7474 | } |
| 7475 | |
| 7476 | |
| 7477 | /* Vector by scalar shift of E by an immediate byte. */ |
| 7478 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 7479 | static |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 7480 | UInt dis_SSE_shiftE_imm ( Int delta, const HChar* opname, IROp op ) |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7481 | { |
| 7482 | Bool shl, shr, sar; |
| 7483 | UChar rm = getIByte(delta); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 7484 | IRTemp e0 = newTemp(Ity_V128); |
| 7485 | IRTemp e1 = newTemp(Ity_V128); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7486 | UChar amt, size; |
| 7487 | vassert(epartIsReg(rm)); |
| 7488 | vassert(gregOfRM(rm) == 2 |
| 7489 | || gregOfRM(rm) == 4 || gregOfRM(rm) == 6); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 7490 | amt = getIByte(delta+1); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7491 | delta += 2; |
| 7492 | DIP("%s $%d,%s\n", opname, |
| 7493 | (Int)amt, |
| 7494 | nameXMMReg(eregOfRM(rm)) ); |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 7495 | assign( e0, getXMMReg(eregOfRM(rm)) ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7496 | |
| 7497 | shl = shr = sar = False; |
| 7498 | size = 0; |
| 7499 | switch (op) { |
| 7500 | case Iop_ShlN16x8: shl = True; size = 16; break; |
| 7501 | case Iop_ShlN32x4: shl = True; size = 32; break; |
| 7502 | case Iop_ShlN64x2: shl = True; size = 64; break; |
| 7503 | case Iop_SarN16x8: sar = True; size = 16; break; |
| 7504 | case Iop_SarN32x4: sar = True; size = 32; break; |
| 7505 | case Iop_ShrN16x8: shr = True; size = 16; break; |
| 7506 | case Iop_ShrN32x4: shr = True; size = 32; break; |
| 7507 | case Iop_ShrN64x2: shr = True; size = 64; break; |
| 7508 | default: vassert(0); |
| 7509 | } |
| 7510 | |
| 7511 | if (shl || shr) { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 7512 | assign( e1, amt >= size |
| 7513 | ? mkV128(0x0000) |
| 7514 | : binop(op, mkexpr(e0), mkU8(amt)) |
| 7515 | ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7516 | } else |
| 7517 | if (sar) { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 7518 | assign( e1, amt >= size |
| 7519 | ? binop(op, mkexpr(e0), mkU8(size-1)) |
| 7520 | : binop(op, mkexpr(e0), mkU8(amt)) |
| 7521 | ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7522 | } else { |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 7523 | /*NOTREACHED*/ |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7524 | vassert(0); |
| 7525 | } |
| 7526 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 7527 | putXMMReg( eregOfRM(rm), mkexpr(e1) ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7528 | return delta; |
| 7529 | } |
| 7530 | |
| 7531 | |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 7532 | /* Get the current SSE rounding mode. */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 7533 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 7534 | static IRExpr* /* :: Ity_I32 */ get_sse_roundingmode ( void ) |
| 7535 | { |
| 7536 | return binop( Iop_And32, |
| 7537 | IRExpr_Get( OFFB_SSEROUND, Ity_I32 ), |
| 7538 | mkU32(3) ); |
| 7539 | } |
| 7540 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 7541 | static void put_sse_roundingmode ( IRExpr* sseround ) |
| 7542 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 7543 | vassert(typeOfIRExpr(irsb->tyenv, sseround) == Ity_I32); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 7544 | stmt( IRStmt_Put( OFFB_SSEROUND, sseround ) ); |
| 7545 | } |
| 7546 | |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 7547 | /* Break a 128-bit value up into four 32-bit ints. */ |
| 7548 | |
| 7549 | static void breakup128to32s ( IRTemp t128, |
| 7550 | /*OUTs*/ |
| 7551 | IRTemp* t3, IRTemp* t2, |
| 7552 | IRTemp* t1, IRTemp* t0 ) |
| 7553 | { |
| 7554 | IRTemp hi64 = newTemp(Ity_I64); |
| 7555 | IRTemp lo64 = newTemp(Ity_I64); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7556 | assign( hi64, unop(Iop_V128HIto64, mkexpr(t128)) ); |
| 7557 | assign( lo64, unop(Iop_V128to64, mkexpr(t128)) ); |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 7558 | |
| 7559 | vassert(t0 && *t0 == IRTemp_INVALID); |
| 7560 | vassert(t1 && *t1 == IRTemp_INVALID); |
| 7561 | vassert(t2 && *t2 == IRTemp_INVALID); |
| 7562 | vassert(t3 && *t3 == IRTemp_INVALID); |
| 7563 | |
| 7564 | *t0 = newTemp(Ity_I32); |
| 7565 | *t1 = newTemp(Ity_I32); |
| 7566 | *t2 = newTemp(Ity_I32); |
| 7567 | *t3 = newTemp(Ity_I32); |
| 7568 | assign( *t0, unop(Iop_64to32, mkexpr(lo64)) ); |
| 7569 | assign( *t1, unop(Iop_64HIto32, mkexpr(lo64)) ); |
| 7570 | assign( *t2, unop(Iop_64to32, mkexpr(hi64)) ); |
| 7571 | assign( *t3, unop(Iop_64HIto32, mkexpr(hi64)) ); |
| 7572 | } |
| 7573 | |
| 7574 | /* Construct a 128-bit value from four 32-bit ints. */ |
| 7575 | |
| 7576 | static IRExpr* mk128from32s ( IRTemp t3, IRTemp t2, |
| 7577 | IRTemp t1, IRTemp t0 ) |
| 7578 | { |
| 7579 | return |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 7580 | binop( Iop_64HLtoV128, |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 7581 | binop(Iop_32HLto64, mkexpr(t3), mkexpr(t2)), |
| 7582 | binop(Iop_32HLto64, mkexpr(t1), mkexpr(t0)) |
| 7583 | ); |
| 7584 | } |
| 7585 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 7586 | /* Break a 64-bit value up into four 16-bit ints. */ |
| 7587 | |
| 7588 | static void breakup64to16s ( IRTemp t64, |
| 7589 | /*OUTs*/ |
| 7590 | IRTemp* t3, IRTemp* t2, |
| 7591 | IRTemp* t1, IRTemp* t0 ) |
| 7592 | { |
| 7593 | IRTemp hi32 = newTemp(Ity_I32); |
| 7594 | IRTemp lo32 = newTemp(Ity_I32); |
| 7595 | assign( hi32, unop(Iop_64HIto32, mkexpr(t64)) ); |
| 7596 | assign( lo32, unop(Iop_64to32, mkexpr(t64)) ); |
| 7597 | |
| 7598 | vassert(t0 && *t0 == IRTemp_INVALID); |
| 7599 | vassert(t1 && *t1 == IRTemp_INVALID); |
| 7600 | vassert(t2 && *t2 == IRTemp_INVALID); |
| 7601 | vassert(t3 && *t3 == IRTemp_INVALID); |
| 7602 | |
| 7603 | *t0 = newTemp(Ity_I16); |
| 7604 | *t1 = newTemp(Ity_I16); |
| 7605 | *t2 = newTemp(Ity_I16); |
| 7606 | *t3 = newTemp(Ity_I16); |
| 7607 | assign( *t0, unop(Iop_32to16, mkexpr(lo32)) ); |
| 7608 | assign( *t1, unop(Iop_32HIto16, mkexpr(lo32)) ); |
| 7609 | assign( *t2, unop(Iop_32to16, mkexpr(hi32)) ); |
| 7610 | assign( *t3, unop(Iop_32HIto16, mkexpr(hi32)) ); |
| 7611 | } |
| 7612 | |
| 7613 | /* Construct a 64-bit value from four 16-bit ints. */ |
| 7614 | |
| 7615 | static IRExpr* mk64from16s ( IRTemp t3, IRTemp t2, |
| 7616 | IRTemp t1, IRTemp t0 ) |
| 7617 | { |
| 7618 | return |
| 7619 | binop( Iop_32HLto64, |
| 7620 | binop(Iop_16HLto32, mkexpr(t3), mkexpr(t2)), |
| 7621 | binop(Iop_16HLto32, mkexpr(t1), mkexpr(t0)) |
| 7622 | ); |
| 7623 | } |
| 7624 | |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 7625 | /* Generate IR to set the guest %EFLAGS from the pushfl-format image |
| 7626 | in the given 32-bit temporary. The flags that are set are: O S Z A |
| 7627 | C P D ID AC. |
| 7628 | |
| 7629 | In all cases, code to set AC is generated. However, VEX actually |
| 7630 | ignores the AC value and so can optionally emit an emulation |
| 7631 | warning when it is enabled. In this routine, an emulation warning |
| 7632 | is only emitted if emit_AC_emwarn is True, in which case |
| 7633 | next_insn_EIP must be correct (this allows for correct code |
| 7634 | generation for popfl/popfw). If emit_AC_emwarn is False, |
| 7635 | next_insn_EIP is unimportant (this allows for easy if kludgey code |
| 7636 | generation for IRET.) */ |
| 7637 | |
| 7638 | static |
| 7639 | void set_EFLAGS_from_value ( IRTemp t1, |
| 7640 | Bool emit_AC_emwarn, |
| 7641 | Addr32 next_insn_EIP ) |
| 7642 | { |
| 7643 | vassert(typeOfIRTemp(irsb->tyenv,t1) == Ity_I32); |
| 7644 | |
| 7645 | /* t1 is the flag word. Mask out everything except OSZACP and set |
| 7646 | the flags thunk to X86G_CC_OP_COPY. */ |
| 7647 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 7648 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 7649 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
| 7650 | binop(Iop_And32, |
| 7651 | mkexpr(t1), |
| 7652 | mkU32( X86G_CC_MASK_C | X86G_CC_MASK_P |
| 7653 | | X86G_CC_MASK_A | X86G_CC_MASK_Z |
| 7654 | | X86G_CC_MASK_S| X86G_CC_MASK_O ) |
| 7655 | ) |
| 7656 | ) |
| 7657 | ); |
| 7658 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 7659 | elimination of previous stores to this field work better. */ |
| 7660 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 7661 | |
| 7662 | /* Also need to set the D flag, which is held in bit 10 of t1. |
| 7663 | If zero, put 1 in OFFB_DFLAG, else -1 in OFFB_DFLAG. */ |
| 7664 | stmt( IRStmt_Put( |
| 7665 | OFFB_DFLAG, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7666 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 7667 | unop(Iop_32to1, |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 7668 | binop(Iop_And32, |
| 7669 | binop(Iop_Shr32, mkexpr(t1), mkU8(10)), |
| 7670 | mkU32(1))), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7671 | mkU32(0xFFFFFFFF), |
| 7672 | mkU32(1))) |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 7673 | ); |
| 7674 | |
| 7675 | /* Set the ID flag */ |
| 7676 | stmt( IRStmt_Put( |
| 7677 | OFFB_IDFLAG, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7678 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 7679 | unop(Iop_32to1, |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 7680 | binop(Iop_And32, |
| 7681 | binop(Iop_Shr32, mkexpr(t1), mkU8(21)), |
| 7682 | mkU32(1))), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7683 | mkU32(1), |
| 7684 | mkU32(0))) |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 7685 | ); |
| 7686 | |
| 7687 | /* And set the AC flag. If setting it 1 to, possibly emit an |
| 7688 | emulation warning. */ |
| 7689 | stmt( IRStmt_Put( |
| 7690 | OFFB_ACFLAG, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7691 | IRExpr_ITE( |
sewardj | 009230b | 2013-01-26 11:47:55 +0000 | [diff] [blame] | 7692 | unop(Iop_32to1, |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 7693 | binop(Iop_And32, |
| 7694 | binop(Iop_Shr32, mkexpr(t1), mkU8(18)), |
| 7695 | mkU32(1))), |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 7696 | mkU32(1), |
| 7697 | mkU32(0))) |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 7698 | ); |
| 7699 | |
| 7700 | if (emit_AC_emwarn) { |
| 7701 | put_emwarn( mkU32(EmWarn_X86_acFlag) ); |
| 7702 | stmt( |
| 7703 | IRStmt_Exit( |
| 7704 | binop( Iop_CmpNE32, |
| 7705 | binop(Iop_And32, mkexpr(t1), mkU32(1<<18)), |
| 7706 | mkU32(0) ), |
| 7707 | Ijk_EmWarn, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 7708 | IRConst_U32( next_insn_EIP ), |
| 7709 | OFFB_EIP |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 7710 | ) |
| 7711 | ); |
| 7712 | } |
| 7713 | } |
| 7714 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 7715 | |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 7716 | /* Helper for the SSSE3 (not SSE3) PMULHRSW insns. Given two 64-bit |
| 7717 | values (aa,bb), computes, for each of the 4 16-bit lanes: |
| 7718 | |
| 7719 | (((aa_lane *s32 bb_lane) >>u 14) + 1) >>u 1 |
| 7720 | */ |
| 7721 | static IRExpr* dis_PMULHRSW_helper ( IRExpr* aax, IRExpr* bbx ) |
| 7722 | { |
| 7723 | IRTemp aa = newTemp(Ity_I64); |
| 7724 | IRTemp bb = newTemp(Ity_I64); |
| 7725 | IRTemp aahi32s = newTemp(Ity_I64); |
| 7726 | IRTemp aalo32s = newTemp(Ity_I64); |
| 7727 | IRTemp bbhi32s = newTemp(Ity_I64); |
| 7728 | IRTemp bblo32s = newTemp(Ity_I64); |
| 7729 | IRTemp rHi = newTemp(Ity_I64); |
| 7730 | IRTemp rLo = newTemp(Ity_I64); |
| 7731 | IRTemp one32x2 = newTemp(Ity_I64); |
| 7732 | assign(aa, aax); |
| 7733 | assign(bb, bbx); |
| 7734 | assign( aahi32s, |
| 7735 | binop(Iop_SarN32x2, |
| 7736 | binop(Iop_InterleaveHI16x4, mkexpr(aa), mkexpr(aa)), |
| 7737 | mkU8(16) )); |
| 7738 | assign( aalo32s, |
| 7739 | binop(Iop_SarN32x2, |
| 7740 | binop(Iop_InterleaveLO16x4, mkexpr(aa), mkexpr(aa)), |
| 7741 | mkU8(16) )); |
| 7742 | assign( bbhi32s, |
| 7743 | binop(Iop_SarN32x2, |
| 7744 | binop(Iop_InterleaveHI16x4, mkexpr(bb), mkexpr(bb)), |
| 7745 | mkU8(16) )); |
| 7746 | assign( bblo32s, |
| 7747 | binop(Iop_SarN32x2, |
| 7748 | binop(Iop_InterleaveLO16x4, mkexpr(bb), mkexpr(bb)), |
| 7749 | mkU8(16) )); |
| 7750 | assign(one32x2, mkU64( (1ULL << 32) + 1 )); |
| 7751 | assign( |
| 7752 | rHi, |
| 7753 | binop( |
| 7754 | Iop_ShrN32x2, |
| 7755 | binop( |
| 7756 | Iop_Add32x2, |
| 7757 | binop( |
| 7758 | Iop_ShrN32x2, |
| 7759 | binop(Iop_Mul32x2, mkexpr(aahi32s), mkexpr(bbhi32s)), |
| 7760 | mkU8(14) |
| 7761 | ), |
| 7762 | mkexpr(one32x2) |
| 7763 | ), |
| 7764 | mkU8(1) |
| 7765 | ) |
| 7766 | ); |
| 7767 | assign( |
| 7768 | rLo, |
| 7769 | binop( |
| 7770 | Iop_ShrN32x2, |
| 7771 | binop( |
| 7772 | Iop_Add32x2, |
| 7773 | binop( |
| 7774 | Iop_ShrN32x2, |
| 7775 | binop(Iop_Mul32x2, mkexpr(aalo32s), mkexpr(bblo32s)), |
| 7776 | mkU8(14) |
| 7777 | ), |
| 7778 | mkexpr(one32x2) |
| 7779 | ), |
| 7780 | mkU8(1) |
| 7781 | ) |
| 7782 | ); |
| 7783 | return |
| 7784 | binop(Iop_CatEvenLanes16x4, mkexpr(rHi), mkexpr(rLo)); |
| 7785 | } |
| 7786 | |
| 7787 | /* Helper for the SSSE3 (not SSE3) PSIGN{B,W,D} insns. Given two 64-bit |
| 7788 | values (aa,bb), computes, for each lane: |
| 7789 | |
| 7790 | if aa_lane < 0 then - bb_lane |
| 7791 | else if aa_lane > 0 then bb_lane |
| 7792 | else 0 |
| 7793 | */ |
| 7794 | static IRExpr* dis_PSIGN_helper ( IRExpr* aax, IRExpr* bbx, Int laneszB ) |
| 7795 | { |
| 7796 | IRTemp aa = newTemp(Ity_I64); |
| 7797 | IRTemp bb = newTemp(Ity_I64); |
| 7798 | IRTemp zero = newTemp(Ity_I64); |
| 7799 | IRTemp bbNeg = newTemp(Ity_I64); |
| 7800 | IRTemp negMask = newTemp(Ity_I64); |
| 7801 | IRTemp posMask = newTemp(Ity_I64); |
| 7802 | IROp opSub = Iop_INVALID; |
| 7803 | IROp opCmpGTS = Iop_INVALID; |
| 7804 | |
| 7805 | switch (laneszB) { |
| 7806 | case 1: opSub = Iop_Sub8x8; opCmpGTS = Iop_CmpGT8Sx8; break; |
| 7807 | case 2: opSub = Iop_Sub16x4; opCmpGTS = Iop_CmpGT16Sx4; break; |
| 7808 | case 4: opSub = Iop_Sub32x2; opCmpGTS = Iop_CmpGT32Sx2; break; |
| 7809 | default: vassert(0); |
| 7810 | } |
| 7811 | |
| 7812 | assign( aa, aax ); |
| 7813 | assign( bb, bbx ); |
| 7814 | assign( zero, mkU64(0) ); |
| 7815 | assign( bbNeg, binop(opSub, mkexpr(zero), mkexpr(bb)) ); |
| 7816 | assign( negMask, binop(opCmpGTS, mkexpr(zero), mkexpr(aa)) ); |
| 7817 | assign( posMask, binop(opCmpGTS, mkexpr(aa), mkexpr(zero)) ); |
| 7818 | |
| 7819 | return |
| 7820 | binop(Iop_Or64, |
| 7821 | binop(Iop_And64, mkexpr(bb), mkexpr(posMask)), |
| 7822 | binop(Iop_And64, mkexpr(bbNeg), mkexpr(negMask)) ); |
| 7823 | |
| 7824 | } |
| 7825 | |
| 7826 | /* Helper for the SSSE3 (not SSE3) PABS{B,W,D} insns. Given a 64-bit |
| 7827 | value aa, computes, for each lane |
| 7828 | |
| 7829 | if aa < 0 then -aa else aa |
| 7830 | |
| 7831 | Note that the result is interpreted as unsigned, so that the |
| 7832 | absolute value of the most negative signed input can be |
| 7833 | represented. |
| 7834 | */ |
| 7835 | static IRExpr* dis_PABS_helper ( IRExpr* aax, Int laneszB ) |
| 7836 | { |
| 7837 | IRTemp aa = newTemp(Ity_I64); |
| 7838 | IRTemp zero = newTemp(Ity_I64); |
| 7839 | IRTemp aaNeg = newTemp(Ity_I64); |
| 7840 | IRTemp negMask = newTemp(Ity_I64); |
| 7841 | IRTemp posMask = newTemp(Ity_I64); |
| 7842 | IROp opSub = Iop_INVALID; |
| 7843 | IROp opSarN = Iop_INVALID; |
| 7844 | |
| 7845 | switch (laneszB) { |
| 7846 | case 1: opSub = Iop_Sub8x8; opSarN = Iop_SarN8x8; break; |
| 7847 | case 2: opSub = Iop_Sub16x4; opSarN = Iop_SarN16x4; break; |
| 7848 | case 4: opSub = Iop_Sub32x2; opSarN = Iop_SarN32x2; break; |
| 7849 | default: vassert(0); |
| 7850 | } |
| 7851 | |
| 7852 | assign( aa, aax ); |
| 7853 | assign( negMask, binop(opSarN, mkexpr(aa), mkU8(8*laneszB-1)) ); |
| 7854 | assign( posMask, unop(Iop_Not64, mkexpr(negMask)) ); |
| 7855 | assign( zero, mkU64(0) ); |
| 7856 | assign( aaNeg, binop(opSub, mkexpr(zero), mkexpr(aa)) ); |
| 7857 | return |
| 7858 | binop(Iop_Or64, |
| 7859 | binop(Iop_And64, mkexpr(aa), mkexpr(posMask)), |
| 7860 | binop(Iop_And64, mkexpr(aaNeg), mkexpr(negMask)) ); |
| 7861 | } |
| 7862 | |
| 7863 | static IRExpr* dis_PALIGNR_XMM_helper ( IRTemp hi64, |
| 7864 | IRTemp lo64, Int byteShift ) |
| 7865 | { |
| 7866 | vassert(byteShift >= 1 && byteShift <= 7); |
| 7867 | return |
| 7868 | binop(Iop_Or64, |
| 7869 | binop(Iop_Shl64, mkexpr(hi64), mkU8(8*(8-byteShift))), |
| 7870 | binop(Iop_Shr64, mkexpr(lo64), mkU8(8*byteShift)) |
| 7871 | ); |
| 7872 | } |
| 7873 | |
| 7874 | /* Generate a SIGSEGV followed by a restart of the current instruction |
| 7875 | if effective_addr is not 16-aligned. This is required behaviour |
| 7876 | for some SSE3 instructions and all 128-bit SSSE3 instructions. |
| 7877 | This assumes that guest_RIP_curr_instr is set correctly! */ |
| 7878 | static void gen_SEGV_if_not_16_aligned ( IRTemp effective_addr ) |
| 7879 | { |
| 7880 | stmt( |
| 7881 | IRStmt_Exit( |
| 7882 | binop(Iop_CmpNE32, |
| 7883 | binop(Iop_And32,mkexpr(effective_addr),mkU32(0xF)), |
| 7884 | mkU32(0)), |
| 7885 | Ijk_SigSEGV, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 7886 | IRConst_U32(guest_EIP_curr_instr), |
| 7887 | OFFB_EIP |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 7888 | ) |
| 7889 | ); |
| 7890 | } |
| 7891 | |
| 7892 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7893 | /* Helper for deciding whether a given insn (starting at the opcode |
| 7894 | byte) may validly be used with a LOCK prefix. The following insns |
| 7895 | may be used with LOCK when their destination operand is in memory. |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7896 | AFAICS this is exactly the same for both 32-bit and 64-bit mode. |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7897 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7898 | ADD 80 /0, 81 /0, 82 /0, 83 /0, 00, 01 |
| 7899 | OR 80 /1, 81 /1, 82 /x, 83 /1, 08, 09 |
| 7900 | ADC 80 /2, 81 /2, 82 /2, 83 /2, 10, 11 |
| 7901 | SBB 81 /3, 81 /3, 82 /x, 83 /3, 18, 19 |
| 7902 | AND 80 /4, 81 /4, 82 /x, 83 /4, 20, 21 |
| 7903 | SUB 80 /5, 81 /5, 82 /x, 83 /5, 28, 29 |
| 7904 | XOR 80 /6, 81 /6, 82 /x, 83 /6, 30, 31 |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7905 | |
| 7906 | DEC FE /1, FF /1 |
| 7907 | INC FE /0, FF /0 |
| 7908 | |
| 7909 | NEG F6 /3, F7 /3 |
| 7910 | NOT F6 /2, F7 /2 |
| 7911 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7912 | XCHG 86, 87 |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7913 | |
| 7914 | BTC 0F BB, 0F BA /7 |
| 7915 | BTR 0F B3, 0F BA /6 |
| 7916 | BTS 0F AB, 0F BA /5 |
| 7917 | |
| 7918 | CMPXCHG 0F B0, 0F B1 |
| 7919 | CMPXCHG8B 0F C7 /1 |
| 7920 | |
| 7921 | XADD 0F C0, 0F C1 |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7922 | |
| 7923 | ------------------------------ |
| 7924 | |
| 7925 | 80 /0 = addb $imm8, rm8 |
| 7926 | 81 /0 = addl $imm32, rm32 and addw $imm16, rm16 |
| 7927 | 82 /0 = addb $imm8, rm8 |
| 7928 | 83 /0 = addl $simm8, rm32 and addw $simm8, rm16 |
| 7929 | |
| 7930 | 00 = addb r8, rm8 |
| 7931 | 01 = addl r32, rm32 and addw r16, rm16 |
| 7932 | |
| 7933 | Same for ADD OR ADC SBB AND SUB XOR |
| 7934 | |
| 7935 | FE /1 = dec rm8 |
| 7936 | FF /1 = dec rm32 and dec rm16 |
| 7937 | |
| 7938 | FE /0 = inc rm8 |
| 7939 | FF /0 = inc rm32 and inc rm16 |
| 7940 | |
| 7941 | F6 /3 = neg rm8 |
| 7942 | F7 /3 = neg rm32 and neg rm16 |
| 7943 | |
| 7944 | F6 /2 = not rm8 |
| 7945 | F7 /2 = not rm32 and not rm16 |
| 7946 | |
| 7947 | 0F BB = btcw r16, rm16 and btcl r32, rm32 |
| 7948 | OF BA /7 = btcw $imm8, rm16 and btcw $imm8, rm32 |
| 7949 | |
| 7950 | Same for BTS, BTR |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7951 | */ |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 7952 | static Bool can_be_used_with_LOCK_prefix ( const UChar* opc ) |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7953 | { |
| 7954 | switch (opc[0]) { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7955 | case 0x00: case 0x01: case 0x08: case 0x09: |
| 7956 | case 0x10: case 0x11: case 0x18: case 0x19: |
| 7957 | case 0x20: case 0x21: case 0x28: case 0x29: |
| 7958 | case 0x30: case 0x31: |
| 7959 | if (!epartIsReg(opc[1])) |
| 7960 | return True; |
| 7961 | break; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7962 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7963 | case 0x80: case 0x81: case 0x82: case 0x83: |
| 7964 | if (gregOfRM(opc[1]) >= 0 && gregOfRM(opc[1]) <= 6 |
| 7965 | && !epartIsReg(opc[1])) |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7966 | return True; |
| 7967 | break; |
| 7968 | |
| 7969 | case 0xFE: case 0xFF: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7970 | if (gregOfRM(opc[1]) >= 0 && gregOfRM(opc[1]) <= 1 |
| 7971 | && !epartIsReg(opc[1])) |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7972 | return True; |
| 7973 | break; |
| 7974 | |
| 7975 | case 0xF6: case 0xF7: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7976 | if (gregOfRM(opc[1]) >= 2 && gregOfRM(opc[1]) <= 3 |
| 7977 | && !epartIsReg(opc[1])) |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7978 | return True; |
| 7979 | break; |
| 7980 | |
| 7981 | case 0x86: case 0x87: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7982 | if (!epartIsReg(opc[1])) |
| 7983 | return True; |
| 7984 | break; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7985 | |
| 7986 | case 0x0F: { |
| 7987 | switch (opc[1]) { |
| 7988 | case 0xBB: case 0xB3: case 0xAB: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7989 | if (!epartIsReg(opc[2])) |
| 7990 | return True; |
| 7991 | break; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7992 | case 0xBA: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7993 | if (gregOfRM(opc[2]) >= 5 && gregOfRM(opc[2]) <= 7 |
| 7994 | && !epartIsReg(opc[2])) |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 7995 | return True; |
| 7996 | break; |
| 7997 | case 0xB0: case 0xB1: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 7998 | if (!epartIsReg(opc[2])) |
| 7999 | return True; |
| 8000 | break; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8001 | case 0xC7: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 8002 | if (gregOfRM(opc[2]) == 1 && !epartIsReg(opc[2]) ) |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8003 | return True; |
| 8004 | break; |
| 8005 | case 0xC0: case 0xC1: |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 8006 | if (!epartIsReg(opc[2])) |
| 8007 | return True; |
| 8008 | break; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8009 | default: |
| 8010 | break; |
| 8011 | } /* switch (opc[1]) */ |
| 8012 | break; |
| 8013 | } |
| 8014 | |
| 8015 | default: |
| 8016 | break; |
| 8017 | } /* switch (opc[0]) */ |
| 8018 | |
| 8019 | return False; |
| 8020 | } |
| 8021 | |
sewardj | 021f6b4 | 2012-08-23 23:39:49 +0000 | [diff] [blame] | 8022 | static IRTemp math_BSWAP ( IRTemp t1, IRType ty ) |
| 8023 | { |
| 8024 | IRTemp t2 = newTemp(ty); |
| 8025 | if (ty == Ity_I32) { |
| 8026 | assign( t2, |
| 8027 | binop( |
| 8028 | Iop_Or32, |
| 8029 | binop(Iop_Shl32, mkexpr(t1), mkU8(24)), |
| 8030 | binop( |
| 8031 | Iop_Or32, |
| 8032 | binop(Iop_And32, binop(Iop_Shl32, mkexpr(t1), mkU8(8)), |
| 8033 | mkU32(0x00FF0000)), |
| 8034 | binop(Iop_Or32, |
| 8035 | binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(8)), |
| 8036 | mkU32(0x0000FF00)), |
| 8037 | binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(24)), |
| 8038 | mkU32(0x000000FF) ) |
| 8039 | ))) |
| 8040 | ); |
| 8041 | return t2; |
| 8042 | } |
| 8043 | if (ty == Ity_I16) { |
| 8044 | assign(t2, |
| 8045 | binop(Iop_Or16, |
| 8046 | binop(Iop_Shl16, mkexpr(t1), mkU8(8)), |
| 8047 | binop(Iop_Shr16, mkexpr(t1), mkU8(8)) )); |
| 8048 | return t2; |
| 8049 | } |
| 8050 | vassert(0); |
| 8051 | /*NOTREACHED*/ |
| 8052 | return IRTemp_INVALID; |
| 8053 | } |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8054 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8055 | /*------------------------------------------------------------*/ |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 8056 | /*--- Disassemble a single instruction ---*/ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8057 | /*------------------------------------------------------------*/ |
| 8058 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 8059 | /* Disassemble a single instruction into IR. The instruction is |
| 8060 | located in host memory at &guest_code[delta]. *expect_CAS is set |
| 8061 | to True if the resulting IR is expected to contain an IRCAS |
| 8062 | statement, and False if it's not expected to. This makes it |
| 8063 | possible for the caller of disInstr_X86_WRK to check that |
| 8064 | LOCK-prefixed instructions are at least plausibly translated, in |
| 8065 | that it becomes possible to check that a (validly) LOCK-prefixed |
| 8066 | instruction generates a translation containing an IRCAS, and |
| 8067 | instructions without LOCK prefixes don't generate translations |
| 8068 | containing an IRCAS. |
| 8069 | */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8070 | static |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 8071 | DisResult disInstr_X86_WRK ( |
| 8072 | /*OUT*/Bool* expect_CAS, |
florian | beac530 | 2014-12-31 12:09:38 +0000 | [diff] [blame] | 8073 | Bool (*resteerOkFn) ( /*opaque*/void*, Addr ), |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 8074 | Bool resteerCisOk, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 8075 | void* callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8076 | Long delta64, |
florian | cacba8e | 2014-12-15 18:58:07 +0000 | [diff] [blame] | 8077 | const VexArchInfo* archinfo, |
| 8078 | const VexAbiInfo* vbi, |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 8079 | Bool sigill_diag |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8080 | ) |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8081 | { |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 8082 | IRType ty; |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8083 | IRTemp addr, t0, t1, t2, t3, t4, t5, t6; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 8084 | Int alen; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8085 | UChar opc, modrm, abyte, pre; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 8086 | UInt d32; |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8087 | HChar dis_buf[50]; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8088 | Int am_sz, d_sz, n_prefixes; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8089 | DisResult dres; |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 8090 | const UChar* insn; /* used in SSE decoders */ |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 8091 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8092 | /* The running delta */ |
| 8093 | Int delta = (Int)delta64; |
| 8094 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8095 | /* Holds eip at the start of the insn, so that we can print |
| 8096 | consistent error messages for unimplemented insns. */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8097 | Int delta_start = delta; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8098 | |
| 8099 | /* sz denotes the nominal data-op size of the insn; we change it to |
| 8100 | 2 if an 0x66 prefix is seen */ |
| 8101 | Int sz = 4; |
| 8102 | |
| 8103 | /* sorb holds the segment-override-prefix byte, if any. Zero if no |
| 8104 | prefix has been seen, else one of {0x26, 0x3E, 0x64, 0x65} |
| 8105 | indicating the prefix. */ |
| 8106 | UChar sorb = 0; |
| 8107 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8108 | /* Gets set to True if a LOCK prefix is seen. */ |
| 8109 | Bool pfx_lock = False; |
| 8110 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8111 | /* Set result defaults. */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 8112 | dres.whatNext = Dis_Continue; |
| 8113 | dres.len = 0; |
| 8114 | dres.continueAt = 0; |
| 8115 | dres.jk_StopHere = Ijk_INVALID; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 8116 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 8117 | *expect_CAS = False; |
| 8118 | |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8119 | addr = t0 = t1 = t2 = t3 = t4 = t5 = t6 = IRTemp_INVALID; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8120 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 8121 | vassert(guest_EIP_bbstart + delta == guest_EIP_curr_instr); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8122 | DIP("\t0x%x: ", guest_EIP_bbstart+delta); |
| 8123 | |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 8124 | /* Spot "Special" instructions (see comment at top of file). */ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 8125 | { |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 8126 | const UChar* code = guest_code + delta; |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 8127 | /* Spot the 12-byte preamble: |
| 8128 | C1C703 roll $3, %edi |
| 8129 | C1C70D roll $13, %edi |
| 8130 | C1C71D roll $29, %edi |
| 8131 | C1C713 roll $19, %edi |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 8132 | */ |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 8133 | if (code[ 0] == 0xC1 && code[ 1] == 0xC7 && code[ 2] == 0x03 && |
| 8134 | code[ 3] == 0xC1 && code[ 4] == 0xC7 && code[ 5] == 0x0D && |
| 8135 | code[ 6] == 0xC1 && code[ 7] == 0xC7 && code[ 8] == 0x1D && |
| 8136 | code[ 9] == 0xC1 && code[10] == 0xC7 && code[11] == 0x13) { |
| 8137 | /* Got a "Special" instruction preamble. Which one is it? */ |
| 8138 | if (code[12] == 0x87 && code[13] == 0xDB /* xchgl %ebx,%ebx */) { |
| 8139 | /* %EDX = client_request ( %EAX ) */ |
| 8140 | DIP("%%edx = client_request ( %%eax )\n"); |
| 8141 | delta += 14; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 8142 | jmp_lit(&dres, Ijk_ClientReq, guest_EIP_bbstart+delta); |
| 8143 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 8144 | goto decode_success; |
| 8145 | } |
| 8146 | else |
| 8147 | if (code[12] == 0x87 && code[13] == 0xC9 /* xchgl %ecx,%ecx */) { |
| 8148 | /* %EAX = guest_NRADDR */ |
| 8149 | DIP("%%eax = guest_NRADDR\n"); |
| 8150 | delta += 14; |
| 8151 | putIReg(4, R_EAX, IRExpr_Get( OFFB_NRADDR, Ity_I32 )); |
| 8152 | goto decode_success; |
| 8153 | } |
| 8154 | else |
| 8155 | if (code[12] == 0x87 && code[13] == 0xD2 /* xchgl %edx,%edx */) { |
| 8156 | /* call-noredir *%EAX */ |
| 8157 | DIP("call-noredir *%%eax\n"); |
| 8158 | delta += 14; |
| 8159 | t1 = newTemp(Ity_I32); |
| 8160 | assign(t1, getIReg(4,R_EAX)); |
| 8161 | t2 = newTemp(Ity_I32); |
| 8162 | assign(t2, binop(Iop_Sub32, getIReg(4,R_ESP), mkU32(4))); |
| 8163 | putIReg(4, R_ESP, mkexpr(t2)); |
| 8164 | storeLE( mkexpr(t2), mkU32(guest_EIP_bbstart+delta)); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 8165 | jmp_treg(&dres, Ijk_NoRedir, t1); |
| 8166 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 8167 | goto decode_success; |
| 8168 | } |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 8169 | else |
| 8170 | if (code[12] == 0x87 && code[13] == 0xFF /* xchgl %edi,%edi */) { |
| 8171 | /* IR injection */ |
| 8172 | DIP("IR injection\n"); |
| 8173 | vex_inject_ir(irsb, Iend_LE); |
| 8174 | |
| 8175 | // Invalidate the current insn. The reason is that the IRop we're |
| 8176 | // injecting here can change. In which case the translation has to |
| 8177 | // be redone. For ease of handling, we simply invalidate all the |
| 8178 | // time. |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 8179 | stmt(IRStmt_Put(OFFB_CMSTART, mkU32(guest_EIP_curr_instr))); |
| 8180 | stmt(IRStmt_Put(OFFB_CMLEN, mkU32(14))); |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 8181 | |
| 8182 | delta += 14; |
| 8183 | |
| 8184 | stmt( IRStmt_Put( OFFB_EIP, mkU32(guest_EIP_bbstart + delta) ) ); |
| 8185 | dres.whatNext = Dis_StopHere; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 8186 | dres.jk_StopHere = Ijk_InvalICache; |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 8187 | goto decode_success; |
| 8188 | } |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 8189 | /* We don't know what it is. */ |
| 8190 | goto decode_failure; |
| 8191 | /*NOTREACHED*/ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 8192 | } |
| 8193 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8194 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8195 | /* Handle a couple of weird-ass NOPs that have been observed in the |
| 8196 | wild. */ |
| 8197 | { |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 8198 | const UChar* code = guest_code + delta; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8199 | /* Sun's JVM 1.5.0 uses the following as a NOP: |
| 8200 | 26 2E 64 65 90 %es:%cs:%fs:%gs:nop */ |
| 8201 | if (code[0] == 0x26 && code[1] == 0x2E && code[2] == 0x64 |
| 8202 | && code[3] == 0x65 && code[4] == 0x90) { |
| 8203 | DIP("%%es:%%cs:%%fs:%%gs:nop\n"); |
| 8204 | delta += 5; |
| 8205 | goto decode_success; |
sewardj | bb3f52d | 2005-01-07 14:14:50 +0000 | [diff] [blame] | 8206 | } |
sewardj | deceef8 | 2010-05-03 21:58:22 +0000 | [diff] [blame] | 8207 | /* Don't barf on recent binutils padding, |
| 8208 | all variants of which are: nopw %cs:0x0(%eax,%eax,1) |
| 8209 | 66 2e 0f 1f 84 00 00 00 00 00 |
| 8210 | 66 66 2e 0f 1f 84 00 00 00 00 00 |
| 8211 | 66 66 66 2e 0f 1f 84 00 00 00 00 00 |
| 8212 | 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 |
| 8213 | 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 |
| 8214 | 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 |
| 8215 | */ |
| 8216 | if (code[0] == 0x66) { |
| 8217 | Int data16_cnt; |
| 8218 | for (data16_cnt = 1; data16_cnt < 6; data16_cnt++) |
| 8219 | if (code[data16_cnt] != 0x66) |
| 8220 | break; |
| 8221 | if (code[data16_cnt] == 0x2E && code[data16_cnt + 1] == 0x0F |
| 8222 | && code[data16_cnt + 2] == 0x1F && code[data16_cnt + 3] == 0x84 |
| 8223 | && code[data16_cnt + 4] == 0x00 && code[data16_cnt + 5] == 0x00 |
| 8224 | && code[data16_cnt + 6] == 0x00 && code[data16_cnt + 7] == 0x00 |
| 8225 | && code[data16_cnt + 8] == 0x00 ) { |
| 8226 | DIP("nopw %%cs:0x0(%%eax,%%eax,1)\n"); |
| 8227 | delta += 9 + data16_cnt; |
| 8228 | goto decode_success; |
| 8229 | } |
sewardj | ce4a282 | 2005-01-07 13:25:28 +0000 | [diff] [blame] | 8230 | } |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8231 | } |
sewardj | bb3f52d | 2005-01-07 14:14:50 +0000 | [diff] [blame] | 8232 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8233 | /* Normal instruction handling starts here. */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8234 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8235 | /* Deal with some but not all prefixes: |
| 8236 | 66(oso) |
| 8237 | F0(lock) |
| 8238 | 2E(cs:) 3E(ds:) 26(es:) 64(fs:) 65(gs:) 36(ss:) |
| 8239 | Not dealt with (left in place): |
| 8240 | F2 F3 |
| 8241 | */ |
| 8242 | n_prefixes = 0; |
| 8243 | while (True) { |
| 8244 | if (n_prefixes > 7) goto decode_failure; |
| 8245 | pre = getUChar(delta); |
| 8246 | switch (pre) { |
| 8247 | case 0x66: |
| 8248 | sz = 2; |
| 8249 | break; |
| 8250 | case 0xF0: |
| 8251 | pfx_lock = True; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 8252 | *expect_CAS = True; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8253 | break; |
| 8254 | case 0x3E: /* %DS: */ |
| 8255 | case 0x26: /* %ES: */ |
| 8256 | case 0x64: /* %FS: */ |
| 8257 | case 0x65: /* %GS: */ |
| 8258 | if (sorb != 0) |
| 8259 | goto decode_failure; /* only one seg override allowed */ |
| 8260 | sorb = pre; |
| 8261 | break; |
| 8262 | case 0x2E: { /* %CS: */ |
| 8263 | /* 2E prefix on a conditional branch instruction is a |
| 8264 | branch-prediction hint, which can safely be ignored. */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8265 | UChar op1 = getIByte(delta+1); |
| 8266 | UChar op2 = getIByte(delta+2); |
| 8267 | if ((op1 >= 0x70 && op1 <= 0x7F) |
| 8268 | || (op1 == 0xE3) |
| 8269 | || (op1 == 0x0F && op2 >= 0x80 && op2 <= 0x8F)) { |
sewardj | 4dfb199 | 2005-03-13 18:56:28 +0000 | [diff] [blame] | 8270 | if (0) vex_printf("vex x86->IR: ignoring branch hint\n"); |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8271 | } else { |
| 8272 | /* All other CS override cases are not handled */ |
| 8273 | goto decode_failure; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8274 | } |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8275 | break; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8276 | } |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8277 | case 0x36: /* %SS: */ |
| 8278 | /* SS override cases are not handled */ |
| 8279 | goto decode_failure; |
| 8280 | default: |
| 8281 | goto not_a_prefix; |
| 8282 | } |
| 8283 | n_prefixes++; |
| 8284 | delta++; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 8285 | } |
| 8286 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8287 | not_a_prefix: |
| 8288 | |
| 8289 | /* Now we should be looking at the primary opcode byte or the |
| 8290 | leading F2 or F3. Check that any LOCK prefix is actually |
| 8291 | allowed. */ |
| 8292 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8293 | if (pfx_lock) { |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 8294 | if (can_be_used_with_LOCK_prefix( &guest_code[delta] )) { |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8295 | DIP("lock "); |
| 8296 | } else { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 8297 | *expect_CAS = False; |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 8298 | goto decode_failure; |
| 8299 | } |
| 8300 | } |
| 8301 | |
| 8302 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8303 | /* ---------------------------------------------------- */ |
| 8304 | /* --- The SSE decoder. --- */ |
| 8305 | /* ---------------------------------------------------- */ |
| 8306 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8307 | /* What did I do to deserve SSE ? Perhaps I was really bad in a |
| 8308 | previous life? */ |
| 8309 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 8310 | /* Note, this doesn't handle SSE2 or SSE3. That is handled in a |
| 8311 | later section, further on. */ |
| 8312 | |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 8313 | insn = &guest_code[delta]; |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8314 | |
| 8315 | /* Treat fxsave specially. It should be doable even on an SSE0 |
| 8316 | (Pentium-II class) CPU. Hence be prepared to handle it on |
| 8317 | any subarchitecture variant. |
| 8318 | */ |
| 8319 | |
| 8320 | /* 0F AE /0 = FXSAVE m512 -- write x87 and SSE state to memory */ |
| 8321 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xAE |
| 8322 | && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 0) { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 8323 | IRDirty* d; |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8324 | modrm = getIByte(delta+2); |
| 8325 | vassert(sz == 4); |
| 8326 | vassert(!epartIsReg(modrm)); |
| 8327 | |
| 8328 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8329 | delta += 2+alen; |
sewardj | ec993de | 2011-01-21 18:02:54 +0000 | [diff] [blame] | 8330 | gen_SEGV_if_not_16_aligned(addr); |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8331 | |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 8332 | DIP("fxsave %s\n", dis_buf); |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8333 | |
| 8334 | /* Uses dirty helper: |
| 8335 | void x86g_do_FXSAVE ( VexGuestX86State*, UInt ) */ |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 8336 | d = unsafeIRDirty_0_N ( |
| 8337 | 0/*regparms*/, |
| 8338 | "x86g_dirtyhelper_FXSAVE", |
| 8339 | &x86g_dirtyhelper_FXSAVE, |
florian | 9041956 | 2013-08-15 20:54:52 +0000 | [diff] [blame] | 8340 | mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) ) |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 8341 | ); |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8342 | |
| 8343 | /* declare we're writing memory */ |
| 8344 | d->mFx = Ifx_Write; |
| 8345 | d->mAddr = mkexpr(addr); |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 8346 | d->mSize = 464; /* according to recent Intel docs */ |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8347 | |
| 8348 | /* declare we're reading guest state */ |
| 8349 | d->nFxState = 7; |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 8350 | vex_bzero(&d->fxState, sizeof(d->fxState)); |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8351 | |
| 8352 | d->fxState[0].fx = Ifx_Read; |
| 8353 | d->fxState[0].offset = OFFB_FTOP; |
| 8354 | d->fxState[0].size = sizeof(UInt); |
| 8355 | |
| 8356 | d->fxState[1].fx = Ifx_Read; |
| 8357 | d->fxState[1].offset = OFFB_FPREGS; |
| 8358 | d->fxState[1].size = 8 * sizeof(ULong); |
| 8359 | |
| 8360 | d->fxState[2].fx = Ifx_Read; |
| 8361 | d->fxState[2].offset = OFFB_FPTAGS; |
| 8362 | d->fxState[2].size = 8 * sizeof(UChar); |
| 8363 | |
| 8364 | d->fxState[3].fx = Ifx_Read; |
| 8365 | d->fxState[3].offset = OFFB_FPROUND; |
| 8366 | d->fxState[3].size = sizeof(UInt); |
| 8367 | |
| 8368 | d->fxState[4].fx = Ifx_Read; |
| 8369 | d->fxState[4].offset = OFFB_FC3210; |
| 8370 | d->fxState[4].size = sizeof(UInt); |
| 8371 | |
| 8372 | d->fxState[5].fx = Ifx_Read; |
| 8373 | d->fxState[5].offset = OFFB_XMM0; |
| 8374 | d->fxState[5].size = 8 * sizeof(U128); |
| 8375 | |
| 8376 | d->fxState[6].fx = Ifx_Read; |
| 8377 | d->fxState[6].offset = OFFB_SSEROUND; |
| 8378 | d->fxState[6].size = sizeof(UInt); |
| 8379 | |
| 8380 | /* Be paranoid ... this assertion tries to ensure the 8 %xmm |
| 8381 | images are packed back-to-back. If not, the value of |
| 8382 | d->fxState[5].size is wrong. */ |
| 8383 | vassert(16 == sizeof(U128)); |
| 8384 | vassert(OFFB_XMM7 == (OFFB_XMM0 + 7 * 16)); |
| 8385 | |
| 8386 | stmt( IRStmt_Dirty(d) ); |
| 8387 | |
| 8388 | goto decode_success; |
| 8389 | } |
| 8390 | |
sewardj | 3800e2d | 2008-05-09 13:24:43 +0000 | [diff] [blame] | 8391 | /* 0F AE /1 = FXRSTOR m512 -- read x87 and SSE state from memory */ |
| 8392 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xAE |
| 8393 | && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 1) { |
| 8394 | IRDirty* d; |
| 8395 | modrm = getIByte(delta+2); |
| 8396 | vassert(sz == 4); |
| 8397 | vassert(!epartIsReg(modrm)); |
| 8398 | |
| 8399 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8400 | delta += 2+alen; |
sewardj | ec993de | 2011-01-21 18:02:54 +0000 | [diff] [blame] | 8401 | gen_SEGV_if_not_16_aligned(addr); |
sewardj | 3800e2d | 2008-05-09 13:24:43 +0000 | [diff] [blame] | 8402 | |
| 8403 | DIP("fxrstor %s\n", dis_buf); |
| 8404 | |
| 8405 | /* Uses dirty helper: |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 8406 | VexEmNote x86g_do_FXRSTOR ( VexGuestX86State*, UInt ) |
sewardj | ec993de | 2011-01-21 18:02:54 +0000 | [diff] [blame] | 8407 | NOTE: |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 8408 | the VexEmNote value is simply ignored (unlike for FRSTOR) |
sewardj | ec993de | 2011-01-21 18:02:54 +0000 | [diff] [blame] | 8409 | */ |
sewardj | 3800e2d | 2008-05-09 13:24:43 +0000 | [diff] [blame] | 8410 | d = unsafeIRDirty_0_N ( |
| 8411 | 0/*regparms*/, |
| 8412 | "x86g_dirtyhelper_FXRSTOR", |
| 8413 | &x86g_dirtyhelper_FXRSTOR, |
florian | 9041956 | 2013-08-15 20:54:52 +0000 | [diff] [blame] | 8414 | mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) ) |
sewardj | 3800e2d | 2008-05-09 13:24:43 +0000 | [diff] [blame] | 8415 | ); |
sewardj | 3800e2d | 2008-05-09 13:24:43 +0000 | [diff] [blame] | 8416 | |
| 8417 | /* declare we're reading memory */ |
| 8418 | d->mFx = Ifx_Read; |
| 8419 | d->mAddr = mkexpr(addr); |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 8420 | d->mSize = 464; /* according to recent Intel docs */ |
sewardj | 3800e2d | 2008-05-09 13:24:43 +0000 | [diff] [blame] | 8421 | |
| 8422 | /* declare we're writing guest state */ |
| 8423 | d->nFxState = 7; |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 8424 | vex_bzero(&d->fxState, sizeof(d->fxState)); |
sewardj | 3800e2d | 2008-05-09 13:24:43 +0000 | [diff] [blame] | 8425 | |
| 8426 | d->fxState[0].fx = Ifx_Write; |
| 8427 | d->fxState[0].offset = OFFB_FTOP; |
| 8428 | d->fxState[0].size = sizeof(UInt); |
| 8429 | |
| 8430 | d->fxState[1].fx = Ifx_Write; |
| 8431 | d->fxState[1].offset = OFFB_FPREGS; |
| 8432 | d->fxState[1].size = 8 * sizeof(ULong); |
| 8433 | |
| 8434 | d->fxState[2].fx = Ifx_Write; |
| 8435 | d->fxState[2].offset = OFFB_FPTAGS; |
| 8436 | d->fxState[2].size = 8 * sizeof(UChar); |
| 8437 | |
| 8438 | d->fxState[3].fx = Ifx_Write; |
| 8439 | d->fxState[3].offset = OFFB_FPROUND; |
| 8440 | d->fxState[3].size = sizeof(UInt); |
| 8441 | |
| 8442 | d->fxState[4].fx = Ifx_Write; |
| 8443 | d->fxState[4].offset = OFFB_FC3210; |
| 8444 | d->fxState[4].size = sizeof(UInt); |
| 8445 | |
| 8446 | d->fxState[5].fx = Ifx_Write; |
| 8447 | d->fxState[5].offset = OFFB_XMM0; |
| 8448 | d->fxState[5].size = 8 * sizeof(U128); |
| 8449 | |
| 8450 | d->fxState[6].fx = Ifx_Write; |
| 8451 | d->fxState[6].offset = OFFB_SSEROUND; |
| 8452 | d->fxState[6].size = sizeof(UInt); |
| 8453 | |
| 8454 | /* Be paranoid ... this assertion tries to ensure the 8 %xmm |
| 8455 | images are packed back-to-back. If not, the value of |
| 8456 | d->fxState[5].size is wrong. */ |
| 8457 | vassert(16 == sizeof(U128)); |
| 8458 | vassert(OFFB_XMM7 == (OFFB_XMM0 + 7 * 16)); |
| 8459 | |
| 8460 | stmt( IRStmt_Dirty(d) ); |
| 8461 | |
| 8462 | goto decode_success; |
| 8463 | } |
| 8464 | |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 8465 | /* ------ SSE decoder main ------ */ |
| 8466 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 8467 | /* Skip parts of the decoder which don't apply given the stated |
| 8468 | guest subarchitecture. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8469 | if (archinfo->hwcaps == 0/*baseline, no sse at all*/) |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 8470 | goto after_sse_decoders; |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 8471 | |
| 8472 | /* With mmxext only some extended MMX instructions are recognized. |
| 8473 | The mmxext instructions are MASKMOVQ MOVNTQ PAVGB PAVGW PMAXSW |
| 8474 | PMAXUB PMINSW PMINUB PMULHUW PSADBW PSHUFW PEXTRW PINSRW PMOVMSKB |
| 8475 | PREFETCHNTA PREFETCHT0 PREFETCHT1 PREFETCHT2 SFENCE |
| 8476 | |
| 8477 | http://support.amd.com/us/Embedded_TechDocs/22466.pdf |
| 8478 | https://en.wikipedia.org/wiki/3DNow!#3DNow.21_extensions */ |
| 8479 | |
| 8480 | if (archinfo->hwcaps == VEX_HWCAPS_X86_MMXEXT/*integer only sse1 subset*/) |
| 8481 | goto mmxext; |
| 8482 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 8483 | /* Otherwise we must be doing sse1 or sse2, so we can at least try |
| 8484 | for SSE1 here. */ |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8485 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8486 | /* 0F 58 = ADDPS -- add 32Fx4 from R/M to R */ |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 8487 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x58) { |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8488 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "addps", Iop_Add32Fx4 ); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8489 | goto decode_success; |
| 8490 | } |
| 8491 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 8492 | /* F3 0F 58 = ADDSS -- add 32F0x4 from R/M to R */ |
| 8493 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x58) { |
| 8494 | vassert(sz == 4); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8495 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "addss", Iop_Add32F0x4 ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 8496 | goto decode_success; |
| 8497 | } |
| 8498 | |
| 8499 | /* 0F 55 = ANDNPS -- G = (not G) and E */ |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 8500 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x55) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 8501 | delta = dis_SSE_E_to_G_all_invG( sorb, delta+2, "andnps", Iop_AndV128 ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 8502 | goto decode_success; |
| 8503 | } |
| 8504 | |
| 8505 | /* 0F 54 = ANDPS -- G = G and E */ |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 8506 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x54) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 8507 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "andps", Iop_AndV128 ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 8508 | goto decode_success; |
| 8509 | } |
| 8510 | |
| 8511 | /* 0F C2 = CMPPS -- 32Fx4 comparison from R/M to R */ |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 8512 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xC2) { |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 8513 | delta = dis_SSEcmp_E_to_G( sorb, delta+2, "cmpps", True, 4 ); |
| 8514 | goto decode_success; |
| 8515 | } |
| 8516 | |
| 8517 | /* F3 0F C2 = CMPSS -- 32F0x4 comparison from R/M to R */ |
| 8518 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xC2) { |
| 8519 | vassert(sz == 4); |
| 8520 | delta = dis_SSEcmp_E_to_G( sorb, delta+3, "cmpss", False, 4 ); |
| 8521 | goto decode_success; |
| 8522 | } |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8523 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 8524 | /* 0F 2F = COMISS -- 32F0x4 comparison G,E, and set ZCP */ |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 8525 | /* 0F 2E = UCOMISS -- 32F0x4 comparison G,E, and set ZCP */ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 8526 | if (sz == 4 && insn[0] == 0x0F && (insn[1] == 0x2F || insn[1] == 0x2E)) { |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 8527 | IRTemp argL = newTemp(Ity_F32); |
| 8528 | IRTemp argR = newTemp(Ity_F32); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 8529 | modrm = getIByte(delta+2); |
| 8530 | if (epartIsReg(modrm)) { |
| 8531 | assign( argR, getXMMRegLane32F( eregOfRM(modrm), 0/*lowest lane*/ ) ); |
| 8532 | delta += 2+1; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 8533 | DIP("[u]comiss %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 8534 | nameXMMReg(gregOfRM(modrm)) ); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 8535 | } else { |
| 8536 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8537 | assign( argR, loadLE(Ity_F32, mkexpr(addr)) ); |
| 8538 | delta += 2+alen; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 8539 | DIP("[u]comiss %s,%s\n", dis_buf, |
| 8540 | nameXMMReg(gregOfRM(modrm)) ); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 8541 | } |
| 8542 | assign( argL, getXMMRegLane32F( gregOfRM(modrm), 0/*lowest lane*/ ) ); |
| 8543 | |
| 8544 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 8545 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 8546 | stmt( IRStmt_Put( |
| 8547 | OFFB_CC_DEP1, |
| 8548 | binop( Iop_And32, |
| 8549 | binop(Iop_CmpF64, |
| 8550 | unop(Iop_F32toF64,mkexpr(argL)), |
| 8551 | unop(Iop_F32toF64,mkexpr(argR))), |
| 8552 | mkU32(0x45) |
| 8553 | ))); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 8554 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 8555 | elimination of previous stores to this field work better. */ |
| 8556 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | 67e002d | 2004-12-02 18:16:33 +0000 | [diff] [blame] | 8557 | goto decode_success; |
| 8558 | } |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 8559 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8560 | /* 0F 2A = CVTPI2PS -- convert 2 x I32 in mem/mmx to 2 x F32 in low |
| 8561 | half xmm */ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 8562 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x2A) { |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8563 | IRTemp arg64 = newTemp(Ity_I64); |
| 8564 | IRTemp rmode = newTemp(Ity_I32); |
| 8565 | vassert(sz == 4); |
| 8566 | |
| 8567 | modrm = getIByte(delta+2); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8568 | if (epartIsReg(modrm)) { |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 8569 | /* Only switch to MMX mode if the source is a MMX register. |
| 8570 | See comments on CVTPI2PD for details. Fixes #357059. */ |
| 8571 | do_MMX_preamble(); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8572 | assign( arg64, getMMXReg(eregOfRM(modrm)) ); |
| 8573 | delta += 2+1; |
| 8574 | DIP("cvtpi2ps %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 8575 | nameXMMReg(gregOfRM(modrm))); |
| 8576 | } else { |
| 8577 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8578 | assign( arg64, loadLE(Ity_I64, mkexpr(addr)) ); |
| 8579 | delta += 2+alen; |
| 8580 | DIP("cvtpi2ps %s,%s\n", dis_buf, |
| 8581 | nameXMMReg(gregOfRM(modrm)) ); |
| 8582 | } |
| 8583 | |
| 8584 | assign( rmode, get_sse_roundingmode() ); |
| 8585 | |
| 8586 | putXMMRegLane32F( |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8587 | gregOfRM(modrm), 0, |
| 8588 | binop(Iop_F64toF32, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8589 | mkexpr(rmode), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8590 | unop(Iop_I32StoF64, |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8591 | unop(Iop_64to32, mkexpr(arg64)) )) ); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8592 | |
| 8593 | putXMMRegLane32F( |
| 8594 | gregOfRM(modrm), 1, |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8595 | binop(Iop_F64toF32, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8596 | mkexpr(rmode), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8597 | unop(Iop_I32StoF64, |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8598 | unop(Iop_64HIto32, mkexpr(arg64)) )) ); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8599 | |
| 8600 | goto decode_success; |
| 8601 | } |
| 8602 | |
| 8603 | /* F3 0F 2A = CVTSI2SS -- convert I32 in mem/ireg to F32 in low |
| 8604 | quarter xmm */ |
| 8605 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x2A) { |
| 8606 | IRTemp arg32 = newTemp(Ity_I32); |
| 8607 | IRTemp rmode = newTemp(Ity_I32); |
| 8608 | vassert(sz == 4); |
| 8609 | |
| 8610 | modrm = getIByte(delta+3); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8611 | if (epartIsReg(modrm)) { |
| 8612 | assign( arg32, getIReg(4, eregOfRM(modrm)) ); |
| 8613 | delta += 3+1; |
| 8614 | DIP("cvtsi2ss %s,%s\n", nameIReg(4, eregOfRM(modrm)), |
| 8615 | nameXMMReg(gregOfRM(modrm))); |
| 8616 | } else { |
| 8617 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 8618 | assign( arg32, loadLE(Ity_I32, mkexpr(addr)) ); |
| 8619 | delta += 3+alen; |
| 8620 | DIP("cvtsi2ss %s,%s\n", dis_buf, |
| 8621 | nameXMMReg(gregOfRM(modrm)) ); |
| 8622 | } |
| 8623 | |
| 8624 | assign( rmode, get_sse_roundingmode() ); |
| 8625 | |
| 8626 | putXMMRegLane32F( |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8627 | gregOfRM(modrm), 0, |
| 8628 | binop(Iop_F64toF32, |
| 8629 | mkexpr(rmode), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8630 | unop(Iop_I32StoF64, mkexpr(arg32)) ) ); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8631 | |
| 8632 | goto decode_success; |
| 8633 | } |
| 8634 | |
| 8635 | /* 0F 2D = CVTPS2PI -- convert 2 x F32 in mem/low half xmm to 2 x |
| 8636 | I32 in mmx, according to prevailing SSE rounding mode */ |
| 8637 | /* 0F 2C = CVTTPS2PI -- convert 2 x F32 in mem/low half xmm to 2 x |
| 8638 | I32 in mmx, rounding towards zero */ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 8639 | if (sz == 4 && insn[0] == 0x0F && (insn[1] == 0x2D || insn[1] == 0x2C)) { |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8640 | IRTemp dst64 = newTemp(Ity_I64); |
| 8641 | IRTemp rmode = newTemp(Ity_I32); |
| 8642 | IRTemp f32lo = newTemp(Ity_F32); |
| 8643 | IRTemp f32hi = newTemp(Ity_F32); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 8644 | Bool r2zero = toBool(insn[1] == 0x2C); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8645 | |
| 8646 | do_MMX_preamble(); |
| 8647 | modrm = getIByte(delta+2); |
| 8648 | |
| 8649 | if (epartIsReg(modrm)) { |
| 8650 | delta += 2+1; |
| 8651 | assign(f32lo, getXMMRegLane32F(eregOfRM(modrm), 0)); |
| 8652 | assign(f32hi, getXMMRegLane32F(eregOfRM(modrm), 1)); |
| 8653 | DIP("cvt%sps2pi %s,%s\n", r2zero ? "t" : "", |
| 8654 | nameXMMReg(eregOfRM(modrm)), |
| 8655 | nameMMXReg(gregOfRM(modrm))); |
| 8656 | } else { |
| 8657 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8658 | assign(f32lo, loadLE(Ity_F32, mkexpr(addr))); |
| 8659 | assign(f32hi, loadLE(Ity_F32, binop( Iop_Add32, |
| 8660 | mkexpr(addr), |
| 8661 | mkU32(4) ))); |
| 8662 | delta += 2+alen; |
| 8663 | DIP("cvt%sps2pi %s,%s\n", r2zero ? "t" : "", |
| 8664 | dis_buf, |
| 8665 | nameMMXReg(gregOfRM(modrm))); |
| 8666 | } |
| 8667 | |
| 8668 | if (r2zero) { |
| 8669 | assign(rmode, mkU32((UInt)Irrm_ZERO) ); |
| 8670 | } else { |
| 8671 | assign( rmode, get_sse_roundingmode() ); |
| 8672 | } |
| 8673 | |
| 8674 | assign( |
| 8675 | dst64, |
| 8676 | binop( Iop_32HLto64, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8677 | binop( Iop_F64toI32S, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8678 | mkexpr(rmode), |
| 8679 | unop( Iop_F32toF64, mkexpr(f32hi) ) ), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8680 | binop( Iop_F64toI32S, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8681 | mkexpr(rmode), |
| 8682 | unop( Iop_F32toF64, mkexpr(f32lo) ) ) |
| 8683 | ) |
| 8684 | ); |
| 8685 | |
| 8686 | putMMXReg(gregOfRM(modrm), mkexpr(dst64)); |
| 8687 | goto decode_success; |
| 8688 | } |
| 8689 | |
| 8690 | /* F3 0F 2D = CVTSS2SI -- convert F32 in mem/low quarter xmm to |
| 8691 | I32 in ireg, according to prevailing SSE rounding mode */ |
| 8692 | /* F3 0F 2C = CVTTSS2SI -- convert F32 in mem/low quarter xmm to |
sewardj | 0b21044 | 2005-02-23 13:28:27 +0000 | [diff] [blame] | 8693 | I32 in ireg, rounding towards zero */ |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8694 | if (insn[0] == 0xF3 && insn[1] == 0x0F |
| 8695 | && (insn[2] == 0x2D || insn[2] == 0x2C)) { |
| 8696 | IRTemp rmode = newTemp(Ity_I32); |
| 8697 | IRTemp f32lo = newTemp(Ity_F32); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 8698 | Bool r2zero = toBool(insn[2] == 0x2C); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8699 | vassert(sz == 4); |
| 8700 | |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8701 | modrm = getIByte(delta+3); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8702 | if (epartIsReg(modrm)) { |
| 8703 | delta += 3+1; |
| 8704 | assign(f32lo, getXMMRegLane32F(eregOfRM(modrm), 0)); |
| 8705 | DIP("cvt%sss2si %s,%s\n", r2zero ? "t" : "", |
| 8706 | nameXMMReg(eregOfRM(modrm)), |
| 8707 | nameIReg(4, gregOfRM(modrm))); |
| 8708 | } else { |
| 8709 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 8710 | assign(f32lo, loadLE(Ity_F32, mkexpr(addr))); |
| 8711 | delta += 3+alen; |
| 8712 | DIP("cvt%sss2si %s,%s\n", r2zero ? "t" : "", |
| 8713 | dis_buf, |
| 8714 | nameIReg(4, gregOfRM(modrm))); |
| 8715 | } |
| 8716 | |
| 8717 | if (r2zero) { |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8718 | assign( rmode, mkU32((UInt)Irrm_ZERO) ); |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8719 | } else { |
| 8720 | assign( rmode, get_sse_roundingmode() ); |
| 8721 | } |
| 8722 | |
| 8723 | putIReg(4, gregOfRM(modrm), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 8724 | binop( Iop_F64toI32S, |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 8725 | mkexpr(rmode), |
| 8726 | unop( Iop_F32toF64, mkexpr(f32lo) ) ) |
| 8727 | ); |
| 8728 | |
| 8729 | goto decode_success; |
| 8730 | } |
| 8731 | |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 8732 | /* 0F 5E = DIVPS -- div 32Fx4 from R/M to R */ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 8733 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5E) { |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8734 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "divps", Iop_Div32Fx4 ); |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 8735 | goto decode_success; |
| 8736 | } |
| 8737 | |
| 8738 | /* F3 0F 5E = DIVSS -- div 32F0x4 from R/M to R */ |
| 8739 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5E) { |
| 8740 | vassert(sz == 4); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 8741 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "divss", Iop_Div32F0x4 ); |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 8742 | goto decode_success; |
| 8743 | } |
| 8744 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8745 | /* 0F AE /2 = LDMXCSR m32 -- load %mxcsr */ |
| 8746 | if (insn[0] == 0x0F && insn[1] == 0xAE |
| 8747 | && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 2) { |
| 8748 | |
| 8749 | IRTemp t64 = newTemp(Ity_I64); |
| 8750 | IRTemp ew = newTemp(Ity_I32); |
| 8751 | |
| 8752 | modrm = getIByte(delta+2); |
| 8753 | vassert(!epartIsReg(modrm)); |
| 8754 | vassert(sz == 4); |
| 8755 | |
| 8756 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8757 | delta += 2+alen; |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 8758 | DIP("ldmxcsr %s\n", dis_buf); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8759 | |
| 8760 | /* The only thing we observe in %mxcsr is the rounding mode. |
| 8761 | Therefore, pass the 32-bit value (SSE native-format control |
| 8762 | word) to a clean helper, getting back a 64-bit value, the |
| 8763 | lower half of which is the SSEROUND value to store, and the |
| 8764 | upper half of which is the emulation-warning token which may |
| 8765 | be generated. |
| 8766 | */ |
| 8767 | /* ULong x86h_check_ldmxcsr ( UInt ); */ |
| 8768 | assign( t64, mkIRExprCCall( |
| 8769 | Ity_I64, 0/*regparms*/, |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 8770 | "x86g_check_ldmxcsr", |
| 8771 | &x86g_check_ldmxcsr, |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8772 | mkIRExprVec_1( loadLE(Ity_I32, mkexpr(addr)) ) |
| 8773 | ) |
| 8774 | ); |
| 8775 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 8776 | put_sse_roundingmode( unop(Iop_64to32, mkexpr(t64)) ); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8777 | assign( ew, unop(Iop_64HIto32, mkexpr(t64) ) ); |
| 8778 | put_emwarn( mkexpr(ew) ); |
| 8779 | /* Finally, if an emulation warning was reported, side-exit to |
| 8780 | the next insn, reporting the warning, so that Valgrind's |
| 8781 | dispatcher sees the warning. */ |
| 8782 | stmt( |
| 8783 | IRStmt_Exit( |
| 8784 | binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)), |
| 8785 | Ijk_EmWarn, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 8786 | IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta), |
| 8787 | OFFB_EIP |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8788 | ) |
| 8789 | ); |
| 8790 | goto decode_success; |
| 8791 | } |
| 8792 | |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 8793 | |
| 8794 | /* mmxext sse1 subset starts here. mmxext only arches will parse |
| 8795 | only this subset of the sse1 instructions. */ |
| 8796 | mmxext: |
| 8797 | |
sewardj | d71ba83 | 2006-12-27 01:15:29 +0000 | [diff] [blame] | 8798 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8799 | /* 0F F7 = MASKMOVQ -- 8x8 masked store */ |
| 8800 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xF7) { |
| 8801 | Bool ok = False; |
| 8802 | delta = dis_MMX( &ok, sorb, sz, delta+1 ); |
| 8803 | if (!ok) |
| 8804 | goto decode_failure; |
| 8805 | goto decode_success; |
| 8806 | } |
| 8807 | |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8808 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8809 | /* 0F E7 = MOVNTQ -- for us, just a plain MMX store. Note, the |
| 8810 | Intel manual does not say anything about the usual business of |
| 8811 | the FP reg tags getting trashed whenever an MMX insn happens. |
| 8812 | So we just leave them alone. |
| 8813 | */ |
| 8814 | if (insn[0] == 0x0F && insn[1] == 0xE7) { |
| 8815 | modrm = getIByte(delta+2); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 8816 | if (sz == 4 && !epartIsReg(modrm)) { |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 8817 | /* do_MMX_preamble(); Intel docs don't specify this */ |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 8818 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8819 | storeLE( mkexpr(addr), getMMXReg(gregOfRM(modrm)) ); |
| 8820 | DIP("movntq %s,%s\n", dis_buf, |
| 8821 | nameMMXReg(gregOfRM(modrm))); |
| 8822 | delta += 2+alen; |
| 8823 | goto decode_success; |
| 8824 | } |
| 8825 | /* else fall through */ |
| 8826 | } |
| 8827 | |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8828 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8829 | /* 0F E0 = PAVGB -- 8x8 unsigned Packed Average, with rounding */ |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 8830 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xE0) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8831 | do_MMX_preamble(); |
| 8832 | delta = dis_MMXop_regmem_to_reg ( |
| 8833 | sorb, delta+2, insn[1], "pavgb", False ); |
| 8834 | goto decode_success; |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 8835 | } |
| 8836 | |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8837 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8838 | /* 0F E3 = PAVGW -- 16x4 unsigned Packed Average, with rounding */ |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 8839 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xE3) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8840 | do_MMX_preamble(); |
| 8841 | delta = dis_MMXop_regmem_to_reg ( |
| 8842 | sorb, delta+2, insn[1], "pavgw", False ); |
| 8843 | goto decode_success; |
| 8844 | } |
| 8845 | |
| 8846 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8847 | /* 0F C5 = PEXTRW -- extract 16-bit field from mmx(E) and put |
| 8848 | zero-extend of it in ireg(G). */ |
| 8849 | if (insn[0] == 0x0F && insn[1] == 0xC5) { |
| 8850 | modrm = insn[2]; |
| 8851 | if (sz == 4 && epartIsReg(modrm)) { |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8852 | IRTemp sV = newTemp(Ity_I64); |
| 8853 | t5 = newTemp(Ity_I16); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8854 | do_MMX_preamble(); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8855 | assign(sV, getMMXReg(eregOfRM(modrm))); |
| 8856 | breakup64to16s( sV, &t3, &t2, &t1, &t0 ); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8857 | switch (insn[3] & 3) { |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8858 | case 0: assign(t5, mkexpr(t0)); break; |
| 8859 | case 1: assign(t5, mkexpr(t1)); break; |
| 8860 | case 2: assign(t5, mkexpr(t2)); break; |
| 8861 | case 3: assign(t5, mkexpr(t3)); break; |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 8862 | default: vassert(0); /*NOTREACHED*/ |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8863 | } |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8864 | putIReg(4, gregOfRM(modrm), unop(Iop_16Uto32, mkexpr(t5))); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8865 | DIP("pextrw $%d,%s,%s\n", |
| 8866 | (Int)insn[3], nameMMXReg(eregOfRM(modrm)), |
| 8867 | nameIReg(4,gregOfRM(modrm))); |
| 8868 | delta += 4; |
| 8869 | goto decode_success; |
| 8870 | } |
| 8871 | /* else fall through */ |
| 8872 | } |
| 8873 | |
| 8874 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8875 | /* 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and |
| 8876 | put it into the specified lane of mmx(G). */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8877 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xC4) { |
| 8878 | /* Use t0 .. t3 to hold the 4 original 16-bit lanes of the |
| 8879 | mmx reg. t4 is the new lane value. t5 is the original |
| 8880 | mmx value. t6 is the new mmx value. */ |
| 8881 | Int lane; |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8882 | t4 = newTemp(Ity_I16); |
| 8883 | t5 = newTemp(Ity_I64); |
| 8884 | t6 = newTemp(Ity_I64); |
| 8885 | modrm = insn[2]; |
| 8886 | do_MMX_preamble(); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8887 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8888 | assign(t5, getMMXReg(gregOfRM(modrm))); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8889 | breakup64to16s( t5, &t3, &t2, &t1, &t0 ); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8890 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8891 | if (epartIsReg(modrm)) { |
| 8892 | assign(t4, getIReg(2, eregOfRM(modrm))); |
sewardj | aac7e08 | 2005-03-17 14:03:46 +0000 | [diff] [blame] | 8893 | delta += 3+1; |
| 8894 | lane = insn[3+1-1]; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 8895 | DIP("pinsrw $%d,%s,%s\n", lane, |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8896 | nameIReg(2,eregOfRM(modrm)), |
| 8897 | nameMMXReg(gregOfRM(modrm))); |
| 8898 | } else { |
sewardj | 7420b09 | 2005-03-13 20:19:19 +0000 | [diff] [blame] | 8899 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8900 | delta += 3+alen; |
| 8901 | lane = insn[3+alen-1]; |
| 8902 | assign(t4, loadLE(Ity_I16, mkexpr(addr))); |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 8903 | DIP("pinsrw $%d,%s,%s\n", lane, |
sewardj | 7420b09 | 2005-03-13 20:19:19 +0000 | [diff] [blame] | 8904 | dis_buf, |
| 8905 | nameMMXReg(gregOfRM(modrm))); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8906 | } |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8907 | |
| 8908 | switch (lane & 3) { |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 8909 | case 0: assign(t6, mk64from16s(t3,t2,t1,t4)); break; |
| 8910 | case 1: assign(t6, mk64from16s(t3,t2,t4,t0)); break; |
| 8911 | case 2: assign(t6, mk64from16s(t3,t4,t1,t0)); break; |
| 8912 | case 3: assign(t6, mk64from16s(t4,t2,t1,t0)); break; |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 8913 | default: vassert(0); /*NOTREACHED*/ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8914 | } |
| 8915 | putMMXReg(gregOfRM(modrm), mkexpr(t6)); |
| 8916 | goto decode_success; |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8917 | } |
| 8918 | |
| 8919 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8920 | /* 0F EE = PMAXSW -- 16x4 signed max */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8921 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xEE) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8922 | do_MMX_preamble(); |
| 8923 | delta = dis_MMXop_regmem_to_reg ( |
| 8924 | sorb, delta+2, insn[1], "pmaxsw", False ); |
| 8925 | goto decode_success; |
| 8926 | } |
| 8927 | |
| 8928 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8929 | /* 0F DE = PMAXUB -- 8x8 unsigned max */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8930 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xDE) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8931 | do_MMX_preamble(); |
| 8932 | delta = dis_MMXop_regmem_to_reg ( |
| 8933 | sorb, delta+2, insn[1], "pmaxub", False ); |
| 8934 | goto decode_success; |
| 8935 | } |
| 8936 | |
| 8937 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8938 | /* 0F EA = PMINSW -- 16x4 signed min */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8939 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xEA) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8940 | do_MMX_preamble(); |
| 8941 | delta = dis_MMXop_regmem_to_reg ( |
| 8942 | sorb, delta+2, insn[1], "pminsw", False ); |
| 8943 | goto decode_success; |
| 8944 | } |
| 8945 | |
| 8946 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8947 | /* 0F DA = PMINUB -- 8x8 unsigned min */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8948 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xDA) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8949 | do_MMX_preamble(); |
| 8950 | delta = dis_MMXop_regmem_to_reg ( |
| 8951 | sorb, delta+2, insn[1], "pminub", False ); |
| 8952 | goto decode_success; |
| 8953 | } |
| 8954 | |
| 8955 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8956 | /* 0F D7 = PMOVMSKB -- extract sign bits from each of 8 lanes in |
sewardj | e13074c | 2012-11-08 10:57:08 +0000 | [diff] [blame] | 8957 | mmx(E), turn them into a byte, and put zero-extend of it in |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8958 | ireg(G). */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8959 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xD7) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8960 | modrm = insn[2]; |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8961 | if (epartIsReg(modrm)) { |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8962 | do_MMX_preamble(); |
| 8963 | t0 = newTemp(Ity_I64); |
| 8964 | t1 = newTemp(Ity_I32); |
| 8965 | assign(t0, getMMXReg(eregOfRM(modrm))); |
sewardj | e13074c | 2012-11-08 10:57:08 +0000 | [diff] [blame] | 8966 | assign(t1, unop(Iop_8Uto32, unop(Iop_GetMSBs8x8, mkexpr(t0)))); |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 8967 | putIReg(4, gregOfRM(modrm), mkexpr(t1)); |
| 8968 | DIP("pmovmskb %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 8969 | nameIReg(4,gregOfRM(modrm))); |
| 8970 | delta += 3; |
| 8971 | goto decode_success; |
| 8972 | } |
| 8973 | /* else fall through */ |
| 8974 | } |
| 8975 | |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8976 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 8977 | /* 0F E4 = PMULUH -- 16x4 hi-half of unsigned widening multiply */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 8978 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xE4) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 8979 | do_MMX_preamble(); |
| 8980 | delta = dis_MMXop_regmem_to_reg ( |
| 8981 | sorb, delta+2, insn[1], "pmuluh", False ); |
| 8982 | goto decode_success; |
| 8983 | } |
| 8984 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8985 | /* 0F 18 /0 = PREFETCHNTA -- prefetch into caches, */ |
| 8986 | /* 0F 18 /1 = PREFETCH0 -- with various different hints */ |
| 8987 | /* 0F 18 /2 = PREFETCH1 */ |
| 8988 | /* 0F 18 /3 = PREFETCH2 */ |
| 8989 | if (insn[0] == 0x0F && insn[1] == 0x18 |
| 8990 | && !epartIsReg(insn[2]) |
| 8991 | && gregOfRM(insn[2]) >= 0 && gregOfRM(insn[2]) <= 3) { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 8992 | const HChar* hintstr = "??"; |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 8993 | |
| 8994 | modrm = getIByte(delta+2); |
| 8995 | vassert(!epartIsReg(modrm)); |
| 8996 | |
| 8997 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 8998 | delta += 2+alen; |
| 8999 | |
| 9000 | switch (gregOfRM(modrm)) { |
| 9001 | case 0: hintstr = "nta"; break; |
| 9002 | case 1: hintstr = "t0"; break; |
| 9003 | case 2: hintstr = "t1"; break; |
| 9004 | case 3: hintstr = "t2"; break; |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 9005 | default: vassert(0); /*NOTREACHED*/ |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 9006 | } |
| 9007 | |
| 9008 | DIP("prefetch%s %s\n", hintstr, dis_buf); |
| 9009 | goto decode_success; |
| 9010 | } |
| 9011 | |
sewardj | 8531768 | 2006-03-06 14:07:58 +0000 | [diff] [blame] | 9012 | /* 0F 0D /0 = PREFETCH m8 -- 3DNow! prefetch */ |
| 9013 | /* 0F 0D /1 = PREFETCHW m8 -- ditto, with some other hint */ |
| 9014 | if (insn[0] == 0x0F && insn[1] == 0x0D |
| 9015 | && !epartIsReg(insn[2]) |
| 9016 | && gregOfRM(insn[2]) >= 0 && gregOfRM(insn[2]) <= 1) { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 9017 | const HChar* hintstr = "??"; |
sewardj | 8531768 | 2006-03-06 14:07:58 +0000 | [diff] [blame] | 9018 | |
| 9019 | modrm = getIByte(delta+2); |
| 9020 | vassert(!epartIsReg(modrm)); |
| 9021 | |
| 9022 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9023 | delta += 2+alen; |
| 9024 | |
| 9025 | switch (gregOfRM(modrm)) { |
| 9026 | case 0: hintstr = ""; break; |
| 9027 | case 1: hintstr = "w"; break; |
| 9028 | default: vassert(0); /*NOTREACHED*/ |
| 9029 | } |
| 9030 | |
| 9031 | DIP("prefetch%s %s\n", hintstr, dis_buf); |
| 9032 | goto decode_success; |
| 9033 | } |
| 9034 | |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9035 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 9036 | /* 0F F6 = PSADBW -- sum of 8Ux8 absolute differences */ |
sewardj | 7b5b998 | 2005-10-04 11:43:37 +0000 | [diff] [blame] | 9037 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xF6) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9038 | do_MMX_preamble(); |
| 9039 | delta = dis_MMXop_regmem_to_reg ( |
| 9040 | sorb, delta+2, insn[1], "psadbw", False ); |
| 9041 | goto decode_success; |
| 9042 | } |
| 9043 | |
| 9044 | /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ |
| 9045 | /* 0F 70 = PSHUFW -- rearrange 4x16 from E(mmx or mem) to G(mmx) */ |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9046 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x70) { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9047 | Int order; |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9048 | IRTemp sV, dV, s3, s2, s1, s0; |
| 9049 | s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 9050 | sV = newTemp(Ity_I64); |
| 9051 | dV = newTemp(Ity_I64); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9052 | do_MMX_preamble(); |
| 9053 | modrm = insn[2]; |
| 9054 | if (epartIsReg(modrm)) { |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9055 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9056 | order = (Int)insn[3]; |
| 9057 | delta += 2+2; |
| 9058 | DIP("pshufw $%d,%s,%s\n", order, |
| 9059 | nameMMXReg(eregOfRM(modrm)), |
| 9060 | nameMMXReg(gregOfRM(modrm))); |
| 9061 | } else { |
| 9062 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9063 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9064 | order = (Int)insn[2+alen]; |
| 9065 | delta += 3+alen; |
| 9066 | DIP("pshufw $%d,%s,%s\n", order, |
| 9067 | dis_buf, |
| 9068 | nameMMXReg(gregOfRM(modrm))); |
| 9069 | } |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9070 | breakup64to16s( sV, &s3, &s2, &s1, &s0 ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9071 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9072 | # define SEL(n) \ |
| 9073 | ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) |
| 9074 | assign(dV, |
| 9075 | mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3), |
| 9076 | SEL((order>>2)&3), SEL((order>>0)&3) ) |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9077 | ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 9078 | putMMXReg(gregOfRM(modrm), mkexpr(dV)); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9079 | # undef SEL |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9080 | goto decode_success; |
| 9081 | } |
| 9082 | |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 9083 | /* 0F AE /7 = SFENCE -- flush pending operations to memory */ |
| 9084 | if (insn[0] == 0x0F && insn[1] == 0xAE |
| 9085 | && epartIsReg(insn[2]) && gregOfRM(insn[2]) == 7) { |
| 9086 | vassert(sz == 4); |
| 9087 | delta += 3; |
| 9088 | /* Insert a memory fence. It's sometimes important that these |
| 9089 | are carried through to the generated code. */ |
| 9090 | stmt( IRStmt_MBE(Imbe_Fence) ); |
| 9091 | DIP("sfence\n"); |
| 9092 | goto decode_success; |
| 9093 | } |
| 9094 | |
| 9095 | /* End of mmxext sse1 subset. No more sse parsing for mmxext only arches. */ |
| 9096 | if (archinfo->hwcaps == VEX_HWCAPS_X86_MMXEXT/*integer only sse1 subset*/) |
| 9097 | goto after_sse_decoders; |
| 9098 | |
| 9099 | |
| 9100 | /* 0F 5F = MAXPS -- max 32Fx4 from R/M to R */ |
| 9101 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5F) { |
| 9102 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "maxps", Iop_Max32Fx4 ); |
| 9103 | goto decode_success; |
| 9104 | } |
| 9105 | |
| 9106 | /* F3 0F 5F = MAXSS -- max 32F0x4 from R/M to R */ |
| 9107 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5F) { |
| 9108 | vassert(sz == 4); |
| 9109 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "maxss", Iop_Max32F0x4 ); |
| 9110 | goto decode_success; |
| 9111 | } |
| 9112 | |
| 9113 | /* 0F 5D = MINPS -- min 32Fx4 from R/M to R */ |
| 9114 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5D) { |
| 9115 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "minps", Iop_Min32Fx4 ); |
| 9116 | goto decode_success; |
| 9117 | } |
| 9118 | |
| 9119 | /* F3 0F 5D = MINSS -- min 32F0x4 from R/M to R */ |
| 9120 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5D) { |
| 9121 | vassert(sz == 4); |
| 9122 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "minss", Iop_Min32F0x4 ); |
| 9123 | goto decode_success; |
| 9124 | } |
| 9125 | |
| 9126 | /* 0F 28 = MOVAPS -- move from E (mem or xmm) to G (xmm). */ |
| 9127 | /* 0F 10 = MOVUPS -- move from E (mem or xmm) to G (xmm). */ |
| 9128 | if (sz == 4 && insn[0] == 0x0F && (insn[1] == 0x28 || insn[1] == 0x10)) { |
| 9129 | modrm = getIByte(delta+2); |
| 9130 | if (epartIsReg(modrm)) { |
| 9131 | putXMMReg( gregOfRM(modrm), |
| 9132 | getXMMReg( eregOfRM(modrm) )); |
| 9133 | DIP("mov[ua]ps %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9134 | nameXMMReg(gregOfRM(modrm))); |
| 9135 | delta += 2+1; |
| 9136 | } else { |
| 9137 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9138 | if (insn[1] == 0x28/*movaps*/) |
| 9139 | gen_SEGV_if_not_16_aligned( addr ); |
| 9140 | putXMMReg( gregOfRM(modrm), |
| 9141 | loadLE(Ity_V128, mkexpr(addr)) ); |
| 9142 | DIP("mov[ua]ps %s,%s\n", dis_buf, |
| 9143 | nameXMMReg(gregOfRM(modrm))); |
| 9144 | delta += 2+alen; |
| 9145 | } |
| 9146 | goto decode_success; |
| 9147 | } |
| 9148 | |
| 9149 | /* 0F 29 = MOVAPS -- move from G (xmm) to E (mem or xmm). */ |
| 9150 | /* 0F 11 = MOVUPS -- move from G (xmm) to E (mem or xmm). */ |
| 9151 | if (sz == 4 && insn[0] == 0x0F |
| 9152 | && (insn[1] == 0x29 || insn[1] == 0x11)) { |
| 9153 | modrm = getIByte(delta+2); |
| 9154 | if (epartIsReg(modrm)) { |
| 9155 | /* fall through; awaiting test case */ |
| 9156 | } else { |
| 9157 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9158 | if (insn[1] == 0x29/*movaps*/) |
| 9159 | gen_SEGV_if_not_16_aligned( addr ); |
| 9160 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
| 9161 | DIP("mov[ua]ps %s,%s\n", nameXMMReg(gregOfRM(modrm)), |
| 9162 | dis_buf ); |
| 9163 | delta += 2+alen; |
| 9164 | goto decode_success; |
| 9165 | } |
| 9166 | } |
| 9167 | |
| 9168 | /* 0F 16 = MOVHPS -- move from mem to high half of XMM. */ |
| 9169 | /* 0F 16 = MOVLHPS -- move from lo half to hi half of XMM. */ |
| 9170 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x16) { |
| 9171 | modrm = getIByte(delta+2); |
| 9172 | if (epartIsReg(modrm)) { |
| 9173 | delta += 2+1; |
| 9174 | putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/, |
| 9175 | getXMMRegLane64( eregOfRM(modrm), 0 ) ); |
| 9176 | DIP("movhps %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9177 | nameXMMReg(gregOfRM(modrm))); |
| 9178 | } else { |
| 9179 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9180 | delta += 2+alen; |
| 9181 | putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/, |
| 9182 | loadLE(Ity_I64, mkexpr(addr)) ); |
| 9183 | DIP("movhps %s,%s\n", dis_buf, |
| 9184 | nameXMMReg( gregOfRM(modrm) )); |
| 9185 | } |
| 9186 | goto decode_success; |
| 9187 | } |
| 9188 | |
| 9189 | /* 0F 17 = MOVHPS -- move from high half of XMM to mem. */ |
| 9190 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x17) { |
| 9191 | if (!epartIsReg(insn[2])) { |
| 9192 | delta += 2; |
| 9193 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 9194 | delta += alen; |
| 9195 | storeLE( mkexpr(addr), |
| 9196 | getXMMRegLane64( gregOfRM(insn[2]), |
| 9197 | 1/*upper lane*/ ) ); |
| 9198 | DIP("movhps %s,%s\n", nameXMMReg( gregOfRM(insn[2]) ), |
| 9199 | dis_buf); |
| 9200 | goto decode_success; |
| 9201 | } |
| 9202 | /* else fall through */ |
| 9203 | } |
| 9204 | |
| 9205 | /* 0F 12 = MOVLPS -- move from mem to low half of XMM. */ |
| 9206 | /* OF 12 = MOVHLPS -- from from hi half to lo half of XMM. */ |
| 9207 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x12) { |
| 9208 | modrm = getIByte(delta+2); |
| 9209 | if (epartIsReg(modrm)) { |
| 9210 | delta += 2+1; |
| 9211 | putXMMRegLane64( gregOfRM(modrm), |
| 9212 | 0/*lower lane*/, |
| 9213 | getXMMRegLane64( eregOfRM(modrm), 1 )); |
| 9214 | DIP("movhlps %s, %s\n", nameXMMReg(eregOfRM(modrm)), |
| 9215 | nameXMMReg(gregOfRM(modrm))); |
| 9216 | } else { |
| 9217 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9218 | delta += 2+alen; |
| 9219 | putXMMRegLane64( gregOfRM(modrm), 0/*lower lane*/, |
| 9220 | loadLE(Ity_I64, mkexpr(addr)) ); |
| 9221 | DIP("movlps %s, %s\n", |
| 9222 | dis_buf, nameXMMReg( gregOfRM(modrm) )); |
| 9223 | } |
| 9224 | goto decode_success; |
| 9225 | } |
| 9226 | |
| 9227 | /* 0F 13 = MOVLPS -- move from low half of XMM to mem. */ |
| 9228 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x13) { |
| 9229 | if (!epartIsReg(insn[2])) { |
| 9230 | delta += 2; |
| 9231 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 9232 | delta += alen; |
| 9233 | storeLE( mkexpr(addr), |
| 9234 | getXMMRegLane64( gregOfRM(insn[2]), |
| 9235 | 0/*lower lane*/ ) ); |
| 9236 | DIP("movlps %s, %s\n", nameXMMReg( gregOfRM(insn[2]) ), |
| 9237 | dis_buf); |
| 9238 | goto decode_success; |
| 9239 | } |
| 9240 | /* else fall through */ |
| 9241 | } |
| 9242 | |
| 9243 | /* 0F 50 = MOVMSKPS - move 4 sign bits from 4 x F32 in xmm(E) |
| 9244 | to 4 lowest bits of ireg(G) */ |
| 9245 | if (insn[0] == 0x0F && insn[1] == 0x50) { |
| 9246 | modrm = getIByte(delta+2); |
| 9247 | if (sz == 4 && epartIsReg(modrm)) { |
| 9248 | Int src; |
| 9249 | t0 = newTemp(Ity_I32); |
| 9250 | t1 = newTemp(Ity_I32); |
| 9251 | t2 = newTemp(Ity_I32); |
| 9252 | t3 = newTemp(Ity_I32); |
| 9253 | delta += 2+1; |
| 9254 | src = eregOfRM(modrm); |
| 9255 | assign( t0, binop( Iop_And32, |
| 9256 | binop(Iop_Shr32, getXMMRegLane32(src,0), mkU8(31)), |
| 9257 | mkU32(1) )); |
| 9258 | assign( t1, binop( Iop_And32, |
| 9259 | binop(Iop_Shr32, getXMMRegLane32(src,1), mkU8(30)), |
| 9260 | mkU32(2) )); |
| 9261 | assign( t2, binop( Iop_And32, |
| 9262 | binop(Iop_Shr32, getXMMRegLane32(src,2), mkU8(29)), |
| 9263 | mkU32(4) )); |
| 9264 | assign( t3, binop( Iop_And32, |
| 9265 | binop(Iop_Shr32, getXMMRegLane32(src,3), mkU8(28)), |
| 9266 | mkU32(8) )); |
| 9267 | putIReg(4, gregOfRM(modrm), |
| 9268 | binop(Iop_Or32, |
| 9269 | binop(Iop_Or32, mkexpr(t0), mkexpr(t1)), |
| 9270 | binop(Iop_Or32, mkexpr(t2), mkexpr(t3)) |
| 9271 | ) |
| 9272 | ); |
| 9273 | DIP("movmskps %s,%s\n", nameXMMReg(src), |
| 9274 | nameIReg(4, gregOfRM(modrm))); |
| 9275 | goto decode_success; |
| 9276 | } |
| 9277 | /* else fall through */ |
| 9278 | } |
| 9279 | |
| 9280 | /* 0F 2B = MOVNTPS -- for us, just a plain SSE store. */ |
| 9281 | /* 66 0F 2B = MOVNTPD -- for us, just a plain SSE store. */ |
| 9282 | if (insn[0] == 0x0F && insn[1] == 0x2B) { |
| 9283 | modrm = getIByte(delta+2); |
| 9284 | if (!epartIsReg(modrm)) { |
| 9285 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9286 | gen_SEGV_if_not_16_aligned( addr ); |
| 9287 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
| 9288 | DIP("movntp%s %s,%s\n", sz==2 ? "d" : "s", |
| 9289 | dis_buf, |
| 9290 | nameXMMReg(gregOfRM(modrm))); |
| 9291 | delta += 2+alen; |
| 9292 | goto decode_success; |
| 9293 | } |
| 9294 | /* else fall through */ |
| 9295 | } |
| 9296 | |
| 9297 | /* F3 0F 10 = MOVSS -- move 32 bits from E (mem or lo 1/4 xmm) to G |
| 9298 | (lo 1/4 xmm). If E is mem, upper 3/4 of G is zeroed out. */ |
| 9299 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x10) { |
| 9300 | vassert(sz == 4); |
| 9301 | modrm = getIByte(delta+3); |
| 9302 | if (epartIsReg(modrm)) { |
| 9303 | putXMMRegLane32( gregOfRM(modrm), 0, |
| 9304 | getXMMRegLane32( eregOfRM(modrm), 0 )); |
| 9305 | DIP("movss %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9306 | nameXMMReg(gregOfRM(modrm))); |
| 9307 | delta += 3+1; |
| 9308 | } else { |
| 9309 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9310 | /* zero bits 127:64 */ |
| 9311 | putXMMRegLane64( gregOfRM(modrm), 1, mkU64(0) ); |
| 9312 | /* zero bits 63:32 */ |
| 9313 | putXMMRegLane32( gregOfRM(modrm), 1, mkU32(0) ); |
| 9314 | /* write bits 31:0 */ |
| 9315 | putXMMRegLane32( gregOfRM(modrm), 0, |
| 9316 | loadLE(Ity_I32, mkexpr(addr)) ); |
| 9317 | DIP("movss %s,%s\n", dis_buf, |
| 9318 | nameXMMReg(gregOfRM(modrm))); |
| 9319 | delta += 3+alen; |
| 9320 | } |
| 9321 | goto decode_success; |
| 9322 | } |
| 9323 | |
| 9324 | /* F3 0F 11 = MOVSS -- move 32 bits from G (lo 1/4 xmm) to E (mem |
| 9325 | or lo 1/4 xmm). */ |
| 9326 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x11) { |
| 9327 | vassert(sz == 4); |
| 9328 | modrm = getIByte(delta+3); |
| 9329 | if (epartIsReg(modrm)) { |
| 9330 | /* fall through, we don't yet have a test case */ |
| 9331 | } else { |
| 9332 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9333 | storeLE( mkexpr(addr), |
| 9334 | getXMMRegLane32(gregOfRM(modrm), 0) ); |
| 9335 | DIP("movss %s,%s\n", nameXMMReg(gregOfRM(modrm)), |
| 9336 | dis_buf); |
| 9337 | delta += 3+alen; |
| 9338 | goto decode_success; |
| 9339 | } |
| 9340 | } |
| 9341 | |
| 9342 | /* 0F 59 = MULPS -- mul 32Fx4 from R/M to R */ |
| 9343 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x59) { |
| 9344 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "mulps", Iop_Mul32Fx4 ); |
| 9345 | goto decode_success; |
| 9346 | } |
| 9347 | |
| 9348 | /* F3 0F 59 = MULSS -- mul 32F0x4 from R/M to R */ |
| 9349 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x59) { |
| 9350 | vassert(sz == 4); |
| 9351 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "mulss", Iop_Mul32F0x4 ); |
| 9352 | goto decode_success; |
| 9353 | } |
| 9354 | |
| 9355 | /* 0F 56 = ORPS -- G = G and E */ |
| 9356 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x56) { |
| 9357 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "orps", Iop_OrV128 ); |
| 9358 | goto decode_success; |
| 9359 | } |
| 9360 | |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9361 | /* 0F 53 = RCPPS -- approx reciprocal 32Fx4 from R/M to R */ |
| 9362 | if (insn[0] == 0x0F && insn[1] == 0x53) { |
| 9363 | vassert(sz == 4); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 9364 | delta = dis_SSE_E_to_G_unary_all( sorb, delta+2, |
sewardj | 1ddee21 | 2014-08-24 14:00:19 +0000 | [diff] [blame] | 9365 | "rcpps", Iop_RecipEst32Fx4 ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9366 | goto decode_success; |
| 9367 | } |
| 9368 | |
| 9369 | /* F3 0F 53 = RCPSS -- approx reciprocal 32F0x4 from R/M to R */ |
| 9370 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x53) { |
| 9371 | vassert(sz == 4); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 9372 | delta = dis_SSE_E_to_G_unary_lo32( sorb, delta+3, |
sewardj | 1ddee21 | 2014-08-24 14:00:19 +0000 | [diff] [blame] | 9373 | "rcpss", Iop_RecipEst32F0x4 ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 9374 | goto decode_success; |
| 9375 | } |
sewardj | b545208 | 2004-12-04 20:33:02 +0000 | [diff] [blame] | 9376 | |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9377 | /* 0F 52 = RSQRTPS -- approx reciprocal sqrt 32Fx4 from R/M to R */ |
| 9378 | if (insn[0] == 0x0F && insn[1] == 0x52) { |
| 9379 | vassert(sz == 4); |
| 9380 | delta = dis_SSE_E_to_G_unary_all( sorb, delta+2, |
sewardj | 1ddee21 | 2014-08-24 14:00:19 +0000 | [diff] [blame] | 9381 | "rsqrtps", Iop_RSqrtEst32Fx4 ); |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9382 | goto decode_success; |
| 9383 | } |
| 9384 | |
| 9385 | /* F3 0F 52 = RSQRTSS -- approx reciprocal sqrt 32F0x4 from R/M to R */ |
| 9386 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x52) { |
| 9387 | vassert(sz == 4); |
| 9388 | delta = dis_SSE_E_to_G_unary_lo32( sorb, delta+3, |
sewardj | 1ddee21 | 2014-08-24 14:00:19 +0000 | [diff] [blame] | 9389 | "rsqrtss", Iop_RSqrtEst32F0x4 ); |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9390 | goto decode_success; |
| 9391 | } |
| 9392 | |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9393 | /* 0F C6 /r ib = SHUFPS -- shuffle packed F32s */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9394 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xC6) { |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9395 | Int select; |
| 9396 | IRTemp sV, dV; |
| 9397 | IRTemp s3, s2, s1, s0, d3, d2, d1, d0; |
| 9398 | sV = newTemp(Ity_V128); |
| 9399 | dV = newTemp(Ity_V128); |
| 9400 | s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9401 | modrm = insn[2]; |
| 9402 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 9403 | |
| 9404 | if (epartIsReg(modrm)) { |
| 9405 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 9406 | select = (Int)insn[3]; |
| 9407 | delta += 2+2; |
| 9408 | DIP("shufps $%d,%s,%s\n", select, |
| 9409 | nameXMMReg(eregOfRM(modrm)), |
| 9410 | nameXMMReg(gregOfRM(modrm))); |
| 9411 | } else { |
| 9412 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9413 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9414 | select = (Int)insn[2+alen]; |
| 9415 | delta += 3+alen; |
| 9416 | DIP("shufps $%d,%s,%s\n", select, |
| 9417 | dis_buf, |
| 9418 | nameXMMReg(gregOfRM(modrm))); |
| 9419 | } |
| 9420 | |
| 9421 | breakup128to32s( dV, &d3, &d2, &d1, &d0 ); |
| 9422 | breakup128to32s( sV, &s3, &s2, &s1, &s0 ); |
| 9423 | |
| 9424 | # define SELD(n) ((n)==0 ? d0 : ((n)==1 ? d1 : ((n)==2 ? d2 : d3))) |
| 9425 | # define SELS(n) ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) |
| 9426 | |
| 9427 | putXMMReg( |
| 9428 | gregOfRM(modrm), |
| 9429 | mk128from32s( SELS((select>>6)&3), SELS((select>>4)&3), |
| 9430 | SELD((select>>2)&3), SELD((select>>0)&3) ) |
| 9431 | ); |
| 9432 | |
| 9433 | # undef SELD |
| 9434 | # undef SELS |
| 9435 | |
| 9436 | goto decode_success; |
| 9437 | } |
| 9438 | |
| 9439 | /* 0F 51 = SQRTPS -- approx sqrt 32Fx4 from R/M to R */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9440 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x51) { |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9441 | delta = dis_SSE_E_to_G_unary_all( sorb, delta+2, |
| 9442 | "sqrtps", Iop_Sqrt32Fx4 ); |
| 9443 | goto decode_success; |
| 9444 | } |
| 9445 | |
| 9446 | /* F3 0F 51 = SQRTSS -- approx sqrt 32F0x4 from R/M to R */ |
| 9447 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x51) { |
| 9448 | vassert(sz == 4); |
| 9449 | delta = dis_SSE_E_to_G_unary_lo32( sorb, delta+3, |
| 9450 | "sqrtss", Iop_Sqrt32F0x4 ); |
| 9451 | goto decode_success; |
| 9452 | } |
| 9453 | |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 9454 | /* 0F AE /3 = STMXCSR m32 -- store %mxcsr */ |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 9455 | if (insn[0] == 0x0F && insn[1] == 0xAE |
| 9456 | && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 3) { |
| 9457 | modrm = getIByte(delta+2); |
| 9458 | vassert(sz == 4); |
| 9459 | vassert(!epartIsReg(modrm)); |
| 9460 | |
| 9461 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9462 | delta += 2+alen; |
| 9463 | |
| 9464 | /* Fake up a native SSE mxcsr word. The only thing it depends |
| 9465 | on is SSEROUND[1:0], so call a clean helper to cook it up. |
| 9466 | */ |
| 9467 | /* UInt x86h_create_mxcsr ( UInt sseround ) */ |
sewardj | 33dd31b | 2005-01-08 18:17:32 +0000 | [diff] [blame] | 9468 | DIP("stmxcsr %s\n", dis_buf); |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 9469 | storeLE( mkexpr(addr), |
| 9470 | mkIRExprCCall( |
| 9471 | Ity_I32, 0/*regp*/, |
sewardj | 3bd6f3e | 2004-12-13 10:48:19 +0000 | [diff] [blame] | 9472 | "x86g_create_mxcsr", &x86g_create_mxcsr, |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 9473 | mkIRExprVec_1( get_sse_roundingmode() ) |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 9474 | ) |
| 9475 | ); |
| 9476 | goto decode_success; |
| 9477 | } |
| 9478 | |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9479 | /* 0F 5C = SUBPS -- sub 32Fx4 from R/M to R */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9480 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5C) { |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9481 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "subps", Iop_Sub32Fx4 ); |
| 9482 | goto decode_success; |
| 9483 | } |
| 9484 | |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9485 | /* F3 0F 5C = SUBSS -- sub 32F0x4 from R/M to R */ |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9486 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5C) { |
| 9487 | vassert(sz == 4); |
| 9488 | delta = dis_SSE_E_to_G_lo32( sorb, delta+3, "subss", Iop_Sub32F0x4 ); |
| 9489 | goto decode_success; |
| 9490 | } |
| 9491 | |
| 9492 | /* 0F 15 = UNPCKHPS -- unpack and interleave high part F32s */ |
| 9493 | /* 0F 14 = UNPCKLPS -- unpack and interleave low part F32s */ |
| 9494 | /* These just appear to be special cases of SHUFPS */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9495 | if (sz == 4 && insn[0] == 0x0F && (insn[1] == 0x15 || insn[1] == 0x14)) { |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9496 | IRTemp sV, dV; |
| 9497 | IRTemp s3, s2, s1, s0, d3, d2, d1, d0; |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 9498 | Bool hi = toBool(insn[1] == 0x15); |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9499 | sV = newTemp(Ity_V128); |
| 9500 | dV = newTemp(Ity_V128); |
| 9501 | s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9502 | modrm = insn[2]; |
| 9503 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 9504 | |
| 9505 | if (epartIsReg(modrm)) { |
| 9506 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 9507 | delta += 2+1; |
| 9508 | DIP("unpck%sps %s,%s\n", hi ? "h" : "l", |
| 9509 | nameXMMReg(eregOfRM(modrm)), |
| 9510 | nameXMMReg(gregOfRM(modrm))); |
| 9511 | } else { |
| 9512 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9513 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9514 | delta += 2+alen; |
| 9515 | DIP("unpck%sps %s,%s\n", hi ? "h" : "l", |
| 9516 | dis_buf, |
| 9517 | nameXMMReg(gregOfRM(modrm))); |
| 9518 | } |
| 9519 | |
| 9520 | breakup128to32s( dV, &d3, &d2, &d1, &d0 ); |
| 9521 | breakup128to32s( sV, &s3, &s2, &s1, &s0 ); |
| 9522 | |
| 9523 | if (hi) { |
| 9524 | putXMMReg( gregOfRM(modrm), mk128from32s( s3, d3, s2, d2 ) ); |
| 9525 | } else { |
| 9526 | putXMMReg( gregOfRM(modrm), mk128from32s( s1, d1, s0, d0 ) ); |
| 9527 | } |
| 9528 | |
| 9529 | goto decode_success; |
| 9530 | } |
| 9531 | |
| 9532 | /* 0F 57 = XORPS -- G = G and E */ |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 9533 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x57) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9534 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "xorps", Iop_XorV128 ); |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 9535 | goto decode_success; |
| 9536 | } |
| 9537 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 9538 | /* ---------------------------------------------------- */ |
| 9539 | /* --- end of the SSE decoder. --- */ |
| 9540 | /* ---------------------------------------------------- */ |
| 9541 | |
| 9542 | /* ---------------------------------------------------- */ |
| 9543 | /* --- start of the SSE2 decoder. --- */ |
| 9544 | /* ---------------------------------------------------- */ |
| 9545 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 9546 | /* Skip parts of the decoder which don't apply given the stated |
| 9547 | guest subarchitecture. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9548 | if (0 == (archinfo->hwcaps & VEX_HWCAPS_X86_SSE2)) |
| 9549 | goto after_sse_decoders; /* no SSE2 capabilities */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 9550 | |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 9551 | insn = &guest_code[delta]; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 9552 | |
| 9553 | /* 66 0F 58 = ADDPD -- add 32Fx4 from R/M to R */ |
| 9554 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x58) { |
| 9555 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "addpd", Iop_Add64Fx2 ); |
| 9556 | goto decode_success; |
| 9557 | } |
| 9558 | |
| 9559 | /* F2 0F 58 = ADDSD -- add 64F0x2 from R/M to R */ |
| 9560 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x58) { |
| 9561 | vassert(sz == 4); |
| 9562 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "addsd", Iop_Add64F0x2 ); |
| 9563 | goto decode_success; |
| 9564 | } |
| 9565 | |
| 9566 | /* 66 0F 55 = ANDNPD -- G = (not G) and E */ |
| 9567 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x55) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9568 | delta = dis_SSE_E_to_G_all_invG( sorb, delta+2, "andnpd", Iop_AndV128 ); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 9569 | goto decode_success; |
| 9570 | } |
| 9571 | |
| 9572 | /* 66 0F 54 = ANDPD -- G = G and E */ |
| 9573 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x54) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9574 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "andpd", Iop_AndV128 ); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 9575 | goto decode_success; |
| 9576 | } |
| 9577 | |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9578 | /* 66 0F C2 = CMPPD -- 64Fx2 comparison from R/M to R */ |
| 9579 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xC2) { |
| 9580 | delta = dis_SSEcmp_E_to_G( sorb, delta+2, "cmppd", True, 8 ); |
| 9581 | goto decode_success; |
| 9582 | } |
| 9583 | |
| 9584 | /* F2 0F C2 = CMPSD -- 64F0x2 comparison from R/M to R */ |
| 9585 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xC2) { |
| 9586 | vassert(sz == 4); |
| 9587 | delta = dis_SSEcmp_E_to_G( sorb, delta+3, "cmpsd", False, 8 ); |
| 9588 | goto decode_success; |
| 9589 | } |
| 9590 | |
| 9591 | /* 66 0F 2F = COMISD -- 64F0x2 comparison G,E, and set ZCP */ |
| 9592 | /* 66 0F 2E = UCOMISD -- 64F0x2 comparison G,E, and set ZCP */ |
| 9593 | if (sz == 2 && insn[0] == 0x0F && (insn[1] == 0x2F || insn[1] == 0x2E)) { |
| 9594 | IRTemp argL = newTemp(Ity_F64); |
| 9595 | IRTemp argR = newTemp(Ity_F64); |
| 9596 | modrm = getIByte(delta+2); |
| 9597 | if (epartIsReg(modrm)) { |
| 9598 | assign( argR, getXMMRegLane64F( eregOfRM(modrm), 0/*lowest lane*/ ) ); |
| 9599 | delta += 2+1; |
| 9600 | DIP("[u]comisd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9601 | nameXMMReg(gregOfRM(modrm)) ); |
| 9602 | } else { |
| 9603 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9604 | assign( argR, loadLE(Ity_F64, mkexpr(addr)) ); |
| 9605 | delta += 2+alen; |
| 9606 | DIP("[u]comisd %s,%s\n", dis_buf, |
| 9607 | nameXMMReg(gregOfRM(modrm)) ); |
| 9608 | } |
| 9609 | assign( argL, getXMMRegLane64F( gregOfRM(modrm), 0/*lowest lane*/ ) ); |
| 9610 | |
| 9611 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 9612 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 9613 | stmt( IRStmt_Put( |
| 9614 | OFFB_CC_DEP1, |
| 9615 | binop( Iop_And32, |
| 9616 | binop(Iop_CmpF64, mkexpr(argL), mkexpr(argR)), |
| 9617 | mkU32(0x45) |
| 9618 | ))); |
sewardj | a3b7e3a | 2005-04-05 01:54:19 +0000 | [diff] [blame] | 9619 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 9620 | elimination of previous stores to this field work better. */ |
| 9621 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9622 | goto decode_success; |
| 9623 | } |
| 9624 | |
| 9625 | /* F3 0F E6 = CVTDQ2PD -- convert 2 x I32 in mem/lo half xmm to 2 x |
| 9626 | F64 in xmm(G) */ |
| 9627 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xE6) { |
| 9628 | IRTemp arg64 = newTemp(Ity_I64); |
| 9629 | vassert(sz == 4); |
| 9630 | |
| 9631 | modrm = getIByte(delta+3); |
| 9632 | if (epartIsReg(modrm)) { |
| 9633 | assign( arg64, getXMMRegLane64(eregOfRM(modrm), 0) ); |
| 9634 | delta += 3+1; |
| 9635 | DIP("cvtdq2pd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9636 | nameXMMReg(gregOfRM(modrm))); |
| 9637 | } else { |
| 9638 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9639 | assign( arg64, loadLE(Ity_I64, mkexpr(addr)) ); |
| 9640 | delta += 3+alen; |
| 9641 | DIP("cvtdq2pd %s,%s\n", dis_buf, |
| 9642 | nameXMMReg(gregOfRM(modrm)) ); |
| 9643 | } |
| 9644 | |
| 9645 | putXMMRegLane64F( |
| 9646 | gregOfRM(modrm), 0, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9647 | unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64))) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9648 | ); |
| 9649 | |
| 9650 | putXMMRegLane64F( |
| 9651 | gregOfRM(modrm), 1, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9652 | unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64))) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9653 | ); |
| 9654 | |
| 9655 | goto decode_success; |
| 9656 | } |
| 9657 | |
| 9658 | /* 0F 5B = CVTDQ2PS -- convert 4 x I32 in mem/xmm to 4 x F32 in |
| 9659 | xmm(G) */ |
| 9660 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5B) { |
| 9661 | IRTemp argV = newTemp(Ity_V128); |
| 9662 | IRTemp rmode = newTemp(Ity_I32); |
| 9663 | |
| 9664 | modrm = getIByte(delta+2); |
| 9665 | if (epartIsReg(modrm)) { |
| 9666 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 9667 | delta += 2+1; |
| 9668 | DIP("cvtdq2ps %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9669 | nameXMMReg(gregOfRM(modrm))); |
| 9670 | } else { |
| 9671 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9672 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9673 | delta += 2+alen; |
| 9674 | DIP("cvtdq2ps %s,%s\n", dis_buf, |
| 9675 | nameXMMReg(gregOfRM(modrm)) ); |
| 9676 | } |
| 9677 | |
| 9678 | assign( rmode, get_sse_roundingmode() ); |
| 9679 | breakup128to32s( argV, &t3, &t2, &t1, &t0 ); |
| 9680 | |
| 9681 | # define CVT(_t) binop( Iop_F64toF32, \ |
| 9682 | mkexpr(rmode), \ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9683 | unop(Iop_I32StoF64,mkexpr(_t))) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9684 | |
| 9685 | putXMMRegLane32F( gregOfRM(modrm), 3, CVT(t3) ); |
| 9686 | putXMMRegLane32F( gregOfRM(modrm), 2, CVT(t2) ); |
| 9687 | putXMMRegLane32F( gregOfRM(modrm), 1, CVT(t1) ); |
| 9688 | putXMMRegLane32F( gregOfRM(modrm), 0, CVT(t0) ); |
| 9689 | |
| 9690 | # undef CVT |
| 9691 | |
| 9692 | goto decode_success; |
| 9693 | } |
| 9694 | |
| 9695 | /* F2 0F E6 = CVTPD2DQ -- convert 2 x F64 in mem/xmm to 2 x I32 in |
| 9696 | lo half xmm(G), and zero upper half */ |
| 9697 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xE6) { |
| 9698 | IRTemp argV = newTemp(Ity_V128); |
| 9699 | IRTemp rmode = newTemp(Ity_I32); |
| 9700 | vassert(sz == 4); |
| 9701 | |
| 9702 | modrm = getIByte(delta+3); |
| 9703 | if (epartIsReg(modrm)) { |
| 9704 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 9705 | delta += 3+1; |
| 9706 | DIP("cvtpd2dq %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9707 | nameXMMReg(gregOfRM(modrm))); |
| 9708 | } else { |
| 9709 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9710 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9711 | delta += 3+alen; |
| 9712 | DIP("cvtpd2dq %s,%s\n", dis_buf, |
| 9713 | nameXMMReg(gregOfRM(modrm)) ); |
| 9714 | } |
| 9715 | |
| 9716 | assign( rmode, get_sse_roundingmode() ); |
| 9717 | t0 = newTemp(Ity_F64); |
| 9718 | t1 = newTemp(Ity_F64); |
| 9719 | assign( t0, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9720 | unop(Iop_V128to64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9721 | assign( t1, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9722 | unop(Iop_V128HIto64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9723 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9724 | # define CVT(_t) binop( Iop_F64toI32S, \ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9725 | mkexpr(rmode), \ |
| 9726 | mkexpr(_t) ) |
| 9727 | |
| 9728 | putXMMRegLane32( gregOfRM(modrm), 3, mkU32(0) ); |
| 9729 | putXMMRegLane32( gregOfRM(modrm), 2, mkU32(0) ); |
| 9730 | putXMMRegLane32( gregOfRM(modrm), 1, CVT(t1) ); |
| 9731 | putXMMRegLane32( gregOfRM(modrm), 0, CVT(t0) ); |
| 9732 | |
| 9733 | # undef CVT |
| 9734 | |
| 9735 | goto decode_success; |
| 9736 | } |
| 9737 | |
| 9738 | /* 66 0F 2D = CVTPD2PI -- convert 2 x F64 in mem/xmm to 2 x |
| 9739 | I32 in mmx, according to prevailing SSE rounding mode */ |
| 9740 | /* 66 0F 2C = CVTTPD2PI -- convert 2 x F64 in mem/xmm to 2 x |
| 9741 | I32 in mmx, rounding towards zero */ |
| 9742 | if (sz == 2 && insn[0] == 0x0F && (insn[1] == 0x2D || insn[1] == 0x2C)) { |
| 9743 | IRTemp dst64 = newTemp(Ity_I64); |
| 9744 | IRTemp rmode = newTemp(Ity_I32); |
| 9745 | IRTemp f64lo = newTemp(Ity_F64); |
| 9746 | IRTemp f64hi = newTemp(Ity_F64); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 9747 | Bool r2zero = toBool(insn[1] == 0x2C); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9748 | |
| 9749 | do_MMX_preamble(); |
| 9750 | modrm = getIByte(delta+2); |
| 9751 | |
| 9752 | if (epartIsReg(modrm)) { |
| 9753 | delta += 2+1; |
| 9754 | assign(f64lo, getXMMRegLane64F(eregOfRM(modrm), 0)); |
| 9755 | assign(f64hi, getXMMRegLane64F(eregOfRM(modrm), 1)); |
| 9756 | DIP("cvt%spd2pi %s,%s\n", r2zero ? "t" : "", |
| 9757 | nameXMMReg(eregOfRM(modrm)), |
| 9758 | nameMMXReg(gregOfRM(modrm))); |
| 9759 | } else { |
| 9760 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9761 | assign(f64lo, loadLE(Ity_F64, mkexpr(addr))); |
| 9762 | assign(f64hi, loadLE(Ity_F64, binop( Iop_Add32, |
| 9763 | mkexpr(addr), |
| 9764 | mkU32(8) ))); |
| 9765 | delta += 2+alen; |
| 9766 | DIP("cvt%spf2pi %s,%s\n", r2zero ? "t" : "", |
| 9767 | dis_buf, |
| 9768 | nameMMXReg(gregOfRM(modrm))); |
| 9769 | } |
| 9770 | |
| 9771 | if (r2zero) { |
| 9772 | assign(rmode, mkU32((UInt)Irrm_ZERO) ); |
| 9773 | } else { |
| 9774 | assign( rmode, get_sse_roundingmode() ); |
| 9775 | } |
| 9776 | |
| 9777 | assign( |
| 9778 | dst64, |
| 9779 | binop( Iop_32HLto64, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9780 | binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64hi) ), |
| 9781 | binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo) ) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9782 | ) |
| 9783 | ); |
| 9784 | |
| 9785 | putMMXReg(gregOfRM(modrm), mkexpr(dst64)); |
| 9786 | goto decode_success; |
| 9787 | } |
| 9788 | |
| 9789 | /* 66 0F 5A = CVTPD2PS -- convert 2 x F64 in mem/xmm to 2 x F32 in |
| 9790 | lo half xmm(G), and zero upper half */ |
| 9791 | /* Note, this is practically identical to CVTPD2DQ. It would have |
| 9792 | been nicer to merge them together, but the insn[] offsets differ |
| 9793 | by one. */ |
| 9794 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5A) { |
| 9795 | IRTemp argV = newTemp(Ity_V128); |
| 9796 | IRTemp rmode = newTemp(Ity_I32); |
| 9797 | |
| 9798 | modrm = getIByte(delta+2); |
| 9799 | if (epartIsReg(modrm)) { |
| 9800 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 9801 | delta += 2+1; |
| 9802 | DIP("cvtpd2ps %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9803 | nameXMMReg(gregOfRM(modrm))); |
| 9804 | } else { |
| 9805 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9806 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9807 | delta += 2+alen; |
| 9808 | DIP("cvtpd2ps %s,%s\n", dis_buf, |
| 9809 | nameXMMReg(gregOfRM(modrm)) ); |
| 9810 | } |
| 9811 | |
| 9812 | assign( rmode, get_sse_roundingmode() ); |
| 9813 | t0 = newTemp(Ity_F64); |
| 9814 | t1 = newTemp(Ity_F64); |
| 9815 | assign( t0, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9816 | unop(Iop_V128to64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9817 | assign( t1, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 9818 | unop(Iop_V128HIto64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9819 | |
| 9820 | # define CVT(_t) binop( Iop_F64toF32, \ |
| 9821 | mkexpr(rmode), \ |
| 9822 | mkexpr(_t) ) |
| 9823 | |
| 9824 | putXMMRegLane32( gregOfRM(modrm), 3, mkU32(0) ); |
| 9825 | putXMMRegLane32( gregOfRM(modrm), 2, mkU32(0) ); |
| 9826 | putXMMRegLane32F( gregOfRM(modrm), 1, CVT(t1) ); |
| 9827 | putXMMRegLane32F( gregOfRM(modrm), 0, CVT(t0) ); |
| 9828 | |
| 9829 | # undef CVT |
| 9830 | |
| 9831 | goto decode_success; |
| 9832 | } |
| 9833 | |
| 9834 | /* 66 0F 2A = CVTPI2PD -- convert 2 x I32 in mem/mmx to 2 x F64 in |
| 9835 | xmm(G) */ |
| 9836 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x2A) { |
| 9837 | IRTemp arg64 = newTemp(Ity_I64); |
| 9838 | |
| 9839 | modrm = getIByte(delta+2); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9840 | if (epartIsReg(modrm)) { |
sewardj | 30a20e9 | 2010-02-21 20:40:53 +0000 | [diff] [blame] | 9841 | /* Only switch to MMX mode if the source is a MMX register. |
| 9842 | This is inconsistent with all other instructions which |
| 9843 | convert between XMM and (M64 or MMX), which always switch |
| 9844 | to MMX mode even if 64-bit operand is M64 and not MMX. At |
| 9845 | least, that's what the Intel docs seem to me to say. |
| 9846 | Fixes #210264. */ |
| 9847 | do_MMX_preamble(); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9848 | assign( arg64, getMMXReg(eregOfRM(modrm)) ); |
| 9849 | delta += 2+1; |
| 9850 | DIP("cvtpi2pd %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 9851 | nameXMMReg(gregOfRM(modrm))); |
| 9852 | } else { |
| 9853 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9854 | assign( arg64, loadLE(Ity_I64, mkexpr(addr)) ); |
| 9855 | delta += 2+alen; |
| 9856 | DIP("cvtpi2pd %s,%s\n", dis_buf, |
| 9857 | nameXMMReg(gregOfRM(modrm)) ); |
| 9858 | } |
| 9859 | |
| 9860 | putXMMRegLane64F( |
| 9861 | gregOfRM(modrm), 0, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9862 | unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64)) ) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9863 | ); |
| 9864 | |
| 9865 | putXMMRegLane64F( |
| 9866 | gregOfRM(modrm), 1, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9867 | unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64)) ) |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9868 | ); |
| 9869 | |
| 9870 | goto decode_success; |
| 9871 | } |
| 9872 | |
| 9873 | /* 66 0F 5B = CVTPS2DQ -- convert 4 x F32 in mem/xmm to 4 x I32 in |
| 9874 | xmm(G) */ |
| 9875 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5B) { |
| 9876 | IRTemp argV = newTemp(Ity_V128); |
| 9877 | IRTemp rmode = newTemp(Ity_I32); |
| 9878 | |
| 9879 | modrm = getIByte(delta+2); |
| 9880 | if (epartIsReg(modrm)) { |
| 9881 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 9882 | delta += 2+1; |
| 9883 | DIP("cvtps2dq %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9884 | nameXMMReg(gregOfRM(modrm))); |
| 9885 | } else { |
| 9886 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9887 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 9888 | delta += 2+alen; |
| 9889 | DIP("cvtps2dq %s,%s\n", dis_buf, |
| 9890 | nameXMMReg(gregOfRM(modrm)) ); |
| 9891 | } |
| 9892 | |
| 9893 | assign( rmode, get_sse_roundingmode() ); |
| 9894 | breakup128to32s( argV, &t3, &t2, &t1, &t0 ); |
| 9895 | |
| 9896 | /* This is less than ideal. If it turns out to be a performance |
| 9897 | bottleneck it can be improved. */ |
| 9898 | # define CVT(_t) \ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9899 | binop( Iop_F64toI32S, \ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9900 | mkexpr(rmode), \ |
| 9901 | unop( Iop_F32toF64, \ |
| 9902 | unop( Iop_ReinterpI32asF32, mkexpr(_t))) ) |
| 9903 | |
| 9904 | putXMMRegLane32( gregOfRM(modrm), 3, CVT(t3) ); |
| 9905 | putXMMRegLane32( gregOfRM(modrm), 2, CVT(t2) ); |
| 9906 | putXMMRegLane32( gregOfRM(modrm), 1, CVT(t1) ); |
| 9907 | putXMMRegLane32( gregOfRM(modrm), 0, CVT(t0) ); |
| 9908 | |
| 9909 | # undef CVT |
| 9910 | |
| 9911 | goto decode_success; |
| 9912 | } |
| 9913 | |
| 9914 | /* 0F 5A = CVTPS2PD -- convert 2 x F32 in low half mem/xmm to 2 x |
| 9915 | F64 in xmm(G). */ |
| 9916 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0x5A) { |
| 9917 | IRTemp f32lo = newTemp(Ity_F32); |
| 9918 | IRTemp f32hi = newTemp(Ity_F32); |
| 9919 | |
| 9920 | modrm = getIByte(delta+2); |
| 9921 | if (epartIsReg(modrm)) { |
| 9922 | assign( f32lo, getXMMRegLane32F(eregOfRM(modrm), 0) ); |
| 9923 | assign( f32hi, getXMMRegLane32F(eregOfRM(modrm), 1) ); |
| 9924 | delta += 2+1; |
| 9925 | DIP("cvtps2pd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9926 | nameXMMReg(gregOfRM(modrm))); |
| 9927 | } else { |
| 9928 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 9929 | assign( f32lo, loadLE(Ity_F32, mkexpr(addr)) ); |
| 9930 | assign( f32hi, loadLE(Ity_F32, |
| 9931 | binop(Iop_Add32,mkexpr(addr),mkU32(4))) ); |
| 9932 | delta += 2+alen; |
| 9933 | DIP("cvtps2pd %s,%s\n", dis_buf, |
| 9934 | nameXMMReg(gregOfRM(modrm)) ); |
| 9935 | } |
| 9936 | |
| 9937 | putXMMRegLane64F( gregOfRM(modrm), 1, |
| 9938 | unop(Iop_F32toF64, mkexpr(f32hi)) ); |
| 9939 | putXMMRegLane64F( gregOfRM(modrm), 0, |
| 9940 | unop(Iop_F32toF64, mkexpr(f32lo)) ); |
| 9941 | |
| 9942 | goto decode_success; |
| 9943 | } |
| 9944 | |
| 9945 | /* F2 0F 2D = CVTSD2SI -- convert F64 in mem/low half xmm to |
| 9946 | I32 in ireg, according to prevailing SSE rounding mode */ |
| 9947 | /* F2 0F 2C = CVTTSD2SI -- convert F64 in mem/low half xmm to |
sewardj | 0b21044 | 2005-02-23 13:28:27 +0000 | [diff] [blame] | 9948 | I32 in ireg, rounding towards zero */ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9949 | if (insn[0] == 0xF2 && insn[1] == 0x0F |
| 9950 | && (insn[2] == 0x2D || insn[2] == 0x2C)) { |
| 9951 | IRTemp rmode = newTemp(Ity_I32); |
| 9952 | IRTemp f64lo = newTemp(Ity_F64); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 9953 | Bool r2zero = toBool(insn[2] == 0x2C); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9954 | vassert(sz == 4); |
| 9955 | |
| 9956 | modrm = getIByte(delta+3); |
| 9957 | if (epartIsReg(modrm)) { |
| 9958 | delta += 3+1; |
| 9959 | assign(f64lo, getXMMRegLane64F(eregOfRM(modrm), 0)); |
| 9960 | DIP("cvt%ssd2si %s,%s\n", r2zero ? "t" : "", |
| 9961 | nameXMMReg(eregOfRM(modrm)), |
| 9962 | nameIReg(4, gregOfRM(modrm))); |
| 9963 | } else { |
| 9964 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9965 | assign(f64lo, loadLE(Ity_F64, mkexpr(addr))); |
| 9966 | delta += 3+alen; |
| 9967 | DIP("cvt%ssd2si %s,%s\n", r2zero ? "t" : "", |
| 9968 | dis_buf, |
| 9969 | nameIReg(4, gregOfRM(modrm))); |
| 9970 | } |
| 9971 | |
| 9972 | if (r2zero) { |
| 9973 | assign( rmode, mkU32((UInt)Irrm_ZERO) ); |
| 9974 | } else { |
| 9975 | assign( rmode, get_sse_roundingmode() ); |
| 9976 | } |
| 9977 | |
| 9978 | putIReg(4, gregOfRM(modrm), |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 9979 | binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo)) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 9980 | |
| 9981 | goto decode_success; |
| 9982 | } |
| 9983 | |
| 9984 | /* F2 0F 5A = CVTSD2SS -- convert F64 in mem/low half xmm to F32 in |
| 9985 | low 1/4 xmm(G), according to prevailing SSE rounding mode */ |
| 9986 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x5A) { |
| 9987 | IRTemp rmode = newTemp(Ity_I32); |
| 9988 | IRTemp f64lo = newTemp(Ity_F64); |
| 9989 | vassert(sz == 4); |
| 9990 | |
| 9991 | modrm = getIByte(delta+3); |
| 9992 | if (epartIsReg(modrm)) { |
| 9993 | delta += 3+1; |
| 9994 | assign(f64lo, getXMMRegLane64F(eregOfRM(modrm), 0)); |
| 9995 | DIP("cvtsd2ss %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 9996 | nameXMMReg(gregOfRM(modrm))); |
| 9997 | } else { |
| 9998 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 9999 | assign(f64lo, loadLE(Ity_F64, mkexpr(addr))); |
| 10000 | delta += 3+alen; |
| 10001 | DIP("cvtsd2ss %s,%s\n", dis_buf, |
| 10002 | nameXMMReg(gregOfRM(modrm))); |
| 10003 | } |
| 10004 | |
| 10005 | assign( rmode, get_sse_roundingmode() ); |
| 10006 | putXMMRegLane32F( |
| 10007 | gregOfRM(modrm), 0, |
| 10008 | binop( Iop_F64toF32, mkexpr(rmode), mkexpr(f64lo) ) |
| 10009 | ); |
| 10010 | |
| 10011 | goto decode_success; |
| 10012 | } |
| 10013 | |
| 10014 | /* F2 0F 2A = CVTSI2SD -- convert I32 in mem/ireg to F64 in low |
| 10015 | half xmm */ |
| 10016 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x2A) { |
| 10017 | IRTemp arg32 = newTemp(Ity_I32); |
| 10018 | vassert(sz == 4); |
| 10019 | |
| 10020 | modrm = getIByte(delta+3); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 10021 | if (epartIsReg(modrm)) { |
| 10022 | assign( arg32, getIReg(4, eregOfRM(modrm)) ); |
| 10023 | delta += 3+1; |
| 10024 | DIP("cvtsi2sd %s,%s\n", nameIReg(4, eregOfRM(modrm)), |
| 10025 | nameXMMReg(gregOfRM(modrm))); |
| 10026 | } else { |
| 10027 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 10028 | assign( arg32, loadLE(Ity_I32, mkexpr(addr)) ); |
| 10029 | delta += 3+alen; |
| 10030 | DIP("cvtsi2sd %s,%s\n", dis_buf, |
| 10031 | nameXMMReg(gregOfRM(modrm)) ); |
| 10032 | } |
| 10033 | |
| 10034 | putXMMRegLane64F( |
| 10035 | gregOfRM(modrm), 0, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 10036 | unop(Iop_I32StoF64, mkexpr(arg32)) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 10037 | |
| 10038 | goto decode_success; |
| 10039 | } |
| 10040 | |
| 10041 | /* F3 0F 5A = CVTSS2SD -- convert F32 in mem/low 1/4 xmm to F64 in |
| 10042 | low half xmm(G) */ |
| 10043 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5A) { |
| 10044 | IRTemp f32lo = newTemp(Ity_F32); |
| 10045 | vassert(sz == 4); |
| 10046 | |
| 10047 | modrm = getIByte(delta+3); |
| 10048 | if (epartIsReg(modrm)) { |
| 10049 | delta += 3+1; |
| 10050 | assign(f32lo, getXMMRegLane32F(eregOfRM(modrm), 0)); |
| 10051 | DIP("cvtss2sd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10052 | nameXMMReg(gregOfRM(modrm))); |
| 10053 | } else { |
| 10054 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 10055 | assign(f32lo, loadLE(Ity_F32, mkexpr(addr))); |
| 10056 | delta += 3+alen; |
| 10057 | DIP("cvtss2sd %s,%s\n", dis_buf, |
| 10058 | nameXMMReg(gregOfRM(modrm))); |
| 10059 | } |
| 10060 | |
| 10061 | putXMMRegLane64F( gregOfRM(modrm), 0, |
| 10062 | unop( Iop_F32toF64, mkexpr(f32lo) ) ); |
| 10063 | |
| 10064 | goto decode_success; |
| 10065 | } |
| 10066 | |
| 10067 | /* 66 0F E6 = CVTTPD2DQ -- convert 2 x F64 in mem/xmm to 2 x I32 in |
| 10068 | lo half xmm(G), and zero upper half, rounding towards zero */ |
| 10069 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE6) { |
| 10070 | IRTemp argV = newTemp(Ity_V128); |
| 10071 | IRTemp rmode = newTemp(Ity_I32); |
| 10072 | |
| 10073 | modrm = getIByte(delta+2); |
| 10074 | if (epartIsReg(modrm)) { |
| 10075 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 10076 | delta += 2+1; |
| 10077 | DIP("cvttpd2dq %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10078 | nameXMMReg(gregOfRM(modrm))); |
| 10079 | } else { |
| 10080 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10081 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 10082 | delta += 2+alen; |
| 10083 | DIP("cvttpd2dq %s,%s\n", dis_buf, |
| 10084 | nameXMMReg(gregOfRM(modrm)) ); |
| 10085 | } |
| 10086 | |
| 10087 | assign( rmode, mkU32((UInt)Irrm_ZERO) ); |
| 10088 | |
| 10089 | t0 = newTemp(Ity_F64); |
| 10090 | t1 = newTemp(Ity_F64); |
| 10091 | assign( t0, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10092 | unop(Iop_V128to64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 10093 | assign( t1, unop(Iop_ReinterpI64asF64, |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10094 | unop(Iop_V128HIto64, mkexpr(argV))) ); |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 10095 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 10096 | # define CVT(_t) binop( Iop_F64toI32S, \ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 10097 | mkexpr(rmode), \ |
| 10098 | mkexpr(_t) ) |
| 10099 | |
| 10100 | putXMMRegLane32( gregOfRM(modrm), 3, mkU32(0) ); |
| 10101 | putXMMRegLane32( gregOfRM(modrm), 2, mkU32(0) ); |
| 10102 | putXMMRegLane32( gregOfRM(modrm), 1, CVT(t1) ); |
| 10103 | putXMMRegLane32( gregOfRM(modrm), 0, CVT(t0) ); |
| 10104 | |
| 10105 | # undef CVT |
| 10106 | |
| 10107 | goto decode_success; |
| 10108 | } |
| 10109 | |
| 10110 | /* F3 0F 5B = CVTTPS2DQ -- convert 4 x F32 in mem/xmm to 4 x I32 in |
| 10111 | xmm(G), rounding towards zero */ |
| 10112 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5B) { |
| 10113 | IRTemp argV = newTemp(Ity_V128); |
| 10114 | IRTemp rmode = newTemp(Ity_I32); |
| 10115 | vassert(sz == 4); |
| 10116 | |
| 10117 | modrm = getIByte(delta+3); |
| 10118 | if (epartIsReg(modrm)) { |
| 10119 | assign( argV, getXMMReg(eregOfRM(modrm)) ); |
| 10120 | delta += 3+1; |
| 10121 | DIP("cvttps2dq %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10122 | nameXMMReg(gregOfRM(modrm))); |
| 10123 | } else { |
| 10124 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 10125 | assign( argV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 10126 | delta += 3+alen; |
| 10127 | DIP("cvttps2dq %s,%s\n", dis_buf, |
| 10128 | nameXMMReg(gregOfRM(modrm)) ); |
| 10129 | } |
| 10130 | |
| 10131 | assign( rmode, mkU32((UInt)Irrm_ZERO) ); |
| 10132 | breakup128to32s( argV, &t3, &t2, &t1, &t0 ); |
| 10133 | |
| 10134 | /* This is less than ideal. If it turns out to be a performance |
| 10135 | bottleneck it can be improved. */ |
| 10136 | # define CVT(_t) \ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 10137 | binop( Iop_F64toI32S, \ |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 10138 | mkexpr(rmode), \ |
| 10139 | unop( Iop_F32toF64, \ |
| 10140 | unop( Iop_ReinterpI32asF32, mkexpr(_t))) ) |
| 10141 | |
| 10142 | putXMMRegLane32( gregOfRM(modrm), 3, CVT(t3) ); |
| 10143 | putXMMRegLane32( gregOfRM(modrm), 2, CVT(t2) ); |
| 10144 | putXMMRegLane32( gregOfRM(modrm), 1, CVT(t1) ); |
| 10145 | putXMMRegLane32( gregOfRM(modrm), 0, CVT(t0) ); |
| 10146 | |
| 10147 | # undef CVT |
| 10148 | |
| 10149 | goto decode_success; |
| 10150 | } |
| 10151 | |
| 10152 | /* 66 0F 5E = DIVPD -- div 64Fx2 from R/M to R */ |
| 10153 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5E) { |
| 10154 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "divpd", Iop_Div64Fx2 ); |
| 10155 | goto decode_success; |
| 10156 | } |
| 10157 | |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10158 | /* F2 0F 5E = DIVSD -- div 64F0x2 from R/M to R */ |
| 10159 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x5E) { |
| 10160 | vassert(sz == 4); |
| 10161 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "divsd", Iop_Div64F0x2 ); |
| 10162 | goto decode_success; |
| 10163 | } |
| 10164 | |
| 10165 | /* 0F AE /5 = LFENCE -- flush pending operations to memory */ |
| 10166 | /* 0F AE /6 = MFENCE -- flush pending operations to memory */ |
| 10167 | if (insn[0] == 0x0F && insn[1] == 0xAE |
| 10168 | && epartIsReg(insn[2]) |
| 10169 | && (gregOfRM(insn[2]) == 5 || gregOfRM(insn[2]) == 6)) { |
| 10170 | vassert(sz == 4); |
| 10171 | delta += 3; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 10172 | /* Insert a memory fence. It's sometimes important that these |
| 10173 | are carried through to the generated code. */ |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 10174 | stmt( IRStmt_MBE(Imbe_Fence) ); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10175 | DIP("%sfence\n", gregOfRM(insn[2])==5 ? "l" : "m"); |
| 10176 | goto decode_success; |
| 10177 | } |
| 10178 | |
| 10179 | /* 66 0F 5F = MAXPD -- max 64Fx2 from R/M to R */ |
| 10180 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5F) { |
| 10181 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "maxpd", Iop_Max64Fx2 ); |
| 10182 | goto decode_success; |
| 10183 | } |
| 10184 | |
| 10185 | /* F2 0F 5F = MAXSD -- max 64F0x2 from R/M to R */ |
| 10186 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x5F) { |
| 10187 | vassert(sz == 4); |
| 10188 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "maxsd", Iop_Max64F0x2 ); |
| 10189 | goto decode_success; |
| 10190 | } |
| 10191 | |
| 10192 | /* 66 0F 5D = MINPD -- min 64Fx2 from R/M to R */ |
| 10193 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5D) { |
| 10194 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "minpd", Iop_Min64Fx2 ); |
| 10195 | goto decode_success; |
| 10196 | } |
| 10197 | |
| 10198 | /* F2 0F 5D = MINSD -- min 64F0x2 from R/M to R */ |
| 10199 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x5D) { |
| 10200 | vassert(sz == 4); |
| 10201 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "minsd", Iop_Min64F0x2 ); |
| 10202 | goto decode_success; |
| 10203 | } |
| 10204 | |
| 10205 | /* 66 0F 28 = MOVAPD -- move from E (mem or xmm) to G (xmm). */ |
| 10206 | /* 66 0F 10 = MOVUPD -- move from E (mem or xmm) to G (xmm). */ |
| 10207 | /* 66 0F 6F = MOVDQA -- move from E (mem or xmm) to G (xmm). */ |
| 10208 | if (sz == 2 && insn[0] == 0x0F |
| 10209 | && (insn[1] == 0x28 || insn[1] == 0x10 || insn[1] == 0x6F)) { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 10210 | const HChar* wot = insn[1]==0x28 ? "apd" : |
| 10211 | insn[1]==0x10 ? "upd" : "dqa"; |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10212 | modrm = getIByte(delta+2); |
| 10213 | if (epartIsReg(modrm)) { |
| 10214 | putXMMReg( gregOfRM(modrm), |
| 10215 | getXMMReg( eregOfRM(modrm) )); |
| 10216 | DIP("mov%s %s,%s\n", wot, nameXMMReg(eregOfRM(modrm)), |
| 10217 | nameXMMReg(gregOfRM(modrm))); |
| 10218 | delta += 2+1; |
| 10219 | } else { |
| 10220 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 10221 | if (insn[1] == 0x28/*movapd*/ || insn[1] == 0x6F/*movdqa*/) |
| 10222 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10223 | putXMMReg( gregOfRM(modrm), |
| 10224 | loadLE(Ity_V128, mkexpr(addr)) ); |
| 10225 | DIP("mov%s %s,%s\n", wot, dis_buf, |
| 10226 | nameXMMReg(gregOfRM(modrm))); |
| 10227 | delta += 2+alen; |
| 10228 | } |
| 10229 | goto decode_success; |
| 10230 | } |
| 10231 | |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10232 | /* 66 0F 29 = MOVAPD -- move from G (xmm) to E (mem or xmm). */ |
sewardj | 1c31877 | 2005-03-19 14:27:04 +0000 | [diff] [blame] | 10233 | /* 66 0F 11 = MOVUPD -- move from G (xmm) to E (mem or xmm). */ |
| 10234 | if (sz == 2 && insn[0] == 0x0F |
| 10235 | && (insn[1] == 0x29 || insn[1] == 0x11)) { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 10236 | const HChar* wot = insn[1]==0x29 ? "apd" : "upd"; |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10237 | modrm = getIByte(delta+2); |
| 10238 | if (epartIsReg(modrm)) { |
| 10239 | /* fall through; awaiting test case */ |
| 10240 | } else { |
| 10241 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 10242 | if (insn[1] == 0x29/*movapd*/) |
| 10243 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10244 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
sewardj | 1c31877 | 2005-03-19 14:27:04 +0000 | [diff] [blame] | 10245 | DIP("mov%s %s,%s\n", wot, nameXMMReg(gregOfRM(modrm)), |
| 10246 | dis_buf ); |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10247 | delta += 2+alen; |
| 10248 | goto decode_success; |
| 10249 | } |
| 10250 | } |
| 10251 | |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10252 | /* 66 0F 6E = MOVD from r/m32 to xmm, zeroing high 3/4 of xmm. */ |
| 10253 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x6E) { |
| 10254 | modrm = getIByte(delta+2); |
| 10255 | if (epartIsReg(modrm)) { |
| 10256 | delta += 2+1; |
| 10257 | putXMMReg( |
| 10258 | gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10259 | unop( Iop_32UtoV128, getIReg(4, eregOfRM(modrm)) ) |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10260 | ); |
| 10261 | DIP("movd %s, %s\n", |
| 10262 | nameIReg(4,eregOfRM(modrm)), nameXMMReg(gregOfRM(modrm))); |
| 10263 | } else { |
| 10264 | addr = disAMode( &alen, sorb, delta+2, dis_buf ); |
| 10265 | delta += 2+alen; |
| 10266 | putXMMReg( |
| 10267 | gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10268 | unop( Iop_32UtoV128,loadLE(Ity_I32, mkexpr(addr)) ) |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10269 | ); |
| 10270 | DIP("movd %s, %s\n", dis_buf, nameXMMReg(gregOfRM(modrm))); |
| 10271 | } |
| 10272 | goto decode_success; |
| 10273 | } |
| 10274 | |
| 10275 | /* 66 0F 7E = MOVD from xmm low 1/4 to r/m32. */ |
| 10276 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x7E) { |
| 10277 | modrm = getIByte(delta+2); |
| 10278 | if (epartIsReg(modrm)) { |
| 10279 | delta += 2+1; |
| 10280 | putIReg( 4, eregOfRM(modrm), |
| 10281 | getXMMRegLane32(gregOfRM(modrm), 0) ); |
| 10282 | DIP("movd %s, %s\n", |
| 10283 | nameXMMReg(gregOfRM(modrm)), nameIReg(4,eregOfRM(modrm))); |
| 10284 | } else { |
| 10285 | addr = disAMode( &alen, sorb, delta+2, dis_buf ); |
| 10286 | delta += 2+alen; |
| 10287 | storeLE( mkexpr(addr), |
| 10288 | getXMMRegLane32(gregOfRM(modrm), 0) ); |
| 10289 | DIP("movd %s, %s\n", nameXMMReg(gregOfRM(modrm)), dis_buf); |
| 10290 | } |
| 10291 | goto decode_success; |
| 10292 | } |
| 10293 | |
| 10294 | /* 66 0F 7F = MOVDQA -- move from G (xmm) to E (mem or xmm). */ |
| 10295 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x7F) { |
| 10296 | modrm = getIByte(delta+2); |
| 10297 | if (epartIsReg(modrm)) { |
| 10298 | delta += 2+1; |
| 10299 | putXMMReg( eregOfRM(modrm), |
| 10300 | getXMMReg(gregOfRM(modrm)) ); |
| 10301 | DIP("movdqa %s, %s\n", nameXMMReg(gregOfRM(modrm)), |
| 10302 | nameXMMReg(eregOfRM(modrm))); |
| 10303 | } else { |
| 10304 | addr = disAMode( &alen, sorb, delta+2, dis_buf ); |
| 10305 | delta += 2+alen; |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 10306 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10307 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
| 10308 | DIP("movdqa %s, %s\n", nameXMMReg(gregOfRM(modrm)), dis_buf); |
| 10309 | } |
| 10310 | goto decode_success; |
| 10311 | } |
| 10312 | |
| 10313 | /* F3 0F 6F = MOVDQU -- move from E (mem or xmm) to G (xmm). */ |
| 10314 | /* Unfortunately can't simply use the MOVDQA case since the |
| 10315 | prefix lengths are different (66 vs F3) */ |
| 10316 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x6F) { |
| 10317 | vassert(sz == 4); |
| 10318 | modrm = getIByte(delta+3); |
| 10319 | if (epartIsReg(modrm)) { |
| 10320 | putXMMReg( gregOfRM(modrm), |
| 10321 | getXMMReg( eregOfRM(modrm) )); |
| 10322 | DIP("movdqu %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10323 | nameXMMReg(gregOfRM(modrm))); |
| 10324 | delta += 3+1; |
| 10325 | } else { |
| 10326 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 10327 | putXMMReg( gregOfRM(modrm), |
| 10328 | loadLE(Ity_V128, mkexpr(addr)) ); |
| 10329 | DIP("movdqu %s,%s\n", dis_buf, |
| 10330 | nameXMMReg(gregOfRM(modrm))); |
| 10331 | delta += 3+alen; |
| 10332 | } |
| 10333 | goto decode_success; |
| 10334 | } |
| 10335 | |
| 10336 | /* F3 0F 7F = MOVDQU -- move from G (xmm) to E (mem or xmm). */ |
| 10337 | /* Unfortunately can't simply use the MOVDQA case since the |
| 10338 | prefix lengths are different (66 vs F3) */ |
| 10339 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x7F) { |
| 10340 | vassert(sz == 4); |
| 10341 | modrm = getIByte(delta+3); |
| 10342 | if (epartIsReg(modrm)) { |
| 10343 | delta += 3+1; |
| 10344 | putXMMReg( eregOfRM(modrm), |
| 10345 | getXMMReg(gregOfRM(modrm)) ); |
| 10346 | DIP("movdqu %s, %s\n", nameXMMReg(gregOfRM(modrm)), |
| 10347 | nameXMMReg(eregOfRM(modrm))); |
| 10348 | } else { |
| 10349 | addr = disAMode( &alen, sorb, delta+3, dis_buf ); |
| 10350 | delta += 3+alen; |
| 10351 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
| 10352 | DIP("movdqu %s, %s\n", nameXMMReg(gregOfRM(modrm)), dis_buf); |
| 10353 | } |
| 10354 | goto decode_success; |
| 10355 | } |
| 10356 | |
| 10357 | /* F2 0F D6 = MOVDQ2Q -- move from E (lo half xmm, not mem) to G (mmx). */ |
| 10358 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xD6) { |
| 10359 | vassert(sz == 4); |
| 10360 | modrm = getIByte(delta+3); |
| 10361 | if (epartIsReg(modrm)) { |
| 10362 | do_MMX_preamble(); |
| 10363 | putMMXReg( gregOfRM(modrm), |
| 10364 | getXMMRegLane64( eregOfRM(modrm), 0 )); |
| 10365 | DIP("movdq2q %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10366 | nameMMXReg(gregOfRM(modrm))); |
| 10367 | delta += 3+1; |
| 10368 | goto decode_success; |
| 10369 | } else { |
| 10370 | /* fall through, apparently no mem case for this insn */ |
| 10371 | } |
| 10372 | } |
| 10373 | |
| 10374 | /* 66 0F 16 = MOVHPD -- move from mem to high half of XMM. */ |
| 10375 | /* These seems identical to MOVHPS. This instruction encoding is |
| 10376 | completely crazy. */ |
| 10377 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x16) { |
| 10378 | modrm = getIByte(delta+2); |
| 10379 | if (epartIsReg(modrm)) { |
| 10380 | /* fall through; apparently reg-reg is not possible */ |
| 10381 | } else { |
| 10382 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10383 | delta += 2+alen; |
| 10384 | putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/, |
| 10385 | loadLE(Ity_I64, mkexpr(addr)) ); |
| 10386 | DIP("movhpd %s,%s\n", dis_buf, |
| 10387 | nameXMMReg( gregOfRM(modrm) )); |
| 10388 | goto decode_success; |
| 10389 | } |
| 10390 | } |
| 10391 | |
| 10392 | /* 66 0F 17 = MOVHPD -- move from high half of XMM to mem. */ |
| 10393 | /* Again, this seems identical to MOVHPS. */ |
| 10394 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x17) { |
| 10395 | if (!epartIsReg(insn[2])) { |
| 10396 | delta += 2; |
| 10397 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 10398 | delta += alen; |
| 10399 | storeLE( mkexpr(addr), |
| 10400 | getXMMRegLane64( gregOfRM(insn[2]), |
| 10401 | 1/*upper lane*/ ) ); |
| 10402 | DIP("movhpd %s,%s\n", nameXMMReg( gregOfRM(insn[2]) ), |
| 10403 | dis_buf); |
| 10404 | goto decode_success; |
| 10405 | } |
| 10406 | /* else fall through */ |
| 10407 | } |
| 10408 | |
| 10409 | /* 66 0F 12 = MOVLPD -- move from mem to low half of XMM. */ |
| 10410 | /* Identical to MOVLPS ? */ |
| 10411 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x12) { |
| 10412 | modrm = getIByte(delta+2); |
| 10413 | if (epartIsReg(modrm)) { |
| 10414 | /* fall through; apparently reg-reg is not possible */ |
| 10415 | } else { |
| 10416 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10417 | delta += 2+alen; |
| 10418 | putXMMRegLane64( gregOfRM(modrm), 0/*lower lane*/, |
| 10419 | loadLE(Ity_I64, mkexpr(addr)) ); |
| 10420 | DIP("movlpd %s, %s\n", |
| 10421 | dis_buf, nameXMMReg( gregOfRM(modrm) )); |
| 10422 | goto decode_success; |
| 10423 | } |
| 10424 | } |
| 10425 | |
| 10426 | /* 66 0F 13 = MOVLPD -- move from low half of XMM to mem. */ |
| 10427 | /* Identical to MOVLPS ? */ |
| 10428 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x13) { |
| 10429 | if (!epartIsReg(insn[2])) { |
| 10430 | delta += 2; |
| 10431 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 10432 | delta += alen; |
| 10433 | storeLE( mkexpr(addr), |
| 10434 | getXMMRegLane64( gregOfRM(insn[2]), |
| 10435 | 0/*lower lane*/ ) ); |
| 10436 | DIP("movlpd %s, %s\n", nameXMMReg( gregOfRM(insn[2]) ), |
| 10437 | dis_buf); |
| 10438 | goto decode_success; |
| 10439 | } |
| 10440 | /* else fall through */ |
| 10441 | } |
| 10442 | |
| 10443 | /* 66 0F 50 = MOVMSKPD - move 2 sign bits from 2 x F64 in xmm(E) to |
| 10444 | 2 lowest bits of ireg(G) */ |
| 10445 | if (insn[0] == 0x0F && insn[1] == 0x50) { |
| 10446 | modrm = getIByte(delta+2); |
| 10447 | if (sz == 2 && epartIsReg(modrm)) { |
| 10448 | Int src; |
| 10449 | t0 = newTemp(Ity_I32); |
| 10450 | t1 = newTemp(Ity_I32); |
| 10451 | delta += 2+1; |
| 10452 | src = eregOfRM(modrm); |
| 10453 | assign( t0, binop( Iop_And32, |
| 10454 | binop(Iop_Shr32, getXMMRegLane32(src,1), mkU8(31)), |
| 10455 | mkU32(1) )); |
| 10456 | assign( t1, binop( Iop_And32, |
| 10457 | binop(Iop_Shr32, getXMMRegLane32(src,3), mkU8(30)), |
| 10458 | mkU32(2) )); |
| 10459 | putIReg(4, gregOfRM(modrm), |
| 10460 | binop(Iop_Or32, mkexpr(t0), mkexpr(t1)) |
| 10461 | ); |
| 10462 | DIP("movmskpd %s,%s\n", nameXMMReg(src), |
| 10463 | nameIReg(4, gregOfRM(modrm))); |
| 10464 | goto decode_success; |
| 10465 | } |
| 10466 | /* else fall through */ |
| 10467 | } |
| 10468 | |
sewardj | d71ba83 | 2006-12-27 01:15:29 +0000 | [diff] [blame] | 10469 | /* 66 0F F7 = MASKMOVDQU -- store selected bytes of double quadword */ |
| 10470 | if (insn[0] == 0x0F && insn[1] == 0xF7) { |
| 10471 | modrm = getIByte(delta+2); |
| 10472 | if (sz == 2 && epartIsReg(modrm)) { |
| 10473 | IRTemp regD = newTemp(Ity_V128); |
| 10474 | IRTemp mask = newTemp(Ity_V128); |
| 10475 | IRTemp olddata = newTemp(Ity_V128); |
| 10476 | IRTemp newdata = newTemp(Ity_V128); |
| 10477 | addr = newTemp(Ity_I32); |
| 10478 | |
| 10479 | assign( addr, handleSegOverride( sorb, getIReg(4, R_EDI) )); |
| 10480 | assign( regD, getXMMReg( gregOfRM(modrm) )); |
| 10481 | |
| 10482 | /* Unfortunately can't do the obvious thing with SarN8x16 |
| 10483 | here since that can't be re-emitted as SSE2 code - no such |
| 10484 | insn. */ |
| 10485 | assign( |
| 10486 | mask, |
| 10487 | binop(Iop_64HLtoV128, |
| 10488 | binop(Iop_SarN8x8, |
| 10489 | getXMMRegLane64( eregOfRM(modrm), 1 ), |
| 10490 | mkU8(7) ), |
| 10491 | binop(Iop_SarN8x8, |
| 10492 | getXMMRegLane64( eregOfRM(modrm), 0 ), |
| 10493 | mkU8(7) ) )); |
| 10494 | assign( olddata, loadLE( Ity_V128, mkexpr(addr) )); |
| 10495 | assign( newdata, |
| 10496 | binop(Iop_OrV128, |
| 10497 | binop(Iop_AndV128, |
| 10498 | mkexpr(regD), |
| 10499 | mkexpr(mask) ), |
| 10500 | binop(Iop_AndV128, |
| 10501 | mkexpr(olddata), |
| 10502 | unop(Iop_NotV128, mkexpr(mask)))) ); |
| 10503 | storeLE( mkexpr(addr), mkexpr(newdata) ); |
| 10504 | |
| 10505 | delta += 2+1; |
| 10506 | DIP("maskmovdqu %s,%s\n", nameXMMReg( eregOfRM(modrm) ), |
| 10507 | nameXMMReg( gregOfRM(modrm) ) ); |
| 10508 | goto decode_success; |
| 10509 | } |
| 10510 | /* else fall through */ |
| 10511 | } |
| 10512 | |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10513 | /* 66 0F E7 = MOVNTDQ -- for us, just a plain SSE store. */ |
| 10514 | if (insn[0] == 0x0F && insn[1] == 0xE7) { |
| 10515 | modrm = getIByte(delta+2); |
| 10516 | if (sz == 2 && !epartIsReg(modrm)) { |
| 10517 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 10518 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10519 | storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); |
| 10520 | DIP("movntdq %s,%s\n", dis_buf, |
| 10521 | nameXMMReg(gregOfRM(modrm))); |
| 10522 | delta += 2+alen; |
| 10523 | goto decode_success; |
| 10524 | } |
| 10525 | /* else fall through */ |
| 10526 | } |
| 10527 | |
| 10528 | /* 0F C3 = MOVNTI -- for us, just a plain ireg store. */ |
| 10529 | if (insn[0] == 0x0F && insn[1] == 0xC3) { |
| 10530 | vassert(sz == 4); |
| 10531 | modrm = getIByte(delta+2); |
| 10532 | if (!epartIsReg(modrm)) { |
| 10533 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10534 | storeLE( mkexpr(addr), getIReg(4, gregOfRM(modrm)) ); |
| 10535 | DIP("movnti %s,%s\n", dis_buf, |
| 10536 | nameIReg(4, gregOfRM(modrm))); |
| 10537 | delta += 2+alen; |
| 10538 | goto decode_success; |
| 10539 | } |
| 10540 | /* else fall through */ |
| 10541 | } |
| 10542 | |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10543 | /* 66 0F D6 = MOVQ -- move 64 bits from G (lo half xmm) to E (mem |
| 10544 | or lo half xmm). */ |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 10545 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD6) { |
| 10546 | modrm = getIByte(delta+2); |
| 10547 | if (epartIsReg(modrm)) { |
| 10548 | /* fall through, awaiting test case */ |
sewardj | 6d7ccd5 | 2005-05-14 02:04:12 +0000 | [diff] [blame] | 10549 | /* dst: lo half copied, hi half zeroed */ |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 10550 | } else { |
| 10551 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10552 | storeLE( mkexpr(addr), |
| 10553 | getXMMRegLane64( gregOfRM(modrm), 0 )); |
| 10554 | DIP("movq %s,%s\n", nameXMMReg(gregOfRM(modrm)), dis_buf ); |
| 10555 | delta += 2+alen; |
| 10556 | goto decode_success; |
| 10557 | } |
| 10558 | } |
| 10559 | |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10560 | /* F3 0F D6 = MOVQ2DQ -- move from E (mmx) to G (lo half xmm, zero |
| 10561 | hi half). */ |
| 10562 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xD6) { |
| 10563 | vassert(sz == 4); |
| 10564 | modrm = getIByte(delta+3); |
| 10565 | if (epartIsReg(modrm)) { |
| 10566 | do_MMX_preamble(); |
| 10567 | putXMMReg( gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10568 | unop(Iop_64UtoV128, getMMXReg( eregOfRM(modrm) )) ); |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10569 | DIP("movq2dq %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 10570 | nameXMMReg(gregOfRM(modrm))); |
| 10571 | delta += 3+1; |
| 10572 | goto decode_success; |
| 10573 | } else { |
| 10574 | /* fall through, apparently no mem case for this insn */ |
| 10575 | } |
| 10576 | } |
| 10577 | |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10578 | /* F3 0F 7E = MOVQ -- move 64 bits from E (mem or lo half xmm) to |
sewardj | 6d7ccd5 | 2005-05-14 02:04:12 +0000 | [diff] [blame] | 10579 | G (lo half xmm). Upper half of G is zeroed out. */ |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10580 | /* F2 0F 10 = MOVSD -- move 64 bits from E (mem or lo half xmm) to |
| 10581 | G (lo half xmm). If E is mem, upper half of G is zeroed out. |
sewardj | 6d7ccd5 | 2005-05-14 02:04:12 +0000 | [diff] [blame] | 10582 | If E is reg, upper half of G is unchanged. */ |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 10583 | if ((insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x10) |
| 10584 | || (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x7E)) { |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10585 | vassert(sz == 4); |
| 10586 | modrm = getIByte(delta+3); |
| 10587 | if (epartIsReg(modrm)) { |
| 10588 | putXMMRegLane64( gregOfRM(modrm), 0, |
| 10589 | getXMMRegLane64( eregOfRM(modrm), 0 )); |
sewardj | 6d7ccd5 | 2005-05-14 02:04:12 +0000 | [diff] [blame] | 10590 | if (insn[0] == 0xF3/*MOVQ*/) { |
| 10591 | /* zero bits 127:64 */ |
| 10592 | putXMMRegLane64( gregOfRM(modrm), 1, mkU64(0) ); |
| 10593 | } |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10594 | DIP("movsd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 10595 | nameXMMReg(gregOfRM(modrm))); |
| 10596 | delta += 3+1; |
| 10597 | } else { |
| 10598 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
sewardj | ad50db0 | 2005-04-06 01:45:44 +0000 | [diff] [blame] | 10599 | /* zero bits 127:64 */ |
sewardj | 5bf1fd4 | 2005-04-06 01:11:08 +0000 | [diff] [blame] | 10600 | putXMMRegLane64( gregOfRM(modrm), 1, mkU64(0) ); |
sewardj | ad50db0 | 2005-04-06 01:45:44 +0000 | [diff] [blame] | 10601 | /* write bits 63:0 */ |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10602 | putXMMRegLane64( gregOfRM(modrm), 0, |
| 10603 | loadLE(Ity_I64, mkexpr(addr)) ); |
| 10604 | DIP("movsd %s,%s\n", dis_buf, |
| 10605 | nameXMMReg(gregOfRM(modrm))); |
| 10606 | delta += 3+alen; |
| 10607 | } |
| 10608 | goto decode_success; |
| 10609 | } |
| 10610 | |
| 10611 | /* F2 0F 11 = MOVSD -- move 64 bits from G (lo half xmm) to E (mem |
| 10612 | or lo half xmm). */ |
| 10613 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x11) { |
| 10614 | vassert(sz == 4); |
| 10615 | modrm = getIByte(delta+3); |
| 10616 | if (epartIsReg(modrm)) { |
sewardj | b7ba04f | 2008-11-17 20:25:37 +0000 | [diff] [blame] | 10617 | putXMMRegLane64( eregOfRM(modrm), 0, |
| 10618 | getXMMRegLane64( gregOfRM(modrm), 0 )); |
| 10619 | DIP("movsd %s,%s\n", nameXMMReg(gregOfRM(modrm)), |
| 10620 | nameXMMReg(eregOfRM(modrm))); |
| 10621 | delta += 3+1; |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10622 | } else { |
| 10623 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 10624 | storeLE( mkexpr(addr), |
sewardj | 519d66f | 2004-12-15 11:57:58 +0000 | [diff] [blame] | 10625 | getXMMRegLane64(gregOfRM(modrm), 0) ); |
| 10626 | DIP("movsd %s,%s\n", nameXMMReg(gregOfRM(modrm)), |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10627 | dis_buf); |
| 10628 | delta += 3+alen; |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10629 | } |
sewardj | b7ba04f | 2008-11-17 20:25:37 +0000 | [diff] [blame] | 10630 | goto decode_success; |
sewardj | c2feffc | 2004-12-08 12:31:22 +0000 | [diff] [blame] | 10631 | } |
sewardj | fd22645 | 2004-12-07 19:02:18 +0000 | [diff] [blame] | 10632 | |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10633 | /* 66 0F 59 = MULPD -- mul 64Fx2 from R/M to R */ |
| 10634 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x59) { |
| 10635 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "mulpd", Iop_Mul64Fx2 ); |
| 10636 | goto decode_success; |
| 10637 | } |
| 10638 | |
| 10639 | /* F2 0F 59 = MULSD -- mul 64F0x2 from R/M to R */ |
| 10640 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x59) { |
| 10641 | vassert(sz == 4); |
| 10642 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "mulsd", Iop_Mul64F0x2 ); |
| 10643 | goto decode_success; |
| 10644 | } |
| 10645 | |
| 10646 | /* 66 0F 56 = ORPD -- G = G and E */ |
| 10647 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x56) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10648 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "orpd", Iop_OrV128 ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10649 | goto decode_success; |
| 10650 | } |
| 10651 | |
| 10652 | /* 66 0F C6 /r ib = SHUFPD -- shuffle packed F64s */ |
| 10653 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xC6) { |
| 10654 | Int select; |
| 10655 | IRTemp sV = newTemp(Ity_V128); |
| 10656 | IRTemp dV = newTemp(Ity_V128); |
| 10657 | IRTemp s1 = newTemp(Ity_I64); |
| 10658 | IRTemp s0 = newTemp(Ity_I64); |
| 10659 | IRTemp d1 = newTemp(Ity_I64); |
| 10660 | IRTemp d0 = newTemp(Ity_I64); |
| 10661 | |
| 10662 | modrm = insn[2]; |
| 10663 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 10664 | |
| 10665 | if (epartIsReg(modrm)) { |
| 10666 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 10667 | select = (Int)insn[3]; |
| 10668 | delta += 2+2; |
| 10669 | DIP("shufpd $%d,%s,%s\n", select, |
| 10670 | nameXMMReg(eregOfRM(modrm)), |
| 10671 | nameXMMReg(gregOfRM(modrm))); |
| 10672 | } else { |
| 10673 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10674 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 10675 | select = (Int)insn[2+alen]; |
| 10676 | delta += 3+alen; |
| 10677 | DIP("shufpd $%d,%s,%s\n", select, |
| 10678 | dis_buf, |
| 10679 | nameXMMReg(gregOfRM(modrm))); |
| 10680 | } |
| 10681 | |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10682 | assign( d1, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 10683 | assign( d0, unop(Iop_V128to64, mkexpr(dV)) ); |
| 10684 | assign( s1, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 10685 | assign( s0, unop(Iop_V128to64, mkexpr(sV)) ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10686 | |
| 10687 | # define SELD(n) mkexpr((n)==0 ? d0 : d1) |
| 10688 | # define SELS(n) mkexpr((n)==0 ? s0 : s1) |
| 10689 | |
| 10690 | putXMMReg( |
| 10691 | gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10692 | binop(Iop_64HLtoV128, SELS((select>>1)&1), SELD((select>>0)&1) ) |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10693 | ); |
| 10694 | |
| 10695 | # undef SELD |
| 10696 | # undef SELS |
| 10697 | |
| 10698 | goto decode_success; |
| 10699 | } |
| 10700 | |
| 10701 | /* 66 0F 51 = SQRTPD -- approx sqrt 64Fx2 from R/M to R */ |
| 10702 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x51) { |
| 10703 | delta = dis_SSE_E_to_G_unary_all( sorb, delta+2, |
| 10704 | "sqrtpd", Iop_Sqrt64Fx2 ); |
| 10705 | goto decode_success; |
| 10706 | } |
| 10707 | |
| 10708 | /* F2 0F 51 = SQRTSD -- approx sqrt 64F0x2 from R/M to R */ |
| 10709 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x51) { |
| 10710 | vassert(sz == 4); |
| 10711 | delta = dis_SSE_E_to_G_unary_lo64( sorb, delta+3, |
| 10712 | "sqrtsd", Iop_Sqrt64F0x2 ); |
| 10713 | goto decode_success; |
| 10714 | } |
| 10715 | |
| 10716 | /* 66 0F 5C = SUBPD -- sub 64Fx2 from R/M to R */ |
| 10717 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x5C) { |
| 10718 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "subpd", Iop_Sub64Fx2 ); |
| 10719 | goto decode_success; |
| 10720 | } |
| 10721 | |
| 10722 | /* F2 0F 5C = SUBSD -- sub 64F0x2 from R/M to R */ |
| 10723 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x5C) { |
| 10724 | vassert(sz == 4); |
| 10725 | delta = dis_SSE_E_to_G_lo64( sorb, delta+3, "subsd", Iop_Sub64F0x2 ); |
| 10726 | goto decode_success; |
| 10727 | } |
| 10728 | |
| 10729 | /* 66 0F 15 = UNPCKHPD -- unpack and interleave high part F64s */ |
| 10730 | /* 66 0F 14 = UNPCKLPD -- unpack and interleave low part F64s */ |
| 10731 | /* These just appear to be special cases of SHUFPS */ |
| 10732 | if (sz == 2 && insn[0] == 0x0F && (insn[1] == 0x15 || insn[1] == 0x14)) { |
| 10733 | IRTemp s1 = newTemp(Ity_I64); |
| 10734 | IRTemp s0 = newTemp(Ity_I64); |
| 10735 | IRTemp d1 = newTemp(Ity_I64); |
| 10736 | IRTemp d0 = newTemp(Ity_I64); |
| 10737 | IRTemp sV = newTemp(Ity_V128); |
| 10738 | IRTemp dV = newTemp(Ity_V128); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 10739 | Bool hi = toBool(insn[1] == 0x15); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10740 | |
| 10741 | modrm = insn[2]; |
| 10742 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 10743 | |
| 10744 | if (epartIsReg(modrm)) { |
| 10745 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 10746 | delta += 2+1; |
| 10747 | DIP("unpck%sps %s,%s\n", hi ? "h" : "l", |
| 10748 | nameXMMReg(eregOfRM(modrm)), |
| 10749 | nameXMMReg(gregOfRM(modrm))); |
| 10750 | } else { |
| 10751 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10752 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 10753 | delta += 2+alen; |
| 10754 | DIP("unpck%sps %s,%s\n", hi ? "h" : "l", |
| 10755 | dis_buf, |
| 10756 | nameXMMReg(gregOfRM(modrm))); |
| 10757 | } |
| 10758 | |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10759 | assign( d1, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 10760 | assign( d0, unop(Iop_V128to64, mkexpr(dV)) ); |
| 10761 | assign( s1, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 10762 | assign( s0, unop(Iop_V128to64, mkexpr(sV)) ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10763 | |
| 10764 | if (hi) { |
| 10765 | putXMMReg( gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10766 | binop(Iop_64HLtoV128, mkexpr(s1), mkexpr(d1)) ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10767 | } else { |
| 10768 | putXMMReg( gregOfRM(modrm), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10769 | binop(Iop_64HLtoV128, mkexpr(s0), mkexpr(d0)) ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10770 | } |
| 10771 | |
| 10772 | goto decode_success; |
| 10773 | } |
| 10774 | |
| 10775 | /* 66 0F 57 = XORPD -- G = G and E */ |
| 10776 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x57) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10777 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "xorpd", Iop_XorV128 ); |
sewardj | 008754b | 2004-12-08 14:37:10 +0000 | [diff] [blame] | 10778 | goto decode_success; |
| 10779 | } |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 10780 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10781 | /* 66 0F 6B = PACKSSDW */ |
| 10782 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x6B) { |
| 10783 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
sewardj | c9bff7d | 2011-06-15 15:09:37 +0000 | [diff] [blame] | 10784 | "packssdw", |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 10785 | Iop_QNarrowBin32Sto16Sx8, True ); |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10786 | goto decode_success; |
| 10787 | } |
| 10788 | |
| 10789 | /* 66 0F 63 = PACKSSWB */ |
| 10790 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x63) { |
| 10791 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
sewardj | c9bff7d | 2011-06-15 15:09:37 +0000 | [diff] [blame] | 10792 | "packsswb", |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 10793 | Iop_QNarrowBin16Sto8Sx16, True ); |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10794 | goto decode_success; |
| 10795 | } |
| 10796 | |
| 10797 | /* 66 0F 67 = PACKUSWB */ |
| 10798 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x67) { |
| 10799 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
sewardj | c9bff7d | 2011-06-15 15:09:37 +0000 | [diff] [blame] | 10800 | "packuswb", |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 10801 | Iop_QNarrowBin16Sto8Ux16, True ); |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10802 | goto decode_success; |
| 10803 | } |
| 10804 | |
| 10805 | /* 66 0F FC = PADDB */ |
| 10806 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xFC) { |
| 10807 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10808 | "paddb", Iop_Add8x16, False ); |
| 10809 | goto decode_success; |
| 10810 | } |
| 10811 | |
| 10812 | /* 66 0F FE = PADDD */ |
| 10813 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xFE) { |
| 10814 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10815 | "paddd", Iop_Add32x4, False ); |
| 10816 | goto decode_success; |
| 10817 | } |
| 10818 | |
| 10819 | /* ***--- this is an MMX class insn introduced in SSE2 ---*** */ |
| 10820 | /* 0F D4 = PADDQ -- add 64x1 */ |
| 10821 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xD4) { |
| 10822 | do_MMX_preamble(); |
| 10823 | delta = dis_MMXop_regmem_to_reg ( |
| 10824 | sorb, delta+2, insn[1], "paddq", False ); |
| 10825 | goto decode_success; |
| 10826 | } |
| 10827 | |
| 10828 | /* 66 0F D4 = PADDQ */ |
| 10829 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD4) { |
| 10830 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10831 | "paddq", Iop_Add64x2, False ); |
| 10832 | goto decode_success; |
| 10833 | } |
| 10834 | |
| 10835 | /* 66 0F FD = PADDW */ |
| 10836 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xFD) { |
| 10837 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10838 | "paddw", Iop_Add16x8, False ); |
| 10839 | goto decode_success; |
| 10840 | } |
| 10841 | |
| 10842 | /* 66 0F EC = PADDSB */ |
| 10843 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xEC) { |
| 10844 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10845 | "paddsb", Iop_QAdd8Sx16, False ); |
| 10846 | goto decode_success; |
| 10847 | } |
| 10848 | |
| 10849 | /* 66 0F ED = PADDSW */ |
| 10850 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xED) { |
| 10851 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10852 | "paddsw", Iop_QAdd16Sx8, False ); |
| 10853 | goto decode_success; |
| 10854 | } |
| 10855 | |
| 10856 | /* 66 0F DC = PADDUSB */ |
| 10857 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDC) { |
| 10858 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10859 | "paddusb", Iop_QAdd8Ux16, False ); |
| 10860 | goto decode_success; |
| 10861 | } |
| 10862 | |
| 10863 | /* 66 0F DD = PADDUSW */ |
| 10864 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDD) { |
| 10865 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10866 | "paddusw", Iop_QAdd16Ux8, False ); |
| 10867 | goto decode_success; |
| 10868 | } |
| 10869 | |
| 10870 | /* 66 0F DB = PAND */ |
| 10871 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDB) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10872 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "pand", Iop_AndV128 ); |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10873 | goto decode_success; |
| 10874 | } |
| 10875 | |
| 10876 | /* 66 0F DF = PANDN */ |
| 10877 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDF) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 10878 | delta = dis_SSE_E_to_G_all_invG( sorb, delta+2, "pandn", Iop_AndV128 ); |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 10879 | goto decode_success; |
| 10880 | } |
| 10881 | |
| 10882 | /* 66 0F E0 = PAVGB */ |
| 10883 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE0) { |
| 10884 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10885 | "pavgb", Iop_Avg8Ux16, False ); |
| 10886 | goto decode_success; |
| 10887 | } |
| 10888 | |
| 10889 | /* 66 0F E3 = PAVGW */ |
| 10890 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE3) { |
| 10891 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10892 | "pavgw", Iop_Avg16Ux8, False ); |
| 10893 | goto decode_success; |
| 10894 | } |
| 10895 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 10896 | /* 66 0F 74 = PCMPEQB */ |
| 10897 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x74) { |
| 10898 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10899 | "pcmpeqb", Iop_CmpEQ8x16, False ); |
| 10900 | goto decode_success; |
| 10901 | } |
| 10902 | |
| 10903 | /* 66 0F 76 = PCMPEQD */ |
| 10904 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x76) { |
| 10905 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10906 | "pcmpeqd", Iop_CmpEQ32x4, False ); |
| 10907 | goto decode_success; |
| 10908 | } |
| 10909 | |
| 10910 | /* 66 0F 75 = PCMPEQW */ |
| 10911 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x75) { |
| 10912 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10913 | "pcmpeqw", Iop_CmpEQ16x8, False ); |
| 10914 | goto decode_success; |
| 10915 | } |
| 10916 | |
| 10917 | /* 66 0F 64 = PCMPGTB */ |
| 10918 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x64) { |
| 10919 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10920 | "pcmpgtb", Iop_CmpGT8Sx16, False ); |
| 10921 | goto decode_success; |
| 10922 | } |
| 10923 | |
| 10924 | /* 66 0F 66 = PCMPGTD */ |
| 10925 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x66) { |
| 10926 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10927 | "pcmpgtd", Iop_CmpGT32Sx4, False ); |
| 10928 | goto decode_success; |
| 10929 | } |
| 10930 | |
| 10931 | /* 66 0F 65 = PCMPGTW */ |
| 10932 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x65) { |
| 10933 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 10934 | "pcmpgtw", Iop_CmpGT16Sx8, False ); |
| 10935 | goto decode_success; |
| 10936 | } |
| 10937 | |
| 10938 | /* 66 0F C5 = PEXTRW -- extract 16-bit field from xmm(E) and put |
| 10939 | zero-extend of it in ireg(G). */ |
| 10940 | if (insn[0] == 0x0F && insn[1] == 0xC5) { |
| 10941 | modrm = insn[2]; |
| 10942 | if (sz == 2 && epartIsReg(modrm)) { |
| 10943 | t5 = newTemp(Ity_V128); |
| 10944 | t4 = newTemp(Ity_I16); |
| 10945 | assign(t5, getXMMReg(eregOfRM(modrm))); |
| 10946 | breakup128to32s( t5, &t3, &t2, &t1, &t0 ); |
| 10947 | switch (insn[3] & 7) { |
| 10948 | case 0: assign(t4, unop(Iop_32to16, mkexpr(t0))); break; |
| 10949 | case 1: assign(t4, unop(Iop_32HIto16, mkexpr(t0))); break; |
| 10950 | case 2: assign(t4, unop(Iop_32to16, mkexpr(t1))); break; |
| 10951 | case 3: assign(t4, unop(Iop_32HIto16, mkexpr(t1))); break; |
| 10952 | case 4: assign(t4, unop(Iop_32to16, mkexpr(t2))); break; |
| 10953 | case 5: assign(t4, unop(Iop_32HIto16, mkexpr(t2))); break; |
| 10954 | case 6: assign(t4, unop(Iop_32to16, mkexpr(t3))); break; |
| 10955 | case 7: assign(t4, unop(Iop_32HIto16, mkexpr(t3))); break; |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 10956 | default: vassert(0); /*NOTREACHED*/ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 10957 | } |
| 10958 | putIReg(4, gregOfRM(modrm), unop(Iop_16Uto32, mkexpr(t4))); |
| 10959 | DIP("pextrw $%d,%s,%s\n", |
| 10960 | (Int)insn[3], nameXMMReg(eregOfRM(modrm)), |
| 10961 | nameIReg(4,gregOfRM(modrm))); |
| 10962 | delta += 4; |
| 10963 | goto decode_success; |
| 10964 | } |
| 10965 | /* else fall through */ |
| 10966 | } |
| 10967 | |
| 10968 | /* 66 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and |
| 10969 | put it into the specified lane of xmm(G). */ |
| 10970 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xC4) { |
| 10971 | Int lane; |
| 10972 | t4 = newTemp(Ity_I16); |
| 10973 | modrm = insn[2]; |
| 10974 | |
| 10975 | if (epartIsReg(modrm)) { |
| 10976 | assign(t4, getIReg(2, eregOfRM(modrm))); |
sewardj | aac7e08 | 2005-03-17 14:03:46 +0000 | [diff] [blame] | 10977 | delta += 3+1; |
| 10978 | lane = insn[3+1-1]; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 10979 | DIP("pinsrw $%d,%s,%s\n", lane, |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 10980 | nameIReg(2,eregOfRM(modrm)), |
| 10981 | nameXMMReg(gregOfRM(modrm))); |
| 10982 | } else { |
sewardj | aac7e08 | 2005-03-17 14:03:46 +0000 | [diff] [blame] | 10983 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 10984 | delta += 3+alen; |
| 10985 | lane = insn[3+alen-1]; |
| 10986 | assign(t4, loadLE(Ity_I16, mkexpr(addr))); |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 10987 | DIP("pinsrw $%d,%s,%s\n", lane, |
sewardj | aac7e08 | 2005-03-17 14:03:46 +0000 | [diff] [blame] | 10988 | dis_buf, |
| 10989 | nameXMMReg(gregOfRM(modrm))); |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 10990 | } |
| 10991 | |
| 10992 | putXMMRegLane16( gregOfRM(modrm), lane & 7, mkexpr(t4) ); |
| 10993 | goto decode_success; |
| 10994 | } |
| 10995 | |
sewardj | b8a3dea | 2005-10-04 20:00:49 +0000 | [diff] [blame] | 10996 | /* 66 0F F5 = PMADDWD -- Multiply and add packed integers from |
| 10997 | E(xmm or mem) to G(xmm) */ |
| 10998 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF5) { |
| 10999 | IRTemp s1V = newTemp(Ity_V128); |
| 11000 | IRTemp s2V = newTemp(Ity_V128); |
| 11001 | IRTemp dV = newTemp(Ity_V128); |
| 11002 | IRTemp s1Hi = newTemp(Ity_I64); |
| 11003 | IRTemp s1Lo = newTemp(Ity_I64); |
| 11004 | IRTemp s2Hi = newTemp(Ity_I64); |
| 11005 | IRTemp s2Lo = newTemp(Ity_I64); |
| 11006 | IRTemp dHi = newTemp(Ity_I64); |
| 11007 | IRTemp dLo = newTemp(Ity_I64); |
| 11008 | modrm = insn[2]; |
| 11009 | if (epartIsReg(modrm)) { |
| 11010 | assign( s1V, getXMMReg(eregOfRM(modrm)) ); |
| 11011 | delta += 2+1; |
| 11012 | DIP("pmaddwd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 11013 | nameXMMReg(gregOfRM(modrm))); |
| 11014 | } else { |
| 11015 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11016 | assign( s1V, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11017 | delta += 2+alen; |
| 11018 | DIP("pmaddwd %s,%s\n", dis_buf, |
| 11019 | nameXMMReg(gregOfRM(modrm))); |
| 11020 | } |
| 11021 | assign( s2V, getXMMReg(gregOfRM(modrm)) ); |
| 11022 | assign( s1Hi, unop(Iop_V128HIto64, mkexpr(s1V)) ); |
| 11023 | assign( s1Lo, unop(Iop_V128to64, mkexpr(s1V)) ); |
| 11024 | assign( s2Hi, unop(Iop_V128HIto64, mkexpr(s2V)) ); |
| 11025 | assign( s2Lo, unop(Iop_V128to64, mkexpr(s2V)) ); |
| 11026 | assign( dHi, mkIRExprCCall( |
| 11027 | Ity_I64, 0/*regparms*/, |
| 11028 | "x86g_calculate_mmx_pmaddwd", |
| 11029 | &x86g_calculate_mmx_pmaddwd, |
| 11030 | mkIRExprVec_2( mkexpr(s1Hi), mkexpr(s2Hi)) |
| 11031 | )); |
| 11032 | assign( dLo, mkIRExprCCall( |
| 11033 | Ity_I64, 0/*regparms*/, |
| 11034 | "x86g_calculate_mmx_pmaddwd", |
| 11035 | &x86g_calculate_mmx_pmaddwd, |
| 11036 | mkIRExprVec_2( mkexpr(s1Lo), mkexpr(s2Lo)) |
| 11037 | )); |
| 11038 | assign( dV, binop(Iop_64HLtoV128, mkexpr(dHi), mkexpr(dLo))) ; |
| 11039 | putXMMReg(gregOfRM(modrm), mkexpr(dV)); |
| 11040 | goto decode_success; |
| 11041 | } |
| 11042 | |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 11043 | /* 66 0F EE = PMAXSW -- 16x8 signed max */ |
| 11044 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xEE) { |
| 11045 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11046 | "pmaxsw", Iop_Max16Sx8, False ); |
| 11047 | goto decode_success; |
| 11048 | } |
| 11049 | |
| 11050 | /* 66 0F DE = PMAXUB -- 8x16 unsigned max */ |
| 11051 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDE) { |
| 11052 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11053 | "pmaxub", Iop_Max8Ux16, False ); |
| 11054 | goto decode_success; |
| 11055 | } |
| 11056 | |
| 11057 | /* 66 0F EA = PMINSW -- 16x8 signed min */ |
| 11058 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xEA) { |
| 11059 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11060 | "pminsw", Iop_Min16Sx8, False ); |
| 11061 | goto decode_success; |
| 11062 | } |
| 11063 | |
| 11064 | /* 66 0F DA = PMINUB -- 8x16 unsigned min */ |
| 11065 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xDA) { |
| 11066 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11067 | "pminub", Iop_Min8Ux16, False ); |
| 11068 | goto decode_success; |
| 11069 | } |
| 11070 | |
sewardj | e13074c | 2012-11-08 10:57:08 +0000 | [diff] [blame] | 11071 | /* 66 0F D7 = PMOVMSKB -- extract sign bits from each of 16 lanes |
| 11072 | in xmm(E), turn them into a byte, and put zero-extend of it in |
| 11073 | ireg(G). */ |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 11074 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD7) { |
| 11075 | modrm = insn[2]; |
| 11076 | if (epartIsReg(modrm)) { |
| 11077 | t0 = newTemp(Ity_I64); |
| 11078 | t1 = newTemp(Ity_I64); |
| 11079 | assign(t0, getXMMRegLane64(eregOfRM(modrm), 0)); |
| 11080 | assign(t1, getXMMRegLane64(eregOfRM(modrm), 1)); |
| 11081 | t5 = newTemp(Ity_I32); |
sewardj | e13074c | 2012-11-08 10:57:08 +0000 | [diff] [blame] | 11082 | assign(t5, |
| 11083 | unop(Iop_16Uto32, |
| 11084 | binop(Iop_8HLto16, |
| 11085 | unop(Iop_GetMSBs8x8, mkexpr(t1)), |
| 11086 | unop(Iop_GetMSBs8x8, mkexpr(t0))))); |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 11087 | putIReg(4, gregOfRM(modrm), mkexpr(t5)); |
| 11088 | DIP("pmovmskb %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 11089 | nameIReg(4,gregOfRM(modrm))); |
| 11090 | delta += 3; |
| 11091 | goto decode_success; |
| 11092 | } |
| 11093 | /* else fall through */ |
| 11094 | } |
| 11095 | |
| 11096 | /* 66 0F E4 = PMULHUW -- 16x8 hi-half of unsigned widening multiply */ |
| 11097 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE4) { |
| 11098 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11099 | "pmulhuw", Iop_MulHi16Ux8, False ); |
| 11100 | goto decode_success; |
| 11101 | } |
| 11102 | |
| 11103 | /* 66 0F E5 = PMULHW -- 16x8 hi-half of signed widening multiply */ |
| 11104 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE5) { |
| 11105 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11106 | "pmulhw", Iop_MulHi16Sx8, False ); |
| 11107 | goto decode_success; |
| 11108 | } |
| 11109 | |
| 11110 | /* 66 0F D5 = PMULHL -- 16x8 multiply */ |
| 11111 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD5) { |
| 11112 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11113 | "pmullw", Iop_Mul16x8, False ); |
| 11114 | goto decode_success; |
| 11115 | } |
| 11116 | |
| 11117 | /* ***--- this is an MMX class insn introduced in SSE2 ---*** */ |
| 11118 | /* 0F F4 = PMULUDQ -- unsigned widening multiply of 32-lanes 0 x |
| 11119 | 0 to form 64-bit result */ |
| 11120 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xF4) { |
| 11121 | IRTemp sV = newTemp(Ity_I64); |
| 11122 | IRTemp dV = newTemp(Ity_I64); |
| 11123 | t1 = newTemp(Ity_I32); |
| 11124 | t0 = newTemp(Ity_I32); |
| 11125 | modrm = insn[2]; |
| 11126 | |
| 11127 | do_MMX_preamble(); |
| 11128 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 11129 | |
| 11130 | if (epartIsReg(modrm)) { |
| 11131 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 11132 | delta += 2+1; |
| 11133 | DIP("pmuludq %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 11134 | nameMMXReg(gregOfRM(modrm))); |
| 11135 | } else { |
| 11136 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11137 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 11138 | delta += 2+alen; |
| 11139 | DIP("pmuludq %s,%s\n", dis_buf, |
| 11140 | nameMMXReg(gregOfRM(modrm))); |
| 11141 | } |
| 11142 | |
| 11143 | assign( t0, unop(Iop_64to32, mkexpr(dV)) ); |
| 11144 | assign( t1, unop(Iop_64to32, mkexpr(sV)) ); |
| 11145 | putMMXReg( gregOfRM(modrm), |
| 11146 | binop( Iop_MullU32, mkexpr(t0), mkexpr(t1) ) ); |
| 11147 | goto decode_success; |
| 11148 | } |
| 11149 | |
| 11150 | /* 66 0F F4 = PMULUDQ -- unsigned widening multiply of 32-lanes 0 x |
| 11151 | 0 to form lower 64-bit half and lanes 2 x 2 to form upper 64-bit |
| 11152 | half */ |
| 11153 | /* This is a really poor translation -- could be improved if |
| 11154 | performance critical */ |
| 11155 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF4) { |
| 11156 | IRTemp sV, dV; |
| 11157 | IRTemp s3, s2, s1, s0, d3, d2, d1, d0; |
| 11158 | sV = newTemp(Ity_V128); |
| 11159 | dV = newTemp(Ity_V128); |
| 11160 | s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID; |
| 11161 | t1 = newTemp(Ity_I64); |
| 11162 | t0 = newTemp(Ity_I64); |
| 11163 | modrm = insn[2]; |
| 11164 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 11165 | |
| 11166 | if (epartIsReg(modrm)) { |
| 11167 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 11168 | delta += 2+1; |
| 11169 | DIP("pmuludq %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 11170 | nameXMMReg(gregOfRM(modrm))); |
| 11171 | } else { |
| 11172 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11173 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11174 | delta += 2+alen; |
| 11175 | DIP("pmuludq %s,%s\n", dis_buf, |
| 11176 | nameXMMReg(gregOfRM(modrm))); |
| 11177 | } |
| 11178 | |
| 11179 | breakup128to32s( dV, &d3, &d2, &d1, &d0 ); |
| 11180 | breakup128to32s( sV, &s3, &s2, &s1, &s0 ); |
| 11181 | |
| 11182 | assign( t0, binop( Iop_MullU32, mkexpr(d0), mkexpr(s0)) ); |
| 11183 | putXMMRegLane64( gregOfRM(modrm), 0, mkexpr(t0) ); |
| 11184 | assign( t1, binop( Iop_MullU32, mkexpr(d2), mkexpr(s2)) ); |
| 11185 | putXMMRegLane64( gregOfRM(modrm), 1, mkexpr(t1) ); |
| 11186 | goto decode_success; |
| 11187 | } |
| 11188 | |
| 11189 | /* 66 0F EB = POR */ |
| 11190 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xEB) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11191 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "por", Iop_OrV128 ); |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 11192 | goto decode_success; |
| 11193 | } |
| 11194 | |
sewardj | 7b5b998 | 2005-10-04 11:43:37 +0000 | [diff] [blame] | 11195 | /* 66 0F F6 = PSADBW -- 2 x (8x8 -> 48 zeroes ++ u16) Sum Abs Diffs |
| 11196 | from E(xmm or mem) to G(xmm) */ |
| 11197 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF6) { |
| 11198 | IRTemp s1V = newTemp(Ity_V128); |
| 11199 | IRTemp s2V = newTemp(Ity_V128); |
| 11200 | IRTemp dV = newTemp(Ity_V128); |
| 11201 | IRTemp s1Hi = newTemp(Ity_I64); |
| 11202 | IRTemp s1Lo = newTemp(Ity_I64); |
| 11203 | IRTemp s2Hi = newTemp(Ity_I64); |
| 11204 | IRTemp s2Lo = newTemp(Ity_I64); |
| 11205 | IRTemp dHi = newTemp(Ity_I64); |
| 11206 | IRTemp dLo = newTemp(Ity_I64); |
| 11207 | modrm = insn[2]; |
| 11208 | if (epartIsReg(modrm)) { |
| 11209 | assign( s1V, getXMMReg(eregOfRM(modrm)) ); |
| 11210 | delta += 2+1; |
| 11211 | DIP("psadbw %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 11212 | nameXMMReg(gregOfRM(modrm))); |
| 11213 | } else { |
| 11214 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11215 | assign( s1V, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11216 | delta += 2+alen; |
| 11217 | DIP("psadbw %s,%s\n", dis_buf, |
| 11218 | nameXMMReg(gregOfRM(modrm))); |
| 11219 | } |
| 11220 | assign( s2V, getXMMReg(gregOfRM(modrm)) ); |
| 11221 | assign( s1Hi, unop(Iop_V128HIto64, mkexpr(s1V)) ); |
| 11222 | assign( s1Lo, unop(Iop_V128to64, mkexpr(s1V)) ); |
| 11223 | assign( s2Hi, unop(Iop_V128HIto64, mkexpr(s2V)) ); |
| 11224 | assign( s2Lo, unop(Iop_V128to64, mkexpr(s2V)) ); |
| 11225 | assign( dHi, mkIRExprCCall( |
| 11226 | Ity_I64, 0/*regparms*/, |
| 11227 | "x86g_calculate_mmx_psadbw", |
| 11228 | &x86g_calculate_mmx_psadbw, |
| 11229 | mkIRExprVec_2( mkexpr(s1Hi), mkexpr(s2Hi)) |
| 11230 | )); |
| 11231 | assign( dLo, mkIRExprCCall( |
| 11232 | Ity_I64, 0/*regparms*/, |
| 11233 | "x86g_calculate_mmx_psadbw", |
| 11234 | &x86g_calculate_mmx_psadbw, |
| 11235 | mkIRExprVec_2( mkexpr(s1Lo), mkexpr(s2Lo)) |
| 11236 | )); |
| 11237 | assign( dV, binop(Iop_64HLtoV128, mkexpr(dHi), mkexpr(dLo))) ; |
| 11238 | putXMMReg(gregOfRM(modrm), mkexpr(dV)); |
| 11239 | goto decode_success; |
| 11240 | } |
| 11241 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11242 | /* 66 0F 70 = PSHUFD -- rearrange 4x32 from E(xmm or mem) to G(xmm) */ |
| 11243 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x70) { |
| 11244 | Int order; |
| 11245 | IRTemp sV, dV, s3, s2, s1, s0; |
| 11246 | s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 11247 | sV = newTemp(Ity_V128); |
| 11248 | dV = newTemp(Ity_V128); |
| 11249 | modrm = insn[2]; |
| 11250 | if (epartIsReg(modrm)) { |
| 11251 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 11252 | order = (Int)insn[3]; |
| 11253 | delta += 2+2; |
| 11254 | DIP("pshufd $%d,%s,%s\n", order, |
| 11255 | nameXMMReg(eregOfRM(modrm)), |
| 11256 | nameXMMReg(gregOfRM(modrm))); |
| 11257 | } else { |
| 11258 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11259 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11260 | order = (Int)insn[2+alen]; |
| 11261 | delta += 3+alen; |
| 11262 | DIP("pshufd $%d,%s,%s\n", order, |
| 11263 | dis_buf, |
| 11264 | nameXMMReg(gregOfRM(modrm))); |
| 11265 | } |
| 11266 | breakup128to32s( sV, &s3, &s2, &s1, &s0 ); |
| 11267 | |
| 11268 | # define SEL(n) \ |
| 11269 | ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) |
| 11270 | assign(dV, |
| 11271 | mk128from32s( SEL((order>>6)&3), SEL((order>>4)&3), |
| 11272 | SEL((order>>2)&3), SEL((order>>0)&3) ) |
| 11273 | ); |
| 11274 | putXMMReg(gregOfRM(modrm), mkexpr(dV)); |
| 11275 | # undef SEL |
| 11276 | goto decode_success; |
| 11277 | } |
| 11278 | |
| 11279 | /* F3 0F 70 = PSHUFHW -- rearrange upper half 4x16 from E(xmm or |
| 11280 | mem) to G(xmm), and copy lower half */ |
| 11281 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x70) { |
| 11282 | Int order; |
| 11283 | IRTemp sVhi, dVhi, sV, dV, s3, s2, s1, s0; |
| 11284 | s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 11285 | sV = newTemp(Ity_V128); |
| 11286 | dV = newTemp(Ity_V128); |
| 11287 | sVhi = newTemp(Ity_I64); |
| 11288 | dVhi = newTemp(Ity_I64); |
| 11289 | modrm = insn[3]; |
| 11290 | if (epartIsReg(modrm)) { |
| 11291 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 11292 | order = (Int)insn[4]; |
| 11293 | delta += 4+1; |
| 11294 | DIP("pshufhw $%d,%s,%s\n", order, |
| 11295 | nameXMMReg(eregOfRM(modrm)), |
| 11296 | nameXMMReg(gregOfRM(modrm))); |
| 11297 | } else { |
| 11298 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11299 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11300 | order = (Int)insn[3+alen]; |
| 11301 | delta += 4+alen; |
| 11302 | DIP("pshufhw $%d,%s,%s\n", order, |
| 11303 | dis_buf, |
| 11304 | nameXMMReg(gregOfRM(modrm))); |
| 11305 | } |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11306 | assign( sVhi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11307 | breakup64to16s( sVhi, &s3, &s2, &s1, &s0 ); |
| 11308 | |
| 11309 | # define SEL(n) \ |
| 11310 | ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) |
| 11311 | assign(dVhi, |
| 11312 | mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3), |
| 11313 | SEL((order>>2)&3), SEL((order>>0)&3) ) |
| 11314 | ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11315 | assign(dV, binop( Iop_64HLtoV128, |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11316 | mkexpr(dVhi), |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11317 | unop(Iop_V128to64, mkexpr(sV))) ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11318 | putXMMReg(gregOfRM(modrm), mkexpr(dV)); |
| 11319 | # undef SEL |
| 11320 | goto decode_success; |
| 11321 | } |
| 11322 | |
| 11323 | /* F2 0F 70 = PSHUFLW -- rearrange lower half 4x16 from E(xmm or |
| 11324 | mem) to G(xmm), and copy upper half */ |
| 11325 | if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x70) { |
| 11326 | Int order; |
| 11327 | IRTemp sVlo, dVlo, sV, dV, s3, s2, s1, s0; |
| 11328 | s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 11329 | sV = newTemp(Ity_V128); |
| 11330 | dV = newTemp(Ity_V128); |
| 11331 | sVlo = newTemp(Ity_I64); |
| 11332 | dVlo = newTemp(Ity_I64); |
| 11333 | modrm = insn[3]; |
| 11334 | if (epartIsReg(modrm)) { |
| 11335 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 11336 | order = (Int)insn[4]; |
| 11337 | delta += 4+1; |
| 11338 | DIP("pshuflw $%d,%s,%s\n", order, |
| 11339 | nameXMMReg(eregOfRM(modrm)), |
| 11340 | nameXMMReg(gregOfRM(modrm))); |
| 11341 | } else { |
| 11342 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11343 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11344 | order = (Int)insn[3+alen]; |
| 11345 | delta += 4+alen; |
| 11346 | DIP("pshuflw $%d,%s,%s\n", order, |
| 11347 | dis_buf, |
| 11348 | nameXMMReg(gregOfRM(modrm))); |
| 11349 | } |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11350 | assign( sVlo, unop(Iop_V128to64, mkexpr(sV)) ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11351 | breakup64to16s( sVlo, &s3, &s2, &s1, &s0 ); |
| 11352 | |
| 11353 | # define SEL(n) \ |
| 11354 | ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3))) |
| 11355 | assign(dVlo, |
| 11356 | mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3), |
| 11357 | SEL((order>>2)&3), SEL((order>>0)&3) ) |
| 11358 | ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11359 | assign(dV, binop( Iop_64HLtoV128, |
| 11360 | unop(Iop_V128HIto64, mkexpr(sV)), |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11361 | mkexpr(dVlo) ) ); |
| 11362 | putXMMReg(gregOfRM(modrm), mkexpr(dV)); |
| 11363 | # undef SEL |
| 11364 | goto decode_success; |
| 11365 | } |
| 11366 | |
| 11367 | /* 66 0F 72 /6 ib = PSLLD by immediate */ |
| 11368 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x72 |
| 11369 | && epartIsReg(insn[2]) |
| 11370 | && gregOfRM(insn[2]) == 6) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11371 | delta = dis_SSE_shiftE_imm( delta+2, "pslld", Iop_ShlN32x4 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11372 | goto decode_success; |
| 11373 | } |
| 11374 | |
| 11375 | /* 66 0F F2 = PSLLD by E */ |
| 11376 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF2) { |
| 11377 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "pslld", Iop_ShlN32x4 ); |
| 11378 | goto decode_success; |
| 11379 | } |
| 11380 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11381 | /* 66 0F 73 /7 ib = PSLLDQ by immediate */ |
| 11382 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x73 |
| 11383 | && epartIsReg(insn[2]) |
| 11384 | && gregOfRM(insn[2]) == 7) { |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11385 | IRTemp sV, dV, hi64, lo64, hi64r, lo64r; |
| 11386 | Int imm = (Int)insn[3]; |
| 11387 | Int reg = eregOfRM(insn[2]); |
| 11388 | DIP("pslldq $%d,%s\n", imm, nameXMMReg(reg)); |
| 11389 | vassert(imm >= 0 && imm <= 255); |
| 11390 | delta += 4; |
| 11391 | |
| 11392 | sV = newTemp(Ity_V128); |
| 11393 | dV = newTemp(Ity_V128); |
| 11394 | hi64 = newTemp(Ity_I64); |
| 11395 | lo64 = newTemp(Ity_I64); |
| 11396 | hi64r = newTemp(Ity_I64); |
| 11397 | lo64r = newTemp(Ity_I64); |
| 11398 | |
| 11399 | if (imm >= 16) { |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11400 | putXMMReg(reg, mkV128(0x0000)); |
| 11401 | goto decode_success; |
| 11402 | } |
| 11403 | |
| 11404 | assign( sV, getXMMReg(reg) ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11405 | assign( hi64, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 11406 | assign( lo64, unop(Iop_V128to64, mkexpr(sV)) ); |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11407 | |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 11408 | if (imm == 0) { |
| 11409 | assign( lo64r, mkexpr(lo64) ); |
| 11410 | assign( hi64r, mkexpr(hi64) ); |
| 11411 | } |
| 11412 | else |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11413 | if (imm == 8) { |
| 11414 | assign( lo64r, mkU64(0) ); |
| 11415 | assign( hi64r, mkexpr(lo64) ); |
| 11416 | } |
sewardj | c02043c | 2005-01-11 15:03:53 +0000 | [diff] [blame] | 11417 | else |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11418 | if (imm > 8) { |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11419 | assign( lo64r, mkU64(0) ); |
| 11420 | assign( hi64r, binop( Iop_Shl64, |
| 11421 | mkexpr(lo64), |
| 11422 | mkU8( 8*(imm-8) ) )); |
| 11423 | } else { |
| 11424 | assign( lo64r, binop( Iop_Shl64, |
| 11425 | mkexpr(lo64), |
| 11426 | mkU8(8 * imm) )); |
| 11427 | assign( hi64r, |
| 11428 | binop( Iop_Or64, |
| 11429 | binop(Iop_Shl64, mkexpr(hi64), |
| 11430 | mkU8(8 * imm)), |
| 11431 | binop(Iop_Shr64, mkexpr(lo64), |
| 11432 | mkU8(8 * (8 - imm)) ) |
| 11433 | ) |
| 11434 | ); |
| 11435 | } |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11436 | assign( dV, binop(Iop_64HLtoV128, mkexpr(hi64r), mkexpr(lo64r)) ); |
sewardj | 0c9907c | 2005-01-10 20:37:31 +0000 | [diff] [blame] | 11437 | putXMMReg(reg, mkexpr(dV)); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11438 | goto decode_success; |
| 11439 | } |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11440 | |
| 11441 | /* 66 0F 73 /6 ib = PSLLQ by immediate */ |
| 11442 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x73 |
| 11443 | && epartIsReg(insn[2]) |
| 11444 | && gregOfRM(insn[2]) == 6) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11445 | delta = dis_SSE_shiftE_imm( delta+2, "psllq", Iop_ShlN64x2 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11446 | goto decode_success; |
| 11447 | } |
| 11448 | |
| 11449 | /* 66 0F F3 = PSLLQ by E */ |
| 11450 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF3) { |
| 11451 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psllq", Iop_ShlN64x2 ); |
| 11452 | goto decode_success; |
| 11453 | } |
| 11454 | |
| 11455 | /* 66 0F 71 /6 ib = PSLLW by immediate */ |
| 11456 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x71 |
| 11457 | && epartIsReg(insn[2]) |
| 11458 | && gregOfRM(insn[2]) == 6) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11459 | delta = dis_SSE_shiftE_imm( delta+2, "psllw", Iop_ShlN16x8 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11460 | goto decode_success; |
| 11461 | } |
| 11462 | |
| 11463 | /* 66 0F F1 = PSLLW by E */ |
| 11464 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF1) { |
| 11465 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psllw", Iop_ShlN16x8 ); |
| 11466 | goto decode_success; |
| 11467 | } |
| 11468 | |
| 11469 | /* 66 0F 72 /4 ib = PSRAD by immediate */ |
| 11470 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x72 |
| 11471 | && epartIsReg(insn[2]) |
| 11472 | && gregOfRM(insn[2]) == 4) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11473 | delta = dis_SSE_shiftE_imm( delta+2, "psrad", Iop_SarN32x4 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11474 | goto decode_success; |
| 11475 | } |
| 11476 | |
| 11477 | /* 66 0F E2 = PSRAD by E */ |
| 11478 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE2) { |
| 11479 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psrad", Iop_SarN32x4 ); |
| 11480 | goto decode_success; |
| 11481 | } |
| 11482 | |
| 11483 | /* 66 0F 71 /4 ib = PSRAW by immediate */ |
| 11484 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x71 |
| 11485 | && epartIsReg(insn[2]) |
| 11486 | && gregOfRM(insn[2]) == 4) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11487 | delta = dis_SSE_shiftE_imm( delta+2, "psraw", Iop_SarN16x8 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11488 | goto decode_success; |
| 11489 | } |
| 11490 | |
| 11491 | /* 66 0F E1 = PSRAW by E */ |
| 11492 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE1) { |
| 11493 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psraw", Iop_SarN16x8 ); |
| 11494 | goto decode_success; |
| 11495 | } |
| 11496 | |
| 11497 | /* 66 0F 72 /2 ib = PSRLD by immediate */ |
| 11498 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x72 |
| 11499 | && epartIsReg(insn[2]) |
| 11500 | && gregOfRM(insn[2]) == 2) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11501 | delta = dis_SSE_shiftE_imm( delta+2, "psrld", Iop_ShrN32x4 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11502 | goto decode_success; |
| 11503 | } |
| 11504 | |
| 11505 | /* 66 0F D2 = PSRLD by E */ |
| 11506 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD2) { |
| 11507 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psrld", Iop_ShrN32x4 ); |
| 11508 | goto decode_success; |
| 11509 | } |
| 11510 | |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 11511 | /* 66 0F 73 /3 ib = PSRLDQ by immediate */ |
| 11512 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x73 |
| 11513 | && epartIsReg(insn[2]) |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11514 | && gregOfRM(insn[2]) == 3) { |
| 11515 | IRTemp sV, dV, hi64, lo64, hi64r, lo64r; |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 11516 | Int imm = (Int)insn[3]; |
| 11517 | Int reg = eregOfRM(insn[2]); |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 11518 | DIP("psrldq $%d,%s\n", imm, nameXMMReg(reg)); |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11519 | vassert(imm >= 0 && imm <= 255); |
| 11520 | delta += 4; |
| 11521 | |
| 11522 | sV = newTemp(Ity_V128); |
| 11523 | dV = newTemp(Ity_V128); |
| 11524 | hi64 = newTemp(Ity_I64); |
| 11525 | lo64 = newTemp(Ity_I64); |
| 11526 | hi64r = newTemp(Ity_I64); |
| 11527 | lo64r = newTemp(Ity_I64); |
| 11528 | |
| 11529 | if (imm >= 16) { |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11530 | putXMMReg(reg, mkV128(0x0000)); |
| 11531 | goto decode_success; |
| 11532 | } |
| 11533 | |
| 11534 | assign( sV, getXMMReg(reg) ); |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11535 | assign( hi64, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 11536 | assign( lo64, unop(Iop_V128to64, mkexpr(sV)) ); |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11537 | |
sewardj | ba89f4c | 2005-04-07 17:31:27 +0000 | [diff] [blame] | 11538 | if (imm == 0) { |
| 11539 | assign( lo64r, mkexpr(lo64) ); |
| 11540 | assign( hi64r, mkexpr(hi64) ); |
| 11541 | } |
| 11542 | else |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11543 | if (imm == 8) { |
| 11544 | assign( hi64r, mkU64(0) ); |
| 11545 | assign( lo64r, mkexpr(hi64) ); |
| 11546 | } |
| 11547 | else |
| 11548 | if (imm > 8) { |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11549 | assign( hi64r, mkU64(0) ); |
| 11550 | assign( lo64r, binop( Iop_Shr64, |
| 11551 | mkexpr(hi64), |
| 11552 | mkU8( 8*(imm-8) ) )); |
| 11553 | } else { |
| 11554 | assign( hi64r, binop( Iop_Shr64, |
| 11555 | mkexpr(hi64), |
| 11556 | mkU8(8 * imm) )); |
| 11557 | assign( lo64r, |
| 11558 | binop( Iop_Or64, |
| 11559 | binop(Iop_Shr64, mkexpr(lo64), |
| 11560 | mkU8(8 * imm)), |
| 11561 | binop(Iop_Shl64, mkexpr(hi64), |
| 11562 | mkU8(8 * (8 - imm)) ) |
| 11563 | ) |
| 11564 | ); |
| 11565 | } |
| 11566 | |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11567 | assign( dV, binop(Iop_64HLtoV128, mkexpr(hi64r), mkexpr(lo64r)) ); |
sewardj | 95535fe | 2004-12-15 17:42:58 +0000 | [diff] [blame] | 11568 | putXMMReg(reg, mkexpr(dV)); |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 11569 | goto decode_success; |
| 11570 | } |
| 11571 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11572 | /* 66 0F 73 /2 ib = PSRLQ by immediate */ |
| 11573 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x73 |
| 11574 | && epartIsReg(insn[2]) |
| 11575 | && gregOfRM(insn[2]) == 2) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11576 | delta = dis_SSE_shiftE_imm( delta+2, "psrlq", Iop_ShrN64x2 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11577 | goto decode_success; |
| 11578 | } |
| 11579 | |
| 11580 | /* 66 0F D3 = PSRLQ by E */ |
| 11581 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD3) { |
| 11582 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psrlq", Iop_ShrN64x2 ); |
| 11583 | goto decode_success; |
| 11584 | } |
| 11585 | |
| 11586 | /* 66 0F 71 /2 ib = PSRLW by immediate */ |
| 11587 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x71 |
| 11588 | && epartIsReg(insn[2]) |
| 11589 | && gregOfRM(insn[2]) == 2) { |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 11590 | delta = dis_SSE_shiftE_imm( delta+2, "psrlw", Iop_ShrN16x8 ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 11591 | goto decode_success; |
| 11592 | } |
| 11593 | |
| 11594 | /* 66 0F D1 = PSRLW by E */ |
| 11595 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD1) { |
| 11596 | delta = dis_SSE_shiftG_byE( sorb, delta+2, "psrlw", Iop_ShrN16x8 ); |
| 11597 | goto decode_success; |
| 11598 | } |
| 11599 | |
| 11600 | /* 66 0F F8 = PSUBB */ |
| 11601 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF8) { |
| 11602 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11603 | "psubb", Iop_Sub8x16, False ); |
| 11604 | goto decode_success; |
| 11605 | } |
| 11606 | |
| 11607 | /* 66 0F FA = PSUBD */ |
| 11608 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xFA) { |
| 11609 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11610 | "psubd", Iop_Sub32x4, False ); |
| 11611 | goto decode_success; |
| 11612 | } |
| 11613 | |
| 11614 | /* ***--- this is an MMX class insn introduced in SSE2 ---*** */ |
| 11615 | /* 0F FB = PSUBQ -- sub 64x1 */ |
| 11616 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xFB) { |
| 11617 | do_MMX_preamble(); |
| 11618 | delta = dis_MMXop_regmem_to_reg ( |
| 11619 | sorb, delta+2, insn[1], "psubq", False ); |
| 11620 | goto decode_success; |
| 11621 | } |
| 11622 | |
| 11623 | /* 66 0F FB = PSUBQ */ |
| 11624 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xFB) { |
| 11625 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11626 | "psubq", Iop_Sub64x2, False ); |
| 11627 | goto decode_success; |
| 11628 | } |
| 11629 | |
| 11630 | /* 66 0F F9 = PSUBW */ |
| 11631 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xF9) { |
| 11632 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11633 | "psubw", Iop_Sub16x8, False ); |
| 11634 | goto decode_success; |
| 11635 | } |
| 11636 | |
| 11637 | /* 66 0F E8 = PSUBSB */ |
| 11638 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE8) { |
| 11639 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11640 | "psubsb", Iop_QSub8Sx16, False ); |
| 11641 | goto decode_success; |
| 11642 | } |
| 11643 | |
| 11644 | /* 66 0F E9 = PSUBSW */ |
| 11645 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xE9) { |
| 11646 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11647 | "psubsw", Iop_QSub16Sx8, False ); |
| 11648 | goto decode_success; |
| 11649 | } |
| 11650 | |
| 11651 | /* 66 0F D8 = PSUBSB */ |
| 11652 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD8) { |
| 11653 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11654 | "psubusb", Iop_QSub8Ux16, False ); |
| 11655 | goto decode_success; |
| 11656 | } |
| 11657 | |
| 11658 | /* 66 0F D9 = PSUBSW */ |
| 11659 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD9) { |
| 11660 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11661 | "psubusw", Iop_QSub16Ux8, False ); |
| 11662 | goto decode_success; |
| 11663 | } |
| 11664 | |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 11665 | /* 66 0F 68 = PUNPCKHBW */ |
| 11666 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x68) { |
| 11667 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11668 | "punpckhbw", |
| 11669 | Iop_InterleaveHI8x16, True ); |
| 11670 | goto decode_success; |
| 11671 | } |
| 11672 | |
| 11673 | /* 66 0F 6A = PUNPCKHDQ */ |
| 11674 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x6A) { |
| 11675 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11676 | "punpckhdq", |
| 11677 | Iop_InterleaveHI32x4, True ); |
| 11678 | goto decode_success; |
| 11679 | } |
| 11680 | |
| 11681 | /* 66 0F 6D = PUNPCKHQDQ */ |
| 11682 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x6D) { |
| 11683 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11684 | "punpckhqdq", |
| 11685 | Iop_InterleaveHI64x2, True ); |
| 11686 | goto decode_success; |
| 11687 | } |
| 11688 | |
| 11689 | /* 66 0F 69 = PUNPCKHWD */ |
| 11690 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x69) { |
| 11691 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11692 | "punpckhwd", |
| 11693 | Iop_InterleaveHI16x8, True ); |
| 11694 | goto decode_success; |
| 11695 | } |
| 11696 | |
| 11697 | /* 66 0F 60 = PUNPCKLBW */ |
| 11698 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x60) { |
| 11699 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11700 | "punpcklbw", |
| 11701 | Iop_InterleaveLO8x16, True ); |
| 11702 | goto decode_success; |
| 11703 | } |
| 11704 | |
| 11705 | /* 66 0F 62 = PUNPCKLDQ */ |
| 11706 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x62) { |
| 11707 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11708 | "punpckldq", |
| 11709 | Iop_InterleaveLO32x4, True ); |
| 11710 | goto decode_success; |
| 11711 | } |
| 11712 | |
| 11713 | /* 66 0F 6C = PUNPCKLQDQ */ |
| 11714 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x6C) { |
| 11715 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11716 | "punpcklqdq", |
| 11717 | Iop_InterleaveLO64x2, True ); |
| 11718 | goto decode_success; |
| 11719 | } |
| 11720 | |
| 11721 | /* 66 0F 61 = PUNPCKLWD */ |
| 11722 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x61) { |
| 11723 | delta = dis_SSEint_E_to_G( sorb, delta+2, |
| 11724 | "punpcklwd", |
| 11725 | Iop_InterleaveLO16x8, True ); |
| 11726 | goto decode_success; |
| 11727 | } |
| 11728 | |
| 11729 | /* 66 0F EF = PXOR */ |
| 11730 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xEF) { |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 11731 | delta = dis_SSE_E_to_G_all( sorb, delta+2, "pxor", Iop_XorV128 ); |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 11732 | goto decode_success; |
| 11733 | } |
| 11734 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 11735 | //-- /* FXSAVE/FXRSTOR m32 -- load/store the FPU/MMX/SSE state. */ |
| 11736 | //-- if (insn[0] == 0x0F && insn[1] == 0xAE |
| 11737 | //-- && (!epartIsReg(insn[2])) |
| 11738 | //-- && (gregOfRM(insn[2]) == 1 || gregOfRM(insn[2]) == 0) ) { |
| 11739 | //-- Bool store = gregOfRM(insn[2]) == 0; |
| 11740 | //-- vg_assert(sz == 4); |
| 11741 | //-- pair = disAMode ( cb, sorb, eip+2, dis_buf ); |
| 11742 | //-- t1 = LOW24(pair); |
| 11743 | //-- eip += 2+HI8(pair); |
| 11744 | //-- uInstr3(cb, store ? SSE2a_MemWr : SSE2a_MemRd, 512, |
| 11745 | //-- Lit16, (((UShort)insn[0]) << 8) | (UShort)insn[1], |
| 11746 | //-- Lit16, (UShort)insn[2], |
| 11747 | //-- TempReg, t1 ); |
| 11748 | //-- DIP("fx%s %s\n", store ? "save" : "rstor", dis_buf ); |
| 11749 | //-- goto decode_success; |
| 11750 | //-- } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 11751 | |
sewardj | bfceb08 | 2005-11-15 11:16:30 +0000 | [diff] [blame] | 11752 | /* 0F AE /7 = CLFLUSH -- flush cache line */ |
| 11753 | if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xAE |
| 11754 | && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 7) { |
| 11755 | |
| 11756 | /* This is something of a hack. We need to know the size of the |
| 11757 | cache line containing addr. Since we don't (easily), assume |
| 11758 | 256 on the basis that no real cache would have a line that |
| 11759 | big. It's safe to invalidate more stuff than we need, just |
| 11760 | inefficient. */ |
| 11761 | UInt lineszB = 256; |
| 11762 | |
| 11763 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11764 | delta += 2+alen; |
| 11765 | |
| 11766 | /* Round addr down to the start of the containing block. */ |
| 11767 | stmt( IRStmt_Put( |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 11768 | OFFB_CMSTART, |
sewardj | bfceb08 | 2005-11-15 11:16:30 +0000 | [diff] [blame] | 11769 | binop( Iop_And32, |
| 11770 | mkexpr(addr), |
| 11771 | mkU32( ~(lineszB-1) ))) ); |
| 11772 | |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 11773 | stmt( IRStmt_Put(OFFB_CMLEN, mkU32(lineszB) ) ); |
sewardj | bfceb08 | 2005-11-15 11:16:30 +0000 | [diff] [blame] | 11774 | |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 11775 | jmp_lit(&dres, Ijk_InvalICache, (Addr32)(guest_EIP_bbstart+delta)); |
sewardj | bfceb08 | 2005-11-15 11:16:30 +0000 | [diff] [blame] | 11776 | |
| 11777 | DIP("clflush %s\n", dis_buf); |
| 11778 | goto decode_success; |
| 11779 | } |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 11780 | |
| 11781 | /* ---------------------------------------------------- */ |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11782 | /* --- end of the SSE2 decoder. --- */ |
| 11783 | /* ---------------------------------------------------- */ |
| 11784 | |
| 11785 | /* ---------------------------------------------------- */ |
| 11786 | /* --- start of the SSE3 decoder. --- */ |
| 11787 | /* ---------------------------------------------------- */ |
| 11788 | |
| 11789 | /* Skip parts of the decoder which don't apply given the stated |
| 11790 | guest subarchitecture. */ |
florian | 9f07e86 | 2014-12-09 20:09:42 +0000 | [diff] [blame] | 11791 | if (0 == (archinfo->hwcaps & VEX_HWCAPS_X86_SSE3)) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 11792 | goto after_sse_decoders; /* no SSE3 capabilities */ |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11793 | |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 11794 | insn = &guest_code[delta]; |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11795 | |
| 11796 | /* F3 0F 12 = MOVSLDUP -- move from E (mem or xmm) to G (xmm), |
| 11797 | duplicating some lanes (2:2:0:0). */ |
| 11798 | /* F3 0F 16 = MOVSHDUP -- move from E (mem or xmm) to G (xmm), |
| 11799 | duplicating some lanes (3:3:1:1). */ |
| 11800 | if (sz == 4 && insn[0] == 0xF3 && insn[1] == 0x0F |
| 11801 | && (insn[2] == 0x12 || insn[2] == 0x16)) { |
| 11802 | IRTemp s3, s2, s1, s0; |
| 11803 | IRTemp sV = newTemp(Ity_V128); |
| 11804 | Bool isH = insn[2] == 0x16; |
| 11805 | s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 11806 | |
| 11807 | modrm = insn[3]; |
| 11808 | if (epartIsReg(modrm)) { |
| 11809 | assign( sV, getXMMReg( eregOfRM(modrm)) ); |
| 11810 | DIP("movs%cdup %s,%s\n", isH ? 'h' : 'l', |
| 11811 | nameXMMReg(eregOfRM(modrm)), |
| 11812 | nameXMMReg(gregOfRM(modrm))); |
| 11813 | delta += 3+1; |
| 11814 | } else { |
| 11815 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
sewardj | 45ca0b9 | 2010-09-30 14:51:51 +0000 | [diff] [blame] | 11816 | gen_SEGV_if_not_16_aligned( addr ); |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11817 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11818 | DIP("movs%cdup %s,%s\n", isH ? 'h' : 'l', |
| 11819 | dis_buf, |
| 11820 | nameXMMReg(gregOfRM(modrm))); |
| 11821 | delta += 3+alen; |
| 11822 | } |
| 11823 | |
| 11824 | breakup128to32s( sV, &s3, &s2, &s1, &s0 ); |
| 11825 | putXMMReg( gregOfRM(modrm), |
| 11826 | isH ? mk128from32s( s3, s3, s1, s1 ) |
| 11827 | : mk128from32s( s2, s2, s0, s0 ) ); |
| 11828 | goto decode_success; |
| 11829 | } |
| 11830 | |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11831 | /* F2 0F 12 = MOVDDUP -- move from E (mem or xmm) to G (xmm), |
| 11832 | duplicating some lanes (0:1:0:1). */ |
| 11833 | if (sz == 4 && insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x12) { |
| 11834 | IRTemp sV = newTemp(Ity_V128); |
| 11835 | IRTemp d0 = newTemp(Ity_I64); |
| 11836 | |
| 11837 | modrm = insn[3]; |
| 11838 | if (epartIsReg(modrm)) { |
| 11839 | assign( sV, getXMMReg( eregOfRM(modrm)) ); |
| 11840 | DIP("movddup %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 11841 | nameXMMReg(gregOfRM(modrm))); |
| 11842 | delta += 3+1; |
| 11843 | assign ( d0, unop(Iop_V128to64, mkexpr(sV)) ); |
| 11844 | } else { |
| 11845 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11846 | assign( d0, loadLE(Ity_I64, mkexpr(addr)) ); |
| 11847 | DIP("movddup %s,%s\n", dis_buf, |
| 11848 | nameXMMReg(gregOfRM(modrm))); |
| 11849 | delta += 3+alen; |
| 11850 | } |
| 11851 | |
| 11852 | putXMMReg( gregOfRM(modrm), binop(Iop_64HLtoV128,mkexpr(d0),mkexpr(d0)) ); |
| 11853 | goto decode_success; |
| 11854 | } |
| 11855 | |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11856 | /* F2 0F D0 = ADDSUBPS -- 32x4 +/-/+/- from E (mem or xmm) to G (xmm). */ |
| 11857 | if (sz == 4 && insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xD0) { |
| 11858 | IRTemp a3, a2, a1, a0, s3, s2, s1, s0; |
| 11859 | IRTemp eV = newTemp(Ity_V128); |
| 11860 | IRTemp gV = newTemp(Ity_V128); |
| 11861 | IRTemp addV = newTemp(Ity_V128); |
| 11862 | IRTemp subV = newTemp(Ity_V128); |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 11863 | IRTemp rm = newTemp(Ity_I32); |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11864 | a3 = a2 = a1 = a0 = s3 = s2 = s1 = s0 = IRTemp_INVALID; |
| 11865 | |
| 11866 | modrm = insn[3]; |
| 11867 | if (epartIsReg(modrm)) { |
| 11868 | assign( eV, getXMMReg( eregOfRM(modrm)) ); |
| 11869 | DIP("addsubps %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 11870 | nameXMMReg(gregOfRM(modrm))); |
| 11871 | delta += 3+1; |
| 11872 | } else { |
| 11873 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11874 | assign( eV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11875 | DIP("addsubps %s,%s\n", dis_buf, |
| 11876 | nameXMMReg(gregOfRM(modrm))); |
| 11877 | delta += 3+alen; |
| 11878 | } |
| 11879 | |
| 11880 | assign( gV, getXMMReg(gregOfRM(modrm)) ); |
| 11881 | |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 11882 | assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ |
| 11883 | assign( addV, triop(Iop_Add32Fx4, mkexpr(rm), mkexpr(gV), mkexpr(eV)) ); |
| 11884 | assign( subV, triop(Iop_Sub32Fx4, mkexpr(rm), mkexpr(gV), mkexpr(eV)) ); |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 11885 | |
| 11886 | breakup128to32s( addV, &a3, &a2, &a1, &a0 ); |
| 11887 | breakup128to32s( subV, &s3, &s2, &s1, &s0 ); |
| 11888 | |
| 11889 | putXMMReg( gregOfRM(modrm), mk128from32s( a3, s2, a1, s0 )); |
| 11890 | goto decode_success; |
| 11891 | } |
| 11892 | |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11893 | /* 66 0F D0 = ADDSUBPD -- 64x4 +/- from E (mem or xmm) to G (xmm). */ |
| 11894 | if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD0) { |
| 11895 | IRTemp eV = newTemp(Ity_V128); |
| 11896 | IRTemp gV = newTemp(Ity_V128); |
| 11897 | IRTemp addV = newTemp(Ity_V128); |
| 11898 | IRTemp subV = newTemp(Ity_V128); |
| 11899 | IRTemp a1 = newTemp(Ity_I64); |
| 11900 | IRTemp s0 = newTemp(Ity_I64); |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 11901 | IRTemp rm = newTemp(Ity_I32); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11902 | |
| 11903 | modrm = insn[2]; |
| 11904 | if (epartIsReg(modrm)) { |
| 11905 | assign( eV, getXMMReg( eregOfRM(modrm)) ); |
| 11906 | DIP("addsubpd %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 11907 | nameXMMReg(gregOfRM(modrm))); |
| 11908 | delta += 2+1; |
| 11909 | } else { |
| 11910 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11911 | assign( eV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11912 | DIP("addsubpd %s,%s\n", dis_buf, |
| 11913 | nameXMMReg(gregOfRM(modrm))); |
| 11914 | delta += 2+alen; |
| 11915 | } |
| 11916 | |
| 11917 | assign( gV, getXMMReg(gregOfRM(modrm)) ); |
| 11918 | |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 11919 | assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ |
| 11920 | assign( addV, triop(Iop_Add64Fx2, mkexpr(rm), mkexpr(gV), mkexpr(eV)) ); |
| 11921 | assign( subV, triop(Iop_Sub64Fx2, mkexpr(rm), mkexpr(gV), mkexpr(eV)) ); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11922 | |
| 11923 | assign( a1, unop(Iop_V128HIto64, mkexpr(addV) )); |
| 11924 | assign( s0, unop(Iop_V128to64, mkexpr(subV) )); |
| 11925 | |
| 11926 | putXMMReg( gregOfRM(modrm), |
| 11927 | binop(Iop_64HLtoV128, mkexpr(a1), mkexpr(s0)) ); |
| 11928 | goto decode_success; |
| 11929 | } |
| 11930 | |
| 11931 | /* F2 0F 7D = HSUBPS -- 32x4 sub across from E (mem or xmm) to G (xmm). */ |
| 11932 | /* F2 0F 7C = HADDPS -- 32x4 add across from E (mem or xmm) to G (xmm). */ |
| 11933 | if (sz == 4 && insn[0] == 0xF2 && insn[1] == 0x0F |
| 11934 | && (insn[2] == 0x7C || insn[2] == 0x7D)) { |
| 11935 | IRTemp e3, e2, e1, e0, g3, g2, g1, g0; |
| 11936 | IRTemp eV = newTemp(Ity_V128); |
| 11937 | IRTemp gV = newTemp(Ity_V128); |
| 11938 | IRTemp leftV = newTemp(Ity_V128); |
| 11939 | IRTemp rightV = newTemp(Ity_V128); |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 11940 | IRTemp rm = newTemp(Ity_I32); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11941 | Bool isAdd = insn[2] == 0x7C; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 11942 | const HChar* str = isAdd ? "add" : "sub"; |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11943 | e3 = e2 = e1 = e0 = g3 = g2 = g1 = g0 = IRTemp_INVALID; |
| 11944 | |
| 11945 | modrm = insn[3]; |
| 11946 | if (epartIsReg(modrm)) { |
| 11947 | assign( eV, getXMMReg( eregOfRM(modrm)) ); |
| 11948 | DIP("h%sps %s,%s\n", str, nameXMMReg(eregOfRM(modrm)), |
| 11949 | nameXMMReg(gregOfRM(modrm))); |
| 11950 | delta += 3+1; |
| 11951 | } else { |
| 11952 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 11953 | assign( eV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11954 | DIP("h%sps %s,%s\n", str, dis_buf, |
| 11955 | nameXMMReg(gregOfRM(modrm))); |
| 11956 | delta += 3+alen; |
| 11957 | } |
| 11958 | |
| 11959 | assign( gV, getXMMReg(gregOfRM(modrm)) ); |
| 11960 | |
| 11961 | breakup128to32s( eV, &e3, &e2, &e1, &e0 ); |
| 11962 | breakup128to32s( gV, &g3, &g2, &g1, &g0 ); |
| 11963 | |
| 11964 | assign( leftV, mk128from32s( e2, e0, g2, g0 ) ); |
| 11965 | assign( rightV, mk128from32s( e3, e1, g3, g1 ) ); |
| 11966 | |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 11967 | assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11968 | putXMMReg( gregOfRM(modrm), |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 11969 | triop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, |
| 11970 | mkexpr(rm), mkexpr(leftV), mkexpr(rightV) ) ); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11971 | goto decode_success; |
| 11972 | } |
| 11973 | |
| 11974 | /* 66 0F 7D = HSUBPD -- 64x2 sub across from E (mem or xmm) to G (xmm). */ |
| 11975 | /* 66 0F 7C = HADDPD -- 64x2 add across from E (mem or xmm) to G (xmm). */ |
| 11976 | if (sz == 2 && insn[0] == 0x0F && (insn[1] == 0x7C || insn[1] == 0x7D)) { |
| 11977 | IRTemp e1 = newTemp(Ity_I64); |
| 11978 | IRTemp e0 = newTemp(Ity_I64); |
| 11979 | IRTemp g1 = newTemp(Ity_I64); |
| 11980 | IRTemp g0 = newTemp(Ity_I64); |
| 11981 | IRTemp eV = newTemp(Ity_V128); |
| 11982 | IRTemp gV = newTemp(Ity_V128); |
| 11983 | IRTemp leftV = newTemp(Ity_V128); |
| 11984 | IRTemp rightV = newTemp(Ity_V128); |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 11985 | IRTemp rm = newTemp(Ity_I32); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11986 | Bool isAdd = insn[1] == 0x7C; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 11987 | const HChar* str = isAdd ? "add" : "sub"; |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 11988 | |
| 11989 | modrm = insn[2]; |
| 11990 | if (epartIsReg(modrm)) { |
| 11991 | assign( eV, getXMMReg( eregOfRM(modrm)) ); |
| 11992 | DIP("h%spd %s,%s\n", str, nameXMMReg(eregOfRM(modrm)), |
| 11993 | nameXMMReg(gregOfRM(modrm))); |
| 11994 | delta += 2+1; |
| 11995 | } else { |
| 11996 | addr = disAMode ( &alen, sorb, delta+2, dis_buf ); |
| 11997 | assign( eV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 11998 | DIP("h%spd %s,%s\n", str, dis_buf, |
| 11999 | nameXMMReg(gregOfRM(modrm))); |
| 12000 | delta += 2+alen; |
| 12001 | } |
| 12002 | |
| 12003 | assign( gV, getXMMReg(gregOfRM(modrm)) ); |
| 12004 | |
| 12005 | assign( e1, unop(Iop_V128HIto64, mkexpr(eV) )); |
| 12006 | assign( e0, unop(Iop_V128to64, mkexpr(eV) )); |
| 12007 | assign( g1, unop(Iop_V128HIto64, mkexpr(gV) )); |
| 12008 | assign( g0, unop(Iop_V128to64, mkexpr(gV) )); |
| 12009 | |
| 12010 | assign( leftV, binop(Iop_64HLtoV128, mkexpr(e0),mkexpr(g0)) ); |
| 12011 | assign( rightV, binop(Iop_64HLtoV128, mkexpr(e1),mkexpr(g1)) ); |
| 12012 | |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 12013 | assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 12014 | putXMMReg( gregOfRM(modrm), |
sewardj | 9571dc0 | 2014-01-26 18:34:23 +0000 | [diff] [blame] | 12015 | triop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, |
| 12016 | mkexpr(rm), mkexpr(leftV), mkexpr(rightV) ) ); |
sewardj | dd5d204 | 2006-08-03 15:03:19 +0000 | [diff] [blame] | 12017 | goto decode_success; |
| 12018 | } |
| 12019 | |
| 12020 | /* F2 0F F0 = LDDQU -- move from E (mem or xmm) to G (xmm). */ |
| 12021 | if (sz == 4 && insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xF0) { |
| 12022 | modrm = getIByte(delta+3); |
| 12023 | if (epartIsReg(modrm)) { |
| 12024 | goto decode_failure; |
| 12025 | } else { |
| 12026 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12027 | putXMMReg( gregOfRM(modrm), |
| 12028 | loadLE(Ity_V128, mkexpr(addr)) ); |
| 12029 | DIP("lddqu %s,%s\n", dis_buf, |
| 12030 | nameXMMReg(gregOfRM(modrm))); |
| 12031 | delta += 3+alen; |
| 12032 | } |
| 12033 | goto decode_success; |
| 12034 | } |
| 12035 | |
sewardj | 90e91ee | 2005-11-07 14:23:52 +0000 | [diff] [blame] | 12036 | /* ---------------------------------------------------- */ |
| 12037 | /* --- end of the SSE3 decoder. --- */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 12038 | /* ---------------------------------------------------- */ |
| 12039 | |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12040 | /* ---------------------------------------------------- */ |
| 12041 | /* --- start of the SSSE3 decoder. --- */ |
| 12042 | /* ---------------------------------------------------- */ |
| 12043 | |
| 12044 | /* 0F 38 04 = PMADDUBSW -- Multiply and Add Packed Signed and |
| 12045 | Unsigned Bytes (MMX) */ |
| 12046 | if (sz == 4 |
| 12047 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x04) { |
| 12048 | IRTemp sV = newTemp(Ity_I64); |
| 12049 | IRTemp dV = newTemp(Ity_I64); |
| 12050 | IRTemp sVoddsSX = newTemp(Ity_I64); |
| 12051 | IRTemp sVevensSX = newTemp(Ity_I64); |
| 12052 | IRTemp dVoddsZX = newTemp(Ity_I64); |
| 12053 | IRTemp dVevensZX = newTemp(Ity_I64); |
| 12054 | |
| 12055 | modrm = insn[3]; |
| 12056 | do_MMX_preamble(); |
| 12057 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 12058 | |
| 12059 | if (epartIsReg(modrm)) { |
| 12060 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12061 | delta += 3+1; |
| 12062 | DIP("pmaddubsw %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 12063 | nameMMXReg(gregOfRM(modrm))); |
| 12064 | } else { |
| 12065 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12066 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12067 | delta += 3+alen; |
| 12068 | DIP("pmaddubsw %s,%s\n", dis_buf, |
| 12069 | nameMMXReg(gregOfRM(modrm))); |
| 12070 | } |
| 12071 | |
| 12072 | /* compute dV unsigned x sV signed */ |
| 12073 | assign( sVoddsSX, |
| 12074 | binop(Iop_SarN16x4, mkexpr(sV), mkU8(8)) ); |
| 12075 | assign( sVevensSX, |
| 12076 | binop(Iop_SarN16x4, |
| 12077 | binop(Iop_ShlN16x4, mkexpr(sV), mkU8(8)), |
| 12078 | mkU8(8)) ); |
| 12079 | assign( dVoddsZX, |
| 12080 | binop(Iop_ShrN16x4, mkexpr(dV), mkU8(8)) ); |
| 12081 | assign( dVevensZX, |
| 12082 | binop(Iop_ShrN16x4, |
| 12083 | binop(Iop_ShlN16x4, mkexpr(dV), mkU8(8)), |
| 12084 | mkU8(8)) ); |
| 12085 | |
| 12086 | putMMXReg( |
| 12087 | gregOfRM(modrm), |
| 12088 | binop(Iop_QAdd16Sx4, |
| 12089 | binop(Iop_Mul16x4, mkexpr(sVoddsSX), mkexpr(dVoddsZX)), |
| 12090 | binop(Iop_Mul16x4, mkexpr(sVevensSX), mkexpr(dVevensZX)) |
| 12091 | ) |
| 12092 | ); |
| 12093 | goto decode_success; |
| 12094 | } |
| 12095 | |
| 12096 | /* 66 0F 38 04 = PMADDUBSW -- Multiply and Add Packed Signed and |
| 12097 | Unsigned Bytes (XMM) */ |
| 12098 | if (sz == 2 |
| 12099 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x04) { |
| 12100 | IRTemp sV = newTemp(Ity_V128); |
| 12101 | IRTemp dV = newTemp(Ity_V128); |
| 12102 | IRTemp sVoddsSX = newTemp(Ity_V128); |
| 12103 | IRTemp sVevensSX = newTemp(Ity_V128); |
| 12104 | IRTemp dVoddsZX = newTemp(Ity_V128); |
| 12105 | IRTemp dVevensZX = newTemp(Ity_V128); |
| 12106 | |
| 12107 | modrm = insn[3]; |
| 12108 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 12109 | |
| 12110 | if (epartIsReg(modrm)) { |
| 12111 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 12112 | delta += 3+1; |
| 12113 | DIP("pmaddubsw %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 12114 | nameXMMReg(gregOfRM(modrm))); |
| 12115 | } else { |
| 12116 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12117 | gen_SEGV_if_not_16_aligned( addr ); |
| 12118 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12119 | delta += 3+alen; |
| 12120 | DIP("pmaddubsw %s,%s\n", dis_buf, |
| 12121 | nameXMMReg(gregOfRM(modrm))); |
| 12122 | } |
| 12123 | |
| 12124 | /* compute dV unsigned x sV signed */ |
| 12125 | assign( sVoddsSX, |
| 12126 | binop(Iop_SarN16x8, mkexpr(sV), mkU8(8)) ); |
| 12127 | assign( sVevensSX, |
| 12128 | binop(Iop_SarN16x8, |
| 12129 | binop(Iop_ShlN16x8, mkexpr(sV), mkU8(8)), |
| 12130 | mkU8(8)) ); |
| 12131 | assign( dVoddsZX, |
| 12132 | binop(Iop_ShrN16x8, mkexpr(dV), mkU8(8)) ); |
| 12133 | assign( dVevensZX, |
| 12134 | binop(Iop_ShrN16x8, |
| 12135 | binop(Iop_ShlN16x8, mkexpr(dV), mkU8(8)), |
| 12136 | mkU8(8)) ); |
| 12137 | |
| 12138 | putXMMReg( |
| 12139 | gregOfRM(modrm), |
| 12140 | binop(Iop_QAdd16Sx8, |
| 12141 | binop(Iop_Mul16x8, mkexpr(sVoddsSX), mkexpr(dVoddsZX)), |
| 12142 | binop(Iop_Mul16x8, mkexpr(sVevensSX), mkexpr(dVevensZX)) |
| 12143 | ) |
| 12144 | ); |
| 12145 | goto decode_success; |
| 12146 | } |
| 12147 | |
| 12148 | /* ***--- these are MMX class insns introduced in SSSE3 ---*** */ |
| 12149 | /* 0F 38 03 = PHADDSW -- 16x4 signed qadd across from E (mem or |
| 12150 | mmx) and G to G (mmx). */ |
| 12151 | /* 0F 38 07 = PHSUBSW -- 16x4 signed qsub across from E (mem or |
| 12152 | mmx) and G to G (mmx). */ |
| 12153 | /* 0F 38 01 = PHADDW -- 16x4 add across from E (mem or mmx) and G |
| 12154 | to G (mmx). */ |
| 12155 | /* 0F 38 05 = PHSUBW -- 16x4 sub across from E (mem or mmx) and G |
| 12156 | to G (mmx). */ |
| 12157 | /* 0F 38 02 = PHADDD -- 32x2 add across from E (mem or mmx) and G |
| 12158 | to G (mmx). */ |
| 12159 | /* 0F 38 06 = PHSUBD -- 32x2 sub across from E (mem or mmx) and G |
| 12160 | to G (mmx). */ |
| 12161 | |
| 12162 | if (sz == 4 |
| 12163 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 12164 | && (insn[2] == 0x03 || insn[2] == 0x07 || insn[2] == 0x01 |
| 12165 | || insn[2] == 0x05 || insn[2] == 0x02 || insn[2] == 0x06)) { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 12166 | const HChar* str = "???"; |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12167 | IROp opV64 = Iop_INVALID; |
| 12168 | IROp opCatO = Iop_CatOddLanes16x4; |
| 12169 | IROp opCatE = Iop_CatEvenLanes16x4; |
| 12170 | IRTemp sV = newTemp(Ity_I64); |
| 12171 | IRTemp dV = newTemp(Ity_I64); |
| 12172 | |
| 12173 | modrm = insn[3]; |
| 12174 | |
| 12175 | switch (insn[2]) { |
| 12176 | case 0x03: opV64 = Iop_QAdd16Sx4; str = "addsw"; break; |
| 12177 | case 0x07: opV64 = Iop_QSub16Sx4; str = "subsw"; break; |
| 12178 | case 0x01: opV64 = Iop_Add16x4; str = "addw"; break; |
| 12179 | case 0x05: opV64 = Iop_Sub16x4; str = "subw"; break; |
| 12180 | case 0x02: opV64 = Iop_Add32x2; str = "addd"; break; |
| 12181 | case 0x06: opV64 = Iop_Sub32x2; str = "subd"; break; |
| 12182 | default: vassert(0); |
| 12183 | } |
| 12184 | if (insn[2] == 0x02 || insn[2] == 0x06) { |
| 12185 | opCatO = Iop_InterleaveHI32x2; |
| 12186 | opCatE = Iop_InterleaveLO32x2; |
| 12187 | } |
| 12188 | |
| 12189 | do_MMX_preamble(); |
| 12190 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 12191 | |
| 12192 | if (epartIsReg(modrm)) { |
| 12193 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12194 | delta += 3+1; |
| 12195 | DIP("ph%s %s,%s\n", str, nameMMXReg(eregOfRM(modrm)), |
| 12196 | nameMMXReg(gregOfRM(modrm))); |
| 12197 | } else { |
| 12198 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12199 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12200 | delta += 3+alen; |
| 12201 | DIP("ph%s %s,%s\n", str, dis_buf, |
| 12202 | nameMMXReg(gregOfRM(modrm))); |
| 12203 | } |
| 12204 | |
| 12205 | putMMXReg( |
| 12206 | gregOfRM(modrm), |
| 12207 | binop(opV64, |
| 12208 | binop(opCatE,mkexpr(sV),mkexpr(dV)), |
| 12209 | binop(opCatO,mkexpr(sV),mkexpr(dV)) |
| 12210 | ) |
| 12211 | ); |
| 12212 | goto decode_success; |
| 12213 | } |
| 12214 | |
| 12215 | /* 66 0F 38 03 = PHADDSW -- 16x8 signed qadd across from E (mem or |
| 12216 | xmm) and G to G (xmm). */ |
| 12217 | /* 66 0F 38 07 = PHSUBSW -- 16x8 signed qsub across from E (mem or |
| 12218 | xmm) and G to G (xmm). */ |
| 12219 | /* 66 0F 38 01 = PHADDW -- 16x8 add across from E (mem or xmm) and |
| 12220 | G to G (xmm). */ |
| 12221 | /* 66 0F 38 05 = PHSUBW -- 16x8 sub across from E (mem or xmm) and |
| 12222 | G to G (xmm). */ |
| 12223 | /* 66 0F 38 02 = PHADDD -- 32x4 add across from E (mem or xmm) and |
| 12224 | G to G (xmm). */ |
| 12225 | /* 66 0F 38 06 = PHSUBD -- 32x4 sub across from E (mem or xmm) and |
| 12226 | G to G (xmm). */ |
| 12227 | |
| 12228 | if (sz == 2 |
| 12229 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 12230 | && (insn[2] == 0x03 || insn[2] == 0x07 || insn[2] == 0x01 |
| 12231 | || insn[2] == 0x05 || insn[2] == 0x02 || insn[2] == 0x06)) { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 12232 | const HChar* str = "???"; |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12233 | IROp opV64 = Iop_INVALID; |
| 12234 | IROp opCatO = Iop_CatOddLanes16x4; |
| 12235 | IROp opCatE = Iop_CatEvenLanes16x4; |
| 12236 | IRTemp sV = newTemp(Ity_V128); |
| 12237 | IRTemp dV = newTemp(Ity_V128); |
| 12238 | IRTemp sHi = newTemp(Ity_I64); |
| 12239 | IRTemp sLo = newTemp(Ity_I64); |
| 12240 | IRTemp dHi = newTemp(Ity_I64); |
| 12241 | IRTemp dLo = newTemp(Ity_I64); |
| 12242 | |
| 12243 | modrm = insn[3]; |
| 12244 | |
| 12245 | switch (insn[2]) { |
| 12246 | case 0x03: opV64 = Iop_QAdd16Sx4; str = "addsw"; break; |
| 12247 | case 0x07: opV64 = Iop_QSub16Sx4; str = "subsw"; break; |
| 12248 | case 0x01: opV64 = Iop_Add16x4; str = "addw"; break; |
| 12249 | case 0x05: opV64 = Iop_Sub16x4; str = "subw"; break; |
| 12250 | case 0x02: opV64 = Iop_Add32x2; str = "addd"; break; |
| 12251 | case 0x06: opV64 = Iop_Sub32x2; str = "subd"; break; |
| 12252 | default: vassert(0); |
| 12253 | } |
| 12254 | if (insn[2] == 0x02 || insn[2] == 0x06) { |
| 12255 | opCatO = Iop_InterleaveHI32x2; |
| 12256 | opCatE = Iop_InterleaveLO32x2; |
| 12257 | } |
| 12258 | |
| 12259 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 12260 | |
| 12261 | if (epartIsReg(modrm)) { |
| 12262 | assign( sV, getXMMReg( eregOfRM(modrm)) ); |
| 12263 | DIP("ph%s %s,%s\n", str, nameXMMReg(eregOfRM(modrm)), |
| 12264 | nameXMMReg(gregOfRM(modrm))); |
| 12265 | delta += 3+1; |
| 12266 | } else { |
| 12267 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12268 | gen_SEGV_if_not_16_aligned( addr ); |
| 12269 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12270 | DIP("ph%s %s,%s\n", str, dis_buf, |
| 12271 | nameXMMReg(gregOfRM(modrm))); |
| 12272 | delta += 3+alen; |
| 12273 | } |
| 12274 | |
| 12275 | assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 12276 | assign( dLo, unop(Iop_V128to64, mkexpr(dV)) ); |
| 12277 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12278 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12279 | |
| 12280 | /* This isn't a particularly efficient way to compute the |
| 12281 | result, but at least it avoids a proliferation of IROps, |
| 12282 | hence avoids complication all the backends. */ |
| 12283 | putXMMReg( |
| 12284 | gregOfRM(modrm), |
| 12285 | binop(Iop_64HLtoV128, |
| 12286 | binop(opV64, |
| 12287 | binop(opCatE,mkexpr(sHi),mkexpr(sLo)), |
| 12288 | binop(opCatO,mkexpr(sHi),mkexpr(sLo)) |
| 12289 | ), |
| 12290 | binop(opV64, |
| 12291 | binop(opCatE,mkexpr(dHi),mkexpr(dLo)), |
| 12292 | binop(opCatO,mkexpr(dHi),mkexpr(dLo)) |
| 12293 | ) |
| 12294 | ) |
| 12295 | ); |
| 12296 | goto decode_success; |
| 12297 | } |
| 12298 | |
| 12299 | /* 0F 38 0B = PMULHRSW -- Packed Multiply High with Round and Scale |
| 12300 | (MMX) */ |
| 12301 | if (sz == 4 |
| 12302 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x0B) { |
| 12303 | IRTemp sV = newTemp(Ity_I64); |
| 12304 | IRTemp dV = newTemp(Ity_I64); |
| 12305 | |
| 12306 | modrm = insn[3]; |
| 12307 | do_MMX_preamble(); |
| 12308 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 12309 | |
| 12310 | if (epartIsReg(modrm)) { |
| 12311 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12312 | delta += 3+1; |
| 12313 | DIP("pmulhrsw %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 12314 | nameMMXReg(gregOfRM(modrm))); |
| 12315 | } else { |
| 12316 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12317 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12318 | delta += 3+alen; |
| 12319 | DIP("pmulhrsw %s,%s\n", dis_buf, |
| 12320 | nameMMXReg(gregOfRM(modrm))); |
| 12321 | } |
| 12322 | |
| 12323 | putMMXReg( |
| 12324 | gregOfRM(modrm), |
| 12325 | dis_PMULHRSW_helper( mkexpr(sV), mkexpr(dV) ) |
| 12326 | ); |
| 12327 | goto decode_success; |
| 12328 | } |
| 12329 | |
| 12330 | /* 66 0F 38 0B = PMULHRSW -- Packed Multiply High with Round and |
| 12331 | Scale (XMM) */ |
| 12332 | if (sz == 2 |
| 12333 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x0B) { |
| 12334 | IRTemp sV = newTemp(Ity_V128); |
| 12335 | IRTemp dV = newTemp(Ity_V128); |
| 12336 | IRTemp sHi = newTemp(Ity_I64); |
| 12337 | IRTemp sLo = newTemp(Ity_I64); |
| 12338 | IRTemp dHi = newTemp(Ity_I64); |
| 12339 | IRTemp dLo = newTemp(Ity_I64); |
| 12340 | |
| 12341 | modrm = insn[3]; |
| 12342 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 12343 | |
| 12344 | if (epartIsReg(modrm)) { |
| 12345 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 12346 | delta += 3+1; |
| 12347 | DIP("pmulhrsw %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 12348 | nameXMMReg(gregOfRM(modrm))); |
| 12349 | } else { |
| 12350 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12351 | gen_SEGV_if_not_16_aligned( addr ); |
| 12352 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12353 | delta += 3+alen; |
| 12354 | DIP("pmulhrsw %s,%s\n", dis_buf, |
| 12355 | nameXMMReg(gregOfRM(modrm))); |
| 12356 | } |
| 12357 | |
| 12358 | assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 12359 | assign( dLo, unop(Iop_V128to64, mkexpr(dV)) ); |
| 12360 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12361 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12362 | |
| 12363 | putXMMReg( |
| 12364 | gregOfRM(modrm), |
| 12365 | binop(Iop_64HLtoV128, |
| 12366 | dis_PMULHRSW_helper( mkexpr(sHi), mkexpr(dHi) ), |
| 12367 | dis_PMULHRSW_helper( mkexpr(sLo), mkexpr(dLo) ) |
| 12368 | ) |
| 12369 | ); |
| 12370 | goto decode_success; |
| 12371 | } |
| 12372 | |
| 12373 | /* 0F 38 08 = PSIGNB -- Packed Sign 8x8 (MMX) */ |
| 12374 | /* 0F 38 09 = PSIGNW -- Packed Sign 16x4 (MMX) */ |
| 12375 | /* 0F 38 09 = PSIGND -- Packed Sign 32x2 (MMX) */ |
| 12376 | if (sz == 4 |
| 12377 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 12378 | && (insn[2] == 0x08 || insn[2] == 0x09 || insn[2] == 0x0A)) { |
| 12379 | IRTemp sV = newTemp(Ity_I64); |
| 12380 | IRTemp dV = newTemp(Ity_I64); |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 12381 | const HChar* str = "???"; |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12382 | Int laneszB = 0; |
| 12383 | |
| 12384 | switch (insn[2]) { |
| 12385 | case 0x08: laneszB = 1; str = "b"; break; |
| 12386 | case 0x09: laneszB = 2; str = "w"; break; |
| 12387 | case 0x0A: laneszB = 4; str = "d"; break; |
| 12388 | default: vassert(0); |
| 12389 | } |
| 12390 | |
| 12391 | modrm = insn[3]; |
| 12392 | do_MMX_preamble(); |
| 12393 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 12394 | |
| 12395 | if (epartIsReg(modrm)) { |
| 12396 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12397 | delta += 3+1; |
| 12398 | DIP("psign%s %s,%s\n", str, nameMMXReg(eregOfRM(modrm)), |
| 12399 | nameMMXReg(gregOfRM(modrm))); |
| 12400 | } else { |
| 12401 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12402 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12403 | delta += 3+alen; |
| 12404 | DIP("psign%s %s,%s\n", str, dis_buf, |
| 12405 | nameMMXReg(gregOfRM(modrm))); |
| 12406 | } |
| 12407 | |
| 12408 | putMMXReg( |
| 12409 | gregOfRM(modrm), |
| 12410 | dis_PSIGN_helper( mkexpr(sV), mkexpr(dV), laneszB ) |
| 12411 | ); |
| 12412 | goto decode_success; |
| 12413 | } |
| 12414 | |
| 12415 | /* 66 0F 38 08 = PSIGNB -- Packed Sign 8x16 (XMM) */ |
| 12416 | /* 66 0F 38 09 = PSIGNW -- Packed Sign 16x8 (XMM) */ |
| 12417 | /* 66 0F 38 09 = PSIGND -- Packed Sign 32x4 (XMM) */ |
| 12418 | if (sz == 2 |
| 12419 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 12420 | && (insn[2] == 0x08 || insn[2] == 0x09 || insn[2] == 0x0A)) { |
| 12421 | IRTemp sV = newTemp(Ity_V128); |
| 12422 | IRTemp dV = newTemp(Ity_V128); |
| 12423 | IRTemp sHi = newTemp(Ity_I64); |
| 12424 | IRTemp sLo = newTemp(Ity_I64); |
| 12425 | IRTemp dHi = newTemp(Ity_I64); |
| 12426 | IRTemp dLo = newTemp(Ity_I64); |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 12427 | const HChar* str = "???"; |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12428 | Int laneszB = 0; |
| 12429 | |
| 12430 | switch (insn[2]) { |
| 12431 | case 0x08: laneszB = 1; str = "b"; break; |
| 12432 | case 0x09: laneszB = 2; str = "w"; break; |
| 12433 | case 0x0A: laneszB = 4; str = "d"; break; |
| 12434 | default: vassert(0); |
| 12435 | } |
| 12436 | |
| 12437 | modrm = insn[3]; |
| 12438 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 12439 | |
| 12440 | if (epartIsReg(modrm)) { |
| 12441 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 12442 | delta += 3+1; |
| 12443 | DIP("psign%s %s,%s\n", str, nameXMMReg(eregOfRM(modrm)), |
| 12444 | nameXMMReg(gregOfRM(modrm))); |
| 12445 | } else { |
| 12446 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12447 | gen_SEGV_if_not_16_aligned( addr ); |
| 12448 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12449 | delta += 3+alen; |
| 12450 | DIP("psign%s %s,%s\n", str, dis_buf, |
| 12451 | nameXMMReg(gregOfRM(modrm))); |
| 12452 | } |
| 12453 | |
| 12454 | assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 12455 | assign( dLo, unop(Iop_V128to64, mkexpr(dV)) ); |
| 12456 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12457 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12458 | |
| 12459 | putXMMReg( |
| 12460 | gregOfRM(modrm), |
| 12461 | binop(Iop_64HLtoV128, |
| 12462 | dis_PSIGN_helper( mkexpr(sHi), mkexpr(dHi), laneszB ), |
| 12463 | dis_PSIGN_helper( mkexpr(sLo), mkexpr(dLo), laneszB ) |
| 12464 | ) |
| 12465 | ); |
| 12466 | goto decode_success; |
| 12467 | } |
| 12468 | |
| 12469 | /* 0F 38 1C = PABSB -- Packed Absolute Value 8x8 (MMX) */ |
| 12470 | /* 0F 38 1D = PABSW -- Packed Absolute Value 16x4 (MMX) */ |
| 12471 | /* 0F 38 1E = PABSD -- Packed Absolute Value 32x2 (MMX) */ |
| 12472 | if (sz == 4 |
| 12473 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 12474 | && (insn[2] == 0x1C || insn[2] == 0x1D || insn[2] == 0x1E)) { |
| 12475 | IRTemp sV = newTemp(Ity_I64); |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 12476 | const HChar* str = "???"; |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12477 | Int laneszB = 0; |
| 12478 | |
| 12479 | switch (insn[2]) { |
| 12480 | case 0x1C: laneszB = 1; str = "b"; break; |
| 12481 | case 0x1D: laneszB = 2; str = "w"; break; |
| 12482 | case 0x1E: laneszB = 4; str = "d"; break; |
| 12483 | default: vassert(0); |
| 12484 | } |
| 12485 | |
| 12486 | modrm = insn[3]; |
| 12487 | do_MMX_preamble(); |
| 12488 | |
| 12489 | if (epartIsReg(modrm)) { |
| 12490 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12491 | delta += 3+1; |
| 12492 | DIP("pabs%s %s,%s\n", str, nameMMXReg(eregOfRM(modrm)), |
| 12493 | nameMMXReg(gregOfRM(modrm))); |
| 12494 | } else { |
| 12495 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12496 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12497 | delta += 3+alen; |
| 12498 | DIP("pabs%s %s,%s\n", str, dis_buf, |
| 12499 | nameMMXReg(gregOfRM(modrm))); |
| 12500 | } |
| 12501 | |
| 12502 | putMMXReg( |
| 12503 | gregOfRM(modrm), |
| 12504 | dis_PABS_helper( mkexpr(sV), laneszB ) |
| 12505 | ); |
| 12506 | goto decode_success; |
| 12507 | } |
| 12508 | |
| 12509 | /* 66 0F 38 1C = PABSB -- Packed Absolute Value 8x16 (XMM) */ |
| 12510 | /* 66 0F 38 1D = PABSW -- Packed Absolute Value 16x8 (XMM) */ |
| 12511 | /* 66 0F 38 1E = PABSD -- Packed Absolute Value 32x4 (XMM) */ |
| 12512 | if (sz == 2 |
| 12513 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 12514 | && (insn[2] == 0x1C || insn[2] == 0x1D || insn[2] == 0x1E)) { |
| 12515 | IRTemp sV = newTemp(Ity_V128); |
| 12516 | IRTemp sHi = newTemp(Ity_I64); |
| 12517 | IRTemp sLo = newTemp(Ity_I64); |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 12518 | const HChar* str = "???"; |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12519 | Int laneszB = 0; |
| 12520 | |
| 12521 | switch (insn[2]) { |
| 12522 | case 0x1C: laneszB = 1; str = "b"; break; |
| 12523 | case 0x1D: laneszB = 2; str = "w"; break; |
| 12524 | case 0x1E: laneszB = 4; str = "d"; break; |
| 12525 | default: vassert(0); |
| 12526 | } |
| 12527 | |
| 12528 | modrm = insn[3]; |
| 12529 | |
| 12530 | if (epartIsReg(modrm)) { |
| 12531 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 12532 | delta += 3+1; |
| 12533 | DIP("pabs%s %s,%s\n", str, nameXMMReg(eregOfRM(modrm)), |
| 12534 | nameXMMReg(gregOfRM(modrm))); |
| 12535 | } else { |
| 12536 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12537 | gen_SEGV_if_not_16_aligned( addr ); |
| 12538 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12539 | delta += 3+alen; |
| 12540 | DIP("pabs%s %s,%s\n", str, dis_buf, |
| 12541 | nameXMMReg(gregOfRM(modrm))); |
| 12542 | } |
| 12543 | |
| 12544 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12545 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12546 | |
| 12547 | putXMMReg( |
| 12548 | gregOfRM(modrm), |
| 12549 | binop(Iop_64HLtoV128, |
| 12550 | dis_PABS_helper( mkexpr(sHi), laneszB ), |
| 12551 | dis_PABS_helper( mkexpr(sLo), laneszB ) |
| 12552 | ) |
| 12553 | ); |
| 12554 | goto decode_success; |
| 12555 | } |
| 12556 | |
| 12557 | /* 0F 3A 0F = PALIGNR -- Packed Align Right (MMX) */ |
| 12558 | if (sz == 4 |
| 12559 | && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0F) { |
| 12560 | IRTemp sV = newTemp(Ity_I64); |
| 12561 | IRTemp dV = newTemp(Ity_I64); |
| 12562 | IRTemp res = newTemp(Ity_I64); |
| 12563 | |
| 12564 | modrm = insn[3]; |
| 12565 | do_MMX_preamble(); |
| 12566 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 12567 | |
| 12568 | if (epartIsReg(modrm)) { |
| 12569 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12570 | d32 = (UInt)insn[3+1]; |
| 12571 | delta += 3+1+1; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 12572 | DIP("palignr $%u,%s,%s\n", d32, |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12573 | nameMMXReg(eregOfRM(modrm)), |
| 12574 | nameMMXReg(gregOfRM(modrm))); |
| 12575 | } else { |
| 12576 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12577 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12578 | d32 = (UInt)insn[3+alen]; |
| 12579 | delta += 3+alen+1; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 12580 | DIP("palignr $%u%s,%s\n", d32, |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12581 | dis_buf, |
| 12582 | nameMMXReg(gregOfRM(modrm))); |
| 12583 | } |
| 12584 | |
| 12585 | if (d32 == 0) { |
| 12586 | assign( res, mkexpr(sV) ); |
| 12587 | } |
| 12588 | else if (d32 >= 1 && d32 <= 7) { |
| 12589 | assign(res, |
| 12590 | binop(Iop_Or64, |
| 12591 | binop(Iop_Shr64, mkexpr(sV), mkU8(8*d32)), |
| 12592 | binop(Iop_Shl64, mkexpr(dV), mkU8(8*(8-d32)) |
| 12593 | ))); |
| 12594 | } |
| 12595 | else if (d32 == 8) { |
| 12596 | assign( res, mkexpr(dV) ); |
| 12597 | } |
| 12598 | else if (d32 >= 9 && d32 <= 15) { |
| 12599 | assign( res, binop(Iop_Shr64, mkexpr(dV), mkU8(8*(d32-8))) ); |
| 12600 | } |
| 12601 | else if (d32 >= 16 && d32 <= 255) { |
| 12602 | assign( res, mkU64(0) ); |
| 12603 | } |
| 12604 | else |
| 12605 | vassert(0); |
| 12606 | |
| 12607 | putMMXReg( gregOfRM(modrm), mkexpr(res) ); |
| 12608 | goto decode_success; |
| 12609 | } |
| 12610 | |
| 12611 | /* 66 0F 3A 0F = PALIGNR -- Packed Align Right (XMM) */ |
| 12612 | if (sz == 2 |
| 12613 | && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0F) { |
| 12614 | IRTemp sV = newTemp(Ity_V128); |
| 12615 | IRTemp dV = newTemp(Ity_V128); |
| 12616 | IRTemp sHi = newTemp(Ity_I64); |
| 12617 | IRTemp sLo = newTemp(Ity_I64); |
| 12618 | IRTemp dHi = newTemp(Ity_I64); |
| 12619 | IRTemp dLo = newTemp(Ity_I64); |
| 12620 | IRTemp rHi = newTemp(Ity_I64); |
| 12621 | IRTemp rLo = newTemp(Ity_I64); |
| 12622 | |
| 12623 | modrm = insn[3]; |
| 12624 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 12625 | |
| 12626 | if (epartIsReg(modrm)) { |
| 12627 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 12628 | d32 = (UInt)insn[3+1]; |
| 12629 | delta += 3+1+1; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 12630 | DIP("palignr $%u,%s,%s\n", d32, |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12631 | nameXMMReg(eregOfRM(modrm)), |
| 12632 | nameXMMReg(gregOfRM(modrm))); |
| 12633 | } else { |
| 12634 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12635 | gen_SEGV_if_not_16_aligned( addr ); |
| 12636 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12637 | d32 = (UInt)insn[3+alen]; |
| 12638 | delta += 3+alen+1; |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 12639 | DIP("palignr $%u,%s,%s\n", d32, |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12640 | dis_buf, |
| 12641 | nameXMMReg(gregOfRM(modrm))); |
| 12642 | } |
| 12643 | |
| 12644 | assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 12645 | assign( dLo, unop(Iop_V128to64, mkexpr(dV)) ); |
| 12646 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12647 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12648 | |
| 12649 | if (d32 == 0) { |
| 12650 | assign( rHi, mkexpr(sHi) ); |
| 12651 | assign( rLo, mkexpr(sLo) ); |
| 12652 | } |
| 12653 | else if (d32 >= 1 && d32 <= 7) { |
| 12654 | assign( rHi, dis_PALIGNR_XMM_helper(dLo, sHi, d32) ); |
| 12655 | assign( rLo, dis_PALIGNR_XMM_helper(sHi, sLo, d32) ); |
| 12656 | } |
| 12657 | else if (d32 == 8) { |
| 12658 | assign( rHi, mkexpr(dLo) ); |
| 12659 | assign( rLo, mkexpr(sHi) ); |
| 12660 | } |
| 12661 | else if (d32 >= 9 && d32 <= 15) { |
| 12662 | assign( rHi, dis_PALIGNR_XMM_helper(dHi, dLo, d32-8) ); |
| 12663 | assign( rLo, dis_PALIGNR_XMM_helper(dLo, sHi, d32-8) ); |
| 12664 | } |
| 12665 | else if (d32 == 16) { |
| 12666 | assign( rHi, mkexpr(dHi) ); |
| 12667 | assign( rLo, mkexpr(dLo) ); |
| 12668 | } |
| 12669 | else if (d32 >= 17 && d32 <= 23) { |
| 12670 | assign( rHi, binop(Iop_Shr64, mkexpr(dHi), mkU8(8*(d32-16))) ); |
| 12671 | assign( rLo, dis_PALIGNR_XMM_helper(dHi, dLo, d32-16) ); |
| 12672 | } |
| 12673 | else if (d32 == 24) { |
| 12674 | assign( rHi, mkU64(0) ); |
| 12675 | assign( rLo, mkexpr(dHi) ); |
| 12676 | } |
| 12677 | else if (d32 >= 25 && d32 <= 31) { |
| 12678 | assign( rHi, mkU64(0) ); |
| 12679 | assign( rLo, binop(Iop_Shr64, mkexpr(dHi), mkU8(8*(d32-24))) ); |
| 12680 | } |
| 12681 | else if (d32 >= 32 && d32 <= 255) { |
| 12682 | assign( rHi, mkU64(0) ); |
| 12683 | assign( rLo, mkU64(0) ); |
| 12684 | } |
| 12685 | else |
| 12686 | vassert(0); |
| 12687 | |
| 12688 | putXMMReg( |
| 12689 | gregOfRM(modrm), |
| 12690 | binop(Iop_64HLtoV128, mkexpr(rHi), mkexpr(rLo)) |
| 12691 | ); |
| 12692 | goto decode_success; |
| 12693 | } |
| 12694 | |
| 12695 | /* 0F 38 00 = PSHUFB -- Packed Shuffle Bytes 8x8 (MMX) */ |
| 12696 | if (sz == 4 |
| 12697 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x00) { |
| 12698 | IRTemp sV = newTemp(Ity_I64); |
| 12699 | IRTemp dV = newTemp(Ity_I64); |
| 12700 | |
| 12701 | modrm = insn[3]; |
| 12702 | do_MMX_preamble(); |
| 12703 | assign( dV, getMMXReg(gregOfRM(modrm)) ); |
| 12704 | |
| 12705 | if (epartIsReg(modrm)) { |
| 12706 | assign( sV, getMMXReg(eregOfRM(modrm)) ); |
| 12707 | delta += 3+1; |
| 12708 | DIP("pshufb %s,%s\n", nameMMXReg(eregOfRM(modrm)), |
| 12709 | nameMMXReg(gregOfRM(modrm))); |
| 12710 | } else { |
| 12711 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12712 | assign( sV, loadLE(Ity_I64, mkexpr(addr)) ); |
| 12713 | delta += 3+alen; |
| 12714 | DIP("pshufb %s,%s\n", dis_buf, |
| 12715 | nameMMXReg(gregOfRM(modrm))); |
| 12716 | } |
| 12717 | |
| 12718 | putMMXReg( |
| 12719 | gregOfRM(modrm), |
| 12720 | binop( |
| 12721 | Iop_And64, |
| 12722 | /* permute the lanes */ |
| 12723 | binop( |
| 12724 | Iop_Perm8x8, |
| 12725 | mkexpr(dV), |
| 12726 | binop(Iop_And64, mkexpr(sV), mkU64(0x0707070707070707ULL)) |
| 12727 | ), |
| 12728 | /* mask off lanes which have (index & 0x80) == 0x80 */ |
| 12729 | unop(Iop_Not64, binop(Iop_SarN8x8, mkexpr(sV), mkU8(7))) |
| 12730 | ) |
| 12731 | ); |
| 12732 | goto decode_success; |
| 12733 | } |
| 12734 | |
| 12735 | /* 66 0F 38 00 = PSHUFB -- Packed Shuffle Bytes 8x16 (XMM) */ |
| 12736 | if (sz == 2 |
| 12737 | && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x00) { |
| 12738 | IRTemp sV = newTemp(Ity_V128); |
| 12739 | IRTemp dV = newTemp(Ity_V128); |
| 12740 | IRTemp sHi = newTemp(Ity_I64); |
| 12741 | IRTemp sLo = newTemp(Ity_I64); |
| 12742 | IRTemp dHi = newTemp(Ity_I64); |
| 12743 | IRTemp dLo = newTemp(Ity_I64); |
| 12744 | IRTemp rHi = newTemp(Ity_I64); |
| 12745 | IRTemp rLo = newTemp(Ity_I64); |
| 12746 | IRTemp sevens = newTemp(Ity_I64); |
| 12747 | IRTemp mask0x80hi = newTemp(Ity_I64); |
| 12748 | IRTemp mask0x80lo = newTemp(Ity_I64); |
| 12749 | IRTemp maskBit3hi = newTemp(Ity_I64); |
| 12750 | IRTemp maskBit3lo = newTemp(Ity_I64); |
| 12751 | IRTemp sAnd7hi = newTemp(Ity_I64); |
| 12752 | IRTemp sAnd7lo = newTemp(Ity_I64); |
| 12753 | IRTemp permdHi = newTemp(Ity_I64); |
| 12754 | IRTemp permdLo = newTemp(Ity_I64); |
| 12755 | |
| 12756 | modrm = insn[3]; |
| 12757 | assign( dV, getXMMReg(gregOfRM(modrm)) ); |
| 12758 | |
| 12759 | if (epartIsReg(modrm)) { |
| 12760 | assign( sV, getXMMReg(eregOfRM(modrm)) ); |
| 12761 | delta += 3+1; |
| 12762 | DIP("pshufb %s,%s\n", nameXMMReg(eregOfRM(modrm)), |
| 12763 | nameXMMReg(gregOfRM(modrm))); |
| 12764 | } else { |
| 12765 | addr = disAMode ( &alen, sorb, delta+3, dis_buf ); |
| 12766 | gen_SEGV_if_not_16_aligned( addr ); |
| 12767 | assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); |
| 12768 | delta += 3+alen; |
| 12769 | DIP("pshufb %s,%s\n", dis_buf, |
| 12770 | nameXMMReg(gregOfRM(modrm))); |
| 12771 | } |
| 12772 | |
| 12773 | assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) ); |
| 12774 | assign( dLo, unop(Iop_V128to64, mkexpr(dV)) ); |
| 12775 | assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) ); |
| 12776 | assign( sLo, unop(Iop_V128to64, mkexpr(sV)) ); |
| 12777 | |
| 12778 | assign( sevens, mkU64(0x0707070707070707ULL) ); |
| 12779 | |
| 12780 | /* |
| 12781 | mask0x80hi = Not(SarN8x8(sHi,7)) |
| 12782 | maskBit3hi = SarN8x8(ShlN8x8(sHi,4),7) |
| 12783 | sAnd7hi = And(sHi,sevens) |
| 12784 | permdHi = Or( And(Perm8x8(dHi,sAnd7hi),maskBit3hi), |
| 12785 | And(Perm8x8(dLo,sAnd7hi),Not(maskBit3hi)) ) |
| 12786 | rHi = And(permdHi,mask0x80hi) |
| 12787 | */ |
| 12788 | assign( |
| 12789 | mask0x80hi, |
| 12790 | unop(Iop_Not64, binop(Iop_SarN8x8,mkexpr(sHi),mkU8(7)))); |
| 12791 | |
| 12792 | assign( |
| 12793 | maskBit3hi, |
| 12794 | binop(Iop_SarN8x8, |
| 12795 | binop(Iop_ShlN8x8,mkexpr(sHi),mkU8(4)), |
| 12796 | mkU8(7))); |
| 12797 | |
| 12798 | assign(sAnd7hi, binop(Iop_And64,mkexpr(sHi),mkexpr(sevens))); |
| 12799 | |
| 12800 | assign( |
| 12801 | permdHi, |
| 12802 | binop( |
| 12803 | Iop_Or64, |
| 12804 | binop(Iop_And64, |
| 12805 | binop(Iop_Perm8x8,mkexpr(dHi),mkexpr(sAnd7hi)), |
| 12806 | mkexpr(maskBit3hi)), |
| 12807 | binop(Iop_And64, |
| 12808 | binop(Iop_Perm8x8,mkexpr(dLo),mkexpr(sAnd7hi)), |
| 12809 | unop(Iop_Not64,mkexpr(maskBit3hi))) )); |
| 12810 | |
| 12811 | assign(rHi, binop(Iop_And64,mkexpr(permdHi),mkexpr(mask0x80hi)) ); |
| 12812 | |
| 12813 | /* And the same for the lower half of the result. What fun. */ |
| 12814 | |
| 12815 | assign( |
| 12816 | mask0x80lo, |
| 12817 | unop(Iop_Not64, binop(Iop_SarN8x8,mkexpr(sLo),mkU8(7)))); |
| 12818 | |
| 12819 | assign( |
| 12820 | maskBit3lo, |
| 12821 | binop(Iop_SarN8x8, |
| 12822 | binop(Iop_ShlN8x8,mkexpr(sLo),mkU8(4)), |
| 12823 | mkU8(7))); |
| 12824 | |
| 12825 | assign(sAnd7lo, binop(Iop_And64,mkexpr(sLo),mkexpr(sevens))); |
| 12826 | |
| 12827 | assign( |
| 12828 | permdLo, |
| 12829 | binop( |
| 12830 | Iop_Or64, |
| 12831 | binop(Iop_And64, |
| 12832 | binop(Iop_Perm8x8,mkexpr(dHi),mkexpr(sAnd7lo)), |
| 12833 | mkexpr(maskBit3lo)), |
| 12834 | binop(Iop_And64, |
| 12835 | binop(Iop_Perm8x8,mkexpr(dLo),mkexpr(sAnd7lo)), |
| 12836 | unop(Iop_Not64,mkexpr(maskBit3lo))) )); |
| 12837 | |
| 12838 | assign(rLo, binop(Iop_And64,mkexpr(permdLo),mkexpr(mask0x80lo)) ); |
| 12839 | |
| 12840 | putXMMReg( |
| 12841 | gregOfRM(modrm), |
| 12842 | binop(Iop_64HLtoV128, mkexpr(rHi), mkexpr(rLo)) |
| 12843 | ); |
| 12844 | goto decode_success; |
| 12845 | } |
sewardj | 021f6b4 | 2012-08-23 23:39:49 +0000 | [diff] [blame] | 12846 | |
| 12847 | /* 0F 38 F0 = MOVBE m16/32(E), r16/32(G) */ |
| 12848 | /* 0F 38 F1 = MOVBE r16/32(G), m16/32(E) */ |
| 12849 | if ((sz == 2 || sz == 4) |
| 12850 | && insn[0] == 0x0F && insn[1] == 0x38 |
| 12851 | && (insn[2] == 0xF0 || insn[2] == 0xF1) |
| 12852 | && !epartIsReg(insn[3])) { |
| 12853 | |
| 12854 | modrm = insn[3]; |
| 12855 | addr = disAMode(&alen, sorb, delta + 3, dis_buf); |
| 12856 | delta += 3 + alen; |
| 12857 | ty = szToITy(sz); |
| 12858 | IRTemp src = newTemp(ty); |
| 12859 | |
| 12860 | if (insn[2] == 0xF0) { /* LOAD */ |
| 12861 | assign(src, loadLE(ty, mkexpr(addr))); |
| 12862 | IRTemp dst = math_BSWAP(src, ty); |
| 12863 | putIReg(sz, gregOfRM(modrm), mkexpr(dst)); |
| 12864 | DIP("movbe %s,%s\n", dis_buf, nameIReg(sz, gregOfRM(modrm))); |
| 12865 | } else { /* STORE */ |
| 12866 | assign(src, getIReg(sz, gregOfRM(modrm))); |
| 12867 | IRTemp dst = math_BSWAP(src, ty); |
| 12868 | storeLE(mkexpr(addr), mkexpr(dst)); |
| 12869 | DIP("movbe %s,%s\n", nameIReg(sz, gregOfRM(modrm)), dis_buf); |
| 12870 | } |
| 12871 | goto decode_success; |
| 12872 | } |
sewardj | 150c9cd | 2008-02-09 01:16:02 +0000 | [diff] [blame] | 12873 | |
| 12874 | /* ---------------------------------------------------- */ |
| 12875 | /* --- end of the SSSE3 decoder. --- */ |
| 12876 | /* ---------------------------------------------------- */ |
| 12877 | |
sewardj | b727161 | 2010-07-23 21:23:25 +0000 | [diff] [blame] | 12878 | /* ---------------------------------------------------- */ |
| 12879 | /* --- start of the SSE4 decoder --- */ |
| 12880 | /* ---------------------------------------------------- */ |
| 12881 | |
| 12882 | /* 66 0F 3A 0B /r ib = ROUNDSD imm8, xmm2/m64, xmm1 |
| 12883 | (Partial implementation only -- only deal with cases where |
| 12884 | the rounding mode is specified directly by the immediate byte.) |
| 12885 | 66 0F 3A 0A /r ib = ROUNDSS imm8, xmm2/m32, xmm1 |
| 12886 | (Limitations ditto) |
| 12887 | */ |
| 12888 | if (sz == 2 |
| 12889 | && insn[0] == 0x0F && insn[1] == 0x3A |
rhyskidd | e66a247 | 2015-08-15 07:39:27 +0000 | [diff] [blame] | 12890 | && (insn[2] == 0x0B || insn[2] == 0x0A)) { |
sewardj | b727161 | 2010-07-23 21:23:25 +0000 | [diff] [blame] | 12891 | |
| 12892 | Bool isD = insn[2] == 0x0B; |
| 12893 | IRTemp src = newTemp(isD ? Ity_F64 : Ity_F32); |
| 12894 | IRTemp res = newTemp(isD ? Ity_F64 : Ity_F32); |
| 12895 | Int imm = 0; |
| 12896 | |
| 12897 | modrm = insn[3]; |
| 12898 | |
| 12899 | if (epartIsReg(modrm)) { |
| 12900 | assign( src, |
| 12901 | isD ? getXMMRegLane64F( eregOfRM(modrm), 0 ) |
| 12902 | : getXMMRegLane32F( eregOfRM(modrm), 0 ) ); |
| 12903 | imm = insn[3+1]; |
| 12904 | if (imm & ~3) goto decode_failure; |
| 12905 | delta += 3+1+1; |
| 12906 | DIP( "rounds%c $%d,%s,%s\n", |
| 12907 | isD ? 'd' : 's', |
| 12908 | imm, nameXMMReg( eregOfRM(modrm) ), |
| 12909 | nameXMMReg( gregOfRM(modrm) ) ); |
| 12910 | } else { |
| 12911 | addr = disAMode( &alen, sorb, delta+3, dis_buf ); |
| 12912 | assign( src, loadLE( isD ? Ity_F64 : Ity_F32, mkexpr(addr) )); |
| 12913 | imm = insn[3+alen]; |
| 12914 | if (imm & ~3) goto decode_failure; |
| 12915 | delta += 3+alen+1; |
| 12916 | DIP( "roundsd $%d,%s,%s\n", |
| 12917 | imm, dis_buf, nameXMMReg( gregOfRM(modrm) ) ); |
| 12918 | } |
| 12919 | |
| 12920 | /* (imm & 3) contains an Intel-encoded rounding mode. Because |
| 12921 | that encoding is the same as the encoding for IRRoundingMode, |
| 12922 | we can use that value directly in the IR as a rounding |
| 12923 | mode. */ |
| 12924 | assign(res, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt, |
| 12925 | mkU32(imm & 3), mkexpr(src)) ); |
| 12926 | |
| 12927 | if (isD) |
| 12928 | putXMMRegLane64F( gregOfRM(modrm), 0, mkexpr(res) ); |
| 12929 | else |
| 12930 | putXMMRegLane32F( gregOfRM(modrm), 0, mkexpr(res) ); |
| 12931 | |
| 12932 | goto decode_success; |
| 12933 | } |
| 12934 | |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 12935 | /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension, |
| 12936 | which we can only decode if we're sure this is an AMD cpu that |
| 12937 | supports LZCNT, since otherwise it's BSR, which behaves |
| 12938 | differently. */ |
| 12939 | if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xBD |
| 12940 | && 0 != (archinfo->hwcaps & VEX_HWCAPS_X86_LZCNT)) { |
sewardj | 9a660ea | 2010-07-29 11:34:38 +0000 | [diff] [blame] | 12941 | vassert(sz == 2 || sz == 4); |
| 12942 | /*IRType*/ ty = szToITy(sz); |
| 12943 | IRTemp src = newTemp(ty); |
| 12944 | modrm = insn[3]; |
| 12945 | if (epartIsReg(modrm)) { |
| 12946 | assign(src, getIReg(sz, eregOfRM(modrm))); |
| 12947 | delta += 3+1; |
| 12948 | DIP("lzcnt%c %s, %s\n", nameISize(sz), |
| 12949 | nameIReg(sz, eregOfRM(modrm)), |
| 12950 | nameIReg(sz, gregOfRM(modrm))); |
| 12951 | } else { |
| 12952 | addr = disAMode( &alen, sorb, delta+3, dis_buf ); |
| 12953 | assign(src, loadLE(ty, mkexpr(addr))); |
| 12954 | delta += 3+alen; |
| 12955 | DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf, |
| 12956 | nameIReg(sz, gregOfRM(modrm))); |
| 12957 | } |
| 12958 | |
| 12959 | IRTemp res = gen_LZCNT(ty, src); |
| 12960 | putIReg(sz, gregOfRM(modrm), mkexpr(res)); |
| 12961 | |
| 12962 | // Update flags. This is pretty lame .. perhaps can do better |
| 12963 | // if this turns out to be performance critical. |
| 12964 | // O S A P are cleared. Z is set if RESULT == 0. |
| 12965 | // C is set if SRC is zero. |
| 12966 | IRTemp src32 = newTemp(Ity_I32); |
| 12967 | IRTemp res32 = newTemp(Ity_I32); |
| 12968 | assign(src32, widenUto32(mkexpr(src))); |
| 12969 | assign(res32, widenUto32(mkexpr(res))); |
| 12970 | |
| 12971 | IRTemp oszacp = newTemp(Ity_I32); |
| 12972 | assign( |
| 12973 | oszacp, |
| 12974 | binop(Iop_Or32, |
| 12975 | binop(Iop_Shl32, |
| 12976 | unop(Iop_1Uto32, |
| 12977 | binop(Iop_CmpEQ32, mkexpr(res32), mkU32(0))), |
| 12978 | mkU8(X86G_CC_SHIFT_Z)), |
| 12979 | binop(Iop_Shl32, |
| 12980 | unop(Iop_1Uto32, |
| 12981 | binop(Iop_CmpEQ32, mkexpr(src32), mkU32(0))), |
| 12982 | mkU8(X86G_CC_SHIFT_C)) |
| 12983 | ) |
| 12984 | ); |
| 12985 | |
| 12986 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 12987 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 12988 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 12989 | stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(oszacp) )); |
| 12990 | |
| 12991 | goto decode_success; |
| 12992 | } |
| 12993 | |
sewardj | b727161 | 2010-07-23 21:23:25 +0000 | [diff] [blame] | 12994 | /* ---------------------------------------------------- */ |
| 12995 | /* --- end of the SSE4 decoder --- */ |
| 12996 | /* ---------------------------------------------------- */ |
| 12997 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 12998 | after_sse_decoders: |
| 12999 | |
sewardj | dc5d084 | 2006-11-16 10:42:02 +0000 | [diff] [blame] | 13000 | /* ---------------------------------------------------- */ |
| 13001 | /* --- deal with misc 0x67 pfxs (addr size override) -- */ |
| 13002 | /* ---------------------------------------------------- */ |
| 13003 | |
| 13004 | /* 67 E3 = JCXZ (for JECXZ see below) */ |
| 13005 | if (insn[0] == 0x67 && insn[1] == 0xE3 && sz == 4) { |
| 13006 | delta += 2; |
| 13007 | d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta); |
| 13008 | delta ++; |
| 13009 | stmt( IRStmt_Exit( |
| 13010 | binop(Iop_CmpEQ16, getIReg(2,R_ECX), mkU16(0)), |
| 13011 | Ijk_Boring, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13012 | IRConst_U32(d32), |
| 13013 | OFFB_EIP |
sewardj | dc5d084 | 2006-11-16 10:42:02 +0000 | [diff] [blame] | 13014 | )); |
| 13015 | DIP("jcxz 0x%x\n", d32); |
| 13016 | goto decode_success; |
| 13017 | } |
| 13018 | |
| 13019 | /* ---------------------------------------------------- */ |
| 13020 | /* --- start of the baseline insn decoder -- */ |
| 13021 | /* ---------------------------------------------------- */ |
| 13022 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 13023 | /* Get the primary opcode. */ |
| 13024 | opc = getIByte(delta); delta++; |
| 13025 | |
| 13026 | /* We get here if the current insn isn't SSE, or this CPU doesn't |
| 13027 | support SSE. */ |
| 13028 | |
| 13029 | switch (opc) { |
| 13030 | |
| 13031 | /* ------------------------ Control flow --------------- */ |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13032 | |
| 13033 | case 0xC2: /* RET imm16 */ |
| 13034 | d32 = getUDisp16(delta); |
| 13035 | delta += 2; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13036 | dis_ret(&dres, d32); |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 13037 | DIP("ret %u\n", d32); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13038 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13039 | case 0xC3: /* RET */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13040 | dis_ret(&dres, 0); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13041 | DIP("ret\n"); |
| 13042 | break; |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 13043 | |
| 13044 | case 0xCF: /* IRET */ |
| 13045 | /* Note, this is an extremely kludgey and limited implementation |
| 13046 | of iret. All it really does is: |
| 13047 | popl %EIP; popl %CS; popl %EFLAGS. |
| 13048 | %CS is set but ignored (as it is in (eg) popw %cs)". */ |
| 13049 | t1 = newTemp(Ity_I32); /* ESP */ |
| 13050 | t2 = newTemp(Ity_I32); /* new EIP */ |
| 13051 | t3 = newTemp(Ity_I32); /* new CS */ |
| 13052 | t4 = newTemp(Ity_I32); /* new EFLAGS */ |
| 13053 | assign(t1, getIReg(4,R_ESP)); |
| 13054 | assign(t2, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t1),mkU32(0) ))); |
| 13055 | assign(t3, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t1),mkU32(4) ))); |
| 13056 | assign(t4, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t1),mkU32(8) ))); |
| 13057 | /* Get stuff off stack */ |
| 13058 | putIReg(4, R_ESP,binop(Iop_Add32, mkexpr(t1), mkU32(12))); |
| 13059 | /* set %CS (which is ignored anyway) */ |
| 13060 | putSReg( R_CS, unop(Iop_32to16, mkexpr(t3)) ); |
| 13061 | /* set %EFLAGS */ |
| 13062 | set_EFLAGS_from_value( t4, False/*!emit_AC_emwarn*/, 0/*unused*/ ); |
| 13063 | /* goto new EIP value */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13064 | jmp_treg(&dres, Ijk_Ret, t2); |
| 13065 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 13066 | DIP("iret (very kludgey)\n"); |
| 13067 | break; |
| 13068 | |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 13069 | case 0xE8: /* CALL J4 */ |
| 13070 | d32 = getUDisp32(delta); delta += 4; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13071 | d32 += (guest_EIP_bbstart+delta); |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13072 | /* (guest_eip_bbstart+delta) == return-to addr, d32 == call-to addr */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13073 | if (d32 == guest_EIP_bbstart+delta && getIByte(delta) >= 0x58 |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13074 | && getIByte(delta) <= 0x5F) { |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 13075 | /* Specially treat the position-independent-code idiom |
| 13076 | call X |
| 13077 | X: popl %reg |
| 13078 | as |
| 13079 | movl %eip, %reg. |
| 13080 | since this generates better code, but for no other reason. */ |
| 13081 | Int archReg = getIByte(delta) - 0x58; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13082 | /* vex_printf("-- fPIC thingy\n"); */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13083 | putIReg(4, archReg, mkU32(guest_EIP_bbstart+delta)); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 13084 | delta++; /* Step over the POP */ |
| 13085 | DIP("call 0x%x ; popl %s\n",d32,nameIReg(4,archReg)); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13086 | } else { |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 13087 | /* The normal sequence for a call. */ |
| 13088 | t1 = newTemp(Ity_I32); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 13089 | assign(t1, binop(Iop_Sub32, getIReg(4,R_ESP), mkU32(4))); |
| 13090 | putIReg(4, R_ESP, mkexpr(t1)); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13091 | storeLE( mkexpr(t1), mkU32(guest_EIP_bbstart+delta)); |
florian | beac530 | 2014-12-31 12:09:38 +0000 | [diff] [blame] | 13092 | if (resteerOkFn( callback_opaque, (Addr32)d32 )) { |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13093 | /* follow into the call target. */ |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13094 | dres.whatNext = Dis_ResteerU; |
florian | 0eaa35f | 2015-01-02 13:34:15 +0000 | [diff] [blame] | 13095 | dres.continueAt = (Addr32)d32; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13096 | } else { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13097 | jmp_lit(&dres, Ijk_Call, d32); |
| 13098 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13099 | } |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 13100 | DIP("call 0x%x\n",d32); |
| 13101 | } |
| 13102 | break; |
| 13103 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 13104 | //-- case 0xC8: /* ENTER */ |
| 13105 | //-- d32 = getUDisp16(eip); eip += 2; |
| 13106 | //-- abyte = getIByte(delta); delta++; |
| 13107 | //-- |
| 13108 | //-- vg_assert(sz == 4); |
| 13109 | //-- vg_assert(abyte == 0); |
| 13110 | //-- |
| 13111 | //-- t1 = newTemp(cb); t2 = newTemp(cb); |
| 13112 | //-- uInstr2(cb, GET, sz, ArchReg, R_EBP, TempReg, t1); |
| 13113 | //-- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t2); |
| 13114 | //-- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2); |
| 13115 | //-- uLiteral(cb, sz); |
| 13116 | //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP); |
| 13117 | //-- uInstr2(cb, STORE, 4, TempReg, t1, TempReg, t2); |
| 13118 | //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_EBP); |
| 13119 | //-- if (d32) { |
| 13120 | //-- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 13121 | //-- uLiteral(cb, d32); |
| 13122 | //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP); |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 13123 | //-- } |
| 13124 | //-- DIP("enter 0x%x, 0x%x", d32, abyte); |
| 13125 | //-- break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13126 | |
| 13127 | case 0xC9: /* LEAVE */ |
| 13128 | vassert(sz == 4); |
| 13129 | t1 = newTemp(Ity_I32); t2 = newTemp(Ity_I32); |
| 13130 | assign(t1, getIReg(4,R_EBP)); |
| 13131 | /* First PUT ESP looks redundant, but need it because ESP must |
| 13132 | always be up-to-date for Memcheck to work... */ |
| 13133 | putIReg(4, R_ESP, mkexpr(t1)); |
| 13134 | assign(t2, loadLE(Ity_I32,mkexpr(t1))); |
| 13135 | putIReg(4, R_EBP, mkexpr(t2)); |
| 13136 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t1), mkU32(4)) ); |
| 13137 | DIP("leave\n"); |
| 13138 | break; |
| 13139 | |
sewardj | 8edc36b | 2007-11-23 02:46:29 +0000 | [diff] [blame] | 13140 | /* ---------------- Misc weird-ass insns --------------- */ |
| 13141 | |
| 13142 | case 0x27: /* DAA */ |
| 13143 | case 0x2F: /* DAS */ |
| 13144 | case 0x37: /* AAA */ |
| 13145 | case 0x3F: /* AAS */ |
| 13146 | /* An ugly implementation for some ugly instructions. Oh |
| 13147 | well. */ |
| 13148 | if (sz != 4) goto decode_failure; |
| 13149 | t1 = newTemp(Ity_I32); |
| 13150 | t2 = newTemp(Ity_I32); |
| 13151 | /* Make up a 32-bit value (t1), with the old value of AX in the |
| 13152 | bottom 16 bits, and the old OSZACP bitmask in the upper 16 |
| 13153 | bits. */ |
| 13154 | assign(t1, |
| 13155 | binop(Iop_16HLto32, |
| 13156 | unop(Iop_32to16, |
| 13157 | mk_x86g_calculate_eflags_all()), |
| 13158 | getIReg(2, R_EAX) |
| 13159 | )); |
| 13160 | /* Call the helper fn, to get a new AX and OSZACP value, and |
| 13161 | poke both back into the guest state. Also pass the helper |
| 13162 | the actual opcode so it knows which of the 4 instructions it |
| 13163 | is doing the computation for. */ |
| 13164 | vassert(opc == 0x27 || opc == 0x2F || opc == 0x37 || opc == 0x3F); |
| 13165 | assign(t2, |
| 13166 | mkIRExprCCall( |
| 13167 | Ity_I32, 0/*regparm*/, "x86g_calculate_daa_das_aaa_aas", |
| 13168 | &x86g_calculate_daa_das_aaa_aas, |
| 13169 | mkIRExprVec_2( mkexpr(t1), mkU32( opc & 0xFF) ) |
| 13170 | )); |
| 13171 | putIReg(2, R_EAX, unop(Iop_32to16, mkexpr(t2) )); |
| 13172 | |
| 13173 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 13174 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 13175 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
| 13176 | binop(Iop_And32, |
| 13177 | binop(Iop_Shr32, mkexpr(t2), mkU8(16)), |
| 13178 | mkU32( X86G_CC_MASK_C | X86G_CC_MASK_P |
| 13179 | | X86G_CC_MASK_A | X86G_CC_MASK_Z |
| 13180 | | X86G_CC_MASK_S| X86G_CC_MASK_O ) |
| 13181 | ) |
| 13182 | ) |
| 13183 | ); |
| 13184 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 13185 | elimination of previous stores to this field work better. */ |
| 13186 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 13187 | switch (opc) { |
| 13188 | case 0x27: DIP("daa\n"); break; |
| 13189 | case 0x2F: DIP("das\n"); break; |
| 13190 | case 0x37: DIP("aaa\n"); break; |
| 13191 | case 0x3F: DIP("aas\n"); break; |
| 13192 | default: vassert(0); |
| 13193 | } |
| 13194 | break; |
| 13195 | |
sewardj | 321bbbf | 2011-01-17 12:32:25 +0000 | [diff] [blame] | 13196 | case 0xD4: /* AAM */ |
| 13197 | case 0xD5: /* AAD */ |
| 13198 | d32 = getIByte(delta); delta++; |
| 13199 | if (sz != 4 || d32 != 10) goto decode_failure; |
| 13200 | t1 = newTemp(Ity_I32); |
| 13201 | t2 = newTemp(Ity_I32); |
| 13202 | /* Make up a 32-bit value (t1), with the old value of AX in the |
| 13203 | bottom 16 bits, and the old OSZACP bitmask in the upper 16 |
| 13204 | bits. */ |
| 13205 | assign(t1, |
| 13206 | binop(Iop_16HLto32, |
| 13207 | unop(Iop_32to16, |
| 13208 | mk_x86g_calculate_eflags_all()), |
| 13209 | getIReg(2, R_EAX) |
| 13210 | )); |
| 13211 | /* Call the helper fn, to get a new AX and OSZACP value, and |
| 13212 | poke both back into the guest state. Also pass the helper |
| 13213 | the actual opcode so it knows which of the 2 instructions it |
| 13214 | is doing the computation for. */ |
| 13215 | assign(t2, |
| 13216 | mkIRExprCCall( |
| 13217 | Ity_I32, 0/*regparm*/, "x86g_calculate_aad_aam", |
| 13218 | &x86g_calculate_aad_aam, |
| 13219 | mkIRExprVec_2( mkexpr(t1), mkU32( opc & 0xFF) ) |
| 13220 | )); |
| 13221 | putIReg(2, R_EAX, unop(Iop_32to16, mkexpr(t2) )); |
| 13222 | |
| 13223 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 13224 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 13225 | stmt( IRStmt_Put( OFFB_CC_DEP1, |
| 13226 | binop(Iop_And32, |
| 13227 | binop(Iop_Shr32, mkexpr(t2), mkU8(16)), |
| 13228 | mkU32( X86G_CC_MASK_C | X86G_CC_MASK_P |
| 13229 | | X86G_CC_MASK_A | X86G_CC_MASK_Z |
| 13230 | | X86G_CC_MASK_S| X86G_CC_MASK_O ) |
| 13231 | ) |
| 13232 | ) |
| 13233 | ); |
| 13234 | /* Set NDEP even though it isn't used. This makes |
| 13235 | redundant-PUT elimination of previous stores to this field |
| 13236 | work better. */ |
| 13237 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 13238 | |
| 13239 | DIP(opc == 0xD4 ? "aam\n" : "aad\n"); |
| 13240 | break; |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 13241 | |
| 13242 | /* ------------------------ CWD/CDQ -------------------- */ |
| 13243 | |
| 13244 | case 0x98: /* CBW */ |
| 13245 | if (sz == 4) { |
| 13246 | putIReg(4, R_EAX, unop(Iop_16Sto32, getIReg(2, R_EAX))); |
| 13247 | DIP("cwde\n"); |
| 13248 | } else { |
sewardj | 4734104 | 2004-09-19 11:55:46 +0000 | [diff] [blame] | 13249 | vassert(sz == 2); |
| 13250 | putIReg(2, R_EAX, unop(Iop_8Sto16, getIReg(1, R_EAX))); |
| 13251 | DIP("cbw\n"); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 13252 | } |
| 13253 | break; |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 13254 | |
| 13255 | case 0x99: /* CWD/CDQ */ |
| 13256 | ty = szToITy(sz); |
| 13257 | putIReg(sz, R_EDX, |
| 13258 | binop(mkSizedOp(ty,Iop_Sar8), |
| 13259 | getIReg(sz, R_EAX), |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 13260 | mkU8(sz == 2 ? 15 : 31)) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 13261 | DIP(sz == 2 ? "cwdq\n" : "cdqq\n"); |
| 13262 | break; |
| 13263 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 13264 | /* ------------------------ FPU ops -------------------- */ |
| 13265 | |
| 13266 | case 0x9E: /* SAHF */ |
| 13267 | codegen_SAHF(); |
| 13268 | DIP("sahf\n"); |
| 13269 | break; |
| 13270 | |
sewardj | 8dfdc8a | 2005-10-03 11:39:02 +0000 | [diff] [blame] | 13271 | case 0x9F: /* LAHF */ |
| 13272 | codegen_LAHF(); |
| 13273 | DIP("lahf\n"); |
| 13274 | break; |
| 13275 | |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 13276 | case 0x9B: /* FWAIT */ |
| 13277 | /* ignore? */ |
| 13278 | DIP("fwait\n"); |
| 13279 | break; |
| 13280 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 13281 | case 0xD8: |
| 13282 | case 0xD9: |
| 13283 | case 0xDA: |
| 13284 | case 0xDB: |
| 13285 | case 0xDC: |
| 13286 | case 0xDD: |
| 13287 | case 0xDE: |
| 13288 | case 0xDF: { |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 13289 | Int delta0 = delta; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 13290 | Bool decode_OK = False; |
| 13291 | delta = dis_FPU ( &decode_OK, sorb, delta ); |
| 13292 | if (!decode_OK) { |
| 13293 | delta = delta0; |
| 13294 | goto decode_failure; |
| 13295 | } |
| 13296 | break; |
| 13297 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13298 | |
| 13299 | /* ------------------------ INC & DEC ------------------ */ |
| 13300 | |
| 13301 | case 0x40: /* INC eAX */ |
| 13302 | case 0x41: /* INC eCX */ |
| 13303 | case 0x42: /* INC eDX */ |
| 13304 | case 0x43: /* INC eBX */ |
| 13305 | case 0x44: /* INC eSP */ |
| 13306 | case 0x45: /* INC eBP */ |
| 13307 | case 0x46: /* INC eSI */ |
| 13308 | case 0x47: /* INC eDI */ |
| 13309 | vassert(sz == 2 || sz == 4); |
| 13310 | ty = szToITy(sz); |
| 13311 | t1 = newTemp(ty); |
| 13312 | assign( t1, binop(mkSizedOp(ty,Iop_Add8), |
| 13313 | getIReg(sz, (UInt)(opc - 0x40)), |
| 13314 | mkU(ty,1)) ); |
| 13315 | setFlags_INC_DEC( True, t1, ty ); |
| 13316 | putIReg(sz, (UInt)(opc - 0x40), mkexpr(t1)); |
| 13317 | DIP("inc%c %s\n", nameISize(sz), nameIReg(sz,opc-0x40)); |
| 13318 | break; |
| 13319 | |
| 13320 | case 0x48: /* DEC eAX */ |
| 13321 | case 0x49: /* DEC eCX */ |
| 13322 | case 0x4A: /* DEC eDX */ |
| 13323 | case 0x4B: /* DEC eBX */ |
| 13324 | case 0x4C: /* DEC eSP */ |
| 13325 | case 0x4D: /* DEC eBP */ |
| 13326 | case 0x4E: /* DEC eSI */ |
| 13327 | case 0x4F: /* DEC eDI */ |
| 13328 | vassert(sz == 2 || sz == 4); |
| 13329 | ty = szToITy(sz); |
| 13330 | t1 = newTemp(ty); |
| 13331 | assign( t1, binop(mkSizedOp(ty,Iop_Sub8), |
| 13332 | getIReg(sz, (UInt)(opc - 0x48)), |
| 13333 | mkU(ty,1)) ); |
| 13334 | setFlags_INC_DEC( False, t1, ty ); |
| 13335 | putIReg(sz, (UInt)(opc - 0x48), mkexpr(t1)); |
| 13336 | DIP("dec%c %s\n", nameISize(sz), nameIReg(sz,opc-0x48)); |
| 13337 | break; |
| 13338 | |
| 13339 | /* ------------------------ INT ------------------------ */ |
| 13340 | |
sewardj | 322bfa0 | 2007-02-28 23:31:42 +0000 | [diff] [blame] | 13341 | case 0xCC: /* INT 3 */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13342 | jmp_lit(&dres, Ijk_SigTRAP, ((Addr32)guest_EIP_bbstart)+delta); |
| 13343 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | 322bfa0 | 2007-02-28 23:31:42 +0000 | [diff] [blame] | 13344 | DIP("int $0x3\n"); |
| 13345 | break; |
| 13346 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13347 | case 0xCD: /* INT imm8 */ |
| 13348 | d32 = getIByte(delta); delta++; |
sewardj | 0f50004 | 2007-08-29 09:09:17 +0000 | [diff] [blame] | 13349 | |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13350 | /* For any of the cases where we emit a jump (that is, for all |
| 13351 | currently handled cases), it's important that all ArchRegs |
| 13352 | carry their up-to-date value at this point. So we declare an |
| 13353 | end-of-block here, which forces any TempRegs caching ArchRegs |
| 13354 | to be flushed. */ |
| 13355 | |
sewardj | 84af676 | 2012-02-16 12:36:47 +0000 | [diff] [blame] | 13356 | /* Handle int $0x3F .. $0x4F by synthesising a segfault and a |
sewardj | 0f50004 | 2007-08-29 09:09:17 +0000 | [diff] [blame] | 13357 | restart of this instruction (hence the "-2" two lines below, |
| 13358 | to get the restart EIP to be this instruction. This is |
| 13359 | probably Linux-specific and it would be more correct to only |
sewardj | 84af676 | 2012-02-16 12:36:47 +0000 | [diff] [blame] | 13360 | do this if the VexAbiInfo says that is what we should do. |
| 13361 | This used to handle just 0x40-0x43; Jikes RVM uses a larger |
| 13362 | range (0x3F-0x49), and this allows some slack as well. */ |
| 13363 | if (d32 >= 0x3F && d32 <= 0x4F) { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13364 | jmp_lit(&dres, Ijk_SigSEGV, ((Addr32)guest_EIP_bbstart)+delta-2); |
| 13365 | vassert(dres.whatNext == Dis_StopHere); |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 13366 | DIP("int $0x%x\n", d32); |
sewardj | 0f50004 | 2007-08-29 09:09:17 +0000 | [diff] [blame] | 13367 | break; |
| 13368 | } |
| 13369 | |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13370 | /* Handle int $0x80 (linux syscalls), int $0x81 and $0x82 |
sewardj | 3e5d82d | 2015-07-21 14:43:23 +0000 | [diff] [blame] | 13371 | (darwin syscalls), int $0x91 (Solaris syscalls) and int $0xD2 |
| 13372 | (Solaris fasttrap syscalls). As part of this, note where we are, so we |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 13373 | can back up the guest to this point if the syscall needs to |
| 13374 | be restarted. */ |
sewardj | 3e5d82d | 2015-07-21 14:43:23 +0000 | [diff] [blame] | 13375 | IRJumpKind jump_kind; |
| 13376 | switch (d32) { |
| 13377 | case 0x80: |
| 13378 | jump_kind = Ijk_Sys_int128; |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13379 | break; |
sewardj | 3e5d82d | 2015-07-21 14:43:23 +0000 | [diff] [blame] | 13380 | case 0x81: |
| 13381 | jump_kind = Ijk_Sys_int129; |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13382 | break; |
sewardj | 3e5d82d | 2015-07-21 14:43:23 +0000 | [diff] [blame] | 13383 | case 0x82: |
| 13384 | jump_kind = Ijk_Sys_int130; |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13385 | break; |
sewardj | 3e5d82d | 2015-07-21 14:43:23 +0000 | [diff] [blame] | 13386 | case 0x91: |
| 13387 | jump_kind = Ijk_Sys_int145; |
| 13388 | break; |
| 13389 | case 0xD2: |
| 13390 | jump_kind = Ijk_Sys_int210; |
| 13391 | break; |
| 13392 | default: |
| 13393 | /* none of the above */ |
| 13394 | goto decode_failure; |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 13395 | } |
| 13396 | |
sewardj | 3e5d82d | 2015-07-21 14:43:23 +0000 | [diff] [blame] | 13397 | stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL, |
| 13398 | mkU32(guest_EIP_curr_instr) ) ); |
| 13399 | jmp_lit(&dres, jump_kind, ((Addr32)guest_EIP_bbstart)+delta); |
| 13400 | vassert(dres.whatNext == Dis_StopHere); |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 13401 | DIP("int $0x%x\n", d32); |
sewardj | 3e5d82d | 2015-07-21 14:43:23 +0000 | [diff] [blame] | 13402 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13403 | |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13404 | /* ------------------------ Jcond, byte offset --------- */ |
| 13405 | |
| 13406 | case 0xEB: /* Jb (jump, byte offset) */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13407 | d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13408 | delta++; |
florian | beac530 | 2014-12-31 12:09:38 +0000 | [diff] [blame] | 13409 | if (resteerOkFn( callback_opaque, (Addr32)d32) ) { |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13410 | dres.whatNext = Dis_ResteerU; |
florian | 0eaa35f | 2015-01-02 13:34:15 +0000 | [diff] [blame] | 13411 | dres.continueAt = (Addr32)d32; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13412 | } else { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13413 | jmp_lit(&dres, Ijk_Boring, d32); |
| 13414 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13415 | } |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13416 | DIP("jmp-8 0x%x\n", d32); |
| 13417 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13418 | |
| 13419 | case 0xE9: /* Jv (jump, 16/32 offset) */ |
| 13420 | vassert(sz == 4); /* JRS added 2004 July 11 */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13421 | d32 = (((Addr32)guest_EIP_bbstart)+delta+sz) + getSDisp(sz,delta); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13422 | delta += sz; |
florian | beac530 | 2014-12-31 12:09:38 +0000 | [diff] [blame] | 13423 | if (resteerOkFn( callback_opaque, (Addr32)d32) ) { |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13424 | dres.whatNext = Dis_ResteerU; |
florian | 0eaa35f | 2015-01-02 13:34:15 +0000 | [diff] [blame] | 13425 | dres.continueAt = (Addr32)d32; |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13426 | } else { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13427 | jmp_lit(&dres, Ijk_Boring, d32); |
| 13428 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | ce70a5c | 2004-10-18 14:09:54 +0000 | [diff] [blame] | 13429 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13430 | DIP("jmp 0x%x\n", d32); |
| 13431 | break; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13432 | |
| 13433 | case 0x70: |
| 13434 | case 0x71: |
| 13435 | case 0x72: /* JBb/JNAEb (jump below) */ |
| 13436 | case 0x73: /* JNBb/JAEb (jump not below) */ |
| 13437 | case 0x74: /* JZb/JEb (jump zero) */ |
| 13438 | case 0x75: /* JNZb/JNEb (jump not zero) */ |
| 13439 | case 0x76: /* JBEb/JNAb (jump below or equal) */ |
| 13440 | case 0x77: /* JNBEb/JAb (jump not below or equal) */ |
| 13441 | case 0x78: /* JSb (jump negative) */ |
| 13442 | case 0x79: /* JSb (jump not negative) */ |
| 13443 | case 0x7A: /* JP (jump parity even) */ |
| 13444 | case 0x7B: /* JNP/JPO (jump parity odd) */ |
| 13445 | case 0x7C: /* JLb/JNGEb (jump less) */ |
| 13446 | case 0x7D: /* JGEb/JNLb (jump greater or equal) */ |
| 13447 | case 0x7E: /* JLEb/JNGb (jump less or equal) */ |
| 13448 | case 0x7F: /* JGb/JNLEb (jump greater) */ |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13449 | { Int jmpDelta; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 13450 | const HChar* comment = ""; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13451 | jmpDelta = (Int)getSDisp8(delta); |
| 13452 | vassert(-128 <= jmpDelta && jmpDelta < 128); |
| 13453 | d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + jmpDelta; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13454 | delta++; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13455 | if (resteerCisOk |
| 13456 | && vex_control.guest_chase_cond |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 13457 | && (Addr32)d32 != (Addr32)guest_EIP_bbstart |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13458 | && jmpDelta < 0 |
florian | beac530 | 2014-12-31 12:09:38 +0000 | [diff] [blame] | 13459 | && resteerOkFn( callback_opaque, (Addr32)d32) ) { |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13460 | /* Speculation: assume this backward branch is taken. So we |
| 13461 | need to emit a side-exit to the insn following this one, |
| 13462 | on the negation of the condition, and continue at the |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 13463 | branch target address (d32). If we wind up back at the |
| 13464 | first instruction of the trace, just stop; it's better to |
| 13465 | let the IR loop unroller handle that case. */ |
sewardj | dbf550c | 2005-01-24 11:54:11 +0000 | [diff] [blame] | 13466 | stmt( IRStmt_Exit( |
| 13467 | mk_x86g_calculate_condition((X86Condcode)(1 ^ (opc - 0x70))), |
| 13468 | Ijk_Boring, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13469 | IRConst_U32(guest_EIP_bbstart+delta), |
| 13470 | OFFB_EIP ) ); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13471 | dres.whatNext = Dis_ResteerC; |
florian | 0eaa35f | 2015-01-02 13:34:15 +0000 | [diff] [blame] | 13472 | dres.continueAt = (Addr32)d32; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13473 | comment = "(assumed taken)"; |
| 13474 | } |
| 13475 | else |
| 13476 | if (resteerCisOk |
| 13477 | && vex_control.guest_chase_cond |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 13478 | && (Addr32)d32 != (Addr32)guest_EIP_bbstart |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13479 | && jmpDelta >= 0 |
| 13480 | && resteerOkFn( callback_opaque, |
florian | beac530 | 2014-12-31 12:09:38 +0000 | [diff] [blame] | 13481 | (Addr32)(guest_EIP_bbstart+delta)) ) { |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13482 | /* Speculation: assume this forward branch is not taken. So |
| 13483 | we need to emit a side-exit to d32 (the dest) and continue |
| 13484 | disassembling at the insn immediately following this |
| 13485 | one. */ |
| 13486 | stmt( IRStmt_Exit( |
| 13487 | mk_x86g_calculate_condition((X86Condcode)(opc - 0x70)), |
| 13488 | Ijk_Boring, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13489 | IRConst_U32(d32), |
| 13490 | OFFB_EIP ) ); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13491 | dres.whatNext = Dis_ResteerC; |
florian | 0eaa35f | 2015-01-02 13:34:15 +0000 | [diff] [blame] | 13492 | dres.continueAt = guest_EIP_bbstart + delta; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13493 | comment = "(assumed not taken)"; |
| 13494 | } |
| 13495 | else { |
| 13496 | /* Conservative default translation - end the block at this |
| 13497 | point. */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13498 | jcc_01( &dres, (X86Condcode)(opc - 0x70), |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13499 | (Addr32)(guest_EIP_bbstart+delta), d32); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13500 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | dbf550c | 2005-01-24 11:54:11 +0000 | [diff] [blame] | 13501 | } |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13502 | DIP("j%s-8 0x%x %s\n", name_X86Condcode(opc - 0x70), d32, comment); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13503 | break; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 13504 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13505 | |
sewardj | dc5d084 | 2006-11-16 10:42:02 +0000 | [diff] [blame] | 13506 | case 0xE3: /* JECXZ (for JCXZ see above) */ |
sewardj | baa6608 | 2005-08-23 17:29:27 +0000 | [diff] [blame] | 13507 | if (sz != 4) goto decode_failure; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 13508 | d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta); |
sewardj | dc5d084 | 2006-11-16 10:42:02 +0000 | [diff] [blame] | 13509 | delta ++; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 13510 | stmt( IRStmt_Exit( |
sewardj | dc5d084 | 2006-11-16 10:42:02 +0000 | [diff] [blame] | 13511 | binop(Iop_CmpEQ32, getIReg(4,R_ECX), mkU32(0)), |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 13512 | Ijk_Boring, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13513 | IRConst_U32(d32), |
| 13514 | OFFB_EIP |
sewardj | dc5d084 | 2006-11-16 10:42:02 +0000 | [diff] [blame] | 13515 | )); |
| 13516 | DIP("jecxz 0x%x\n", d32); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 13517 | break; |
| 13518 | |
sewardj | baa6608 | 2005-08-23 17:29:27 +0000 | [diff] [blame] | 13519 | case 0xE0: /* LOOPNE disp8: decrement count, jump if count != 0 && ZF==0 */ |
| 13520 | case 0xE1: /* LOOPE disp8: decrement count, jump if count != 0 && ZF==1 */ |
| 13521 | case 0xE2: /* LOOP disp8: decrement count, jump if count != 0 */ |
| 13522 | { /* Again, the docs say this uses ECX/CX as a count depending on |
| 13523 | the address size override, not the operand one. Since we |
| 13524 | don't handle address size overrides, I guess that means |
| 13525 | ECX. */ |
| 13526 | IRExpr* zbit = NULL; |
| 13527 | IRExpr* count = NULL; |
| 13528 | IRExpr* cond = NULL; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 13529 | const HChar* xtra = NULL; |
sewardj | baa6608 | 2005-08-23 17:29:27 +0000 | [diff] [blame] | 13530 | |
| 13531 | if (sz != 4) goto decode_failure; |
| 13532 | d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta); |
| 13533 | delta++; |
| 13534 | putIReg(4, R_ECX, binop(Iop_Sub32, getIReg(4,R_ECX), mkU32(1))); |
| 13535 | |
| 13536 | count = getIReg(4,R_ECX); |
| 13537 | cond = binop(Iop_CmpNE32, count, mkU32(0)); |
| 13538 | switch (opc) { |
| 13539 | case 0xE2: |
| 13540 | xtra = ""; |
| 13541 | break; |
| 13542 | case 0xE1: |
| 13543 | xtra = "e"; |
| 13544 | zbit = mk_x86g_calculate_condition( X86CondZ ); |
| 13545 | cond = mkAnd1(cond, zbit); |
| 13546 | break; |
| 13547 | case 0xE0: |
| 13548 | xtra = "ne"; |
| 13549 | zbit = mk_x86g_calculate_condition( X86CondNZ ); |
| 13550 | cond = mkAnd1(cond, zbit); |
| 13551 | break; |
| 13552 | default: |
| 13553 | vassert(0); |
| 13554 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 13555 | stmt( IRStmt_Exit(cond, Ijk_Boring, IRConst_U32(d32), OFFB_EIP) ); |
sewardj | baa6608 | 2005-08-23 17:29:27 +0000 | [diff] [blame] | 13556 | |
| 13557 | DIP("loop%s 0x%x\n", xtra, d32); |
| 13558 | break; |
| 13559 | } |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 13560 | |
| 13561 | /* ------------------------ IMUL ----------------------- */ |
| 13562 | |
| 13563 | case 0x69: /* IMUL Iv, Ev, Gv */ |
| 13564 | delta = dis_imul_I_E_G ( sorb, sz, delta, sz ); |
| 13565 | break; |
| 13566 | case 0x6B: /* IMUL Ib, Ev, Gv */ |
| 13567 | delta = dis_imul_I_E_G ( sorb, sz, delta, 1 ); |
| 13568 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13569 | |
| 13570 | /* ------------------------ MOV ------------------------ */ |
| 13571 | |
| 13572 | case 0x88: /* MOV Gb,Eb */ |
| 13573 | delta = dis_mov_G_E(sorb, 1, delta); |
| 13574 | break; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 13575 | |
| 13576 | case 0x89: /* MOV Gv,Ev */ |
| 13577 | delta = dis_mov_G_E(sorb, sz, delta); |
| 13578 | break; |
| 13579 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13580 | case 0x8A: /* MOV Eb,Gb */ |
| 13581 | delta = dis_mov_E_G(sorb, 1, delta); |
| 13582 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13583 | |
| 13584 | case 0x8B: /* MOV Ev,Gv */ |
| 13585 | delta = dis_mov_E_G(sorb, sz, delta); |
| 13586 | break; |
| 13587 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13588 | case 0x8D: /* LEA M,Gv */ |
sewardj | e9460bd | 2005-01-28 13:45:42 +0000 | [diff] [blame] | 13589 | if (sz != 4) |
| 13590 | goto decode_failure; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13591 | modrm = getIByte(delta); |
| 13592 | if (epartIsReg(modrm)) |
sewardj | e9460bd | 2005-01-28 13:45:42 +0000 | [diff] [blame] | 13593 | goto decode_failure; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13594 | /* NOTE! this is the one place where a segment override prefix |
| 13595 | has no effect on the address calculation. Therefore we pass |
| 13596 | zero instead of sorb here. */ |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13597 | addr = disAMode ( &alen, /*sorb*/ 0, delta, dis_buf ); |
| 13598 | delta += alen; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13599 | putIReg(sz, gregOfRM(modrm), mkexpr(addr)); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13600 | DIP("lea%c %s, %s\n", nameISize(sz), dis_buf, |
| 13601 | nameIReg(sz,gregOfRM(modrm))); |
| 13602 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13603 | |
sewardj | 063f02f | 2004-10-20 12:36:12 +0000 | [diff] [blame] | 13604 | case 0x8C: /* MOV Sw,Ew -- MOV from a SEGMENT REGISTER */ |
| 13605 | delta = dis_mov_Sw_Ew(sorb, sz, delta); |
| 13606 | break; |
| 13607 | |
sewardj | 7df596b | 2004-12-06 14:29:12 +0000 | [diff] [blame] | 13608 | case 0x8E: /* MOV Ew,Sw -- MOV to a SEGMENT REGISTER */ |
| 13609 | delta = dis_mov_Ew_Sw(sorb, delta); |
| 13610 | break; |
| 13611 | |
sewardj | 4385281 | 2004-10-16 23:10:08 +0000 | [diff] [blame] | 13612 | case 0xA0: /* MOV Ob,AL */ |
| 13613 | sz = 1; |
| 13614 | /* Fall through ... */ |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 13615 | case 0xA1: /* MOV Ov,eAX */ |
| 13616 | d32 = getUDisp32(delta); delta += 4; |
| 13617 | ty = szToITy(sz); |
| 13618 | addr = newTemp(Ity_I32); |
| 13619 | assign( addr, handleSegOverride(sorb, mkU32(d32)) ); |
| 13620 | putIReg(sz, R_EAX, loadLE(ty, mkexpr(addr))); |
| 13621 | DIP("mov%c %s0x%x, %s\n", nameISize(sz), sorbTxt(sorb), |
| 13622 | d32, nameIReg(sz,R_EAX)); |
| 13623 | break; |
| 13624 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13625 | case 0xA2: /* MOV Ob,AL */ |
| 13626 | sz = 1; |
| 13627 | /* Fall through ... */ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 13628 | case 0xA3: /* MOV eAX,Ov */ |
| 13629 | d32 = getUDisp32(delta); delta += 4; |
| 13630 | ty = szToITy(sz); |
| 13631 | addr = newTemp(Ity_I32); |
| 13632 | assign( addr, handleSegOverride(sorb, mkU32(d32)) ); |
| 13633 | storeLE( mkexpr(addr), getIReg(sz,R_EAX) ); |
| 13634 | DIP("mov%c %s, %s0x%x\n", nameISize(sz), nameIReg(sz,R_EAX), |
| 13635 | sorbTxt(sorb), d32); |
| 13636 | break; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13637 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13638 | case 0xB0: /* MOV imm,AL */ |
| 13639 | case 0xB1: /* MOV imm,CL */ |
| 13640 | case 0xB2: /* MOV imm,DL */ |
| 13641 | case 0xB3: /* MOV imm,BL */ |
| 13642 | case 0xB4: /* MOV imm,AH */ |
| 13643 | case 0xB5: /* MOV imm,CH */ |
| 13644 | case 0xB6: /* MOV imm,DH */ |
| 13645 | case 0xB7: /* MOV imm,BH */ |
| 13646 | d32 = getIByte(delta); delta += 1; |
| 13647 | putIReg(1, opc-0xB0, mkU8(d32)); |
| 13648 | DIP("movb $0x%x,%s\n", d32, nameIReg(1,opc-0xB0)); |
| 13649 | break; |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 13650 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13651 | case 0xB8: /* MOV imm,eAX */ |
| 13652 | case 0xB9: /* MOV imm,eCX */ |
| 13653 | case 0xBA: /* MOV imm,eDX */ |
| 13654 | case 0xBB: /* MOV imm,eBX */ |
| 13655 | case 0xBC: /* MOV imm,eSP */ |
| 13656 | case 0xBD: /* MOV imm,eBP */ |
| 13657 | case 0xBE: /* MOV imm,eSI */ |
| 13658 | case 0xBF: /* MOV imm,eDI */ |
| 13659 | d32 = getUDisp(sz,delta); delta += sz; |
| 13660 | putIReg(sz, opc-0xB8, mkU(szToITy(sz), d32)); |
| 13661 | DIP("mov%c $0x%x,%s\n", nameISize(sz), d32, nameIReg(sz,opc-0xB8)); |
| 13662 | break; |
| 13663 | |
sewardj | 1bf44e3 | 2013-09-18 18:27:55 +0000 | [diff] [blame] | 13664 | case 0xC6: /* C6 /0 = MOV Ib,Eb */ |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13665 | sz = 1; |
sewardj | 1bf44e3 | 2013-09-18 18:27:55 +0000 | [diff] [blame] | 13666 | goto maybe_do_Mov_I_E; |
| 13667 | case 0xC7: /* C7 /0 = MOV Iv,Ev */ |
| 13668 | goto maybe_do_Mov_I_E; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13669 | |
sewardj | 1bf44e3 | 2013-09-18 18:27:55 +0000 | [diff] [blame] | 13670 | maybe_do_Mov_I_E: |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13671 | modrm = getIByte(delta); |
sewardj | 1bf44e3 | 2013-09-18 18:27:55 +0000 | [diff] [blame] | 13672 | if (gregOfRM(modrm) == 0) { |
| 13673 | if (epartIsReg(modrm)) { |
| 13674 | delta++; /* mod/rm byte */ |
| 13675 | d32 = getUDisp(sz,delta); delta += sz; |
| 13676 | putIReg(sz, eregOfRM(modrm), mkU(szToITy(sz), d32)); |
| 13677 | DIP("mov%c $0x%x, %s\n", nameISize(sz), d32, |
| 13678 | nameIReg(sz,eregOfRM(modrm))); |
| 13679 | } else { |
| 13680 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 13681 | delta += alen; |
| 13682 | d32 = getUDisp(sz,delta); delta += sz; |
| 13683 | storeLE(mkexpr(addr), mkU(szToITy(sz), d32)); |
| 13684 | DIP("mov%c $0x%x, %s\n", nameISize(sz), d32, dis_buf); |
| 13685 | } |
| 13686 | break; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13687 | } |
sewardj | 1bf44e3 | 2013-09-18 18:27:55 +0000 | [diff] [blame] | 13688 | goto decode_failure; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13689 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 13690 | /* ------------------------ opl imm, A ----------------- */ |
| 13691 | |
| 13692 | case 0x04: /* ADD Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13693 | delta = dis_op_imm_A( 1, False, Iop_Add8, True, delta, "add" ); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 13694 | break; |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13695 | case 0x05: /* ADD Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13696 | delta = dis_op_imm_A( sz, False, Iop_Add8, True, delta, "add" ); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13697 | break; |
| 13698 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13699 | case 0x0C: /* OR Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13700 | delta = dis_op_imm_A( 1, False, Iop_Or8, True, delta, "or" ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13701 | break; |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 13702 | case 0x0D: /* OR Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13703 | delta = dis_op_imm_A( sz, False, Iop_Or8, True, delta, "or" ); |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 13704 | break; |
| 13705 | |
sewardj | eca2036 | 2005-08-24 09:22:39 +0000 | [diff] [blame] | 13706 | case 0x14: /* ADC Ib, AL */ |
| 13707 | delta = dis_op_imm_A( 1, True, Iop_Add8, True, delta, "adc" ); |
| 13708 | break; |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13709 | case 0x15: /* ADC Iv, eAX */ |
sewardj | eca2036 | 2005-08-24 09:22:39 +0000 | [diff] [blame] | 13710 | delta = dis_op_imm_A( sz, True, Iop_Add8, True, delta, "adc" ); |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13711 | break; |
| 13712 | |
sewardj | 2fbae08 | 2005-10-03 02:07:08 +0000 | [diff] [blame] | 13713 | case 0x1C: /* SBB Ib, AL */ |
| 13714 | delta = dis_op_imm_A( 1, True, Iop_Sub8, True, delta, "sbb" ); |
| 13715 | break; |
| 13716 | case 0x1D: /* SBB Iv, eAX */ |
| 13717 | delta = dis_op_imm_A( sz, True, Iop_Sub8, True, delta, "sbb" ); |
| 13718 | break; |
| 13719 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13720 | case 0x24: /* AND Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13721 | delta = dis_op_imm_A( 1, False, Iop_And8, True, delta, "and" ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13722 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13723 | case 0x25: /* AND Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13724 | delta = dis_op_imm_A( sz, False, Iop_And8, True, delta, "and" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13725 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13726 | |
| 13727 | case 0x2C: /* SUB Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13728 | delta = dis_op_imm_A( 1, False, Iop_Sub8, True, delta, "sub" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13729 | break; |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 13730 | case 0x2D: /* SUB Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13731 | delta = dis_op_imm_A( sz, False, Iop_Sub8, True, delta, "sub" ); |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 13732 | break; |
| 13733 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 13734 | case 0x34: /* XOR Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13735 | delta = dis_op_imm_A( 1, False, Iop_Xor8, True, delta, "xor" ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 13736 | break; |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13737 | case 0x35: /* XOR Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13738 | delta = dis_op_imm_A( sz, False, Iop_Xor8, True, delta, "xor" ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13739 | break; |
| 13740 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13741 | case 0x3C: /* CMP Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13742 | delta = dis_op_imm_A( 1, False, Iop_Sub8, False, delta, "cmp" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13743 | break; |
| 13744 | case 0x3D: /* CMP Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13745 | delta = dis_op_imm_A( sz, False, Iop_Sub8, False, delta, "cmp" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13746 | break; |
| 13747 | |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13748 | case 0xA8: /* TEST Ib, AL */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13749 | delta = dis_op_imm_A( 1, False, Iop_And8, False, delta, "test" ); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 13750 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13751 | case 0xA9: /* TEST Iv, eAX */ |
sewardj | a718d5d | 2005-04-03 14:59:54 +0000 | [diff] [blame] | 13752 | delta = dis_op_imm_A( sz, False, Iop_And8, False, delta, "test" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13753 | break; |
| 13754 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 13755 | /* ------------------------ opl Ev, Gv ----------------- */ |
| 13756 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 13757 | case 0x02: /* ADD Eb,Gb */ |
| 13758 | delta = dis_op2_E_G ( sorb, False, Iop_Add8, True, 1, delta, "add" ); |
| 13759 | break; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 13760 | case 0x03: /* ADD Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13761 | delta = dis_op2_E_G ( sorb, False, Iop_Add8, True, sz, delta, "add" ); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 13762 | break; |
| 13763 | |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 13764 | case 0x0A: /* OR Eb,Gb */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13765 | delta = dis_op2_E_G ( sorb, False, Iop_Or8, True, 1, delta, "or" ); |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 13766 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13767 | case 0x0B: /* OR Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13768 | delta = dis_op2_E_G ( sorb, False, Iop_Or8, True, sz, delta, "or" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13769 | break; |
sewardj | 2fbae08 | 2005-10-03 02:07:08 +0000 | [diff] [blame] | 13770 | |
| 13771 | case 0x12: /* ADC Eb,Gb */ |
| 13772 | delta = dis_op2_E_G ( sorb, True, Iop_Add8, True, 1, delta, "adc" ); |
| 13773 | break; |
sewardj | c4eaff3 | 2004-09-10 20:25:11 +0000 | [diff] [blame] | 13774 | case 0x13: /* ADC Ev,Gv */ |
| 13775 | delta = dis_op2_E_G ( sorb, True, Iop_Add8, True, sz, delta, "adc" ); |
| 13776 | break; |
| 13777 | |
sewardj | 2fbae08 | 2005-10-03 02:07:08 +0000 | [diff] [blame] | 13778 | case 0x1A: /* SBB Eb,Gb */ |
| 13779 | delta = dis_op2_E_G ( sorb, True, Iop_Sub8, True, 1, delta, "sbb" ); |
| 13780 | break; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13781 | case 0x1B: /* SBB Ev,Gv */ |
| 13782 | delta = dis_op2_E_G ( sorb, True, Iop_Sub8, True, sz, delta, "sbb" ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13783 | break; |
| 13784 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 13785 | case 0x22: /* AND Eb,Gb */ |
| 13786 | delta = dis_op2_E_G ( sorb, False, Iop_And8, True, 1, delta, "and" ); |
| 13787 | break; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13788 | case 0x23: /* AND Ev,Gv */ |
| 13789 | delta = dis_op2_E_G ( sorb, False, Iop_And8, True, sz, delta, "and" ); |
| 13790 | break; |
| 13791 | |
| 13792 | case 0x2A: /* SUB Eb,Gb */ |
| 13793 | delta = dis_op2_E_G ( sorb, False, Iop_Sub8, True, 1, delta, "sub" ); |
| 13794 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13795 | case 0x2B: /* SUB Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13796 | delta = dis_op2_E_G ( sorb, False, Iop_Sub8, True, sz, delta, "sub" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13797 | break; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13798 | |
| 13799 | case 0x32: /* XOR Eb,Gb */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13800 | delta = dis_op2_E_G ( sorb, False, Iop_Xor8, True, 1, delta, "xor" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13801 | break; |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 13802 | case 0x33: /* XOR Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13803 | delta = dis_op2_E_G ( sorb, False, Iop_Xor8, True, sz, delta, "xor" ); |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 13804 | break; |
| 13805 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13806 | case 0x3A: /* CMP Eb,Gb */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13807 | delta = dis_op2_E_G ( sorb, False, Iop_Sub8, False, 1, delta, "cmp" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13808 | break; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 13809 | case 0x3B: /* CMP Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13810 | delta = dis_op2_E_G ( sorb, False, Iop_Sub8, False, sz, delta, "cmp" ); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 13811 | break; |
| 13812 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13813 | case 0x84: /* TEST Eb,Gb */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13814 | delta = dis_op2_E_G ( sorb, False, Iop_And8, False, 1, delta, "test" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13815 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13816 | case 0x85: /* TEST Ev,Gv */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13817 | delta = dis_op2_E_G ( sorb, False, Iop_And8, False, sz, delta, "test" ); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13818 | break; |
| 13819 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13820 | /* ------------------------ opl Gv, Ev ----------------- */ |
| 13821 | |
| 13822 | case 0x00: /* ADD Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13823 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13824 | Iop_Add8, True, 1, delta, "add" ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13825 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13826 | case 0x01: /* ADD Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13827 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13828 | Iop_Add8, True, sz, delta, "add" ); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13829 | break; |
| 13830 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13831 | case 0x08: /* OR Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13832 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13833 | Iop_Or8, True, 1, delta, "or" ); |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 13834 | break; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 13835 | case 0x09: /* OR Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13836 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13837 | Iop_Or8, True, sz, delta, "or" ); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 13838 | break; |
| 13839 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13840 | case 0x10: /* ADC Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13841 | delta = dis_op2_G_E ( sorb, pfx_lock, True, |
| 13842 | Iop_Add8, True, 1, delta, "adc" ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13843 | break; |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13844 | case 0x11: /* ADC Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13845 | delta = dis_op2_G_E ( sorb, pfx_lock, True, |
| 13846 | Iop_Add8, True, sz, delta, "adc" ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13847 | break; |
| 13848 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13849 | case 0x18: /* SBB Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13850 | delta = dis_op2_G_E ( sorb, pfx_lock, True, |
| 13851 | Iop_Sub8, True, 1, delta, "sbb" ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13852 | break; |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13853 | case 0x19: /* SBB Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13854 | delta = dis_op2_G_E ( sorb, pfx_lock, True, |
| 13855 | Iop_Sub8, True, sz, delta, "sbb" ); |
sewardj | caca9d0 | 2004-07-28 07:11:32 +0000 | [diff] [blame] | 13856 | break; |
| 13857 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13858 | case 0x20: /* AND Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13859 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13860 | Iop_And8, True, 1, delta, "and" ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13861 | break; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13862 | case 0x21: /* AND Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13863 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13864 | Iop_And8, True, sz, delta, "and" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13865 | break; |
| 13866 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13867 | case 0x28: /* SUB Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13868 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13869 | Iop_Sub8, True, 1, delta, "sub" ); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 13870 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13871 | case 0x29: /* SUB Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13872 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13873 | Iop_Sub8, True, sz, delta, "sub" ); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 13874 | break; |
| 13875 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13876 | case 0x30: /* XOR Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13877 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13878 | Iop_Xor8, True, 1, delta, "xor" ); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 13879 | break; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13880 | case 0x31: /* XOR Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13881 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13882 | Iop_Xor8, True, sz, delta, "xor" ); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 13883 | break; |
| 13884 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13885 | case 0x38: /* CMP Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13886 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13887 | Iop_Sub8, False, 1, delta, "cmp" ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 13888 | break; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 13889 | case 0x39: /* CMP Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 13890 | delta = dis_op2_G_E ( sorb, pfx_lock, False, |
| 13891 | Iop_Sub8, False, sz, delta, "cmp" ); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 13892 | break; |
| 13893 | |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 13894 | /* ------------------------ POP ------------------------ */ |
| 13895 | |
| 13896 | case 0x58: /* POP eAX */ |
| 13897 | case 0x59: /* POP eCX */ |
| 13898 | case 0x5A: /* POP eDX */ |
| 13899 | case 0x5B: /* POP eBX */ |
| 13900 | case 0x5D: /* POP eBP */ |
| 13901 | case 0x5E: /* POP eSI */ |
| 13902 | case 0x5F: /* POP eDI */ |
| 13903 | case 0x5C: /* POP eSP */ |
| 13904 | vassert(sz == 2 || sz == 4); |
| 13905 | t1 = newTemp(szToITy(sz)); t2 = newTemp(Ity_I32); |
| 13906 | assign(t2, getIReg(4, R_ESP)); |
| 13907 | assign(t1, loadLE(szToITy(sz),mkexpr(t2))); |
| 13908 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t2), mkU32(sz))); |
| 13909 | putIReg(sz, opc-0x58, mkexpr(t1)); |
| 13910 | DIP("pop%c %s\n", nameISize(sz), nameIReg(sz,opc-0x58)); |
| 13911 | break; |
| 13912 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13913 | case 0x9D: /* POPF */ |
| 13914 | vassert(sz == 2 || sz == 4); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13915 | t1 = newTemp(Ity_I32); t2 = newTemp(Ity_I32); |
| 13916 | assign(t2, getIReg(4, R_ESP)); |
sewardj | c22a6fd | 2004-07-29 23:41:47 +0000 | [diff] [blame] | 13917 | assign(t1, widenUto32(loadLE(szToITy(sz),mkexpr(t2)))); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13918 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t2), mkU32(sz))); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13919 | |
sewardj | 0e9a0f5 | 2008-01-04 01:22:41 +0000 | [diff] [blame] | 13920 | /* Generate IR to set %EFLAGS{O,S,Z,A,C,P,D,ID,AC} from the |
| 13921 | value in t1. */ |
| 13922 | set_EFLAGS_from_value( t1, True/*emit_AC_emwarn*/, |
| 13923 | ((Addr32)guest_EIP_bbstart)+delta ); |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 13924 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 13925 | DIP("popf%c\n", nameISize(sz)); |
| 13926 | break; |
| 13927 | |
sewardj | bbdc622 | 2004-12-15 18:43:39 +0000 | [diff] [blame] | 13928 | case 0x61: /* POPA */ |
| 13929 | /* This is almost certainly wrong for sz==2. So ... */ |
| 13930 | if (sz != 4) goto decode_failure; |
| 13931 | |
| 13932 | /* t5 is the old %ESP value. */ |
| 13933 | t5 = newTemp(Ity_I32); |
| 13934 | assign( t5, getIReg(4, R_ESP) ); |
| 13935 | |
| 13936 | /* Reload all the registers, except %esp. */ |
| 13937 | putIReg(4,R_EAX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(28)) )); |
| 13938 | putIReg(4,R_ECX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(24)) )); |
| 13939 | putIReg(4,R_EDX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(20)) )); |
| 13940 | putIReg(4,R_EBX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(16)) )); |
| 13941 | /* ignore saved %ESP */ |
| 13942 | putIReg(4,R_EBP, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32( 8)) )); |
| 13943 | putIReg(4,R_ESI, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32( 4)) )); |
| 13944 | putIReg(4,R_EDI, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32( 0)) )); |
| 13945 | |
| 13946 | /* and move %ESP back up */ |
| 13947 | putIReg( 4, R_ESP, binop(Iop_Add32, mkexpr(t5), mkU32(8*4)) ); |
| 13948 | |
sewardj | a3d1a66 | 2005-03-29 21:33:11 +0000 | [diff] [blame] | 13949 | DIP("popa%c\n", nameISize(sz)); |
sewardj | bbdc622 | 2004-12-15 18:43:39 +0000 | [diff] [blame] | 13950 | break; |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13951 | |
| 13952 | case 0x8F: /* POPL/POPW m32 */ |
sewardj | fcff178 | 2006-05-12 14:04:48 +0000 | [diff] [blame] | 13953 | { Int len; |
| 13954 | UChar rm = getIByte(delta); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13955 | |
| 13956 | /* make sure this instruction is correct POP */ |
sewardj | fcff178 | 2006-05-12 14:04:48 +0000 | [diff] [blame] | 13957 | if (epartIsReg(rm) || gregOfRM(rm) != 0) |
| 13958 | goto decode_failure; |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13959 | /* and has correct size */ |
sewardj | fcff178 | 2006-05-12 14:04:48 +0000 | [diff] [blame] | 13960 | if (sz != 4 && sz != 2) |
| 13961 | goto decode_failure; |
| 13962 | ty = szToITy(sz); |
| 13963 | |
| 13964 | t1 = newTemp(Ity_I32); /* stack address */ |
| 13965 | t3 = newTemp(ty); /* data */ |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13966 | /* set t1 to ESP: t1 = ESP */ |
| 13967 | assign( t1, getIReg(4, R_ESP) ); |
| 13968 | /* load M[ESP] to virtual register t3: t3 = M[t1] */ |
sewardj | fcff178 | 2006-05-12 14:04:48 +0000 | [diff] [blame] | 13969 | assign( t3, loadLE(ty, mkexpr(t1)) ); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13970 | |
| 13971 | /* increase ESP; must be done before the STORE. Intel manual says: |
| 13972 | If the ESP register is used as a base register for addressing |
| 13973 | a destination operand in memory, the POP instruction computes |
| 13974 | the effective address of the operand after it increments the |
| 13975 | ESP register. |
| 13976 | */ |
| 13977 | putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t1), mkU32(sz)) ); |
| 13978 | |
| 13979 | /* resolve MODR/M */ |
| 13980 | addr = disAMode ( &len, sorb, delta, dis_buf); |
| 13981 | storeLE( mkexpr(addr), mkexpr(t3) ); |
| 13982 | |
sewardj | fcff178 | 2006-05-12 14:04:48 +0000 | [diff] [blame] | 13983 | DIP("pop%c %s\n", sz==2 ? 'w' : 'l', dis_buf); |
sewardj | feeb8a8 | 2004-11-30 12:30:11 +0000 | [diff] [blame] | 13984 | |
| 13985 | delta += len; |
| 13986 | break; |
| 13987 | } |
| 13988 | |
sewardj | 5c5f72c | 2006-03-18 11:29:25 +0000 | [diff] [blame] | 13989 | case 0x1F: /* POP %DS */ |
| 13990 | dis_pop_segreg( R_DS, sz ); break; |
| 13991 | case 0x07: /* POP %ES */ |
| 13992 | dis_pop_segreg( R_ES, sz ); break; |
| 13993 | case 0x17: /* POP %SS */ |
| 13994 | dis_pop_segreg( R_SS, sz ); break; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 13995 | |
| 13996 | /* ------------------------ PUSH ----------------------- */ |
| 13997 | |
| 13998 | case 0x50: /* PUSH eAX */ |
| 13999 | case 0x51: /* PUSH eCX */ |
| 14000 | case 0x52: /* PUSH eDX */ |
| 14001 | case 0x53: /* PUSH eBX */ |
| 14002 | case 0x55: /* PUSH eBP */ |
| 14003 | case 0x56: /* PUSH eSI */ |
| 14004 | case 0x57: /* PUSH eDI */ |
| 14005 | case 0x54: /* PUSH eSP */ |
| 14006 | /* This is the Right Way, in that the value to be pushed is |
| 14007 | established before %esp is changed, so that pushl %esp |
| 14008 | correctly pushes the old value. */ |
| 14009 | vassert(sz == 2 || sz == 4); |
| 14010 | ty = sz==2 ? Ity_I16 : Ity_I32; |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 14011 | t1 = newTemp(ty); t2 = newTemp(Ity_I32); |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 14012 | assign(t1, getIReg(sz, opc-0x50)); |
| 14013 | assign(t2, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(sz))); |
| 14014 | putIReg(4, R_ESP, mkexpr(t2) ); |
| 14015 | storeLE(mkexpr(t2),mkexpr(t1)); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 14016 | DIP("push%c %s\n", nameISize(sz), nameIReg(sz,opc-0x50)); |
| 14017 | break; |
| 14018 | |
| 14019 | |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 14020 | case 0x68: /* PUSH Iv */ |
| 14021 | d32 = getUDisp(sz,delta); delta += sz; |
| 14022 | goto do_push_I; |
sewardj | 741153c | 2004-07-25 23:39:13 +0000 | [diff] [blame] | 14023 | case 0x6A: /* PUSH Ib, sign-extended to sz */ |
| 14024 | d32 = getSDisp8(delta); delta += 1; |
| 14025 | goto do_push_I; |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 14026 | do_push_I: |
| 14027 | ty = szToITy(sz); |
| 14028 | t1 = newTemp(Ity_I32); t2 = newTemp(ty); |
| 14029 | assign( t1, binop(Iop_Sub32,getIReg(4,R_ESP),mkU32(sz)) ); |
| 14030 | putIReg(4, R_ESP, mkexpr(t1) ); |
sewardj | c4255a0 | 2006-08-28 18:04:33 +0000 | [diff] [blame] | 14031 | /* stop mkU16 asserting if d32 is a negative 16-bit number |
| 14032 | (bug #132813) */ |
| 14033 | if (ty == Ity_I16) |
| 14034 | d32 &= 0xFFFF; |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 14035 | storeLE( mkexpr(t1), mkU(ty,d32) ); |
| 14036 | DIP("push%c $0x%x\n", nameISize(sz), d32); |
| 14037 | break; |
| 14038 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 14039 | case 0x9C: /* PUSHF */ { |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 14040 | vassert(sz == 2 || sz == 4); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 14041 | |
| 14042 | t1 = newTemp(Ity_I32); |
| 14043 | assign( t1, binop(Iop_Sub32,getIReg(4,R_ESP),mkU32(sz)) ); |
| 14044 | putIReg(4, R_ESP, mkexpr(t1) ); |
| 14045 | |
sewardj | bc21094 | 2005-07-21 10:07:13 +0000 | [diff] [blame] | 14046 | /* Calculate OSZACP, and patch in fixed fields as per |
| 14047 | Intel docs. |
| 14048 | - bit 1 is always 1 |
| 14049 | - bit 9 is Interrupt Enable (should always be 1 in user mode?) |
| 14050 | */ |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 14051 | t2 = newTemp(Ity_I32); |
sewardj | bc21094 | 2005-07-21 10:07:13 +0000 | [diff] [blame] | 14052 | assign( t2, binop(Iop_Or32, |
| 14053 | mk_x86g_calculate_eflags_all(), |
| 14054 | mkU32( (1<<1)|(1<<9) ) )); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 14055 | |
sewardj | f9c74fe | 2004-12-16 02:54:54 +0000 | [diff] [blame] | 14056 | /* Patch in the D flag. This can simply be a copy of bit 10 of |
| 14057 | baseBlock[OFFB_DFLAG]. */ |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 14058 | t3 = newTemp(Ity_I32); |
| 14059 | assign( t3, binop(Iop_Or32, |
| 14060 | mkexpr(t2), |
| 14061 | binop(Iop_And32, |
sewardj | f9c74fe | 2004-12-16 02:54:54 +0000 | [diff] [blame] | 14062 | IRExpr_Get(OFFB_DFLAG,Ity_I32), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14063 | mkU32(1<<10))) |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 14064 | ); |
sewardj | 006a6a2 | 2004-10-26 00:50:52 +0000 | [diff] [blame] | 14065 | |
| 14066 | /* And patch in the ID flag. */ |
| 14067 | t4 = newTemp(Ity_I32); |
| 14068 | assign( t4, binop(Iop_Or32, |
| 14069 | mkexpr(t3), |
| 14070 | binop(Iop_And32, |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14071 | binop(Iop_Shl32, IRExpr_Get(OFFB_IDFLAG,Ity_I32), |
sewardj | 006a6a2 | 2004-10-26 00:50:52 +0000 | [diff] [blame] | 14072 | mkU8(21)), |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14073 | mkU32(1<<21))) |
sewardj | 006a6a2 | 2004-10-26 00:50:52 +0000 | [diff] [blame] | 14074 | ); |
| 14075 | |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 14076 | /* And patch in the AC flag. */ |
| 14077 | t5 = newTemp(Ity_I32); |
| 14078 | assign( t5, binop(Iop_Or32, |
| 14079 | mkexpr(t4), |
| 14080 | binop(Iop_And32, |
| 14081 | binop(Iop_Shl32, IRExpr_Get(OFFB_ACFLAG,Ity_I32), |
| 14082 | mkU8(18)), |
| 14083 | mkU32(1<<18))) |
| 14084 | ); |
| 14085 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 14086 | /* if sz==2, the stored value needs to be narrowed. */ |
| 14087 | if (sz == 2) |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 14088 | storeLE( mkexpr(t1), unop(Iop_32to16,mkexpr(t5)) ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 14089 | else |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 14090 | storeLE( mkexpr(t1), mkexpr(t5) ); |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 14091 | |
| 14092 | DIP("pushf%c\n", nameISize(sz)); |
| 14093 | break; |
| 14094 | } |
| 14095 | |
sewardj | bbdc622 | 2004-12-15 18:43:39 +0000 | [diff] [blame] | 14096 | case 0x60: /* PUSHA */ |
| 14097 | /* This is almost certainly wrong for sz==2. So ... */ |
| 14098 | if (sz != 4) goto decode_failure; |
| 14099 | |
| 14100 | /* This is the Right Way, in that the value to be pushed is |
| 14101 | established before %esp is changed, so that pusha |
| 14102 | correctly pushes the old %esp value. New value of %esp is |
| 14103 | pushed at start. */ |
| 14104 | /* t0 is the %ESP value we're going to push. */ |
| 14105 | t0 = newTemp(Ity_I32); |
| 14106 | assign( t0, getIReg(4, R_ESP) ); |
| 14107 | |
| 14108 | /* t5 will be the new %ESP value. */ |
| 14109 | t5 = newTemp(Ity_I32); |
| 14110 | assign( t5, binop(Iop_Sub32, mkexpr(t0), mkU32(8*4)) ); |
| 14111 | |
| 14112 | /* Update guest state before prodding memory. */ |
| 14113 | putIReg(4, R_ESP, mkexpr(t5)); |
| 14114 | |
| 14115 | /* Dump all the registers. */ |
| 14116 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(28)), getIReg(4,R_EAX) ); |
| 14117 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(24)), getIReg(4,R_ECX) ); |
| 14118 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(20)), getIReg(4,R_EDX) ); |
| 14119 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(16)), getIReg(4,R_EBX) ); |
| 14120 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(12)), mkexpr(t0) /*esp*/); |
| 14121 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32( 8)), getIReg(4,R_EBP) ); |
| 14122 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32( 4)), getIReg(4,R_ESI) ); |
| 14123 | storeLE( binop(Iop_Add32,mkexpr(t5),mkU32( 0)), getIReg(4,R_EDI) ); |
| 14124 | |
| 14125 | DIP("pusha%c\n", nameISize(sz)); |
| 14126 | break; |
| 14127 | |
sewardj | 5c5f72c | 2006-03-18 11:29:25 +0000 | [diff] [blame] | 14128 | case 0x0E: /* PUSH %CS */ |
| 14129 | dis_push_segreg( R_CS, sz ); break; |
| 14130 | case 0x1E: /* PUSH %DS */ |
| 14131 | dis_push_segreg( R_DS, sz ); break; |
| 14132 | case 0x06: /* PUSH %ES */ |
| 14133 | dis_push_segreg( R_ES, sz ); break; |
| 14134 | case 0x16: /* PUSH %SS */ |
| 14135 | dis_push_segreg( R_SS, sz ); break; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14136 | |
| 14137 | /* ------------------------ SCAS et al ----------------- */ |
| 14138 | |
| 14139 | case 0xA4: /* MOVS, no REP prefix */ |
| 14140 | case 0xA5: |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 14141 | if (sorb != 0) |
| 14142 | goto decode_failure; /* else dis_string_op asserts */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14143 | dis_string_op( dis_MOVS, ( opc == 0xA4 ? 1 : sz ), "movs", sorb ); |
| 14144 | break; |
| 14145 | |
sewardj | 8d4d223 | 2005-01-20 10:47:46 +0000 | [diff] [blame] | 14146 | case 0xA6: /* CMPSb, no REP prefix */ |
sewardj | 33b5354 | 2005-03-11 14:00:27 +0000 | [diff] [blame] | 14147 | case 0xA7: |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 14148 | if (sorb != 0) |
| 14149 | goto decode_failure; /* else dis_string_op asserts */ |
| 14150 | dis_string_op( dis_CMPS, ( opc == 0xA6 ? 1 : sz ), "cmps", sorb ); |
| 14151 | break; |
sewardj | 33b5354 | 2005-03-11 14:00:27 +0000 | [diff] [blame] | 14152 | |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 14153 | case 0xAA: /* STOS, no REP prefix */ |
sewardj | 4734104 | 2004-09-19 11:55:46 +0000 | [diff] [blame] | 14154 | case 0xAB: |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 14155 | if (sorb != 0) |
| 14156 | goto decode_failure; /* else dis_string_op asserts */ |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 14157 | dis_string_op( dis_STOS, ( opc == 0xAA ? 1 : sz ), "stos", sorb ); |
| 14158 | break; |
sewardj | 33b5354 | 2005-03-11 14:00:27 +0000 | [diff] [blame] | 14159 | |
sewardj | 10ca4eb | 2005-05-30 11:19:54 +0000 | [diff] [blame] | 14160 | case 0xAC: /* LODS, no REP prefix */ |
| 14161 | case 0xAD: |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 14162 | if (sorb != 0) |
| 14163 | goto decode_failure; /* else dis_string_op asserts */ |
sewardj | 10ca4eb | 2005-05-30 11:19:54 +0000 | [diff] [blame] | 14164 | dis_string_op( dis_LODS, ( opc == 0xAC ? 1 : sz ), "lods", sorb ); |
| 14165 | break; |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 14166 | |
| 14167 | case 0xAE: /* SCAS, no REP prefix */ |
| 14168 | case 0xAF: |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 14169 | if (sorb != 0) |
| 14170 | goto decode_failure; /* else dis_string_op asserts */ |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 14171 | dis_string_op( dis_SCAS, ( opc == 0xAE ? 1 : sz ), "scas", sorb ); |
| 14172 | break; |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14173 | |
| 14174 | |
| 14175 | case 0xFC: /* CLD */ |
sewardj | eeb9ef8 | 2004-07-15 12:39:03 +0000 | [diff] [blame] | 14176 | stmt( IRStmt_Put( OFFB_DFLAG, mkU32(1)) ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14177 | DIP("cld\n"); |
| 14178 | break; |
| 14179 | |
sewardj | 1813dbe | 2004-07-28 17:09:04 +0000 | [diff] [blame] | 14180 | case 0xFD: /* STD */ |
| 14181 | stmt( IRStmt_Put( OFFB_DFLAG, mkU32(0xFFFFFFFF)) ); |
| 14182 | DIP("std\n"); |
| 14183 | break; |
| 14184 | |
sewardj | bc21094 | 2005-07-21 10:07:13 +0000 | [diff] [blame] | 14185 | case 0xF8: /* CLC */ |
| 14186 | case 0xF9: /* STC */ |
| 14187 | case 0xF5: /* CMC */ |
| 14188 | t0 = newTemp(Ity_I32); |
| 14189 | t1 = newTemp(Ity_I32); |
| 14190 | assign( t0, mk_x86g_calculate_eflags_all() ); |
| 14191 | switch (opc) { |
| 14192 | case 0xF8: |
| 14193 | assign( t1, binop(Iop_And32, mkexpr(t0), |
| 14194 | mkU32(~X86G_CC_MASK_C))); |
| 14195 | DIP("clc\n"); |
| 14196 | break; |
| 14197 | case 0xF9: |
| 14198 | assign( t1, binop(Iop_Or32, mkexpr(t0), |
| 14199 | mkU32(X86G_CC_MASK_C))); |
| 14200 | DIP("stc\n"); |
| 14201 | break; |
| 14202 | case 0xF5: |
| 14203 | assign( t1, binop(Iop_Xor32, mkexpr(t0), |
| 14204 | mkU32(X86G_CC_MASK_C))); |
| 14205 | DIP("cmc\n"); |
| 14206 | break; |
| 14207 | default: |
| 14208 | vpanic("disInstr(x86)(clc/stc/cmc)"); |
| 14209 | } |
| 14210 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 14211 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 14212 | stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(t1) )); |
| 14213 | /* Set NDEP even though it isn't used. This makes redundant-PUT |
| 14214 | elimination of previous stores to this field work better. */ |
| 14215 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 14216 | break; |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 14217 | |
sewardj | a384eb9 | 2007-11-16 02:30:38 +0000 | [diff] [blame] | 14218 | case 0xD6: /* SALC */ |
| 14219 | t0 = newTemp(Ity_I32); |
| 14220 | t1 = newTemp(Ity_I32); |
| 14221 | assign( t0, binop(Iop_And32, |
| 14222 | mk_x86g_calculate_eflags_c(), |
| 14223 | mkU32(1)) ); |
| 14224 | assign( t1, binop(Iop_Sar32, |
| 14225 | binop(Iop_Shl32, mkexpr(t0), mkU8(31)), |
| 14226 | mkU8(31)) ); |
| 14227 | putIReg(1, R_EAX, unop(Iop_32to8, mkexpr(t1)) ); |
| 14228 | DIP("salc\n"); |
| 14229 | break; |
| 14230 | |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 14231 | /* REPNE prefix insn */ |
| 14232 | case 0xF2: { |
sewardj | 068baa2 | 2008-05-11 10:11:58 +0000 | [diff] [blame] | 14233 | Addr32 eip_orig = guest_EIP_bbstart + delta_start; |
sewardj | 9c3b25a | 2007-04-05 15:06:56 +0000 | [diff] [blame] | 14234 | if (sorb != 0) goto decode_failure; |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 14235 | abyte = getIByte(delta); delta++; |
| 14236 | |
| 14237 | if (abyte == 0x66) { sz = 2; abyte = getIByte(delta); delta++; } |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 14238 | |
| 14239 | switch (abyte) { |
| 14240 | /* According to the Intel manual, "repne movs" should never occur, but |
| 14241 | * in practice it has happened, so allow for it here... */ |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 14242 | case 0xA4: sz = 1; /* REPNE MOVS<sz> */ |
sewardj | cea9662 | 2006-11-14 15:33:05 +0000 | [diff] [blame] | 14243 | case 0xA5: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 14244 | dis_REP_op ( &dres, X86CondNZ, dis_MOVS, sz, eip_orig, |
| 14245 | guest_EIP_bbstart+delta, "repne movs" ); |
sewardj | cea9662 | 2006-11-14 15:33:05 +0000 | [diff] [blame] | 14246 | break; |
sewardj | 842dfb4 | 2008-05-09 08:53:50 +0000 | [diff] [blame] | 14247 | |
| 14248 | case 0xA6: sz = 1; /* REPNE CMP<sz> */ |
| 14249 | case 0xA7: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 14250 | dis_REP_op ( &dres, X86CondNZ, dis_CMPS, sz, eip_orig, |
| 14251 | guest_EIP_bbstart+delta, "repne cmps" ); |
sewardj | 842dfb4 | 2008-05-09 08:53:50 +0000 | [diff] [blame] | 14252 | break; |
| 14253 | |
sewardj | b69a6fa | 2006-11-14 15:13:55 +0000 | [diff] [blame] | 14254 | case 0xAA: sz = 1; /* REPNE STOS<sz> */ |
| 14255 | case 0xAB: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 14256 | dis_REP_op ( &dres, X86CondNZ, dis_STOS, sz, eip_orig, |
| 14257 | guest_EIP_bbstart+delta, "repne stos" ); |
sewardj | b69a6fa | 2006-11-14 15:13:55 +0000 | [diff] [blame] | 14258 | break; |
| 14259 | |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 14260 | case 0xAE: sz = 1; /* REPNE SCAS<sz> */ |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 14261 | case 0xAF: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 14262 | dis_REP_op ( &dres, X86CondNZ, dis_SCAS, sz, eip_orig, |
| 14263 | guest_EIP_bbstart+delta, "repne scas" ); |
sewardj | 8229288 | 2004-07-27 00:15:59 +0000 | [diff] [blame] | 14264 | break; |
| 14265 | |
| 14266 | default: |
| 14267 | goto decode_failure; |
| 14268 | } |
| 14269 | break; |
| 14270 | } |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14271 | |
| 14272 | /* REP/REPE prefix insn (for SCAS and CMPS, 0xF3 means REPE, |
| 14273 | for the rest, it means REP) */ |
| 14274 | case 0xF3: { |
sewardj | 068baa2 | 2008-05-11 10:11:58 +0000 | [diff] [blame] | 14275 | Addr32 eip_orig = guest_EIP_bbstart + delta_start; |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14276 | abyte = getIByte(delta); delta++; |
| 14277 | |
| 14278 | if (abyte == 0x66) { sz = 2; abyte = getIByte(delta); delta++; } |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14279 | |
sewardj | c8851af | 2012-08-23 20:14:51 +0000 | [diff] [blame] | 14280 | if (sorb != 0 && abyte != 0x0F) goto decode_failure; |
| 14281 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14282 | switch (abyte) { |
sewardj | c8851af | 2012-08-23 20:14:51 +0000 | [diff] [blame] | 14283 | case 0x0F: |
| 14284 | switch (getIByte(delta)) { |
| 14285 | /* On older CPUs, TZCNT behaves the same as BSF. */ |
| 14286 | case 0xBC: /* REP BSF Gv,Ev */ |
| 14287 | delta = dis_bs_E_G ( sorb, sz, delta + 1, True ); |
| 14288 | break; |
| 14289 | /* On older CPUs, LZCNT behaves the same as BSR. */ |
| 14290 | case 0xBD: /* REP BSR Gv,Ev */ |
| 14291 | delta = dis_bs_E_G ( sorb, sz, delta + 1, False ); |
| 14292 | break; |
| 14293 | default: |
| 14294 | goto decode_failure; |
| 14295 | } |
| 14296 | break; |
| 14297 | |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14298 | case 0xA4: sz = 1; /* REP MOVS<sz> */ |
| 14299 | case 0xA5: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 14300 | dis_REP_op ( &dres, X86CondAlways, dis_MOVS, sz, eip_orig, |
| 14301 | guest_EIP_bbstart+delta, "rep movs" ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14302 | break; |
| 14303 | |
| 14304 | case 0xA6: sz = 1; /* REPE CMP<sz> */ |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 14305 | case 0xA7: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 14306 | dis_REP_op ( &dres, X86CondZ, dis_CMPS, sz, eip_orig, |
| 14307 | guest_EIP_bbstart+delta, "repe cmps" ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14308 | break; |
| 14309 | |
| 14310 | case 0xAA: sz = 1; /* REP STOS<sz> */ |
| 14311 | case 0xAB: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 14312 | dis_REP_op ( &dres, X86CondAlways, dis_STOS, sz, eip_orig, |
| 14313 | guest_EIP_bbstart+delta, "rep stos" ); |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14314 | break; |
sewardj | 576f323 | 2006-04-12 17:30:46 +0000 | [diff] [blame] | 14315 | |
sewardj | dfb038d | 2007-11-25 01:34:03 +0000 | [diff] [blame] | 14316 | case 0xAC: sz = 1; /* REP LODS<sz> */ |
| 14317 | case 0xAD: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 14318 | dis_REP_op ( &dres, X86CondAlways, dis_LODS, sz, eip_orig, |
| 14319 | guest_EIP_bbstart+delta, "rep lods" ); |
sewardj | dfb038d | 2007-11-25 01:34:03 +0000 | [diff] [blame] | 14320 | break; |
| 14321 | |
sewardj | 576f323 | 2006-04-12 17:30:46 +0000 | [diff] [blame] | 14322 | case 0xAE: sz = 1; /* REPE SCAS<sz> */ |
| 14323 | case 0xAF: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 14324 | dis_REP_op ( &dres, X86CondZ, dis_SCAS, sz, eip_orig, |
| 14325 | guest_EIP_bbstart+delta, "repe scas" ); |
sewardj | 576f323 | 2006-04-12 17:30:46 +0000 | [diff] [blame] | 14326 | break; |
sewardj | 43b8df1 | 2004-11-26 12:18:51 +0000 | [diff] [blame] | 14327 | |
| 14328 | case 0x90: /* REP NOP (PAUSE) */ |
| 14329 | /* a hint to the P4 re spin-wait loop */ |
| 14330 | DIP("rep nop (P4 pause)\n"); |
sewardj | 7ec59f6 | 2005-03-12 16:47:18 +0000 | [diff] [blame] | 14331 | /* "observe" the hint. The Vex client needs to be careful not |
| 14332 | to cause very long delays as a result, though. */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 14333 | jmp_lit(&dres, Ijk_Yield, ((Addr32)guest_EIP_bbstart)+delta); |
| 14334 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | 43b8df1 | 2004-11-26 12:18:51 +0000 | [diff] [blame] | 14335 | break; |
| 14336 | |
sewardj | 7d3d347 | 2005-08-12 23:51:31 +0000 | [diff] [blame] | 14337 | case 0xC3: /* REP RET -- same as normal ret? */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 14338 | dis_ret(&dres, 0); |
sewardj | 7d3d347 | 2005-08-12 23:51:31 +0000 | [diff] [blame] | 14339 | DIP("rep ret\n"); |
| 14340 | break; |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14341 | |
| 14342 | default: |
| 14343 | goto decode_failure; |
| 14344 | } |
| 14345 | break; |
| 14346 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14347 | |
| 14348 | /* ------------------------ XCHG ----------------------- */ |
| 14349 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 14350 | /* XCHG reg,mem automatically asserts LOCK# even without a LOCK |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 14351 | prefix; hence it must be translated with an IRCAS (at least, the |
| 14352 | memory variant). */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14353 | case 0x86: /* XCHG Gb,Eb */ |
| 14354 | sz = 1; |
| 14355 | /* Fall through ... */ |
| 14356 | case 0x87: /* XCHG Gv,Ev */ |
| 14357 | modrm = getIByte(delta); |
| 14358 | ty = szToITy(sz); |
| 14359 | t1 = newTemp(ty); t2 = newTemp(ty); |
| 14360 | if (epartIsReg(modrm)) { |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14361 | assign(t1, getIReg(sz, eregOfRM(modrm))); |
| 14362 | assign(t2, getIReg(sz, gregOfRM(modrm))); |
| 14363 | putIReg(sz, gregOfRM(modrm), mkexpr(t1)); |
| 14364 | putIReg(sz, eregOfRM(modrm), mkexpr(t2)); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14365 | delta++; |
| 14366 | DIP("xchg%c %s, %s\n", |
| 14367 | nameISize(sz), nameIReg(sz,gregOfRM(modrm)), |
| 14368 | nameIReg(sz,eregOfRM(modrm))); |
| 14369 | } else { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14370 | *expect_CAS = True; |
sewardj | 0c12ea8 | 2004-07-12 08:18:16 +0000 | [diff] [blame] | 14371 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14372 | assign( t1, loadLE(ty,mkexpr(addr)) ); |
| 14373 | assign( t2, getIReg(sz,gregOfRM(modrm)) ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14374 | casLE( mkexpr(addr), |
| 14375 | mkexpr(t1), mkexpr(t2), guest_EIP_curr_instr ); |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14376 | putIReg( sz, gregOfRM(modrm), mkexpr(t1) ); |
| 14377 | delta += alen; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14378 | DIP("xchg%c %s, %s\n", nameISize(sz), |
| 14379 | nameIReg(sz,gregOfRM(modrm)), dis_buf); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14380 | } |
| 14381 | break; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 14382 | |
| 14383 | case 0x90: /* XCHG eAX,eAX */ |
| 14384 | DIP("nop\n"); |
| 14385 | break; |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 14386 | case 0x91: /* XCHG eAX,eCX */ |
| 14387 | case 0x92: /* XCHG eAX,eDX */ |
| 14388 | case 0x93: /* XCHG eAX,eBX */ |
| 14389 | case 0x94: /* XCHG eAX,eSP */ |
| 14390 | case 0x95: /* XCHG eAX,eBP */ |
| 14391 | case 0x96: /* XCHG eAX,eSI */ |
| 14392 | case 0x97: /* XCHG eAX,eDI */ |
| 14393 | codegen_xchg_eAX_Reg ( sz, opc - 0x90 ); |
| 14394 | break; |
| 14395 | |
sewardj | 048de4d | 2006-11-12 22:25:21 +0000 | [diff] [blame] | 14396 | /* ------------------------ XLAT ----------------------- */ |
| 14397 | |
| 14398 | case 0xD7: /* XLAT */ |
| 14399 | if (sz != 4) goto decode_failure; /* sz == 2 is also allowed (0x66) */ |
| 14400 | putIReg( |
| 14401 | 1, |
| 14402 | R_EAX/*AL*/, |
| 14403 | loadLE(Ity_I8, |
| 14404 | handleSegOverride( |
| 14405 | sorb, |
| 14406 | binop(Iop_Add32, |
| 14407 | getIReg(4, R_EBX), |
| 14408 | unop(Iop_8Uto32, getIReg(1, R_EAX/*AL*/)))))); |
| 14409 | |
| 14410 | DIP("xlat%c [ebx]\n", nameISize(sz)); |
| 14411 | break; |
sewardj | d14c570 | 2005-10-29 19:19:51 +0000 | [diff] [blame] | 14412 | |
| 14413 | /* ------------------------ IN / OUT ----------------------- */ |
| 14414 | |
| 14415 | case 0xE4: /* IN imm8, AL */ |
| 14416 | sz = 1; |
| 14417 | t1 = newTemp(Ity_I32); |
| 14418 | abyte = getIByte(delta); delta++; |
| 14419 | assign(t1, mkU32( abyte & 0xFF )); |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 14420 | DIP("in%c $%d,%s\n", nameISize(sz), abyte, nameIReg(sz,R_EAX)); |
sewardj | d14c570 | 2005-10-29 19:19:51 +0000 | [diff] [blame] | 14421 | goto do_IN; |
| 14422 | case 0xE5: /* IN imm8, eAX */ |
| 14423 | vassert(sz == 2 || sz == 4); |
| 14424 | t1 = newTemp(Ity_I32); |
| 14425 | abyte = getIByte(delta); delta++; |
| 14426 | assign(t1, mkU32( abyte & 0xFF )); |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 14427 | DIP("in%c $%d,%s\n", nameISize(sz), abyte, nameIReg(sz,R_EAX)); |
sewardj | d14c570 | 2005-10-29 19:19:51 +0000 | [diff] [blame] | 14428 | goto do_IN; |
| 14429 | case 0xEC: /* IN %DX, AL */ |
| 14430 | sz = 1; |
| 14431 | t1 = newTemp(Ity_I32); |
| 14432 | assign(t1, unop(Iop_16Uto32, getIReg(2, R_EDX))); |
| 14433 | DIP("in%c %s,%s\n", nameISize(sz), nameIReg(2,R_EDX), |
| 14434 | nameIReg(sz,R_EAX)); |
| 14435 | goto do_IN; |
| 14436 | case 0xED: /* IN %DX, eAX */ |
| 14437 | vassert(sz == 2 || sz == 4); |
| 14438 | t1 = newTemp(Ity_I32); |
| 14439 | assign(t1, unop(Iop_16Uto32, getIReg(2, R_EDX))); |
| 14440 | DIP("in%c %s,%s\n", nameISize(sz), nameIReg(2,R_EDX), |
| 14441 | nameIReg(sz,R_EAX)); |
| 14442 | goto do_IN; |
| 14443 | do_IN: { |
| 14444 | /* At this point, sz indicates the width, and t1 is a 32-bit |
| 14445 | value giving port number. */ |
| 14446 | IRDirty* d; |
| 14447 | vassert(sz == 1 || sz == 2 || sz == 4); |
| 14448 | ty = szToITy(sz); |
| 14449 | t2 = newTemp(Ity_I32); |
| 14450 | d = unsafeIRDirty_1_N( |
| 14451 | t2, |
| 14452 | 0/*regparms*/, |
| 14453 | "x86g_dirtyhelper_IN", |
| 14454 | &x86g_dirtyhelper_IN, |
| 14455 | mkIRExprVec_2( mkexpr(t1), mkU32(sz) ) |
| 14456 | ); |
| 14457 | /* do the call, dumping the result in t2. */ |
| 14458 | stmt( IRStmt_Dirty(d) ); |
| 14459 | putIReg(sz, R_EAX, narrowTo( ty, mkexpr(t2) ) ); |
| 14460 | break; |
| 14461 | } |
| 14462 | |
| 14463 | case 0xE6: /* OUT AL, imm8 */ |
| 14464 | sz = 1; |
| 14465 | t1 = newTemp(Ity_I32); |
| 14466 | abyte = getIByte(delta); delta++; |
| 14467 | assign( t1, mkU32( abyte & 0xFF ) ); |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 14468 | DIP("out%c %s,$%d\n", nameISize(sz), nameIReg(sz,R_EAX), abyte); |
sewardj | d14c570 | 2005-10-29 19:19:51 +0000 | [diff] [blame] | 14469 | goto do_OUT; |
| 14470 | case 0xE7: /* OUT eAX, imm8 */ |
| 14471 | vassert(sz == 2 || sz == 4); |
| 14472 | t1 = newTemp(Ity_I32); |
| 14473 | abyte = getIByte(delta); delta++; |
| 14474 | assign( t1, mkU32( abyte & 0xFF ) ); |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 14475 | DIP("out%c %s,$%d\n", nameISize(sz), nameIReg(sz,R_EAX), abyte); |
sewardj | d14c570 | 2005-10-29 19:19:51 +0000 | [diff] [blame] | 14476 | goto do_OUT; |
| 14477 | case 0xEE: /* OUT AL, %DX */ |
| 14478 | sz = 1; |
| 14479 | t1 = newTemp(Ity_I32); |
| 14480 | assign( t1, unop(Iop_16Uto32, getIReg(2, R_EDX)) ); |
| 14481 | DIP("out%c %s,%s\n", nameISize(sz), nameIReg(sz,R_EAX), |
| 14482 | nameIReg(2,R_EDX)); |
| 14483 | goto do_OUT; |
| 14484 | case 0xEF: /* OUT eAX, %DX */ |
| 14485 | vassert(sz == 2 || sz == 4); |
| 14486 | t1 = newTemp(Ity_I32); |
| 14487 | assign( t1, unop(Iop_16Uto32, getIReg(2, R_EDX)) ); |
| 14488 | DIP("out%c %s,%s\n", nameISize(sz), nameIReg(sz,R_EAX), |
| 14489 | nameIReg(2,R_EDX)); |
| 14490 | goto do_OUT; |
| 14491 | do_OUT: { |
| 14492 | /* At this point, sz indicates the width, and t1 is a 32-bit |
| 14493 | value giving port number. */ |
| 14494 | IRDirty* d; |
| 14495 | vassert(sz == 1 || sz == 2 || sz == 4); |
| 14496 | ty = szToITy(sz); |
| 14497 | d = unsafeIRDirty_0_N( |
| 14498 | 0/*regparms*/, |
| 14499 | "x86g_dirtyhelper_OUT", |
| 14500 | &x86g_dirtyhelper_OUT, |
| 14501 | mkIRExprVec_3( mkexpr(t1), |
| 14502 | widenUto32( getIReg(sz, R_EAX) ), |
| 14503 | mkU32(sz) ) |
| 14504 | ); |
| 14505 | stmt( IRStmt_Dirty(d) ); |
| 14506 | break; |
| 14507 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14508 | |
| 14509 | /* ------------------------ (Grp1 extensions) ---------- */ |
| 14510 | |
sewardj | 792d771 | 2008-10-31 21:27:38 +0000 | [diff] [blame] | 14511 | case 0x82: /* Grp1 Ib,Eb too. Apparently this is the same as |
| 14512 | case 0x80, but only in 32-bit mode. */ |
| 14513 | /* fallthru */ |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14514 | case 0x80: /* Grp1 Ib,Eb */ |
| 14515 | modrm = getIByte(delta); |
| 14516 | am_sz = lengthAMode(delta); |
| 14517 | sz = 1; |
| 14518 | d_sz = 1; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14519 | d32 = getUChar(delta + am_sz); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14520 | delta = dis_Grp1 ( sorb, pfx_lock, delta, modrm, am_sz, d_sz, sz, d32 ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14521 | break; |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 14522 | |
| 14523 | case 0x81: /* Grp1 Iv,Ev */ |
| 14524 | modrm = getIByte(delta); |
| 14525 | am_sz = lengthAMode(delta); |
| 14526 | d_sz = sz; |
| 14527 | d32 = getUDisp(d_sz, delta + am_sz); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14528 | delta = dis_Grp1 ( sorb, pfx_lock, delta, modrm, am_sz, d_sz, sz, d32 ); |
sewardj | e05c42c | 2004-07-08 20:25:10 +0000 | [diff] [blame] | 14529 | break; |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 14530 | |
| 14531 | case 0x83: /* Grp1 Ib,Ev */ |
| 14532 | modrm = getIByte(delta); |
| 14533 | am_sz = lengthAMode(delta); |
| 14534 | d_sz = 1; |
| 14535 | d32 = getSDisp8(delta + am_sz); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14536 | delta = dis_Grp1 ( sorb, pfx_lock, delta, modrm, am_sz, d_sz, sz, d32 ); |
sewardj | d1061ab | 2004-07-08 01:45:30 +0000 | [diff] [blame] | 14537 | break; |
| 14538 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14539 | /* ------------------------ (Grp2 extensions) ---------- */ |
| 14540 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14541 | case 0xC0: { /* Grp2 Ib,Eb */ |
| 14542 | Bool decode_OK = True; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14543 | modrm = getIByte(delta); |
| 14544 | am_sz = lengthAMode(delta); |
| 14545 | d_sz = 1; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 14546 | d32 = getUChar(delta + am_sz); |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14547 | sz = 1; |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 14548 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14549 | mkU8(d32 & 0xFF), NULL, &decode_OK ); |
| 14550 | if (!decode_OK) |
| 14551 | goto decode_failure; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14552 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14553 | } |
| 14554 | case 0xC1: { /* Grp2 Ib,Ev */ |
| 14555 | Bool decode_OK = True; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14556 | modrm = getIByte(delta); |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 14557 | am_sz = lengthAMode(delta); |
| 14558 | d_sz = 1; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 14559 | d32 = getUChar(delta + am_sz); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 14560 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14561 | mkU8(d32 & 0xFF), NULL, &decode_OK ); |
| 14562 | if (!decode_OK) |
| 14563 | goto decode_failure; |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 14564 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14565 | } |
| 14566 | case 0xD0: { /* Grp2 1,Eb */ |
| 14567 | Bool decode_OK = True; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 14568 | modrm = getIByte(delta); |
| 14569 | am_sz = lengthAMode(delta); |
| 14570 | d_sz = 0; |
| 14571 | d32 = 1; |
| 14572 | sz = 1; |
| 14573 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14574 | mkU8(d32), NULL, &decode_OK ); |
| 14575 | if (!decode_OK) |
| 14576 | goto decode_failure; |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 14577 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14578 | } |
| 14579 | case 0xD1: { /* Grp2 1,Ev */ |
| 14580 | Bool decode_OK = True; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14581 | modrm = getUChar(delta); |
| 14582 | am_sz = lengthAMode(delta); |
| 14583 | d_sz = 0; |
| 14584 | d32 = 1; |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 14585 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14586 | mkU8(d32), NULL, &decode_OK ); |
| 14587 | if (!decode_OK) |
| 14588 | goto decode_failure; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14589 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14590 | } |
| 14591 | case 0xD2: { /* Grp2 CL,Eb */ |
| 14592 | Bool decode_OK = True; |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 14593 | modrm = getUChar(delta); |
| 14594 | am_sz = lengthAMode(delta); |
| 14595 | d_sz = 0; |
| 14596 | sz = 1; |
| 14597 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14598 | getIReg(1,R_ECX), "%cl", &decode_OK ); |
| 14599 | if (!decode_OK) |
| 14600 | goto decode_failure; |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 14601 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14602 | } |
| 14603 | case 0xD3: { /* Grp2 CL,Ev */ |
| 14604 | Bool decode_OK = True; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 14605 | modrm = getIByte(delta); |
| 14606 | am_sz = lengthAMode(delta); |
| 14607 | d_sz = 0; |
| 14608 | delta = dis_Grp2 ( sorb, delta, modrm, am_sz, d_sz, sz, |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14609 | getIReg(1,R_ECX), "%cl", &decode_OK ); |
| 14610 | if (!decode_OK) |
| 14611 | goto decode_failure; |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 14612 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14613 | } |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 14614 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14615 | /* ------------------------ (Grp3 extensions) ---------- */ |
| 14616 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14617 | case 0xF6: { /* Grp3 Eb */ |
| 14618 | Bool decode_OK = True; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14619 | delta = dis_Grp3 ( sorb, pfx_lock, 1, delta, &decode_OK ); |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14620 | if (!decode_OK) |
| 14621 | goto decode_failure; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14622 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14623 | } |
| 14624 | case 0xF7: { /* Grp3 Ev */ |
| 14625 | Bool decode_OK = True; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14626 | delta = dis_Grp3 ( sorb, pfx_lock, sz, delta, &decode_OK ); |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14627 | if (!decode_OK) |
| 14628 | goto decode_failure; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14629 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14630 | } |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14631 | |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14632 | /* ------------------------ (Grp4 extensions) ---------- */ |
| 14633 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14634 | case 0xFE: { /* Grp4 Eb */ |
| 14635 | Bool decode_OK = True; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14636 | delta = dis_Grp4 ( sorb, pfx_lock, delta, &decode_OK ); |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14637 | if (!decode_OK) |
| 14638 | goto decode_failure; |
sewardj | c2ac51e | 2004-07-12 01:03:26 +0000 | [diff] [blame] | 14639 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14640 | } |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14641 | |
| 14642 | /* ------------------------ (Grp5 extensions) ---------- */ |
| 14643 | |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14644 | case 0xFF: { /* Grp5 Ev */ |
| 14645 | Bool decode_OK = True; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14646 | delta = dis_Grp5 ( sorb, pfx_lock, sz, delta, &dres, &decode_OK ); |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14647 | if (!decode_OK) |
| 14648 | goto decode_failure; |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14649 | break; |
sewardj | d51dc81 | 2007-03-20 14:18:45 +0000 | [diff] [blame] | 14650 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 14651 | |
| 14652 | /* ------------------------ Escapes to 2-byte opcodes -- */ |
| 14653 | |
| 14654 | case 0x0F: { |
| 14655 | opc = getIByte(delta); delta++; |
| 14656 | switch (opc) { |
| 14657 | |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 14658 | /* =-=-=-=-=-=-=-=-=- Grp8 =-=-=-=-=-=-=-=-=-=-=-= */ |
| 14659 | |
| 14660 | case 0xBA: { /* Grp8 Ib,Ev */ |
| 14661 | Bool decode_OK = False; |
| 14662 | modrm = getUChar(delta); |
| 14663 | am_sz = lengthAMode(delta); |
| 14664 | d32 = getSDisp8(delta + am_sz); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14665 | delta = dis_Grp8_Imm ( sorb, pfx_lock, delta, modrm, |
| 14666 | am_sz, sz, d32, &decode_OK ); |
sewardj | 490ad38 | 2005-03-13 17:25:53 +0000 | [diff] [blame] | 14667 | if (!decode_OK) |
| 14668 | goto decode_failure; |
| 14669 | break; |
| 14670 | } |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 14671 | |
| 14672 | /* =-=-=-=-=-=-=-=-=- BSF/BSR -=-=-=-=-=-=-=-=-=-= */ |
| 14673 | |
| 14674 | case 0xBC: /* BSF Gv,Ev */ |
| 14675 | delta = dis_bs_E_G ( sorb, sz, delta, True ); |
| 14676 | break; |
| 14677 | case 0xBD: /* BSR Gv,Ev */ |
| 14678 | delta = dis_bs_E_G ( sorb, sz, delta, False ); |
| 14679 | break; |
sewardj | 1c4208f | 2004-08-25 13:25:29 +0000 | [diff] [blame] | 14680 | |
| 14681 | /* =-=-=-=-=-=-=-=-=- BSWAP -=-=-=-=-=-=-=-=-=-=-= */ |
| 14682 | |
| 14683 | case 0xC8: /* BSWAP %eax */ |
| 14684 | case 0xC9: |
| 14685 | case 0xCA: |
sewardj | b4666cf | 2004-10-23 00:21:50 +0000 | [diff] [blame] | 14686 | case 0xCB: |
| 14687 | case 0xCC: |
| 14688 | case 0xCD: |
sewardj | 1c4208f | 2004-08-25 13:25:29 +0000 | [diff] [blame] | 14689 | case 0xCE: |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 14690 | case 0xCF: /* BSWAP %edi */ |
sewardj | 1c4208f | 2004-08-25 13:25:29 +0000 | [diff] [blame] | 14691 | /* AFAICS from the Intel docs, this only exists at size 4. */ |
sewardj | 021f6b4 | 2012-08-23 23:39:49 +0000 | [diff] [blame] | 14692 | if (sz != 4) goto decode_failure; |
| 14693 | |
sewardj | 1c4208f | 2004-08-25 13:25:29 +0000 | [diff] [blame] | 14694 | t1 = newTemp(Ity_I32); |
sewardj | 1c4208f | 2004-08-25 13:25:29 +0000 | [diff] [blame] | 14695 | assign( t1, getIReg(4, opc-0xC8) ); |
sewardj | 021f6b4 | 2012-08-23 23:39:49 +0000 | [diff] [blame] | 14696 | t2 = math_BSWAP(t1, Ity_I32); |
sewardj | 1c4208f | 2004-08-25 13:25:29 +0000 | [diff] [blame] | 14697 | |
| 14698 | putIReg(4, opc-0xC8, mkexpr(t2)); |
sewardj | 1c4208f | 2004-08-25 13:25:29 +0000 | [diff] [blame] | 14699 | DIP("bswapl %s\n", nameIReg(4, opc-0xC8)); |
| 14700 | break; |
| 14701 | |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 14702 | /* =-=-=-=-=-=-=-=-=- BT/BTS/BTR/BTC =-=-=-=-=-=-= */ |
| 14703 | |
| 14704 | case 0xA3: /* BT Gv,Ev */ |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 14705 | delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpNone ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 14706 | break; |
sewardj | e670911 | 2004-09-10 18:37:18 +0000 | [diff] [blame] | 14707 | case 0xB3: /* BTR Gv,Ev */ |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 14708 | delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpReset ); |
sewardj | e670911 | 2004-09-10 18:37:18 +0000 | [diff] [blame] | 14709 | break; |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 14710 | case 0xAB: /* BTS Gv,Ev */ |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 14711 | delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpSet ); |
sewardj | 1c6f991 | 2004-09-07 10:15:24 +0000 | [diff] [blame] | 14712 | break; |
sewardj | 4963a42 | 2004-10-14 23:34:03 +0000 | [diff] [blame] | 14713 | case 0xBB: /* BTC Gv,Ev */ |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 14714 | delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpComp ); |
sewardj | 4963a42 | 2004-10-14 23:34:03 +0000 | [diff] [blame] | 14715 | break; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14716 | |
| 14717 | /* =-=-=-=-=-=-=-=-=- CMOV =-=-=-=-=-=-=-=-=-=-=-= */ |
| 14718 | |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 14719 | case 0x40: |
| 14720 | case 0x41: |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14721 | case 0x42: /* CMOVBb/CMOVNAEb (cmov below) */ |
| 14722 | case 0x43: /* CMOVNBb/CMOVAEb (cmov not below) */ |
| 14723 | case 0x44: /* CMOVZb/CMOVEb (cmov zero) */ |
| 14724 | case 0x45: /* CMOVNZb/CMOVNEb (cmov not zero) */ |
| 14725 | case 0x46: /* CMOVBEb/CMOVNAb (cmov below or equal) */ |
| 14726 | case 0x47: /* CMOVNBEb/CMOVAb (cmov not below or equal) */ |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 14727 | case 0x48: /* CMOVSb (cmov negative) */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14728 | case 0x49: /* CMOVSb (cmov not negative) */ |
sewardj | 2d4c3a0 | 2004-10-15 00:03:23 +0000 | [diff] [blame] | 14729 | case 0x4A: /* CMOVP (cmov parity even) */ |
| 14730 | case 0x4B: /* CMOVNP (cmov parity odd) */ |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14731 | case 0x4C: /* CMOVLb/CMOVNGEb (cmov less) */ |
| 14732 | case 0x4D: /* CMOVGEb/CMOVNLb (cmov greater or equal) */ |
| 14733 | case 0x4E: /* CMOVLEb/CMOVNGb (cmov less or equal) */ |
| 14734 | case 0x4F: /* CMOVGb/CMOVNLEb (cmov greater) */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 14735 | delta = dis_cmov_E_G(sorb, sz, (X86Condcode)(opc - 0x40), delta); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14736 | break; |
| 14737 | |
| 14738 | /* =-=-=-=-=-=-=-=-=- CMPXCHG -=-=-=-=-=-=-=-=-=-= */ |
| 14739 | |
sewardj | c744e87 | 2004-08-26 11:24:39 +0000 | [diff] [blame] | 14740 | case 0xB0: /* CMPXCHG Gb,Eb */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14741 | delta = dis_cmpxchg_G_E ( sorb, pfx_lock, 1, delta ); |
sewardj | c744e87 | 2004-08-26 11:24:39 +0000 | [diff] [blame] | 14742 | break; |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14743 | case 0xB1: /* CMPXCHG Gv,Ev */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14744 | delta = dis_cmpxchg_G_E ( sorb, pfx_lock, sz, delta ); |
sewardj | 458a6f8 | 2004-08-25 12:46:02 +0000 | [diff] [blame] | 14745 | break; |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14746 | |
| 14747 | case 0xC7: { /* CMPXCHG8B Gv (0F C7 /1) */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14748 | IRTemp expdHi = newTemp(Ity_I32); |
| 14749 | IRTemp expdLo = newTemp(Ity_I32); |
| 14750 | IRTemp dataHi = newTemp(Ity_I32); |
| 14751 | IRTemp dataLo = newTemp(Ity_I32); |
| 14752 | IRTemp oldHi = newTemp(Ity_I32); |
| 14753 | IRTemp oldLo = newTemp(Ity_I32); |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14754 | IRTemp flags_old = newTemp(Ity_I32); |
| 14755 | IRTemp flags_new = newTemp(Ity_I32); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14756 | IRTemp success = newTemp(Ity_I1); |
| 14757 | |
| 14758 | /* Translate this using a DCAS, even if there is no LOCK |
| 14759 | prefix. Life is too short to bother with generating two |
| 14760 | different translations for the with/without-LOCK-prefix |
| 14761 | cases. */ |
| 14762 | *expect_CAS = True; |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14763 | |
| 14764 | /* Decode, and generate address. */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14765 | if (sz != 4) goto decode_failure; |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14766 | modrm = getIByte(delta); |
| 14767 | if (epartIsReg(modrm)) goto decode_failure; |
| 14768 | if (gregOfRM(modrm) != 1) goto decode_failure; |
| 14769 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 14770 | delta += alen; |
| 14771 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14772 | /* Get the expected and new values. */ |
| 14773 | assign( expdHi, getIReg(4,R_EDX) ); |
| 14774 | assign( expdLo, getIReg(4,R_EAX) ); |
| 14775 | assign( dataHi, getIReg(4,R_ECX) ); |
| 14776 | assign( dataLo, getIReg(4,R_EBX) ); |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14777 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14778 | /* Do the DCAS */ |
| 14779 | stmt( IRStmt_CAS( |
| 14780 | mkIRCAS( oldHi, oldLo, |
| 14781 | Iend_LE, mkexpr(addr), |
| 14782 | mkexpr(expdHi), mkexpr(expdLo), |
| 14783 | mkexpr(dataHi), mkexpr(dataLo) |
| 14784 | ))); |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14785 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14786 | /* success when oldHi:oldLo == expdHi:expdLo */ |
| 14787 | assign( success, |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 14788 | binop(Iop_CasCmpEQ32, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14789 | binop(Iop_Or32, |
| 14790 | binop(Iop_Xor32, mkexpr(oldHi), mkexpr(expdHi)), |
| 14791 | binop(Iop_Xor32, mkexpr(oldLo), mkexpr(expdLo)) |
| 14792 | ), |
| 14793 | mkU32(0) |
| 14794 | )); |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14795 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14796 | /* If the DCAS is successful, that is to say oldHi:oldLo == |
| 14797 | expdHi:expdLo, then put expdHi:expdLo back in EDX:EAX, |
| 14798 | which is where they came from originally. Both the actual |
| 14799 | contents of these two regs, and any shadow values, are |
| 14800 | unchanged. If the DCAS fails then we're putting into |
| 14801 | EDX:EAX the value seen in memory. */ |
| 14802 | putIReg(4, R_EDX, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 14803 | IRExpr_ITE( mkexpr(success), |
| 14804 | mkexpr(expdHi), mkexpr(oldHi) |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14805 | )); |
| 14806 | putIReg(4, R_EAX, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 14807 | IRExpr_ITE( mkexpr(success), |
| 14808 | mkexpr(expdLo), mkexpr(oldLo) |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14809 | )); |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14810 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14811 | /* Copy the success bit into the Z flag and leave the others |
| 14812 | unchanged */ |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14813 | assign( flags_old, widenUto32(mk_x86g_calculate_eflags_all())); |
| 14814 | assign( |
| 14815 | flags_new, |
| 14816 | binop(Iop_Or32, |
| 14817 | binop(Iop_And32, mkexpr(flags_old), |
| 14818 | mkU32(~X86G_CC_MASK_Z)), |
| 14819 | binop(Iop_Shl32, |
| 14820 | binop(Iop_And32, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 14821 | unop(Iop_1Uto32, mkexpr(success)), mkU32(1)), |
sewardj | 300bb87 | 2005-08-12 23:04:48 +0000 | [diff] [blame] | 14822 | mkU8(X86G_CC_SHIFT_Z)) )); |
| 14823 | |
| 14824 | stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); |
| 14825 | stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(flags_new) )); |
| 14826 | stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); |
| 14827 | /* Set NDEP even though it isn't used. This makes |
| 14828 | redundant-PUT elimination of previous stores to this field |
| 14829 | work better. */ |
| 14830 | stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); |
| 14831 | |
| 14832 | /* Sheesh. Aren't you glad it was me and not you that had to |
| 14833 | write and validate all this grunge? */ |
| 14834 | |
| 14835 | DIP("cmpxchg8b %s\n", dis_buf); |
| 14836 | break; |
| 14837 | } |
| 14838 | |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 14839 | /* =-=-=-=-=-=-=-=-=- CPUID -=-=-=-=-=-=-=-=-=-=-= */ |
| 14840 | |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14841 | case 0xA2: { /* CPUID */ |
| 14842 | /* Uses dirty helper: |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 14843 | void dirtyhelper_CPUID_sse[012] ( VexGuestX86State* ) |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14844 | declared to mod eax, wr ebx, ecx, edx |
| 14845 | */ |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 14846 | IRDirty* d = NULL; |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 14847 | void* fAddr = NULL; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 14848 | const HChar* fName = NULL; |
philippe | 6d7c8e4 | 2015-06-17 21:33:19 +0000 | [diff] [blame] | 14849 | if (archinfo->hwcaps & VEX_HWCAPS_X86_SSE3) { |
| 14850 | fName = "x86g_dirtyhelper_CPUID_sse3"; |
| 14851 | fAddr = &x86g_dirtyhelper_CPUID_sse3; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 14852 | } |
| 14853 | else |
philippe | 7ffce01 | 2015-06-18 21:31:32 +0000 | [diff] [blame] | 14854 | if (archinfo->hwcaps & VEX_HWCAPS_X86_SSE2) { |
| 14855 | fName = "x86g_dirtyhelper_CPUID_sse2"; |
| 14856 | fAddr = &x86g_dirtyhelper_CPUID_sse2; |
| 14857 | } |
| 14858 | else |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 14859 | if (archinfo->hwcaps & VEX_HWCAPS_X86_SSE1) { |
| 14860 | fName = "x86g_dirtyhelper_CPUID_sse1"; |
| 14861 | fAddr = &x86g_dirtyhelper_CPUID_sse1; |
| 14862 | } |
| 14863 | else |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 14864 | if (archinfo->hwcaps & VEX_HWCAPS_X86_MMXEXT) { |
| 14865 | fName = "x86g_dirtyhelper_CPUID_mmxext"; |
| 14866 | fAddr = &x86g_dirtyhelper_CPUID_mmxext; |
| 14867 | } |
| 14868 | else |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 14869 | if (archinfo->hwcaps == 0/*no SSE*/) { |
| 14870 | fName = "x86g_dirtyhelper_CPUID_sse0"; |
| 14871 | fAddr = &x86g_dirtyhelper_CPUID_sse0; |
| 14872 | } else |
| 14873 | vpanic("disInstr(x86)(cpuid)"); |
| 14874 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 14875 | vassert(fName); vassert(fAddr); |
| 14876 | d = unsafeIRDirty_0_N ( 0/*regparms*/, |
florian | 9041956 | 2013-08-15 20:54:52 +0000 | [diff] [blame] | 14877 | fName, fAddr, mkIRExprVec_1(IRExpr_BBPTR()) ); |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14878 | /* declare guest state effects */ |
| 14879 | d->nFxState = 4; |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 14880 | vex_bzero(&d->fxState, sizeof(d->fxState)); |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14881 | d->fxState[0].fx = Ifx_Modify; |
| 14882 | d->fxState[0].offset = OFFB_EAX; |
| 14883 | d->fxState[0].size = 4; |
| 14884 | d->fxState[1].fx = Ifx_Write; |
| 14885 | d->fxState[1].offset = OFFB_EBX; |
| 14886 | d->fxState[1].size = 4; |
sewardj | 32bfd3e | 2008-02-10 13:29:19 +0000 | [diff] [blame] | 14887 | d->fxState[2].fx = Ifx_Modify; |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14888 | d->fxState[2].offset = OFFB_ECX; |
| 14889 | d->fxState[2].size = 4; |
| 14890 | d->fxState[3].fx = Ifx_Write; |
| 14891 | d->fxState[3].offset = OFFB_EDX; |
| 14892 | d->fxState[3].size = 4; |
| 14893 | /* execute the dirty call, side-effecting guest state */ |
| 14894 | stmt( IRStmt_Dirty(d) ); |
sewardj | 55860d8 | 2005-01-08 18:25:05 +0000 | [diff] [blame] | 14895 | /* CPUID is a serialising insn. So, just in case someone is |
| 14896 | using it as a memory fence ... */ |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 14897 | stmt( IRStmt_MBE(Imbe_Fence) ); |
sewardj | 517a7d6 | 2004-10-25 09:52:18 +0000 | [diff] [blame] | 14898 | DIP("cpuid\n"); |
sewardj | 588ea76 | 2004-09-10 18:56:32 +0000 | [diff] [blame] | 14899 | break; |
sewardj | 7cb49d7 | 2004-10-24 22:31:25 +0000 | [diff] [blame] | 14900 | } |
| 14901 | |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 14902 | //-- if (!VG_(cpu_has_feature)(VG_X86_FEAT_CPUID)) |
| 14903 | //-- goto decode_failure; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 14904 | //-- |
| 14905 | //-- t1 = newTemp(cb); |
| 14906 | //-- t2 = newTemp(cb); |
| 14907 | //-- t3 = newTemp(cb); |
| 14908 | //-- t4 = newTemp(cb); |
| 14909 | //-- uInstr0(cb, CALLM_S, 0); |
| 14910 | //-- |
| 14911 | //-- uInstr2(cb, GET, 4, ArchReg, R_EAX, TempReg, t1); |
| 14912 | //-- uInstr1(cb, PUSH, 4, TempReg, t1); |
| 14913 | //-- |
| 14914 | //-- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t2); |
| 14915 | //-- uLiteral(cb, 0); |
| 14916 | //-- uInstr1(cb, PUSH, 4, TempReg, t2); |
| 14917 | //-- |
| 14918 | //-- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t3); |
| 14919 | //-- uLiteral(cb, 0); |
| 14920 | //-- uInstr1(cb, PUSH, 4, TempReg, t3); |
| 14921 | //-- |
| 14922 | //-- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t4); |
| 14923 | //-- uLiteral(cb, 0); |
| 14924 | //-- uInstr1(cb, PUSH, 4, TempReg, t4); |
| 14925 | //-- |
| 14926 | //-- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_CPUID)); |
| 14927 | //-- uFlagsRWU(cb, FlagsEmpty, FlagsEmpty, FlagsEmpty); |
| 14928 | //-- |
| 14929 | //-- uInstr1(cb, POP, 4, TempReg, t4); |
| 14930 | //-- uInstr2(cb, PUT, 4, TempReg, t4, ArchReg, R_EDX); |
| 14931 | //-- |
| 14932 | //-- uInstr1(cb, POP, 4, TempReg, t3); |
| 14933 | //-- uInstr2(cb, PUT, 4, TempReg, t3, ArchReg, R_ECX); |
| 14934 | //-- |
| 14935 | //-- uInstr1(cb, POP, 4, TempReg, t2); |
| 14936 | //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_EBX); |
| 14937 | //-- |
| 14938 | //-- uInstr1(cb, POP, 4, TempReg, t1); |
| 14939 | //-- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, R_EAX); |
| 14940 | //-- |
| 14941 | //-- uInstr0(cb, CALLM_E, 0); |
| 14942 | //-- DIP("cpuid\n"); |
| 14943 | //-- break; |
| 14944 | //-- |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 14945 | /* =-=-=-=-=-=-=-=-=- MOVZX, MOVSX =-=-=-=-=-=-=-= */ |
| 14946 | |
| 14947 | case 0xB6: /* MOVZXb Eb,Gv */ |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14948 | if (sz != 2 && sz != 4) |
| 14949 | goto decode_failure; |
| 14950 | delta = dis_movx_E_G ( sorb, delta, 1, sz, False ); |
sewardj | 9334b0f | 2004-07-10 22:43:54 +0000 | [diff] [blame] | 14951 | break; |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14952 | |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14953 | case 0xB7: /* MOVZXw Ew,Gv */ |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14954 | if (sz != 4) |
| 14955 | goto decode_failure; |
sewardj | 940e8c9 | 2004-07-11 16:53:24 +0000 | [diff] [blame] | 14956 | delta = dis_movx_E_G ( sorb, delta, 2, 4, False ); |
| 14957 | break; |
| 14958 | |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14959 | case 0xBE: /* MOVSXb Eb,Gv */ |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14960 | if (sz != 2 && sz != 4) |
| 14961 | goto decode_failure; |
| 14962 | delta = dis_movx_E_G ( sorb, delta, 1, sz, True ); |
sewardj | 0611d80 | 2004-07-11 02:37:54 +0000 | [diff] [blame] | 14963 | break; |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14964 | |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 14965 | case 0xBF: /* MOVSXw Ew,Gv */ |
sewardj | 33ca4ac | 2010-09-30 13:37:31 +0000 | [diff] [blame] | 14966 | if (sz != 4 && /* accept movsww, sigh, see #250799 */sz != 2) |
sewardj | 6ba982f | 2006-05-03 17:57:15 +0000 | [diff] [blame] | 14967 | goto decode_failure; |
sewardj | 33ca4ac | 2010-09-30 13:37:31 +0000 | [diff] [blame] | 14968 | delta = dis_movx_E_G ( sorb, delta, 2, sz, True ); |
sewardj | 7ed2295 | 2004-07-29 00:09:58 +0000 | [diff] [blame] | 14969 | break; |
| 14970 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 14971 | //-- /* =-=-=-=-=-=-=-=-=-=-= MOVNTI -=-=-=-=-=-=-=-=-= */ |
| 14972 | //-- |
| 14973 | //-- case 0xC3: /* MOVNTI Gv,Ev */ |
| 14974 | //-- vg_assert(sz == 4); |
| 14975 | //-- modrm = getUChar(eip); |
| 14976 | //-- vg_assert(!epartIsReg(modrm)); |
| 14977 | //-- t1 = newTemp(cb); |
| 14978 | //-- uInstr2(cb, GET, 4, ArchReg, gregOfRM(modrm), TempReg, t1); |
| 14979 | //-- pair = disAMode ( cb, sorb, eip, dis_buf ); |
| 14980 | //-- t2 = LOW24(pair); |
| 14981 | //-- eip += HI8(pair); |
| 14982 | //-- uInstr2(cb, STORE, 4, TempReg, t1, TempReg, t2); |
| 14983 | //-- DIP("movnti %s,%s\n", nameIReg(4,gregOfRM(modrm)), dis_buf); |
| 14984 | //-- break; |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 14985 | |
| 14986 | /* =-=-=-=-=-=-=-=-=- MUL/IMUL =-=-=-=-=-=-=-=-=-= */ |
| 14987 | |
| 14988 | case 0xAF: /* IMUL Ev, Gv */ |
sewardj | 2a2ba8b | 2004-11-08 13:14:06 +0000 | [diff] [blame] | 14989 | delta = dis_mul_E_G ( sorb, sz, delta ); |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 14990 | break; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 14991 | |
sewardj | ec387ca | 2006-08-01 18:36:25 +0000 | [diff] [blame] | 14992 | /* =-=-=-=-=-=-=-=-=- NOPs =-=-=-=-=-=-=-=-=-=-=-= */ |
| 14993 | |
| 14994 | case 0x1F: |
| 14995 | modrm = getUChar(delta); |
| 14996 | if (epartIsReg(modrm)) goto decode_failure; |
| 14997 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 14998 | delta += alen; |
| 14999 | DIP("nop%c %s\n", nameISize(sz), dis_buf); |
| 15000 | break; |
| 15001 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 15002 | /* =-=-=-=-=-=-=-=-=- Jcond d32 -=-=-=-=-=-=-=-=-= */ |
| 15003 | case 0x80: |
| 15004 | case 0x81: |
| 15005 | case 0x82: /* JBb/JNAEb (jump below) */ |
| 15006 | case 0x83: /* JNBb/JAEb (jump not below) */ |
| 15007 | case 0x84: /* JZb/JEb (jump zero) */ |
| 15008 | case 0x85: /* JNZb/JNEb (jump not zero) */ |
| 15009 | case 0x86: /* JBEb/JNAb (jump below or equal) */ |
| 15010 | case 0x87: /* JNBEb/JAb (jump not below or equal) */ |
| 15011 | case 0x88: /* JSb (jump negative) */ |
| 15012 | case 0x89: /* JSb (jump not negative) */ |
| 15013 | case 0x8A: /* JP (jump parity even) */ |
| 15014 | case 0x8B: /* JNP/JPO (jump parity odd) */ |
| 15015 | case 0x8C: /* JLb/JNGEb (jump less) */ |
| 15016 | case 0x8D: /* JGEb/JNLb (jump greater or equal) */ |
| 15017 | case 0x8E: /* JLEb/JNGb (jump less or equal) */ |
| 15018 | case 0x8F: /* JGb/JNLEb (jump greater) */ |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15019 | { Int jmpDelta; |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 15020 | const HChar* comment = ""; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15021 | jmpDelta = (Int)getUDisp32(delta); |
| 15022 | d32 = (((Addr32)guest_EIP_bbstart)+delta+4) + jmpDelta; |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 15023 | delta += 4; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15024 | if (resteerCisOk |
| 15025 | && vex_control.guest_chase_cond |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 15026 | && (Addr32)d32 != (Addr32)guest_EIP_bbstart |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15027 | && jmpDelta < 0 |
florian | beac530 | 2014-12-31 12:09:38 +0000 | [diff] [blame] | 15028 | && resteerOkFn( callback_opaque, (Addr32)d32) ) { |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15029 | /* Speculation: assume this backward branch is taken. So |
| 15030 | we need to emit a side-exit to the insn following this |
| 15031 | one, on the negation of the condition, and continue at |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 15032 | the branch target address (d32). If we wind up back at |
| 15033 | the first instruction of the trace, just stop; it's |
| 15034 | better to let the IR loop unroller handle that case.*/ |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15035 | stmt( IRStmt_Exit( |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 15036 | mk_x86g_calculate_condition((X86Condcode) |
| 15037 | (1 ^ (opc - 0x80))), |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15038 | Ijk_Boring, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 15039 | IRConst_U32(guest_EIP_bbstart+delta), |
| 15040 | OFFB_EIP ) ); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15041 | dres.whatNext = Dis_ResteerC; |
florian | 0eaa35f | 2015-01-02 13:34:15 +0000 | [diff] [blame] | 15042 | dres.continueAt = (Addr32)d32; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15043 | comment = "(assumed taken)"; |
| 15044 | } |
| 15045 | else |
| 15046 | if (resteerCisOk |
| 15047 | && vex_control.guest_chase_cond |
sewardj | 0d925b1 | 2010-01-17 15:47:01 +0000 | [diff] [blame] | 15048 | && (Addr32)d32 != (Addr32)guest_EIP_bbstart |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15049 | && jmpDelta >= 0 |
| 15050 | && resteerOkFn( callback_opaque, |
florian | beac530 | 2014-12-31 12:09:38 +0000 | [diff] [blame] | 15051 | (Addr32)(guest_EIP_bbstart+delta)) ) { |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15052 | /* Speculation: assume this forward branch is not taken. |
| 15053 | So we need to emit a side-exit to d32 (the dest) and |
| 15054 | continue disassembling at the insn immediately |
| 15055 | following this one. */ |
| 15056 | stmt( IRStmt_Exit( |
| 15057 | mk_x86g_calculate_condition((X86Condcode)(opc - 0x80)), |
| 15058 | Ijk_Boring, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 15059 | IRConst_U32(d32), |
| 15060 | OFFB_EIP ) ); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15061 | dres.whatNext = Dis_ResteerC; |
florian | 0eaa35f | 2015-01-02 13:34:15 +0000 | [diff] [blame] | 15062 | dres.continueAt = guest_EIP_bbstart + delta; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15063 | comment = "(assumed not taken)"; |
| 15064 | } |
| 15065 | else { |
| 15066 | /* Conservative default translation - end the block at |
| 15067 | this point. */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 15068 | jcc_01( &dres, (X86Condcode)(opc - 0x80), |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15069 | (Addr32)(guest_EIP_bbstart+delta), d32); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 15070 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15071 | } |
| 15072 | DIP("j%s-32 0x%x %s\n", name_X86Condcode(opc - 0x80), d32, comment); |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 15073 | break; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15074 | } |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 15075 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 15076 | /* =-=-=-=-=-=-=-=-=- RDTSC -=-=-=-=-=-=-=-=-=-=-= */ |
sewardj | 4ed6429 | 2005-08-23 19:24:29 +0000 | [diff] [blame] | 15077 | case 0x31: { /* RDTSC */ |
| 15078 | IRTemp val = newTemp(Ity_I64); |
| 15079 | IRExpr** args = mkIRExprVec_0(); |
| 15080 | IRDirty* d = unsafeIRDirty_1_N ( |
| 15081 | val, |
| 15082 | 0/*regparms*/, |
| 15083 | "x86g_dirtyhelper_RDTSC", |
| 15084 | &x86g_dirtyhelper_RDTSC, |
| 15085 | args |
| 15086 | ); |
sewardj | a5cbbdc | 2005-08-23 23:17:38 +0000 | [diff] [blame] | 15087 | /* execute the dirty call, dumping the result in val. */ |
| 15088 | stmt( IRStmt_Dirty(d) ); |
| 15089 | putIReg(4, R_EDX, unop(Iop_64HIto32, mkexpr(val))); |
| 15090 | putIReg(4, R_EAX, unop(Iop_64to32, mkexpr(val))); |
| 15091 | DIP("rdtsc\n"); |
| 15092 | break; |
sewardj | 4ed6429 | 2005-08-23 19:24:29 +0000 | [diff] [blame] | 15093 | } |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 15094 | |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 15095 | /* =-=-=-=-=-=-=-=-=- PUSH/POP Sreg =-=-=-=-=-=-=-=-=-= */ |
| 15096 | |
| 15097 | case 0xA1: /* POP %FS */ |
| 15098 | dis_pop_segreg( R_FS, sz ); break; |
| 15099 | case 0xA9: /* POP %GS */ |
| 15100 | dis_pop_segreg( R_GS, sz ); break; |
| 15101 | |
| 15102 | case 0xA0: /* PUSH %FS */ |
| 15103 | dis_push_segreg( R_FS, sz ); break; |
| 15104 | case 0xA8: /* PUSH %GS */ |
| 15105 | dis_push_segreg( R_GS, sz ); break; |
| 15106 | |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 15107 | /* =-=-=-=-=-=-=-=-=- SETcc Eb =-=-=-=-=-=-=-=-=-= */ |
| 15108 | case 0x90: |
| 15109 | case 0x91: |
| 15110 | case 0x92: /* set-Bb/set-NAEb (jump below) */ |
| 15111 | case 0x93: /* set-NBb/set-AEb (jump not below) */ |
| 15112 | case 0x94: /* set-Zb/set-Eb (jump zero) */ |
| 15113 | case 0x95: /* set-NZb/set-NEb (jump not zero) */ |
| 15114 | case 0x96: /* set-BEb/set-NAb (jump below or equal) */ |
| 15115 | case 0x97: /* set-NBEb/set-Ab (jump not below or equal) */ |
| 15116 | case 0x98: /* set-Sb (jump negative) */ |
| 15117 | case 0x99: /* set-Sb (jump not negative) */ |
| 15118 | case 0x9A: /* set-P (jump parity even) */ |
| 15119 | case 0x9B: /* set-NP (jump parity odd) */ |
| 15120 | case 0x9C: /* set-Lb/set-NGEb (jump less) */ |
| 15121 | case 0x9D: /* set-GEb/set-NLb (jump greater or equal) */ |
| 15122 | case 0x9E: /* set-LEb/set-NGb (jump less or equal) */ |
| 15123 | case 0x9F: /* set-Gb/set-NLEb (jump greater) */ |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 15124 | t1 = newTemp(Ity_I8); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 15125 | assign( t1, unop(Iop_1Uto8,mk_x86g_calculate_condition(opc-0x90)) ); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 15126 | modrm = getIByte(delta); |
| 15127 | if (epartIsReg(modrm)) { |
| 15128 | delta++; |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 15129 | putIReg(1, eregOfRM(modrm), mkexpr(t1)); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 15130 | DIP("set%s %s\n", name_X86Condcode(opc-0x90), |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 15131 | nameIReg(1,eregOfRM(modrm))); |
| 15132 | } else { |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 15133 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 15134 | delta += alen; |
| 15135 | storeLE( mkexpr(addr), mkexpr(t1) ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 15136 | DIP("set%s %s\n", name_X86Condcode(opc-0x90), dis_buf); |
sewardj | 77b86be | 2004-07-11 13:28:24 +0000 | [diff] [blame] | 15137 | } |
| 15138 | break; |
| 15139 | |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 15140 | /* =-=-=-=-=-=-=-=-=- SHLD/SHRD -=-=-=-=-=-=-=-=-= */ |
| 15141 | |
| 15142 | case 0xA4: /* SHLDv imm8,Gv,Ev */ |
| 15143 | modrm = getIByte(delta); |
| 15144 | d32 = delta + lengthAMode(delta); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 15145 | vex_sprintf(dis_buf, "$%d", getIByte(d32)); |
sewardj | 180e8b3 | 2004-07-29 01:40:11 +0000 | [diff] [blame] | 15146 | delta = dis_SHLRD_Gv_Ev ( |
| 15147 | sorb, delta, modrm, sz, |
| 15148 | mkU8(getIByte(d32)), True, /* literal */ |
| 15149 | dis_buf, True ); |
| 15150 | break; |
sewardj | a06e556 | 2004-07-14 13:18:05 +0000 | [diff] [blame] | 15151 | case 0xA5: /* SHLDv %cl,Gv,Ev */ |
| 15152 | modrm = getIByte(delta); |
| 15153 | delta = dis_SHLRD_Gv_Ev ( |
| 15154 | sorb, delta, modrm, sz, |
| 15155 | getIReg(1,R_ECX), False, /* not literal */ |
| 15156 | "%cl", True ); |
| 15157 | break; |
| 15158 | |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 15159 | case 0xAC: /* SHRDv imm8,Gv,Ev */ |
| 15160 | modrm = getIByte(delta); |
| 15161 | d32 = delta + lengthAMode(delta); |
sewardj | 2d49b43 | 2005-02-01 00:37:06 +0000 | [diff] [blame] | 15162 | vex_sprintf(dis_buf, "$%d", getIByte(d32)); |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 15163 | delta = dis_SHLRD_Gv_Ev ( |
| 15164 | sorb, delta, modrm, sz, |
| 15165 | mkU8(getIByte(d32)), True, /* literal */ |
| 15166 | dis_buf, False ); |
| 15167 | break; |
sewardj | a511afc | 2004-07-29 22:26:03 +0000 | [diff] [blame] | 15168 | case 0xAD: /* SHRDv %cl,Gv,Ev */ |
| 15169 | modrm = getIByte(delta); |
| 15170 | delta = dis_SHLRD_Gv_Ev ( |
| 15171 | sorb, delta, modrm, sz, |
| 15172 | getIReg(1,R_ECX), False, /* not literal */ |
| 15173 | "%cl", False ); |
| 15174 | break; |
| 15175 | |
sewardj | f07ed03 | 2005-08-07 14:48:03 +0000 | [diff] [blame] | 15176 | /* =-=-=-=-=-=-=-=-=- SYSENTER -=-=-=-=-=-=-=-=-=-= */ |
| 15177 | |
| 15178 | case 0x34: |
| 15179 | /* Simple implementation needing a long explaination. |
| 15180 | |
| 15181 | sysenter is a kind of syscall entry. The key thing here |
| 15182 | is that the return address is not known -- that is |
| 15183 | something that is beyond Vex's knowledge. So this IR |
| 15184 | forces a return to the scheduler, which can do what it |
sewardj | 4fa325a | 2005-11-03 13:27:24 +0000 | [diff] [blame] | 15185 | likes to simulate the systenter, but it MUST set this |
sewardj | f07ed03 | 2005-08-07 14:48:03 +0000 | [diff] [blame] | 15186 | thread's guest_EIP field with the continuation address |
| 15187 | before resuming execution. If that doesn't happen, the |
| 15188 | thread will jump to address zero, which is probably |
| 15189 | fatal. |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 15190 | */ |
| 15191 | |
| 15192 | /* Note where we are, so we can back up the guest to this |
| 15193 | point if the syscall needs to be restarted. */ |
| 15194 | stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL, |
| 15195 | mkU32(guest_EIP_curr_instr) ) ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 15196 | jmp_lit(&dres, Ijk_Sys_sysenter, 0/*bogus next EIP value*/); |
| 15197 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | f07ed03 | 2005-08-07 14:48:03 +0000 | [diff] [blame] | 15198 | DIP("sysenter"); |
| 15199 | break; |
| 15200 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 15201 | /* =-=-=-=-=-=-=-=-=- XADD -=-=-=-=-=-=-=-=-=-= */ |
| 15202 | |
sewardj | 0092e0d | 2006-03-06 13:35:42 +0000 | [diff] [blame] | 15203 | case 0xC0: { /* XADD Gb,Eb */ |
| 15204 | Bool decodeOK; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15205 | delta = dis_xadd_G_E ( sorb, pfx_lock, 1, delta, &decodeOK ); |
sewardj | 0092e0d | 2006-03-06 13:35:42 +0000 | [diff] [blame] | 15206 | if (!decodeOK) goto decode_failure; |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 15207 | break; |
sewardj | 0092e0d | 2006-03-06 13:35:42 +0000 | [diff] [blame] | 15208 | } |
| 15209 | case 0xC1: { /* XADD Gv,Ev */ |
| 15210 | Bool decodeOK; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15211 | delta = dis_xadd_G_E ( sorb, pfx_lock, sz, delta, &decodeOK ); |
sewardj | 0092e0d | 2006-03-06 13:35:42 +0000 | [diff] [blame] | 15212 | if (!decodeOK) goto decode_failure; |
| 15213 | break; |
| 15214 | } |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 15215 | |
sewardj | f13f37b | 2004-12-08 17:01:23 +0000 | [diff] [blame] | 15216 | /* =-=-=-=-=-=-=-=-=- MMXery =-=-=-=-=-=-=-=-=-=-= */ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 15217 | |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 15218 | case 0x71: |
| 15219 | case 0x72: |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 15220 | case 0x73: /* PSLLgg/PSRAgg/PSRLgg mmxreg by imm8 */ |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 15221 | |
| 15222 | case 0x6E: /* MOVD (src)ireg-or-mem, (dst)mmxreg */ |
| 15223 | case 0x7E: /* MOVD (src)mmxreg, (dst)ireg-or-mem */ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 15224 | case 0x7F: /* MOVQ (src)mmxreg, (dst)mmxreg-or-mem */ |
sewardj | 2b7a920 | 2004-11-26 19:15:38 +0000 | [diff] [blame] | 15225 | case 0x6F: /* MOVQ (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 15226 | |
| 15227 | case 0xFC: |
| 15228 | case 0xFD: |
| 15229 | case 0xFE: /* PADDgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15230 | |
| 15231 | case 0xEC: |
| 15232 | case 0xED: /* PADDSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15233 | |
| 15234 | case 0xDC: |
| 15235 | case 0xDD: /* PADDUSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15236 | |
| 15237 | case 0xF8: |
| 15238 | case 0xF9: |
| 15239 | case 0xFA: /* PSUBgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15240 | |
| 15241 | case 0xE8: |
| 15242 | case 0xE9: /* PSUBSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15243 | |
| 15244 | case 0xD8: |
| 15245 | case 0xD9: /* PSUBUSgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15246 | |
| 15247 | case 0xE5: /* PMULHW (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15248 | case 0xD5: /* PMULLW (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15249 | |
sewardj | 4340dac | 2004-11-20 13:17:04 +0000 | [diff] [blame] | 15250 | case 0xF5: /* PMADDWD (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15251 | |
| 15252 | case 0x74: |
| 15253 | case 0x75: |
| 15254 | case 0x76: /* PCMPEQgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15255 | |
| 15256 | case 0x64: |
| 15257 | case 0x65: |
| 15258 | case 0x66: /* PCMPGTgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15259 | |
sewardj | 63ba409 | 2004-11-21 12:30:18 +0000 | [diff] [blame] | 15260 | case 0x6B: /* PACKSSDW (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15261 | case 0x63: /* PACKSSWB (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15262 | case 0x67: /* PACKUSWB (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15263 | |
| 15264 | case 0x68: |
| 15265 | case 0x69: |
| 15266 | case 0x6A: /* PUNPCKHgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15267 | |
| 15268 | case 0x60: |
| 15269 | case 0x61: |
| 15270 | case 0x62: /* PUNPCKLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15271 | |
| 15272 | case 0xDB: /* PAND (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15273 | case 0xDF: /* PANDN (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15274 | case 0xEB: /* POR (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15275 | case 0xEF: /* PXOR (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15276 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 15277 | case 0xF1: /* PSLLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 15278 | case 0xF2: |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 15279 | case 0xF3: |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 15280 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 15281 | case 0xD1: /* PSRLgg (src)mmxreg-or-mem, (dst)mmxreg */ |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 15282 | case 0xD2: |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 15283 | case 0xD3: |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 15284 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 15285 | case 0xE1: /* PSRAgg (src)mmxreg-or-mem, (dst)mmxreg */ |
| 15286 | case 0xE2: |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 15287 | { |
sewardj | 52d0491 | 2005-07-03 00:52:48 +0000 | [diff] [blame] | 15288 | Int delta0 = delta-1; |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 15289 | Bool decode_OK = False; |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 15290 | |
| 15291 | /* If sz==2 this is SSE, and we assume sse idec has |
| 15292 | already spotted those cases by now. */ |
| 15293 | if (sz != 4) |
| 15294 | goto decode_failure; |
| 15295 | |
sewardj | 464efa4 | 2004-11-19 22:17:29 +0000 | [diff] [blame] | 15296 | delta = dis_MMX ( &decode_OK, sorb, sz, delta-1 ); |
| 15297 | if (!decode_OK) { |
| 15298 | delta = delta0; |
| 15299 | goto decode_failure; |
| 15300 | } |
| 15301 | break; |
| 15302 | } |
| 15303 | |
tom | e3aa016 | 2011-08-11 14:43:12 +0000 | [diff] [blame] | 15304 | case 0x0E: /* FEMMS */ |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 15305 | case 0x77: /* EMMS */ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 15306 | if (sz != 4) |
| 15307 | goto decode_failure; |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 15308 | do_EMMS_preamble(); |
tom | e3aa016 | 2011-08-11 14:43:12 +0000 | [diff] [blame] | 15309 | DIP("{f}emms\n"); |
sewardj | 8d14a59 | 2004-11-21 17:04:50 +0000 | [diff] [blame] | 15310 | break; |
| 15311 | |
sewardj | b9dc243 | 2010-06-07 16:22:22 +0000 | [diff] [blame] | 15312 | /* =-=-=-=-=-=-=-=-=- SGDT and SIDT =-=-=-=-=-=-=-=-=-=-= */ |
| 15313 | case 0x01: /* 0F 01 /0 -- SGDT */ |
| 15314 | /* 0F 01 /1 -- SIDT */ |
| 15315 | { |
| 15316 | /* This is really revolting, but ... since each processor |
| 15317 | (core) only has one IDT and one GDT, just let the guest |
| 15318 | see it (pass-through semantics). I can't see any way to |
| 15319 | construct a faked-up value, so don't bother to try. */ |
| 15320 | modrm = getUChar(delta); |
| 15321 | addr = disAMode ( &alen, sorb, delta, dis_buf ); |
| 15322 | delta += alen; |
| 15323 | if (epartIsReg(modrm)) goto decode_failure; |
| 15324 | if (gregOfRM(modrm) != 0 && gregOfRM(modrm) != 1) |
| 15325 | goto decode_failure; |
| 15326 | switch (gregOfRM(modrm)) { |
| 15327 | case 0: DIP("sgdt %s\n", dis_buf); break; |
| 15328 | case 1: DIP("sidt %s\n", dis_buf); break; |
| 15329 | default: vassert(0); /*NOTREACHED*/ |
| 15330 | } |
| 15331 | |
| 15332 | IRDirty* d = unsafeIRDirty_0_N ( |
| 15333 | 0/*regparms*/, |
| 15334 | "x86g_dirtyhelper_SxDT", |
| 15335 | &x86g_dirtyhelper_SxDT, |
| 15336 | mkIRExprVec_2( mkexpr(addr), |
| 15337 | mkU32(gregOfRM(modrm)) ) |
| 15338 | ); |
| 15339 | /* declare we're writing memory */ |
| 15340 | d->mFx = Ifx_Write; |
| 15341 | d->mAddr = mkexpr(addr); |
| 15342 | d->mSize = 6; |
| 15343 | stmt( IRStmt_Dirty(d) ); |
| 15344 | break; |
| 15345 | } |
| 15346 | |
tom | f0bb679 | 2014-02-09 11:40:20 +0000 | [diff] [blame] | 15347 | case 0x05: /* AMD's syscall */ |
| 15348 | stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL, |
sewardj | 3e5d82d | 2015-07-21 14:43:23 +0000 | [diff] [blame] | 15349 | mkU32(guest_EIP_curr_instr) ) ); |
tom | f0bb679 | 2014-02-09 11:40:20 +0000 | [diff] [blame] | 15350 | jmp_lit(&dres, Ijk_Sys_syscall, ((Addr32)guest_EIP_bbstart)+delta); |
| 15351 | vassert(dres.whatNext == Dis_StopHere); |
| 15352 | DIP("syscall\n"); |
| 15353 | break; |
| 15354 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 15355 | /* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */ |
| 15356 | |
| 15357 | default: |
| 15358 | goto decode_failure; |
| 15359 | } /* switch (opc) for the 2-byte opcodes */ |
| 15360 | goto decode_success; |
| 15361 | } /* case 0x0F: of primary opcode */ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15362 | |
| 15363 | /* ------------------------ ??? ------------------------ */ |
| 15364 | |
| 15365 | default: |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 15366 | decode_failure: |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15367 | /* All decode failures end up here. */ |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 15368 | if (sigill_diag) { |
| 15369 | vex_printf("vex x86->IR: unhandled instruction bytes: " |
| 15370 | "0x%x 0x%x 0x%x 0x%x\n", |
florian | b173774 | 2015-08-03 16:03:13 +0000 | [diff] [blame] | 15371 | getIByte(delta_start+0), |
| 15372 | getIByte(delta_start+1), |
| 15373 | getIByte(delta_start+2), |
| 15374 | getIByte(delta_start+3)); |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 15375 | } |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 15376 | |
sewardj | b64821b | 2004-12-14 10:00:16 +0000 | [diff] [blame] | 15377 | /* Tell the dispatcher that this insn cannot be decoded, and so has |
| 15378 | not been executed, and (is currently) the next to be executed. |
| 15379 | EIP should be up-to-date since it made so at the start of each |
| 15380 | insn, but nevertheless be paranoid and update it again right |
| 15381 | now. */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15382 | stmt( IRStmt_Put( OFFB_EIP, mkU32(guest_EIP_curr_instr) ) ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 15383 | jmp_lit(&dres, Ijk_NoDecode, guest_EIP_curr_instr); |
| 15384 | vassert(dres.whatNext == Dis_StopHere); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15385 | dres.len = 0; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15386 | /* We also need to say that a CAS is not expected now, regardless |
| 15387 | of what it might have been set to at the start of the function, |
| 15388 | since the IR that we've emitted just above (to synthesis a |
| 15389 | SIGILL) does not involve any CAS, and presumably no other IR has |
| 15390 | been emitted for this (non-decoded) insn. */ |
| 15391 | *expect_CAS = False; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15392 | return dres; |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 15393 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15394 | } /* switch (opc) for the main (primary) opcode switch. */ |
| 15395 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 15396 | decode_success: |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15397 | /* All decode successes end up here. */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 15398 | switch (dres.whatNext) { |
| 15399 | case Dis_Continue: |
| 15400 | stmt( IRStmt_Put( OFFB_EIP, mkU32(guest_EIP_bbstart + delta) ) ); |
| 15401 | break; |
| 15402 | case Dis_ResteerU: |
| 15403 | case Dis_ResteerC: |
| 15404 | stmt( IRStmt_Put( OFFB_EIP, mkU32(dres.continueAt) ) ); |
| 15405 | break; |
| 15406 | case Dis_StopHere: |
| 15407 | break; |
| 15408 | default: |
| 15409 | vassert(0); |
| 15410 | } |
| 15411 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15412 | DIP("\n"); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15413 | dres.len = delta - delta_start; |
| 15414 | return dres; |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15415 | } |
| 15416 | |
| 15417 | #undef DIP |
| 15418 | #undef DIS |
| 15419 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15420 | |
| 15421 | /*------------------------------------------------------------*/ |
| 15422 | /*--- Top-level fn ---*/ |
| 15423 | /*------------------------------------------------------------*/ |
| 15424 | |
| 15425 | /* Disassemble a single instruction into IR. The instruction |
| 15426 | is located in host memory at &guest_code[delta]. */ |
| 15427 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 15428 | DisResult disInstr_X86 ( IRSB* irsb_IN, |
florian | beac530 | 2014-12-31 12:09:38 +0000 | [diff] [blame] | 15429 | Bool (*resteerOkFn) ( void*, Addr ), |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15430 | Bool resteerCisOk, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 15431 | void* callback_opaque, |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 15432 | const UChar* guest_code_IN, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15433 | Long delta, |
florian | d4cc0de | 2015-01-02 11:44:12 +0000 | [diff] [blame] | 15434 | Addr guest_IP, |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 15435 | VexArch guest_arch, |
florian | cacba8e | 2014-12-15 18:58:07 +0000 | [diff] [blame] | 15436 | const VexArchInfo* archinfo, |
| 15437 | const VexAbiInfo* abiinfo, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 15438 | VexEndness host_endness_IN, |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 15439 | Bool sigill_diag_IN ) |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15440 | { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15441 | Int i, x1, x2; |
| 15442 | Bool expect_CAS, has_CAS; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15443 | DisResult dres; |
| 15444 | |
| 15445 | /* Set globals (see top of this file) */ |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 15446 | vassert(guest_arch == VexArchX86); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15447 | guest_code = guest_code_IN; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 15448 | irsb = irsb_IN; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 15449 | host_endness = host_endness_IN; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15450 | guest_EIP_curr_instr = (Addr32)guest_IP; |
| 15451 | guest_EIP_bbstart = (Addr32)toUInt(guest_IP - delta); |
| 15452 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15453 | x1 = irsb_IN->stmts_used; |
| 15454 | expect_CAS = False; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 15455 | dres = disInstr_X86_WRK ( &expect_CAS, resteerOkFn, |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15456 | resteerCisOk, |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 15457 | callback_opaque, |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 15458 | delta, archinfo, abiinfo, sigill_diag_IN ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15459 | x2 = irsb_IN->stmts_used; |
| 15460 | vassert(x2 >= x1); |
| 15461 | |
| 15462 | /* See comment at the top of disInstr_X86_WRK for meaning of |
| 15463 | expect_CAS. Here, we (sanity-)check for the presence/absence of |
| 15464 | IRCAS as directed by the returned expect_CAS value. */ |
| 15465 | has_CAS = False; |
| 15466 | for (i = x1; i < x2; i++) { |
| 15467 | if (irsb_IN->stmts[i]->tag == Ist_CAS) |
| 15468 | has_CAS = True; |
| 15469 | } |
| 15470 | |
| 15471 | if (expect_CAS != has_CAS) { |
| 15472 | /* inconsistency detected. re-disassemble the instruction so as |
| 15473 | to generate a useful error message; then assert. */ |
| 15474 | vex_traceflags |= VEX_TRACE_FE; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 15475 | dres = disInstr_X86_WRK ( &expect_CAS, resteerOkFn, |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 15476 | resteerCisOk, |
sewardj | 0283430 | 2010-07-29 18:10:51 +0000 | [diff] [blame] | 15477 | callback_opaque, |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 15478 | delta, archinfo, abiinfo, sigill_diag_IN ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 15479 | for (i = x1; i < x2; i++) { |
| 15480 | vex_printf("\t\t"); |
| 15481 | ppIRStmt(irsb_IN->stmts[i]); |
| 15482 | vex_printf("\n"); |
| 15483 | } |
| 15484 | /* Failure of this assertion is serious and denotes a bug in |
| 15485 | disInstr. */ |
| 15486 | vpanic("disInstr_X86: inconsistency in LOCK prefix handling"); |
| 15487 | } |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 15488 | |
| 15489 | return dres; |
| 15490 | } |
| 15491 | |
| 15492 | |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15493 | /*--------------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 15494 | /*--- end guest_x86_toIR.c ---*/ |
sewardj | c9a6570 | 2004-07-07 16:32:57 +0000 | [diff] [blame] | 15495 | /*--------------------------------------------------------------------*/ |