blob: 454ef109ec2b6993a348a97ffe570c8e617d64df [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
Chia-I Wu730e5362014-08-19 12:15:09 +080025#include "genhw/genhw.h"
26#include "kmd/winsys.h"
27#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080028#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080030#include "cmd_priv.h"
Chia-I Wu09142132014-08-11 15:42:55 +080031
Chia-I Wue24c3292014-08-21 14:05:23 +080032static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
33 struct intel_cmd_writer *writer,
34 XGL_UINT size)
Chia-I Wu730e5362014-08-19 12:15:09 +080035{
36 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wue24c3292014-08-21 14:05:23 +080037 const XGL_GPU_SIZE bo_size = sizeof(uint32_t) * size;
Chia-I Wu730e5362014-08-19 12:15:09 +080038 struct intel_bo *bo;
39 void *ptr;
40
41 bo = intel_winsys_alloc_buffer(winsys,
Chia-I Wu32a22462014-08-26 14:13:46 +080042 "batch buffer", bo_size, true);
Chia-I Wu730e5362014-08-19 12:15:09 +080043 if (!bo)
44 return XGL_ERROR_OUT_OF_GPU_MEMORY;
45
46 ptr = intel_bo_map(bo, true);
47 if (!bo) {
48 intel_bo_unreference(bo);
49 return XGL_ERROR_MEMORY_MAP_FAILED;
50 }
51
Chia-I Wue24c3292014-08-21 14:05:23 +080052 writer->bo = bo;
53 writer->ptr_opaque = ptr;
54 writer->size = size;
55 writer->used = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +080056
57 return XGL_SUCCESS;
58}
59
Chia-I Wu5e25c272014-08-21 20:19:12 +080060static void cmd_writer_copy(struct intel_cmd *cmd,
61 struct intel_cmd_writer *writer,
62 const uint32_t *vals, XGL_UINT len)
63{
64 assert(writer->used + len <= writer->size);
65 memcpy((uint32_t *) writer->ptr_opaque + writer->used,
66 vals, sizeof(uint32_t) * len);
67 writer->used += len;
68}
69
70static void cmd_writer_patch(struct intel_cmd *cmd,
71 struct intel_cmd_writer *writer,
72 XGL_UINT pos, uint32_t val)
73{
74 assert(pos < writer->used);
75 ((uint32_t *) writer->ptr_opaque)[pos] = val;
76}
77
Chia-I Wue24c3292014-08-21 14:05:23 +080078void cmd_writer_grow(struct intel_cmd *cmd,
79 struct intel_cmd_writer *writer)
Chia-I Wu730e5362014-08-19 12:15:09 +080080{
Chia-I Wue24c3292014-08-21 14:05:23 +080081 const XGL_UINT size = writer->size << 1;
82 const XGL_UINT old_used = writer->used;
83 struct intel_bo *old_bo = writer->bo;
84 void *old_ptr = writer->ptr_opaque;
85
86 if (size >= writer->size &&
87 cmd_writer_alloc_and_map(cmd, writer, size) == XGL_SUCCESS) {
88 cmd_writer_copy(cmd, writer, (const uint32_t *) old_ptr, old_used);
89
90 intel_bo_unmap(old_bo);
91 intel_bo_unreference(old_bo);
92 } else {
93 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
94 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
95 "failed to grow command buffer of size %u", writer->size);
96
97 /* wrap it and fail silently */
98 writer->used = 0;
99 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
100 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800101}
102
Chia-I Wue24c3292014-08-21 14:05:23 +0800103static void cmd_writer_unmap(struct intel_cmd *cmd,
104 struct intel_cmd_writer *writer)
Chia-I Wu730e5362014-08-19 12:15:09 +0800105{
Chia-I Wue24c3292014-08-21 14:05:23 +0800106 intel_bo_unmap(writer->bo);
107 writer->ptr_opaque = NULL;
108}
109
110static void cmd_writer_free(struct intel_cmd *cmd,
111 struct intel_cmd_writer *writer)
112{
113 intel_bo_unreference(writer->bo);
114 writer->bo = NULL;
115}
116
117static void cmd_writer_reset(struct intel_cmd *cmd,
118 struct intel_cmd_writer *writer)
119{
120 /* do not reset writer->size as we want to know how big it has grown to */
121 writer->used = 0;
122
123 if (writer->ptr_opaque)
124 cmd_writer_unmap(cmd, writer);
125 if (writer->bo)
126 cmd_writer_free(cmd, writer);
127}
128
129static void cmd_unmap(struct intel_cmd *cmd)
130{
131 cmd_writer_unmap(cmd, &cmd->batch);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800132 cmd_writer_unmap(cmd, &cmd->state);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800133 cmd_writer_unmap(cmd, &cmd->kernel);
Chia-I Wu730e5362014-08-19 12:15:09 +0800134}
135
136static void cmd_reset(struct intel_cmd *cmd)
137{
Chia-I Wue24c3292014-08-21 14:05:23 +0800138 cmd_writer_reset(cmd, &cmd->batch);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800139 cmd_writer_reset(cmd, &cmd->state);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800140 cmd_writer_reset(cmd, &cmd->kernel);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800141
Chia-I Wu338fe642014-08-28 10:43:04 +0800142 if (cmd->bind.shaderCache.shaderArray)
143 icd_free(cmd->bind.shaderCache.shaderArray);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800144 memset(&cmd->bind, 0, sizeof(cmd->bind));
145
Chia-I Wu343b1372014-08-20 16:39:20 +0800146 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800147 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800148}
149
150static void cmd_destroy(struct intel_obj *obj)
151{
152 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
153
154 intel_cmd_destroy(cmd);
155}
156
157XGL_RESULT intel_cmd_create(struct intel_dev *dev,
158 const XGL_CMD_BUFFER_CREATE_INFO *info,
159 struct intel_cmd **cmd_ret)
160{
Chia-I Wu63883292014-08-25 13:50:26 +0800161 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800162 struct intel_cmd *cmd;
163
Chia-I Wu63883292014-08-25 13:50:26 +0800164 switch (info->queueType) {
165 case XGL_QUEUE_TYPE_GRAPHICS:
166 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
167 break;
168 case XGL_QUEUE_TYPE_COMPUTE:
169 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
170 break;
171 case XGL_QUEUE_TYPE_DMA:
172 pipeline_select = -1;
173 break;
174 default:
175 return XGL_ERROR_INVALID_VALUE;
176 break;
177 }
178
Chia-I Wu730e5362014-08-19 12:15:09 +0800179 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
180 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
181 if (!cmd)
182 return XGL_ERROR_OUT_OF_MEMORY;
183
184 cmd->obj.destroy = cmd_destroy;
185
186 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800187 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800188 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800189
Chia-I Wue0cdd832014-08-25 12:38:56 +0800190 /*
191 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
192 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
193 * and end offsets, for each referenced memories.
194 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800195 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
196 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
197 4096, XGL_SYSTEM_ALLOC_INTERNAL);
198 if (!cmd->relocs) {
199 intel_cmd_destroy(cmd);
200 return XGL_ERROR_OUT_OF_MEMORY;
201 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800202
203 *cmd_ret = cmd;
204
205 return XGL_SUCCESS;
206}
207
208void intel_cmd_destroy(struct intel_cmd *cmd)
209{
210 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800211
212 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800213 intel_base_destroy(&cmd->obj.base);
214}
215
216XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags)
217{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800218 XGL_RESULT ret;
Chia-I Wu730e5362014-08-19 12:15:09 +0800219
220 cmd_reset(cmd);
221
Chia-I Wu24565ee2014-08-21 20:24:31 +0800222 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800223 cmd->flags = flags;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800224 cmd->batch.size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800225 }
226
Chia-I Wu24565ee2014-08-21 20:24:31 +0800227 if (!cmd->batch.size) {
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800228 const XGL_UINT size =
229 cmd->dev->gpu->max_batch_buffer_size / sizeof(uint32_t) / 2;
230 XGL_UINT divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800231
232 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
233 divider *= 4;
234
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800235 cmd->batch.size = size / divider;
236 cmd->state.size = size / divider;
237 cmd->kernel.size = 16384 / sizeof(uint32_t) / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800238 }
239
240 ret = cmd_writer_alloc_and_map(cmd, &cmd->batch, cmd->batch.size);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800241 if (ret == XGL_SUCCESS)
242 ret = cmd_writer_alloc_and_map(cmd, &cmd->state, cmd->state.size);
243 if (ret == XGL_SUCCESS)
244 ret = cmd_writer_alloc_and_map(cmd, &cmd->kernel, cmd->kernel.size);
245 if (ret != XGL_SUCCESS) {
246 cmd_reset(cmd);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800247 return ret;
248 }
249
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800250 cmd_batch_begin(cmd);
251
Chia-I Wu24565ee2014-08-21 20:24:31 +0800252 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800253}
254
255XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
256{
257 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wu343b1372014-08-20 16:39:20 +0800258 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800259
Chia-I Wue24c3292014-08-21 14:05:23 +0800260 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800261
Chia-I Wu343b1372014-08-20 16:39:20 +0800262 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800263 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800264 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
265 uint64_t presumed_offset;
266 int err;
267
Chia-I Wue24c3292014-08-21 14:05:23 +0800268 err = intel_bo_add_reloc(reloc->writer->bo,
Chia-I Wu9ee38722014-08-25 12:11:36 +0800269 sizeof(uint32_t) * reloc->pos, reloc->bo, reloc->val,
Chia-I Wu32a22462014-08-26 14:13:46 +0800270 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800271 if (err) {
272 cmd->result = XGL_ERROR_UNKNOWN;
273 break;
274 }
275
276 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wue24c3292014-08-21 14:05:23 +0800277 cmd_writer_patch(cmd, reloc->writer, reloc->pos,
278 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800279 }
280
Chia-I Wu730e5362014-08-19 12:15:09 +0800281 cmd_unmap(cmd);
282
Chia-I Wu04966702014-08-20 15:05:03 +0800283 if (cmd->result != XGL_SUCCESS)
284 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800285
286 if (intel_winsys_can_submit_bo(winsys, &cmd->batch.bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800287 return XGL_SUCCESS;
288 else
289 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
290}
291
Chia-I Wu09142132014-08-11 15:42:55 +0800292XGL_RESULT XGLAPI intelCreateCommandBuffer(
293 XGL_DEVICE device,
294 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
295 XGL_CMD_BUFFER* pCmdBuffer)
296{
Chia-I Wu730e5362014-08-19 12:15:09 +0800297 struct intel_dev *dev = intel_dev(device);
298
299 return intel_cmd_create(dev, pCreateInfo,
300 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800301}
302
303XGL_RESULT XGLAPI intelBeginCommandBuffer(
304 XGL_CMD_BUFFER cmdBuffer,
305 XGL_FLAGS flags)
306{
Chia-I Wu730e5362014-08-19 12:15:09 +0800307 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
308
309 return intel_cmd_begin(cmd, flags);
Chia-I Wu09142132014-08-11 15:42:55 +0800310}
311
312XGL_RESULT XGLAPI intelEndCommandBuffer(
313 XGL_CMD_BUFFER cmdBuffer)
314{
Chia-I Wu730e5362014-08-19 12:15:09 +0800315 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
316
317 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800318}
319
320XGL_RESULT XGLAPI intelResetCommandBuffer(
321 XGL_CMD_BUFFER cmdBuffer)
322{
Chia-I Wu730e5362014-08-19 12:15:09 +0800323 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
324
325 cmd_reset(cmd);
326
327 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800328}
329
Chia-I Wu09142132014-08-11 15:42:55 +0800330XGL_VOID XGLAPI intelCmdCopyMemory(
331 XGL_CMD_BUFFER cmdBuffer,
332 XGL_GPU_MEMORY srcMem,
333 XGL_GPU_MEMORY destMem,
334 XGL_UINT regionCount,
335 const XGL_MEMORY_COPY* pRegions)
336{
337}
338
339XGL_VOID XGLAPI intelCmdCopyImage(
340 XGL_CMD_BUFFER cmdBuffer,
341 XGL_IMAGE srcImage,
342 XGL_IMAGE destImage,
343 XGL_UINT regionCount,
344 const XGL_IMAGE_COPY* pRegions)
345{
346}
347
348XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
349 XGL_CMD_BUFFER cmdBuffer,
350 XGL_GPU_MEMORY srcMem,
351 XGL_IMAGE destImage,
352 XGL_UINT regionCount,
353 const XGL_MEMORY_IMAGE_COPY* pRegions)
354{
355}
356
357XGL_VOID XGLAPI intelCmdCopyImageToMemory(
358 XGL_CMD_BUFFER cmdBuffer,
359 XGL_IMAGE srcImage,
360 XGL_GPU_MEMORY destMem,
361 XGL_UINT regionCount,
362 const XGL_MEMORY_IMAGE_COPY* pRegions)
363{
364}
365
366XGL_VOID XGLAPI intelCmdCloneImageData(
367 XGL_CMD_BUFFER cmdBuffer,
368 XGL_IMAGE srcImage,
369 XGL_IMAGE_STATE srcImageState,
370 XGL_IMAGE destImage,
371 XGL_IMAGE_STATE destImageState)
372{
373}
374
375XGL_VOID XGLAPI intelCmdUpdateMemory(
376 XGL_CMD_BUFFER cmdBuffer,
377 XGL_GPU_MEMORY destMem,
378 XGL_GPU_SIZE destOffset,
379 XGL_GPU_SIZE dataSize,
380 const XGL_UINT32* pData)
381{
382}
383
384XGL_VOID XGLAPI intelCmdFillMemory(
385 XGL_CMD_BUFFER cmdBuffer,
386 XGL_GPU_MEMORY destMem,
387 XGL_GPU_SIZE destOffset,
388 XGL_GPU_SIZE fillSize,
389 XGL_UINT32 data)
390{
391}
392
393XGL_VOID XGLAPI intelCmdClearColorImage(
394 XGL_CMD_BUFFER cmdBuffer,
395 XGL_IMAGE image,
396 const XGL_FLOAT color[4],
397 XGL_UINT rangeCount,
398 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
399{
400}
401
402XGL_VOID XGLAPI intelCmdClearColorImageRaw(
403 XGL_CMD_BUFFER cmdBuffer,
404 XGL_IMAGE image,
405 const XGL_UINT32 color[4],
406 XGL_UINT rangeCount,
407 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
408{
409}
410
411XGL_VOID XGLAPI intelCmdClearDepthStencil(
412 XGL_CMD_BUFFER cmdBuffer,
413 XGL_IMAGE image,
414 XGL_FLOAT depth,
415 XGL_UINT32 stencil,
416 XGL_UINT rangeCount,
417 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
418{
419}
420
421XGL_VOID XGLAPI intelCmdResolveImage(
422 XGL_CMD_BUFFER cmdBuffer,
423 XGL_IMAGE srcImage,
424 XGL_IMAGE destImage,
425 XGL_UINT rectCount,
426 const XGL_IMAGE_RESOLVE* pRects)
427{
428}
429
Chia-I Wu09142132014-08-11 15:42:55 +0800430XGL_VOID XGLAPI intelCmdMemoryAtomic(
431 XGL_CMD_BUFFER cmdBuffer,
432 XGL_GPU_MEMORY destMem,
433 XGL_GPU_SIZE destOffset,
434 XGL_UINT64 srcData,
435 XGL_ATOMIC_OP atomicOp)
436{
437}
438
Chia-I Wu09142132014-08-11 15:42:55 +0800439XGL_VOID XGLAPI intelCmdInitAtomicCounters(
440 XGL_CMD_BUFFER cmdBuffer,
441 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
442 XGL_UINT startCounter,
443 XGL_UINT counterCount,
444 const XGL_UINT32* pData)
445{
446}
447
448XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
449 XGL_CMD_BUFFER cmdBuffer,
450 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
451 XGL_UINT startCounter,
452 XGL_UINT counterCount,
453 XGL_GPU_MEMORY srcMem,
454 XGL_GPU_SIZE srcOffset)
455{
456}
457
458XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
459 XGL_CMD_BUFFER cmdBuffer,
460 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
461 XGL_UINT startCounter,
462 XGL_UINT counterCount,
463 XGL_GPU_MEMORY destMem,
464 XGL_GPU_SIZE destOffset)
465{
466}
467
468XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
469 XGL_CMD_BUFFER cmdBuffer,
470 const XGL_CHAR* pMarker)
471{
472}
473
474XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
475 XGL_CMD_BUFFER cmdBuffer)
476{
477}