blob: ce4db29b701aeea1f8ef7feac9c28afe5e9a4648 [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
Chia-I Wu730e5362014-08-19 12:15:09 +080025#include "genhw/genhw.h"
26#include "kmd/winsys.h"
27#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080028#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080030#include "cmd_priv.h"
Chia-I Wu09142132014-08-11 15:42:55 +080031
Chia-I Wue24c3292014-08-21 14:05:23 +080032static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
33 struct intel_cmd_writer *writer,
34 XGL_UINT size)
Chia-I Wu730e5362014-08-19 12:15:09 +080035{
36 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wue24c3292014-08-21 14:05:23 +080037 const XGL_GPU_SIZE bo_size = sizeof(uint32_t) * size;
Chia-I Wu730e5362014-08-19 12:15:09 +080038 struct intel_bo *bo;
39 void *ptr;
40
41 bo = intel_winsys_alloc_buffer(winsys,
Chia-I Wu32a22462014-08-26 14:13:46 +080042 "batch buffer", bo_size, true);
Chia-I Wu730e5362014-08-19 12:15:09 +080043 if (!bo)
44 return XGL_ERROR_OUT_OF_GPU_MEMORY;
45
46 ptr = intel_bo_map(bo, true);
47 if (!bo) {
48 intel_bo_unreference(bo);
49 return XGL_ERROR_MEMORY_MAP_FAILED;
50 }
51
Chia-I Wue24c3292014-08-21 14:05:23 +080052 writer->bo = bo;
53 writer->ptr_opaque = ptr;
54 writer->size = size;
55 writer->used = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +080056
57 return XGL_SUCCESS;
58}
59
Chia-I Wu5e25c272014-08-21 20:19:12 +080060static void cmd_writer_copy(struct intel_cmd *cmd,
61 struct intel_cmd_writer *writer,
62 const uint32_t *vals, XGL_UINT len)
63{
64 assert(writer->used + len <= writer->size);
65 memcpy((uint32_t *) writer->ptr_opaque + writer->used,
66 vals, sizeof(uint32_t) * len);
67 writer->used += len;
68}
69
70static void cmd_writer_patch(struct intel_cmd *cmd,
71 struct intel_cmd_writer *writer,
72 XGL_UINT pos, uint32_t val)
73{
74 assert(pos < writer->used);
75 ((uint32_t *) writer->ptr_opaque)[pos] = val;
76}
77
Chia-I Wue24c3292014-08-21 14:05:23 +080078void cmd_writer_grow(struct intel_cmd *cmd,
79 struct intel_cmd_writer *writer)
Chia-I Wu730e5362014-08-19 12:15:09 +080080{
Chia-I Wue24c3292014-08-21 14:05:23 +080081 const XGL_UINT size = writer->size << 1;
82 const XGL_UINT old_used = writer->used;
83 struct intel_bo *old_bo = writer->bo;
84 void *old_ptr = writer->ptr_opaque;
85
86 if (size >= writer->size &&
87 cmd_writer_alloc_and_map(cmd, writer, size) == XGL_SUCCESS) {
88 cmd_writer_copy(cmd, writer, (const uint32_t *) old_ptr, old_used);
89
90 intel_bo_unmap(old_bo);
91 intel_bo_unreference(old_bo);
92 } else {
93 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
94 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
95 "failed to grow command buffer of size %u", writer->size);
96
97 /* wrap it and fail silently */
98 writer->used = 0;
99 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
100 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800101}
102
Chia-I Wue24c3292014-08-21 14:05:23 +0800103static void cmd_writer_unmap(struct intel_cmd *cmd,
104 struct intel_cmd_writer *writer)
Chia-I Wu730e5362014-08-19 12:15:09 +0800105{
Chia-I Wue24c3292014-08-21 14:05:23 +0800106 intel_bo_unmap(writer->bo);
107 writer->ptr_opaque = NULL;
108}
109
110static void cmd_writer_free(struct intel_cmd *cmd,
111 struct intel_cmd_writer *writer)
112{
113 intel_bo_unreference(writer->bo);
114 writer->bo = NULL;
115}
116
117static void cmd_writer_reset(struct intel_cmd *cmd,
118 struct intel_cmd_writer *writer)
119{
120 /* do not reset writer->size as we want to know how big it has grown to */
121 writer->used = 0;
122
123 if (writer->ptr_opaque)
124 cmd_writer_unmap(cmd, writer);
125 if (writer->bo)
126 cmd_writer_free(cmd, writer);
127}
128
129static void cmd_unmap(struct intel_cmd *cmd)
130{
131 cmd_writer_unmap(cmd, &cmd->batch);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800132 cmd_writer_unmap(cmd, &cmd->state);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800133 cmd_writer_unmap(cmd, &cmd->kernel);
Chia-I Wu730e5362014-08-19 12:15:09 +0800134}
135
136static void cmd_reset(struct intel_cmd *cmd)
137{
Chia-I Wue24c3292014-08-21 14:05:23 +0800138 cmd_writer_reset(cmd, &cmd->batch);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800139 cmd_writer_reset(cmd, &cmd->state);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800140 cmd_writer_reset(cmd, &cmd->kernel);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800141
142 memset(&cmd->bind, 0, sizeof(cmd->bind));
143
Chia-I Wu343b1372014-08-20 16:39:20 +0800144 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800145 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800146}
147
148static void cmd_destroy(struct intel_obj *obj)
149{
150 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
151
152 intel_cmd_destroy(cmd);
153}
154
155XGL_RESULT intel_cmd_create(struct intel_dev *dev,
156 const XGL_CMD_BUFFER_CREATE_INFO *info,
157 struct intel_cmd **cmd_ret)
158{
Chia-I Wu63883292014-08-25 13:50:26 +0800159 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800160 struct intel_cmd *cmd;
161
Chia-I Wu63883292014-08-25 13:50:26 +0800162 switch (info->queueType) {
163 case XGL_QUEUE_TYPE_GRAPHICS:
164 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
165 break;
166 case XGL_QUEUE_TYPE_COMPUTE:
167 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
168 break;
169 case XGL_QUEUE_TYPE_DMA:
170 pipeline_select = -1;
171 break;
172 default:
173 return XGL_ERROR_INVALID_VALUE;
174 break;
175 }
176
Chia-I Wu730e5362014-08-19 12:15:09 +0800177 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
178 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
179 if (!cmd)
180 return XGL_ERROR_OUT_OF_MEMORY;
181
182 cmd->obj.destroy = cmd_destroy;
183
184 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800185 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800186 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800187
Chia-I Wue0cdd832014-08-25 12:38:56 +0800188 /*
189 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
190 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
191 * and end offsets, for each referenced memories.
192 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800193 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
194 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
195 4096, XGL_SYSTEM_ALLOC_INTERNAL);
196 if (!cmd->relocs) {
197 intel_cmd_destroy(cmd);
198 return XGL_ERROR_OUT_OF_MEMORY;
199 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800200
201 *cmd_ret = cmd;
202
203 return XGL_SUCCESS;
204}
205
206void intel_cmd_destroy(struct intel_cmd *cmd)
207{
208 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800209
210 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800211 intel_base_destroy(&cmd->obj.base);
212}
213
214XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags)
215{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800216 XGL_RESULT ret;
Chia-I Wu730e5362014-08-19 12:15:09 +0800217
218 cmd_reset(cmd);
219
Chia-I Wu24565ee2014-08-21 20:24:31 +0800220 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800221 cmd->flags = flags;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800222 cmd->batch.size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800223 }
224
Chia-I Wu24565ee2014-08-21 20:24:31 +0800225 if (!cmd->batch.size) {
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800226 const XGL_UINT size =
227 cmd->dev->gpu->max_batch_buffer_size / sizeof(uint32_t) / 2;
228 XGL_UINT divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800229
230 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
231 divider *= 4;
232
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800233 cmd->batch.size = size / divider;
234 cmd->state.size = size / divider;
235 cmd->kernel.size = 16384 / sizeof(uint32_t) / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800236 }
237
238 ret = cmd_writer_alloc_and_map(cmd, &cmd->batch, cmd->batch.size);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800239 if (ret == XGL_SUCCESS)
240 ret = cmd_writer_alloc_and_map(cmd, &cmd->state, cmd->state.size);
241 if (ret == XGL_SUCCESS)
242 ret = cmd_writer_alloc_and_map(cmd, &cmd->kernel, cmd->kernel.size);
243 if (ret != XGL_SUCCESS) {
244 cmd_reset(cmd);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800245 return ret;
246 }
247
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800248 cmd_batch_begin(cmd);
249
Chia-I Wu24565ee2014-08-21 20:24:31 +0800250 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800251}
252
253XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
254{
255 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wu343b1372014-08-20 16:39:20 +0800256 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800257
Chia-I Wue24c3292014-08-21 14:05:23 +0800258 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800259
Chia-I Wu343b1372014-08-20 16:39:20 +0800260 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800261 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800262 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
263 uint64_t presumed_offset;
264 int err;
265
Chia-I Wue24c3292014-08-21 14:05:23 +0800266 err = intel_bo_add_reloc(reloc->writer->bo,
Chia-I Wu9ee38722014-08-25 12:11:36 +0800267 sizeof(uint32_t) * reloc->pos, reloc->bo, reloc->val,
Chia-I Wu32a22462014-08-26 14:13:46 +0800268 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800269 if (err) {
270 cmd->result = XGL_ERROR_UNKNOWN;
271 break;
272 }
273
274 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wue24c3292014-08-21 14:05:23 +0800275 cmd_writer_patch(cmd, reloc->writer, reloc->pos,
276 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800277 }
278
Chia-I Wu730e5362014-08-19 12:15:09 +0800279 cmd_unmap(cmd);
280
Chia-I Wu04966702014-08-20 15:05:03 +0800281 if (cmd->result != XGL_SUCCESS)
282 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800283
284 if (intel_winsys_can_submit_bo(winsys, &cmd->batch.bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800285 return XGL_SUCCESS;
286 else
287 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
288}
289
Chia-I Wu09142132014-08-11 15:42:55 +0800290XGL_RESULT XGLAPI intelCreateCommandBuffer(
291 XGL_DEVICE device,
292 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
293 XGL_CMD_BUFFER* pCmdBuffer)
294{
Chia-I Wu730e5362014-08-19 12:15:09 +0800295 struct intel_dev *dev = intel_dev(device);
296
297 return intel_cmd_create(dev, pCreateInfo,
298 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800299}
300
301XGL_RESULT XGLAPI intelBeginCommandBuffer(
302 XGL_CMD_BUFFER cmdBuffer,
303 XGL_FLAGS flags)
304{
Chia-I Wu730e5362014-08-19 12:15:09 +0800305 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
306
307 return intel_cmd_begin(cmd, flags);
Chia-I Wu09142132014-08-11 15:42:55 +0800308}
309
310XGL_RESULT XGLAPI intelEndCommandBuffer(
311 XGL_CMD_BUFFER cmdBuffer)
312{
Chia-I Wu730e5362014-08-19 12:15:09 +0800313 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
314
315 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800316}
317
318XGL_RESULT XGLAPI intelResetCommandBuffer(
319 XGL_CMD_BUFFER cmdBuffer)
320{
Chia-I Wu730e5362014-08-19 12:15:09 +0800321 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
322
323 cmd_reset(cmd);
324
325 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800326}
327
Chia-I Wu09142132014-08-11 15:42:55 +0800328XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
329 XGL_CMD_BUFFER cmdBuffer,
330 XGL_UINT transitionCount,
331 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions)
332{
333}
334
335XGL_VOID XGLAPI intelCmdPrepareImages(
336 XGL_CMD_BUFFER cmdBuffer,
337 XGL_UINT transitionCount,
338 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions)
339{
340}
341
Chia-I Wu09142132014-08-11 15:42:55 +0800342XGL_VOID XGLAPI intelCmdCopyMemory(
343 XGL_CMD_BUFFER cmdBuffer,
344 XGL_GPU_MEMORY srcMem,
345 XGL_GPU_MEMORY destMem,
346 XGL_UINT regionCount,
347 const XGL_MEMORY_COPY* pRegions)
348{
349}
350
351XGL_VOID XGLAPI intelCmdCopyImage(
352 XGL_CMD_BUFFER cmdBuffer,
353 XGL_IMAGE srcImage,
354 XGL_IMAGE destImage,
355 XGL_UINT regionCount,
356 const XGL_IMAGE_COPY* pRegions)
357{
358}
359
360XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
361 XGL_CMD_BUFFER cmdBuffer,
362 XGL_GPU_MEMORY srcMem,
363 XGL_IMAGE destImage,
364 XGL_UINT regionCount,
365 const XGL_MEMORY_IMAGE_COPY* pRegions)
366{
367}
368
369XGL_VOID XGLAPI intelCmdCopyImageToMemory(
370 XGL_CMD_BUFFER cmdBuffer,
371 XGL_IMAGE srcImage,
372 XGL_GPU_MEMORY destMem,
373 XGL_UINT regionCount,
374 const XGL_MEMORY_IMAGE_COPY* pRegions)
375{
376}
377
378XGL_VOID XGLAPI intelCmdCloneImageData(
379 XGL_CMD_BUFFER cmdBuffer,
380 XGL_IMAGE srcImage,
381 XGL_IMAGE_STATE srcImageState,
382 XGL_IMAGE destImage,
383 XGL_IMAGE_STATE destImageState)
384{
385}
386
387XGL_VOID XGLAPI intelCmdUpdateMemory(
388 XGL_CMD_BUFFER cmdBuffer,
389 XGL_GPU_MEMORY destMem,
390 XGL_GPU_SIZE destOffset,
391 XGL_GPU_SIZE dataSize,
392 const XGL_UINT32* pData)
393{
394}
395
396XGL_VOID XGLAPI intelCmdFillMemory(
397 XGL_CMD_BUFFER cmdBuffer,
398 XGL_GPU_MEMORY destMem,
399 XGL_GPU_SIZE destOffset,
400 XGL_GPU_SIZE fillSize,
401 XGL_UINT32 data)
402{
403}
404
405XGL_VOID XGLAPI intelCmdClearColorImage(
406 XGL_CMD_BUFFER cmdBuffer,
407 XGL_IMAGE image,
408 const XGL_FLOAT color[4],
409 XGL_UINT rangeCount,
410 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
411{
412}
413
414XGL_VOID XGLAPI intelCmdClearColorImageRaw(
415 XGL_CMD_BUFFER cmdBuffer,
416 XGL_IMAGE image,
417 const XGL_UINT32 color[4],
418 XGL_UINT rangeCount,
419 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
420{
421}
422
423XGL_VOID XGLAPI intelCmdClearDepthStencil(
424 XGL_CMD_BUFFER cmdBuffer,
425 XGL_IMAGE image,
426 XGL_FLOAT depth,
427 XGL_UINT32 stencil,
428 XGL_UINT rangeCount,
429 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
430{
431}
432
433XGL_VOID XGLAPI intelCmdResolveImage(
434 XGL_CMD_BUFFER cmdBuffer,
435 XGL_IMAGE srcImage,
436 XGL_IMAGE destImage,
437 XGL_UINT rectCount,
438 const XGL_IMAGE_RESOLVE* pRects)
439{
440}
441
442XGL_VOID XGLAPI intelCmdSetEvent(
443 XGL_CMD_BUFFER cmdBuffer,
444 XGL_EVENT event)
445{
446}
447
448XGL_VOID XGLAPI intelCmdResetEvent(
449 XGL_CMD_BUFFER cmdBuffer,
450 XGL_EVENT event)
451{
452}
453
454XGL_VOID XGLAPI intelCmdMemoryAtomic(
455 XGL_CMD_BUFFER cmdBuffer,
456 XGL_GPU_MEMORY destMem,
457 XGL_GPU_SIZE destOffset,
458 XGL_UINT64 srcData,
459 XGL_ATOMIC_OP atomicOp)
460{
461}
462
463XGL_VOID XGLAPI intelCmdBeginQuery(
464 XGL_CMD_BUFFER cmdBuffer,
465 XGL_QUERY_POOL queryPool,
466 XGL_UINT slot,
467 XGL_FLAGS flags)
468{
469}
470
471XGL_VOID XGLAPI intelCmdEndQuery(
472 XGL_CMD_BUFFER cmdBuffer,
473 XGL_QUERY_POOL queryPool,
474 XGL_UINT slot)
475{
476}
477
478XGL_VOID XGLAPI intelCmdResetQueryPool(
479 XGL_CMD_BUFFER cmdBuffer,
480 XGL_QUERY_POOL queryPool,
481 XGL_UINT startQuery,
482 XGL_UINT queryCount)
483{
484}
485
486XGL_VOID XGLAPI intelCmdWriteTimestamp(
487 XGL_CMD_BUFFER cmdBuffer,
488 XGL_TIMESTAMP_TYPE timestampType,
489 XGL_GPU_MEMORY destMem,
490 XGL_GPU_SIZE destOffset)
491{
492}
493
494XGL_VOID XGLAPI intelCmdInitAtomicCounters(
495 XGL_CMD_BUFFER cmdBuffer,
496 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
497 XGL_UINT startCounter,
498 XGL_UINT counterCount,
499 const XGL_UINT32* pData)
500{
501}
502
503XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
504 XGL_CMD_BUFFER cmdBuffer,
505 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
506 XGL_UINT startCounter,
507 XGL_UINT counterCount,
508 XGL_GPU_MEMORY srcMem,
509 XGL_GPU_SIZE srcOffset)
510{
511}
512
513XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
514 XGL_CMD_BUFFER cmdBuffer,
515 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
516 XGL_UINT startCounter,
517 XGL_UINT counterCount,
518 XGL_GPU_MEMORY destMem,
519 XGL_GPU_SIZE destOffset)
520{
521}
522
523XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
524 XGL_CMD_BUFFER cmdBuffer,
525 const XGL_CHAR* pMarker)
526{
527}
528
529XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
530 XGL_CMD_BUFFER cmdBuffer)
531{
532}