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Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef CMD_H
26#define CMD_H
27
28#include "intel.h"
29#include "obj.h"
Chia-I Wub2755562014-08-20 13:38:52 +080030#include "view.h"
31
32struct intel_pipeline;
33struct intel_pipeline_delta;
34struct intel_viewport_state;
35struct intel_raster_state;
36struct intel_msaa_state;
37struct intel_blend_state;
38struct intel_ds_state;
39struct intel_dset;
40
Chia-I Wu958d1b72014-08-21 11:28:11 +080041struct intel_cmd_reloc;
42
Chia-I Wub2755562014-08-20 13:38:52 +080043/*
44 * States bounded to the command buffer. We want to write states directly to
45 * the command buffer when possible, and reduce this struct.
46 */
47struct intel_cmd_bind {
48 struct {
49 const struct intel_pipeline *graphics;
50 const struct intel_pipeline *compute;
51 const struct intel_pipeline_delta *graphics_delta;
52 const struct intel_pipeline_delta *compute_delta;
53 } pipeline;
54
55 struct {
56 const struct intel_viewport_state *viewport;
57 const struct intel_raster_state *raster;
58 const struct intel_msaa_state *msaa;
59 const struct intel_blend_state *blend;
60 const struct intel_ds_state *ds;
61 } state;
62
63 struct {
64 const struct intel_dset *graphics;
65 XGL_UINT graphics_offset;
66 const struct intel_dset *compute;
67 XGL_UINT compute_offset;
68 } dset;
69
70 struct {
71 struct intel_mem_view graphics;
72 struct intel_mem_view compute;
Chia-I Wu9f1722c2014-08-25 10:17:58 +080073 } dyn_view;
Chia-I Wub2755562014-08-20 13:38:52 +080074
75 struct {
76 const struct intel_mem *mem;
77 XGL_GPU_SIZE offset;
78 XGL_INDEX_TYPE type;
79 } index;
80
81 struct {
82 const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS];
83 XGL_UINT rt_count;
84
85 const struct intel_ds_view *ds;
86 } att;
Chia-I Wu48c283d2014-08-25 23:13:46 +080087
88 uint32_t wa_flags;
Chia-I Wub2755562014-08-20 13:38:52 +080089};
Chia-I Wu09142132014-08-11 15:42:55 +080090
Chia-I Wue24c3292014-08-21 14:05:23 +080091struct intel_cmd_writer {
92 struct intel_bo *bo;
93 void *ptr_opaque;
94
95 /* in DWords */
96 XGL_UINT size;
97 XGL_UINT used;
98};
99
Chia-I Wu730e5362014-08-19 12:15:09 +0800100struct intel_cmd {
101 struct intel_obj obj;
102
103 struct intel_dev *dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800104 struct intel_bo *scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800105 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800106
Chia-I Wu343b1372014-08-20 16:39:20 +0800107 struct intel_cmd_reloc *relocs;
108 XGL_UINT reloc_count;
109
Chia-I Wu730e5362014-08-19 12:15:09 +0800110 XGL_FLAGS flags;
111
Chia-I Wue24c3292014-08-21 14:05:23 +0800112 struct intel_cmd_writer batch;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800113 struct intel_cmd_writer state;
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800114 struct intel_cmd_writer kernel;
Chia-I Wu730e5362014-08-19 12:15:09 +0800115
Chia-I Wu343b1372014-08-20 16:39:20 +0800116 XGL_UINT reloc_used;
Chia-I Wu04966702014-08-20 15:05:03 +0800117 XGL_RESULT result;
Chia-I Wub2755562014-08-20 13:38:52 +0800118
119 struct intel_cmd_bind bind;
Chia-I Wu730e5362014-08-19 12:15:09 +0800120};
121
122static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd)
123{
124 return (struct intel_cmd *) cmd;
125}
126
127static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj)
128{
129 return (struct intel_cmd *) obj;
130}
131
132XGL_RESULT intel_cmd_create(struct intel_dev *dev,
133 const XGL_CMD_BUFFER_CREATE_INFO *info,
134 struct intel_cmd **cmd_ret);
135void intel_cmd_destroy(struct intel_cmd *cmd);
136
137XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags);
138XGL_RESULT intel_cmd_end(struct intel_cmd *cmd);
139
Chia-I Wue24c3292014-08-21 14:05:23 +0800140static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd,
141 XGL_GPU_SIZE *used)
142{
143 const struct intel_cmd_writer *writer = &cmd->batch;
144
145 if (used)
146 *used = sizeof(uint32_t) * writer->used;
147
148 return writer->bo;
149}
150
Chia-I Wu09142132014-08-11 15:42:55 +0800151XGL_RESULT XGLAPI intelCreateCommandBuffer(
152 XGL_DEVICE device,
153 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
154 XGL_CMD_BUFFER* pCmdBuffer);
155
156XGL_RESULT XGLAPI intelBeginCommandBuffer(
157 XGL_CMD_BUFFER cmdBuffer,
158 XGL_FLAGS flags);
159
160XGL_RESULT XGLAPI intelEndCommandBuffer(
161 XGL_CMD_BUFFER cmdBuffer);
162
163XGL_RESULT XGLAPI intelResetCommandBuffer(
164 XGL_CMD_BUFFER cmdBuffer);
165
166XGL_VOID XGLAPI intelCmdBindPipeline(
167 XGL_CMD_BUFFER cmdBuffer,
168 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
169 XGL_PIPELINE pipeline);
170
171XGL_VOID XGLAPI intelCmdBindPipelineDelta(
172 XGL_CMD_BUFFER cmdBuffer,
173 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
174 XGL_PIPELINE_DELTA delta);
175
176XGL_VOID XGLAPI intelCmdBindStateObject(
177 XGL_CMD_BUFFER cmdBuffer,
178 XGL_STATE_BIND_POINT stateBindPoint,
179 XGL_STATE_OBJECT state);
180
181XGL_VOID XGLAPI intelCmdBindDescriptorSet(
182 XGL_CMD_BUFFER cmdBuffer,
183 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
184 XGL_UINT index,
185 XGL_DESCRIPTOR_SET descriptorSet,
186 XGL_UINT slotOffset);
187
188XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
189 XGL_CMD_BUFFER cmdBuffer,
190 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
191 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
192
193XGL_VOID XGLAPI intelCmdBindIndexData(
194 XGL_CMD_BUFFER cmdBuffer,
195 XGL_GPU_MEMORY mem,
196 XGL_GPU_SIZE offset,
197 XGL_INDEX_TYPE indexType);
198
199XGL_VOID XGLAPI intelCmdBindAttachments(
200 XGL_CMD_BUFFER cmdBuffer,
201 XGL_UINT colorAttachmentCount,
202 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
203 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
204
205XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
206 XGL_CMD_BUFFER cmdBuffer,
207 XGL_UINT transitionCount,
208 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
209
210XGL_VOID XGLAPI intelCmdPrepareImages(
211 XGL_CMD_BUFFER cmdBuffer,
212 XGL_UINT transitionCount,
213 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
214
215XGL_VOID XGLAPI intelCmdDraw(
216 XGL_CMD_BUFFER cmdBuffer,
217 XGL_UINT firstVertex,
218 XGL_UINT vertexCount,
219 XGL_UINT firstInstance,
220 XGL_UINT instanceCount);
221
222XGL_VOID XGLAPI intelCmdDrawIndexed(
223 XGL_CMD_BUFFER cmdBuffer,
224 XGL_UINT firstIndex,
225 XGL_UINT indexCount,
226 XGL_INT vertexOffset,
227 XGL_UINT firstInstance,
228 XGL_UINT instanceCount);
229
230XGL_VOID XGLAPI intelCmdDrawIndirect(
231 XGL_CMD_BUFFER cmdBuffer,
232 XGL_GPU_MEMORY mem,
233 XGL_GPU_SIZE offset,
234 XGL_UINT32 count,
235 XGL_UINT32 stride);
236
237XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
238 XGL_CMD_BUFFER cmdBuffer,
239 XGL_GPU_MEMORY mem,
240 XGL_GPU_SIZE offset,
241 XGL_UINT32 count,
242 XGL_UINT32 stride);
243
244XGL_VOID XGLAPI intelCmdDispatch(
245 XGL_CMD_BUFFER cmdBuffer,
246 XGL_UINT x,
247 XGL_UINT y,
248 XGL_UINT z);
249
250XGL_VOID XGLAPI intelCmdDispatchIndirect(
251 XGL_CMD_BUFFER cmdBuffer,
252 XGL_GPU_MEMORY mem,
253 XGL_GPU_SIZE offset);
254
255XGL_VOID XGLAPI intelCmdCopyMemory(
256 XGL_CMD_BUFFER cmdBuffer,
257 XGL_GPU_MEMORY srcMem,
258 XGL_GPU_MEMORY destMem,
259 XGL_UINT regionCount,
260 const XGL_MEMORY_COPY* pRegions);
261
262XGL_VOID XGLAPI intelCmdCopyImage(
263 XGL_CMD_BUFFER cmdBuffer,
264 XGL_IMAGE srcImage,
265 XGL_IMAGE destImage,
266 XGL_UINT regionCount,
267 const XGL_IMAGE_COPY* pRegions);
268
269XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
270 XGL_CMD_BUFFER cmdBuffer,
271 XGL_GPU_MEMORY srcMem,
272 XGL_IMAGE destImage,
273 XGL_UINT regionCount,
274 const XGL_MEMORY_IMAGE_COPY* pRegions);
275
276XGL_VOID XGLAPI intelCmdCopyImageToMemory(
277 XGL_CMD_BUFFER cmdBuffer,
278 XGL_IMAGE srcImage,
279 XGL_GPU_MEMORY destMem,
280 XGL_UINT regionCount,
281 const XGL_MEMORY_IMAGE_COPY* pRegions);
282
283XGL_VOID XGLAPI intelCmdCloneImageData(
284 XGL_CMD_BUFFER cmdBuffer,
285 XGL_IMAGE srcImage,
286 XGL_IMAGE_STATE srcImageState,
287 XGL_IMAGE destImage,
288 XGL_IMAGE_STATE destImageState);
289
290XGL_VOID XGLAPI intelCmdUpdateMemory(
291 XGL_CMD_BUFFER cmdBuffer,
292 XGL_GPU_MEMORY destMem,
293 XGL_GPU_SIZE destOffset,
294 XGL_GPU_SIZE dataSize,
295 const XGL_UINT32* pData);
296
297XGL_VOID XGLAPI intelCmdFillMemory(
298 XGL_CMD_BUFFER cmdBuffer,
299 XGL_GPU_MEMORY destMem,
300 XGL_GPU_SIZE destOffset,
301 XGL_GPU_SIZE fillSize,
302 XGL_UINT32 data);
303
304XGL_VOID XGLAPI intelCmdClearColorImage(
305 XGL_CMD_BUFFER cmdBuffer,
306 XGL_IMAGE image,
307 const XGL_FLOAT color[4],
308 XGL_UINT rangeCount,
309 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
310
311XGL_VOID XGLAPI intelCmdClearColorImageRaw(
312 XGL_CMD_BUFFER cmdBuffer,
313 XGL_IMAGE image,
314 const XGL_UINT32 color[4],
315 XGL_UINT rangeCount,
316 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
317
318XGL_VOID XGLAPI intelCmdClearDepthStencil(
319 XGL_CMD_BUFFER cmdBuffer,
320 XGL_IMAGE image,
321 XGL_FLOAT depth,
322 XGL_UINT32 stencil,
323 XGL_UINT rangeCount,
324 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
325
326XGL_VOID XGLAPI intelCmdResolveImage(
327 XGL_CMD_BUFFER cmdBuffer,
328 XGL_IMAGE srcImage,
329 XGL_IMAGE destImage,
330 XGL_UINT rectCount,
331 const XGL_IMAGE_RESOLVE* pRects);
332
333XGL_VOID XGLAPI intelCmdSetEvent(
334 XGL_CMD_BUFFER cmdBuffer,
335 XGL_EVENT event);
336
337XGL_VOID XGLAPI intelCmdResetEvent(
338 XGL_CMD_BUFFER cmdBuffer,
339 XGL_EVENT event);
340
341XGL_VOID XGLAPI intelCmdMemoryAtomic(
342 XGL_CMD_BUFFER cmdBuffer,
343 XGL_GPU_MEMORY destMem,
344 XGL_GPU_SIZE destOffset,
345 XGL_UINT64 srcData,
346 XGL_ATOMIC_OP atomicOp);
347
348XGL_VOID XGLAPI intelCmdBeginQuery(
349 XGL_CMD_BUFFER cmdBuffer,
350 XGL_QUERY_POOL queryPool,
351 XGL_UINT slot,
352 XGL_FLAGS flags);
353
354XGL_VOID XGLAPI intelCmdEndQuery(
355 XGL_CMD_BUFFER cmdBuffer,
356 XGL_QUERY_POOL queryPool,
357 XGL_UINT slot);
358
359XGL_VOID XGLAPI intelCmdResetQueryPool(
360 XGL_CMD_BUFFER cmdBuffer,
361 XGL_QUERY_POOL queryPool,
362 XGL_UINT startQuery,
363 XGL_UINT queryCount);
364
365XGL_VOID XGLAPI intelCmdWriteTimestamp(
366 XGL_CMD_BUFFER cmdBuffer,
367 XGL_TIMESTAMP_TYPE timestampType,
368 XGL_GPU_MEMORY destMem,
369 XGL_GPU_SIZE destOffset);
370
371XGL_VOID XGLAPI intelCmdInitAtomicCounters(
372 XGL_CMD_BUFFER cmdBuffer,
373 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
374 XGL_UINT startCounter,
375 XGL_UINT counterCount,
376 const XGL_UINT32* pData);
377
378XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
379 XGL_CMD_BUFFER cmdBuffer,
380 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
381 XGL_UINT startCounter,
382 XGL_UINT counterCount,
383 XGL_GPU_MEMORY srcMem,
384 XGL_GPU_SIZE srcOffset);
385
386XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
387 XGL_CMD_BUFFER cmdBuffer,
388 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
389 XGL_UINT startCounter,
390 XGL_UINT counterCount,
391 XGL_GPU_MEMORY destMem,
392 XGL_GPU_SIZE destOffset);
393
394XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
395 XGL_CMD_BUFFER cmdBuffer,
396 const XGL_CHAR* pMarker);
397
398XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
399 XGL_CMD_BUFFER cmdBuffer);
400
401#endif /* CMD_H */