blob: d58cf3308f9db1f17b20d5e7558cf1ed75187f37 [file] [log] [blame]
Chia-I Wu82f50aa2014-08-05 10:43:03 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wu82f50aa2014-08-05 10:43:03 +080026 */
27
Chia-I Wude2bb862014-08-19 14:32:47 +080028#include "dispatch.h"
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -060029#include "dev.h"
Chia-I Wu9e61c0d2014-09-15 15:12:06 +080030#include "gpu.h"
31#include "mem.h"
Chia-I Wu82f50aa2014-08-05 10:43:03 +080032#include "obj.h"
33
34/**
35 * Return true if an (not so) arbitrary pointer casted to intel_base points to
36 * a valid intel_base. This assumes at least the first sizeof(void*) bytes of
37 * the address are accessible, and they does not happen to be our magic
38 * values.
39 */
40bool intel_base_is_valid(const struct intel_base *base)
41{
Chia-I Wu6a42c2a2014-08-19 14:36:47 +080042 if (base->dispatch != intel_dispatch_get(true) &&
43 base->dispatch != intel_dispatch_get(false))
Chia-I Wu82f50aa2014-08-05 10:43:03 +080044 return false;
45
46 return !intel_gpu_is_valid((const struct intel_gpu *) base);
47}
48
Chia-I Wu26f0bd02014-08-07 10:38:40 +080049XGL_RESULT intel_base_get_info(struct intel_base *base, int type,
50 XGL_SIZE *size, XGL_VOID *data)
51{
52 XGL_RESULT ret = XGL_SUCCESS;
53 XGL_SIZE s;
54
55 switch (type) {
56 case XGL_INFO_TYPE_MEMORY_REQUIREMENTS:
57 s = sizeof(XGL_MEMORY_REQUIREMENTS);
Chia-I Wu26f0bd02014-08-07 10:38:40 +080058 *size = s;
Jon Ashburn408daec2014-12-05 09:23:52 -070059 if (data == NULL)
60 return ret;
61 memset(data, 0, s);
62
Chia-I Wu26f0bd02014-08-07 10:38:40 +080063 break;
64 default:
65 ret = XGL_ERROR_INVALID_VALUE;
66 break;
67 }
68
69 return ret;
70}
71
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080072static bool base_dbg_copy_create_info(struct intel_base_dbg *dbg,
73 const void *create_info)
74{
75 const union {
76 const void *ptr;
77 const struct {
78 XGL_STRUCTURE_TYPE struct_type;
79 XGL_VOID *next;
80 } *header;
81 } info = { .ptr = create_info };
82 XGL_SIZE shallow_copy = 0;
83
84 if (!create_info)
85 return true;
86
Chia-I Wub1076d72014-08-18 16:10:20 +080087 switch (dbg->type) {
88 case XGL_DBG_OBJECT_DEVICE:
89 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DEVICE_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080090 break;
Chia-I Wub1076d72014-08-18 16:10:20 +080091 case XGL_DBG_OBJECT_GPU_MEMORY:
92 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_MEMORY_ALLOC_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080093 shallow_copy = sizeof(XGL_MEMORY_ALLOC_INFO);
94 break;
Chia-I Wub1076d72014-08-18 16:10:20 +080095 case XGL_DBG_OBJECT_EVENT:
96 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_EVENT_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080097 shallow_copy = sizeof(XGL_EVENT_CREATE_INFO);
98 break;
Chia-I Wub1076d72014-08-18 16:10:20 +080099 case XGL_DBG_OBJECT_FENCE:
100 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_FENCE_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800101 shallow_copy = sizeof(XGL_FENCE_CREATE_INFO);
102 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800103 case XGL_DBG_OBJECT_QUERY_POOL:
104 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO);
Courtney Goeltzenleuchter850d12c2014-08-07 18:13:10 -0600105 shallow_copy = sizeof(XGL_QUERY_POOL_CREATE_INFO);
106 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800107 case XGL_DBG_OBJECT_IMAGE:
108 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
Chia-I Wufeb441f2014-08-08 21:27:38 +0800109 shallow_copy = sizeof(XGL_IMAGE_CREATE_INFO);
110 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800111 case XGL_DBG_OBJECT_IMAGE_VIEW:
112 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800113 shallow_copy = sizeof(XGL_IMAGE_VIEW_CREATE_INFO);
114 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800115 case XGL_DBG_OBJECT_COLOR_TARGET_VIEW:
116 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_COLOR_ATTACHMENT_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800117 shallow_copy = sizeof(XGL_COLOR_ATTACHMENT_VIEW_CREATE_INFO);
118 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800119 case XGL_DBG_OBJECT_DEPTH_STENCIL_VIEW:
120 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DEPTH_STENCIL_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800121 shallow_copy = sizeof(XGL_DEPTH_STENCIL_VIEW_CREATE_INFO);
122 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800123 case XGL_DBG_OBJECT_SAMPLER:
124 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
Chia-I Wu28b89962014-08-18 14:40:49 +0800125 shallow_copy = sizeof(XGL_SAMPLER_CREATE_INFO);
126 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800127 case XGL_DBG_OBJECT_DESCRIPTOR_SET:
128 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DESCRIPTOR_SET_CREATE_INFO);
Chia-I Wub8d04c82014-08-18 15:51:10 +0800129 shallow_copy = sizeof(XGL_DESCRIPTOR_SET_CREATE_INFO);
130 break;
Chia-I Wua5714e82014-08-11 15:33:42 +0800131 case XGL_DBG_OBJECT_VIEWPORT_STATE:
132 /* no struct header! */
133 shallow_copy = sizeof(XGL_VIEWPORT_STATE_CREATE_INFO);
134 break;
135 case XGL_DBG_OBJECT_RASTER_STATE:
136 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_RASTER_STATE_CREATE_INFO);
137 shallow_copy = sizeof(XGL_RASTER_STATE_CREATE_INFO);
138 break;
139 case XGL_DBG_OBJECT_MSAA_STATE:
140 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_MSAA_STATE_CREATE_INFO);
141 shallow_copy = sizeof(XGL_MSAA_STATE_CREATE_INFO);
142 break;
143 case XGL_DBG_OBJECT_COLOR_BLEND_STATE:
144 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_COLOR_BLEND_STATE_CREATE_INFO);
145 shallow_copy = sizeof(XGL_COLOR_BLEND_STATE_CREATE_INFO);
146 break;
147 case XGL_DBG_OBJECT_DEPTH_STENCIL_STATE:
148 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DEPTH_STENCIL_STATE_CREATE_INFO);
149 shallow_copy = sizeof(XGL_DEPTH_STENCIL_STATE_CREATE_INFO);
150 break;
Chia-I Wu730e5362014-08-19 12:15:09 +0800151 case XGL_DBG_OBJECT_CMD_BUFFER:
152 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_CMD_BUFFER_CREATE_INFO);
153 shallow_copy = sizeof(XGL_CMD_BUFFER_CREATE_INFO);
154 break;
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600155 case XGL_DBG_OBJECT_GRAPHICS_PIPELINE:
156 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
157 break;
Courtney Goeltzenleuchter52ec3362014-08-19 11:52:02 -0600158 case XGL_DBG_OBJECT_SHADER:
Courtney Goeltzenleuchteref5b1162014-10-10 16:29:46 -0600159 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_SHADER_CREATE_INFO);
Courtney Goeltzenleuchter52ec3362014-08-19 11:52:02 -0600160 shallow_copy = sizeof(XGL_SHADER_CREATE_INFO);
161 break;
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800162 default:
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600163 // log debug message regarding invalid struct_type?
164 intel_dev_log(dbg->dev, XGL_DBG_MSG_ERROR,
165 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
166 "Invalid Create Info type: 0x%x", info.header->struct_type);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800167 return false;
168 break;
169 }
170
171 if (shallow_copy) {
Chia-I Wu73523682014-10-23 01:38:26 +0800172 /* XGL_VIEWPORT_STATE_CREATE_INFO has no header */
173 if (dbg->type != XGL_DBG_OBJECT_VIEWPORT_STATE)
174 assert(!info.header->next);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800175
176 dbg->create_info = icd_alloc(shallow_copy, 0, XGL_SYSTEM_ALLOC_DEBUG);
177 if (!dbg->create_info)
178 return false;
179
180 memcpy(dbg->create_info, create_info, shallow_copy);
Chia-I Wue2934f92014-08-16 13:17:22 +0800181 dbg->create_info_size = shallow_copy;
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800182 } else if (info.header->struct_type ==
183 XGL_STRUCTURE_TYPE_DEVICE_CREATE_INFO) {
184 const XGL_DEVICE_CREATE_INFO *src = info.ptr;
185 XGL_DEVICE_CREATE_INFO *dst;
186 uint8_t *d;
187 XGL_SIZE size;
188 XGL_UINT i;
189
190 size = sizeof(*src);
Chia-I Wue2934f92014-08-16 13:17:22 +0800191 dbg->create_info_size = size;
192
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800193 size += sizeof(src->pRequestedQueues[0]) * src->queueRecordCount;
194 size += sizeof(src->ppEnabledExtensionNames[0]) * src->extensionCount;
195 for (i = 0; i < src->extensionCount; i++) {
196 size += 1 +
197 strlen((const char *) src->ppEnabledExtensionNames[i]);
198 }
199
Chia-I Wu98dcfab2014-08-07 12:07:52 +0800200 dst = icd_alloc(size, 0, XGL_SYSTEM_ALLOC_DEBUG);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800201 if (!dst)
202 return false;
203
204 memcpy(dst, src, sizeof(*src));
205
206 d = (uint8_t *) dst;
207 d += sizeof(*src);
208
209 size = sizeof(src->pRequestedQueues[0]) * src->queueRecordCount;
210 memcpy(d, src->pRequestedQueues, size);
211 dst->pRequestedQueues = (const XGL_DEVICE_QUEUE_CREATE_INFO *) d;
212 d += size;
213
214 size = sizeof(src->ppEnabledExtensionNames[0]) * src->extensionCount;
215 dst->ppEnabledExtensionNames = (const XGL_CHAR * const *) d;
216
217 for (i = 0; i < src->extensionCount; i++) {
218 const XGL_SIZE len =
219 strlen((const char *) src->ppEnabledExtensionNames[i]);
220
221 memcpy(d + size, src->ppEnabledExtensionNames[i], len + 1);
222 ((const XGL_CHAR **) d)[i] = (const XGL_CHAR *) (d + size);
223
224 size += len + 1;
225 }
Courtney Goeltzenleuchter191b06c2014-10-17 16:21:35 -0600226 dbg->create_info = dst;
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600227 } else if (info.header->struct_type == XGL_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO) {
228 // TODO: What do we want to copy here?
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800229 }
230
231 return true;
232}
233
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800234/**
Chia-I Wubbf2c932014-08-07 12:20:08 +0800235 * Create an intel_base_dbg. When dbg_size is non-zero, a buffer of that
Chia-I Wu660caf82014-08-07 10:54:26 +0800236 * size is allocated and zeroed.
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800237 */
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600238struct intel_base_dbg *intel_base_dbg_create(struct intel_dev *dev,
239 XGL_DBG_OBJECT_TYPE type,
Chia-I Wu660caf82014-08-07 10:54:26 +0800240 const void *create_info,
Chia-I Wubbf2c932014-08-07 12:20:08 +0800241 XGL_SIZE dbg_size)
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800242{
Chia-I Wu660caf82014-08-07 10:54:26 +0800243 struct intel_base_dbg *dbg;
244
Chia-I Wubbf2c932014-08-07 12:20:08 +0800245 if (!dbg_size)
246 dbg_size = sizeof(*dbg);
Chia-I Wu660caf82014-08-07 10:54:26 +0800247
Chia-I Wubbf2c932014-08-07 12:20:08 +0800248 assert(dbg_size >= sizeof(*dbg));
Chia-I Wu660caf82014-08-07 10:54:26 +0800249
Chia-I Wubbf2c932014-08-07 12:20:08 +0800250 dbg = icd_alloc(dbg_size, 0, XGL_SYSTEM_ALLOC_DEBUG);
Chia-I Wu660caf82014-08-07 10:54:26 +0800251 if (!dbg)
252 return NULL;
253
Chia-I Wubbf2c932014-08-07 12:20:08 +0800254 memset(dbg, 0, dbg_size);
Chia-I Wu660caf82014-08-07 10:54:26 +0800255
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800256 dbg->alloc_id = icd_get_allocator_id();
257 dbg->type = type;
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600258 dbg->dev = dev;
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800259
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800260 if (!base_dbg_copy_create_info(dbg, create_info)) {
261 icd_free(dbg);
262 return NULL;
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800263 }
264
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800265 return dbg;
266}
267
268void intel_base_dbg_destroy(struct intel_base_dbg *dbg)
269{
Chia-I Wu660caf82014-08-07 10:54:26 +0800270 if (dbg->tag)
271 icd_free(dbg->tag);
272
273 if (dbg->create_info)
274 icd_free(dbg->create_info);
275
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800276 icd_free(dbg);
277}
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800278
Chia-I Wubbf2c932014-08-07 12:20:08 +0800279/**
280 * Create an intel_base. obj_size and dbg_size specify the real sizes of the
281 * object and the debug metadata. Memories are zeroed.
282 */
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600283struct intel_base *intel_base_create(struct intel_dev *dev,
284 XGL_SIZE obj_size, bool debug,
Chia-I Wubbf2c932014-08-07 12:20:08 +0800285 XGL_DBG_OBJECT_TYPE type,
286 const void *create_info,
287 XGL_SIZE dbg_size)
288{
289 struct intel_base *base;
290
291 if (!obj_size)
292 obj_size = sizeof(*base);
293
294 assert(obj_size >= sizeof(*base));
295
296 base = icd_alloc(obj_size, 0, XGL_SYSTEM_ALLOC_API_OBJECT);
297 if (!base)
298 return NULL;
299
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600300 if (dev == NULL) {
301 /*
302 * dev is NULL when we are creating the base device object
303 * Set dev now so that debug setup happens correctly
304 */
305 dev = (struct intel_dev *) base;
306 }
307
Chia-I Wubbf2c932014-08-07 12:20:08 +0800308 memset(base, 0, obj_size);
309
Chia-I Wu6a42c2a2014-08-19 14:36:47 +0800310 base->dispatch = intel_dispatch_get(debug);
Chia-I Wubbf2c932014-08-07 12:20:08 +0800311 if (debug) {
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600312 base->dbg = intel_base_dbg_create(dev, type, create_info, dbg_size);
Chia-I Wubbf2c932014-08-07 12:20:08 +0800313 if (!base->dbg) {
314 icd_free(base);
315 return NULL;
316 }
317 }
Chia-I Wu6a42c2a2014-08-19 14:36:47 +0800318
Chia-I Wubbf2c932014-08-07 12:20:08 +0800319 base->get_info = intel_base_get_info;
320
321 return base;
322}
323
324void intel_base_destroy(struct intel_base *base)
325{
326 if (base->dbg)
327 intel_base_dbg_destroy(base->dbg);
328 icd_free(base);
329}
330
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800331XGL_RESULT XGLAPI intelDestroyObject(
332 XGL_OBJECT object)
333{
334 struct intel_obj *obj = intel_obj(object);
335
336 obj->destroy(obj);
337
338 return XGL_SUCCESS;
339}
340
341XGL_RESULT XGLAPI intelGetObjectInfo(
342 XGL_BASE_OBJECT object,
343 XGL_OBJECT_INFO_TYPE infoType,
344 XGL_SIZE* pDataSize,
345 XGL_VOID* pData)
346{
347 struct intel_base *base = intel_base(object);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800348
Chia-I Wu26f0bd02014-08-07 10:38:40 +0800349 return base->get_info(base, infoType, pDataSize, pData);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800350}
351
352XGL_RESULT XGLAPI intelBindObjectMemory(
353 XGL_OBJECT object,
Chia-I Wu9e61c0d2014-09-15 15:12:06 +0800354 XGL_GPU_MEMORY mem_,
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800355 XGL_GPU_SIZE offset)
356{
357 struct intel_obj *obj = intel_obj(object);
Chia-I Wu9e61c0d2014-09-15 15:12:06 +0800358 struct intel_mem *mem = intel_mem(mem_);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800359
Chia-I Wu9e61c0d2014-09-15 15:12:06 +0800360 intel_obj_bind_mem(obj, mem, offset);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800361
362 return XGL_SUCCESS;
363}
Chia-I Wu7ec9f342014-08-19 10:47:53 +0800364
365XGL_RESULT XGLAPI intelDbgSetObjectTag(
366 XGL_BASE_OBJECT object,
367 XGL_SIZE tagSize,
368 const XGL_VOID* pTag)
369{
370 struct intel_base *base = intel_base(object);
371 struct intel_base_dbg *dbg = base->dbg;
372 void *tag;
373
374 if (!dbg)
375 return XGL_SUCCESS;
376
377 tag = icd_alloc(tagSize, 0, XGL_SYSTEM_ALLOC_DEBUG);
378 if (!tag)
379 return XGL_ERROR_OUT_OF_MEMORY;
380
381 memcpy(tag, pTag, tagSize);
382
383 if (dbg->tag)
384 icd_free(dbg->tag);
385
386 dbg->tag = tag;
387 dbg->tag_size = tagSize;
388
389 return XGL_SUCCESS;
390}