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Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef CMD_H
26#define CMD_H
27
28#include "intel.h"
29#include "obj.h"
Chia-I Wub2755562014-08-20 13:38:52 +080030#include "view.h"
31
32struct intel_pipeline;
33struct intel_pipeline_delta;
34struct intel_viewport_state;
35struct intel_raster_state;
36struct intel_msaa_state;
37struct intel_blend_state;
38struct intel_ds_state;
39struct intel_dset;
40
Chia-I Wu958d1b72014-08-21 11:28:11 +080041struct intel_cmd_reloc;
42
Chia-I Wub2755562014-08-20 13:38:52 +080043/*
44 * States bounded to the command buffer. We want to write states directly to
45 * the command buffer when possible, and reduce this struct.
46 */
47struct intel_cmd_bind {
48 struct {
49 const struct intel_pipeline *graphics;
50 const struct intel_pipeline *compute;
51 const struct intel_pipeline_delta *graphics_delta;
52 const struct intel_pipeline_delta *compute_delta;
53 } pipeline;
54
55 struct {
56 const struct intel_viewport_state *viewport;
57 const struct intel_raster_state *raster;
58 const struct intel_msaa_state *msaa;
59 const struct intel_blend_state *blend;
60 const struct intel_ds_state *ds;
61 } state;
62
63 struct {
64 const struct intel_dset *graphics;
65 XGL_UINT graphics_offset;
66 const struct intel_dset *compute;
67 XGL_UINT compute_offset;
68 } dset;
69
70 struct {
71 struct intel_mem_view graphics;
72 struct intel_mem_view compute;
Chia-I Wu9f1722c2014-08-25 10:17:58 +080073 } dyn_view;
Chia-I Wub2755562014-08-20 13:38:52 +080074
75 struct {
76 const struct intel_mem *mem;
77 XGL_GPU_SIZE offset;
78 XGL_INDEX_TYPE type;
79 } index;
80
81 struct {
82 const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS];
83 XGL_UINT rt_count;
84
85 const struct intel_ds_view *ds;
86 } att;
Chia-I Wu48c283d2014-08-25 23:13:46 +080087
Chia-I Wu707a29e2014-08-27 12:51:47 +080088 XGL_UINT draw_count;
Chia-I Wu48c283d2014-08-25 23:13:46 +080089 uint32_t wa_flags;
Chia-I Wub2755562014-08-20 13:38:52 +080090};
Chia-I Wu09142132014-08-11 15:42:55 +080091
Chia-I Wue24c3292014-08-21 14:05:23 +080092struct intel_cmd_writer {
93 struct intel_bo *bo;
94 void *ptr_opaque;
95
96 /* in DWords */
97 XGL_UINT size;
98 XGL_UINT used;
99};
100
Chia-I Wu730e5362014-08-19 12:15:09 +0800101struct intel_cmd {
102 struct intel_obj obj;
103
104 struct intel_dev *dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800105 struct intel_bo *scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800106 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800107
Chia-I Wu343b1372014-08-20 16:39:20 +0800108 struct intel_cmd_reloc *relocs;
109 XGL_UINT reloc_count;
110
Chia-I Wu730e5362014-08-19 12:15:09 +0800111 XGL_FLAGS flags;
112
Chia-I Wue24c3292014-08-21 14:05:23 +0800113 struct intel_cmd_writer batch;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800114 struct intel_cmd_writer state;
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800115 struct intel_cmd_writer kernel;
Chia-I Wu730e5362014-08-19 12:15:09 +0800116
Chia-I Wu343b1372014-08-20 16:39:20 +0800117 XGL_UINT reloc_used;
Chia-I Wu04966702014-08-20 15:05:03 +0800118 XGL_RESULT result;
Chia-I Wub2755562014-08-20 13:38:52 +0800119
120 struct intel_cmd_bind bind;
Chia-I Wu730e5362014-08-19 12:15:09 +0800121};
122
123static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd)
124{
125 return (struct intel_cmd *) cmd;
126}
127
128static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj)
129{
130 return (struct intel_cmd *) obj;
131}
132
133XGL_RESULT intel_cmd_create(struct intel_dev *dev,
134 const XGL_CMD_BUFFER_CREATE_INFO *info,
135 struct intel_cmd **cmd_ret);
136void intel_cmd_destroy(struct intel_cmd *cmd);
137
138XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags);
139XGL_RESULT intel_cmd_end(struct intel_cmd *cmd);
140
Chia-I Wue24c3292014-08-21 14:05:23 +0800141static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd,
142 XGL_GPU_SIZE *used)
143{
144 const struct intel_cmd_writer *writer = &cmd->batch;
145
146 if (used)
147 *used = sizeof(uint32_t) * writer->used;
148
149 return writer->bo;
150}
151
Chia-I Wu09142132014-08-11 15:42:55 +0800152XGL_RESULT XGLAPI intelCreateCommandBuffer(
153 XGL_DEVICE device,
154 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
155 XGL_CMD_BUFFER* pCmdBuffer);
156
157XGL_RESULT XGLAPI intelBeginCommandBuffer(
158 XGL_CMD_BUFFER cmdBuffer,
159 XGL_FLAGS flags);
160
161XGL_RESULT XGLAPI intelEndCommandBuffer(
162 XGL_CMD_BUFFER cmdBuffer);
163
164XGL_RESULT XGLAPI intelResetCommandBuffer(
165 XGL_CMD_BUFFER cmdBuffer);
166
167XGL_VOID XGLAPI intelCmdBindPipeline(
168 XGL_CMD_BUFFER cmdBuffer,
169 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
170 XGL_PIPELINE pipeline);
171
172XGL_VOID XGLAPI intelCmdBindPipelineDelta(
173 XGL_CMD_BUFFER cmdBuffer,
174 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
175 XGL_PIPELINE_DELTA delta);
176
177XGL_VOID XGLAPI intelCmdBindStateObject(
178 XGL_CMD_BUFFER cmdBuffer,
179 XGL_STATE_BIND_POINT stateBindPoint,
180 XGL_STATE_OBJECT state);
181
182XGL_VOID XGLAPI intelCmdBindDescriptorSet(
183 XGL_CMD_BUFFER cmdBuffer,
184 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
185 XGL_UINT index,
186 XGL_DESCRIPTOR_SET descriptorSet,
187 XGL_UINT slotOffset);
188
189XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
190 XGL_CMD_BUFFER cmdBuffer,
191 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
192 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
193
194XGL_VOID XGLAPI intelCmdBindIndexData(
195 XGL_CMD_BUFFER cmdBuffer,
196 XGL_GPU_MEMORY mem,
197 XGL_GPU_SIZE offset,
198 XGL_INDEX_TYPE indexType);
199
200XGL_VOID XGLAPI intelCmdBindAttachments(
201 XGL_CMD_BUFFER cmdBuffer,
202 XGL_UINT colorAttachmentCount,
203 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
204 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
205
206XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
207 XGL_CMD_BUFFER cmdBuffer,
208 XGL_UINT transitionCount,
209 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
210
211XGL_VOID XGLAPI intelCmdPrepareImages(
212 XGL_CMD_BUFFER cmdBuffer,
213 XGL_UINT transitionCount,
214 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
215
216XGL_VOID XGLAPI intelCmdDraw(
217 XGL_CMD_BUFFER cmdBuffer,
218 XGL_UINT firstVertex,
219 XGL_UINT vertexCount,
220 XGL_UINT firstInstance,
221 XGL_UINT instanceCount);
222
223XGL_VOID XGLAPI intelCmdDrawIndexed(
224 XGL_CMD_BUFFER cmdBuffer,
225 XGL_UINT firstIndex,
226 XGL_UINT indexCount,
227 XGL_INT vertexOffset,
228 XGL_UINT firstInstance,
229 XGL_UINT instanceCount);
230
231XGL_VOID XGLAPI intelCmdDrawIndirect(
232 XGL_CMD_BUFFER cmdBuffer,
233 XGL_GPU_MEMORY mem,
234 XGL_GPU_SIZE offset,
235 XGL_UINT32 count,
236 XGL_UINT32 stride);
237
238XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
239 XGL_CMD_BUFFER cmdBuffer,
240 XGL_GPU_MEMORY mem,
241 XGL_GPU_SIZE offset,
242 XGL_UINT32 count,
243 XGL_UINT32 stride);
244
245XGL_VOID XGLAPI intelCmdDispatch(
246 XGL_CMD_BUFFER cmdBuffer,
247 XGL_UINT x,
248 XGL_UINT y,
249 XGL_UINT z);
250
251XGL_VOID XGLAPI intelCmdDispatchIndirect(
252 XGL_CMD_BUFFER cmdBuffer,
253 XGL_GPU_MEMORY mem,
254 XGL_GPU_SIZE offset);
255
256XGL_VOID XGLAPI intelCmdCopyMemory(
257 XGL_CMD_BUFFER cmdBuffer,
258 XGL_GPU_MEMORY srcMem,
259 XGL_GPU_MEMORY destMem,
260 XGL_UINT regionCount,
261 const XGL_MEMORY_COPY* pRegions);
262
263XGL_VOID XGLAPI intelCmdCopyImage(
264 XGL_CMD_BUFFER cmdBuffer,
265 XGL_IMAGE srcImage,
266 XGL_IMAGE destImage,
267 XGL_UINT regionCount,
268 const XGL_IMAGE_COPY* pRegions);
269
270XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
271 XGL_CMD_BUFFER cmdBuffer,
272 XGL_GPU_MEMORY srcMem,
273 XGL_IMAGE destImage,
274 XGL_UINT regionCount,
275 const XGL_MEMORY_IMAGE_COPY* pRegions);
276
277XGL_VOID XGLAPI intelCmdCopyImageToMemory(
278 XGL_CMD_BUFFER cmdBuffer,
279 XGL_IMAGE srcImage,
280 XGL_GPU_MEMORY destMem,
281 XGL_UINT regionCount,
282 const XGL_MEMORY_IMAGE_COPY* pRegions);
283
284XGL_VOID XGLAPI intelCmdCloneImageData(
285 XGL_CMD_BUFFER cmdBuffer,
286 XGL_IMAGE srcImage,
287 XGL_IMAGE_STATE srcImageState,
288 XGL_IMAGE destImage,
289 XGL_IMAGE_STATE destImageState);
290
291XGL_VOID XGLAPI intelCmdUpdateMemory(
292 XGL_CMD_BUFFER cmdBuffer,
293 XGL_GPU_MEMORY destMem,
294 XGL_GPU_SIZE destOffset,
295 XGL_GPU_SIZE dataSize,
296 const XGL_UINT32* pData);
297
298XGL_VOID XGLAPI intelCmdFillMemory(
299 XGL_CMD_BUFFER cmdBuffer,
300 XGL_GPU_MEMORY destMem,
301 XGL_GPU_SIZE destOffset,
302 XGL_GPU_SIZE fillSize,
303 XGL_UINT32 data);
304
305XGL_VOID XGLAPI intelCmdClearColorImage(
306 XGL_CMD_BUFFER cmdBuffer,
307 XGL_IMAGE image,
308 const XGL_FLOAT color[4],
309 XGL_UINT rangeCount,
310 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
311
312XGL_VOID XGLAPI intelCmdClearColorImageRaw(
313 XGL_CMD_BUFFER cmdBuffer,
314 XGL_IMAGE image,
315 const XGL_UINT32 color[4],
316 XGL_UINT rangeCount,
317 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
318
319XGL_VOID XGLAPI intelCmdClearDepthStencil(
320 XGL_CMD_BUFFER cmdBuffer,
321 XGL_IMAGE image,
322 XGL_FLOAT depth,
323 XGL_UINT32 stencil,
324 XGL_UINT rangeCount,
325 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
326
327XGL_VOID XGLAPI intelCmdResolveImage(
328 XGL_CMD_BUFFER cmdBuffer,
329 XGL_IMAGE srcImage,
330 XGL_IMAGE destImage,
331 XGL_UINT rectCount,
332 const XGL_IMAGE_RESOLVE* pRects);
333
334XGL_VOID XGLAPI intelCmdSetEvent(
335 XGL_CMD_BUFFER cmdBuffer,
336 XGL_EVENT event);
337
338XGL_VOID XGLAPI intelCmdResetEvent(
339 XGL_CMD_BUFFER cmdBuffer,
340 XGL_EVENT event);
341
342XGL_VOID XGLAPI intelCmdMemoryAtomic(
343 XGL_CMD_BUFFER cmdBuffer,
344 XGL_GPU_MEMORY destMem,
345 XGL_GPU_SIZE destOffset,
346 XGL_UINT64 srcData,
347 XGL_ATOMIC_OP atomicOp);
348
349XGL_VOID XGLAPI intelCmdBeginQuery(
350 XGL_CMD_BUFFER cmdBuffer,
351 XGL_QUERY_POOL queryPool,
352 XGL_UINT slot,
353 XGL_FLAGS flags);
354
355XGL_VOID XGLAPI intelCmdEndQuery(
356 XGL_CMD_BUFFER cmdBuffer,
357 XGL_QUERY_POOL queryPool,
358 XGL_UINT slot);
359
360XGL_VOID XGLAPI intelCmdResetQueryPool(
361 XGL_CMD_BUFFER cmdBuffer,
362 XGL_QUERY_POOL queryPool,
363 XGL_UINT startQuery,
364 XGL_UINT queryCount);
365
366XGL_VOID XGLAPI intelCmdWriteTimestamp(
367 XGL_CMD_BUFFER cmdBuffer,
368 XGL_TIMESTAMP_TYPE timestampType,
369 XGL_GPU_MEMORY destMem,
370 XGL_GPU_SIZE destOffset);
371
372XGL_VOID XGLAPI intelCmdInitAtomicCounters(
373 XGL_CMD_BUFFER cmdBuffer,
374 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
375 XGL_UINT startCounter,
376 XGL_UINT counterCount,
377 const XGL_UINT32* pData);
378
379XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
380 XGL_CMD_BUFFER cmdBuffer,
381 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
382 XGL_UINT startCounter,
383 XGL_UINT counterCount,
384 XGL_GPU_MEMORY srcMem,
385 XGL_GPU_SIZE srcOffset);
386
387XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
388 XGL_CMD_BUFFER cmdBuffer,
389 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
390 XGL_UINT startCounter,
391 XGL_UINT counterCount,
392 XGL_GPU_MEMORY destMem,
393 XGL_GPU_SIZE destOffset);
394
395XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
396 XGL_CMD_BUFFER cmdBuffer,
397 const XGL_CHAR* pMarker);
398
399XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
400 XGL_CMD_BUFFER cmdBuffer);
401
402#endif /* CMD_H */