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Chia-I Wu00a23b22014-08-20 15:28:08 +08001/*
Courtney Goeltzenleuchter9cc421e2015-04-08 15:36:08 -06002 * Vulkan
Chia-I Wu00a23b22014-08-20 15:28:08 +08003 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wu00a23b22014-08-20 15:28:08 +080026 */
27
28#ifndef CMD_PRIV_H
29#define CMD_PRIV_H
30
Chia-I Wue24c3292014-08-21 14:05:23 +080031#include "genhw/genhw.h"
Chia-I Wu32710d72014-08-20 16:05:22 +080032#include "dev.h"
Chia-I Wubdeed152015-07-09 12:16:29 +080033#include "fb.h"
Chia-I Wu32710d72014-08-20 16:05:22 +080034#include "gpu.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080035#include "cmd.h"
36
Chia-I Wu32710d72014-08-20 16:05:22 +080037#define CMD_ASSERT(cmd, min_gen, max_gen) \
38 INTEL_GPU_ASSERT((cmd)->dev->gpu, (min_gen), (max_gen))
39
Chia-I Wu00b51a82014-09-09 12:07:37 +080040enum intel_cmd_item_type {
41 /* for state buffer */
42 INTEL_CMD_ITEM_BLOB,
43 INTEL_CMD_ITEM_CLIP_VIEWPORT,
44 INTEL_CMD_ITEM_SF_VIEWPORT,
45 INTEL_CMD_ITEM_SCISSOR_RECT,
46 INTEL_CMD_ITEM_CC_VIEWPORT,
47 INTEL_CMD_ITEM_COLOR_CALC,
48 INTEL_CMD_ITEM_DEPTH_STENCIL,
49 INTEL_CMD_ITEM_BLEND,
50 INTEL_CMD_ITEM_SAMPLER,
51
52 /* for surface buffer */
53 INTEL_CMD_ITEM_SURFACE,
54 INTEL_CMD_ITEM_BINDING_TABLE,
55
56 /* for instruction buffer */
57 INTEL_CMD_ITEM_KERNEL,
58
59 INTEL_CMD_ITEM_COUNT,
60};
61
62struct intel_cmd_item {
63 enum intel_cmd_item_type type;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060064 size_t offset;
65 size_t size;
Chia-I Wu00b51a82014-09-09 12:07:37 +080066};
67
Chia-I Wud7d1e482014-10-18 13:25:10 +080068#define INTEL_CMD_RELOC_TARGET_IS_WRITER (1u << 31)
Chia-I Wu958d1b72014-08-21 11:28:11 +080069struct intel_cmd_reloc {
Chia-I Wu68f319d2014-09-09 09:43:21 +080070 enum intel_cmd_writer_type which;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060071 size_t offset;
Chia-I Wu958d1b72014-08-21 11:28:11 +080072
Chia-I Wud7d1e482014-10-18 13:25:10 +080073 intptr_t target;
74 uint32_t target_offset;
Chia-I Wu958d1b72014-08-21 11:28:11 +080075
Chia-I Wu32a22462014-08-26 14:13:46 +080076 uint32_t flags;
Chia-I Wu958d1b72014-08-21 11:28:11 +080077};
78
Chia-I Wu3d4d4a62015-07-09 10:34:10 +080079struct intel_att_view;
Chia-I Wuc14d1562014-10-17 09:49:22 +080080
Chia-I Wu29e6f502014-11-24 14:27:29 +080081enum intel_cmd_meta_mode {
82 /*
Chia-I Wu4d344e62014-12-20 21:06:04 +080083 * Draw POINTLIST of (width * height) vertices with only VS enabled. The
84 * vertex id is from 0 to (width * height - 1).
Chia-I Wu29e6f502014-11-24 14:27:29 +080085 */
86 INTEL_CMD_META_VS_POINTS,
87
88 /*
89 * Draw a RECTLIST from (dst.x, dst.y) to (dst.x + width, dst.y + height)
90 * with only FS enabled.
91 */
92 INTEL_CMD_META_FS_RECT,
93
94 /*
95 * Draw a RECTLIST from (dst.x, dst.y) to (dst.x + width, dst.y + height)
96 * with only depth/stencil enabled.
97 */
98 INTEL_CMD_META_DEPTH_STENCIL_RECT,
99};
100
Chia-I Wu73520ac2015-02-19 11:17:45 -0700101enum intel_cmd_meta_ds_op {
102 INTEL_CMD_META_DS_NOP,
103 INTEL_CMD_META_DS_HIZ_CLEAR,
104 INTEL_CMD_META_DS_HIZ_RESOLVE,
105 INTEL_CMD_META_DS_RESOLVE,
106};
107
Chia-I Wuc14d1562014-10-17 09:49:22 +0800108struct intel_cmd_meta {
Chia-I Wu29e6f502014-11-24 14:27:29 +0800109 enum intel_cmd_meta_mode mode;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800110 enum intel_dev_meta_shader shader_id;
111
112 struct {
113 bool valid;
114
115 uint32_t surface[8];
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600116 uint32_t surface_len;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800117
118 intptr_t reloc_target;
119 uint32_t reloc_offset;
120 uint32_t reloc_flags;
121
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600122 uint32_t lod, layer;
123 uint32_t x, y;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800124 } src, dst;
125
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800126 struct {
Courtney Goeltzenleuchter1856d6f2015-09-01 17:30:39 -0600127 struct intel_att_view view;
Tony Barbourfa6cac72015-01-16 14:27:35 -0700128 uint32_t stencil_ref;
Courtney Goeltzenleuchterba11ebe2015-10-21 17:00:51 -0600129 /* Using VkImageAspectFlagBits as that means we
130 * are expecting only one bit to be set at a time */
131 VkImageAspectFlagBits aspect;
Chia-I Wu73520ac2015-02-19 11:17:45 -0700132
133 enum intel_cmd_meta_ds_op op;
134 bool optimal;
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800135 } ds;
136
Chia-I Wuc14d1562014-10-17 09:49:22 +0800137 uint32_t clear_val[4];
138
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600139 uint32_t width, height;
140 uint32_t samples;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800141};
142
Chia-I Wu9f039862014-08-20 15:39:56 +0800143static inline int cmd_gen(const struct intel_cmd *cmd)
144{
145 return intel_gpu_gen(cmd->dev->gpu);
146}
147
Courtney Goeltzenleuchter382489d2015-04-10 08:34:15 -0600148static inline void cmd_fail(struct intel_cmd *cmd, VkResult result)
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700149{
Courtney Goeltzenleuchter1c7c65d2015-06-10 17:39:03 -0600150 intel_dev_log(cmd->dev, VK_DBG_REPORT_ERROR_BIT,
151 &cmd->obj.base, 0, 0,
152 "command building error");
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700153
154 cmd->result = result;
155}
156
Chia-I Wucdff0592014-08-22 09:27:36 +0800157static inline void cmd_reserve_reloc(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600158 uint32_t reloc_len)
Chia-I Wucdff0592014-08-22 09:27:36 +0800159{
160 /* fail silently */
161 if (cmd->reloc_used + reloc_len > cmd->reloc_count) {
162 cmd->reloc_used = 0;
Courtney Goeltzenleuchterac544f32015-09-14 18:01:17 -0600163 cmd_fail(cmd, VK_ERROR_VALIDATION_FAILED);
Chia-I Wucdff0592014-08-22 09:27:36 +0800164 }
165 assert(cmd->reloc_used + reloc_len <= cmd->reloc_count);
166}
167
Chia-I Wue24c3292014-08-21 14:05:23 +0800168void cmd_writer_grow(struct intel_cmd *cmd,
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800169 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600170 size_t new_size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800171
Chia-I Wu00b51a82014-09-09 12:07:37 +0800172void cmd_writer_record(struct intel_cmd *cmd,
173 enum intel_cmd_writer_type which,
174 enum intel_cmd_item_type type,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600175 size_t offset, size_t size);
Chia-I Wu00b51a82014-09-09 12:07:37 +0800176
Chia-I Wu72292b72014-09-09 10:48:33 +0800177/**
178 * Return an offset to a region that is aligned to \p alignment and has at
179 * least \p size bytes.
180 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600181static inline size_t cmd_writer_reserve(struct intel_cmd *cmd,
182 enum intel_cmd_writer_type which,
183 size_t alignment, size_t size)
Chia-I Wu72292b72014-09-09 10:48:33 +0800184{
185 struct intel_cmd_writer *writer = &cmd->writers[which];
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600186 size_t offset;
Chia-I Wu72292b72014-09-09 10:48:33 +0800187
188 assert(alignment && u_is_pow2(alignment));
189 offset = u_align(writer->used, alignment);
190
191 if (offset + size > writer->size) {
192 cmd_writer_grow(cmd, which, offset + size);
193 /* align again in case of errors */
194 offset = u_align(writer->used, alignment);
195
196 assert(offset + size <= writer->size);
197 }
198
199 return offset;
200}
Chia-I Wu00a23b22014-08-20 15:28:08 +0800201
Chia-I Wu32710d72014-08-20 16:05:22 +0800202/**
Chia-I Wubda55fd2014-08-25 12:46:10 +0800203 * Add a reloc at \p pos. No error checking.
Chia-I Wucdff0592014-08-22 09:27:36 +0800204 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800205static inline void cmd_writer_reloc(struct intel_cmd *cmd,
206 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600207 size_t offset, intptr_t target,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800208 uint32_t target_offset, uint32_t flags)
Chia-I Wucdff0592014-08-22 09:27:36 +0800209{
210 struct intel_cmd_reloc *reloc = &cmd->relocs[cmd->reloc_used];
211
212 assert(cmd->reloc_used < cmd->reloc_count);
213
Chia-I Wu68f319d2014-09-09 09:43:21 +0800214 reloc->which = which;
Chia-I Wu72292b72014-09-09 10:48:33 +0800215 reloc->offset = offset;
Chia-I Wud7d1e482014-10-18 13:25:10 +0800216 reloc->target = target;
217 reloc->target_offset = target_offset;
Chia-I Wu32a22462014-08-26 14:13:46 +0800218 reloc->flags = flags;
Chia-I Wucdff0592014-08-22 09:27:36 +0800219
220 cmd->reloc_used++;
221}
222
223/**
Chia-I Wu5da476a2014-12-10 08:50:28 +0800224 * Reserve a region from the state buffer. The offset, in bytes, to the
225 * reserved region is returned.
Chia-I Wu72292b72014-09-09 10:48:33 +0800226 *
227 * Note that \p alignment is in bytes and \p len is in DWords.
Chia-I Wue24c3292014-08-21 14:05:23 +0800228 */
Chia-I Wu5da476a2014-12-10 08:50:28 +0800229static inline uint32_t cmd_state_reserve(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800230 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600231 size_t alignment, uint32_t len)
Chia-I Wue24c3292014-08-21 14:05:23 +0800232{
Chia-I Wu72292b72014-09-09 10:48:33 +0800233 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_STATE;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600234 const size_t size = len << 2;
235 const size_t offset = cmd_writer_reserve(cmd, which, alignment, size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800236 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wue24c3292014-08-21 14:05:23 +0800237
Chia-I Wu72292b72014-09-09 10:48:33 +0800238 /* all states are at least aligned to 32-bytes */
239 assert(alignment % 32 == 0);
240
Chia-I Wu72292b72014-09-09 10:48:33 +0800241 writer->used = offset + size;
242
Chia-I Wu465fe212015-02-11 11:27:06 -0700243 if (intel_debug & (INTEL_DEBUG_BATCH | INTEL_DEBUG_HANG))
Chia-I Wu00b51a82014-09-09 12:07:37 +0800244 cmd_writer_record(cmd, which, item, offset, size);
245
Chia-I Wu72292b72014-09-09 10:48:33 +0800246 return offset;
Chia-I Wue24c3292014-08-21 14:05:23 +0800247}
248
249/**
Chia-I Wu5da476a2014-12-10 08:50:28 +0800250 * Get the pointer to a reserved region for updating. The pointer is only
251 * valid until the next reserve call.
252 */
253static inline void cmd_state_update(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600254 uint32_t offset, uint32_t len,
Chia-I Wu5da476a2014-12-10 08:50:28 +0800255 uint32_t **dw)
256{
257 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_STATE;
258 struct intel_cmd_writer *writer = &cmd->writers[which];
259
260 assert(offset + (len << 2) <= writer->used);
261
262 *dw = (uint32_t *) ((char *) writer->ptr + offset);
263}
264
265/**
266 * Reserve a region from the state buffer. Both the offset, in bytes, and the
267 * pointer to the reserved region are returned. The pointer is only valid
268 * until the next reserve call.
269 *
270 * Note that \p alignment is in bytes and \p len is in DWords.
271 */
272static inline uint32_t cmd_state_pointer(struct intel_cmd *cmd,
273 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600274 size_t alignment, uint32_t len,
Chia-I Wu5da476a2014-12-10 08:50:28 +0800275 uint32_t **dw)
276{
277 const uint32_t offset = cmd_state_reserve(cmd, item, alignment, len);
278
279 cmd_state_update(cmd, offset, len, dw);
280
281 return offset;
282}
283
284/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800285 * Write a dynamic state to the state buffer.
Chia-I Wucdff0592014-08-22 09:27:36 +0800286 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800287static inline uint32_t cmd_state_write(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800288 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600289 size_t alignment, uint32_t len,
Chia-I Wu72292b72014-09-09 10:48:33 +0800290 const uint32_t *dw)
Chia-I Wucdff0592014-08-22 09:27:36 +0800291{
Chia-I Wu72292b72014-09-09 10:48:33 +0800292 uint32_t offset, *dst;
293
Chia-I Wu00b51a82014-09-09 12:07:37 +0800294 offset = cmd_state_pointer(cmd, item, alignment, len, &dst);
Chia-I Wu72292b72014-09-09 10:48:33 +0800295 memcpy(dst, dw, len << 2);
296
297 return offset;
Chia-I Wucdff0592014-08-22 09:27:36 +0800298}
299
300/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800301 * Write a surface state to the surface buffer. The offset, in bytes, of the
302 * state is returned.
303 *
304 * Note that \p alignment is in bytes and \p len is in DWords.
Chia-I Wue24c3292014-08-21 14:05:23 +0800305 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800306static inline uint32_t cmd_surface_write(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800307 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600308 size_t alignment, uint32_t len,
Chia-I Wu72292b72014-09-09 10:48:33 +0800309 const uint32_t *dw)
Chia-I Wue24c3292014-08-21 14:05:23 +0800310{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800311 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wuf98dd882015-02-10 04:17:47 +0800312 const size_t size = len << 2;
Chia-I Wu15cccf72015-02-10 04:07:40 +0800313 const uint32_t offset = cmd_writer_reserve(cmd, which, alignment, size);
314 struct intel_cmd_writer *writer = &cmd->writers[which];
315 uint32_t *dst;
316
Chia-I Wu00b51a82014-09-09 12:07:37 +0800317 assert(item == INTEL_CMD_ITEM_SURFACE ||
318 item == INTEL_CMD_ITEM_BINDING_TABLE);
319
Chia-I Wu15cccf72015-02-10 04:07:40 +0800320 /* all states are at least aligned to 32-bytes */
321 assert(alignment % 32 == 0);
322
323 writer->used = offset + size;
324
325 if (intel_debug & INTEL_DEBUG_BATCH)
326 cmd_writer_record(cmd, which, item, offset, size);
327
328 dst = (uint32_t *) ((char *) writer->ptr + offset);
329 memcpy(dst, dw, size);
330
331 return offset;
Chia-I Wue24c3292014-08-21 14:05:23 +0800332}
333
334/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800335 * Add a relocation entry for a DWord of a surface state.
Chia-I Wucdff0592014-08-22 09:27:36 +0800336 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800337static inline void cmd_surface_reloc(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600338 uint32_t offset, uint32_t dw_index,
Chia-I Wu72292b72014-09-09 10:48:33 +0800339 struct intel_bo *bo,
340 uint32_t bo_offset, uint32_t reloc_flags)
Chia-I Wucdff0592014-08-22 09:27:36 +0800341{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800342 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wucdff0592014-08-22 09:27:36 +0800343
Chia-I Wu72292b72014-09-09 10:48:33 +0800344 cmd_writer_reloc(cmd, which, offset + (dw_index << 2),
Chia-I Wud7d1e482014-10-18 13:25:10 +0800345 (intptr_t) bo, bo_offset, reloc_flags);
346}
347
348static inline void cmd_surface_reloc_writer(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600349 uint32_t offset, uint32_t dw_index,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800350 enum intel_cmd_writer_type writer,
351 uint32_t writer_offset)
352{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800353 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wud7d1e482014-10-18 13:25:10 +0800354
355 cmd_writer_reloc(cmd, which, offset + (dw_index << 2),
356 (intptr_t) writer, writer_offset,
357 INTEL_CMD_RELOC_TARGET_IS_WRITER);
Chia-I Wucdff0592014-08-22 09:27:36 +0800358}
359
360/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800361 * Write a kernel to the instruction buffer. The offset, in bytes, of the
362 * kernel is returned.
Chia-I Wue24c3292014-08-21 14:05:23 +0800363 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800364static inline uint32_t cmd_instruction_write(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600365 size_t size,
Chia-I Wu72292b72014-09-09 10:48:33 +0800366 const void *kernel)
Chia-I Wue24c3292014-08-21 14:05:23 +0800367{
Chia-I Wu72292b72014-09-09 10:48:33 +0800368 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_INSTRUCTION;
369 /*
370 * From the Sandy Bridge PRM, volume 4 part 2, page 112:
371 *
372 * "Due to prefetch of the instruction stream, the EUs may attempt to
373 * access up to 8 instructions (128 bytes) beyond the end of the
374 * kernel program - possibly into the next memory page. Although
375 * these instructions will not be executed, software must account for
376 * the prefetch in order to avoid invalid page access faults."
377 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600378 const size_t reserved_size = size + 128;
Chia-I Wu72292b72014-09-09 10:48:33 +0800379 /* kernels are aligned to 64 bytes */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600380 const size_t alignment = 64;
381 const size_t offset = cmd_writer_reserve(cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +0800382 which, alignment, reserved_size);
383 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wue24c3292014-08-21 14:05:23 +0800384
Chia-I Wu72292b72014-09-09 10:48:33 +0800385 memcpy((char *) writer->ptr + offset, kernel, size);
Chia-I Wu5e25c272014-08-21 20:19:12 +0800386
Chia-I Wu72292b72014-09-09 10:48:33 +0800387 writer->used = offset + size;
388
Chia-I Wu465fe212015-02-11 11:27:06 -0700389 if (intel_debug & (INTEL_DEBUG_BATCH | INTEL_DEBUG_HANG))
Chia-I Wu00b51a82014-09-09 12:07:37 +0800390 cmd_writer_record(cmd, which, INTEL_CMD_ITEM_KERNEL, offset, size);
391
Chia-I Wu72292b72014-09-09 10:48:33 +0800392 return offset;
393}
394
395/**
396 * Reserve a region from the batch buffer. Both the offset, in DWords, and
Chia-I Wu5da476a2014-12-10 08:50:28 +0800397 * the pointer to the reserved region are returned. The pointer is only valid
398 * until the next reserve call.
Chia-I Wu72292b72014-09-09 10:48:33 +0800399 *
400 * Note that \p len is in DWords.
401 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600402static inline uint32_t cmd_batch_pointer(struct intel_cmd *cmd,
403 uint32_t len, uint32_t **dw)
Chia-I Wu72292b72014-09-09 10:48:33 +0800404{
405 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
406 /*
407 * We know the batch bo is always aligned. Using 1 here should allow the
408 * compiler to optimize away aligning.
409 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600410 const size_t alignment = 1;
411 const size_t size = len << 2;
412 const size_t offset = cmd_writer_reserve(cmd, which, alignment, size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800413 struct intel_cmd_writer *writer = &cmd->writers[which];
414
415 assert(offset % 4 == 0);
416 *dw = (uint32_t *) ((char *) writer->ptr + offset);
417
418 writer->used = offset + size;
419
420 return offset >> 2;
421}
422
423/**
424 * Write a command to the batch buffer.
425 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600426static inline uint32_t cmd_batch_write(struct intel_cmd *cmd,
427 uint32_t len, const uint32_t *dw)
Chia-I Wu72292b72014-09-09 10:48:33 +0800428{
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600429 uint32_t pos;
Chia-I Wu72292b72014-09-09 10:48:33 +0800430 uint32_t *dst;
431
432 pos = cmd_batch_pointer(cmd, len, &dst);
433 memcpy(dst, dw, len << 2);
434
435 return pos;
436}
437
438/**
439 * Add a relocation entry for a DWord of a command.
440 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600441static inline void cmd_batch_reloc(struct intel_cmd *cmd, uint32_t pos,
Chia-I Wu72292b72014-09-09 10:48:33 +0800442 struct intel_bo *bo,
443 uint32_t bo_offset, uint32_t reloc_flags)
444{
445 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
446
Chia-I Wud7d1e482014-10-18 13:25:10 +0800447 cmd_writer_reloc(cmd, which, pos << 2, (intptr_t) bo, bo_offset, reloc_flags);
448}
449
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600450static inline void cmd_batch_reloc_writer(struct intel_cmd *cmd, uint32_t pos,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800451 enum intel_cmd_writer_type writer,
452 uint32_t writer_offset)
453{
454 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
455
456 cmd_writer_reloc(cmd, which, pos << 2, (intptr_t) writer, writer_offset,
457 INTEL_CMD_RELOC_TARGET_IS_WRITER);
Chia-I Wue24c3292014-08-21 14:05:23 +0800458}
459
Chia-I Wu66bdcd72015-02-10 04:11:31 +0800460void cmd_batch_state_base_address(struct intel_cmd *cmd);
Chia-I Wu7c853562015-02-27 14:35:08 -0700461void cmd_batch_push_const_alloc(struct intel_cmd *cmd);
Chia-I Wu66bdcd72015-02-10 04:11:31 +0800462
Chia-I Wue24c3292014-08-21 14:05:23 +0800463/**
Chia-I Wu48c283d2014-08-25 23:13:46 +0800464 * Begin the batch buffer.
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800465 */
466static inline void cmd_batch_begin(struct intel_cmd *cmd)
467{
Chia-I Wu66bdcd72015-02-10 04:11:31 +0800468 cmd_batch_state_base_address(cmd);
Chia-I Wu7c853562015-02-27 14:35:08 -0700469 cmd_batch_push_const_alloc(cmd);
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800470}
471
472/**
Chia-I Wue24c3292014-08-21 14:05:23 +0800473 * End the batch buffer.
474 */
475static inline void cmd_batch_end(struct intel_cmd *cmd)
476{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800477 struct intel_cmd_writer *writer = &cmd->writers[INTEL_CMD_WRITER_BATCH];
Chia-I Wu72292b72014-09-09 10:48:33 +0800478 uint32_t *dw;
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800479
Chia-I Wu72292b72014-09-09 10:48:33 +0800480 if (writer->used & 0x7) {
481 cmd_batch_pointer(cmd, 1, &dw);
482 dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
Chia-I Wue24c3292014-08-21 14:05:23 +0800483 } else {
Chia-I Wu72292b72014-09-09 10:48:33 +0800484 cmd_batch_pointer(cmd, 2, &dw);
485 dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
486 dw[1] = GEN6_MI_CMD(MI_NOOP);
Chia-I Wue24c3292014-08-21 14:05:23 +0800487 }
Chia-I Wu343b1372014-08-20 16:39:20 +0800488}
489
Chia-I Wub5af7c52015-02-18 14:51:59 -0700490static inline void cmd_begin_render_pass(struct intel_cmd *cmd,
Courtney Goeltzenleuchtere3b0f3a2015-04-03 15:25:24 -0600491 const struct intel_render_pass *rp,
Chia-I Wu513ae5b2015-07-01 19:04:59 +0800492 const struct intel_fb *fb,
Cody Northrop16898b02015-08-11 11:35:58 -0600493 const uint32_t sp,
Chia-I Wu513ae5b2015-07-01 19:04:59 +0800494 VkRenderPassContents contents)
Chia-I Wub5af7c52015-02-18 14:51:59 -0700495{
Cody Northrop16898b02015-08-11 11:35:58 -0600496 assert(sp < rp->subpass_count);
497
Chia-I Wubbc7d912015-02-27 14:59:50 -0700498 cmd->bind.render_pass_changed = true;
Chia-I Wubdeed152015-07-09 12:16:29 +0800499 cmd->bind.render_pass = rp;
Cody Northrop16898b02015-08-11 11:35:58 -0600500 cmd->bind.render_pass_subpass = &rp->subpasses[sp];
Courtney Goeltzenleuchtere3b0f3a2015-04-03 15:25:24 -0600501 cmd->bind.fb = fb;
Chia-I Wu513ae5b2015-07-01 19:04:59 +0800502 cmd->bind.render_pass_contents = contents;
Chia-I Wub5af7c52015-02-18 14:51:59 -0700503}
504
Chia-I Wu88eaa3b2015-06-26 15:34:39 +0800505static inline void cmd_end_render_pass(struct intel_cmd *cmd)
Chia-I Wub5af7c52015-02-18 14:51:59 -0700506{
507 //note what to do if rp != bound rp
508 cmd->bind.render_pass = 0;
Courtney Goeltzenleuchtere3b0f3a2015-04-03 15:25:24 -0600509 cmd->bind.fb = 0;
Chia-I Wub5af7c52015-02-18 14:51:59 -0700510}
511
Chia-I Wu525c6602014-08-27 10:22:34 +0800512void cmd_batch_flush(struct intel_cmd *cmd, uint32_t pipe_control_dw0);
Chia-I Wu3fb47ce2014-10-28 11:19:36 +0800513void cmd_batch_flush_all(struct intel_cmd *cmd);
Chia-I Wu525c6602014-08-27 10:22:34 +0800514
Chia-I Wu759fa2e2014-08-30 18:44:47 +0800515void cmd_batch_depth_count(struct intel_cmd *cmd,
516 struct intel_bo *bo,
Tony Barbour8205d902015-04-16 15:59:00 -0600517 VkDeviceSize offset);
Chia-I Wu759fa2e2014-08-30 18:44:47 +0800518
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800519void cmd_batch_timestamp(struct intel_cmd *cmd,
520 struct intel_bo *bo,
Tony Barbour8205d902015-04-16 15:59:00 -0600521 VkDeviceSize offset);
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800522
523void cmd_batch_immediate(struct intel_cmd *cmd,
Mike Stroyan55658c22014-12-04 11:08:39 +0000524 uint32_t pipe_control_flags,
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800525 struct intel_bo *bo,
Tony Barbour8205d902015-04-16 15:59:00 -0600526 VkDeviceSize offset,
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800527 uint64_t val);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800528
Chia-I Wuc14d1562014-10-17 09:49:22 +0800529void cmd_draw_meta(struct intel_cmd *cmd, const struct intel_cmd_meta *meta);
530
Chia-I Wu73520ac2015-02-19 11:17:45 -0700531void cmd_meta_ds_op(struct intel_cmd *cmd,
532 enum intel_cmd_meta_ds_op op,
533 struct intel_img *img,
Courtney Goeltzenleuchter382489d2015-04-10 08:34:15 -0600534 const VkImageSubresourceRange *range);
Chia-I Wu73520ac2015-02-19 11:17:45 -0700535
Chris Forbesfff9bf42015-06-15 15:26:19 +1200536void cmd_meta_clear_color_image(
537 VkCmdBuffer cmdBuffer,
Tony Barbourde4124d2015-07-03 10:33:54 -0600538 struct intel_img *img,
Chris Forbesfff9bf42015-06-15 15:26:19 +1200539 VkImageLayout imageLayout,
Chris Forbese3105972015-06-24 14:34:53 +1200540 const VkClearColorValue *pClearColor,
Chris Forbesfff9bf42015-06-15 15:26:19 +1200541 uint32_t rangeCount,
542 const VkImageSubresourceRange *pRanges);
543
Chris Forbes4cf9d102015-06-22 18:46:05 +1200544void cmd_meta_clear_depth_stencil_image(
545 VkCmdBuffer cmdBuffer,
Tony Barbourde4124d2015-07-03 10:33:54 -0600546 struct intel_img* img,
Chris Forbes4cf9d102015-06-22 18:46:05 +1200547 VkImageLayout imageLayout,
548 float depth,
549 uint32_t stencil,
550 uint32_t rangeCount,
551 const VkImageSubresourceRange* pRanges);
552
Chia-I Wu00a23b22014-08-20 15:28:08 +0800553#endif /* CMD_PRIV_H */