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gerrit-public.fairphone.software / toolchain / llvm-project / 1de2d44dcf9507fce06d9dd1629dcbec4685ccb2 / . / llvm / lib / Target / AArch64 / AArch64LoadStoreOptimizer.cpp
blob: cc9524615c1c94b1101d8ad9062bf65373c3b777 [file] [log] [blame]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1//=- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a pass that performs load / store related peephole
11// optimizations. This pass should be run after register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AArch64InstrInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]16#include "AArch64Subtarget.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]17#include "MCTargetDesc/AArch64AddressingModes.h"
18#include "llvm/ADT/BitVector.h"
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]19#include "llvm/ADT/SmallVector.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]20#include "llvm/ADT/Statistic.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/MachineInstr.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/raw_ostream.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]29#include "llvm/Target/TargetInstrInfo.h"
30#include "llvm/Target/TargetMachine.h"
31#include "llvm/Target/TargetRegisterInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]32using namespace llvm;
33
34#define DEBUG_TYPE "aarch64-ldst-opt"
35
36/// AArch64AllocLoadStoreOpt - Post-register allocation pass to combine
37/// load / store instructions to form ldp / stp instructions.
38
39STATISTIC(NumPairCreated, "Number of load/store pair instructions generated");
40STATISTIC(NumPostFolded, "Number of post-index updates folded");
41STATISTIC(NumPreFolded, "Number of pre-index updates folded");
42STATISTIC(NumUnscaledPairCreated,
43 "Number of load/store from unscaled generated");
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]44STATISTIC(NumNarrowLoadsPromoted, "Number of narrow loads promoted");
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]45STATISTIC(NumZeroStoresPromoted, "Number of narrow zero stores promoted");
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]46STATISTIC(NumLoadsFromStoresPromoted, "Number of loads from stores promoted");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]48// The LdStLimit limits how far we search for load/store pairs.
49static cl::opt<unsigned> LdStLimit("aarch64-load-store-scan-limit",
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]50 cl::init(20), cl::Hidden);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]51
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]52// The UpdateLimit limits how far we search for update instructions when we form
53// pre-/post-index instructions.
54static cl::opt<unsigned> UpdateLimit("aarch64-update-scan-limit", cl::init(100),
55 cl::Hidden);
56
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]57namespace llvm {
58void initializeAArch64LoadStoreOptPass(PassRegistry &);
59}
60
61#define AARCH64_LOAD_STORE_OPT_NAME "AArch64 load / store optimization pass"
62
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]63namespace {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]64
65typedef struct LdStPairFlags {
66 // If a matching instruction is found, MergeForward is set to true if the
67 // merge is to remove the first instruction and replace the second with
68 // a pair-wise insn, and false if the reverse is true.
69 bool MergeForward;
70
71 // SExtIdx gives the index of the result of the load pair that must be
72 // extended. The value of SExtIdx assumes that the paired load produces the
73 // value in this order: (I, returned iterator), i.e., -1 means no value has
74 // to be extended, 0 means I, and 1 means the returned iterator.
75 int SExtIdx;
76
77 LdStPairFlags() : MergeForward(false), SExtIdx(-1) {}
78
79 void setMergeForward(bool V = true) { MergeForward = V; }
80 bool getMergeForward() const { return MergeForward; }
81
82 void setSExtIdx(int V) { SExtIdx = V; }
83 int getSExtIdx() const { return SExtIdx; }
84
85} LdStPairFlags;
86
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]87struct AArch64LoadStoreOpt : public MachineFunctionPass {
88 static char ID;
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]89 AArch64LoadStoreOpt() : MachineFunctionPass(ID) {
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]90 initializeAArch64LoadStoreOptPass(*PassRegistry::getPassRegistry());
91 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]92
93 const AArch64InstrInfo *TII;
94 const TargetRegisterInfo *TRI;
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]95 const AArch64Subtarget *Subtarget;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]96
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]97 // Track which registers have been modified and used.
98 BitVector ModifiedRegs, UsedRegs;
99
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]100 // Scan the instructions looking for a load/store that can be combined
101 // with the current instruction into a load/store pair.
102 // Return the matching instruction if one is found, else MBB->end().
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]103 MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]104 LdStPairFlags &Flags,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]105 unsigned Limit);
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]106
107 // Scan the instructions looking for a store that writes to the address from
108 // which the current load instruction reads. Return true if one is found.
109 bool findMatchingStore(MachineBasicBlock::iterator I, unsigned Limit,
110 MachineBasicBlock::iterator &StoreI);
111
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]112 // Merge the two instructions indicated into a single pair-wise instruction.
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]113 // If MergeForward is true, erase the first instruction and fold its
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]114 // operation into the second. If false, the reverse. Return the instruction
115 // following the first instruction (which may change during processing).
116 MachineBasicBlock::iterator
117 mergePairedInsns(MachineBasicBlock::iterator I,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]118 MachineBasicBlock::iterator Paired,
Chad Rosierfe5399f2015-07-21 17:47:56 +0000[diff] [blame]119 const LdStPairFlags &Flags);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]120
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]121 // Promote the load that reads directly from the address stored to.
122 MachineBasicBlock::iterator
123 promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
124 MachineBasicBlock::iterator StoreI);
125
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]126 // Scan the instruction list to find a base register update that can
127 // be combined with the current instruction (a load or store) using
128 // pre or post indexed addressing with writeback. Scan forwards.
129 MachineBasicBlock::iterator
Chad Rosier234bf6f2016-01-18 21:56:40 +0000[diff] [blame]130 findMatchingUpdateInsnForward(MachineBasicBlock::iterator I,
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]131 int UnscaledOffset, unsigned Limit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]132
133 // Scan the instruction list to find a base register update that can
134 // be combined with the current instruction (a load or store) using
135 // pre or post indexed addressing with writeback. Scan backwards.
136 MachineBasicBlock::iterator
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]137 findMatchingUpdateInsnBackward(MachineBasicBlock::iterator I, unsigned Limit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]138
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]139 // Find an instruction that updates the base register of the ld/st
140 // instruction.
141 bool isMatchingUpdateInsn(MachineInstr *MemMI, MachineInstr *MI,
142 unsigned BaseReg, int Offset);
143
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]144 // Merge a pre- or post-index base register update into a ld/st instruction.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]145 MachineBasicBlock::iterator
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]146 mergeUpdateInsn(MachineBasicBlock::iterator I,
147 MachineBasicBlock::iterator Update, bool IsPreIdx);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]148
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]149 // Find and merge foldable ldr/str instructions.
150 bool tryToMergeLdStInst(MachineBasicBlock::iterator &MBBI);
151
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]152 // Find and promote load instructions which read directly from store.
153 bool tryToPromoteLoadFromStore(MachineBasicBlock::iterator &MBBI);
154
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]155 // Check if converting two narrow loads into a single wider load with
156 // bitfield extracts could be enabled.
157 bool enableNarrowLdMerge(MachineFunction &Fn);
158
159 bool optimizeBlock(MachineBasicBlock &MBB, bool enableNarrowLdOpt);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]160
161 bool runOnMachineFunction(MachineFunction &Fn) override;
162
163 const char *getPassName() const override {
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]164 return AARCH64_LOAD_STORE_OPT_NAME;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]165 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]166};
167char AArch64LoadStoreOpt::ID = 0;
Jim Grosbach1eee3df2014-08-11 22:42:31 +0000[diff] [blame]168} // namespace
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]169
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]170INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
171 AARCH64_LOAD_STORE_OPT_NAME, false, false)
172
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]173static bool isUnscaledLdSt(unsigned Opc) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]174 switch (Opc) {
175 default:
176 return false;
177 case AArch64::STURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]178 case AArch64::STURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]179 case AArch64::STURQi:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]180 case AArch64::STURBBi:
181 case AArch64::STURHHi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]182 case AArch64::STURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]183 case AArch64::STURXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]184 case AArch64::LDURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]185 case AArch64::LDURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]186 case AArch64::LDURQi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]187 case AArch64::LDURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]188 case AArch64::LDURXi:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]189 case AArch64::LDURSWi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]190 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]191 case AArch64::LDURBBi:
192 case AArch64::LDURSBWi:
193 case AArch64::LDURSHWi:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]194 return true;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]195 }
196}
197
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]198static bool isUnscaledLdSt(MachineInstr *MI) {
199 return isUnscaledLdSt(MI->getOpcode());
200}
201
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]202static unsigned getBitExtrOpcode(MachineInstr *MI) {
203 switch (MI->getOpcode()) {
204 default:
205 llvm_unreachable("Unexpected opcode.");
206 case AArch64::LDRBBui:
207 case AArch64::LDURBBi:
208 case AArch64::LDRHHui:
209 case AArch64::LDURHHi:
210 return AArch64::UBFMWri;
211 case AArch64::LDRSBWui:
212 case AArch64::LDURSBWi:
213 case AArch64::LDRSHWui:
214 case AArch64::LDURSHWi:
215 return AArch64::SBFMWri;
216 }
217}
218
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]219static bool isNarrowStore(unsigned Opc) {
220 switch (Opc) {
221 default:
222 return false;
223 case AArch64::STRBBui:
224 case AArch64::STURBBi:
225 case AArch64::STRHHui:
226 case AArch64::STURHHi:
227 return true;
228 }
229}
230
231static bool isNarrowStore(MachineInstr *MI) {
232 return isNarrowStore(MI->getOpcode());
233}
234
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]235static bool isNarrowLoad(unsigned Opc) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]236 switch (Opc) {
237 default:
238 return false;
239 case AArch64::LDRHHui:
240 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]241 case AArch64::LDRBBui:
242 case AArch64::LDURBBi:
243 case AArch64::LDRSHWui:
244 case AArch64::LDURSHWi:
245 case AArch64::LDRSBWui:
246 case AArch64::LDURSBWi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]247 return true;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]248 }
249}
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]250
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]251static bool isNarrowLoad(MachineInstr *MI) {
252 return isNarrowLoad(MI->getOpcode());
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]253}
254
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]255// Scaling factor for unscaled load or store.
256static int getMemScale(MachineInstr *MI) {
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]257 switch (MI->getOpcode()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]258 default:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]259 llvm_unreachable("Opcode has unknown scale!");
260 case AArch64::LDRBBui:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]261 case AArch64::LDURBBi:
262 case AArch64::LDRSBWui:
263 case AArch64::LDURSBWi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]264 case AArch64::STRBBui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]265 case AArch64::STURBBi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]266 return 1;
267 case AArch64::LDRHHui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]268 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]269 case AArch64::LDRSHWui:
270 case AArch64::LDURSHWi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]271 case AArch64::STRHHui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]272 case AArch64::STURHHi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]273 return 2;
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]274 case AArch64::LDRSui:
275 case AArch64::LDURSi:
276 case AArch64::LDRSWui:
277 case AArch64::LDURSWi:
278 case AArch64::LDRWui:
279 case AArch64::LDURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]280 case AArch64::STRSui:
281 case AArch64::STURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]282 case AArch64::STRWui:
283 case AArch64::STURWi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]284 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]285 case AArch64::LDPSWi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]286 case AArch64::LDPWi:
287 case AArch64::STPSi:
288 case AArch64::STPWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]289 return 4;
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]290 case AArch64::LDRDui:
291 case AArch64::LDURDi:
292 case AArch64::LDRXui:
293 case AArch64::LDURXi:
294 case AArch64::STRDui:
295 case AArch64::STURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]296 case AArch64::STRXui:
297 case AArch64::STURXi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]298 case AArch64::LDPDi:
299 case AArch64::LDPXi:
300 case AArch64::STPDi:
301 case AArch64::STPXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]302 return 8;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]303 case AArch64::LDRQui:
304 case AArch64::LDURQi:
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]305 case AArch64::STRQui:
306 case AArch64::STURQi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]307 case AArch64::LDPQi:
308 case AArch64::STPQi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]309 return 16;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]310 }
311}
312
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]313static unsigned getMatchingNonSExtOpcode(unsigned Opc,
314 bool *IsValidLdStrOpc = nullptr) {
315 if (IsValidLdStrOpc)
316 *IsValidLdStrOpc = true;
317 switch (Opc) {
318 default:
319 if (IsValidLdStrOpc)
320 *IsValidLdStrOpc = false;
321 return UINT_MAX;
322 case AArch64::STRDui:
323 case AArch64::STURDi:
324 case AArch64::STRQui:
325 case AArch64::STURQi:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]326 case AArch64::STRBBui:
327 case AArch64::STURBBi:
328 case AArch64::STRHHui:
329 case AArch64::STURHHi:
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]330 case AArch64::STRWui:
331 case AArch64::STURWi:
332 case AArch64::STRXui:
333 case AArch64::STURXi:
334 case AArch64::LDRDui:
335 case AArch64::LDURDi:
336 case AArch64::LDRQui:
337 case AArch64::LDURQi:
338 case AArch64::LDRWui:
339 case AArch64::LDURWi:
340 case AArch64::LDRXui:
341 case AArch64::LDURXi:
342 case AArch64::STRSui:
343 case AArch64::STURSi:
344 case AArch64::LDRSui:
345 case AArch64::LDURSi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]346 case AArch64::LDRHHui:
347 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]348 case AArch64::LDRBBui:
349 case AArch64::LDURBBi:
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]350 return Opc;
351 case AArch64::LDRSWui:
352 return AArch64::LDRWui;
353 case AArch64::LDURSWi:
354 return AArch64::LDURWi;
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]355 case AArch64::LDRSBWui:
356 return AArch64::LDRBBui;
357 case AArch64::LDRSHWui:
358 return AArch64::LDRHHui;
359 case AArch64::LDURSBWi:
360 return AArch64::LDURBBi;
361 case AArch64::LDURSHWi:
362 return AArch64::LDURHHi;
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]363 }
364}
365
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame^]366static unsigned getMatchingWideOpcode(unsigned Opc) {
367 switch (Opc) {
368 default:
369 llvm_unreachable("Opcode has no wide equivalent!");
370 case AArch64::STRBBui:
371 return AArch64::STRHHui;
372 case AArch64::STRHHui:
373 return AArch64::STRWui;
374 case AArch64::STURBBi:
375 return AArch64::STURHHi;
376 case AArch64::STURHHi:
377 return AArch64::STURWi;
378 case AArch64::LDRHHui:
379 case AArch64::LDRSHWui:
380 return AArch64::LDRWui;
381 case AArch64::LDURHHi:
382 case AArch64::LDURSHWi:
383 return AArch64::LDURWi;
384 case AArch64::LDRBBui:
385 case AArch64::LDRSBWui:
386 return AArch64::LDRHHui;
387 case AArch64::LDURBBi:
388 case AArch64::LDURSBWi:
389 return AArch64::LDURHHi;
390 }
391}
392
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]393static unsigned getMatchingPairOpcode(unsigned Opc) {
394 switch (Opc) {
395 default:
396 llvm_unreachable("Opcode has no pairwise equivalent!");
397 case AArch64::STRSui:
398 case AArch64::STURSi:
399 return AArch64::STPSi;
400 case AArch64::STRDui:
401 case AArch64::STURDi:
402 return AArch64::STPDi;
403 case AArch64::STRQui:
404 case AArch64::STURQi:
405 return AArch64::STPQi;
406 case AArch64::STRWui:
407 case AArch64::STURWi:
408 return AArch64::STPWi;
409 case AArch64::STRXui:
410 case AArch64::STURXi:
411 return AArch64::STPXi;
412 case AArch64::LDRSui:
413 case AArch64::LDURSi:
414 return AArch64::LDPSi;
415 case AArch64::LDRDui:
416 case AArch64::LDURDi:
417 return AArch64::LDPDi;
418 case AArch64::LDRQui:
419 case AArch64::LDURQi:
420 return AArch64::LDPQi;
421 case AArch64::LDRWui:
422 case AArch64::LDURWi:
423 return AArch64::LDPWi;
424 case AArch64::LDRXui:
425 case AArch64::LDURXi:
426 return AArch64::LDPXi;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]427 case AArch64::LDRSWui:
428 case AArch64::LDURSWi:
429 return AArch64::LDPSWi;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]430 }
431}
432
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]433static unsigned isMatchingStore(MachineInstr *LoadInst,
434 MachineInstr *StoreInst) {
435 unsigned LdOpc = LoadInst->getOpcode();
436 unsigned StOpc = StoreInst->getOpcode();
437 switch (LdOpc) {
438 default:
439 llvm_unreachable("Unsupported load instruction!");
440 case AArch64::LDRBBui:
441 return StOpc == AArch64::STRBBui || StOpc == AArch64::STRHHui ||
442 StOpc == AArch64::STRWui || StOpc == AArch64::STRXui;
443 case AArch64::LDURBBi:
444 return StOpc == AArch64::STURBBi || StOpc == AArch64::STURHHi ||
445 StOpc == AArch64::STURWi || StOpc == AArch64::STURXi;
446 case AArch64::LDRHHui:
447 return StOpc == AArch64::STRHHui || StOpc == AArch64::STRWui ||
448 StOpc == AArch64::STRXui;
449 case AArch64::LDURHHi:
450 return StOpc == AArch64::STURHHi || StOpc == AArch64::STURWi ||
451 StOpc == AArch64::STURXi;
452 case AArch64::LDRWui:
453 return StOpc == AArch64::STRWui || StOpc == AArch64::STRXui;
454 case AArch64::LDURWi:
455 return StOpc == AArch64::STURWi || StOpc == AArch64::STURXi;
456 case AArch64::LDRXui:
457 return StOpc == AArch64::STRXui;
458 case AArch64::LDURXi:
459 return StOpc == AArch64::STURXi;
460 }
461}
462
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]463static unsigned getPreIndexedOpcode(unsigned Opc) {
464 switch (Opc) {
465 default:
466 llvm_unreachable("Opcode has no pre-indexed equivalent!");
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]467 case AArch64::STRSui:
468 return AArch64::STRSpre;
469 case AArch64::STRDui:
470 return AArch64::STRDpre;
471 case AArch64::STRQui:
472 return AArch64::STRQpre;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]473 case AArch64::STRBBui:
474 return AArch64::STRBBpre;
475 case AArch64::STRHHui:
476 return AArch64::STRHHpre;
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]477 case AArch64::STRWui:
478 return AArch64::STRWpre;
479 case AArch64::STRXui:
480 return AArch64::STRXpre;
481 case AArch64::LDRSui:
482 return AArch64::LDRSpre;
483 case AArch64::LDRDui:
484 return AArch64::LDRDpre;
485 case AArch64::LDRQui:
486 return AArch64::LDRQpre;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]487 case AArch64::LDRBBui:
488 return AArch64::LDRBBpre;
489 case AArch64::LDRHHui:
490 return AArch64::LDRHHpre;
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]491 case AArch64::LDRWui:
492 return AArch64::LDRWpre;
493 case AArch64::LDRXui:
494 return AArch64::LDRXpre;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]495 case AArch64::LDRSWui:
496 return AArch64::LDRSWpre;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]497 case AArch64::LDPSi:
498 return AArch64::LDPSpre;
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]499 case AArch64::LDPSWi:
500 return AArch64::LDPSWpre;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]501 case AArch64::LDPDi:
502 return AArch64::LDPDpre;
503 case AArch64::LDPQi:
504 return AArch64::LDPQpre;
505 case AArch64::LDPWi:
506 return AArch64::LDPWpre;
507 case AArch64::LDPXi:
508 return AArch64::LDPXpre;
509 case AArch64::STPSi:
510 return AArch64::STPSpre;
511 case AArch64::STPDi:
512 return AArch64::STPDpre;
513 case AArch64::STPQi:
514 return AArch64::STPQpre;
515 case AArch64::STPWi:
516 return AArch64::STPWpre;
517 case AArch64::STPXi:
518 return AArch64::STPXpre;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]519 }
520}
521
522static unsigned getPostIndexedOpcode(unsigned Opc) {
523 switch (Opc) {
524 default:
525 llvm_unreachable("Opcode has no post-indexed wise equivalent!");
526 case AArch64::STRSui:
527 return AArch64::STRSpost;
528 case AArch64::STRDui:
529 return AArch64::STRDpost;
530 case AArch64::STRQui:
531 return AArch64::STRQpost;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]532 case AArch64::STRBBui:
533 return AArch64::STRBBpost;
534 case AArch64::STRHHui:
535 return AArch64::STRHHpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]536 case AArch64::STRWui:
537 return AArch64::STRWpost;
538 case AArch64::STRXui:
539 return AArch64::STRXpost;
540 case AArch64::LDRSui:
541 return AArch64::LDRSpost;
542 case AArch64::LDRDui:
543 return AArch64::LDRDpost;
544 case AArch64::LDRQui:
545 return AArch64::LDRQpost;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]546 case AArch64::LDRBBui:
547 return AArch64::LDRBBpost;
548 case AArch64::LDRHHui:
549 return AArch64::LDRHHpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]550 case AArch64::LDRWui:
551 return AArch64::LDRWpost;
552 case AArch64::LDRXui:
553 return AArch64::LDRXpost;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]554 case AArch64::LDRSWui:
555 return AArch64::LDRSWpost;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]556 case AArch64::LDPSi:
557 return AArch64::LDPSpost;
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]558 case AArch64::LDPSWi:
559 return AArch64::LDPSWpost;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]560 case AArch64::LDPDi:
561 return AArch64::LDPDpost;
562 case AArch64::LDPQi:
563 return AArch64::LDPQpost;
564 case AArch64::LDPWi:
565 return AArch64::LDPWpost;
566 case AArch64::LDPXi:
567 return AArch64::LDPXpost;
568 case AArch64::STPSi:
569 return AArch64::STPSpost;
570 case AArch64::STPDi:
571 return AArch64::STPDpost;
572 case AArch64::STPQi:
573 return AArch64::STPQpost;
574 case AArch64::STPWi:
575 return AArch64::STPWpost;
576 case AArch64::STPXi:
577 return AArch64::STPXpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]578 }
579}
580
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]581static bool isPairedLdSt(const MachineInstr *MI) {
582 switch (MI->getOpcode()) {
583 default:
584 return false;
585 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]586 case AArch64::LDPSWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]587 case AArch64::LDPDi:
588 case AArch64::LDPQi:
589 case AArch64::LDPWi:
590 case AArch64::LDPXi:
591 case AArch64::STPSi:
592 case AArch64::STPDi:
593 case AArch64::STPQi:
594 case AArch64::STPWi:
595 case AArch64::STPXi:
596 return true;
597 }
598}
599
600static const MachineOperand &getLdStRegOp(const MachineInstr *MI,
601 unsigned PairedRegOp = 0) {
602 assert(PairedRegOp < 2 && "Unexpected register operand idx.");
603 unsigned Idx = isPairedLdSt(MI) ? PairedRegOp : 0;
604 return MI->getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]605}
606
607static const MachineOperand &getLdStBaseOp(const MachineInstr *MI) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]608 unsigned Idx = isPairedLdSt(MI) ? 2 : 1;
609 return MI->getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]610}
611
612static const MachineOperand &getLdStOffsetOp(const MachineInstr *MI) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]613 unsigned Idx = isPairedLdSt(MI) ? 3 : 2;
614 return MI->getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]615}
616
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]617static bool isLdOffsetInRangeOfSt(MachineInstr *LoadInst,
618 MachineInstr *StoreInst) {
619 assert(isMatchingStore(LoadInst, StoreInst) && "Expect only matched ld/st.");
620 int LoadSize = getMemScale(LoadInst);
621 int StoreSize = getMemScale(StoreInst);
622 int UnscaledStOffset = isUnscaledLdSt(StoreInst)
623 ? getLdStOffsetOp(StoreInst).getImm()
624 : getLdStOffsetOp(StoreInst).getImm() * StoreSize;
625 int UnscaledLdOffset = isUnscaledLdSt(LoadInst)
626 ? getLdStOffsetOp(LoadInst).getImm()
627 : getLdStOffsetOp(LoadInst).getImm() * LoadSize;
628 return (UnscaledStOffset <= UnscaledLdOffset) &&
629 (UnscaledLdOffset + LoadSize <= (UnscaledStOffset + StoreSize));
630}
631
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]632MachineBasicBlock::iterator
633AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
634 MachineBasicBlock::iterator Paired,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]635 const LdStPairFlags &Flags) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]636 MachineBasicBlock::iterator NextI = I;
637 ++NextI;
638 // If NextI is the second of the two instructions to be merged, we need
639 // to skip one further. Either way we merge will invalidate the iterator,
640 // and we don't need to scan the new instruction, as it's a pairwise
641 // instruction, which we're not considering for further action anyway.
642 if (NextI == Paired)
643 ++NextI;
644
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]645 int SExtIdx = Flags.getSExtIdx();
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]646 unsigned Opc =
647 SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]648 bool IsUnscaled = isUnscaledLdSt(Opc);
Chad Rosierf11d0402015-10-01 18:17:12 +0000[diff] [blame]649 int OffsetStride = IsUnscaled ? getMemScale(I) : 1;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]650
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]651 bool MergeForward = Flags.getMergeForward();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]652 // Insert our new paired instruction after whichever of the paired
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]653 // instructions MergeForward indicates.
654 MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
655 // Also based on MergeForward is from where we copy the base register operand
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]656 // so we get the flags compatible with the input code.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]657 const MachineOperand &BaseRegOp =
658 MergeForward ? getLdStBaseOp(Paired) : getLdStBaseOp(I);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]659
660 // Which register is Rt and which is Rt2 depends on the offset order.
661 MachineInstr *RtMI, *Rt2MI;
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame]662 if (getLdStOffsetOp(I).getImm() ==
663 getLdStOffsetOp(Paired).getImm() + OffsetStride) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]664 RtMI = Paired;
665 Rt2MI = I;
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]666 // Here we swapped the assumption made for SExtIdx.
667 // I.e., we turn ldp I, Paired into ldp Paired, I.
668 // Update the index accordingly.
669 if (SExtIdx != -1)
670 SExtIdx = (SExtIdx + 1) % 2;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]671 } else {
672 RtMI = I;
673 Rt2MI = Paired;
674 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]675
James Molloy5b18b4c2015-10-23 10:41:38 +0000[diff] [blame]676 int OffsetImm = getLdStOffsetOp(RtMI).getImm();
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]677
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]678 if (isNarrowLoad(Opc)) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]679 // Change the scaled offset from small to large type.
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]680 if (!IsUnscaled) {
681 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge");
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]682 OffsetImm /= 2;
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]683 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]684 MachineInstr *RtNewDest = MergeForward ? I : Paired;
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]685 // When merging small (< 32 bit) loads for big-endian targets, the order of
686 // the component parts gets swapped.
687 if (!Subtarget->isLittleEndian())
688 std::swap(RtMI, Rt2MI);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]689 // Construct the new load instruction.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]690 MachineInstr *NewMemMI, *BitExtMI1, *BitExtMI2;
691 NewMemMI = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame^]692 TII->get(getMatchingWideOpcode(Opc)))
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]693 .addOperand(getLdStRegOp(RtNewDest))
694 .addOperand(BaseRegOp)
Philip Reamesc86ed002016-01-06 04:39:03 +0000[diff] [blame]695 .addImm(OffsetImm)
696 .setMemRefs(I->mergeMemRefsWith(*Paired));
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]697
698 DEBUG(
699 dbgs()
700 << "Creating the new load and extract. Replacing instructions:\n ");
701 DEBUG(I->print(dbgs()));
702 DEBUG(dbgs() << " ");
703 DEBUG(Paired->print(dbgs()));
704 DEBUG(dbgs() << " with instructions:\n ");
705 DEBUG((NewMemMI)->print(dbgs()));
706
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]707 int Width = getMemScale(I) == 1 ? 8 : 16;
708 int LSBLow = 0;
709 int LSBHigh = Width;
710 int ImmsLow = LSBLow + Width - 1;
711 int ImmsHigh = LSBHigh + Width - 1;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]712 MachineInstr *ExtDestMI = MergeForward ? Paired : I;
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]713 if ((ExtDestMI == Rt2MI) == Subtarget->isLittleEndian()) {
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]714 // Create the bitfield extract for high bits.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]715 BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]716 TII->get(getBitExtrOpcode(Rt2MI)))
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]717 .addOperand(getLdStRegOp(Rt2MI))
718 .addReg(getLdStRegOp(RtNewDest).getReg())
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]719 .addImm(LSBHigh)
720 .addImm(ImmsHigh);
721 // Create the bitfield extract for low bits.
722 if (RtMI->getOpcode() == getMatchingNonSExtOpcode(RtMI->getOpcode())) {
723 // For unsigned, prefer to use AND for low bits.
724 BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
725 TII->get(AArch64::ANDWri))
726 .addOperand(getLdStRegOp(RtMI))
727 .addReg(getLdStRegOp(RtNewDest).getReg())
728 .addImm(ImmsLow);
729 } else {
730 BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
731 TII->get(getBitExtrOpcode(RtMI)))
732 .addOperand(getLdStRegOp(RtMI))
733 .addReg(getLdStRegOp(RtNewDest).getReg())
734 .addImm(LSBLow)
735 .addImm(ImmsLow);
736 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]737 } else {
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]738 // Create the bitfield extract for low bits.
739 if (RtMI->getOpcode() == getMatchingNonSExtOpcode(RtMI->getOpcode())) {
740 // For unsigned, prefer to use AND for low bits.
741 BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
742 TII->get(AArch64::ANDWri))
743 .addOperand(getLdStRegOp(RtMI))
744 .addReg(getLdStRegOp(RtNewDest).getReg())
745 .addImm(ImmsLow);
746 } else {
747 BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
748 TII->get(getBitExtrOpcode(RtMI)))
749 .addOperand(getLdStRegOp(RtMI))
750 .addReg(getLdStRegOp(RtNewDest).getReg())
751 .addImm(LSBLow)
752 .addImm(ImmsLow);
753 }
754
755 // Create the bitfield extract for high bits.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]756 BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]757 TII->get(getBitExtrOpcode(Rt2MI)))
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]758 .addOperand(getLdStRegOp(Rt2MI))
759 .addReg(getLdStRegOp(RtNewDest).getReg())
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]760 .addImm(LSBHigh)
761 .addImm(ImmsHigh);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]762 }
763 DEBUG(dbgs() << " ");
764 DEBUG((BitExtMI1)->print(dbgs()));
765 DEBUG(dbgs() << " ");
766 DEBUG((BitExtMI2)->print(dbgs()));
767 DEBUG(dbgs() << "\n");
768
769 // Erase the old instructions.
770 I->eraseFromParent();
771 Paired->eraseFromParent();
772 return NextI;
773 }
774
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]775 // Construct the new instruction.
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]776 MachineInstrBuilder MIB;
777 if (isNarrowStore(Opc)) {
778 // Change the scaled offset from small to large type.
779 if (!IsUnscaled) {
780 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge");
781 OffsetImm /= 2;
782 }
783 MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame^]784 TII->get(getMatchingWideOpcode(Opc)))
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]785 .addOperand(getLdStRegOp(I))
786 .addOperand(BaseRegOp)
Philip Reamesc86ed002016-01-06 04:39:03 +0000[diff] [blame]787 .addImm(OffsetImm)
788 .setMemRefs(I->mergeMemRefsWith(*Paired));
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]789 } else {
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame]790 // Handle Unscaled
791 if (IsUnscaled)
792 OffsetImm /= OffsetStride;
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]793 MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame^]794 TII->get(getMatchingPairOpcode(Opc)))
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]795 .addOperand(getLdStRegOp(RtMI))
796 .addOperand(getLdStRegOp(Rt2MI))
797 .addOperand(BaseRegOp)
798 .addImm(OffsetImm);
799 }
800
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]801 (void)MIB;
802
803 // FIXME: Do we need/want to copy the mem operands from the source
804 // instructions? Probably. What uses them after this?
805
806 DEBUG(dbgs() << "Creating pair load/store. Replacing instructions:\n ");
807 DEBUG(I->print(dbgs()));
808 DEBUG(dbgs() << " ");
809 DEBUG(Paired->print(dbgs()));
810 DEBUG(dbgs() << " with instruction:\n ");
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]811
812 if (SExtIdx != -1) {
813 // Generate the sign extension for the proper result of the ldp.
814 // I.e., with X1, that would be:
815 // %W1<def> = KILL %W1, %X1<imp-def>
816 // %X1<def> = SBFMXri %X1<kill>, 0, 31
817 MachineOperand &DstMO = MIB->getOperand(SExtIdx);
818 // Right now, DstMO has the extended register, since it comes from an
819 // extended opcode.
820 unsigned DstRegX = DstMO.getReg();
821 // Get the W variant of that register.
822 unsigned DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);
823 // Update the result of LDP to use the W instead of the X variant.
824 DstMO.setReg(DstRegW);
825 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
826 DEBUG(dbgs() << "\n");
827 // Make the machine verifier happy by providing a definition for
828 // the X register.
829 // Insert this definition right after the generated LDP, i.e., before
830 // InsertionPoint.
831 MachineInstrBuilder MIBKill =
832 BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
833 TII->get(TargetOpcode::KILL), DstRegW)
834 .addReg(DstRegW)
835 .addReg(DstRegX, RegState::Define);
836 MIBKill->getOperand(2).setImplicit();
837 // Create the sign extension.
838 MachineInstrBuilder MIBSXTW =
839 BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
840 TII->get(AArch64::SBFMXri), DstRegX)
841 .addReg(DstRegX)
842 .addImm(0)
843 .addImm(31);
844 (void)MIBSXTW;
845 DEBUG(dbgs() << " Extend operand:\n ");
846 DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));
847 DEBUG(dbgs() << "\n");
848 } else {
849 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
850 DEBUG(dbgs() << "\n");
851 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]852
853 // Erase the old instructions.
854 I->eraseFromParent();
855 Paired->eraseFromParent();
856
857 return NextI;
858}
859
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]860MachineBasicBlock::iterator
861AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
862 MachineBasicBlock::iterator StoreI) {
863 MachineBasicBlock::iterator NextI = LoadI;
864 ++NextI;
865
866 int LoadSize = getMemScale(LoadI);
867 int StoreSize = getMemScale(StoreI);
868 unsigned LdRt = getLdStRegOp(LoadI).getReg();
869 unsigned StRt = getLdStRegOp(StoreI).getReg();
870 bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt);
871
872 assert((IsStoreXReg ||
873 TRI->getRegClass(AArch64::GPR32RegClassID)->contains(StRt)) &&
874 "Unexpected RegClass");
875
876 MachineInstr *BitExtMI;
877 if (LoadSize == StoreSize && (LoadSize == 4 || LoadSize == 8)) {
878 // Remove the load, if the destination register of the loads is the same
879 // register for stored value.
880 if (StRt == LdRt && LoadSize == 8) {
881 DEBUG(dbgs() << "Remove load instruction:\n ");
882 DEBUG(LoadI->print(dbgs()));
883 DEBUG(dbgs() << "\n");
884 LoadI->eraseFromParent();
885 return NextI;
886 }
887 // Replace the load with a mov if the load and store are in the same size.
888 BitExtMI =
889 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
890 TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
891 .addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
892 .addReg(StRt)
893 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
894 } else {
895 // FIXME: Currently we disable this transformation in big-endian targets as
896 // performance and correctness are verified only in little-endian.
897 if (!Subtarget->isLittleEndian())
898 return NextI;
899 bool IsUnscaled = isUnscaledLdSt(LoadI);
900 assert(IsUnscaled == isUnscaledLdSt(StoreI) && "Unsupported ld/st match");
901 assert(LoadSize <= StoreSize && "Invalid load size");
902 int UnscaledLdOffset = IsUnscaled
903 ? getLdStOffsetOp(LoadI).getImm()
904 : getLdStOffsetOp(LoadI).getImm() * LoadSize;
905 int UnscaledStOffset = IsUnscaled
906 ? getLdStOffsetOp(StoreI).getImm()
907 : getLdStOffsetOp(StoreI).getImm() * StoreSize;
908 int Width = LoadSize * 8;
909 int Immr = 8 * (UnscaledLdOffset - UnscaledStOffset);
910 int Imms = Immr + Width - 1;
911 unsigned DestReg = IsStoreXReg
912 ? TRI->getMatchingSuperReg(LdRt, AArch64::sub_32,
913 &AArch64::GPR64RegClass)
914 : LdRt;
915
916 assert((UnscaledLdOffset >= UnscaledStOffset &&
917 (UnscaledLdOffset + LoadSize) <= UnscaledStOffset + StoreSize) &&
918 "Invalid offset");
919
920 Immr = 8 * (UnscaledLdOffset - UnscaledStOffset);
921 Imms = Immr + Width - 1;
922 if (UnscaledLdOffset == UnscaledStOffset) {
923 uint32_t AndMaskEncoded = ((IsStoreXReg ? 1 : 0) << 12) // N
924 | ((Immr) << 6) // immr
925 | ((Imms) << 0) // imms
926 ;
927
928 BitExtMI =
929 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
930 TII->get(IsStoreXReg ? AArch64::ANDXri : AArch64::ANDWri),
931 DestReg)
932 .addReg(StRt)
933 .addImm(AndMaskEncoded);
934 } else {
935 BitExtMI =
936 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
937 TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri),
938 DestReg)
939 .addReg(StRt)
940 .addImm(Immr)
941 .addImm(Imms);
942 }
943 }
944
945 DEBUG(dbgs() << "Promoting load by replacing :\n ");
946 DEBUG(StoreI->print(dbgs()));
947 DEBUG(dbgs() << " ");
948 DEBUG(LoadI->print(dbgs()));
949 DEBUG(dbgs() << " with instructions:\n ");
950 DEBUG(StoreI->print(dbgs()));
951 DEBUG(dbgs() << " ");
952 DEBUG((BitExtMI)->print(dbgs()));
953 DEBUG(dbgs() << "\n");
954
955 // Erase the old instructions.
956 LoadI->eraseFromParent();
957 return NextI;
958}
959
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]960/// trackRegDefsUses - Remember what registers the specified instruction uses
961/// and modifies.
Pete Cooper7be8f8f2015-08-03 19:04:32 +0000[diff] [blame]962static void trackRegDefsUses(const MachineInstr *MI, BitVector &ModifiedRegs,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]963 BitVector &UsedRegs,
964 const TargetRegisterInfo *TRI) {
Pete Cooper7be8f8f2015-08-03 19:04:32 +0000[diff] [blame]965 for (const MachineOperand &MO : MI->operands()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]966 if (MO.isRegMask())
967 ModifiedRegs.setBitsNotInMask(MO.getRegMask());
968
969 if (!MO.isReg())
970 continue;
971 unsigned Reg = MO.getReg();
972 if (MO.isDef()) {
973 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
974 ModifiedRegs.set(*AI);
975 } else {
976 assert(MO.isUse() && "Reg operand not a def and not a use?!?");
977 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
978 UsedRegs.set(*AI);
979 }
980 }
981}
982
983static bool inBoundsForPair(bool IsUnscaled, int Offset, int OffsetStride) {
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]984 // Convert the byte-offset used by unscaled into an "element" offset used
985 // by the scaled pair load/store instructions.
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame]986 if (IsUnscaled)
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]987 Offset /= OffsetStride;
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame]988
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]989 return Offset <= 63 && Offset >= -64;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]990}
991
992// Do alignment, specialized to power of 2 and for signed ints,
993// avoiding having to do a C-style cast from uint_64t to int when
Rui Ueyamada00f2f2016-01-14 21:06:47 +0000[diff] [blame]994// using alignTo from include/llvm/Support/MathExtras.h.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]995// FIXME: Move this function to include/MathExtras.h?
996static int alignTo(int Num, int PowOf2) {
997 return (Num + PowOf2 - 1) & ~(PowOf2 - 1);
998}
999
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1000static bool mayAlias(MachineInstr *MIa, MachineInstr *MIb,
1001 const AArch64InstrInfo *TII) {
1002 // One of the instructions must modify memory.
1003 if (!MIa->mayStore() && !MIb->mayStore())
1004 return false;
1005
1006 // Both instructions must be memory operations.
1007 if (!MIa->mayLoadOrStore() && !MIb->mayLoadOrStore())
1008 return false;
1009
1010 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb);
1011}
1012
1013static bool mayAlias(MachineInstr *MIa,
1014 SmallVectorImpl<MachineInstr *> &MemInsns,
1015 const AArch64InstrInfo *TII) {
1016 for (auto &MIb : MemInsns)
1017 if (mayAlias(MIa, MIb, TII))
1018 return true;
1019
1020 return false;
1021}
1022
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1023bool AArch64LoadStoreOpt::findMatchingStore(
1024 MachineBasicBlock::iterator I, unsigned Limit,
1025 MachineBasicBlock::iterator &StoreI) {
1026 MachineBasicBlock::iterator E = I->getParent()->begin();
1027 MachineBasicBlock::iterator MBBI = I;
1028 MachineInstr *FirstMI = I;
1029 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
1030
1031 // Track which registers have been modified and used between the first insn
1032 // and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1033 ModifiedRegs.reset();
1034 UsedRegs.reset();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1035
Chad Rosier1142f3c2016-02-02 15:22:55 +0000[diff] [blame]1036 // FIXME: We miss the case where the matching store is the first instruction
1037 // in the basic block.
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1038 for (unsigned Count = 0; MBBI != E && Count < Limit;) {
1039 --MBBI;
1040 MachineInstr *MI = MBBI;
1041 // Skip DBG_VALUE instructions. Otherwise debug info can affect the
1042 // optimization by changing how far we scan.
1043 if (MI->isDebugValue())
1044 continue;
1045 // Now that we know this is a real instruction, count it.
1046 ++Count;
1047
1048 // If the load instruction reads directly from the address to which the
1049 // store instruction writes and the stored value is not modified, we can
1050 // promote the load. Since we do not handle stores with pre-/post-index,
1051 // it's unnecessary to check if BaseReg is modified by the store itself.
1052 if (MI->mayStore() && isMatchingStore(FirstMI, MI) &&
1053 BaseReg == getLdStBaseOp(MI).getReg() &&
1054 isLdOffsetInRangeOfSt(FirstMI, MI) &&
1055 !ModifiedRegs[getLdStRegOp(MI).getReg()]) {
1056 StoreI = MBBI;
1057 return true;
1058 }
1059
1060 if (MI->isCall())
1061 return false;
1062
1063 // Update modified / uses register lists.
1064 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1065
1066 // Otherwise, if the base register is modified, we have no match, so
1067 // return early.
1068 if (ModifiedRegs[BaseReg])
1069 return false;
1070
1071 // If we encounter a store aliased with the load, return early.
1072 if (MI->mayStore() && mayAlias(FirstMI, MI, TII))
1073 return false;
1074 }
1075 return false;
1076}
1077
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1078/// findMatchingInsn - Scan the instructions looking for a load/store that can
1079/// be combined with the current instruction into a load/store pair.
1080MachineBasicBlock::iterator
1081AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1082 LdStPairFlags &Flags, unsigned Limit) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1083 MachineBasicBlock::iterator E = I->getParent()->end();
1084 MachineBasicBlock::iterator MBBI = I;
1085 MachineInstr *FirstMI = I;
1086 ++MBBI;
1087
Matthias Braunfa3872e2015-05-18 20:27:55 +0000[diff] [blame]1088 unsigned Opc = FirstMI->getOpcode();
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]1089 bool MayLoad = FirstMI->mayLoad();
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]1090 bool IsUnscaled = isUnscaledLdSt(FirstMI);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1091 unsigned Reg = getLdStRegOp(FirstMI).getReg();
1092 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
1093 int Offset = getLdStOffsetOp(FirstMI).getImm();
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1094 bool IsNarrowStore = isNarrowStore(Opc);
1095
1096 // For narrow stores, find only the case where the stored value is WZR.
1097 if (IsNarrowStore && Reg != AArch64::WZR)
1098 return E;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1099
1100 // Early exit if the first instruction modifies the base register.
1101 // e.g., ldr x0, [x0]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1102 if (FirstMI->modifiesRegister(BaseReg, TRI))
1103 return E;
Chad Rosiercaed6db2015-08-10 17:17:19 +0000[diff] [blame]1104
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame^]1105 // Early exit if the offset is not possible to match. (6 bits of positive
Chad Rosiercaed6db2015-08-10 17:17:19 +0000[diff] [blame]1106 // range, plus allow an extra one in case we find a later insn that matches
1107 // with Offset-1)
Chad Rosierf11d0402015-10-01 18:17:12 +0000[diff] [blame]1108 int OffsetStride = IsUnscaled ? getMemScale(FirstMI) : 1;
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1109 if (!(isNarrowLoad(Opc) || IsNarrowStore) &&
1110 !inBoundsForPair(IsUnscaled, Offset, OffsetStride))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1111 return E;
1112
1113 // Track which registers have been modified and used between the first insn
1114 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1115 ModifiedRegs.reset();
1116 UsedRegs.reset();
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1117
1118 // Remember any instructions that read/write memory between FirstMI and MI.
1119 SmallVector<MachineInstr *, 4> MemInsns;
1120
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1121 for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
1122 MachineInstr *MI = MBBI;
1123 // Skip DBG_VALUE instructions. Otherwise debug info can affect the
1124 // optimization by changing how far we scan.
1125 if (MI->isDebugValue())
1126 continue;
1127
1128 // Now that we know this is a real instruction, count it.
1129 ++Count;
1130
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame]1131 bool CanMergeOpc = Opc == MI->getOpcode();
Chad Rosier18896c02016-02-04 16:01:40 +0000[diff] [blame]1132 Flags.setSExtIdx(-1);
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame]1133 if (!CanMergeOpc) {
1134 bool IsValidLdStrOpc;
1135 unsigned NonSExtOpc = getMatchingNonSExtOpcode(Opc, &IsValidLdStrOpc);
1136 assert(IsValidLdStrOpc &&
1137 "Given Opc should be a Load or Store with an immediate");
1138 // Opc will be the first instruction in the pair.
1139 Flags.setSExtIdx(NonSExtOpc == (unsigned)Opc ? 1 : 0);
1140 CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode(MI->getOpcode());
1141 }
1142
1143 if (CanMergeOpc && getLdStOffsetOp(MI).isImm()) {
Chad Rosierc56a9132015-08-10 18:42:45 +0000[diff] [blame]1144 assert(MI->mayLoadOrStore() && "Expected memory operation.");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1145 // If we've found another instruction with the same opcode, check to see
1146 // if the base and offset are compatible with our starting instruction.
1147 // These instructions all have scaled immediate operands, so we just
1148 // check for +1/-1. Make sure to check the new instruction offset is
1149 // actually an immediate and not a symbolic reference destined for
1150 // a relocation.
1151 //
1152 // Pairwise instructions have a 7-bit signed offset field. Single insns
1153 // have a 12-bit unsigned offset field. To be a valid combine, the
1154 // final offset must be in range.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1155 unsigned MIBaseReg = getLdStBaseOp(MI).getReg();
1156 int MIOffset = getLdStOffsetOp(MI).getImm();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1157 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
1158 (Offset + OffsetStride == MIOffset))) {
1159 int MinOffset = Offset < MIOffset ? Offset : MIOffset;
1160 // If this is a volatile load/store that otherwise matched, stop looking
1161 // as something is going on that we don't have enough information to
1162 // safely transform. Similarly, stop if we see a hint to avoid pairs.
1163 if (MI->hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI))
1164 return E;
1165 // If the resultant immediate offset of merging these instructions
1166 // is out of range for a pairwise instruction, bail and keep looking.
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame]1167 bool MIIsUnscaled = isUnscaledLdSt(MI);
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1168 bool IsNarrowLoad = isNarrowLoad(MI->getOpcode());
1169 if (!IsNarrowLoad &&
Renato Golin6274e522016-02-05 12:14:30 +0000[diff] [blame]1170 !inBoundsForPair(MIIsUnscaled, MinOffset, OffsetStride)) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1171 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Chad Rosierc56a9132015-08-10 18:42:45 +0000[diff] [blame]1172 MemInsns.push_back(MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1173 continue;
1174 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1175
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1176 if (IsNarrowLoad || IsNarrowStore) {
1177 // If the alignment requirements of the scaled wide load/store
1178 // instruction can't express the offset of the scaled narrow
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1179 // input, bail and keep looking.
1180 if (!IsUnscaled && alignTo(MinOffset, 2) != MinOffset) {
1181 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1182 MemInsns.push_back(MI);
1183 continue;
1184 }
1185 } else {
1186 // If the alignment requirements of the paired (scaled) instruction
1187 // can't express the offset of the unscaled input, bail and keep
1188 // looking.
1189 if (IsUnscaled && (alignTo(MinOffset, OffsetStride) != MinOffset)) {
1190 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1191 MemInsns.push_back(MI);
1192 continue;
1193 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1194 }
1195 // If the destination register of the loads is the same register, bail
1196 // and keep looking. A load-pair instruction with both destination
1197 // registers the same is UNPREDICTABLE and will result in an exception.
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1198 // For narrow stores, allow only when the stored value is the same
1199 // (i.e., WZR).
1200 if ((MayLoad && Reg == getLdStRegOp(MI).getReg()) ||
1201 (IsNarrowStore && Reg != getLdStRegOp(MI).getReg())) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1202 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Chad Rosierc56a9132015-08-10 18:42:45 +0000[diff] [blame]1203 MemInsns.push_back(MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1204 continue;
1205 }
1206
1207 // If the Rt of the second instruction was not modified or used between
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1208 // the two instructions and none of the instructions between the second
1209 // and first alias with the second, we can combine the second into the
1210 // first.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1211 if (!ModifiedRegs[getLdStRegOp(MI).getReg()] &&
1212 !(MI->mayLoad() && UsedRegs[getLdStRegOp(MI).getReg()]) &&
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1213 !mayAlias(MI, MemInsns, TII)) {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]1214 Flags.setMergeForward(false);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1215 return MBBI;
1216 }
1217
1218 // Likewise, if the Rt of the first instruction is not modified or used
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1219 // between the two instructions and none of the instructions between the
1220 // first and the second alias with the first, we can combine the first
1221 // into the second.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1222 if (!ModifiedRegs[getLdStRegOp(FirstMI).getReg()] &&
Chad Rosier5f668e12015-09-03 14:19:43 +0000[diff] [blame]1223 !(MayLoad && UsedRegs[getLdStRegOp(FirstMI).getReg()]) &&
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1224 !mayAlias(FirstMI, MemInsns, TII)) {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]1225 Flags.setMergeForward(true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1226 return MBBI;
1227 }
1228 // Unable to combine these instructions due to interference in between.
1229 // Keep looking.
1230 }
1231 }
1232
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1233 // If the instruction wasn't a matching load or store. Stop searching if we
1234 // encounter a call instruction that might modify memory.
1235 if (MI->isCall())
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1236 return E;
1237
1238 // Update modified / uses register lists.
1239 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1240
1241 // Otherwise, if the base register is modified, we have no match, so
1242 // return early.
1243 if (ModifiedRegs[BaseReg])
1244 return E;
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1245
1246 // Update list of instructions that read/write memory.
1247 if (MI->mayLoadOrStore())
1248 MemInsns.push_back(MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1249 }
1250 return E;
1251}
1252
1253MachineBasicBlock::iterator
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1254AArch64LoadStoreOpt::mergeUpdateInsn(MachineBasicBlock::iterator I,
1255 MachineBasicBlock::iterator Update,
1256 bool IsPreIdx) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1257 assert((Update->getOpcode() == AArch64::ADDXri ||
1258 Update->getOpcode() == AArch64::SUBXri) &&
1259 "Unexpected base register update instruction to merge!");
1260 MachineBasicBlock::iterator NextI = I;
1261 // Return the instruction following the merged instruction, which is
1262 // the instruction following our unmerged load. Unless that's the add/sub
1263 // instruction we're merging, in which case it's the one after that.
1264 if (++NextI == Update)
1265 ++NextI;
1266
1267 int Value = Update->getOperand(2).getImm();
1268 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1269 "Can't merge 1 << 12 offset into pre-/post-indexed load / store");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1270 if (Update->getOpcode() == AArch64::SUBXri)
1271 Value = -Value;
1272
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1273 unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode(I->getOpcode())
1274 : getPostIndexedOpcode(I->getOpcode());
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1275 MachineInstrBuilder MIB;
1276 if (!isPairedLdSt(I)) {
1277 // Non-paired instruction.
1278 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1279 .addOperand(getLdStRegOp(Update))
1280 .addOperand(getLdStRegOp(I))
1281 .addOperand(getLdStBaseOp(I))
Chad Rosier3ada75f2016-01-28 15:38:24 +0000[diff] [blame]1282 .addImm(Value)
1283 .setMemRefs(I->memoperands_begin(), I->memoperands_end());
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1284 } else {
1285 // Paired instruction.
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]1286 int Scale = getMemScale(I);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1287 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1288 .addOperand(getLdStRegOp(Update))
1289 .addOperand(getLdStRegOp(I, 0))
1290 .addOperand(getLdStRegOp(I, 1))
1291 .addOperand(getLdStBaseOp(I))
Chad Rosier3ada75f2016-01-28 15:38:24 +0000[diff] [blame]1292 .addImm(Value / Scale)
1293 .setMemRefs(I->memoperands_begin(), I->memoperands_end());
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1294 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1295 (void)MIB;
1296
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1297 if (IsPreIdx)
1298 DEBUG(dbgs() << "Creating pre-indexed load/store.");
1299 else
1300 DEBUG(dbgs() << "Creating post-indexed load/store.");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1301 DEBUG(dbgs() << " Replacing instructions:\n ");
1302 DEBUG(I->print(dbgs()));
1303 DEBUG(dbgs() << " ");
1304 DEBUG(Update->print(dbgs()));
1305 DEBUG(dbgs() << " with instruction:\n ");
1306 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
1307 DEBUG(dbgs() << "\n");
1308
1309 // Erase the old instructions for the block.
1310 I->eraseFromParent();
1311 Update->eraseFromParent();
1312
1313 return NextI;
1314}
1315
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1316bool AArch64LoadStoreOpt::isMatchingUpdateInsn(MachineInstr *MemMI,
1317 MachineInstr *MI,
1318 unsigned BaseReg, int Offset) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1319 switch (MI->getOpcode()) {
1320 default:
1321 break;
1322 case AArch64::SUBXri:
1323 // Negate the offset for a SUB instruction.
1324 Offset *= -1;
1325 // FALLTHROUGH
1326 case AArch64::ADDXri:
1327 // Make sure it's a vanilla immediate operand, not a relocation or
1328 // anything else we can't handle.
1329 if (!MI->getOperand(2).isImm())
1330 break;
1331 // Watch out for 1 << 12 shifted value.
1332 if (AArch64_AM::getShiftValue(MI->getOperand(3).getImm()))
1333 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1334
1335 // The update instruction source and destination register must be the
1336 // same as the load/store base register.
1337 if (MI->getOperand(0).getReg() != BaseReg ||
1338 MI->getOperand(1).getReg() != BaseReg)
1339 break;
1340
1341 bool IsPairedInsn = isPairedLdSt(MemMI);
1342 int UpdateOffset = MI->getOperand(2).getImm();
1343 // For non-paired load/store instructions, the immediate must fit in a
1344 // signed 9-bit integer.
1345 if (!IsPairedInsn && (UpdateOffset > 255 || UpdateOffset < -256))
1346 break;
1347
1348 // For paired load/store instructions, the immediate must be a multiple of
1349 // the scaling factor. The scaled offset must also fit into a signed 7-bit
1350 // integer.
1351 if (IsPairedInsn) {
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]1352 int Scale = getMemScale(MemMI);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1353 if (UpdateOffset % Scale != 0)
1354 break;
1355
1356 int ScaledOffset = UpdateOffset / Scale;
1357 if (ScaledOffset > 64 || ScaledOffset < -64)
1358 break;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1359 }
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1360
1361 // If we have a non-zero Offset, we check that it matches the amount
1362 // we're adding to the register.
1363 if (!Offset || Offset == MI->getOperand(2).getImm())
1364 return true;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1365 break;
1366 }
1367 return false;
1368}
1369
1370MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1371 MachineBasicBlock::iterator I, int UnscaledOffset, unsigned Limit) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1372 MachineBasicBlock::iterator E = I->getParent()->end();
1373 MachineInstr *MemMI = I;
1374 MachineBasicBlock::iterator MBBI = I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1375
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1376 unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1377 int MIUnscaledOffset = getLdStOffsetOp(MemMI).getImm() * getMemScale(MemMI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1378
Chad Rosierb7c5b912015-10-01 13:43:05 +0000[diff] [blame]1379 // Scan forward looking for post-index opportunities. Updating instructions
1380 // can't be formed if the memory instruction doesn't have the offset we're
1381 // looking for.
1382 if (MIUnscaledOffset != UnscaledOffset)
1383 return E;
1384
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1385 // If the base register overlaps a destination register, we can't
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1386 // merge the update.
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1387 bool IsPairedInsn = isPairedLdSt(MemMI);
1388 for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
1389 unsigned DestReg = getLdStRegOp(MemMI, i).getReg();
1390 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
1391 return E;
1392 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1393
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1394 // Track which registers have been modified and used between the first insn
1395 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1396 ModifiedRegs.reset();
1397 UsedRegs.reset();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1398 ++MBBI;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1399 for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1400 MachineInstr *MI = MBBI;
Chad Rosierb11c82d2016-01-19 21:27:05 +0000[diff] [blame]1401 // Skip DBG_VALUE instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1402 if (MI->isDebugValue())
1403 continue;
1404
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1405 // Now that we know this is a real instruction, count it.
1406 ++Count;
1407
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1408 // If we found a match, return it.
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1409 if (isMatchingUpdateInsn(I, MI, BaseReg, UnscaledOffset))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1410 return MBBI;
1411
1412 // Update the status of what the instruction clobbered and used.
1413 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1414
1415 // Otherwise, if the base register is used or modified, we have no match, so
1416 // return early.
1417 if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
1418 return E;
1419 }
1420 return E;
1421}
1422
1423MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1424 MachineBasicBlock::iterator I, unsigned Limit) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1425 MachineBasicBlock::iterator B = I->getParent()->begin();
1426 MachineBasicBlock::iterator E = I->getParent()->end();
1427 MachineInstr *MemMI = I;
1428 MachineBasicBlock::iterator MBBI = I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1429
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1430 unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
1431 int Offset = getLdStOffsetOp(MemMI).getImm();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1432
1433 // If the load/store is the first instruction in the block, there's obviously
1434 // not any matching update. Ditto if the memory offset isn't zero.
1435 if (MBBI == B || Offset != 0)
1436 return E;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1437 // If the base register overlaps a destination register, we can't
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1438 // merge the update.
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1439 bool IsPairedInsn = isPairedLdSt(MemMI);
1440 for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
1441 unsigned DestReg = getLdStRegOp(MemMI, i).getReg();
1442 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
1443 return E;
1444 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1445
1446 // Track which registers have been modified and used between the first insn
1447 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1448 ModifiedRegs.reset();
1449 UsedRegs.reset();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1450 --MBBI;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1451 for (unsigned Count = 0; MBBI != B && Count < Limit; --MBBI) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1452 MachineInstr *MI = MBBI;
Chad Rosierb11c82d2016-01-19 21:27:05 +0000[diff] [blame]1453 // Skip DBG_VALUE instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1454 if (MI->isDebugValue())
1455 continue;
1456
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1457 // Now that we know this is a real instruction, count it.
1458 ++Count;
1459
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1460 // If we found a match, return it.
Chad Rosier11c825f2015-09-30 19:44:40 +0000[diff] [blame]1461 if (isMatchingUpdateInsn(I, MI, BaseReg, Offset))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1462 return MBBI;
1463
1464 // Update the status of what the instruction clobbered and used.
1465 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1466
1467 // Otherwise, if the base register is used or modified, we have no match, so
1468 // return early.
1469 if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
1470 return E;
1471 }
1472 return E;
1473}
1474
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1475bool AArch64LoadStoreOpt::tryToPromoteLoadFromStore(
1476 MachineBasicBlock::iterator &MBBI) {
1477 MachineInstr *MI = MBBI;
1478 // If this is a volatile load, don't mess with it.
1479 if (MI->hasOrderedMemoryRef())
1480 return false;
1481
1482 // Make sure this is a reg+imm.
1483 // FIXME: It is possible to extend it to handle reg+reg cases.
1484 if (!getLdStOffsetOp(MI).isImm())
1485 return false;
1486
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1487 // Look backward up to LdStLimit instructions.
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1488 MachineBasicBlock::iterator StoreI;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1489 if (findMatchingStore(MBBI, LdStLimit, StoreI)) {
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1490 ++NumLoadsFromStoresPromoted;
1491 // Promote the load. Keeping the iterator straight is a
1492 // pain, so we let the merge routine tell us what the next instruction
1493 // is after it's done mucking about.
1494 MBBI = promoteLoadFromStore(MBBI, StoreI);
1495 return true;
1496 }
1497 return false;
1498}
1499
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1500bool AArch64LoadStoreOpt::tryToMergeLdStInst(
1501 MachineBasicBlock::iterator &MBBI) {
1502 MachineInstr *MI = MBBI;
1503 MachineBasicBlock::iterator E = MI->getParent()->end();
1504 // If this is a volatile load/store, don't mess with it.
1505 if (MI->hasOrderedMemoryRef())
1506 return false;
1507
1508 // Make sure this is a reg+imm (as opposed to an address reloc).
1509 if (!getLdStOffsetOp(MI).isImm())
1510 return false;
1511
1512 // Check if this load/store has a hint to avoid pair formation.
1513 // MachineMemOperands hints are set by the AArch64StorePairSuppress pass.
1514 if (TII->isLdStPairSuppressed(MI))
1515 return false;
1516
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1517 // Look ahead up to LdStLimit instructions for a pairable instruction.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1518 LdStPairFlags Flags;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1519 MachineBasicBlock::iterator Paired = findMatchingInsn(MBBI, Flags, LdStLimit);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1520 if (Paired != E) {
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1521 if (isNarrowLoad(MI)) {
1522 ++NumNarrowLoadsPromoted;
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1523 } else if (isNarrowStore(MI)) {
1524 ++NumZeroStoresPromoted;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1525 } else {
1526 ++NumPairCreated;
1527 if (isUnscaledLdSt(MI))
1528 ++NumUnscaledPairCreated;
1529 }
1530
1531 // Merge the loads into a pair. Keeping the iterator straight is a
1532 // pain, so we let the merge routine tell us what the next instruction
1533 // is after it's done mucking about.
1534 MBBI = mergePairedInsns(MBBI, Paired, Flags);
1535 return true;
1536 }
1537 return false;
1538}
1539
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1540bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
1541 bool enableNarrowLdOpt) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1542 bool Modified = false;
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1543 // Four tranformations to do here:
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1544 // 1) Find loads that directly read from stores and promote them by
1545 // replacing with mov instructions. If the store is wider than the load,
1546 // the load will be replaced with a bitfield extract.
1547 // e.g.,
1548 // str w1, [x0, #4]
1549 // ldrh w2, [x0, #6]
1550 // ; becomes
1551 // str w1, [x0, #4]
1552 // lsr w2, w1, #16
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1553 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1554 MBBI != E;) {
1555 MachineInstr *MI = MBBI;
1556 switch (MI->getOpcode()) {
1557 default:
1558 // Just move on to the next instruction.
1559 ++MBBI;
1560 break;
1561 // Scaled instructions.
1562 case AArch64::LDRBBui:
1563 case AArch64::LDRHHui:
1564 case AArch64::LDRWui:
1565 case AArch64::LDRXui:
1566 // Unscaled instructions.
1567 case AArch64::LDURBBi:
1568 case AArch64::LDURHHi:
1569 case AArch64::LDURWi:
1570 case AArch64::LDURXi: {
1571 if (tryToPromoteLoadFromStore(MBBI)) {
1572 Modified = true;
1573 break;
1574 }
1575 ++MBBI;
1576 break;
1577 }
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1578 }
1579 }
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1580 // 2) Find narrow loads that can be converted into a single wider load
1581 // with bitfield extract instructions.
1582 // e.g.,
1583 // ldrh w0, [x2]
1584 // ldrh w1, [x2, #2]
1585 // ; becomes
1586 // ldr w0, [x2]
1587 // ubfx w1, w0, #16, #16
1588 // and w0, w0, #ffff
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame^]1589 //
1590 // Also merge adjacent zero stores into a wider store.
1591 // e.g.,
1592 // strh wzr, [x0]
1593 // strh wzr, [x0, #2]
1594 // ; becomes
1595 // str wzr, [x0]
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1596 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1597 enableNarrowLdOpt && MBBI != E;) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1598 MachineInstr *MI = MBBI;
1599 switch (MI->getOpcode()) {
1600 default:
1601 // Just move on to the next instruction.
1602 ++MBBI;
1603 break;
1604 // Scaled instructions.
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]1605 case AArch64::LDRBBui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1606 case AArch64::LDRHHui:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]1607 case AArch64::LDRSBWui:
1608 case AArch64::LDRSHWui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1609 case AArch64::STRBBui:
1610 case AArch64::STRHHui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1611 // Unscaled instructions.
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]1612 case AArch64::LDURBBi:
1613 case AArch64::LDURHHi:
1614 case AArch64::LDURSBWi:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1615 case AArch64::LDURSHWi:
1616 case AArch64::STURBBi:
1617 case AArch64::STURHHi: {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1618 if (tryToMergeLdStInst(MBBI)) {
1619 Modified = true;
1620 break;
1621 }
1622 ++MBBI;
1623 break;
1624 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1625 }
1626 }
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1627 // 3) Find loads and stores that can be merged into a single load or store
1628 // pair instruction.
1629 // e.g.,
1630 // ldr x0, [x2]
1631 // ldr x1, [x2, #8]
1632 // ; becomes
1633 // ldp x0, x1, [x2]
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1634 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1635 MBBI != E;) {
1636 MachineInstr *MI = MBBI;
1637 switch (MI->getOpcode()) {
1638 default:
1639 // Just move on to the next instruction.
1640 ++MBBI;
1641 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1642 // Scaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1643 case AArch64::STRSui:
1644 case AArch64::STRDui:
1645 case AArch64::STRQui:
1646 case AArch64::STRXui:
1647 case AArch64::STRWui:
1648 case AArch64::LDRSui:
1649 case AArch64::LDRDui:
1650 case AArch64::LDRQui:
1651 case AArch64::LDRXui:
1652 case AArch64::LDRWui:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]1653 case AArch64::LDRSWui:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1654 // Unscaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1655 case AArch64::STURSi:
1656 case AArch64::STURDi:
1657 case AArch64::STURQi:
1658 case AArch64::STURWi:
1659 case AArch64::STURXi:
1660 case AArch64::LDURSi:
1661 case AArch64::LDURDi:
1662 case AArch64::LDURQi:
1663 case AArch64::LDURWi:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]1664 case AArch64::LDURXi:
1665 case AArch64::LDURSWi: {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1666 if (tryToMergeLdStInst(MBBI)) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1667 Modified = true;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1668 break;
1669 }
1670 ++MBBI;
1671 break;
1672 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1673 }
1674 }
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1675 // 4) Find base register updates that can be merged into the load or store
1676 // as a base-reg writeback.
1677 // e.g.,
1678 // ldr x0, [x2]
1679 // add x2, x2, #4
1680 // ; becomes
1681 // ldr x0, [x2], #4
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1682 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1683 MBBI != E;) {
1684 MachineInstr *MI = MBBI;
1685 // Do update merging. It's simpler to keep this separate from the above
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1686 // switchs, though not strictly necessary.
Matthias Braunfa3872e2015-05-18 20:27:55 +0000[diff] [blame]1687 unsigned Opc = MI->getOpcode();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1688 switch (Opc) {
1689 default:
1690 // Just move on to the next instruction.
1691 ++MBBI;
1692 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1693 // Scaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1694 case AArch64::STRSui:
1695 case AArch64::STRDui:
1696 case AArch64::STRQui:
1697 case AArch64::STRXui:
1698 case AArch64::STRWui:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]1699 case AArch64::STRHHui:
1700 case AArch64::STRBBui:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1701 case AArch64::LDRSui:
1702 case AArch64::LDRDui:
1703 case AArch64::LDRQui:
1704 case AArch64::LDRXui:
1705 case AArch64::LDRWui:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]1706 case AArch64::LDRHHui:
1707 case AArch64::LDRBBui:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1708 // Unscaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1709 case AArch64::STURSi:
1710 case AArch64::STURDi:
1711 case AArch64::STURQi:
1712 case AArch64::STURWi:
1713 case AArch64::STURXi:
1714 case AArch64::LDURSi:
1715 case AArch64::LDURDi:
1716 case AArch64::LDURQi:
1717 case AArch64::LDURWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1718 case AArch64::LDURXi:
1719 // Paired instructions.
1720 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]1721 case AArch64::LDPSWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1722 case AArch64::LDPDi:
1723 case AArch64::LDPQi:
1724 case AArch64::LDPWi:
1725 case AArch64::LDPXi:
1726 case AArch64::STPSi:
1727 case AArch64::STPDi:
1728 case AArch64::STPQi:
1729 case AArch64::STPWi:
1730 case AArch64::STPXi: {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1731 // Make sure this is a reg+imm (as opposed to an address reloc).
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1732 if (!getLdStOffsetOp(MI).isImm()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1733 ++MBBI;
1734 break;
1735 }
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1736 // Look forward to try to form a post-index instruction. For example,
1737 // ldr x0, [x20]
1738 // add x20, x20, #32
1739 // merged into:
1740 // ldr x0, [x20], #32
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1741 MachineBasicBlock::iterator Update =
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1742 findMatchingUpdateInsnForward(MBBI, 0, UpdateLimit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1743 if (Update != E) {
1744 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1745 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/false);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1746 Modified = true;
1747 ++NumPostFolded;
1748 break;
1749 }
1750 // Don't know how to handle pre/post-index versions, so move to the next
1751 // instruction.
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]1752 if (isUnscaledLdSt(Opc)) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1753 ++MBBI;
1754 break;
1755 }
1756
1757 // Look back to try to find a pre-index instruction. For example,
1758 // add x0, x0, #8
1759 // ldr x1, [x0]
1760 // merged into:
1761 // ldr x1, [x0, #8]!
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1762 Update = findMatchingUpdateInsnBackward(MBBI, UpdateLimit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1763 if (Update != E) {
1764 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1765 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1766 Modified = true;
1767 ++NumPreFolded;
1768 break;
1769 }
Chad Rosier7a83d772015-10-01 13:09:44 +0000[diff] [blame]1770 // The immediate in the load/store is scaled by the size of the memory
1771 // operation. The immediate in the add we're looking for,
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1772 // however, is not, so adjust here.
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1773 int UnscaledOffset = getLdStOffsetOp(MI).getImm() * getMemScale(MI);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1774
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1775 // Look forward to try to find a post-index instruction. For example,
1776 // ldr x1, [x0, #64]
1777 // add x0, x0, #64
1778 // merged into:
1779 // ldr x1, [x0, #64]!
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1780 Update = findMatchingUpdateInsnForward(MBBI, UnscaledOffset, UpdateLimit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1781 if (Update != E) {
1782 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1783 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1784 Modified = true;
1785 ++NumPreFolded;
1786 break;
1787 }
1788
1789 // Nothing found. Just move to the next instruction.
1790 ++MBBI;
1791 break;
1792 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1793 }
1794 }
1795
1796 return Modified;
1797}
1798
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1799bool AArch64LoadStoreOpt::enableNarrowLdMerge(MachineFunction &Fn) {
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1800 bool ProfitableArch = Subtarget->isCortexA57();
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1801 // FIXME: The benefit from converting narrow loads into a wider load could be
1802 // microarchitectural as it assumes that a single load with two bitfield
1803 // extracts is cheaper than two narrow loads. Currently, this conversion is
1804 // enabled only in cortex-a57 on which performance benefits were verified.
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1805 return ProfitableArch && !Subtarget->requiresStrictAlign();
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1806}
1807
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1808bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]1809 Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
1810 TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
1811 TRI = Subtarget->getRegisterInfo();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1812
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1813 // Resize the modified and used register bitfield trackers. We do this once
1814 // per function and then clear the bitfield each time we optimize a load or
1815 // store.
1816 ModifiedRegs.resize(TRI->getNumRegs());
1817 UsedRegs.resize(TRI->getNumRegs());
1818
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1819 bool Modified = false;
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1820 bool enableNarrowLdOpt = enableNarrowLdMerge(Fn);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1821 for (auto &MBB : Fn)
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1822 Modified |= optimizeBlock(MBB, enableNarrowLdOpt);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1823
1824 return Modified;
1825}
1826
1827// FIXME: Do we need/want a pre-alloc pass like ARM has to try to keep
1828// loads and stores near one another?
1829
Chad Rosier43f5c842015-08-05 12:40:13 +0000[diff] [blame]1830/// createAArch64LoadStoreOptimizationPass - returns an instance of the
1831/// load / store optimization pass.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1832FunctionPass *llvm::createAArch64LoadStoreOptimizationPass() {
1833 return new AArch64LoadStoreOpt();
1834}