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gerrit-public.fairphone.software / toolchain / llvm-project / 6506a90a703ba1c034602b07cce81f633aebf9e4 / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: 3fc6bbc123fdd40219ed30cb83677cd74a9d60f9 [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]17#include "llvm/ADT/StringExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]18#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]19#include "llvm/CodeGen/Analysis.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]22#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]23#include "llvm/CodeGen/MachineJumpTableInfo.h"
Matthias Braun744c2152017-04-28 20:25:05 +0000[diff] [blame]24#include "llvm/CodeGen/MachineRegisterInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]25#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]26#include "llvm/IR/DataLayout.h"
27#include "llvm/IR/DerivedTypes.h"
28#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]29#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]30#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]31#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]32#include "llvm/MC/MCExpr.h"
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]33#include "llvm/Support/BranchProbability.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/MathExtras.h"
37#include "llvm/Target/TargetLoweringObjectFile.h"
38#include "llvm/Target/TargetMachine.h"
39#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]40#include "llvm/Target/TargetSubtargetInfo.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]41#include <cctype>
42using namespace llvm;
43
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]44static cl::opt<bool> JumpIsExpensiveOverride(
45 "jump-is-expensive", cl::init(false),
46 cl::desc("Do not create extra branches to split comparison logic."),
47 cl::Hidden);
48
Evandro Menezeseb97e352016-10-25 19:53:51 +0000[diff] [blame]49static cl::opt<unsigned> MinimumJumpTableEntries
50 ("min-jump-table-entries", cl::init(4), cl::Hidden,
51 cl::desc("Set minimum number of entries to use a jump table."));
52
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]53static cl::opt<unsigned> MaximumJumpTableSize
Evandro Menezeseb97e352016-10-25 19:53:51 +0000[diff] [blame]54 ("max-jump-table-size", cl::init(0), cl::Hidden,
55 cl::desc("Set maximum size of jump tables; zero for no limit."));
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]56
Jun Bum Lim919f9e82017-04-28 16:04:03 +0000[diff] [blame]57/// Minimum jump table density for normal functions.
58static cl::opt<unsigned>
59 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
60 cl::desc("Minimum density for building a jump table in "
61 "a normal function"));
62
63/// Minimum jump table density for -Os or -Oz functions.
64static cl::opt<unsigned> OptsizeJumpTableDensity(
65 "optsize-jump-table-density", cl::init(40), cl::Hidden,
66 cl::desc("Minimum density for building a jump table in "
67 "an optsize function"));
68
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]69// Although this default value is arbitrary, it is not random. It is assumed
70// that a condition that evaluates the same way by a higher percentage than this
71// is best represented as control flow. Therefore, the default value N should be
72// set such that the win from N% correct executions is greater than the loss
73// from (100 - N)% mispredicted executions for the majority of intended targets.
74static cl::opt<int> MinPercentageForPredictableBranch(
75 "min-predictable-branch", cl::init(99),
76 cl::desc("Minimum percentage (0-100) that a condition must be either true "
77 "or false to assume that the condition is predictable"),
78 cl::Hidden);
79
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]80/// InitLibcallNames - Set default libcall names.
81///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]82static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]83 Names[RTLIB::SHL_I16] = "__ashlhi3";
84 Names[RTLIB::SHL_I32] = "__ashlsi3";
85 Names[RTLIB::SHL_I64] = "__ashldi3";
86 Names[RTLIB::SHL_I128] = "__ashlti3";
87 Names[RTLIB::SRL_I16] = "__lshrhi3";
88 Names[RTLIB::SRL_I32] = "__lshrsi3";
89 Names[RTLIB::SRL_I64] = "__lshrdi3";
90 Names[RTLIB::SRL_I128] = "__lshrti3";
91 Names[RTLIB::SRA_I16] = "__ashrhi3";
92 Names[RTLIB::SRA_I32] = "__ashrsi3";
93 Names[RTLIB::SRA_I64] = "__ashrdi3";
94 Names[RTLIB::SRA_I128] = "__ashrti3";
95 Names[RTLIB::MUL_I8] = "__mulqi3";
96 Names[RTLIB::MUL_I16] = "__mulhi3";
97 Names[RTLIB::MUL_I32] = "__mulsi3";
98 Names[RTLIB::MUL_I64] = "__muldi3";
99 Names[RTLIB::MUL_I128] = "__multi3";
100 Names[RTLIB::MULO_I32] = "__mulosi4";
101 Names[RTLIB::MULO_I64] = "__mulodi4";
102 Names[RTLIB::MULO_I128] = "__muloti4";
103 Names[RTLIB::SDIV_I8] = "__divqi3";
104 Names[RTLIB::SDIV_I16] = "__divhi3";
105 Names[RTLIB::SDIV_I32] = "__divsi3";
106 Names[RTLIB::SDIV_I64] = "__divdi3";
107 Names[RTLIB::SDIV_I128] = "__divti3";
108 Names[RTLIB::UDIV_I8] = "__udivqi3";
109 Names[RTLIB::UDIV_I16] = "__udivhi3";
110 Names[RTLIB::UDIV_I32] = "__udivsi3";
111 Names[RTLIB::UDIV_I64] = "__udivdi3";
112 Names[RTLIB::UDIV_I128] = "__udivti3";
113 Names[RTLIB::SREM_I8] = "__modqi3";
114 Names[RTLIB::SREM_I16] = "__modhi3";
115 Names[RTLIB::SREM_I32] = "__modsi3";
116 Names[RTLIB::SREM_I64] = "__moddi3";
117 Names[RTLIB::SREM_I128] = "__modti3";
118 Names[RTLIB::UREM_I8] = "__umodqi3";
119 Names[RTLIB::UREM_I16] = "__umodhi3";
120 Names[RTLIB::UREM_I32] = "__umodsi3";
121 Names[RTLIB::UREM_I64] = "__umoddi3";
122 Names[RTLIB::UREM_I128] = "__umodti3";
123
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]124 Names[RTLIB::NEG_I32] = "__negsi2";
125 Names[RTLIB::NEG_I64] = "__negdi2";
126 Names[RTLIB::ADD_F32] = "__addsf3";
127 Names[RTLIB::ADD_F64] = "__adddf3";
128 Names[RTLIB::ADD_F80] = "__addxf3";
129 Names[RTLIB::ADD_F128] = "__addtf3";
130 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
131 Names[RTLIB::SUB_F32] = "__subsf3";
132 Names[RTLIB::SUB_F64] = "__subdf3";
133 Names[RTLIB::SUB_F80] = "__subxf3";
134 Names[RTLIB::SUB_F128] = "__subtf3";
135 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
136 Names[RTLIB::MUL_F32] = "__mulsf3";
137 Names[RTLIB::MUL_F64] = "__muldf3";
138 Names[RTLIB::MUL_F80] = "__mulxf3";
139 Names[RTLIB::MUL_F128] = "__multf3";
140 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
141 Names[RTLIB::DIV_F32] = "__divsf3";
142 Names[RTLIB::DIV_F64] = "__divdf3";
143 Names[RTLIB::DIV_F80] = "__divxf3";
144 Names[RTLIB::DIV_F128] = "__divtf3";
145 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
146 Names[RTLIB::REM_F32] = "fmodf";
147 Names[RTLIB::REM_F64] = "fmod";
148 Names[RTLIB::REM_F80] = "fmodl";
149 Names[RTLIB::REM_F128] = "fmodl";
150 Names[RTLIB::REM_PPCF128] = "fmodl";
151 Names[RTLIB::FMA_F32] = "fmaf";
152 Names[RTLIB::FMA_F64] = "fma";
153 Names[RTLIB::FMA_F80] = "fmal";
154 Names[RTLIB::FMA_F128] = "fmal";
155 Names[RTLIB::FMA_PPCF128] = "fmal";
156 Names[RTLIB::POWI_F32] = "__powisf2";
157 Names[RTLIB::POWI_F64] = "__powidf2";
158 Names[RTLIB::POWI_F80] = "__powixf2";
159 Names[RTLIB::POWI_F128] = "__powitf2";
160 Names[RTLIB::POWI_PPCF128] = "__powitf2";
161 Names[RTLIB::SQRT_F32] = "sqrtf";
162 Names[RTLIB::SQRT_F64] = "sqrt";
163 Names[RTLIB::SQRT_F80] = "sqrtl";
164 Names[RTLIB::SQRT_F128] = "sqrtl";
165 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
166 Names[RTLIB::LOG_F32] = "logf";
167 Names[RTLIB::LOG_F64] = "log";
168 Names[RTLIB::LOG_F80] = "logl";
169 Names[RTLIB::LOG_F128] = "logl";
170 Names[RTLIB::LOG_PPCF128] = "logl";
171 Names[RTLIB::LOG2_F32] = "log2f";
172 Names[RTLIB::LOG2_F64] = "log2";
173 Names[RTLIB::LOG2_F80] = "log2l";
174 Names[RTLIB::LOG2_F128] = "log2l";
175 Names[RTLIB::LOG2_PPCF128] = "log2l";
176 Names[RTLIB::LOG10_F32] = "log10f";
177 Names[RTLIB::LOG10_F64] = "log10";
178 Names[RTLIB::LOG10_F80] = "log10l";
179 Names[RTLIB::LOG10_F128] = "log10l";
180 Names[RTLIB::LOG10_PPCF128] = "log10l";
181 Names[RTLIB::EXP_F32] = "expf";
182 Names[RTLIB::EXP_F64] = "exp";
183 Names[RTLIB::EXP_F80] = "expl";
184 Names[RTLIB::EXP_F128] = "expl";
185 Names[RTLIB::EXP_PPCF128] = "expl";
186 Names[RTLIB::EXP2_F32] = "exp2f";
187 Names[RTLIB::EXP2_F64] = "exp2";
188 Names[RTLIB::EXP2_F80] = "exp2l";
189 Names[RTLIB::EXP2_F128] = "exp2l";
190 Names[RTLIB::EXP2_PPCF128] = "exp2l";
191 Names[RTLIB::SIN_F32] = "sinf";
192 Names[RTLIB::SIN_F64] = "sin";
193 Names[RTLIB::SIN_F80] = "sinl";
194 Names[RTLIB::SIN_F128] = "sinl";
195 Names[RTLIB::SIN_PPCF128] = "sinl";
196 Names[RTLIB::COS_F32] = "cosf";
197 Names[RTLIB::COS_F64] = "cos";
198 Names[RTLIB::COS_F80] = "cosl";
199 Names[RTLIB::COS_F128] = "cosl";
200 Names[RTLIB::COS_PPCF128] = "cosl";
201 Names[RTLIB::POW_F32] = "powf";
202 Names[RTLIB::POW_F64] = "pow";
203 Names[RTLIB::POW_F80] = "powl";
204 Names[RTLIB::POW_F128] = "powl";
205 Names[RTLIB::POW_PPCF128] = "powl";
206 Names[RTLIB::CEIL_F32] = "ceilf";
207 Names[RTLIB::CEIL_F64] = "ceil";
208 Names[RTLIB::CEIL_F80] = "ceill";
209 Names[RTLIB::CEIL_F128] = "ceill";
210 Names[RTLIB::CEIL_PPCF128] = "ceill";
211 Names[RTLIB::TRUNC_F32] = "truncf";
212 Names[RTLIB::TRUNC_F64] = "trunc";
213 Names[RTLIB::TRUNC_F80] = "truncl";
214 Names[RTLIB::TRUNC_F128] = "truncl";
215 Names[RTLIB::TRUNC_PPCF128] = "truncl";
216 Names[RTLIB::RINT_F32] = "rintf";
217 Names[RTLIB::RINT_F64] = "rint";
218 Names[RTLIB::RINT_F80] = "rintl";
219 Names[RTLIB::RINT_F128] = "rintl";
220 Names[RTLIB::RINT_PPCF128] = "rintl";
221 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
222 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
223 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
224 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
225 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]226 Names[RTLIB::ROUND_F32] = "roundf";
227 Names[RTLIB::ROUND_F64] = "round";
228 Names[RTLIB::ROUND_F80] = "roundl";
229 Names[RTLIB::ROUND_F128] = "roundl";
230 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]231 Names[RTLIB::FLOOR_F32] = "floorf";
232 Names[RTLIB::FLOOR_F64] = "floor";
233 Names[RTLIB::FLOOR_F80] = "floorl";
234 Names[RTLIB::FLOOR_F128] = "floorl";
235 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]236 Names[RTLIB::FMIN_F32] = "fminf";
237 Names[RTLIB::FMIN_F64] = "fmin";
238 Names[RTLIB::FMIN_F80] = "fminl";
239 Names[RTLIB::FMIN_F128] = "fminl";
240 Names[RTLIB::FMIN_PPCF128] = "fminl";
241 Names[RTLIB::FMAX_F32] = "fmaxf";
242 Names[RTLIB::FMAX_F64] = "fmax";
243 Names[RTLIB::FMAX_F80] = "fmaxl";
244 Names[RTLIB::FMAX_F128] = "fmaxl";
245 Names[RTLIB::FMAX_PPCF128] = "fmaxl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]246 Names[RTLIB::ROUND_F32] = "roundf";
247 Names[RTLIB::ROUND_F64] = "round";
248 Names[RTLIB::ROUND_F80] = "roundl";
249 Names[RTLIB::ROUND_F128] = "roundl";
250 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]251 Names[RTLIB::COPYSIGN_F32] = "copysignf";
252 Names[RTLIB::COPYSIGN_F64] = "copysign";
253 Names[RTLIB::COPYSIGN_F80] = "copysignl";
254 Names[RTLIB::COPYSIGN_F128] = "copysignl";
255 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]256 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq";
257 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]258 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
259 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
260 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
James Y Knight7873fb92016-04-12 22:32:47 +0000[diff] [blame]261 if (TT.isOSDarwin()) {
262 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
263 // of the gnueabi-style __gnu_*_ieee.
264 // FIXME: What about other targets?
265 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2";
266 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2";
267 } else {
268 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
269 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
270 }
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]271 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
272 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
273 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
274 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]275 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
276 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
277 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]278 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]279 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
280 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]281 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]282 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
283 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
284 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]285 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
286 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
287 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
288 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
289 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
290 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
291 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
292 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
293 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]294 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]295 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
296 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]297 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
298 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
299 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]300 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
301 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
302 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
303 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
304 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
305 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
306 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
307 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
308 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
309 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
310 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
311 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
312 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
313 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
314 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
315 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]316 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]317 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
318 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
319 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
320 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
321 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
322 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
323 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
324 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
325 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
326 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
327 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
328 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
329 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
330 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]331 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]332 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
333 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
334 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
335 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
336 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
337 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
338 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
339 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
340 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
341 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
342 Names[RTLIB::OEQ_F32] = "__eqsf2";
343 Names[RTLIB::OEQ_F64] = "__eqdf2";
344 Names[RTLIB::OEQ_F128] = "__eqtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]345 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]346 Names[RTLIB::UNE_F32] = "__nesf2";
347 Names[RTLIB::UNE_F64] = "__nedf2";
348 Names[RTLIB::UNE_F128] = "__netf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]349 Names[RTLIB::UNE_PPCF128] = "__gcc_qne";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]350 Names[RTLIB::OGE_F32] = "__gesf2";
351 Names[RTLIB::OGE_F64] = "__gedf2";
352 Names[RTLIB::OGE_F128] = "__getf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]353 Names[RTLIB::OGE_PPCF128] = "__gcc_qge";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]354 Names[RTLIB::OLT_F32] = "__ltsf2";
355 Names[RTLIB::OLT_F64] = "__ltdf2";
356 Names[RTLIB::OLT_F128] = "__lttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]357 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]358 Names[RTLIB::OLE_F32] = "__lesf2";
359 Names[RTLIB::OLE_F64] = "__ledf2";
360 Names[RTLIB::OLE_F128] = "__letf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]361 Names[RTLIB::OLE_PPCF128] = "__gcc_qle";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]362 Names[RTLIB::OGT_F32] = "__gtsf2";
363 Names[RTLIB::OGT_F64] = "__gtdf2";
364 Names[RTLIB::OGT_F128] = "__gttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]365 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]366 Names[RTLIB::UO_F32] = "__unordsf2";
367 Names[RTLIB::UO_F64] = "__unorddf2";
368 Names[RTLIB::UO_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]369 Names[RTLIB::UO_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]370 Names[RTLIB::O_F32] = "__unordsf2";
371 Names[RTLIB::O_F64] = "__unorddf2";
372 Names[RTLIB::O_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]373 Names[RTLIB::O_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]374 Names[RTLIB::MEMCPY] = "memcpy";
375 Names[RTLIB::MEMMOVE] = "memmove";
376 Names[RTLIB::MEMSET] = "memset";
Igor Laevsky4f31e522016-12-29 14:31:07 +0000[diff] [blame]377 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_1] = "__llvm_memcpy_element_atomic_1";
378 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_2] = "__llvm_memcpy_element_atomic_2";
379 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_4] = "__llvm_memcpy_element_atomic_4";
380 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_8] = "__llvm_memcpy_element_atomic_8";
381 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_16] = "__llvm_memcpy_element_atomic_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]382 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
383 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
384 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
385 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
386 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]387 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]388 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
389 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
390 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
391 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]392 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]393 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
394 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
395 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
396 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]397 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]398 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
399 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
400 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
401 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]402 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]403 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
404 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
405 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
406 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]407 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]408 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
409 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
410 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
411 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]412 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]413 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
414 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
415 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
416 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]417 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]418 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
419 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
420 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
421 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]422 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]423 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
424 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
425 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
426 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
427 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
428 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
429 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
430 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
431 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
432 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
433 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
434 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
435 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
436 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
437 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
438 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
439 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
440 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
441 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
442 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
James Y Knight19f6cce2016-04-12 20:18:48 +0000[diff] [blame]443
444 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load";
445 Names[RTLIB::ATOMIC_LOAD_1] = "__atomic_load_1";
446 Names[RTLIB::ATOMIC_LOAD_2] = "__atomic_load_2";
447 Names[RTLIB::ATOMIC_LOAD_4] = "__atomic_load_4";
448 Names[RTLIB::ATOMIC_LOAD_8] = "__atomic_load_8";
449 Names[RTLIB::ATOMIC_LOAD_16] = "__atomic_load_16";
450
451 Names[RTLIB::ATOMIC_STORE] = "__atomic_store";
452 Names[RTLIB::ATOMIC_STORE_1] = "__atomic_store_1";
453 Names[RTLIB::ATOMIC_STORE_2] = "__atomic_store_2";
454 Names[RTLIB::ATOMIC_STORE_4] = "__atomic_store_4";
455 Names[RTLIB::ATOMIC_STORE_8] = "__atomic_store_8";
456 Names[RTLIB::ATOMIC_STORE_16] = "__atomic_store_16";
457
458 Names[RTLIB::ATOMIC_EXCHANGE] = "__atomic_exchange";
459 Names[RTLIB::ATOMIC_EXCHANGE_1] = "__atomic_exchange_1";
460 Names[RTLIB::ATOMIC_EXCHANGE_2] = "__atomic_exchange_2";
461 Names[RTLIB::ATOMIC_EXCHANGE_4] = "__atomic_exchange_4";
462 Names[RTLIB::ATOMIC_EXCHANGE_8] = "__atomic_exchange_8";
463 Names[RTLIB::ATOMIC_EXCHANGE_16] = "__atomic_exchange_16";
464
465 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE] = "__atomic_compare_exchange";
466 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_1] = "__atomic_compare_exchange_1";
467 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_2] = "__atomic_compare_exchange_2";
468 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_4] = "__atomic_compare_exchange_4";
469 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_8] = "__atomic_compare_exchange_8";
470 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_16] = "__atomic_compare_exchange_16";
471
472 Names[RTLIB::ATOMIC_FETCH_ADD_1] = "__atomic_fetch_add_1";
473 Names[RTLIB::ATOMIC_FETCH_ADD_2] = "__atomic_fetch_add_2";
474 Names[RTLIB::ATOMIC_FETCH_ADD_4] = "__atomic_fetch_add_4";
475 Names[RTLIB::ATOMIC_FETCH_ADD_8] = "__atomic_fetch_add_8";
476 Names[RTLIB::ATOMIC_FETCH_ADD_16] = "__atomic_fetch_add_16";
477 Names[RTLIB::ATOMIC_FETCH_SUB_1] = "__atomic_fetch_sub_1";
478 Names[RTLIB::ATOMIC_FETCH_SUB_2] = "__atomic_fetch_sub_2";
479 Names[RTLIB::ATOMIC_FETCH_SUB_4] = "__atomic_fetch_sub_4";
480 Names[RTLIB::ATOMIC_FETCH_SUB_8] = "__atomic_fetch_sub_8";
481 Names[RTLIB::ATOMIC_FETCH_SUB_16] = "__atomic_fetch_sub_16";
482 Names[RTLIB::ATOMIC_FETCH_AND_1] = "__atomic_fetch_and_1";
483 Names[RTLIB::ATOMIC_FETCH_AND_2] = "__atomic_fetch_and_2";
484 Names[RTLIB::ATOMIC_FETCH_AND_4] = "__atomic_fetch_and_4";
485 Names[RTLIB::ATOMIC_FETCH_AND_8] = "__atomic_fetch_and_8";
486 Names[RTLIB::ATOMIC_FETCH_AND_16] = "__atomic_fetch_and_16";
487 Names[RTLIB::ATOMIC_FETCH_OR_1] = "__atomic_fetch_or_1";
488 Names[RTLIB::ATOMIC_FETCH_OR_2] = "__atomic_fetch_or_2";
489 Names[RTLIB::ATOMIC_FETCH_OR_4] = "__atomic_fetch_or_4";
490 Names[RTLIB::ATOMIC_FETCH_OR_8] = "__atomic_fetch_or_8";
491 Names[RTLIB::ATOMIC_FETCH_OR_16] = "__atomic_fetch_or_16";
492 Names[RTLIB::ATOMIC_FETCH_XOR_1] = "__atomic_fetch_xor_1";
493 Names[RTLIB::ATOMIC_FETCH_XOR_2] = "__atomic_fetch_xor_2";
494 Names[RTLIB::ATOMIC_FETCH_XOR_4] = "__atomic_fetch_xor_4";
495 Names[RTLIB::ATOMIC_FETCH_XOR_8] = "__atomic_fetch_xor_8";
496 Names[RTLIB::ATOMIC_FETCH_XOR_16] = "__atomic_fetch_xor_16";
497 Names[RTLIB::ATOMIC_FETCH_NAND_1] = "__atomic_fetch_nand_1";
498 Names[RTLIB::ATOMIC_FETCH_NAND_2] = "__atomic_fetch_nand_2";
499 Names[RTLIB::ATOMIC_FETCH_NAND_4] = "__atomic_fetch_nand_4";
500 Names[RTLIB::ATOMIC_FETCH_NAND_8] = "__atomic_fetch_nand_8";
501 Names[RTLIB::ATOMIC_FETCH_NAND_16] = "__atomic_fetch_nand_16";
502
Daniel Sandersbf2c03e2016-06-21 12:29:03 +0000[diff] [blame]503 if (TT.isGNUEnvironment()) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]504 Names[RTLIB::SINCOS_F32] = "sincosf";
505 Names[RTLIB::SINCOS_F64] = "sincos";
506 Names[RTLIB::SINCOS_F80] = "sincosl";
507 Names[RTLIB::SINCOS_F128] = "sincosl";
508 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]509 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]510
Simon Pilgrim2bfd9122014-11-29 19:18:21 +0000[diff] [blame]511 if (!TT.isOSOpenBSD()) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]512 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
Ahmed Bougacha6402ad22015-05-14 01:00:51 +0000[diff] [blame]513 }
Sanjoy Dasdf9ae702016-03-24 20:23:29 +0000[diff] [blame]514
515 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]516}
517
Saleem Abdulrasool02d98512016-09-07 17:56:09 +0000[diff] [blame]518/// Set default libcall CallingConvs.
Saleem Abdulrasool92e33a32016-09-09 20:11:31 +0000[diff] [blame]519static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
Saleem Abdulrasool02d98512016-09-07 17:56:09 +0000[diff] [blame]520 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
521 CCs[LC] = CallingConv::C;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]522}
523
524/// getFPEXT - Return the FPEXT_*_* value for the given types, or
525/// UNKNOWN_LIBCALL if there is none.
526RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Tim Northoverf7a02c12014-07-21 09:13:56 +0000[diff] [blame]527 if (OpVT == MVT::f16) {
528 if (RetVT == MVT::f32)
529 return FPEXT_F16_F32;
530 } else if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]531 if (RetVT == MVT::f64)
532 return FPEXT_F32_F64;
533 if (RetVT == MVT::f128)
534 return FPEXT_F32_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]535 if (RetVT == MVT::ppcf128)
536 return FPEXT_F32_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]537 } else if (OpVT == MVT::f64) {
538 if (RetVT == MVT::f128)
539 return FPEXT_F64_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]540 else if (RetVT == MVT::ppcf128)
541 return FPEXT_F64_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]542 }
543
544 return UNKNOWN_LIBCALL;
545}
546
547/// getFPROUND - Return the FPROUND_*_* value for the given types, or
548/// UNKNOWN_LIBCALL if there is none.
549RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]550 if (RetVT == MVT::f16) {
551 if (OpVT == MVT::f32)
552 return FPROUND_F32_F16;
553 if (OpVT == MVT::f64)
554 return FPROUND_F64_F16;
555 if (OpVT == MVT::f80)
556 return FPROUND_F80_F16;
557 if (OpVT == MVT::f128)
558 return FPROUND_F128_F16;
559 if (OpVT == MVT::ppcf128)
560 return FPROUND_PPCF128_F16;
561 } else if (RetVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]562 if (OpVT == MVT::f64)
563 return FPROUND_F64_F32;
564 if (OpVT == MVT::f80)
565 return FPROUND_F80_F32;
566 if (OpVT == MVT::f128)
567 return FPROUND_F128_F32;
568 if (OpVT == MVT::ppcf128)
569 return FPROUND_PPCF128_F32;
570 } else if (RetVT == MVT::f64) {
571 if (OpVT == MVT::f80)
572 return FPROUND_F80_F64;
573 if (OpVT == MVT::f128)
574 return FPROUND_F128_F64;
575 if (OpVT == MVT::ppcf128)
576 return FPROUND_PPCF128_F64;
577 }
578
579 return UNKNOWN_LIBCALL;
580}
581
582/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
583/// UNKNOWN_LIBCALL if there is none.
584RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
585 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]586 if (RetVT == MVT::i32)
587 return FPTOSINT_F32_I32;
588 if (RetVT == MVT::i64)
589 return FPTOSINT_F32_I64;
590 if (RetVT == MVT::i128)
591 return FPTOSINT_F32_I128;
592 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]593 if (RetVT == MVT::i32)
594 return FPTOSINT_F64_I32;
595 if (RetVT == MVT::i64)
596 return FPTOSINT_F64_I64;
597 if (RetVT == MVT::i128)
598 return FPTOSINT_F64_I128;
599 } else if (OpVT == MVT::f80) {
600 if (RetVT == MVT::i32)
601 return FPTOSINT_F80_I32;
602 if (RetVT == MVT::i64)
603 return FPTOSINT_F80_I64;
604 if (RetVT == MVT::i128)
605 return FPTOSINT_F80_I128;
606 } else if (OpVT == MVT::f128) {
607 if (RetVT == MVT::i32)
608 return FPTOSINT_F128_I32;
609 if (RetVT == MVT::i64)
610 return FPTOSINT_F128_I64;
611 if (RetVT == MVT::i128)
612 return FPTOSINT_F128_I128;
613 } else if (OpVT == MVT::ppcf128) {
614 if (RetVT == MVT::i32)
615 return FPTOSINT_PPCF128_I32;
616 if (RetVT == MVT::i64)
617 return FPTOSINT_PPCF128_I64;
618 if (RetVT == MVT::i128)
619 return FPTOSINT_PPCF128_I128;
620 }
621 return UNKNOWN_LIBCALL;
622}
623
624/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
625/// UNKNOWN_LIBCALL if there is none.
626RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
627 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]628 if (RetVT == MVT::i32)
629 return FPTOUINT_F32_I32;
630 if (RetVT == MVT::i64)
631 return FPTOUINT_F32_I64;
632 if (RetVT == MVT::i128)
633 return FPTOUINT_F32_I128;
634 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]635 if (RetVT == MVT::i32)
636 return FPTOUINT_F64_I32;
637 if (RetVT == MVT::i64)
638 return FPTOUINT_F64_I64;
639 if (RetVT == MVT::i128)
640 return FPTOUINT_F64_I128;
641 } else if (OpVT == MVT::f80) {
642 if (RetVT == MVT::i32)
643 return FPTOUINT_F80_I32;
644 if (RetVT == MVT::i64)
645 return FPTOUINT_F80_I64;
646 if (RetVT == MVT::i128)
647 return FPTOUINT_F80_I128;
648 } else if (OpVT == MVT::f128) {
649 if (RetVT == MVT::i32)
650 return FPTOUINT_F128_I32;
651 if (RetVT == MVT::i64)
652 return FPTOUINT_F128_I64;
653 if (RetVT == MVT::i128)
654 return FPTOUINT_F128_I128;
655 } else if (OpVT == MVT::ppcf128) {
656 if (RetVT == MVT::i32)
657 return FPTOUINT_PPCF128_I32;
658 if (RetVT == MVT::i64)
659 return FPTOUINT_PPCF128_I64;
660 if (RetVT == MVT::i128)
661 return FPTOUINT_PPCF128_I128;
662 }
663 return UNKNOWN_LIBCALL;
664}
665
666/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
667/// UNKNOWN_LIBCALL if there is none.
668RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
669 if (OpVT == MVT::i32) {
670 if (RetVT == MVT::f32)
671 return SINTTOFP_I32_F32;
672 if (RetVT == MVT::f64)
673 return SINTTOFP_I32_F64;
674 if (RetVT == MVT::f80)
675 return SINTTOFP_I32_F80;
676 if (RetVT == MVT::f128)
677 return SINTTOFP_I32_F128;
678 if (RetVT == MVT::ppcf128)
679 return SINTTOFP_I32_PPCF128;
680 } else if (OpVT == MVT::i64) {
681 if (RetVT == MVT::f32)
682 return SINTTOFP_I64_F32;
683 if (RetVT == MVT::f64)
684 return SINTTOFP_I64_F64;
685 if (RetVT == MVT::f80)
686 return SINTTOFP_I64_F80;
687 if (RetVT == MVT::f128)
688 return SINTTOFP_I64_F128;
689 if (RetVT == MVT::ppcf128)
690 return SINTTOFP_I64_PPCF128;
691 } else if (OpVT == MVT::i128) {
692 if (RetVT == MVT::f32)
693 return SINTTOFP_I128_F32;
694 if (RetVT == MVT::f64)
695 return SINTTOFP_I128_F64;
696 if (RetVT == MVT::f80)
697 return SINTTOFP_I128_F80;
698 if (RetVT == MVT::f128)
699 return SINTTOFP_I128_F128;
700 if (RetVT == MVT::ppcf128)
701 return SINTTOFP_I128_PPCF128;
702 }
703 return UNKNOWN_LIBCALL;
704}
705
706/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
707/// UNKNOWN_LIBCALL if there is none.
708RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
709 if (OpVT == MVT::i32) {
710 if (RetVT == MVT::f32)
711 return UINTTOFP_I32_F32;
712 if (RetVT == MVT::f64)
713 return UINTTOFP_I32_F64;
714 if (RetVT == MVT::f80)
715 return UINTTOFP_I32_F80;
716 if (RetVT == MVT::f128)
717 return UINTTOFP_I32_F128;
718 if (RetVT == MVT::ppcf128)
719 return UINTTOFP_I32_PPCF128;
720 } else if (OpVT == MVT::i64) {
721 if (RetVT == MVT::f32)
722 return UINTTOFP_I64_F32;
723 if (RetVT == MVT::f64)
724 return UINTTOFP_I64_F64;
725 if (RetVT == MVT::f80)
726 return UINTTOFP_I64_F80;
727 if (RetVT == MVT::f128)
728 return UINTTOFP_I64_F128;
729 if (RetVT == MVT::ppcf128)
730 return UINTTOFP_I64_PPCF128;
731 } else if (OpVT == MVT::i128) {
732 if (RetVT == MVT::f32)
733 return UINTTOFP_I128_F32;
734 if (RetVT == MVT::f64)
735 return UINTTOFP_I128_F64;
736 if (RetVT == MVT::f80)
737 return UINTTOFP_I128_F80;
738 if (RetVT == MVT::f128)
739 return UINTTOFP_I128_F128;
740 if (RetVT == MVT::ppcf128)
741 return UINTTOFP_I128_PPCF128;
742 }
743 return UNKNOWN_LIBCALL;
744}
745
James Y Knightf44fc522016-03-16 22:12:04 +0000[diff] [blame]746RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
Benjamin Kramerc54c38e2015-03-05 20:04:29 +0000[diff] [blame]747#define OP_TO_LIBCALL(Name, Enum) \
748 case Name: \
749 switch (VT.SimpleTy) { \
750 default: \
751 return UNKNOWN_LIBCALL; \
752 case MVT::i8: \
753 return Enum##_1; \
754 case MVT::i16: \
755 return Enum##_2; \
756 case MVT::i32: \
757 return Enum##_4; \
758 case MVT::i64: \
759 return Enum##_8; \
760 case MVT::i128: \
761 return Enum##_16; \
762 }
763
764 switch (Opc) {
765 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
766 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
767 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
768 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
769 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
770 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
771 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
772 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
773 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
774 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
775 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
776 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
777 }
778
779#undef OP_TO_LIBCALL
780
781 return UNKNOWN_LIBCALL;
782}
783
Igor Laevsky4f31e522016-12-29 14:31:07 +0000[diff] [blame]784RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_ATOMIC(uint64_t ElementSize) {
785 switch (ElementSize) {
786 case 1:
787 return MEMCPY_ELEMENT_ATOMIC_1;
788 case 2:
789 return MEMCPY_ELEMENT_ATOMIC_2;
790 case 4:
791 return MEMCPY_ELEMENT_ATOMIC_4;
792 case 8:
793 return MEMCPY_ELEMENT_ATOMIC_8;
794 case 16:
795 return MEMCPY_ELEMENT_ATOMIC_16;
796 default:
797 return UNKNOWN_LIBCALL;
798 }
799
800}
801
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]802/// InitCmpLibcallCCs - Set default comparison libcall CC.
803///
804static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
805 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
806 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
807 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
808 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]809 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]810 CCs[RTLIB::UNE_F32] = ISD::SETNE;
811 CCs[RTLIB::UNE_F64] = ISD::SETNE;
812 CCs[RTLIB::UNE_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]813 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]814 CCs[RTLIB::OGE_F32] = ISD::SETGE;
815 CCs[RTLIB::OGE_F64] = ISD::SETGE;
816 CCs[RTLIB::OGE_F128] = ISD::SETGE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]817 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]818 CCs[RTLIB::OLT_F32] = ISD::SETLT;
819 CCs[RTLIB::OLT_F64] = ISD::SETLT;
820 CCs[RTLIB::OLT_F128] = ISD::SETLT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]821 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]822 CCs[RTLIB::OLE_F32] = ISD::SETLE;
823 CCs[RTLIB::OLE_F64] = ISD::SETLE;
824 CCs[RTLIB::OLE_F128] = ISD::SETLE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]825 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]826 CCs[RTLIB::OGT_F32] = ISD::SETGT;
827 CCs[RTLIB::OGT_F64] = ISD::SETGT;
828 CCs[RTLIB::OGT_F128] = ISD::SETGT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]829 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]830 CCs[RTLIB::UO_F32] = ISD::SETNE;
831 CCs[RTLIB::UO_F64] = ISD::SETNE;
832 CCs[RTLIB::UO_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]833 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]834 CCs[RTLIB::O_F32] = ISD::SETEQ;
835 CCs[RTLIB::O_F64] = ISD::SETEQ;
836 CCs[RTLIB::O_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]837 CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]838}
839
Aditya Nandakumar30531552014-11-13 21:29:21 +0000[diff] [blame]840/// NOTE: The TargetMachine owns TLOF.
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]841TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]842 initActions();
843
844 // Perform these initializations only once.
Zaara Syeda3a7578c2017-05-31 17:12:38 +0000[diff] [blame]845 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
846 MaxLoadsPerMemcmp = 8;
847 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
848 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]849 UseUnderscoreSetJmp = false;
850 UseUnderscoreLongJmp = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]851 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]852 HasExtractBitsInsn = false;
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]853 JumpIsExpensive = JumpIsExpensiveOverride;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]854 PredictableSelectIsExpensive = false;
Quentin Colombetfc2201e2014-12-17 01:36:17 +0000[diff] [blame]855 EnableExtLdPromotion = false;
Pedro Artigascaa56582014-08-08 16:46:53 +0000[diff] [blame]856 HasFloatingPointExceptions = true;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]857 StackPointerRegisterToSaveRestore = 0;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]858 BooleanContents = UndefinedBooleanContent;
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]859 BooleanFloatContents = UndefinedBooleanContent;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]860 BooleanVectorContents = UndefinedBooleanContent;
861 SchedPreferenceInfo = Sched::ILP;
862 JumpBufSize = 0;
863 JumpBufAlignment = 0;
864 MinFunctionAlignment = 0;
865 PrefFunctionAlignment = 0;
866 PrefLoopAlignment = 0;
Nirav Dave54e22f32017-03-14 00:34:14 +0000[diff] [blame]867 GatherAllAliasesMaxDepth = 18;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]868 MinStackArgumentAlignment = 1;
James Y Knight19f6cce2016-04-12 20:18:48 +0000[diff] [blame]869 // TODO: the default will be switched to 0 in the next commit, along
870 // with the Target-specific changes necessary.
871 MaxAtomicSizeInBitsSupported = 1024;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]872
James Y Knight148a6462016-06-17 18:11:48 +0000[diff] [blame]873 MinCmpXchgSizeInBits = 0;
874
James Y Knight7873fb92016-04-12 22:32:47 +0000[diff] [blame]875 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
876
Daniel Sanders110bf6d2015-06-24 13:25:57 +0000[diff] [blame]877 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple());
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]878 InitCmpLibcallCCs(CmpLibcallCCs);
Saleem Abdulrasool92e33a32016-09-09 20:11:31 +0000[diff] [blame]879 InitLibcallCallingConvs(LibcallCallingConvs);
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]880}
881
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]882void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]883 // All operations default to being supported.
884 memset(OpActions, 0, sizeof(OpActions));
885 memset(LoadExtActions, 0, sizeof(LoadExtActions));
886 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
887 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
888 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Craig Topper00230802016-04-08 07:10:46 +0000[diff] [blame]889 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
890 std::fill(std::begin(TargetDAGCombineArray),
891 std::end(TargetDAGCombineArray), 0);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]892
893 // Set default actions for various operations.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]894 for (MVT VT : MVT::all_valuetypes()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]895 // Default all indexed load / store to expand.
896 for (unsigned IM = (unsigned)ISD::PRE_INC;
897 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]898 setIndexedLoadAction(IM, VT, Expand);
899 setIndexedStoreAction(IM, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]900 }
901
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]902 // Most backends expect to see the node which just returns the value loaded.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]903 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]904
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]905 // These operations default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]906 setOperationAction(ISD::FGETSIGN, VT, Expand);
907 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
908 setOperationAction(ISD::FMINNUM, VT, Expand);
909 setOperationAction(ISD::FMAXNUM, VT, Expand);
James Molloy01cdecc2015-08-11 09:13:05 +0000[diff] [blame]910 setOperationAction(ISD::FMINNAN, VT, Expand);
911 setOperationAction(ISD::FMAXNAN, VT, Expand);
Matt Arsenault0dc54c42015-02-20 22:10:33 +0000[diff] [blame]912 setOperationAction(ISD::FMAD, VT, Expand);
James Molloy7e9776b2015-05-15 09:03:15 +0000[diff] [blame]913 setOperationAction(ISD::SMIN, VT, Expand);
914 setOperationAction(ISD::SMAX, VT, Expand);
915 setOperationAction(ISD::UMIN, VT, Expand);
916 setOperationAction(ISD::UMAX, VT, Expand);
Simon Pilgrimcf2da962017-03-14 21:26:58 +0000[diff] [blame]917 setOperationAction(ISD::ABS, VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]918
Jan Vesely75395482015-04-29 16:30:46 +0000[diff] [blame]919 // Overflow operations default to expand
920 setOperationAction(ISD::SADDO, VT, Expand);
921 setOperationAction(ISD::SSUBO, VT, Expand);
922 setOperationAction(ISD::UADDO, VT, Expand);
923 setOperationAction(ISD::USUBO, VT, Expand);
924 setOperationAction(ISD::SMULO, VT, Expand);
925 setOperationAction(ISD::UMULO, VT, Expand);
Hal Finkelcd8664c2015-12-11 23:11:52 +0000[diff] [blame]926
Amaury Sechet8ac81f32017-04-30 19:24:09 +0000[diff] [blame]927 // ADDCARRY operations default to expand
928 setOperationAction(ISD::ADDCARRY, VT, Expand);
929 setOperationAction(ISD::SUBCARRY, VT, Expand);
930
Craig Topper33772c52016-04-28 03:34:31 +0000[diff] [blame]931 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
932 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
933 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
934
James Molloy90111f72015-11-12 12:29:09 +0000[diff] [blame]935 setOperationAction(ISD::BITREVERSE, VT, Expand);
936
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]937 // These library functions default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]938 setOperationAction(ISD::FROUND, VT, Expand);
Craig Topperf6d4dc52017-05-30 15:27:55 +0000[diff] [blame]939 setOperationAction(ISD::FPOWI, VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]940
941 // These operations default to expand for vector types.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]942 if (VT.isVector()) {
943 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
944 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
945 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
946 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]947 }
Yury Gribovd7dbb662015-12-01 11:40:55 +0000[diff] [blame]948
Etienne Bergeron22bfa832016-06-07 20:15:35 +0000[diff] [blame]949 // For most targets @llvm.get.dynamic.area.offset just returns 0.
Yury Gribovd7dbb662015-12-01 11:40:55 +0000[diff] [blame]950 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]951 }
952
953 // Most targets ignore the @llvm.prefetch intrinsic.
954 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
955
Ahmed Bougachaf9c19da2015-08-28 01:49:59 +0000[diff] [blame]956 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
957 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand);
958
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]959 // ConstantFP nodes default to expand. Targets can either change this to
960 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
961 // to optimize expansions for certain constants.
962 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
963 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
964 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
965 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
966 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
967
968 // These library functions default to expand.
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]969 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
970 setOperationAction(ISD::FLOG , VT, Expand);
971 setOperationAction(ISD::FLOG2, VT, Expand);
972 setOperationAction(ISD::FLOG10, VT, Expand);
973 setOperationAction(ISD::FEXP , VT, Expand);
974 setOperationAction(ISD::FEXP2, VT, Expand);
975 setOperationAction(ISD::FFLOOR, VT, Expand);
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]976 setOperationAction(ISD::FNEARBYINT, VT, Expand);
977 setOperationAction(ISD::FCEIL, VT, Expand);
978 setOperationAction(ISD::FRINT, VT, Expand);
979 setOperationAction(ISD::FTRUNC, VT, Expand);
980 setOperationAction(ISD::FROUND, VT, Expand);
981 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]982
983 // Default ISD::TRAP to expand (which turns it into abort).
984 setOperationAction(ISD::TRAP, MVT::Other, Expand);
985
986 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
987 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
988 //
989 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]990}
991
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]992MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
993 EVT) const {
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]994 return MVT::getIntegerVT(8 * DL.getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]995}
996
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]997EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
998 const DataLayout &DL) const {
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]999 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1000 if (LHSTy.isVector())
1001 return LHSTy;
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]1002 return getScalarShiftAmountTy(DL, LHSTy);
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]1003}
1004
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1005bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1006 assert(isTypeLegal(VT));
1007 switch (Op) {
1008 default:
1009 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1010 case ISD::SDIV:
1011 case ISD::UDIV:
1012 case ISD::SREM:
1013 case ISD::UREM:
1014 return true;
1015 }
1016}
1017
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]1018void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1019 // If the command-line option was specified, ignore this request.
1020 if (!JumpIsExpensiveOverride.getNumOccurrences())
1021 JumpIsExpensive = isExpensive;
1022}
1023
Eric Christopher75dbd7c2015-02-25 22:41:30 +0000[diff] [blame]1024TargetLoweringBase::LegalizeKind
1025TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1026 // If this is a simple type, use the ComputeRegisterProp mechanism.
1027 if (VT.isSimple()) {
1028 MVT SVT = VT.getSimpleVT();
1029 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1030 MVT NVT = TransformToType[SVT.SimpleTy];
1031 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1032
1033 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1034 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
1035 "Promote may not follow Expand or Promote");
1036
1037 if (LA == TypeSplitVector)
1038 return LegalizeKind(LA,
1039 EVT::getVectorVT(Context, SVT.getVectorElementType(),
1040 SVT.getVectorNumElements() / 2));
1041 if (LA == TypeScalarizeVector)
1042 return LegalizeKind(LA, SVT.getVectorElementType());
1043 return LegalizeKind(LA, NVT);
1044 }
1045
1046 // Handle Extended Scalar Types.
1047 if (!VT.isVector()) {
1048 assert(VT.isInteger() && "Float types must be simple");
1049 unsigned BitSize = VT.getSizeInBits();
1050 // First promote to a power-of-two size, then expand if necessary.
1051 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1052 EVT NVT = VT.getRoundIntegerType(Context);
1053 assert(NVT != VT && "Unable to round integer VT");
1054 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1055 // Avoid multi-step promotion.
1056 if (NextStep.first == TypePromoteInteger)
1057 return NextStep;
1058 // Return rounded integer type.
1059 return LegalizeKind(TypePromoteInteger, NVT);
1060 }
1061
1062 return LegalizeKind(TypeExpandInteger,
1063 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
1064 }
1065
1066 // Handle vector types.
1067 unsigned NumElts = VT.getVectorNumElements();
1068 EVT EltVT = VT.getVectorElementType();
1069
1070 // Vectors with only one element are always scalarized.
1071 if (NumElts == 1)
1072 return LegalizeKind(TypeScalarizeVector, EltVT);
1073
1074 // Try to widen vector elements until the element type is a power of two and
1075 // promote it to a legal type later on, for example:
1076 // <3 x i8> -> <4 x i8> -> <4 x i32>
1077 if (EltVT.isInteger()) {
1078 // Vectors with a number of elements that is not a power of two are always
1079 // widened, for example <3 x i8> -> <4 x i8>.
1080 if (!VT.isPow2VectorType()) {
1081 NumElts = (unsigned)NextPowerOf2(NumElts);
1082 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1083 return LegalizeKind(TypeWidenVector, NVT);
1084 }
1085
1086 // Examine the element type.
1087 LegalizeKind LK = getTypeConversion(Context, EltVT);
1088
1089 // If type is to be expanded, split the vector.
1090 // <4 x i140> -> <2 x i140>
1091 if (LK.first == TypeExpandInteger)
1092 return LegalizeKind(TypeSplitVector,
1093 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1094
1095 // Promote the integer element types until a legal vector type is found
1096 // or until the element integer type is too big. If a legal type was not
1097 // found, fallback to the usual mechanism of widening/splitting the
1098 // vector.
1099 EVT OldEltVT = EltVT;
1100 while (1) {
1101 // Increase the bitwidth of the element to the next pow-of-two
1102 // (which is greater than 8 bits).
1103 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1104 .getRoundIntegerType(Context);
1105
1106 // Stop trying when getting a non-simple element type.
1107 // Note that vector elements may be greater than legal vector element
1108 // types. Example: X86 XMM registers hold 64bit element on 32bit
1109 // systems.
1110 if (!EltVT.isSimple())
1111 break;
1112
1113 // Build a new vector type and check if it is legal.
1114 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1115 // Found a legal promoted vector type.
1116 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1117 return LegalizeKind(TypePromoteInteger,
1118 EVT::getVectorVT(Context, EltVT, NumElts));
1119 }
1120
1121 // Reset the type to the unexpanded type if we did not find a legal vector
1122 // type with a promoted vector element type.
1123 EltVT = OldEltVT;
1124 }
1125
1126 // Try to widen the vector until a legal type is found.
1127 // If there is no wider legal type, split the vector.
1128 while (1) {
1129 // Round up to the next power of 2.
1130 NumElts = (unsigned)NextPowerOf2(NumElts);
1131
1132 // If there is no simple vector type with this many elements then there
1133 // cannot be a larger legal vector type. Note that this assumes that
1134 // there are no skipped intermediate vector types in the simple types.
1135 if (!EltVT.isSimple())
1136 break;
1137 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1138 if (LargerVector == MVT())
1139 break;
1140
1141 // If this type is legal then widen the vector.
1142 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1143 return LegalizeKind(TypeWidenVector, LargerVector);
1144 }
1145
1146 // Widen odd vectors to next power of two.
1147 if (!VT.isPow2VectorType()) {
1148 EVT NVT = VT.getPow2VectorType(Context);
1149 return LegalizeKind(TypeWidenVector, NVT);
1150 }
1151
1152 // Vectors with illegal element types are expanded.
1153 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1154 return LegalizeKind(TypeSplitVector, NVT);
1155}
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1156
1157static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1158 unsigned &NumIntermediates,
1159 MVT &RegisterVT,
1160 TargetLoweringBase *TLI) {
1161 // Figure out the right, legal destination reg to copy into.
1162 unsigned NumElts = VT.getVectorNumElements();
1163 MVT EltTy = VT.getVectorElementType();
1164
1165 unsigned NumVectorRegs = 1;
1166
1167 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1168 // could break down into LHS/RHS like LegalizeDAG does.
1169 if (!isPowerOf2_32(NumElts)) {
1170 NumVectorRegs = NumElts;
1171 NumElts = 1;
1172 }
1173
1174 // Divide the input until we get to a supported size. This will always
1175 // end with a scalar if the target doesn't support vectors.
1176 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
1177 NumElts >>= 1;
1178 NumVectorRegs <<= 1;
1179 }
1180
1181 NumIntermediates = NumVectorRegs;
1182
1183 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
1184 if (!TLI->isTypeLegal(NewVT))
1185 NewVT = EltTy;
1186 IntermediateVT = NewVT;
1187
1188 unsigned NewVTSize = NewVT.getSizeInBits();
1189
1190 // Convert sizes such as i33 to i64.
1191 if (!isPowerOf2_32(NewVTSize))
1192 NewVTSize = NextPowerOf2(NewVTSize);
1193
1194 MVT DestVT = TLI->getRegisterType(NewVT);
1195 RegisterVT = DestVT;
1196 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1197 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1198
1199 // Otherwise, promotion or legal types use the same number of registers as
1200 // the vector decimated to the appropriate level.
1201 return NumVectorRegs;
1202}
1203
1204/// isLegalRC - Return true if the value types that can be represented by the
1205/// specified register class are all legal.
Krzysztof Parzyszekc8e8e2a2017-04-24 19:51:12 +0000[diff] [blame]1206bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1207 const TargetRegisterClass &RC) const {
1208 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1209 if (isTypeLegal(*I))
1210 return true;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1211 return false;
1212}
1213
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1214/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1215/// sequence of memory operands that is recognized by PrologEpilogInserter.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]1216MachineBasicBlock *
1217TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1218 MachineBasicBlock *MBB) const {
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]1219 MachineInstr *MI = &InitialMI;
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1220 MachineFunction &MF = *MI->getParent()->getParent();
Matthias Braun941a7052016-07-28 18:40:00 +0000[diff] [blame]1221 MachineFrameInfo &MFI = MF.getFrameInfo();
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1222
1223 // We're handling multiple types of operands here:
1224 // PATCHPOINT MetaArgs - live-in, read only, direct
1225 // STATEPOINT Deopt Spill - live-through, read only, indirect
1226 // STATEPOINT Deopt Alloca - live-through, read only, direct
1227 // (We're currently conservative and mark the deopt slots read/write in
1228 // practice.)
1229 // STATEPOINT GC Spill - live-through, read/write, indirect
1230 // STATEPOINT GC Alloca - live-through, read/write, direct
1231 // The live-in vs live-through is handled already (the live through ones are
1232 // all stack slots), but we need to handle the different type of stackmap
1233 // operands and memory effects here.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1234
1235 // MI changes inside this loop as we grow operands.
1236 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1237 MachineOperand &MO = MI->getOperand(OperIdx);
1238 if (!MO.isFI())
1239 continue;
1240
1241 // foldMemoryOperand builds a new MI after replacing a single FI operand
1242 // with the canonical set of five x86 addressing-mode operands.
1243 int FI = MO.getIndex();
1244 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1245
1246 // Copy operands before the frame-index.
1247 for (unsigned i = 0; i < OperIdx; ++i)
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1248 MIB.add(MI->getOperand(i));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1249 // Add frame index operands recognized by stackmaps.cpp
1250 if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1251 // indirect-mem-ref tag, size, #FI, offset.
1252 // Used for spills inserted by StatepointLowering. This codepath is not
1253 // used for patchpoints/stackmaps at all, for these spilling is done via
1254 // foldMemoryOperand callback only.
1255 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1256 MIB.addImm(StackMaps::IndirectMemRefOp);
1257 MIB.addImm(MFI.getObjectSize(FI));
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1258 MIB.add(MI->getOperand(OperIdx));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1259 MIB.addImm(0);
1260 } else {
1261 // direct-mem-ref tag, #FI, offset.
1262 // Used by patchpoint, and direct alloca arguments to statepoints
1263 MIB.addImm(StackMaps::DirectMemRefOp);
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1264 MIB.add(MI->getOperand(OperIdx));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1265 MIB.addImm(0);
1266 }
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1267 // Copy the operands after the frame index.
1268 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1269 MIB.add(MI->getOperand(i));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1270
1271 // Inherit previous memory operands.
1272 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1273 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1274
1275 // Add a new memory operand for this FI.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1276 assert(MFI.getObjectOffset(FI) != -1);
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1277
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]1278 auto Flags = MachineMemOperand::MOLoad;
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1279 if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
1280 Flags |= MachineMemOperand::MOStore;
1281 Flags |= MachineMemOperand::MOVolatile;
1282 }
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]1283 MachineMemOperand *MMO = MF.getMachineMemOperand(
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]1284 MachinePointerInfo::getFixedStack(MF, FI), Flags,
Mehdi Aminibd7287e2015-07-16 06:11:10 +0000[diff] [blame]1285 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1286 MIB->addMemOperand(MF, MMO);
1287
1288 // Replace the instruction and update the operand index.
1289 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1290 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1291 MI->eraseFromParent();
1292 MI = MIB;
1293 }
1294 return MBB;
1295}
1296
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1297/// findRepresentativeClass - Return the largest legal super-reg register class
1298/// of the register class for the specified type and its associated "cost".
Eric Christopher720ab842015-03-03 19:47:14 +0000[diff] [blame]1299// This function is in TargetLowering because it uses RegClassForVT which would
1300// need to be moved to TargetRegisterInfo and would necessitate moving
1301// isTypeLegal over as well - a massive change that would just require
1302// TargetLowering having a TargetRegisterInfo class member that it would use.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1303std::pair<const TargetRegisterClass *, uint8_t>
1304TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1305 MVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1306 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1307 if (!RC)
1308 return std::make_pair(RC, 0);
1309
1310 // Compute the set of all super-register classes.
1311 BitVector SuperRegRC(TRI->getNumRegClasses());
1312 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1313 SuperRegRC.setBitsInMask(RCI.getMask());
1314
1315 // Find the first legal register class with the largest spill size.
1316 const TargetRegisterClass *BestRC = RC;
Francis Visoiu Mistrihb52e0362017-05-17 01:07:53 +0000[diff] [blame]1317 for (unsigned i : SuperRegRC.set_bits()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1318 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1319 // We want the largest possible spill size.
Krzysztof Parzyszek44e25f32017-04-24 18:55:33 +0000[diff] [blame]1320 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1321 continue;
Krzysztof Parzyszekc8e8e2a2017-04-24 19:51:12 +0000[diff] [blame]1322 if (!isLegalRC(*TRI, *SuperRC))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1323 continue;
1324 BestRC = SuperRC;
1325 }
1326 return std::make_pair(BestRC, 1);
1327}
1328
1329/// computeRegisterProperties - Once all of the register classes are added,
1330/// this allows us to compute derived properties we expose.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1331void TargetLoweringBase::computeRegisterProperties(
1332 const TargetRegisterInfo *TRI) {
Craig Topper6438fc32014-11-17 00:26:50 +0000[diff] [blame]1333 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1334 "Too many value types for ValueTypeActions to hold!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1335
1336 // Everything defaults to needing one register.
1337 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1338 NumRegistersForVT[i] = 1;
1339 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1340 }
1341 // ...except isVoid, which doesn't need any registers.
1342 NumRegistersForVT[MVT::isVoid] = 0;
1343
1344 // Find the largest integer register class.
1345 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1346 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1347 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1348
1349 // Every integer value type larger than this largest register takes twice as
1350 // many registers to represent as the previous ValueType.
1351 for (unsigned ExpandedReg = LargestIntReg + 1;
1352 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1353 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1354 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1355 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1356 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1357 TypeExpandInteger);
1358 }
1359
1360 // Inspect all of the ValueType's smaller than the largest integer
1361 // register to see which ones need promotion.
1362 unsigned LegalIntReg = LargestIntReg;
1363 for (unsigned IntReg = LargestIntReg - 1;
1364 IntReg >= (unsigned)MVT::i1; --IntReg) {
1365 MVT IVT = (MVT::SimpleValueType)IntReg;
1366 if (isTypeLegal(IVT)) {
1367 LegalIntReg = IntReg;
1368 } else {
1369 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1370 (const MVT::SimpleValueType)LegalIntReg;
1371 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1372 }
1373 }
1374
1375 // ppcf128 type is really two f64's.
1376 if (!isTypeLegal(MVT::ppcf128)) {
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]1377 if (isTypeLegal(MVT::f64)) {
1378 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1379 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1380 TransformToType[MVT::ppcf128] = MVT::f64;
1381 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1382 } else {
1383 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1384 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1385 TransformToType[MVT::ppcf128] = MVT::i128;
1386 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1387 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1388 }
1389
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1390 // Decide how to handle f128. If the target does not have native f128 support,
1391 // expand it to i128 and we will be generating soft float library calls.
1392 if (!isTypeLegal(MVT::f128)) {
1393 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1394 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1395 TransformToType[MVT::f128] = MVT::i128;
1396 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1397 }
1398
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1399 // Decide how to handle f64. If the target does not have native f64 support,
1400 // expand it to i64 and we will be generating soft float library calls.
1401 if (!isTypeLegal(MVT::f64)) {
1402 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1403 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1404 TransformToType[MVT::f64] = MVT::i64;
1405 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1406 }
1407
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1408 // Decide how to handle f32. If the target does not have native f32 support,
1409 // expand it to i32 and we will be generating soft float library calls.
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1410 if (!isTypeLegal(MVT::f32)) {
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1411 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1412 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1413 TransformToType[MVT::f32] = MVT::i32;
1414 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1415 }
1416
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1417 // Decide how to handle f16. If the target does not have native f16 support,
1418 // promote it to f32, because there are no f16 library calls (except for
1419 // conversions).
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1420 if (!isTypeLegal(MVT::f16)) {
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1421 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1422 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1423 TransformToType[MVT::f16] = MVT::f32;
1424 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1425 }
1426
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1427 // Loop over all of the vector value types to see which need transformations.
1428 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1429 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1430 MVT VT = (MVT::SimpleValueType) i;
1431 if (isTypeLegal(VT))
1432 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1433
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1434 MVT EltVT = VT.getVectorElementType();
1435 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1436 bool IsLegalWiderType = false;
1437 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1438 switch (PreferredAction) {
1439 case TypePromoteInteger: {
1440 // Try to promote the elements of integer vectors. If no legal
1441 // promotion was found, fall through to the widen-vector method.
Matt Arsenault940d19a2016-04-22 21:16:17 +0000[diff] [blame]1442 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1443 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1444 // Promote vectors of integers to vectors with the same number
1445 // of elements, with a wider element type.
Sanjay Patel1ed771f2016-09-14 16:37:15 +0000[diff] [blame]1446 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
Matt Arsenault940d19a2016-04-22 21:16:17 +0000[diff] [blame]1447 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1448 TransformToType[i] = SVT;
1449 RegisterTypeForVT[i] = SVT;
1450 NumRegistersForVT[i] = 1;
1451 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1452 IsLegalWiderType = true;
1453 break;
1454 }
1455 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1456 if (IsLegalWiderType)
1457 break;
1458 }
1459 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1460 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1461 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1462 MVT SVT = (MVT::SimpleValueType) nVT;
1463 if (SVT.getVectorElementType() == EltVT
1464 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1465 TransformToType[i] = SVT;
1466 RegisterTypeForVT[i] = SVT;
1467 NumRegistersForVT[i] = 1;
1468 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1469 IsLegalWiderType = true;
1470 break;
1471 }
1472 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1473 if (IsLegalWiderType)
1474 break;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1475 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1476 case TypeSplitVector:
1477 case TypeScalarizeVector: {
1478 MVT IntermediateVT;
1479 MVT RegisterVT;
1480 unsigned NumIntermediates;
1481 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1482 NumIntermediates, RegisterVT, this);
1483 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1484
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1485 MVT NVT = VT.getPow2VectorType();
1486 if (NVT == VT) {
1487 // Type is already a power of 2. The default action is to split.
1488 TransformToType[i] = MVT::Other;
1489 if (PreferredAction == TypeScalarizeVector)
1490 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1491 else if (PreferredAction == TypeSplitVector)
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1492 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1493 else
1494 // Set type action according to the number of elements.
1495 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1496 : TypeSplitVector);
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1497 } else {
1498 TransformToType[i] = NVT;
1499 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1500 }
1501 break;
1502 }
1503 default:
1504 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1505 }
1506 }
1507
1508 // Determine the 'representative' register class for each value type.
1509 // An representative register class is the largest (meaning one which is
1510 // not a sub-register class / subreg register class) legal register class for
1511 // a group of value types. For example, on i386, i8, i16, and i32
1512 // representative would be GR32; while on x86_64 it's GR64.
1513 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1514 const TargetRegisterClass* RRC;
1515 uint8_t Cost;
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1516 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1517 RepRegClassForVT[i] = RRC;
1518 RepRegClassCostForVT[i] = Cost;
1519 }
1520}
1521
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1522EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1523 EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1524 assert(!VT.isVector() && "No default SetCC type for vectors!");
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1525 return getPointerTy(DL).SimpleTy;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1526}
1527
1528MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1529 return MVT::i32; // return the default value
1530}
1531
1532/// getVectorTypeBreakdown - Vector types are broken down into some number of
1533/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1534/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1535/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1536///
1537/// This method returns the number of registers needed, and the VT for each
1538/// register. It also returns the VT and quantity of the intermediate values
1539/// before they are promoted/expanded.
1540///
1541unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1542 EVT &IntermediateVT,
1543 unsigned &NumIntermediates,
1544 MVT &RegisterVT) const {
1545 unsigned NumElts = VT.getVectorNumElements();
1546
1547 // If there is a wider vector type with the same element type as this one,
1548 // or a promoted vector type that has the same number of elements which
1549 // are wider, then we should convert to that legal vector type.
1550 // This handles things like <2 x float> -> <4 x float> and
1551 // <4 x i1> -> <4 x i32>.
1552 LegalizeTypeAction TA = getTypeAction(Context, VT);
1553 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1554 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1555 if (isTypeLegal(RegisterEVT)) {
1556 IntermediateVT = RegisterEVT;
1557 RegisterVT = RegisterEVT.getSimpleVT();
1558 NumIntermediates = 1;
1559 return 1;
1560 }
1561 }
1562
1563 // Figure out the right, legal destination reg to copy into.
1564 EVT EltTy = VT.getVectorElementType();
1565
1566 unsigned NumVectorRegs = 1;
1567
1568 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1569 // could break down into LHS/RHS like LegalizeDAG does.
1570 if (!isPowerOf2_32(NumElts)) {
1571 NumVectorRegs = NumElts;
1572 NumElts = 1;
1573 }
1574
1575 // Divide the input until we get to a supported size. This will always
1576 // end with a scalar if the target doesn't support vectors.
1577 while (NumElts > 1 && !isTypeLegal(
1578 EVT::getVectorVT(Context, EltTy, NumElts))) {
1579 NumElts >>= 1;
1580 NumVectorRegs <<= 1;
1581 }
1582
1583 NumIntermediates = NumVectorRegs;
1584
1585 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1586 if (!isTypeLegal(NewVT))
1587 NewVT = EltTy;
1588 IntermediateVT = NewVT;
1589
1590 MVT DestVT = getRegisterType(Context, NewVT);
1591 RegisterVT = DestVT;
1592 unsigned NewVTSize = NewVT.getSizeInBits();
1593
1594 // Convert sizes such as i33 to i64.
1595 if (!isPowerOf2_32(NewVTSize))
1596 NewVTSize = NextPowerOf2(NewVTSize);
1597
1598 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1599 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1600
1601 // Otherwise, promotion or legal types use the same number of registers as
1602 // the vector decimated to the appropriate level.
1603 return NumVectorRegs;
1604}
1605
1606/// Get the EVTs and ArgFlags collections that represent the legalized return
1607/// type of the given function. This does not require a DAG or a return value,
1608/// and is suitable for use before any DAGs for the function are constructed.
1609/// TODO: Move this out of TargetLowering.cpp.
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1610void llvm::GetReturnInfo(Type *ReturnType, AttributeList attr,
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1611 SmallVectorImpl<ISD::OutputArg> &Outs,
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1612 const TargetLowering &TLI, const DataLayout &DL) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1613 SmallVector<EVT, 4> ValueVTs;
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1614 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1615 unsigned NumValues = ValueVTs.size();
1616 if (NumValues == 0) return;
1617
1618 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1619 EVT VT = ValueVTs[j];
1620 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1621
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1622 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1623 ExtendKind = ISD::SIGN_EXTEND;
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1624 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1625 ExtendKind = ISD::ZERO_EXTEND;
1626
1627 // FIXME: C calling convention requires the return type to be promoted to
1628 // at least 32-bit. But this is not necessary for non-C calling
1629 // conventions. The frontend should mark functions whose return values
1630 // require promoting with signext or zeroext attributes.
1631 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1632 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1633 if (VT.bitsLT(MinVT))
1634 VT = MinVT;
1635 }
1636
Simon Dardisf7e43882017-04-07 17:25:05 +0000[diff] [blame]1637 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1638 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1639
1640 // 'inreg' on function refers to return value
1641 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1642 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1643 Flags.setInReg();
1644
1645 // Propagate extension type if any
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1646 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1647 Flags.setSExt();
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1648 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1649 Flags.setZExt();
1650
1651 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1652 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1653 }
1654}
1655
1656/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1657/// function arguments in the caller parameter area. This is the actual
1658/// alignment, not its logarithm.
Mehdi Amini5c183d52015-07-09 02:09:28 +0000[diff] [blame]1659unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1660 const DataLayout &DL) const {
1661 return DL.getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1662}
1663
Sanjay Patel0f9dcf82015-07-29 18:24:18 +0000[diff] [blame]1664bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1665 const DataLayout &DL, EVT VT,
1666 unsigned AddrSpace,
1667 unsigned Alignment,
1668 bool *Fast) const {
1669 // Check if the specified alignment is sufficient based on the data layout.
1670 // TODO: While using the data layout works in practice, a better solution
1671 // would be to implement this check directly (make this a virtual function).
1672 // For example, the ABI alignment may change based on software platform while
1673 // this function should only be affected by hardware implementation.
1674 Type *Ty = VT.getTypeForEVT(Context);
1675 if (Alignment >= DL.getABITypeAlignment(Ty)) {
1676 // Assume that an access that meets the ABI-specified alignment is fast.
1677 if (Fast != nullptr)
1678 *Fast = true;
1679 return true;
1680 }
1681
1682 // This is a misaligned access.
1683 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast);
1684}
1685
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]1686BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const {
1687 return BranchProbability(MinPercentageForPredictableBranch, 100);
1688}
Sanjay Patel0f9dcf82015-07-29 18:24:18 +0000[diff] [blame]1689
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1690//===----------------------------------------------------------------------===//
1691// TargetTransformInfo Helpers
1692//===----------------------------------------------------------------------===//
1693
1694int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1695 enum InstructionOpcodes {
1696#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1697#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1698#include "llvm/IR/Instruction.def"
1699 };
1700 switch (static_cast<InstructionOpcodes>(Opcode)) {
1701 case Ret: return 0;
1702 case Br: return 0;
1703 case Switch: return 0;
1704 case IndirectBr: return 0;
1705 case Invoke: return 0;
1706 case Resume: return 0;
1707 case Unreachable: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1708 case CleanupRet: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1709 case CatchRet: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1710 case CatchPad: return 0;
1711 case CatchSwitch: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1712 case CleanupPad: return 0;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1713 case Add: return ISD::ADD;
1714 case FAdd: return ISD::FADD;
1715 case Sub: return ISD::SUB;
1716 case FSub: return ISD::FSUB;
1717 case Mul: return ISD::MUL;
1718 case FMul: return ISD::FMUL;
1719 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1720 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1721 case FDiv: return ISD::FDIV;
1722 case URem: return ISD::UREM;
1723 case SRem: return ISD::SREM;
1724 case FRem: return ISD::FREM;
1725 case Shl: return ISD::SHL;
1726 case LShr: return ISD::SRL;
1727 case AShr: return ISD::SRA;
1728 case And: return ISD::AND;
1729 case Or: return ISD::OR;
1730 case Xor: return ISD::XOR;
1731 case Alloca: return 0;
1732 case Load: return ISD::LOAD;
1733 case Store: return ISD::STORE;
1734 case GetElementPtr: return 0;
1735 case Fence: return 0;
1736 case AtomicCmpXchg: return 0;
1737 case AtomicRMW: return 0;
1738 case Trunc: return ISD::TRUNCATE;
1739 case ZExt: return ISD::ZERO_EXTEND;
1740 case SExt: return ISD::SIGN_EXTEND;
1741 case FPToUI: return ISD::FP_TO_UINT;
1742 case FPToSI: return ISD::FP_TO_SINT;
1743 case UIToFP: return ISD::UINT_TO_FP;
1744 case SIToFP: return ISD::SINT_TO_FP;
1745 case FPTrunc: return ISD::FP_ROUND;
1746 case FPExt: return ISD::FP_EXTEND;
1747 case PtrToInt: return ISD::BITCAST;
1748 case IntToPtr: return ISD::BITCAST;
1749 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1750 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1751 case ICmp: return ISD::SETCC;
1752 case FCmp: return ISD::SETCC;
1753 case PHI: return 0;
1754 case Call: return 0;
1755 case Select: return ISD::SELECT;
1756 case UserOp1: return 0;
1757 case UserOp2: return 0;
1758 case VAArg: return 0;
1759 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1760 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1761 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1762 case ExtractValue: return ISD::MERGE_VALUES;
1763 case InsertValue: return ISD::MERGE_VALUES;
1764 case LandingPad: return 0;
1765 }
1766
1767 llvm_unreachable("Unknown instruction type encountered!");
1768}
1769
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1770std::pair<int, MVT>
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1771TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
1772 Type *Ty) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1773 LLVMContext &C = Ty->getContext();
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1774 EVT MTy = getValueType(DL, Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1775
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1776 int Cost = 1;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1777 // We keep legalizing the type until we find a legal kind. We assume that
1778 // the only operation that costs anything is the split. After splitting
1779 // we need to handle two types.
1780 while (true) {
1781 LegalizeKind LK = getTypeConversion(C, MTy);
1782
1783 if (LK.first == TypeLegal)
1784 return std::make_pair(Cost, MTy.getSimpleVT());
1785
1786 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1787 Cost *= 2;
1788
Chih-Hung Hsiehed7d81e2015-12-03 22:02:40 +0000[diff] [blame]1789 // Do not loop with f128 type.
1790 if (MTy == LK.second)
1791 return std::make_pair(Cost, MTy.getSimpleVT());
1792
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1793 // Keep legalizing the type.
1794 MTy = LK.second;
1795 }
1796}
1797
David L Kreitzerd5c67552016-10-14 17:56:00 +0000[diff] [blame]1798Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1799 bool UseTLS) const {
1800 // compiler-rt provides a variable with a magic name. Targets that do not
1801 // link with compiler-rt may also provide such a variable.
1802 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1803 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1804 auto UnsafeStackPtr =
1805 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1806
1807 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1808
1809 if (!UnsafeStackPtr) {
1810 auto TLSModel = UseTLS ?
1811 GlobalValue::InitialExecTLSModel :
1812 GlobalValue::NotThreadLocal;
1813 // The global variable is not defined yet, define it ourselves.
1814 // We use the initial-exec TLS model because we do not support the
1815 // variable living anywhere other than in the main executable.
1816 UnsafeStackPtr = new GlobalVariable(
1817 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1818 UnsafeStackPtrVar, nullptr, TLSModel);
1819 } else {
1820 // The variable exists, check its type and attributes.
1821 if (UnsafeStackPtr->getValueType() != StackPtrTy)
1822 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1823 if (UseTLS != UnsafeStackPtr->isThreadLocal())
1824 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1825 (UseTLS ? "" : "not ") + "be thread-local");
1826 }
1827 return UnsafeStackPtr;
1828}
1829
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1830Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
1831 if (!TM.getTargetTriple().isAndroid())
David L Kreitzerd5c67552016-10-14 17:56:00 +0000[diff] [blame]1832 return getDefaultSafeStackPointerLocation(IRB, true);
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1833
1834 // Android provides a libc function to retrieve the address of the current
1835 // thread's unsafe stack pointer.
1836 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1837 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1838 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address",
Serge Guelton59a2d7b2017-04-11 15:01:18 +0000[diff] [blame]1839 StackPtrTy->getPointerTo(0));
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1840 return IRB.CreateCall(Fn);
1841}
1842
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1843//===----------------------------------------------------------------------===//
1844// Loop Strength Reduction hooks
1845//===----------------------------------------------------------------------===//
1846
1847/// isLegalAddressingMode - Return true if the addressing mode represented
1848/// by AM is legal for this target, for a load/store of the specified type.
Mehdi Amini0cdec1e2015-07-09 02:09:40 +0000[diff] [blame]1849bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
1850 const AddrMode &AM, Type *Ty,
Matt Arsenaultbd7d80a2015-06-01 05:31:59 +0000[diff] [blame]1851 unsigned AS) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1852 // The default implementation of this implements a conservative RISCy, r+r and
1853 // r+i addr mode.
1854
1855 // Allows a sign-extended 16-bit immediate field.
1856 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1857 return false;
1858
1859 // No global is ever allowed as a base.
1860 if (AM.BaseGV)
1861 return false;
1862
1863 // Only support r+r,
1864 switch (AM.Scale) {
1865 case 0: // "r+i" or just "i", depending on HasBaseReg.
1866 break;
1867 case 1:
1868 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1869 return false;
1870 // Otherwise we have r+r or r+i.
1871 break;
1872 case 2:
1873 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1874 return false;
1875 // Allow 2*r as r+r.
1876 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1877 default: // Don't allow n * r
1878 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1879 }
1880
1881 return true;
1882}
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1883
1884//===----------------------------------------------------------------------===//
1885// Stack Protector
1886//===----------------------------------------------------------------------===//
1887
1888// For OpenBSD return its special guard variable. Otherwise return nullptr,
1889// so that SelectionDAG handle SSP.
1890Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const {
1891 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1892 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1893 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
Tim Shena5cc25e2016-08-22 18:26:27 +0000[diff] [blame]1894 return M.getOrInsertGlobal("__guard_local", PtrTy);
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1895 }
1896 return nullptr;
1897}
1898
1899// Currently only support "standard" __stack_chk_guard.
1900// TODO: add LOAD_STACK_GUARD support.
1901void TargetLoweringBase::insertSSPDeclarations(Module &M) const {
1902 M.getOrInsertGlobal("__stack_chk_guard", Type::getInt8PtrTy(M.getContext()));
1903}
1904
1905// Currently only support "standard" __stack_chk_guard.
1906// TODO: add LOAD_STACK_GUARD support.
Tim Shena1d8bc52016-04-19 20:14:52 +0000[diff] [blame]1907Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const {
Davide Italianobd4243c2016-06-09 14:23:38 +0000[diff] [blame]1908 return M.getGlobalVariable("__stack_chk_guard", true);
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1909}
Etienne Bergeron22bfa832016-06-07 20:15:35 +0000[diff] [blame]1910
1911Value *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const {
1912 return nullptr;
1913}
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]1914
Evandro Menezeseb97e352016-10-25 19:53:51 +0000[diff] [blame]1915unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
1916 return MinimumJumpTableEntries;
1917}
1918
1919void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
1920 MinimumJumpTableEntries = Val;
1921}
1922
Jun Bum Lim919f9e82017-04-28 16:04:03 +0000[diff] [blame]1923unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1924 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1925}
1926
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]1927unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
1928 return MaximumJumpTableSize;
1929}
1930
1931void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
1932 MaximumJumpTableSize = Val;
1933}
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]1934
1935//===----------------------------------------------------------------------===//
1936// Reciprocal Estimates
1937//===----------------------------------------------------------------------===//
1938
1939/// Get the reciprocal estimate attribute string for a function that will
1940/// override the target defaults.
1941static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
1942 const Function *F = MF.getFunction();
David Majnemere0ebdf42017-01-13 22:24:25 +0000[diff] [blame]1943 return F->getFnAttribute("reciprocal-estimates").getValueAsString();
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]1944}
1945
1946/// Construct a string for the given reciprocal operation of the given type.
1947/// This string should match the corresponding option to the front-end's
1948/// "-mrecip" flag assuming those strings have been passed through in an
1949/// attribute string. For example, "vec-divf" for a division of a vXf32.
1950static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1951 std::string Name = VT.isVector() ? "vec-" : "";
1952
1953 Name += IsSqrt ? "sqrt" : "div";
1954
1955 // TODO: Handle "half" or other float types?
1956 if (VT.getScalarType() == MVT::f64) {
1957 Name += "d";
1958 } else {
1959 assert(VT.getScalarType() == MVT::f32 &&
1960 "Unexpected FP type for reciprocal estimate");
1961 Name += "f";
1962 }
1963
1964 return Name;
1965}
1966
1967/// Return the character position and value (a single numeric character) of a
1968/// customized refinement operation in the input string if it exists. Return
1969/// false if there is no customized refinement step count.
1970static bool parseRefinementStep(StringRef In, size_t &Position,
1971 uint8_t &Value) {
1972 const char RefStepToken = ':';
1973 Position = In.find(RefStepToken);
1974 if (Position == StringRef::npos)
1975 return false;
1976
1977 StringRef RefStepString = In.substr(Position + 1);
1978 // Allow exactly one numeric character for the additional refinement
1979 // step parameter.
1980 if (RefStepString.size() == 1) {
1981 char RefStepChar = RefStepString[0];
1982 if (RefStepChar >= '0' && RefStepChar <= '9') {
1983 Value = RefStepChar - '0';
1984 return true;
1985 }
1986 }
1987 report_fatal_error("Invalid refinement step for -recip.");
1988}
1989
1990/// For the input attribute string, return one of the ReciprocalEstimate enum
1991/// status values (enabled, disabled, or not specified) for this operation on
1992/// the specified data type.
1993static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1994 if (Override.empty())
1995 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1996
1997 SmallVector<StringRef, 4> OverrideVector;
1998 SplitString(Override, OverrideVector, ",");
1999 unsigned NumArgs = OverrideVector.size();
2000
2001 // Check if "all", "none", or "default" was specified.
2002 if (NumArgs == 1) {
2003 // Look for an optional setting of the number of refinement steps needed
2004 // for this type of reciprocal operation.
2005 size_t RefPos;
2006 uint8_t RefSteps;
2007 if (parseRefinementStep(Override, RefPos, RefSteps)) {
2008 // Split the string for further processing.
2009 Override = Override.substr(0, RefPos);
2010 }
2011
2012 // All reciprocal types are enabled.
2013 if (Override == "all")
2014 return TargetLoweringBase::ReciprocalEstimate::Enabled;
2015
2016 // All reciprocal types are disabled.
2017 if (Override == "none")
2018 return TargetLoweringBase::ReciprocalEstimate::Disabled;
2019
2020 // Target defaults for enablement are used.
2021 if (Override == "default")
2022 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2023 }
2024
2025 // The attribute string may omit the size suffix ('f'/'d').
2026 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2027 std::string VTNameNoSize = VTName;
Sanjay Patel501be9b2016-10-21 14:58:30 +0000[diff] [blame]2028 VTNameNoSize.pop_back();
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]2029 static const char DisabledPrefix = '!';
2030
2031 for (StringRef RecipType : OverrideVector) {
2032 size_t RefPos;
2033 uint8_t RefSteps;
2034 if (parseRefinementStep(RecipType, RefPos, RefSteps))
2035 RecipType = RecipType.substr(0, RefPos);
2036
2037 // Ignore the disablement token for string matching.
2038 bool IsDisabled = RecipType[0] == DisabledPrefix;
2039 if (IsDisabled)
2040 RecipType = RecipType.substr(1);
2041
2042 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2043 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
2044 : TargetLoweringBase::ReciprocalEstimate::Enabled;
2045 }
2046
2047 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2048}
2049
2050/// For the input attribute string, return the customized refinement step count
2051/// for this operation on the specified data type. If the step count does not
2052/// exist, return the ReciprocalEstimate enum value for unspecified.
2053static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2054 if (Override.empty())
2055 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2056
2057 SmallVector<StringRef, 4> OverrideVector;
2058 SplitString(Override, OverrideVector, ",");
2059 unsigned NumArgs = OverrideVector.size();
2060
2061 // Check if "all", "default", or "none" was specified.
2062 if (NumArgs == 1) {
2063 // Look for an optional setting of the number of refinement steps needed
2064 // for this type of reciprocal operation.
2065 size_t RefPos;
2066 uint8_t RefSteps;
2067 if (!parseRefinementStep(Override, RefPos, RefSteps))
2068 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2069
2070 // Split the string for further processing.
2071 Override = Override.substr(0, RefPos);
2072 assert(Override != "none" &&
2073 "Disabled reciprocals, but specifed refinement steps?");
2074
2075 // If this is a general override, return the specified number of steps.
2076 if (Override == "all" || Override == "default")
2077 return RefSteps;
2078 }
2079
2080 // The attribute string may omit the size suffix ('f'/'d').
2081 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2082 std::string VTNameNoSize = VTName;
Sanjay Patel501be9b2016-10-21 14:58:30 +0000[diff] [blame]2083 VTNameNoSize.pop_back();
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]2084
2085 for (StringRef RecipType : OverrideVector) {
2086 size_t RefPos;
2087 uint8_t RefSteps;
2088 if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2089 continue;
2090
2091 RecipType = RecipType.substr(0, RefPos);
2092 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2093 return RefSteps;
2094 }
2095
2096 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2097}
2098
2099int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2100 MachineFunction &MF) const {
2101 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2102}
2103
2104int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2105 MachineFunction &MF) const {
2106 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2107}
2108
2109int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2110 MachineFunction &MF) const {
2111 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2112}
2113
2114int TargetLoweringBase::getDivRefinementSteps(EVT VT,
2115 MachineFunction &MF) const {
2116 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2117}
Matthias Braun744c2152017-04-28 20:25:05 +0000[diff] [blame]2118
2119void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
2120 MF.getRegInfo().freezeReservedRegs(MF);
2121}