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gerrit-public.fairphone.software / toolchain / llvm-project / 919f9e8d65ada6552b8b8a5ec12ea49db91c922a / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: 9b9f45f040461a9570c9982ee498f8e9f3118f78 [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]17#include "llvm/ADT/StringExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]18#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]19#include "llvm/CodeGen/Analysis.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]22#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]23#include "llvm/CodeGen/MachineJumpTableInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]24#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]25#include "llvm/IR/DataLayout.h"
26#include "llvm/IR/DerivedTypes.h"
27#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]28#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]29#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]30#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]31#include "llvm/MC/MCExpr.h"
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]32#include "llvm/Support/BranchProbability.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/MathExtras.h"
36#include "llvm/Target/TargetLoweringObjectFile.h"
37#include "llvm/Target/TargetMachine.h"
38#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]39#include "llvm/Target/TargetSubtargetInfo.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]40#include <cctype>
41using namespace llvm;
42
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]43static cl::opt<bool> JumpIsExpensiveOverride(
44 "jump-is-expensive", cl::init(false),
45 cl::desc("Do not create extra branches to split comparison logic."),
46 cl::Hidden);
47
Evandro Menezeseb97e352016-10-25 19:53:51 +0000[diff] [blame]48static cl::opt<unsigned> MinimumJumpTableEntries
49 ("min-jump-table-entries", cl::init(4), cl::Hidden,
50 cl::desc("Set minimum number of entries to use a jump table."));
51
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]52static cl::opt<unsigned> MaximumJumpTableSize
Evandro Menezeseb97e352016-10-25 19:53:51 +0000[diff] [blame]53 ("max-jump-table-size", cl::init(0), cl::Hidden,
54 cl::desc("Set maximum size of jump tables; zero for no limit."));
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]55
Jun Bum Lim919f9e82017-04-28 16:04:03 +0000[diff] [blame^]56/// Minimum jump table density for normal functions.
57static cl::opt<unsigned>
58 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
59 cl::desc("Minimum density for building a jump table in "
60 "a normal function"));
61
62/// Minimum jump table density for -Os or -Oz functions.
63static cl::opt<unsigned> OptsizeJumpTableDensity(
64 "optsize-jump-table-density", cl::init(40), cl::Hidden,
65 cl::desc("Minimum density for building a jump table in "
66 "an optsize function"));
67
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]68// Although this default value is arbitrary, it is not random. It is assumed
69// that a condition that evaluates the same way by a higher percentage than this
70// is best represented as control flow. Therefore, the default value N should be
71// set such that the win from N% correct executions is greater than the loss
72// from (100 - N)% mispredicted executions for the majority of intended targets.
73static cl::opt<int> MinPercentageForPredictableBranch(
74 "min-predictable-branch", cl::init(99),
75 cl::desc("Minimum percentage (0-100) that a condition must be either true "
76 "or false to assume that the condition is predictable"),
77 cl::Hidden);
78
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]79/// InitLibcallNames - Set default libcall names.
80///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]81static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]82 Names[RTLIB::SHL_I16] = "__ashlhi3";
83 Names[RTLIB::SHL_I32] = "__ashlsi3";
84 Names[RTLIB::SHL_I64] = "__ashldi3";
85 Names[RTLIB::SHL_I128] = "__ashlti3";
86 Names[RTLIB::SRL_I16] = "__lshrhi3";
87 Names[RTLIB::SRL_I32] = "__lshrsi3";
88 Names[RTLIB::SRL_I64] = "__lshrdi3";
89 Names[RTLIB::SRL_I128] = "__lshrti3";
90 Names[RTLIB::SRA_I16] = "__ashrhi3";
91 Names[RTLIB::SRA_I32] = "__ashrsi3";
92 Names[RTLIB::SRA_I64] = "__ashrdi3";
93 Names[RTLIB::SRA_I128] = "__ashrti3";
94 Names[RTLIB::MUL_I8] = "__mulqi3";
95 Names[RTLIB::MUL_I16] = "__mulhi3";
96 Names[RTLIB::MUL_I32] = "__mulsi3";
97 Names[RTLIB::MUL_I64] = "__muldi3";
98 Names[RTLIB::MUL_I128] = "__multi3";
99 Names[RTLIB::MULO_I32] = "__mulosi4";
100 Names[RTLIB::MULO_I64] = "__mulodi4";
101 Names[RTLIB::MULO_I128] = "__muloti4";
102 Names[RTLIB::SDIV_I8] = "__divqi3";
103 Names[RTLIB::SDIV_I16] = "__divhi3";
104 Names[RTLIB::SDIV_I32] = "__divsi3";
105 Names[RTLIB::SDIV_I64] = "__divdi3";
106 Names[RTLIB::SDIV_I128] = "__divti3";
107 Names[RTLIB::UDIV_I8] = "__udivqi3";
108 Names[RTLIB::UDIV_I16] = "__udivhi3";
109 Names[RTLIB::UDIV_I32] = "__udivsi3";
110 Names[RTLIB::UDIV_I64] = "__udivdi3";
111 Names[RTLIB::UDIV_I128] = "__udivti3";
112 Names[RTLIB::SREM_I8] = "__modqi3";
113 Names[RTLIB::SREM_I16] = "__modhi3";
114 Names[RTLIB::SREM_I32] = "__modsi3";
115 Names[RTLIB::SREM_I64] = "__moddi3";
116 Names[RTLIB::SREM_I128] = "__modti3";
117 Names[RTLIB::UREM_I8] = "__umodqi3";
118 Names[RTLIB::UREM_I16] = "__umodhi3";
119 Names[RTLIB::UREM_I32] = "__umodsi3";
120 Names[RTLIB::UREM_I64] = "__umoddi3";
121 Names[RTLIB::UREM_I128] = "__umodti3";
122
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]123 Names[RTLIB::NEG_I32] = "__negsi2";
124 Names[RTLIB::NEG_I64] = "__negdi2";
125 Names[RTLIB::ADD_F32] = "__addsf3";
126 Names[RTLIB::ADD_F64] = "__adddf3";
127 Names[RTLIB::ADD_F80] = "__addxf3";
128 Names[RTLIB::ADD_F128] = "__addtf3";
129 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
130 Names[RTLIB::SUB_F32] = "__subsf3";
131 Names[RTLIB::SUB_F64] = "__subdf3";
132 Names[RTLIB::SUB_F80] = "__subxf3";
133 Names[RTLIB::SUB_F128] = "__subtf3";
134 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
135 Names[RTLIB::MUL_F32] = "__mulsf3";
136 Names[RTLIB::MUL_F64] = "__muldf3";
137 Names[RTLIB::MUL_F80] = "__mulxf3";
138 Names[RTLIB::MUL_F128] = "__multf3";
139 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
140 Names[RTLIB::DIV_F32] = "__divsf3";
141 Names[RTLIB::DIV_F64] = "__divdf3";
142 Names[RTLIB::DIV_F80] = "__divxf3";
143 Names[RTLIB::DIV_F128] = "__divtf3";
144 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
145 Names[RTLIB::REM_F32] = "fmodf";
146 Names[RTLIB::REM_F64] = "fmod";
147 Names[RTLIB::REM_F80] = "fmodl";
148 Names[RTLIB::REM_F128] = "fmodl";
149 Names[RTLIB::REM_PPCF128] = "fmodl";
150 Names[RTLIB::FMA_F32] = "fmaf";
151 Names[RTLIB::FMA_F64] = "fma";
152 Names[RTLIB::FMA_F80] = "fmal";
153 Names[RTLIB::FMA_F128] = "fmal";
154 Names[RTLIB::FMA_PPCF128] = "fmal";
155 Names[RTLIB::POWI_F32] = "__powisf2";
156 Names[RTLIB::POWI_F64] = "__powidf2";
157 Names[RTLIB::POWI_F80] = "__powixf2";
158 Names[RTLIB::POWI_F128] = "__powitf2";
159 Names[RTLIB::POWI_PPCF128] = "__powitf2";
160 Names[RTLIB::SQRT_F32] = "sqrtf";
161 Names[RTLIB::SQRT_F64] = "sqrt";
162 Names[RTLIB::SQRT_F80] = "sqrtl";
163 Names[RTLIB::SQRT_F128] = "sqrtl";
164 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
165 Names[RTLIB::LOG_F32] = "logf";
166 Names[RTLIB::LOG_F64] = "log";
167 Names[RTLIB::LOG_F80] = "logl";
168 Names[RTLIB::LOG_F128] = "logl";
169 Names[RTLIB::LOG_PPCF128] = "logl";
170 Names[RTLIB::LOG2_F32] = "log2f";
171 Names[RTLIB::LOG2_F64] = "log2";
172 Names[RTLIB::LOG2_F80] = "log2l";
173 Names[RTLIB::LOG2_F128] = "log2l";
174 Names[RTLIB::LOG2_PPCF128] = "log2l";
175 Names[RTLIB::LOG10_F32] = "log10f";
176 Names[RTLIB::LOG10_F64] = "log10";
177 Names[RTLIB::LOG10_F80] = "log10l";
178 Names[RTLIB::LOG10_F128] = "log10l";
179 Names[RTLIB::LOG10_PPCF128] = "log10l";
180 Names[RTLIB::EXP_F32] = "expf";
181 Names[RTLIB::EXP_F64] = "exp";
182 Names[RTLIB::EXP_F80] = "expl";
183 Names[RTLIB::EXP_F128] = "expl";
184 Names[RTLIB::EXP_PPCF128] = "expl";
185 Names[RTLIB::EXP2_F32] = "exp2f";
186 Names[RTLIB::EXP2_F64] = "exp2";
187 Names[RTLIB::EXP2_F80] = "exp2l";
188 Names[RTLIB::EXP2_F128] = "exp2l";
189 Names[RTLIB::EXP2_PPCF128] = "exp2l";
190 Names[RTLIB::SIN_F32] = "sinf";
191 Names[RTLIB::SIN_F64] = "sin";
192 Names[RTLIB::SIN_F80] = "sinl";
193 Names[RTLIB::SIN_F128] = "sinl";
194 Names[RTLIB::SIN_PPCF128] = "sinl";
195 Names[RTLIB::COS_F32] = "cosf";
196 Names[RTLIB::COS_F64] = "cos";
197 Names[RTLIB::COS_F80] = "cosl";
198 Names[RTLIB::COS_F128] = "cosl";
199 Names[RTLIB::COS_PPCF128] = "cosl";
200 Names[RTLIB::POW_F32] = "powf";
201 Names[RTLIB::POW_F64] = "pow";
202 Names[RTLIB::POW_F80] = "powl";
203 Names[RTLIB::POW_F128] = "powl";
204 Names[RTLIB::POW_PPCF128] = "powl";
205 Names[RTLIB::CEIL_F32] = "ceilf";
206 Names[RTLIB::CEIL_F64] = "ceil";
207 Names[RTLIB::CEIL_F80] = "ceill";
208 Names[RTLIB::CEIL_F128] = "ceill";
209 Names[RTLIB::CEIL_PPCF128] = "ceill";
210 Names[RTLIB::TRUNC_F32] = "truncf";
211 Names[RTLIB::TRUNC_F64] = "trunc";
212 Names[RTLIB::TRUNC_F80] = "truncl";
213 Names[RTLIB::TRUNC_F128] = "truncl";
214 Names[RTLIB::TRUNC_PPCF128] = "truncl";
215 Names[RTLIB::RINT_F32] = "rintf";
216 Names[RTLIB::RINT_F64] = "rint";
217 Names[RTLIB::RINT_F80] = "rintl";
218 Names[RTLIB::RINT_F128] = "rintl";
219 Names[RTLIB::RINT_PPCF128] = "rintl";
220 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
221 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
222 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
223 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
224 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]225 Names[RTLIB::ROUND_F32] = "roundf";
226 Names[RTLIB::ROUND_F64] = "round";
227 Names[RTLIB::ROUND_F80] = "roundl";
228 Names[RTLIB::ROUND_F128] = "roundl";
229 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]230 Names[RTLIB::FLOOR_F32] = "floorf";
231 Names[RTLIB::FLOOR_F64] = "floor";
232 Names[RTLIB::FLOOR_F80] = "floorl";
233 Names[RTLIB::FLOOR_F128] = "floorl";
234 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]235 Names[RTLIB::FMIN_F32] = "fminf";
236 Names[RTLIB::FMIN_F64] = "fmin";
237 Names[RTLIB::FMIN_F80] = "fminl";
238 Names[RTLIB::FMIN_F128] = "fminl";
239 Names[RTLIB::FMIN_PPCF128] = "fminl";
240 Names[RTLIB::FMAX_F32] = "fmaxf";
241 Names[RTLIB::FMAX_F64] = "fmax";
242 Names[RTLIB::FMAX_F80] = "fmaxl";
243 Names[RTLIB::FMAX_F128] = "fmaxl";
244 Names[RTLIB::FMAX_PPCF128] = "fmaxl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]245 Names[RTLIB::ROUND_F32] = "roundf";
246 Names[RTLIB::ROUND_F64] = "round";
247 Names[RTLIB::ROUND_F80] = "roundl";
248 Names[RTLIB::ROUND_F128] = "roundl";
249 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]250 Names[RTLIB::COPYSIGN_F32] = "copysignf";
251 Names[RTLIB::COPYSIGN_F64] = "copysign";
252 Names[RTLIB::COPYSIGN_F80] = "copysignl";
253 Names[RTLIB::COPYSIGN_F128] = "copysignl";
254 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]255 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq";
256 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]257 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
258 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
259 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
James Y Knight7873fb92016-04-12 22:32:47 +0000[diff] [blame]260 if (TT.isOSDarwin()) {
261 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
262 // of the gnueabi-style __gnu_*_ieee.
263 // FIXME: What about other targets?
264 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2";
265 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2";
266 } else {
267 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
268 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
269 }
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]270 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
271 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
272 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
273 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]274 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
275 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
276 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]277 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]278 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
279 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]280 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]281 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
282 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
283 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]284 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
285 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
286 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
287 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
288 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
289 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
290 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
291 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
292 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]293 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]294 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
295 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]296 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
297 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
298 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]299 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
300 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
301 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
302 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
303 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
304 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
305 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
306 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
307 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
308 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
309 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
310 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
311 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
312 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
313 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
314 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]315 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]316 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
317 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
318 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
319 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
320 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
321 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
322 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
323 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
324 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
325 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
326 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
327 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
328 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
329 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]330 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]331 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
332 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
333 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
334 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
335 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
336 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
337 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
338 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
339 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
340 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
341 Names[RTLIB::OEQ_F32] = "__eqsf2";
342 Names[RTLIB::OEQ_F64] = "__eqdf2";
343 Names[RTLIB::OEQ_F128] = "__eqtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]344 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]345 Names[RTLIB::UNE_F32] = "__nesf2";
346 Names[RTLIB::UNE_F64] = "__nedf2";
347 Names[RTLIB::UNE_F128] = "__netf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]348 Names[RTLIB::UNE_PPCF128] = "__gcc_qne";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]349 Names[RTLIB::OGE_F32] = "__gesf2";
350 Names[RTLIB::OGE_F64] = "__gedf2";
351 Names[RTLIB::OGE_F128] = "__getf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]352 Names[RTLIB::OGE_PPCF128] = "__gcc_qge";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]353 Names[RTLIB::OLT_F32] = "__ltsf2";
354 Names[RTLIB::OLT_F64] = "__ltdf2";
355 Names[RTLIB::OLT_F128] = "__lttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]356 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]357 Names[RTLIB::OLE_F32] = "__lesf2";
358 Names[RTLIB::OLE_F64] = "__ledf2";
359 Names[RTLIB::OLE_F128] = "__letf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]360 Names[RTLIB::OLE_PPCF128] = "__gcc_qle";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]361 Names[RTLIB::OGT_F32] = "__gtsf2";
362 Names[RTLIB::OGT_F64] = "__gtdf2";
363 Names[RTLIB::OGT_F128] = "__gttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]364 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]365 Names[RTLIB::UO_F32] = "__unordsf2";
366 Names[RTLIB::UO_F64] = "__unorddf2";
367 Names[RTLIB::UO_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]368 Names[RTLIB::UO_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]369 Names[RTLIB::O_F32] = "__unordsf2";
370 Names[RTLIB::O_F64] = "__unorddf2";
371 Names[RTLIB::O_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]372 Names[RTLIB::O_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]373 Names[RTLIB::MEMCPY] = "memcpy";
374 Names[RTLIB::MEMMOVE] = "memmove";
375 Names[RTLIB::MEMSET] = "memset";
Igor Laevsky4f31e522016-12-29 14:31:07 +0000[diff] [blame]376 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_1] = "__llvm_memcpy_element_atomic_1";
377 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_2] = "__llvm_memcpy_element_atomic_2";
378 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_4] = "__llvm_memcpy_element_atomic_4";
379 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_8] = "__llvm_memcpy_element_atomic_8";
380 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_16] = "__llvm_memcpy_element_atomic_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]381 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
382 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
383 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
384 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
385 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]386 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]387 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
388 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
389 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
390 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]391 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]392 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
393 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
394 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
395 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]396 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]397 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
398 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
399 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
400 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]401 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]402 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
403 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
404 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
405 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]406 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]407 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
408 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
409 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
410 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]411 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]412 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
413 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
414 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
415 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]416 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]417 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
418 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
419 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
420 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]421 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]422 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
423 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
424 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
425 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
426 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
427 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
428 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
429 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
430 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
431 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
432 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
433 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
434 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
435 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
436 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
437 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
438 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
439 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
440 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
441 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
James Y Knight19f6cce2016-04-12 20:18:48 +0000[diff] [blame]442
443 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load";
444 Names[RTLIB::ATOMIC_LOAD_1] = "__atomic_load_1";
445 Names[RTLIB::ATOMIC_LOAD_2] = "__atomic_load_2";
446 Names[RTLIB::ATOMIC_LOAD_4] = "__atomic_load_4";
447 Names[RTLIB::ATOMIC_LOAD_8] = "__atomic_load_8";
448 Names[RTLIB::ATOMIC_LOAD_16] = "__atomic_load_16";
449
450 Names[RTLIB::ATOMIC_STORE] = "__atomic_store";
451 Names[RTLIB::ATOMIC_STORE_1] = "__atomic_store_1";
452 Names[RTLIB::ATOMIC_STORE_2] = "__atomic_store_2";
453 Names[RTLIB::ATOMIC_STORE_4] = "__atomic_store_4";
454 Names[RTLIB::ATOMIC_STORE_8] = "__atomic_store_8";
455 Names[RTLIB::ATOMIC_STORE_16] = "__atomic_store_16";
456
457 Names[RTLIB::ATOMIC_EXCHANGE] = "__atomic_exchange";
458 Names[RTLIB::ATOMIC_EXCHANGE_1] = "__atomic_exchange_1";
459 Names[RTLIB::ATOMIC_EXCHANGE_2] = "__atomic_exchange_2";
460 Names[RTLIB::ATOMIC_EXCHANGE_4] = "__atomic_exchange_4";
461 Names[RTLIB::ATOMIC_EXCHANGE_8] = "__atomic_exchange_8";
462 Names[RTLIB::ATOMIC_EXCHANGE_16] = "__atomic_exchange_16";
463
464 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE] = "__atomic_compare_exchange";
465 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_1] = "__atomic_compare_exchange_1";
466 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_2] = "__atomic_compare_exchange_2";
467 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_4] = "__atomic_compare_exchange_4";
468 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_8] = "__atomic_compare_exchange_8";
469 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_16] = "__atomic_compare_exchange_16";
470
471 Names[RTLIB::ATOMIC_FETCH_ADD_1] = "__atomic_fetch_add_1";
472 Names[RTLIB::ATOMIC_FETCH_ADD_2] = "__atomic_fetch_add_2";
473 Names[RTLIB::ATOMIC_FETCH_ADD_4] = "__atomic_fetch_add_4";
474 Names[RTLIB::ATOMIC_FETCH_ADD_8] = "__atomic_fetch_add_8";
475 Names[RTLIB::ATOMIC_FETCH_ADD_16] = "__atomic_fetch_add_16";
476 Names[RTLIB::ATOMIC_FETCH_SUB_1] = "__atomic_fetch_sub_1";
477 Names[RTLIB::ATOMIC_FETCH_SUB_2] = "__atomic_fetch_sub_2";
478 Names[RTLIB::ATOMIC_FETCH_SUB_4] = "__atomic_fetch_sub_4";
479 Names[RTLIB::ATOMIC_FETCH_SUB_8] = "__atomic_fetch_sub_8";
480 Names[RTLIB::ATOMIC_FETCH_SUB_16] = "__atomic_fetch_sub_16";
481 Names[RTLIB::ATOMIC_FETCH_AND_1] = "__atomic_fetch_and_1";
482 Names[RTLIB::ATOMIC_FETCH_AND_2] = "__atomic_fetch_and_2";
483 Names[RTLIB::ATOMIC_FETCH_AND_4] = "__atomic_fetch_and_4";
484 Names[RTLIB::ATOMIC_FETCH_AND_8] = "__atomic_fetch_and_8";
485 Names[RTLIB::ATOMIC_FETCH_AND_16] = "__atomic_fetch_and_16";
486 Names[RTLIB::ATOMIC_FETCH_OR_1] = "__atomic_fetch_or_1";
487 Names[RTLIB::ATOMIC_FETCH_OR_2] = "__atomic_fetch_or_2";
488 Names[RTLIB::ATOMIC_FETCH_OR_4] = "__atomic_fetch_or_4";
489 Names[RTLIB::ATOMIC_FETCH_OR_8] = "__atomic_fetch_or_8";
490 Names[RTLIB::ATOMIC_FETCH_OR_16] = "__atomic_fetch_or_16";
491 Names[RTLIB::ATOMIC_FETCH_XOR_1] = "__atomic_fetch_xor_1";
492 Names[RTLIB::ATOMIC_FETCH_XOR_2] = "__atomic_fetch_xor_2";
493 Names[RTLIB::ATOMIC_FETCH_XOR_4] = "__atomic_fetch_xor_4";
494 Names[RTLIB::ATOMIC_FETCH_XOR_8] = "__atomic_fetch_xor_8";
495 Names[RTLIB::ATOMIC_FETCH_XOR_16] = "__atomic_fetch_xor_16";
496 Names[RTLIB::ATOMIC_FETCH_NAND_1] = "__atomic_fetch_nand_1";
497 Names[RTLIB::ATOMIC_FETCH_NAND_2] = "__atomic_fetch_nand_2";
498 Names[RTLIB::ATOMIC_FETCH_NAND_4] = "__atomic_fetch_nand_4";
499 Names[RTLIB::ATOMIC_FETCH_NAND_8] = "__atomic_fetch_nand_8";
500 Names[RTLIB::ATOMIC_FETCH_NAND_16] = "__atomic_fetch_nand_16";
501
Daniel Sandersbf2c03e2016-06-21 12:29:03 +0000[diff] [blame]502 if (TT.isGNUEnvironment()) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]503 Names[RTLIB::SINCOS_F32] = "sincosf";
504 Names[RTLIB::SINCOS_F64] = "sincos";
505 Names[RTLIB::SINCOS_F80] = "sincosl";
506 Names[RTLIB::SINCOS_F128] = "sincosl";
507 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]508 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]509
Simon Pilgrim2bfd9122014-11-29 19:18:21 +0000[diff] [blame]510 if (!TT.isOSOpenBSD()) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]511 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
Ahmed Bougacha6402ad22015-05-14 01:00:51 +0000[diff] [blame]512 }
Sanjoy Dasdf9ae702016-03-24 20:23:29 +0000[diff] [blame]513
514 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]515}
516
Saleem Abdulrasool02d98512016-09-07 17:56:09 +0000[diff] [blame]517/// Set default libcall CallingConvs.
Saleem Abdulrasool92e33a32016-09-09 20:11:31 +0000[diff] [blame]518static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
Saleem Abdulrasool02d98512016-09-07 17:56:09 +0000[diff] [blame]519 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
520 CCs[LC] = CallingConv::C;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]521}
522
523/// getFPEXT - Return the FPEXT_*_* value for the given types, or
524/// UNKNOWN_LIBCALL if there is none.
525RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Tim Northoverf7a02c12014-07-21 09:13:56 +0000[diff] [blame]526 if (OpVT == MVT::f16) {
527 if (RetVT == MVT::f32)
528 return FPEXT_F16_F32;
529 } else if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]530 if (RetVT == MVT::f64)
531 return FPEXT_F32_F64;
532 if (RetVT == MVT::f128)
533 return FPEXT_F32_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]534 if (RetVT == MVT::ppcf128)
535 return FPEXT_F32_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]536 } else if (OpVT == MVT::f64) {
537 if (RetVT == MVT::f128)
538 return FPEXT_F64_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]539 else if (RetVT == MVT::ppcf128)
540 return FPEXT_F64_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]541 }
542
543 return UNKNOWN_LIBCALL;
544}
545
546/// getFPROUND - Return the FPROUND_*_* value for the given types, or
547/// UNKNOWN_LIBCALL if there is none.
548RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]549 if (RetVT == MVT::f16) {
550 if (OpVT == MVT::f32)
551 return FPROUND_F32_F16;
552 if (OpVT == MVT::f64)
553 return FPROUND_F64_F16;
554 if (OpVT == MVT::f80)
555 return FPROUND_F80_F16;
556 if (OpVT == MVT::f128)
557 return FPROUND_F128_F16;
558 if (OpVT == MVT::ppcf128)
559 return FPROUND_PPCF128_F16;
560 } else if (RetVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]561 if (OpVT == MVT::f64)
562 return FPROUND_F64_F32;
563 if (OpVT == MVT::f80)
564 return FPROUND_F80_F32;
565 if (OpVT == MVT::f128)
566 return FPROUND_F128_F32;
567 if (OpVT == MVT::ppcf128)
568 return FPROUND_PPCF128_F32;
569 } else if (RetVT == MVT::f64) {
570 if (OpVT == MVT::f80)
571 return FPROUND_F80_F64;
572 if (OpVT == MVT::f128)
573 return FPROUND_F128_F64;
574 if (OpVT == MVT::ppcf128)
575 return FPROUND_PPCF128_F64;
576 }
577
578 return UNKNOWN_LIBCALL;
579}
580
581/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
582/// UNKNOWN_LIBCALL if there is none.
583RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
584 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]585 if (RetVT == MVT::i32)
586 return FPTOSINT_F32_I32;
587 if (RetVT == MVT::i64)
588 return FPTOSINT_F32_I64;
589 if (RetVT == MVT::i128)
590 return FPTOSINT_F32_I128;
591 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]592 if (RetVT == MVT::i32)
593 return FPTOSINT_F64_I32;
594 if (RetVT == MVT::i64)
595 return FPTOSINT_F64_I64;
596 if (RetVT == MVT::i128)
597 return FPTOSINT_F64_I128;
598 } else if (OpVT == MVT::f80) {
599 if (RetVT == MVT::i32)
600 return FPTOSINT_F80_I32;
601 if (RetVT == MVT::i64)
602 return FPTOSINT_F80_I64;
603 if (RetVT == MVT::i128)
604 return FPTOSINT_F80_I128;
605 } else if (OpVT == MVT::f128) {
606 if (RetVT == MVT::i32)
607 return FPTOSINT_F128_I32;
608 if (RetVT == MVT::i64)
609 return FPTOSINT_F128_I64;
610 if (RetVT == MVT::i128)
611 return FPTOSINT_F128_I128;
612 } else if (OpVT == MVT::ppcf128) {
613 if (RetVT == MVT::i32)
614 return FPTOSINT_PPCF128_I32;
615 if (RetVT == MVT::i64)
616 return FPTOSINT_PPCF128_I64;
617 if (RetVT == MVT::i128)
618 return FPTOSINT_PPCF128_I128;
619 }
620 return UNKNOWN_LIBCALL;
621}
622
623/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
624/// UNKNOWN_LIBCALL if there is none.
625RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
626 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]627 if (RetVT == MVT::i32)
628 return FPTOUINT_F32_I32;
629 if (RetVT == MVT::i64)
630 return FPTOUINT_F32_I64;
631 if (RetVT == MVT::i128)
632 return FPTOUINT_F32_I128;
633 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]634 if (RetVT == MVT::i32)
635 return FPTOUINT_F64_I32;
636 if (RetVT == MVT::i64)
637 return FPTOUINT_F64_I64;
638 if (RetVT == MVT::i128)
639 return FPTOUINT_F64_I128;
640 } else if (OpVT == MVT::f80) {
641 if (RetVT == MVT::i32)
642 return FPTOUINT_F80_I32;
643 if (RetVT == MVT::i64)
644 return FPTOUINT_F80_I64;
645 if (RetVT == MVT::i128)
646 return FPTOUINT_F80_I128;
647 } else if (OpVT == MVT::f128) {
648 if (RetVT == MVT::i32)
649 return FPTOUINT_F128_I32;
650 if (RetVT == MVT::i64)
651 return FPTOUINT_F128_I64;
652 if (RetVT == MVT::i128)
653 return FPTOUINT_F128_I128;
654 } else if (OpVT == MVT::ppcf128) {
655 if (RetVT == MVT::i32)
656 return FPTOUINT_PPCF128_I32;
657 if (RetVT == MVT::i64)
658 return FPTOUINT_PPCF128_I64;
659 if (RetVT == MVT::i128)
660 return FPTOUINT_PPCF128_I128;
661 }
662 return UNKNOWN_LIBCALL;
663}
664
665/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
666/// UNKNOWN_LIBCALL if there is none.
667RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
668 if (OpVT == MVT::i32) {
669 if (RetVT == MVT::f32)
670 return SINTTOFP_I32_F32;
671 if (RetVT == MVT::f64)
672 return SINTTOFP_I32_F64;
673 if (RetVT == MVT::f80)
674 return SINTTOFP_I32_F80;
675 if (RetVT == MVT::f128)
676 return SINTTOFP_I32_F128;
677 if (RetVT == MVT::ppcf128)
678 return SINTTOFP_I32_PPCF128;
679 } else if (OpVT == MVT::i64) {
680 if (RetVT == MVT::f32)
681 return SINTTOFP_I64_F32;
682 if (RetVT == MVT::f64)
683 return SINTTOFP_I64_F64;
684 if (RetVT == MVT::f80)
685 return SINTTOFP_I64_F80;
686 if (RetVT == MVT::f128)
687 return SINTTOFP_I64_F128;
688 if (RetVT == MVT::ppcf128)
689 return SINTTOFP_I64_PPCF128;
690 } else if (OpVT == MVT::i128) {
691 if (RetVT == MVT::f32)
692 return SINTTOFP_I128_F32;
693 if (RetVT == MVT::f64)
694 return SINTTOFP_I128_F64;
695 if (RetVT == MVT::f80)
696 return SINTTOFP_I128_F80;
697 if (RetVT == MVT::f128)
698 return SINTTOFP_I128_F128;
699 if (RetVT == MVT::ppcf128)
700 return SINTTOFP_I128_PPCF128;
701 }
702 return UNKNOWN_LIBCALL;
703}
704
705/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
706/// UNKNOWN_LIBCALL if there is none.
707RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
708 if (OpVT == MVT::i32) {
709 if (RetVT == MVT::f32)
710 return UINTTOFP_I32_F32;
711 if (RetVT == MVT::f64)
712 return UINTTOFP_I32_F64;
713 if (RetVT == MVT::f80)
714 return UINTTOFP_I32_F80;
715 if (RetVT == MVT::f128)
716 return UINTTOFP_I32_F128;
717 if (RetVT == MVT::ppcf128)
718 return UINTTOFP_I32_PPCF128;
719 } else if (OpVT == MVT::i64) {
720 if (RetVT == MVT::f32)
721 return UINTTOFP_I64_F32;
722 if (RetVT == MVT::f64)
723 return UINTTOFP_I64_F64;
724 if (RetVT == MVT::f80)
725 return UINTTOFP_I64_F80;
726 if (RetVT == MVT::f128)
727 return UINTTOFP_I64_F128;
728 if (RetVT == MVT::ppcf128)
729 return UINTTOFP_I64_PPCF128;
730 } else if (OpVT == MVT::i128) {
731 if (RetVT == MVT::f32)
732 return UINTTOFP_I128_F32;
733 if (RetVT == MVT::f64)
734 return UINTTOFP_I128_F64;
735 if (RetVT == MVT::f80)
736 return UINTTOFP_I128_F80;
737 if (RetVT == MVT::f128)
738 return UINTTOFP_I128_F128;
739 if (RetVT == MVT::ppcf128)
740 return UINTTOFP_I128_PPCF128;
741 }
742 return UNKNOWN_LIBCALL;
743}
744
James Y Knightf44fc522016-03-16 22:12:04 +0000[diff] [blame]745RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
Benjamin Kramerc54c38e2015-03-05 20:04:29 +0000[diff] [blame]746#define OP_TO_LIBCALL(Name, Enum) \
747 case Name: \
748 switch (VT.SimpleTy) { \
749 default: \
750 return UNKNOWN_LIBCALL; \
751 case MVT::i8: \
752 return Enum##_1; \
753 case MVT::i16: \
754 return Enum##_2; \
755 case MVT::i32: \
756 return Enum##_4; \
757 case MVT::i64: \
758 return Enum##_8; \
759 case MVT::i128: \
760 return Enum##_16; \
761 }
762
763 switch (Opc) {
764 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
765 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
766 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
767 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
768 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
769 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
770 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
771 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
772 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
773 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
774 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
775 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
776 }
777
778#undef OP_TO_LIBCALL
779
780 return UNKNOWN_LIBCALL;
781}
782
Igor Laevsky4f31e522016-12-29 14:31:07 +0000[diff] [blame]783RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_ATOMIC(uint64_t ElementSize) {
784 switch (ElementSize) {
785 case 1:
786 return MEMCPY_ELEMENT_ATOMIC_1;
787 case 2:
788 return MEMCPY_ELEMENT_ATOMIC_2;
789 case 4:
790 return MEMCPY_ELEMENT_ATOMIC_4;
791 case 8:
792 return MEMCPY_ELEMENT_ATOMIC_8;
793 case 16:
794 return MEMCPY_ELEMENT_ATOMIC_16;
795 default:
796 return UNKNOWN_LIBCALL;
797 }
798
799}
800
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]801/// InitCmpLibcallCCs - Set default comparison libcall CC.
802///
803static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
804 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
805 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
806 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
807 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]808 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]809 CCs[RTLIB::UNE_F32] = ISD::SETNE;
810 CCs[RTLIB::UNE_F64] = ISD::SETNE;
811 CCs[RTLIB::UNE_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]812 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]813 CCs[RTLIB::OGE_F32] = ISD::SETGE;
814 CCs[RTLIB::OGE_F64] = ISD::SETGE;
815 CCs[RTLIB::OGE_F128] = ISD::SETGE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]816 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]817 CCs[RTLIB::OLT_F32] = ISD::SETLT;
818 CCs[RTLIB::OLT_F64] = ISD::SETLT;
819 CCs[RTLIB::OLT_F128] = ISD::SETLT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]820 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]821 CCs[RTLIB::OLE_F32] = ISD::SETLE;
822 CCs[RTLIB::OLE_F64] = ISD::SETLE;
823 CCs[RTLIB::OLE_F128] = ISD::SETLE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]824 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]825 CCs[RTLIB::OGT_F32] = ISD::SETGT;
826 CCs[RTLIB::OGT_F64] = ISD::SETGT;
827 CCs[RTLIB::OGT_F128] = ISD::SETGT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]828 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]829 CCs[RTLIB::UO_F32] = ISD::SETNE;
830 CCs[RTLIB::UO_F64] = ISD::SETNE;
831 CCs[RTLIB::UO_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]832 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]833 CCs[RTLIB::O_F32] = ISD::SETEQ;
834 CCs[RTLIB::O_F64] = ISD::SETEQ;
835 CCs[RTLIB::O_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]836 CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]837}
838
Aditya Nandakumar30531552014-11-13 21:29:21 +0000[diff] [blame]839/// NOTE: The TargetMachine owns TLOF.
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]840TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]841 initActions();
842
843 // Perform these initializations only once.
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]844 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
845 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
846 = MaxStoresPerMemmoveOptSize = 4;
847 UseUnderscoreSetJmp = false;
848 UseUnderscoreLongJmp = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]849 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]850 HasExtractBitsInsn = false;
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]851 JumpIsExpensive = JumpIsExpensiveOverride;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]852 PredictableSelectIsExpensive = false;
Quentin Colombetfc2201e2014-12-17 01:36:17 +0000[diff] [blame]853 EnableExtLdPromotion = false;
Pedro Artigascaa56582014-08-08 16:46:53 +0000[diff] [blame]854 HasFloatingPointExceptions = true;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]855 StackPointerRegisterToSaveRestore = 0;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]856 BooleanContents = UndefinedBooleanContent;
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]857 BooleanFloatContents = UndefinedBooleanContent;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]858 BooleanVectorContents = UndefinedBooleanContent;
859 SchedPreferenceInfo = Sched::ILP;
860 JumpBufSize = 0;
861 JumpBufAlignment = 0;
862 MinFunctionAlignment = 0;
863 PrefFunctionAlignment = 0;
864 PrefLoopAlignment = 0;
Nirav Dave54e22f32017-03-14 00:34:14 +0000[diff] [blame]865 GatherAllAliasesMaxDepth = 18;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]866 MinStackArgumentAlignment = 1;
James Y Knight19f6cce2016-04-12 20:18:48 +0000[diff] [blame]867 // TODO: the default will be switched to 0 in the next commit, along
868 // with the Target-specific changes necessary.
869 MaxAtomicSizeInBitsSupported = 1024;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]870
James Y Knight148a6462016-06-17 18:11:48 +0000[diff] [blame]871 MinCmpXchgSizeInBits = 0;
872
James Y Knight7873fb92016-04-12 22:32:47 +0000[diff] [blame]873 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
874
Daniel Sanders110bf6d2015-06-24 13:25:57 +0000[diff] [blame]875 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple());
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]876 InitCmpLibcallCCs(CmpLibcallCCs);
Saleem Abdulrasool92e33a32016-09-09 20:11:31 +0000[diff] [blame]877 InitLibcallCallingConvs(LibcallCallingConvs);
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]878}
879
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]880void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]881 // All operations default to being supported.
882 memset(OpActions, 0, sizeof(OpActions));
883 memset(LoadExtActions, 0, sizeof(LoadExtActions));
884 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
885 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
886 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Craig Topper00230802016-04-08 07:10:46 +0000[diff] [blame]887 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
888 std::fill(std::begin(TargetDAGCombineArray),
889 std::end(TargetDAGCombineArray), 0);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]890
891 // Set default actions for various operations.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]892 for (MVT VT : MVT::all_valuetypes()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]893 // Default all indexed load / store to expand.
894 for (unsigned IM = (unsigned)ISD::PRE_INC;
895 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]896 setIndexedLoadAction(IM, VT, Expand);
897 setIndexedStoreAction(IM, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]898 }
899
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]900 // Most backends expect to see the node which just returns the value loaded.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]901 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]902
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]903 // These operations default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]904 setOperationAction(ISD::FGETSIGN, VT, Expand);
905 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
906 setOperationAction(ISD::FMINNUM, VT, Expand);
907 setOperationAction(ISD::FMAXNUM, VT, Expand);
James Molloy01cdecc2015-08-11 09:13:05 +0000[diff] [blame]908 setOperationAction(ISD::FMINNAN, VT, Expand);
909 setOperationAction(ISD::FMAXNAN, VT, Expand);
Matt Arsenault0dc54c42015-02-20 22:10:33 +0000[diff] [blame]910 setOperationAction(ISD::FMAD, VT, Expand);
James Molloy7e9776b2015-05-15 09:03:15 +0000[diff] [blame]911 setOperationAction(ISD::SMIN, VT, Expand);
912 setOperationAction(ISD::SMAX, VT, Expand);
913 setOperationAction(ISD::UMIN, VT, Expand);
914 setOperationAction(ISD::UMAX, VT, Expand);
Simon Pilgrimcf2da962017-03-14 21:26:58 +0000[diff] [blame]915 setOperationAction(ISD::ABS, VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]916
Jan Vesely75395482015-04-29 16:30:46 +0000[diff] [blame]917 // Overflow operations default to expand
918 setOperationAction(ISD::SADDO, VT, Expand);
919 setOperationAction(ISD::SSUBO, VT, Expand);
920 setOperationAction(ISD::UADDO, VT, Expand);
921 setOperationAction(ISD::USUBO, VT, Expand);
922 setOperationAction(ISD::SMULO, VT, Expand);
923 setOperationAction(ISD::UMULO, VT, Expand);
Hal Finkelcd8664c2015-12-11 23:11:52 +0000[diff] [blame]924
Craig Topper33772c52016-04-28 03:34:31 +0000[diff] [blame]925 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
926 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
927 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
928
James Molloy90111f72015-11-12 12:29:09 +0000[diff] [blame]929 setOperationAction(ISD::BITREVERSE, VT, Expand);
930
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]931 // These library functions default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]932 setOperationAction(ISD::FROUND, VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]933
934 // These operations default to expand for vector types.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]935 if (VT.isVector()) {
936 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
937 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
938 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
939 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]940 }
Yury Gribovd7dbb662015-12-01 11:40:55 +0000[diff] [blame]941
Etienne Bergeron22bfa832016-06-07 20:15:35 +0000[diff] [blame]942 // For most targets @llvm.get.dynamic.area.offset just returns 0.
Yury Gribovd7dbb662015-12-01 11:40:55 +0000[diff] [blame]943 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]944 }
945
946 // Most targets ignore the @llvm.prefetch intrinsic.
947 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
948
Ahmed Bougachaf9c19da2015-08-28 01:49:59 +0000[diff] [blame]949 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
950 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand);
951
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]952 // ConstantFP nodes default to expand. Targets can either change this to
953 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
954 // to optimize expansions for certain constants.
955 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
956 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
957 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
958 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
959 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
960
961 // These library functions default to expand.
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]962 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
963 setOperationAction(ISD::FLOG , VT, Expand);
964 setOperationAction(ISD::FLOG2, VT, Expand);
965 setOperationAction(ISD::FLOG10, VT, Expand);
966 setOperationAction(ISD::FEXP , VT, Expand);
967 setOperationAction(ISD::FEXP2, VT, Expand);
968 setOperationAction(ISD::FFLOOR, VT, Expand);
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]969 setOperationAction(ISD::FNEARBYINT, VT, Expand);
970 setOperationAction(ISD::FCEIL, VT, Expand);
971 setOperationAction(ISD::FRINT, VT, Expand);
972 setOperationAction(ISD::FTRUNC, VT, Expand);
973 setOperationAction(ISD::FROUND, VT, Expand);
974 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]975
976 // Default ISD::TRAP to expand (which turns it into abort).
977 setOperationAction(ISD::TRAP, MVT::Other, Expand);
978
979 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
980 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
981 //
982 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]983}
984
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]985MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
986 EVT) const {
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]987 return MVT::getIntegerVT(8 * DL.getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]988}
989
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]990EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
991 const DataLayout &DL) const {
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]992 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
993 if (LHSTy.isVector())
994 return LHSTy;
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]995 return getScalarShiftAmountTy(DL, LHSTy);
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]996}
997
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]998bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
999 assert(isTypeLegal(VT));
1000 switch (Op) {
1001 default:
1002 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1003 case ISD::SDIV:
1004 case ISD::UDIV:
1005 case ISD::SREM:
1006 case ISD::UREM:
1007 return true;
1008 }
1009}
1010
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]1011void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1012 // If the command-line option was specified, ignore this request.
1013 if (!JumpIsExpensiveOverride.getNumOccurrences())
1014 JumpIsExpensive = isExpensive;
1015}
1016
Eric Christopher75dbd7c2015-02-25 22:41:30 +0000[diff] [blame]1017TargetLoweringBase::LegalizeKind
1018TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1019 // If this is a simple type, use the ComputeRegisterProp mechanism.
1020 if (VT.isSimple()) {
1021 MVT SVT = VT.getSimpleVT();
1022 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1023 MVT NVT = TransformToType[SVT.SimpleTy];
1024 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1025
1026 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1027 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
1028 "Promote may not follow Expand or Promote");
1029
1030 if (LA == TypeSplitVector)
1031 return LegalizeKind(LA,
1032 EVT::getVectorVT(Context, SVT.getVectorElementType(),
1033 SVT.getVectorNumElements() / 2));
1034 if (LA == TypeScalarizeVector)
1035 return LegalizeKind(LA, SVT.getVectorElementType());
1036 return LegalizeKind(LA, NVT);
1037 }
1038
1039 // Handle Extended Scalar Types.
1040 if (!VT.isVector()) {
1041 assert(VT.isInteger() && "Float types must be simple");
1042 unsigned BitSize = VT.getSizeInBits();
1043 // First promote to a power-of-two size, then expand if necessary.
1044 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1045 EVT NVT = VT.getRoundIntegerType(Context);
1046 assert(NVT != VT && "Unable to round integer VT");
1047 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1048 // Avoid multi-step promotion.
1049 if (NextStep.first == TypePromoteInteger)
1050 return NextStep;
1051 // Return rounded integer type.
1052 return LegalizeKind(TypePromoteInteger, NVT);
1053 }
1054
1055 return LegalizeKind(TypeExpandInteger,
1056 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
1057 }
1058
1059 // Handle vector types.
1060 unsigned NumElts = VT.getVectorNumElements();
1061 EVT EltVT = VT.getVectorElementType();
1062
1063 // Vectors with only one element are always scalarized.
1064 if (NumElts == 1)
1065 return LegalizeKind(TypeScalarizeVector, EltVT);
1066
1067 // Try to widen vector elements until the element type is a power of two and
1068 // promote it to a legal type later on, for example:
1069 // <3 x i8> -> <4 x i8> -> <4 x i32>
1070 if (EltVT.isInteger()) {
1071 // Vectors with a number of elements that is not a power of two are always
1072 // widened, for example <3 x i8> -> <4 x i8>.
1073 if (!VT.isPow2VectorType()) {
1074 NumElts = (unsigned)NextPowerOf2(NumElts);
1075 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1076 return LegalizeKind(TypeWidenVector, NVT);
1077 }
1078
1079 // Examine the element type.
1080 LegalizeKind LK = getTypeConversion(Context, EltVT);
1081
1082 // If type is to be expanded, split the vector.
1083 // <4 x i140> -> <2 x i140>
1084 if (LK.first == TypeExpandInteger)
1085 return LegalizeKind(TypeSplitVector,
1086 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1087
1088 // Promote the integer element types until a legal vector type is found
1089 // or until the element integer type is too big. If a legal type was not
1090 // found, fallback to the usual mechanism of widening/splitting the
1091 // vector.
1092 EVT OldEltVT = EltVT;
1093 while (1) {
1094 // Increase the bitwidth of the element to the next pow-of-two
1095 // (which is greater than 8 bits).
1096 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1097 .getRoundIntegerType(Context);
1098
1099 // Stop trying when getting a non-simple element type.
1100 // Note that vector elements may be greater than legal vector element
1101 // types. Example: X86 XMM registers hold 64bit element on 32bit
1102 // systems.
1103 if (!EltVT.isSimple())
1104 break;
1105
1106 // Build a new vector type and check if it is legal.
1107 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1108 // Found a legal promoted vector type.
1109 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1110 return LegalizeKind(TypePromoteInteger,
1111 EVT::getVectorVT(Context, EltVT, NumElts));
1112 }
1113
1114 // Reset the type to the unexpanded type if we did not find a legal vector
1115 // type with a promoted vector element type.
1116 EltVT = OldEltVT;
1117 }
1118
1119 // Try to widen the vector until a legal type is found.
1120 // If there is no wider legal type, split the vector.
1121 while (1) {
1122 // Round up to the next power of 2.
1123 NumElts = (unsigned)NextPowerOf2(NumElts);
1124
1125 // If there is no simple vector type with this many elements then there
1126 // cannot be a larger legal vector type. Note that this assumes that
1127 // there are no skipped intermediate vector types in the simple types.
1128 if (!EltVT.isSimple())
1129 break;
1130 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1131 if (LargerVector == MVT())
1132 break;
1133
1134 // If this type is legal then widen the vector.
1135 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1136 return LegalizeKind(TypeWidenVector, LargerVector);
1137 }
1138
1139 // Widen odd vectors to next power of two.
1140 if (!VT.isPow2VectorType()) {
1141 EVT NVT = VT.getPow2VectorType(Context);
1142 return LegalizeKind(TypeWidenVector, NVT);
1143 }
1144
1145 // Vectors with illegal element types are expanded.
1146 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1147 return LegalizeKind(TypeSplitVector, NVT);
1148}
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1149
1150static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1151 unsigned &NumIntermediates,
1152 MVT &RegisterVT,
1153 TargetLoweringBase *TLI) {
1154 // Figure out the right, legal destination reg to copy into.
1155 unsigned NumElts = VT.getVectorNumElements();
1156 MVT EltTy = VT.getVectorElementType();
1157
1158 unsigned NumVectorRegs = 1;
1159
1160 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1161 // could break down into LHS/RHS like LegalizeDAG does.
1162 if (!isPowerOf2_32(NumElts)) {
1163 NumVectorRegs = NumElts;
1164 NumElts = 1;
1165 }
1166
1167 // Divide the input until we get to a supported size. This will always
1168 // end with a scalar if the target doesn't support vectors.
1169 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
1170 NumElts >>= 1;
1171 NumVectorRegs <<= 1;
1172 }
1173
1174 NumIntermediates = NumVectorRegs;
1175
1176 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
1177 if (!TLI->isTypeLegal(NewVT))
1178 NewVT = EltTy;
1179 IntermediateVT = NewVT;
1180
1181 unsigned NewVTSize = NewVT.getSizeInBits();
1182
1183 // Convert sizes such as i33 to i64.
1184 if (!isPowerOf2_32(NewVTSize))
1185 NewVTSize = NextPowerOf2(NewVTSize);
1186
1187 MVT DestVT = TLI->getRegisterType(NewVT);
1188 RegisterVT = DestVT;
1189 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1190 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1191
1192 // Otherwise, promotion or legal types use the same number of registers as
1193 // the vector decimated to the appropriate level.
1194 return NumVectorRegs;
1195}
1196
1197/// isLegalRC - Return true if the value types that can be represented by the
1198/// specified register class are all legal.
Krzysztof Parzyszekc8e8e2a2017-04-24 19:51:12 +0000[diff] [blame]1199bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1200 const TargetRegisterClass &RC) const {
1201 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1202 if (isTypeLegal(*I))
1203 return true;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1204 return false;
1205}
1206
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1207/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1208/// sequence of memory operands that is recognized by PrologEpilogInserter.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]1209MachineBasicBlock *
1210TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1211 MachineBasicBlock *MBB) const {
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]1212 MachineInstr *MI = &InitialMI;
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1213 MachineFunction &MF = *MI->getParent()->getParent();
Matthias Braun941a7052016-07-28 18:40:00 +0000[diff] [blame]1214 MachineFrameInfo &MFI = MF.getFrameInfo();
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1215
1216 // We're handling multiple types of operands here:
1217 // PATCHPOINT MetaArgs - live-in, read only, direct
1218 // STATEPOINT Deopt Spill - live-through, read only, indirect
1219 // STATEPOINT Deopt Alloca - live-through, read only, direct
1220 // (We're currently conservative and mark the deopt slots read/write in
1221 // practice.)
1222 // STATEPOINT GC Spill - live-through, read/write, indirect
1223 // STATEPOINT GC Alloca - live-through, read/write, direct
1224 // The live-in vs live-through is handled already (the live through ones are
1225 // all stack slots), but we need to handle the different type of stackmap
1226 // operands and memory effects here.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1227
1228 // MI changes inside this loop as we grow operands.
1229 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1230 MachineOperand &MO = MI->getOperand(OperIdx);
1231 if (!MO.isFI())
1232 continue;
1233
1234 // foldMemoryOperand builds a new MI after replacing a single FI operand
1235 // with the canonical set of five x86 addressing-mode operands.
1236 int FI = MO.getIndex();
1237 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1238
1239 // Copy operands before the frame-index.
1240 for (unsigned i = 0; i < OperIdx; ++i)
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1241 MIB.add(MI->getOperand(i));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1242 // Add frame index operands recognized by stackmaps.cpp
1243 if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1244 // indirect-mem-ref tag, size, #FI, offset.
1245 // Used for spills inserted by StatepointLowering. This codepath is not
1246 // used for patchpoints/stackmaps at all, for these spilling is done via
1247 // foldMemoryOperand callback only.
1248 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1249 MIB.addImm(StackMaps::IndirectMemRefOp);
1250 MIB.addImm(MFI.getObjectSize(FI));
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1251 MIB.add(MI->getOperand(OperIdx));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1252 MIB.addImm(0);
1253 } else {
1254 // direct-mem-ref tag, #FI, offset.
1255 // Used by patchpoint, and direct alloca arguments to statepoints
1256 MIB.addImm(StackMaps::DirectMemRefOp);
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1257 MIB.add(MI->getOperand(OperIdx));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1258 MIB.addImm(0);
1259 }
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1260 // Copy the operands after the frame index.
1261 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1262 MIB.add(MI->getOperand(i));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1263
1264 // Inherit previous memory operands.
1265 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1266 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1267
1268 // Add a new memory operand for this FI.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1269 assert(MFI.getObjectOffset(FI) != -1);
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1270
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]1271 auto Flags = MachineMemOperand::MOLoad;
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1272 if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
1273 Flags |= MachineMemOperand::MOStore;
1274 Flags |= MachineMemOperand::MOVolatile;
1275 }
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]1276 MachineMemOperand *MMO = MF.getMachineMemOperand(
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]1277 MachinePointerInfo::getFixedStack(MF, FI), Flags,
Mehdi Aminibd7287e2015-07-16 06:11:10 +0000[diff] [blame]1278 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1279 MIB->addMemOperand(MF, MMO);
1280
1281 // Replace the instruction and update the operand index.
1282 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1283 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1284 MI->eraseFromParent();
1285 MI = MIB;
1286 }
1287 return MBB;
1288}
1289
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1290/// findRepresentativeClass - Return the largest legal super-reg register class
1291/// of the register class for the specified type and its associated "cost".
Eric Christopher720ab842015-03-03 19:47:14 +0000[diff] [blame]1292// This function is in TargetLowering because it uses RegClassForVT which would
1293// need to be moved to TargetRegisterInfo and would necessitate moving
1294// isTypeLegal over as well - a massive change that would just require
1295// TargetLowering having a TargetRegisterInfo class member that it would use.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1296std::pair<const TargetRegisterClass *, uint8_t>
1297TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1298 MVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1299 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1300 if (!RC)
1301 return std::make_pair(RC, 0);
1302
1303 // Compute the set of all super-register classes.
1304 BitVector SuperRegRC(TRI->getNumRegClasses());
1305 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1306 SuperRegRC.setBitsInMask(RCI.getMask());
1307
1308 // Find the first legal register class with the largest spill size.
1309 const TargetRegisterClass *BestRC = RC;
1310 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
1311 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1312 // We want the largest possible spill size.
Krzysztof Parzyszek44e25f32017-04-24 18:55:33 +0000[diff] [blame]1313 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1314 continue;
Krzysztof Parzyszekc8e8e2a2017-04-24 19:51:12 +0000[diff] [blame]1315 if (!isLegalRC(*TRI, *SuperRC))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1316 continue;
1317 BestRC = SuperRC;
1318 }
1319 return std::make_pair(BestRC, 1);
1320}
1321
1322/// computeRegisterProperties - Once all of the register classes are added,
1323/// this allows us to compute derived properties we expose.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1324void TargetLoweringBase::computeRegisterProperties(
1325 const TargetRegisterInfo *TRI) {
Craig Topper6438fc32014-11-17 00:26:50 +0000[diff] [blame]1326 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1327 "Too many value types for ValueTypeActions to hold!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1328
1329 // Everything defaults to needing one register.
1330 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1331 NumRegistersForVT[i] = 1;
1332 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1333 }
1334 // ...except isVoid, which doesn't need any registers.
1335 NumRegistersForVT[MVT::isVoid] = 0;
1336
1337 // Find the largest integer register class.
1338 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1339 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1340 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1341
1342 // Every integer value type larger than this largest register takes twice as
1343 // many registers to represent as the previous ValueType.
1344 for (unsigned ExpandedReg = LargestIntReg + 1;
1345 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1346 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1347 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1348 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1349 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1350 TypeExpandInteger);
1351 }
1352
1353 // Inspect all of the ValueType's smaller than the largest integer
1354 // register to see which ones need promotion.
1355 unsigned LegalIntReg = LargestIntReg;
1356 for (unsigned IntReg = LargestIntReg - 1;
1357 IntReg >= (unsigned)MVT::i1; --IntReg) {
1358 MVT IVT = (MVT::SimpleValueType)IntReg;
1359 if (isTypeLegal(IVT)) {
1360 LegalIntReg = IntReg;
1361 } else {
1362 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1363 (const MVT::SimpleValueType)LegalIntReg;
1364 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1365 }
1366 }
1367
1368 // ppcf128 type is really two f64's.
1369 if (!isTypeLegal(MVT::ppcf128)) {
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]1370 if (isTypeLegal(MVT::f64)) {
1371 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1372 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1373 TransformToType[MVT::ppcf128] = MVT::f64;
1374 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1375 } else {
1376 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1377 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1378 TransformToType[MVT::ppcf128] = MVT::i128;
1379 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1380 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1381 }
1382
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1383 // Decide how to handle f128. If the target does not have native f128 support,
1384 // expand it to i128 and we will be generating soft float library calls.
1385 if (!isTypeLegal(MVT::f128)) {
1386 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1387 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1388 TransformToType[MVT::f128] = MVT::i128;
1389 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1390 }
1391
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1392 // Decide how to handle f64. If the target does not have native f64 support,
1393 // expand it to i64 and we will be generating soft float library calls.
1394 if (!isTypeLegal(MVT::f64)) {
1395 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1396 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1397 TransformToType[MVT::f64] = MVT::i64;
1398 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1399 }
1400
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1401 // Decide how to handle f32. If the target does not have native f32 support,
1402 // expand it to i32 and we will be generating soft float library calls.
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1403 if (!isTypeLegal(MVT::f32)) {
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1404 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1405 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1406 TransformToType[MVT::f32] = MVT::i32;
1407 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1408 }
1409
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1410 // Decide how to handle f16. If the target does not have native f16 support,
1411 // promote it to f32, because there are no f16 library calls (except for
1412 // conversions).
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1413 if (!isTypeLegal(MVT::f16)) {
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1414 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1415 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1416 TransformToType[MVT::f16] = MVT::f32;
1417 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1418 }
1419
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1420 // Loop over all of the vector value types to see which need transformations.
1421 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1422 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1423 MVT VT = (MVT::SimpleValueType) i;
1424 if (isTypeLegal(VT))
1425 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1426
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1427 MVT EltVT = VT.getVectorElementType();
1428 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1429 bool IsLegalWiderType = false;
1430 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1431 switch (PreferredAction) {
1432 case TypePromoteInteger: {
1433 // Try to promote the elements of integer vectors. If no legal
1434 // promotion was found, fall through to the widen-vector method.
Matt Arsenault940d19a2016-04-22 21:16:17 +0000[diff] [blame]1435 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1436 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1437 // Promote vectors of integers to vectors with the same number
1438 // of elements, with a wider element type.
Sanjay Patel1ed771f2016-09-14 16:37:15 +0000[diff] [blame]1439 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
Matt Arsenault940d19a2016-04-22 21:16:17 +0000[diff] [blame]1440 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1441 TransformToType[i] = SVT;
1442 RegisterTypeForVT[i] = SVT;
1443 NumRegistersForVT[i] = 1;
1444 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1445 IsLegalWiderType = true;
1446 break;
1447 }
1448 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1449 if (IsLegalWiderType)
1450 break;
1451 }
1452 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1453 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1454 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1455 MVT SVT = (MVT::SimpleValueType) nVT;
1456 if (SVT.getVectorElementType() == EltVT
1457 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1458 TransformToType[i] = SVT;
1459 RegisterTypeForVT[i] = SVT;
1460 NumRegistersForVT[i] = 1;
1461 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1462 IsLegalWiderType = true;
1463 break;
1464 }
1465 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1466 if (IsLegalWiderType)
1467 break;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1468 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1469 case TypeSplitVector:
1470 case TypeScalarizeVector: {
1471 MVT IntermediateVT;
1472 MVT RegisterVT;
1473 unsigned NumIntermediates;
1474 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1475 NumIntermediates, RegisterVT, this);
1476 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1477
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1478 MVT NVT = VT.getPow2VectorType();
1479 if (NVT == VT) {
1480 // Type is already a power of 2. The default action is to split.
1481 TransformToType[i] = MVT::Other;
1482 if (PreferredAction == TypeScalarizeVector)
1483 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1484 else if (PreferredAction == TypeSplitVector)
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1485 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1486 else
1487 // Set type action according to the number of elements.
1488 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1489 : TypeSplitVector);
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1490 } else {
1491 TransformToType[i] = NVT;
1492 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1493 }
1494 break;
1495 }
1496 default:
1497 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1498 }
1499 }
1500
1501 // Determine the 'representative' register class for each value type.
1502 // An representative register class is the largest (meaning one which is
1503 // not a sub-register class / subreg register class) legal register class for
1504 // a group of value types. For example, on i386, i8, i16, and i32
1505 // representative would be GR32; while on x86_64 it's GR64.
1506 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1507 const TargetRegisterClass* RRC;
1508 uint8_t Cost;
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1509 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1510 RepRegClassForVT[i] = RRC;
1511 RepRegClassCostForVT[i] = Cost;
1512 }
1513}
1514
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1515EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1516 EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1517 assert(!VT.isVector() && "No default SetCC type for vectors!");
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1518 return getPointerTy(DL).SimpleTy;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1519}
1520
1521MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1522 return MVT::i32; // return the default value
1523}
1524
1525/// getVectorTypeBreakdown - Vector types are broken down into some number of
1526/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1527/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1528/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1529///
1530/// This method returns the number of registers needed, and the VT for each
1531/// register. It also returns the VT and quantity of the intermediate values
1532/// before they are promoted/expanded.
1533///
1534unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1535 EVT &IntermediateVT,
1536 unsigned &NumIntermediates,
1537 MVT &RegisterVT) const {
1538 unsigned NumElts = VT.getVectorNumElements();
1539
1540 // If there is a wider vector type with the same element type as this one,
1541 // or a promoted vector type that has the same number of elements which
1542 // are wider, then we should convert to that legal vector type.
1543 // This handles things like <2 x float> -> <4 x float> and
1544 // <4 x i1> -> <4 x i32>.
1545 LegalizeTypeAction TA = getTypeAction(Context, VT);
1546 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1547 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1548 if (isTypeLegal(RegisterEVT)) {
1549 IntermediateVT = RegisterEVT;
1550 RegisterVT = RegisterEVT.getSimpleVT();
1551 NumIntermediates = 1;
1552 return 1;
1553 }
1554 }
1555
1556 // Figure out the right, legal destination reg to copy into.
1557 EVT EltTy = VT.getVectorElementType();
1558
1559 unsigned NumVectorRegs = 1;
1560
1561 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1562 // could break down into LHS/RHS like LegalizeDAG does.
1563 if (!isPowerOf2_32(NumElts)) {
1564 NumVectorRegs = NumElts;
1565 NumElts = 1;
1566 }
1567
1568 // Divide the input until we get to a supported size. This will always
1569 // end with a scalar if the target doesn't support vectors.
1570 while (NumElts > 1 && !isTypeLegal(
1571 EVT::getVectorVT(Context, EltTy, NumElts))) {
1572 NumElts >>= 1;
1573 NumVectorRegs <<= 1;
1574 }
1575
1576 NumIntermediates = NumVectorRegs;
1577
1578 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1579 if (!isTypeLegal(NewVT))
1580 NewVT = EltTy;
1581 IntermediateVT = NewVT;
1582
1583 MVT DestVT = getRegisterType(Context, NewVT);
1584 RegisterVT = DestVT;
1585 unsigned NewVTSize = NewVT.getSizeInBits();
1586
1587 // Convert sizes such as i33 to i64.
1588 if (!isPowerOf2_32(NewVTSize))
1589 NewVTSize = NextPowerOf2(NewVTSize);
1590
1591 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1592 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1593
1594 // Otherwise, promotion or legal types use the same number of registers as
1595 // the vector decimated to the appropriate level.
1596 return NumVectorRegs;
1597}
1598
1599/// Get the EVTs and ArgFlags collections that represent the legalized return
1600/// type of the given function. This does not require a DAG or a return value,
1601/// and is suitable for use before any DAGs for the function are constructed.
1602/// TODO: Move this out of TargetLowering.cpp.
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1603void llvm::GetReturnInfo(Type *ReturnType, AttributeList attr,
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1604 SmallVectorImpl<ISD::OutputArg> &Outs,
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1605 const TargetLowering &TLI, const DataLayout &DL) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1606 SmallVector<EVT, 4> ValueVTs;
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1607 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1608 unsigned NumValues = ValueVTs.size();
1609 if (NumValues == 0) return;
1610
1611 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1612 EVT VT = ValueVTs[j];
1613 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1614
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1615 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1616 ExtendKind = ISD::SIGN_EXTEND;
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1617 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1618 ExtendKind = ISD::ZERO_EXTEND;
1619
1620 // FIXME: C calling convention requires the return type to be promoted to
1621 // at least 32-bit. But this is not necessary for non-C calling
1622 // conventions. The frontend should mark functions whose return values
1623 // require promoting with signext or zeroext attributes.
1624 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1625 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1626 if (VT.bitsLT(MinVT))
1627 VT = MinVT;
1628 }
1629
Simon Dardisf7e43882017-04-07 17:25:05 +0000[diff] [blame]1630 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1631 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1632
1633 // 'inreg' on function refers to return value
1634 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1635 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1636 Flags.setInReg();
1637
1638 // Propagate extension type if any
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1639 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1640 Flags.setSExt();
Reid Klecknerb5180542017-03-21 16:57:19 +0000[diff] [blame]1641 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1642 Flags.setZExt();
1643
1644 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1645 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1646 }
1647}
1648
1649/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1650/// function arguments in the caller parameter area. This is the actual
1651/// alignment, not its logarithm.
Mehdi Amini5c183d52015-07-09 02:09:28 +0000[diff] [blame]1652unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1653 const DataLayout &DL) const {
1654 return DL.getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1655}
1656
Sanjay Patel0f9dcf82015-07-29 18:24:18 +0000[diff] [blame]1657bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1658 const DataLayout &DL, EVT VT,
1659 unsigned AddrSpace,
1660 unsigned Alignment,
1661 bool *Fast) const {
1662 // Check if the specified alignment is sufficient based on the data layout.
1663 // TODO: While using the data layout works in practice, a better solution
1664 // would be to implement this check directly (make this a virtual function).
1665 // For example, the ABI alignment may change based on software platform while
1666 // this function should only be affected by hardware implementation.
1667 Type *Ty = VT.getTypeForEVT(Context);
1668 if (Alignment >= DL.getABITypeAlignment(Ty)) {
1669 // Assume that an access that meets the ABI-specified alignment is fast.
1670 if (Fast != nullptr)
1671 *Fast = true;
1672 return true;
1673 }
1674
1675 // This is a misaligned access.
1676 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast);
1677}
1678
Sanjay Pateld66607b2016-04-26 17:11:17 +0000[diff] [blame]1679BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const {
1680 return BranchProbability(MinPercentageForPredictableBranch, 100);
1681}
Sanjay Patel0f9dcf82015-07-29 18:24:18 +0000[diff] [blame]1682
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1683//===----------------------------------------------------------------------===//
1684// TargetTransformInfo Helpers
1685//===----------------------------------------------------------------------===//
1686
1687int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1688 enum InstructionOpcodes {
1689#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1690#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1691#include "llvm/IR/Instruction.def"
1692 };
1693 switch (static_cast<InstructionOpcodes>(Opcode)) {
1694 case Ret: return 0;
1695 case Br: return 0;
1696 case Switch: return 0;
1697 case IndirectBr: return 0;
1698 case Invoke: return 0;
1699 case Resume: return 0;
1700 case Unreachable: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1701 case CleanupRet: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1702 case CatchRet: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1703 case CatchPad: return 0;
1704 case CatchSwitch: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1705 case CleanupPad: return 0;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1706 case Add: return ISD::ADD;
1707 case FAdd: return ISD::FADD;
1708 case Sub: return ISD::SUB;
1709 case FSub: return ISD::FSUB;
1710 case Mul: return ISD::MUL;
1711 case FMul: return ISD::FMUL;
1712 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1713 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1714 case FDiv: return ISD::FDIV;
1715 case URem: return ISD::UREM;
1716 case SRem: return ISD::SREM;
1717 case FRem: return ISD::FREM;
1718 case Shl: return ISD::SHL;
1719 case LShr: return ISD::SRL;
1720 case AShr: return ISD::SRA;
1721 case And: return ISD::AND;
1722 case Or: return ISD::OR;
1723 case Xor: return ISD::XOR;
1724 case Alloca: return 0;
1725 case Load: return ISD::LOAD;
1726 case Store: return ISD::STORE;
1727 case GetElementPtr: return 0;
1728 case Fence: return 0;
1729 case AtomicCmpXchg: return 0;
1730 case AtomicRMW: return 0;
1731 case Trunc: return ISD::TRUNCATE;
1732 case ZExt: return ISD::ZERO_EXTEND;
1733 case SExt: return ISD::SIGN_EXTEND;
1734 case FPToUI: return ISD::FP_TO_UINT;
1735 case FPToSI: return ISD::FP_TO_SINT;
1736 case UIToFP: return ISD::UINT_TO_FP;
1737 case SIToFP: return ISD::SINT_TO_FP;
1738 case FPTrunc: return ISD::FP_ROUND;
1739 case FPExt: return ISD::FP_EXTEND;
1740 case PtrToInt: return ISD::BITCAST;
1741 case IntToPtr: return ISD::BITCAST;
1742 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1743 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1744 case ICmp: return ISD::SETCC;
1745 case FCmp: return ISD::SETCC;
1746 case PHI: return 0;
1747 case Call: return 0;
1748 case Select: return ISD::SELECT;
1749 case UserOp1: return 0;
1750 case UserOp2: return 0;
1751 case VAArg: return 0;
1752 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1753 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1754 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1755 case ExtractValue: return ISD::MERGE_VALUES;
1756 case InsertValue: return ISD::MERGE_VALUES;
1757 case LandingPad: return 0;
1758 }
1759
1760 llvm_unreachable("Unknown instruction type encountered!");
1761}
1762
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1763std::pair<int, MVT>
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1764TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
1765 Type *Ty) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1766 LLVMContext &C = Ty->getContext();
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1767 EVT MTy = getValueType(DL, Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1768
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1769 int Cost = 1;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1770 // We keep legalizing the type until we find a legal kind. We assume that
1771 // the only operation that costs anything is the split. After splitting
1772 // we need to handle two types.
1773 while (true) {
1774 LegalizeKind LK = getTypeConversion(C, MTy);
1775
1776 if (LK.first == TypeLegal)
1777 return std::make_pair(Cost, MTy.getSimpleVT());
1778
1779 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1780 Cost *= 2;
1781
Chih-Hung Hsiehed7d81e2015-12-03 22:02:40 +0000[diff] [blame]1782 // Do not loop with f128 type.
1783 if (MTy == LK.second)
1784 return std::make_pair(Cost, MTy.getSimpleVT());
1785
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1786 // Keep legalizing the type.
1787 MTy = LK.second;
1788 }
1789}
1790
David L Kreitzerd5c67552016-10-14 17:56:00 +0000[diff] [blame]1791Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1792 bool UseTLS) const {
1793 // compiler-rt provides a variable with a magic name. Targets that do not
1794 // link with compiler-rt may also provide such a variable.
1795 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1796 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1797 auto UnsafeStackPtr =
1798 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1799
1800 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1801
1802 if (!UnsafeStackPtr) {
1803 auto TLSModel = UseTLS ?
1804 GlobalValue::InitialExecTLSModel :
1805 GlobalValue::NotThreadLocal;
1806 // The global variable is not defined yet, define it ourselves.
1807 // We use the initial-exec TLS model because we do not support the
1808 // variable living anywhere other than in the main executable.
1809 UnsafeStackPtr = new GlobalVariable(
1810 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1811 UnsafeStackPtrVar, nullptr, TLSModel);
1812 } else {
1813 // The variable exists, check its type and attributes.
1814 if (UnsafeStackPtr->getValueType() != StackPtrTy)
1815 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1816 if (UseTLS != UnsafeStackPtr->isThreadLocal())
1817 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1818 (UseTLS ? "" : "not ") + "be thread-local");
1819 }
1820 return UnsafeStackPtr;
1821}
1822
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1823Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
1824 if (!TM.getTargetTriple().isAndroid())
David L Kreitzerd5c67552016-10-14 17:56:00 +0000[diff] [blame]1825 return getDefaultSafeStackPointerLocation(IRB, true);
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1826
1827 // Android provides a libc function to retrieve the address of the current
1828 // thread's unsafe stack pointer.
1829 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1830 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1831 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address",
Serge Guelton59a2d7b2017-04-11 15:01:18 +0000[diff] [blame]1832 StackPtrTy->getPointerTo(0));
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1833 return IRB.CreateCall(Fn);
1834}
1835
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1836//===----------------------------------------------------------------------===//
1837// Loop Strength Reduction hooks
1838//===----------------------------------------------------------------------===//
1839
1840/// isLegalAddressingMode - Return true if the addressing mode represented
1841/// by AM is legal for this target, for a load/store of the specified type.
Mehdi Amini0cdec1e2015-07-09 02:09:40 +0000[diff] [blame]1842bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
1843 const AddrMode &AM, Type *Ty,
Matt Arsenaultbd7d80a2015-06-01 05:31:59 +0000[diff] [blame]1844 unsigned AS) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1845 // The default implementation of this implements a conservative RISCy, r+r and
1846 // r+i addr mode.
1847
1848 // Allows a sign-extended 16-bit immediate field.
1849 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1850 return false;
1851
1852 // No global is ever allowed as a base.
1853 if (AM.BaseGV)
1854 return false;
1855
1856 // Only support r+r,
1857 switch (AM.Scale) {
1858 case 0: // "r+i" or just "i", depending on HasBaseReg.
1859 break;
1860 case 1:
1861 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1862 return false;
1863 // Otherwise we have r+r or r+i.
1864 break;
1865 case 2:
1866 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1867 return false;
1868 // Allow 2*r as r+r.
1869 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1870 default: // Don't allow n * r
1871 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1872 }
1873
1874 return true;
1875}
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1876
1877//===----------------------------------------------------------------------===//
1878// Stack Protector
1879//===----------------------------------------------------------------------===//
1880
1881// For OpenBSD return its special guard variable. Otherwise return nullptr,
1882// so that SelectionDAG handle SSP.
1883Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const {
1884 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1885 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1886 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
Tim Shena5cc25e2016-08-22 18:26:27 +0000[diff] [blame]1887 return M.getOrInsertGlobal("__guard_local", PtrTy);
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1888 }
1889 return nullptr;
1890}
1891
1892// Currently only support "standard" __stack_chk_guard.
1893// TODO: add LOAD_STACK_GUARD support.
1894void TargetLoweringBase::insertSSPDeclarations(Module &M) const {
1895 M.getOrInsertGlobal("__stack_chk_guard", Type::getInt8PtrTy(M.getContext()));
1896}
1897
1898// Currently only support "standard" __stack_chk_guard.
1899// TODO: add LOAD_STACK_GUARD support.
Tim Shena1d8bc52016-04-19 20:14:52 +0000[diff] [blame]1900Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const {
Davide Italianobd4243c2016-06-09 14:23:38 +0000[diff] [blame]1901 return M.getGlobalVariable("__stack_chk_guard", true);
Tim Shen00127562016-04-08 21:26:31 +0000[diff] [blame]1902}
Etienne Bergeron22bfa832016-06-07 20:15:35 +0000[diff] [blame]1903
1904Value *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const {
1905 return nullptr;
1906}
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]1907
Evandro Menezeseb97e352016-10-25 19:53:51 +0000[diff] [blame]1908unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
1909 return MinimumJumpTableEntries;
1910}
1911
1912void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
1913 MinimumJumpTableEntries = Val;
1914}
1915
Jun Bum Lim919f9e82017-04-28 16:04:03 +0000[diff] [blame^]1916unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1917 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1918}
1919
Evandro Menezese45de8a2016-09-26 15:32:33 +0000[diff] [blame]1920unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
1921 return MaximumJumpTableSize;
1922}
1923
1924void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
1925 MaximumJumpTableSize = Val;
1926}
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]1927
1928//===----------------------------------------------------------------------===//
1929// Reciprocal Estimates
1930//===----------------------------------------------------------------------===//
1931
1932/// Get the reciprocal estimate attribute string for a function that will
1933/// override the target defaults.
1934static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
1935 const Function *F = MF.getFunction();
David Majnemere0ebdf42017-01-13 22:24:25 +0000[diff] [blame]1936 return F->getFnAttribute("reciprocal-estimates").getValueAsString();
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]1937}
1938
1939/// Construct a string for the given reciprocal operation of the given type.
1940/// This string should match the corresponding option to the front-end's
1941/// "-mrecip" flag assuming those strings have been passed through in an
1942/// attribute string. For example, "vec-divf" for a division of a vXf32.
1943static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1944 std::string Name = VT.isVector() ? "vec-" : "";
1945
1946 Name += IsSqrt ? "sqrt" : "div";
1947
1948 // TODO: Handle "half" or other float types?
1949 if (VT.getScalarType() == MVT::f64) {
1950 Name += "d";
1951 } else {
1952 assert(VT.getScalarType() == MVT::f32 &&
1953 "Unexpected FP type for reciprocal estimate");
1954 Name += "f";
1955 }
1956
1957 return Name;
1958}
1959
1960/// Return the character position and value (a single numeric character) of a
1961/// customized refinement operation in the input string if it exists. Return
1962/// false if there is no customized refinement step count.
1963static bool parseRefinementStep(StringRef In, size_t &Position,
1964 uint8_t &Value) {
1965 const char RefStepToken = ':';
1966 Position = In.find(RefStepToken);
1967 if (Position == StringRef::npos)
1968 return false;
1969
1970 StringRef RefStepString = In.substr(Position + 1);
1971 // Allow exactly one numeric character for the additional refinement
1972 // step parameter.
1973 if (RefStepString.size() == 1) {
1974 char RefStepChar = RefStepString[0];
1975 if (RefStepChar >= '0' && RefStepChar <= '9') {
1976 Value = RefStepChar - '0';
1977 return true;
1978 }
1979 }
1980 report_fatal_error("Invalid refinement step for -recip.");
1981}
1982
1983/// For the input attribute string, return one of the ReciprocalEstimate enum
1984/// status values (enabled, disabled, or not specified) for this operation on
1985/// the specified data type.
1986static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1987 if (Override.empty())
1988 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1989
1990 SmallVector<StringRef, 4> OverrideVector;
1991 SplitString(Override, OverrideVector, ",");
1992 unsigned NumArgs = OverrideVector.size();
1993
1994 // Check if "all", "none", or "default" was specified.
1995 if (NumArgs == 1) {
1996 // Look for an optional setting of the number of refinement steps needed
1997 // for this type of reciprocal operation.
1998 size_t RefPos;
1999 uint8_t RefSteps;
2000 if (parseRefinementStep(Override, RefPos, RefSteps)) {
2001 // Split the string for further processing.
2002 Override = Override.substr(0, RefPos);
2003 }
2004
2005 // All reciprocal types are enabled.
2006 if (Override == "all")
2007 return TargetLoweringBase::ReciprocalEstimate::Enabled;
2008
2009 // All reciprocal types are disabled.
2010 if (Override == "none")
2011 return TargetLoweringBase::ReciprocalEstimate::Disabled;
2012
2013 // Target defaults for enablement are used.
2014 if (Override == "default")
2015 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2016 }
2017
2018 // The attribute string may omit the size suffix ('f'/'d').
2019 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2020 std::string VTNameNoSize = VTName;
Sanjay Patel501be9b2016-10-21 14:58:30 +0000[diff] [blame]2021 VTNameNoSize.pop_back();
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]2022 static const char DisabledPrefix = '!';
2023
2024 for (StringRef RecipType : OverrideVector) {
2025 size_t RefPos;
2026 uint8_t RefSteps;
2027 if (parseRefinementStep(RecipType, RefPos, RefSteps))
2028 RecipType = RecipType.substr(0, RefPos);
2029
2030 // Ignore the disablement token for string matching.
2031 bool IsDisabled = RecipType[0] == DisabledPrefix;
2032 if (IsDisabled)
2033 RecipType = RecipType.substr(1);
2034
2035 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2036 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
2037 : TargetLoweringBase::ReciprocalEstimate::Enabled;
2038 }
2039
2040 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2041}
2042
2043/// For the input attribute string, return the customized refinement step count
2044/// for this operation on the specified data type. If the step count does not
2045/// exist, return the ReciprocalEstimate enum value for unspecified.
2046static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2047 if (Override.empty())
2048 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2049
2050 SmallVector<StringRef, 4> OverrideVector;
2051 SplitString(Override, OverrideVector, ",");
2052 unsigned NumArgs = OverrideVector.size();
2053
2054 // Check if "all", "default", or "none" was specified.
2055 if (NumArgs == 1) {
2056 // Look for an optional setting of the number of refinement steps needed
2057 // for this type of reciprocal operation.
2058 size_t RefPos;
2059 uint8_t RefSteps;
2060 if (!parseRefinementStep(Override, RefPos, RefSteps))
2061 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2062
2063 // Split the string for further processing.
2064 Override = Override.substr(0, RefPos);
2065 assert(Override != "none" &&
2066 "Disabled reciprocals, but specifed refinement steps?");
2067
2068 // If this is a general override, return the specified number of steps.
2069 if (Override == "all" || Override == "default")
2070 return RefSteps;
2071 }
2072
2073 // The attribute string may omit the size suffix ('f'/'d').
2074 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2075 std::string VTNameNoSize = VTName;
Sanjay Patel501be9b2016-10-21 14:58:30 +0000[diff] [blame]2076 VTNameNoSize.pop_back();
Sanjay Patel0051efc2016-10-20 16:55:45 +0000[diff] [blame]2077
2078 for (StringRef RecipType : OverrideVector) {
2079 size_t RefPos;
2080 uint8_t RefSteps;
2081 if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2082 continue;
2083
2084 RecipType = RecipType.substr(0, RefPos);
2085 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2086 return RefSteps;
2087 }
2088
2089 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2090}
2091
2092int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2093 MachineFunction &MF) const {
2094 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2095}
2096
2097int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2098 MachineFunction &MF) const {
2099 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2100}
2101
2102int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2103 MachineFunction &MF) const {
2104 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2105}
2106
2107int TargetLoweringBase::getDivRefinementSteps(EVT VT,
2108 MachineFunction &MF) const {
2109 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2110}