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gerrit-public.fairphone.software / toolchain / llvm-project / 2946cd701067404b99c39fb29dc9c74bd7193eb3 / . / llvm / lib / Target / AArch64 / Disassembler / AArch64Disassembler.cpp
blob: 6726c5e7a03ba2928d2721c99586e4d90d1bcd14 [file] [log] [blame]
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]2//
Chandler Carruth2946cd72019-01-19 08:50:56 +0000[diff] [blame^]3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64Disassembler.h"
13#include "AArch64ExternalSymbolizer.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]14#include "MCTargetDesc/AArch64AddressingModes.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]15#include "MCTargetDesc/AArch64MCTargetDesc.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]16#include "Utils/AArch64BaseInfo.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]17#include "llvm-c/Disassembler.h"
18#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]19#include "llvm/MC/MCFixedLenDisassembler.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]20#include "llvm/MC/MCInst.h"
Benjamin Kramer27c769d2018-09-10 12:53:46 +0000[diff] [blame]21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]23#include "llvm/Support/Compiler.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]24#include "llvm/Support/Debug.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]25#include "llvm/Support/ErrorHandling.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]27#include <algorithm>
28#include <memory>
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]29
30using namespace llvm;
31
32#define DEBUG_TYPE "aarch64-disassembler"
33
34// Pull DecodeStatus and its enum values into the global namespace.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]35using DecodeStatus = MCDisassembler::DecodeStatus;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]36
37// Forward declare these because the autogenerated code will reference them.
38// Definitions are further down.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]39static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]40 unsigned RegNo, uint64_t Address,
41 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]42static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]43 unsigned RegNo,
44 uint64_t Address,
45 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]46static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47 uint64_t Address,
48 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]49static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]50 uint64_t Address,
51 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]52static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]53 uint64_t Address,
54 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]55static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]56 uint64_t Address,
57 const void *Decoder);
Sander de Smalen367694b2018-04-20 08:54:49 +0000[diff] [blame]58static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
59 uint64_t Address,
60 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]61static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]62 uint64_t Address,
63 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]64static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]65 unsigned RegNo, uint64_t Address,
66 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]67static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]68 uint64_t Address,
69 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]70static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]71 unsigned RegNo, uint64_t Address,
72 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]73static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]74 uint64_t Address,
75 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]76static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]77 uint64_t Address,
78 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]79static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]80 uint64_t Address,
81 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]82static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]83 uint64_t Address,
84 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]85static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]86 uint64_t Address,
87 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]88static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]89 uint64_t Address,
90 const void *Decoder);
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]91static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
92 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]93 const void *Decoder);
Sander de Smalen8cd1f532018-07-03 15:31:04 +0000[diff] [blame]94static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
95 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]96 const void *Decoder);
Sander de Smalen8cd1f532018-07-03 15:31:04 +0000[diff] [blame]97static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
98 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]99 const void *Decoder);
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]100static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
101 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]102 const void *Decoder);
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame]103static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
104 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]105 const void *Decoder);
Sander de Smalen7a210db2018-04-16 10:46:18 +0000[diff] [blame]106static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
107 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]108 const void *Decoder);
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]109static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
110 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]111 const void *Decoder);
Sander de Smalen906a5de2018-01-09 17:01:27 +0000[diff] [blame]112static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
113 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]114 const void *Decoder);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]115
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]116static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]117 uint64_t Address,
118 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]119static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]120 uint64_t Address,
121 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]122static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]123 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]124static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]125 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]126static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]128static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]129 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]130static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]131 uint64_t Address,
132 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]133static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]134 uint64_t Address,
135 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]136static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]137 uint64_t Address,
138 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]139static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
140 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]141 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]142static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]143 uint64_t Address,
144 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]145static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]146 uint64_t Address,
147 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]148static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
149 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]150 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]151static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
152 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]153 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]154static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]155 uint64_t Address,
156 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]157static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
158 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]159 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]160static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]161 uint64_t Address, const void *Decoder);
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]162static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
163 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]164static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]165 uint64_t Address,
166 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]167static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]168 uint64_t Address,
169 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]170static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
172
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]173static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]174 uint64_t Address,
175 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]176static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]177 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]178static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]179 uint64_t Addr,
180 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]181static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]182 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]183static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]184 uint64_t Addr,
185 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]186static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]187 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]188static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]189 uint64_t Addr,
190 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]191static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]192 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]193static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]194 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]195static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]196 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]197static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]198 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]199static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]200 uint64_t Addr, const void *Decoder);
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]201static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
202 unsigned RegNo,
203 uint64_t Addr,
204 const void *Decoder);
205static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
206 unsigned RegNo,
207 uint64_t Addr,
208 const void *Decoder);
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]209static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
210 uint32_t insn,
211 uint64_t Address,
212 const void *Decoder);
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]213template<int Bits>
214static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
215 uint64_t Address, const void *Decoder);
Sander de Smalen62770792018-05-25 09:47:52 +0000[diff] [blame]216template <int ElementWidth>
217static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
218 uint64_t Addr, const void *Decoder);
Sander de Smalen18ac8f92018-06-15 15:47:44 +0000[diff] [blame]219static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
220 uint64_t Addr, const void *Decoder);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]221
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]222static DecodeStatus DecodeLoadAllocTagArrayInstruction(MCInst &Inst,
223 uint32_t insn,
224 uint64_t address,
225 const void* Decoder);
226
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]227static bool Check(DecodeStatus &Out, DecodeStatus In) {
228 switch (In) {
229 case MCDisassembler::Success:
230 // Out stays the same.
231 return true;
232 case MCDisassembler::SoftFail:
233 Out = In;
234 return true;
235 case MCDisassembler::Fail:
236 Out = In;
237 return false;
238 }
239 llvm_unreachable("Invalid DecodeStatus!");
240}
241
242#include "AArch64GenDisassemblerTables.inc"
243#include "AArch64GenInstrInfo.inc"
244
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]245#define Success MCDisassembler::Success
246#define Fail MCDisassembler::Fail
247#define SoftFail MCDisassembler::SoftFail
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]248
249static MCDisassembler *createAArch64Disassembler(const Target &T,
250 const MCSubtargetInfo &STI,
251 MCContext &Ctx) {
252 return new AArch64Disassembler(STI, Ctx);
253}
254
255DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]256 ArrayRef<uint8_t> Bytes,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]257 uint64_t Address,
258 raw_ostream &OS,
259 raw_ostream &CS) const {
260 CommentStream = &CS;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]261
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]262 Size = 0;
263 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]264 if (Bytes.size() < 4)
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]265 return Fail;
266 Size = 4;
267
268 // Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]269 uint32_t Insn =
270 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]271
272 // Calling the auto-generated decoder function.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]273 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]274}
275
Daniel Sanders50f17232015-09-15 16:17:27 +0000[diff] [blame]276static MCSymbolizer *
277createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
278 LLVMSymbolLookupCallback SymbolLookUp,
279 void *DisInfo, MCContext *Ctx,
280 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]281 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
282 SymbolLookUp, DisInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]283}
284
285extern "C" void LLVMInitializeAArch64Disassembler() {
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]286 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]287 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]288 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]289 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]290 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]291 createAArch64ExternalSymbolizer);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]292 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]293 createAArch64ExternalSymbolizer);
294
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]295 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]296 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]297 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]298 createAArch64ExternalSymbolizer);
299}
300
301static const unsigned FPR128DecoderTable[] = {
302 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
303 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
304 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
305 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
306 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
307 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
308 AArch64::Q30, AArch64::Q31
309};
310
311static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
312 uint64_t Addr,
313 const void *Decoder) {
314 if (RegNo > 31)
315 return Fail;
316
317 unsigned Register = FPR128DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]318 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]319 return Success;
320}
321
322static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
323 uint64_t Addr,
324 const void *Decoder) {
325 if (RegNo > 15)
326 return Fail;
327 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
328}
329
330static const unsigned FPR64DecoderTable[] = {
331 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
332 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
333 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
334 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
335 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
336 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
337 AArch64::D30, AArch64::D31
338};
339
340static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
341 uint64_t Addr,
342 const void *Decoder) {
343 if (RegNo > 31)
344 return Fail;
345
346 unsigned Register = FPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]347 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]348 return Success;
349}
350
351static const unsigned FPR32DecoderTable[] = {
352 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
353 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
354 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
355 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
356 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
357 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
358 AArch64::S30, AArch64::S31
359};
360
361static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
362 uint64_t Addr,
363 const void *Decoder) {
364 if (RegNo > 31)
365 return Fail;
366
367 unsigned Register = FPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]368 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]369 return Success;
370}
371
372static const unsigned FPR16DecoderTable[] = {
373 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
374 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
375 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
376 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
377 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
378 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
379 AArch64::H30, AArch64::H31
380};
381
382static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
383 uint64_t Addr,
384 const void *Decoder) {
385 if (RegNo > 31)
386 return Fail;
387
388 unsigned Register = FPR16DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]389 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]390 return Success;
391}
392
393static const unsigned FPR8DecoderTable[] = {
394 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
395 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
396 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
397 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
398 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
399 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
400 AArch64::B30, AArch64::B31
401};
402
403static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
404 uint64_t Addr,
405 const void *Decoder) {
406 if (RegNo > 31)
407 return Fail;
408
409 unsigned Register = FPR8DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]410 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]411 return Success;
412}
413
414static const unsigned GPR64DecoderTable[] = {
415 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
416 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
417 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
418 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
419 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
420 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
421 AArch64::LR, AArch64::XZR
422};
423
Sander de Smalen367694b2018-04-20 08:54:49 +0000[diff] [blame]424static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
425 uint64_t Addr,
426 const void *Decoder) {
427 if (RegNo > 30)
428 return Fail;
429
430 unsigned Register = GPR64DecoderTable[RegNo];
431 Inst.addOperand(MCOperand::createReg(Register));
432 return Success;
433}
434
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]435static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
436 uint64_t Addr,
437 const void *Decoder) {
438 if (RegNo > 31)
439 return Fail;
440
441 unsigned Register = GPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]442 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]443 return Success;
444}
445
446static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
447 uint64_t Addr,
448 const void *Decoder) {
449 if (RegNo > 31)
450 return Fail;
451 unsigned Register = GPR64DecoderTable[RegNo];
452 if (Register == AArch64::XZR)
453 Register = AArch64::SP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]454 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]455 return Success;
456}
457
458static const unsigned GPR32DecoderTable[] = {
459 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
460 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
461 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
462 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
463 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
464 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
465 AArch64::W30, AArch64::WZR
466};
467
468static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
469 uint64_t Addr,
470 const void *Decoder) {
471 if (RegNo > 31)
472 return Fail;
473
474 unsigned Register = GPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]475 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]476 return Success;
477}
478
479static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
480 uint64_t Addr,
481 const void *Decoder) {
482 if (RegNo > 31)
483 return Fail;
484
485 unsigned Register = GPR32DecoderTable[RegNo];
486 if (Register == AArch64::WZR)
487 Register = AArch64::WSP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]488 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]489 return Success;
490}
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]491static const unsigned ZPRDecoderTable[] = {
492 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
493 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
494 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
495 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
496 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
497 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
498 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
499 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
500};
501
502static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
503 uint64_t Address,
504 const void* Decoder) {
505 if (RegNo > 31)
506 return Fail;
507
508 unsigned Register = ZPRDecoderTable[RegNo];
509 Inst.addOperand(MCOperand::createReg(Register));
510 return Success;
511}
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]512
Sander de Smalen8cd1f532018-07-03 15:31:04 +0000[diff] [blame]513static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
514 uint64_t Address,
515 const void *Decoder) {
516 if (RegNo > 15)
517 return Fail;
518 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
519}
520
521static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
522 uint64_t Address,
523 const void *Decoder) {
524 if (RegNo > 7)
525 return Fail;
526 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
527}
528
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]529static const unsigned ZZDecoderTable[] = {
530 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4,
531 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
532 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12,
533 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
534 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
535 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
536 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
537 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
538};
539
540static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
541 uint64_t Address,
542 const void* Decoder) {
543 if (RegNo > 31)
544 return Fail;
545 unsigned Register = ZZDecoderTable[RegNo];
546 Inst.addOperand(MCOperand::createReg(Register));
547 return Success;
548}
549
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame]550static const unsigned ZZZDecoderTable[] = {
551 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4,
552 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
553 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10,
554 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13,
555 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
556 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19,
557 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22,
558 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25,
559 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28,
560 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
561 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1
562};
563
564static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
565 uint64_t Address,
566 const void* Decoder) {
567 if (RegNo > 31)
568 return Fail;
569 unsigned Register = ZZZDecoderTable[RegNo];
570 Inst.addOperand(MCOperand::createReg(Register));
571 return Success;
572}
573
Sander de Smalen7a210db2018-04-16 10:46:18 +0000[diff] [blame]574static const unsigned ZZZZDecoderTable[] = {
575 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5,
576 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
577 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11,
578 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14,
579 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
580 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20,
581 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23,
582 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26,
583 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29,
584 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
585 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2
586};
587
588static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
589 uint64_t Address,
590 const void* Decoder) {
591 if (RegNo > 31)
592 return Fail;
593 unsigned Register = ZZZZDecoderTable[RegNo];
594 Inst.addOperand(MCOperand::createReg(Register));
595 return Success;
596}
597
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]598static const unsigned PPRDecoderTable[] = {
599 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
600 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
601 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
602 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
603};
604
605static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
606 uint64_t Addr, const void *Decoder) {
607 if (RegNo > 15)
608 return Fail;
609
610 unsigned Register = PPRDecoderTable[RegNo];
611 Inst.addOperand(MCOperand::createReg(Register));
612 return Success;
613}
614
Sander de Smalendc5e0812018-01-03 10:15:46 +0000[diff] [blame]615static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
616 uint64_t Addr,
617 const void* Decoder) {
618 if (RegNo > 7)
619 return Fail;
620
621 // Just reuse the PPR decode table
622 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
623}
624
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]625static const unsigned VectorDecoderTable[] = {
626 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
627 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
628 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
629 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
630 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
631 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
632 AArch64::Q30, AArch64::Q31
633};
634
635static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
636 uint64_t Addr,
637 const void *Decoder) {
638 if (RegNo > 31)
639 return Fail;
640
641 unsigned Register = VectorDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]642 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]643 return Success;
644}
645
646static const unsigned QQDecoderTable[] = {
647 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
648 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
649 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
650 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
651 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
652 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
653 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
654 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
655};
656
657static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
658 uint64_t Addr, const void *Decoder) {
659 if (RegNo > 31)
660 return Fail;
661 unsigned Register = QQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]662 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]663 return Success;
664}
665
666static const unsigned QQQDecoderTable[] = {
667 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
668 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
669 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
670 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
671 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
672 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
673 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
674 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
675 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
676 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
677 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
678};
679
680static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
681 uint64_t Addr, const void *Decoder) {
682 if (RegNo > 31)
683 return Fail;
684 unsigned Register = QQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]685 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]686 return Success;
687}
688
689static const unsigned QQQQDecoderTable[] = {
690 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
691 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
692 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
693 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
694 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
695 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
696 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
697 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
698 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
699 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
700 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
701};
702
703static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
704 uint64_t Addr,
705 const void *Decoder) {
706 if (RegNo > 31)
707 return Fail;
708 unsigned Register = QQQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]709 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]710 return Success;
711}
712
713static const unsigned DDDecoderTable[] = {
714 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
715 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
716 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
717 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
718 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
719 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
720 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
721 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
722};
723
724static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
725 uint64_t Addr, const void *Decoder) {
726 if (RegNo > 31)
727 return Fail;
728 unsigned Register = DDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]729 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]730 return Success;
731}
732
733static const unsigned DDDDecoderTable[] = {
734 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
735 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
736 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
737 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
738 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
739 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
740 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
741 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
742 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
743 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
744 AArch64::D30_D31_D0, AArch64::D31_D0_D1
745};
746
747static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
748 uint64_t Addr, const void *Decoder) {
749 if (RegNo > 31)
750 return Fail;
751 unsigned Register = DDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]752 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]753 return Success;
754}
755
756static const unsigned DDDDDecoderTable[] = {
757 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
758 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
759 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
760 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
761 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
762 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
763 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
764 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
765 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
766 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
767 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
768};
769
770static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
771 uint64_t Addr,
772 const void *Decoder) {
773 if (RegNo > 31)
774 return Fail;
775 unsigned Register = DDDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]776 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]777 return Success;
778}
779
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]780static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]781 uint64_t Addr,
782 const void *Decoder) {
783 // scale{5} is asserted as 1 in tblgen.
Tom Coxon2c13e712014-09-30 16:23:16 +0000[diff] [blame]784 Imm |= 0x20;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]785 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]786 return Success;
787}
788
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]789static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]790 uint64_t Addr,
791 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]792 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]793 return Success;
794}
795
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]796static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]797 uint64_t Addr, const void *Decoder) {
798 int64_t ImmVal = Imm;
799 const AArch64Disassembler *Dis =
800 static_cast<const AArch64Disassembler *>(Decoder);
801
802 // Sign-extend 19-bit immediate.
803 if (ImmVal & (1 << (19 - 1)))
804 ImmVal |= ~((1LL << 19) - 1);
805
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]806 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]807 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]808 Inst.addOperand(MCOperand::createImm(ImmVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]809 return Success;
810}
811
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]812static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]813 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]814 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
815 Inst.addOperand(MCOperand::createImm(Imm & 1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]816 return Success;
817}
818
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]819static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]820 uint64_t Address,
821 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]822 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]823
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]824 // Every system register in the encoding space is valid with the syntax
825 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
826 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]827}
828
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]829static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]830 uint64_t Address,
831 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]832 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]833
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]834 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]835}
836
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]837static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]838 uint64_t Address,
839 const void *Decoder) {
840 // This decoder exists to add the dummy Lane operand to the MCInst, which must
841 // be 1 in assembly but has no other real manifestation.
842 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
843 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
844 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
845
846 if (IsToVec) {
847 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
848 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
849 } else {
850 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
851 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
852 }
853
854 // Add the lane
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]855 Inst.addOperand(MCOperand::createImm(1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]856
857 return Success;
858}
859
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]860static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]861 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]862 Inst.addOperand(MCOperand::createImm(Add - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]863 return Success;
864}
865
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]866static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]867 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]868 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]869 return Success;
870}
871
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]872static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]873 uint64_t Addr, const void *Decoder) {
874 return DecodeVecShiftRImm(Inst, Imm, 64);
875}
876
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]877static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]878 uint64_t Addr,
879 const void *Decoder) {
880 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
881}
882
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]883static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]884 uint64_t Addr, const void *Decoder) {
885 return DecodeVecShiftRImm(Inst, Imm, 32);
886}
887
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]888static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]889 uint64_t Addr,
890 const void *Decoder) {
891 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
892}
893
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]894static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]895 uint64_t Addr, const void *Decoder) {
896 return DecodeVecShiftRImm(Inst, Imm, 16);
897}
898
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]899static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]900 uint64_t Addr,
901 const void *Decoder) {
902 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
903}
904
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]905static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]906 uint64_t Addr, const void *Decoder) {
907 return DecodeVecShiftRImm(Inst, Imm, 8);
908}
909
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]910static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]911 uint64_t Addr, const void *Decoder) {
912 return DecodeVecShiftLImm(Inst, Imm, 64);
913}
914
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]915static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]916 uint64_t Addr, const void *Decoder) {
917 return DecodeVecShiftLImm(Inst, Imm, 32);
918}
919
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]920static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]921 uint64_t Addr, const void *Decoder) {
922 return DecodeVecShiftLImm(Inst, Imm, 16);
923}
924
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]925static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]926 uint64_t Addr, const void *Decoder) {
927 return DecodeVecShiftLImm(Inst, Imm, 8);
928}
929
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]930static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
931 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]932 const void *Decoder) {
933 unsigned Rd = fieldFromInstruction(insn, 0, 5);
934 unsigned Rn = fieldFromInstruction(insn, 5, 5);
935 unsigned Rm = fieldFromInstruction(insn, 16, 5);
936 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
937 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
938 unsigned shift = (shiftHi << 6) | shiftLo;
939 switch (Inst.getOpcode()) {
940 default:
941 return Fail;
942 case AArch64::ADDWrs:
943 case AArch64::ADDSWrs:
944 case AArch64::SUBWrs:
945 case AArch64::SUBSWrs:
946 // if shift == '11' then ReservedValue()
947 if (shiftHi == 0x3)
948 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]949 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]950 case AArch64::ANDWrs:
951 case AArch64::ANDSWrs:
952 case AArch64::BICWrs:
953 case AArch64::BICSWrs:
954 case AArch64::ORRWrs:
955 case AArch64::ORNWrs:
956 case AArch64::EORWrs:
957 case AArch64::EONWrs: {
958 // if sf == '0' and imm6<5> == '1' then ReservedValue()
959 if (shiftLo >> 5 == 1)
960 return Fail;
961 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
962 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
963 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
964 break;
965 }
966 case AArch64::ADDXrs:
967 case AArch64::ADDSXrs:
968 case AArch64::SUBXrs:
969 case AArch64::SUBSXrs:
970 // if shift == '11' then ReservedValue()
971 if (shiftHi == 0x3)
972 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]973 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]974 case AArch64::ANDXrs:
975 case AArch64::ANDSXrs:
976 case AArch64::BICXrs:
977 case AArch64::BICSXrs:
978 case AArch64::ORRXrs:
979 case AArch64::ORNXrs:
980 case AArch64::EORXrs:
981 case AArch64::EONXrs:
982 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
983 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
984 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
985 break;
986 }
987
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]988 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]989 return Success;
990}
991
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]992static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]993 uint64_t Addr,
994 const void *Decoder) {
995 unsigned Rd = fieldFromInstruction(insn, 0, 5);
996 unsigned imm = fieldFromInstruction(insn, 5, 16);
997 unsigned shift = fieldFromInstruction(insn, 21, 2);
998 shift <<= 4;
999 switch (Inst.getOpcode()) {
1000 default:
1001 return Fail;
1002 case AArch64::MOVZWi:
1003 case AArch64::MOVNWi:
1004 case AArch64::MOVKWi:
1005 if (shift & (1U << 5))
1006 return Fail;
1007 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1008 break;
1009 case AArch64::MOVZXi:
1010 case AArch64::MOVNXi:
1011 case AArch64::MOVKXi:
1012 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1013 break;
1014 }
1015
1016 if (Inst.getOpcode() == AArch64::MOVKWi ||
1017 Inst.getOpcode() == AArch64::MOVKXi)
1018 Inst.addOperand(Inst.getOperand(0));
1019
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1020 Inst.addOperand(MCOperand::createImm(imm));
1021 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1022 return Success;
1023}
1024
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1025static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
1026 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1027 const void *Decoder) {
1028 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1029 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1030 unsigned offset = fieldFromInstruction(insn, 10, 12);
1031 const AArch64Disassembler *Dis =
1032 static_cast<const AArch64Disassembler *>(Decoder);
1033
1034 switch (Inst.getOpcode()) {
1035 default:
1036 return Fail;
1037 case AArch64::PRFMui:
1038 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1039 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1040 break;
1041 case AArch64::STRBBui:
1042 case AArch64::LDRBBui:
1043 case AArch64::LDRSBWui:
1044 case AArch64::STRHHui:
1045 case AArch64::LDRHHui:
1046 case AArch64::LDRSHWui:
1047 case AArch64::STRWui:
1048 case AArch64::LDRWui:
1049 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1050 break;
1051 case AArch64::LDRSBXui:
1052 case AArch64::LDRSHXui:
1053 case AArch64::LDRSWui:
1054 case AArch64::STRXui:
1055 case AArch64::LDRXui:
1056 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1057 break;
1058 case AArch64::LDRQui:
1059 case AArch64::STRQui:
1060 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1061 break;
1062 case AArch64::LDRDui:
1063 case AArch64::STRDui:
1064 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1065 break;
1066 case AArch64::LDRSui:
1067 case AArch64::STRSui:
1068 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1069 break;
1070 case AArch64::LDRHui:
1071 case AArch64::STRHui:
1072 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1073 break;
1074 case AArch64::LDRBui:
1075 case AArch64::STRBui:
1076 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1077 break;
1078 }
1079
1080 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1081 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1082 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1083 return Success;
1084}
1085
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1086static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1087 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1088 const void *Decoder) {
1089 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1090 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1091 int64_t offset = fieldFromInstruction(insn, 12, 9);
1092
1093 // offset is a 9-bit signed immediate, so sign extend it to
1094 // fill the unsigned.
1095 if (offset & (1 << (9 - 1)))
1096 offset |= ~((1LL << 9) - 1);
1097
1098 // First operand is always the writeback to the address register, if needed.
1099 switch (Inst.getOpcode()) {
1100 default:
1101 break;
1102 case AArch64::LDRSBWpre:
1103 case AArch64::LDRSHWpre:
1104 case AArch64::STRBBpre:
1105 case AArch64::LDRBBpre:
1106 case AArch64::STRHHpre:
1107 case AArch64::LDRHHpre:
1108 case AArch64::STRWpre:
1109 case AArch64::LDRWpre:
1110 case AArch64::LDRSBWpost:
1111 case AArch64::LDRSHWpost:
1112 case AArch64::STRBBpost:
1113 case AArch64::LDRBBpost:
1114 case AArch64::STRHHpost:
1115 case AArch64::LDRHHpost:
1116 case AArch64::STRWpost:
1117 case AArch64::LDRWpost:
1118 case AArch64::LDRSBXpre:
1119 case AArch64::LDRSHXpre:
1120 case AArch64::STRXpre:
1121 case AArch64::LDRSWpre:
1122 case AArch64::LDRXpre:
1123 case AArch64::LDRSBXpost:
1124 case AArch64::LDRSHXpost:
1125 case AArch64::STRXpost:
1126 case AArch64::LDRSWpost:
1127 case AArch64::LDRXpost:
1128 case AArch64::LDRQpre:
1129 case AArch64::STRQpre:
1130 case AArch64::LDRQpost:
1131 case AArch64::STRQpost:
1132 case AArch64::LDRDpre:
1133 case AArch64::STRDpre:
1134 case AArch64::LDRDpost:
1135 case AArch64::STRDpost:
1136 case AArch64::LDRSpre:
1137 case AArch64::STRSpre:
1138 case AArch64::LDRSpost:
1139 case AArch64::STRSpost:
1140 case AArch64::LDRHpre:
1141 case AArch64::STRHpre:
1142 case AArch64::LDRHpost:
1143 case AArch64::STRHpost:
1144 case AArch64::LDRBpre:
1145 case AArch64::STRBpre:
1146 case AArch64::LDRBpost:
1147 case AArch64::STRBpost:
1148 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1149 break;
1150 }
1151
1152 switch (Inst.getOpcode()) {
1153 default:
1154 return Fail;
1155 case AArch64::PRFUMi:
1156 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1157 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1158 break;
1159 case AArch64::STURBBi:
1160 case AArch64::LDURBBi:
1161 case AArch64::LDURSBWi:
1162 case AArch64::STURHHi:
1163 case AArch64::LDURHHi:
1164 case AArch64::LDURSHWi:
1165 case AArch64::STURWi:
1166 case AArch64::LDURWi:
1167 case AArch64::LDTRSBWi:
1168 case AArch64::LDTRSHWi:
1169 case AArch64::STTRWi:
1170 case AArch64::LDTRWi:
1171 case AArch64::STTRHi:
1172 case AArch64::LDTRHi:
1173 case AArch64::LDTRBi:
1174 case AArch64::STTRBi:
1175 case AArch64::LDRSBWpre:
1176 case AArch64::LDRSHWpre:
1177 case AArch64::STRBBpre:
1178 case AArch64::LDRBBpre:
1179 case AArch64::STRHHpre:
1180 case AArch64::LDRHHpre:
1181 case AArch64::STRWpre:
1182 case AArch64::LDRWpre:
1183 case AArch64::LDRSBWpost:
1184 case AArch64::LDRSHWpost:
1185 case AArch64::STRBBpost:
1186 case AArch64::LDRBBpost:
1187 case AArch64::STRHHpost:
1188 case AArch64::LDRHHpost:
1189 case AArch64::STRWpost:
1190 case AArch64::LDRWpost:
Sjoerd Meijer83a2a622018-07-12 14:57:59 +0000[diff] [blame]1191 case AArch64::STLURBi:
1192 case AArch64::STLURHi:
Sjoerd Meijerceabd502018-07-13 15:25:42 +0000[diff] [blame]1193 case AArch64::STLURWi:
Sjoerd Meijer83a2a622018-07-12 14:57:59 +0000[diff] [blame]1194 case AArch64::LDAPURBi:
Sjoerd Meijerceabd502018-07-13 15:25:42 +0000[diff] [blame]1195 case AArch64::LDAPURSBWi:
Sjoerd Meijer83a2a622018-07-12 14:57:59 +0000[diff] [blame]1196 case AArch64::LDAPURHi:
Sjoerd Meijerceabd502018-07-13 15:25:42 +0000[diff] [blame]1197 case AArch64::LDAPURSHWi:
Sjoerd Meijer83a2a622018-07-12 14:57:59 +0000[diff] [blame]1198 case AArch64::LDAPURi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1199 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1200 break;
1201 case AArch64::LDURSBXi:
1202 case AArch64::LDURSHXi:
1203 case AArch64::LDURSWi:
1204 case AArch64::STURXi:
1205 case AArch64::LDURXi:
1206 case AArch64::LDTRSBXi:
1207 case AArch64::LDTRSHXi:
1208 case AArch64::LDTRSWi:
1209 case AArch64::STTRXi:
1210 case AArch64::LDTRXi:
1211 case AArch64::LDRSBXpre:
1212 case AArch64::LDRSHXpre:
1213 case AArch64::STRXpre:
1214 case AArch64::LDRSWpre:
1215 case AArch64::LDRXpre:
1216 case AArch64::LDRSBXpost:
1217 case AArch64::LDRSHXpost:
1218 case AArch64::STRXpost:
1219 case AArch64::LDRSWpost:
1220 case AArch64::LDRXpost:
Sjoerd Meijer83a2a622018-07-12 14:57:59 +0000[diff] [blame]1221 case AArch64::LDAPURSWi:
Sjoerd Meijerceabd502018-07-13 15:25:42 +0000[diff] [blame]1222 case AArch64::LDAPURSHXi:
1223 case AArch64::LDAPURSBXi:
1224 case AArch64::STLURXi:
1225 case AArch64::LDAPURXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1226 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1227 break;
1228 case AArch64::LDURQi:
1229 case AArch64::STURQi:
1230 case AArch64::LDRQpre:
1231 case AArch64::STRQpre:
1232 case AArch64::LDRQpost:
1233 case AArch64::STRQpost:
1234 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1235 break;
1236 case AArch64::LDURDi:
1237 case AArch64::STURDi:
1238 case AArch64::LDRDpre:
1239 case AArch64::STRDpre:
1240 case AArch64::LDRDpost:
1241 case AArch64::STRDpost:
1242 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1243 break;
1244 case AArch64::LDURSi:
1245 case AArch64::STURSi:
1246 case AArch64::LDRSpre:
1247 case AArch64::STRSpre:
1248 case AArch64::LDRSpost:
1249 case AArch64::STRSpost:
1250 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1251 break;
1252 case AArch64::LDURHi:
1253 case AArch64::STURHi:
1254 case AArch64::LDRHpre:
1255 case AArch64::STRHpre:
1256 case AArch64::LDRHpost:
1257 case AArch64::STRHpost:
1258 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1259 break;
1260 case AArch64::LDURBi:
1261 case AArch64::STURBi:
1262 case AArch64::LDRBpre:
1263 case AArch64::STRBpre:
1264 case AArch64::LDRBpost:
1265 case AArch64::STRBpost:
1266 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1267 break;
1268 }
1269
1270 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1271 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1272
1273 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1274 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1275 bool IsFP = fieldFromInstruction(insn, 26, 1);
1276
1277 // Cannot write back to a transfer register (but xzr != sp).
1278 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1279 return SoftFail;
1280
1281 return Success;
1282}
1283
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1284static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1285 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1286 const void *Decoder) {
1287 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1288 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1289 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1290 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1291
1292 unsigned Opcode = Inst.getOpcode();
1293 switch (Opcode) {
1294 default:
1295 return Fail;
1296 case AArch64::STLXRW:
1297 case AArch64::STLXRB:
1298 case AArch64::STLXRH:
1299 case AArch64::STXRW:
1300 case AArch64::STXRB:
1301 case AArch64::STXRH:
1302 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1303 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1304 case AArch64::LDARW:
1305 case AArch64::LDARB:
1306 case AArch64::LDARH:
1307 case AArch64::LDAXRW:
1308 case AArch64::LDAXRB:
1309 case AArch64::LDAXRH:
1310 case AArch64::LDXRW:
1311 case AArch64::LDXRB:
1312 case AArch64::LDXRH:
1313 case AArch64::STLRW:
1314 case AArch64::STLRB:
1315 case AArch64::STLRH:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1316 case AArch64::STLLRW:
1317 case AArch64::STLLRB:
1318 case AArch64::STLLRH:
1319 case AArch64::LDLARW:
1320 case AArch64::LDLARB:
1321 case AArch64::LDLARH:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1322 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1323 break;
1324 case AArch64::STLXRX:
1325 case AArch64::STXRX:
1326 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1327 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1328 case AArch64::LDARX:
1329 case AArch64::LDAXRX:
1330 case AArch64::LDXRX:
1331 case AArch64::STLRX:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1332 case AArch64::LDLARX:
1333 case AArch64::STLLRX:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1334 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1335 break;
1336 case AArch64::STLXPW:
1337 case AArch64::STXPW:
1338 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1339 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1340 case AArch64::LDAXPW:
1341 case AArch64::LDXPW:
1342 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1343 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1344 break;
1345 case AArch64::STLXPX:
1346 case AArch64::STXPX:
1347 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1348 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1349 case AArch64::LDAXPX:
1350 case AArch64::LDXPX:
1351 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1352 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1353 break;
1354 }
1355
1356 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1357
1358 // You shouldn't load to the same register twice in an instruction...
1359 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1360 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1361 Rt == Rt2)
1362 return SoftFail;
1363
1364 return Success;
1365}
1366
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1367static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1368 uint64_t Addr,
1369 const void *Decoder) {
1370 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1371 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1372 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1373 int64_t offset = fieldFromInstruction(insn, 15, 7);
1374 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1375
1376 // offset is a 7-bit signed immediate, so sign extend it to
1377 // fill the unsigned.
1378 if (offset & (1 << (7 - 1)))
1379 offset |= ~((1LL << 7) - 1);
1380
1381 unsigned Opcode = Inst.getOpcode();
1382 bool NeedsDisjointWritebackTransfer = false;
1383
1384 // First operand is always writeback of base register.
1385 switch (Opcode) {
1386 default:
1387 break;
1388 case AArch64::LDPXpost:
1389 case AArch64::STPXpost:
1390 case AArch64::LDPSWpost:
1391 case AArch64::LDPXpre:
1392 case AArch64::STPXpre:
1393 case AArch64::LDPSWpre:
1394 case AArch64::LDPWpost:
1395 case AArch64::STPWpost:
1396 case AArch64::LDPWpre:
1397 case AArch64::STPWpre:
1398 case AArch64::LDPQpost:
1399 case AArch64::STPQpost:
1400 case AArch64::LDPQpre:
1401 case AArch64::STPQpre:
1402 case AArch64::LDPDpost:
1403 case AArch64::STPDpost:
1404 case AArch64::LDPDpre:
1405 case AArch64::STPDpre:
1406 case AArch64::LDPSpost:
1407 case AArch64::STPSpost:
1408 case AArch64::LDPSpre:
1409 case AArch64::STPSpre:
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]1410 case AArch64::STGPpre:
1411 case AArch64::STGPpost:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1412 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1413 break;
1414 }
1415
1416 switch (Opcode) {
1417 default:
1418 return Fail;
1419 case AArch64::LDPXpost:
1420 case AArch64::STPXpost:
1421 case AArch64::LDPSWpost:
1422 case AArch64::LDPXpre:
1423 case AArch64::STPXpre:
1424 case AArch64::LDPSWpre:
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]1425 case AArch64::STGPpre:
1426 case AArch64::STGPpost:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1427 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1428 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1429 case AArch64::LDNPXi:
1430 case AArch64::STNPXi:
1431 case AArch64::LDPXi:
1432 case AArch64::STPXi:
1433 case AArch64::LDPSWi:
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]1434 case AArch64::STGPi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1435 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1436 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1437 break;
1438 case AArch64::LDPWpost:
1439 case AArch64::STPWpost:
1440 case AArch64::LDPWpre:
1441 case AArch64::STPWpre:
1442 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1443 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1444 case AArch64::LDNPWi:
1445 case AArch64::STNPWi:
1446 case AArch64::LDPWi:
1447 case AArch64::STPWi:
1448 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1449 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1450 break;
1451 case AArch64::LDNPQi:
1452 case AArch64::STNPQi:
1453 case AArch64::LDPQpost:
1454 case AArch64::STPQpost:
1455 case AArch64::LDPQi:
1456 case AArch64::STPQi:
1457 case AArch64::LDPQpre:
1458 case AArch64::STPQpre:
1459 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1460 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1461 break;
1462 case AArch64::LDNPDi:
1463 case AArch64::STNPDi:
1464 case AArch64::LDPDpost:
1465 case AArch64::STPDpost:
1466 case AArch64::LDPDi:
1467 case AArch64::STPDi:
1468 case AArch64::LDPDpre:
1469 case AArch64::STPDpre:
1470 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1471 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1472 break;
1473 case AArch64::LDNPSi:
1474 case AArch64::STNPSi:
1475 case AArch64::LDPSpost:
1476 case AArch64::STPSpost:
1477 case AArch64::LDPSi:
1478 case AArch64::STPSi:
1479 case AArch64::LDPSpre:
1480 case AArch64::STPSpre:
1481 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1482 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1483 break;
1484 }
1485
1486 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1487 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1488
1489 // You shouldn't load to the same register twice in an instruction...
1490 if (IsLoad && Rt == Rt2)
1491 return SoftFail;
1492
1493 // ... or do any operation that writes-back to a transfer register. But note
1494 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1495 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1496 return SoftFail;
1497
1498 return Success;
1499}
1500
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1501static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1502 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1503 const void *Decoder) {
1504 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1505 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1506 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1507 unsigned extend = fieldFromInstruction(insn, 10, 6);
1508
1509 unsigned shift = extend & 0x7;
1510 if (shift > 4)
1511 return Fail;
1512
1513 switch (Inst.getOpcode()) {
1514 default:
1515 return Fail;
1516 case AArch64::ADDWrx:
1517 case AArch64::SUBWrx:
1518 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1519 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1520 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1521 break;
1522 case AArch64::ADDSWrx:
1523 case AArch64::SUBSWrx:
1524 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1525 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1526 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1527 break;
1528 case AArch64::ADDXrx:
1529 case AArch64::SUBXrx:
1530 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1531 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1532 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1533 break;
1534 case AArch64::ADDSXrx:
1535 case AArch64::SUBSXrx:
1536 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1537 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1538 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1539 break;
1540 case AArch64::ADDXrx64:
1541 case AArch64::SUBXrx64:
1542 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1543 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1544 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1545 break;
1546 case AArch64::SUBSXrx64:
1547 case AArch64::ADDSXrx64:
1548 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1549 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1550 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1551 break;
1552 }
1553
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1554 Inst.addOperand(MCOperand::createImm(extend));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1555 return Success;
1556}
1557
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1558static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1559 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1560 const void *Decoder) {
1561 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1562 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1563 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1564 unsigned imm;
1565
1566 if (Datasize) {
1567 if (Inst.getOpcode() == AArch64::ANDSXri)
1568 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1569 else
1570 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1571 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1572 imm = fieldFromInstruction(insn, 10, 13);
1573 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1574 return Fail;
1575 } else {
1576 if (Inst.getOpcode() == AArch64::ANDSWri)
1577 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1578 else
1579 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1580 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1581 imm = fieldFromInstruction(insn, 10, 12);
1582 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1583 return Fail;
1584 }
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1585 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1586 return Success;
1587}
1588
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1589static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1590 uint64_t Addr,
1591 const void *Decoder) {
1592 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1593 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1594 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1595 imm |= fieldFromInstruction(insn, 5, 5);
1596
1597 if (Inst.getOpcode() == AArch64::MOVID)
1598 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1599 else
1600 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1601
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1602 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1603
1604 switch (Inst.getOpcode()) {
1605 default:
1606 break;
1607 case AArch64::MOVIv4i16:
1608 case AArch64::MOVIv8i16:
1609 case AArch64::MVNIv4i16:
1610 case AArch64::MVNIv8i16:
1611 case AArch64::MOVIv2i32:
1612 case AArch64::MOVIv4i32:
1613 case AArch64::MVNIv2i32:
1614 case AArch64::MVNIv4i32:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1615 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1616 break;
1617 case AArch64::MOVIv2s_msl:
1618 case AArch64::MOVIv4s_msl:
1619 case AArch64::MVNIv2s_msl:
1620 case AArch64::MVNIv4s_msl:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1621 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1622 break;
1623 }
1624
1625 return Success;
1626}
1627
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1628static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1629 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1630 const void *Decoder) {
1631 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1632 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1633 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1634 imm |= fieldFromInstruction(insn, 5, 5);
1635
1636 // Tied operands added twice.
1637 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1638 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1639
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1640 Inst.addOperand(MCOperand::createImm(imm));
1641 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1642
1643 return Success;
1644}
1645
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1646static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1647 uint64_t Addr, const void *Decoder) {
1648 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1649 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1650 imm |= fieldFromInstruction(insn, 29, 2);
1651 const AArch64Disassembler *Dis =
1652 static_cast<const AArch64Disassembler *>(Decoder);
1653
1654 // Sign-extend the 21-bit immediate.
1655 if (imm & (1 << (21 - 1)))
1656 imm |= ~((1LL << 21) - 1);
1657
1658 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1659 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1660 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1661
1662 return Success;
1663}
1664
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]1665static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1666 uint64_t Addr, const void *Decoder) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1667 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1668 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1669 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1670 unsigned S = fieldFromInstruction(insn, 29, 1);
1671 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1672
1673 unsigned ShifterVal = (Imm >> 12) & 3;
1674 unsigned ImmVal = Imm & 0xFFF;
1675 const AArch64Disassembler *Dis =
1676 static_cast<const AArch64Disassembler *>(Decoder);
1677
1678 if (ShifterVal != 0 && ShifterVal != 1)
1679 return Fail;
1680
1681 if (Datasize) {
1682 if (Rd == 31 && !S)
1683 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1684 else
1685 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1686 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1687 } else {
1688 if (Rd == 31 && !S)
1689 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1690 else
1691 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1692 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1693 }
1694
1695 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1696 Inst.addOperand(MCOperand::createImm(ImmVal));
1697 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1698 return Success;
1699}
1700
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1701static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1702 uint64_t Addr,
1703 const void *Decoder) {
1704 int64_t imm = fieldFromInstruction(insn, 0, 26);
1705 const AArch64Disassembler *Dis =
1706 static_cast<const AArch64Disassembler *>(Decoder);
1707
1708 // Sign-extend the 26-bit immediate.
1709 if (imm & (1 << (26 - 1)))
1710 imm |= ~((1LL << 26) - 1);
1711
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1712 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1713 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1714
1715 return Success;
1716}
1717
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1718static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1719 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1720 const void *Decoder) {
1721 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1722 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1723 uint64_t crm = fieldFromInstruction(insn, 8, 4);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1724 uint64_t pstate_field = (op1 << 3) | op2;
1725
Oliver Stannard31af1782018-09-27 09:11:27 +0000[diff] [blame]1726 switch (pstate_field) {
1727 case 0x01: // XAFlag
1728 case 0x02: // AXFlag
1729 return Fail;
1730 }
1731
Oliver Stannard911ea202015-11-26 15:32:30 +0000[diff] [blame]1732 if ((pstate_field == AArch64PState::PAN ||
Oliver Stannard8459d342018-09-27 14:05:46 +0000[diff] [blame]1733 pstate_field == AArch64PState::UAO ||
1734 pstate_field == AArch64PState::SSBS) && crm > 1)
Alexandros Lamprineas1bab1912015-10-05 13:42:31 +0000[diff] [blame]1735 return Fail;
1736
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1737 Inst.addOperand(MCOperand::createImm(pstate_field));
1738 Inst.addOperand(MCOperand::createImm(crm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1739
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1740 const AArch64Disassembler *Dis =
Vladimir Sukhareva98f6892015-04-16 12:15:27 +0000[diff] [blame]1741 static_cast<const AArch64Disassembler *>(Decoder);
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1742 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1743 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1744 return Success;
1745 return Fail;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1746}
1747
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1748static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1749 uint64_t Addr, const void *Decoder) {
1750 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1751 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1752 bit |= fieldFromInstruction(insn, 19, 5);
1753 int64_t dst = fieldFromInstruction(insn, 5, 14);
1754 const AArch64Disassembler *Dis =
1755 static_cast<const AArch64Disassembler *>(Decoder);
1756
1757 // Sign-extend 14-bit immediate.
1758 if (dst & (1 << (14 - 1)))
1759 dst |= ~((1LL << 14) - 1);
1760
1761 if (fieldFromInstruction(insn, 31, 1) == 0)
1762 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1763 else
1764 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1765 Inst.addOperand(MCOperand::createImm(bit));
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1766 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1767 Inst.addOperand(MCOperand::createImm(dst));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1768
1769 return Success;
1770}
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1771
1772static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1773 unsigned RegClassID,
1774 unsigned RegNo,
1775 uint64_t Addr,
1776 const void *Decoder) {
1777 // Register number must be even (see CASP instruction)
1778 if (RegNo & 0x1)
1779 return Fail;
1780
1781 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
1782 Inst.addOperand(MCOperand::createReg(Register));
1783 return Success;
1784}
1785
1786static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1787 unsigned RegNo,
1788 uint64_t Addr,
1789 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1790 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1791 AArch64::WSeqPairsClassRegClassID,
1792 RegNo, Addr, Decoder);
1793}
1794
1795static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1796 unsigned RegNo,
1797 uint64_t Addr,
1798 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1799 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1800 AArch64::XSeqPairsClassRegClassID,
1801 RegNo, Addr, Decoder);
1802}
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1803
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]1804static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1805 uint32_t insn,
1806 uint64_t Addr,
1807 const void *Decoder) {
1808 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1809 unsigned imm = fieldFromInstruction(insn, 5, 13);
1810 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1811 return Fail;
1812
1813 // The same (tied) operand is added twice to the instruction.
1814 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
Sander de Smalen97ca6b92018-06-01 07:25:46 +0000[diff] [blame]1815 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1816 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]1817 Inst.addOperand(MCOperand::createImm(imm));
1818 return Success;
1819}
1820
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1821template<int Bits>
1822static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1823 uint64_t Address, const void *Decoder) {
1824 if (Imm & ~((1LL << Bits) - 1))
1825 return Fail;
1826
1827 // Imm is a signed immediate, so sign extend it.
1828 if (Imm & (1 << (Bits - 1)))
1829 Imm |= ~((1LL << Bits) - 1);
1830
1831 Inst.addOperand(MCOperand::createImm(Imm));
1832 return Success;
1833}
1834
Sander de Smalen62770792018-05-25 09:47:52 +0000[diff] [blame]1835// Decode 8-bit signed/unsigned immediate for a given element width.
1836template <int ElementWidth>
1837static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
1838 uint64_t Addr, const void *Decoder) {
1839 unsigned Val = (uint8_t)Imm;
1840 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1841 if (ElementWidth == 8 && Shift)
1842 return Fail;
1843 Inst.addOperand(MCOperand::createImm(Val));
1844 Inst.addOperand(MCOperand::createImm(Shift));
1845 return Success;
1846}
Sander de Smalen18ac8f92018-06-15 15:47:44 +0000[diff] [blame]1847
1848// Decode uimm4 ranged from 1-16.
1849static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1850 uint64_t Addr, const void *Decoder) {
1851 Inst.addOperand(MCOperand::createImm(Imm + 1));
1852 return Success;
1853}
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]1854
1855static DecodeStatus DecodeLoadAllocTagArrayInstruction(MCInst &Inst,
1856 uint32_t insn,
1857 uint64_t address,
1858 const void* Decoder) {
1859 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1860 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1861
1862 // Outputs
1863 DecodeGPR64spRegisterClass(Inst, Rn, address, Decoder);
1864 DecodeGPR64RegisterClass(Inst, Rt, address, Decoder);
1865
1866 // Input (Rn again)
1867 Inst.addOperand(Inst.getOperand(0));
1868
1869 //Do this post decode since the raw number for xzr and sp is the same
1870 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
1871 return SoftFail;
1872 } else {
1873 return Success;
1874 }
1875}