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gerrit-public.fairphone.software / toolchain / llvm-project / 4a3be6e5786f6a0ad96fc2e98f10ef801c5bdb93 / . / llvm / lib / Target / X86 / X86SchedBroadwell.td
blob: 76199f0d1ac262b9c5cbaf0d8149794862122235 [file] [log] [blame]
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Broadwell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
16 // instructions per cycle.
17 let IssueWidth = 4;
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 16;
21
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]24
25 // This flag is set to allow the scheduler to assign a default model to
26 // unrecognized opcodes.
27 let CompleteModel = 0;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]28}
29
30let SchedModel = BroadwellModel in {
31
32// Broadwell can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def BWPort0 : ProcResource<1>;
41def BWPort1 : ProcResource<1>;
42def BWPort2 : ProcResource<1>;
43def BWPort3 : ProcResource<1>;
44def BWPort4 : ProcResource<1>;
45def BWPort5 : ProcResource<1>;
46def BWPort6 : ProcResource<1>;
47def BWPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
62
63// 60 Entry Unified Scheduler
64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
66 let BufferSize=60;
67}
68
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]69// Integer division issued on port 0.
70def BWDivider : ProcResource<1>; // Integer division issued on port 0.
71
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]72// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
73// cycles after the memory operand.
74def : ReadAdvance<ReadAfterLd, 5>;
75
76// Many SchedWrites are defined in pairs with and without a folded load.
77// Instructions with folded loads are usually micro-fused, so they only appear
78// as two micro-ops when queued in the reservation station.
79// This multiclass defines the resource usage for variants with and without
80// folded loads.
81multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]82 list<ProcResourceKind> ExePorts,
83 int Lat, list<int> Res = [1], int UOps = 1> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]84 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]85 def : WriteRes<SchedRW, ExePorts> {
86 let Latency = Lat;
87 let ResourceCycles = Res;
88 let NumMicroOps = UOps;
89 }
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]90
91 // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
92 // latency.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]93 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
94 let Latency = !add(Lat, 5);
95 let ResourceCycles = !listconcat([1], Res);
96 let NumMicroOps = UOps;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]97 }
98}
99
100// A folded store needs a cycle on port 4 for the store data, but it does not
101// need an extra port 2/3 cycle to recompute the address.
102def : WriteRes<WriteRMW, [BWPort4]>;
103
104// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]105defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
106defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
107defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]108def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]109
110def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
111
112// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]113defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]114
115// Loads, stores, and moves, not folded with other operations.
116def : WriteRes<WriteLoad, [BWPort23]> { let Latency = 5; }
117def : WriteRes<WriteStore, [BWPort237, BWPort4]>;
118def : WriteRes<WriteMove, [BWPort0156]>;
119
120// Idioms that clear a register, like xorps %xmm0, %xmm0.
121// These can often bypass execution ports completely.
122def : WriteRes<WriteZero, []>;
123
Sanjoy Das1074eb22017-12-12 19:11:31 +0000[diff] [blame]124// Treat misc copies as a move.
125def : InstRW<[WriteMove], (instrs COPY)>;
126
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]127// Branches don't produce values, so they have no latency, but they still
128// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]129defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]130
131// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]132def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
133def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
134def : WriteRes<WriteFMove, [BWPort5]>;
135
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]136defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare.
137defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
138defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
139defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
140defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
141defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
142defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
143defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
144defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
145defm : BWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]146
147// FMA Scheduling helper class.
148// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
149
150// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]151def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
152def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
153def : WriteRes<WriteVecMove, [BWPort015]>;
154
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]155defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
156defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
157defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
158defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
159defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
160defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
161defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]162
163// Vector bitwise operations.
164// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]165defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]166
167// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]168defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
169defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
170defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]171
172// Strings instructions.
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]173
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]174// Packed Compare Implicit Length Strings, Return Mask
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]175def : WriteRes<WritePCmpIStrM, [BWPort0]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]176 let Latency = 11;
177 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]178 let ResourceCycles = [3];
179}
180def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]181 let Latency = 16;
182 let NumMicroOps = 4;
183 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]184}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]185
186// Packed Compare Explicit Length Strings, Return Mask
187def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
188 let Latency = 19;
189 let NumMicroOps = 9;
190 let ResourceCycles = [4,3,1,1];
191}
192def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
193 let Latency = 24;
194 let NumMicroOps = 10;
195 let ResourceCycles = [4,3,1,1,1];
196}
197
198// Packed Compare Implicit Length Strings, Return Index
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]199def : WriteRes<WritePCmpIStrI, [BWPort0]> {
200 let Latency = 11;
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]201 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]202 let ResourceCycles = [3];
203}
204def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]205 let Latency = 16;
206 let NumMicroOps = 4;
207 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]208}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]209
210// Packed Compare Explicit Length Strings, Return Index
211def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
212 let Latency = 18;
213 let NumMicroOps = 8;
214 let ResourceCycles = [4,3,1];
215}
216def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
217 let Latency = 23;
218 let NumMicroOps = 9;
219 let ResourceCycles = [4,3,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]220}
221
222// AES instructions.
223def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
224 let Latency = 7;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]225 let NumMicroOps = 1;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]226 let ResourceCycles = [1];
227}
228def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]229 let Latency = 12;
230 let NumMicroOps = 2;
231 let ResourceCycles = [1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]232}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]233
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]234def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
235 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]236 let NumMicroOps = 2;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]237 let ResourceCycles = [2];
238}
239def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]240 let Latency = 19;
241 let NumMicroOps = 3;
242 let ResourceCycles = [2,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]243}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]244
245def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
246 let Latency = 29;
247 let NumMicroOps = 11;
248 let ResourceCycles = [2,7,2];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]249}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]250def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
251 let Latency = 33;
252 let NumMicroOps = 11;
253 let ResourceCycles = [2,7,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]254}
255
256// Carry-less multiplication instructions.
Simon Pilgrim3b2ff1f2018-03-22 13:37:30 +0000[diff] [blame]257defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]258
259// Catch-all for expensive system instructions.
260def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
261
262// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]263defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
264defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
265defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]266
267// Old microcoded instructions that nobody use.
268def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
269
270// Fence instructions.
271def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
272
273// Nop, not very useful expect it provides a model for nops!
274def : WriteRes<WriteNop, []>;
275
276////////////////////////////////////////////////////////////////////////////////
277// Horizontal add/sub instructions.
278////////////////////////////////////////////////////////////////////////////////
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]279
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]280defm : BWWriteResPair<WriteFHAdd, [BWPort1], 3>;
281defm : BWWriteResPair<WritePHAdd, [BWPort15], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]282
283// Remaining instrs.
284
285def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
286 let Latency = 1;
287 let NumMicroOps = 1;
288 let ResourceCycles = [1];
289}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]290def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
291 "MMX_MOVD64grr",
292 "MMX_PMOVMSKBrr",
293 "MMX_PSLLDri",
294 "MMX_PSLLDrr",
295 "MMX_PSLLQri",
296 "MMX_PSLLQrr",
297 "MMX_PSLLWri",
298 "MMX_PSLLWrr",
299 "MMX_PSRADri",
300 "MMX_PSRADrr",
301 "MMX_PSRAWri",
302 "MMX_PSRAWrr",
303 "MMX_PSRLDri",
304 "MMX_PSRLDrr",
305 "MMX_PSRLQri",
306 "MMX_PSRLQrr",
307 "MMX_PSRLWri",
308 "MMX_PSRLWrr",
309 "MOVPDI2DIrr",
310 "MOVPQIto64rr",
311 "PSLLDri",
312 "PSLLQri",
313 "PSLLWri",
314 "PSRADri",
315 "PSRAWri",
316 "PSRLDri",
317 "PSRLQri",
318 "PSRLWri",
319 "VMOVPDI2DIrr",
320 "VMOVPQIto64rr",
321 "VPSLLDYri",
322 "VPSLLDri",
323 "VPSLLQYri",
324 "VPSLLQri",
325 "VPSLLVQYrr",
326 "VPSLLVQrr",
327 "VPSLLWYri",
328 "VPSLLWri",
329 "VPSRADYri",
330 "VPSRADri",
331 "VPSRAWYri",
332 "VPSRAWri",
333 "VPSRLDYri",
334 "VPSRLDri",
335 "VPSRLQYri",
336 "VPSRLQri",
337 "VPSRLVQYrr",
338 "VPSRLVQrr",
339 "VPSRLWYri",
340 "VPSRLWri",
341 "VTESTPDYrr",
342 "VTESTPDrr",
343 "VTESTPSYrr",
344 "VTESTPSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]345
346def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
347 let Latency = 1;
348 let NumMicroOps = 1;
349 let ResourceCycles = [1];
350}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]351def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r",
352 "COM_FST0r",
353 "UCOM_FPr",
354 "UCOM_Fr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]355
356def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
357 let Latency = 1;
358 let NumMicroOps = 1;
359 let ResourceCycles = [1];
360}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]361def: InstRW<[BWWriteResGroup3], (instregex "ANDNPDrr",
362 "ANDNPSrr",
363 "ANDPDrr",
364 "ANDPSrr",
365 "INSERTPSrr",
366 "MMX_MOVD64rr",
367 "MMX_MOVD64to64rr",
368 "MMX_MOVQ2DQrr",
369 "MMX_PALIGNRrri",
370 "MMX_PSHUFBrr",
371 "MMX_PSHUFWri",
372 "MMX_PUNPCKHBWirr",
373 "MMX_PUNPCKHDQirr",
374 "MMX_PUNPCKHWDirr",
375 "MMX_PUNPCKLBWirr",
376 "MMX_PUNPCKLDQirr",
377 "MMX_PUNPCKLWDirr",
378 "MOV64toPQIrr",
379 "MOVAPDrr",
380 "MOVAPSrr",
381 "MOVDDUPrr",
382 "MOVDI2PDIrr",
383 "MOVHLPSrr",
384 "MOVLHPSrr",
385 "MOVSDrr",
386 "MOVSHDUPrr",
387 "MOVSLDUPrr",
388 "MOVSSrr",
389 "MOVUPDrr",
390 "MOVUPSrr",
391 "ORPDrr",
392 "ORPSrr",
393 "PACKSSDWrr",
394 "PACKSSWBrr",
395 "PACKUSDWrr",
396 "PACKUSWBrr",
397 "PALIGNRrri",
398 "PBLENDWrri",
399 "PMOVSXBDrr",
400 "PMOVSXBQrr",
401 "PMOVSXBWrr",
402 "PMOVSXDQrr",
403 "PMOVSXWDrr",
404 "PMOVSXWQrr",
405 "PMOVZXBDrr",
406 "PMOVZXBQrr",
407 "PMOVZXBWrr",
408 "PMOVZXDQrr",
409 "PMOVZXWDrr",
410 "PMOVZXWQrr",
411 "PSHUFBrr",
412 "PSHUFDri",
413 "PSHUFHWri",
414 "PSHUFLWri",
415 "PSLLDQri",
416 "PSRLDQri",
417 "PUNPCKHBWrr",
418 "PUNPCKHDQrr",
419 "PUNPCKHQDQrr",
420 "PUNPCKHWDrr",
421 "PUNPCKLBWrr",
422 "PUNPCKLDQrr",
423 "PUNPCKLQDQrr",
424 "PUNPCKLWDrr",
425 "SHUFPDrri",
426 "SHUFPSrri",
427 "UNPCKHPDrr",
428 "UNPCKHPSrr",
429 "UNPCKLPDrr",
430 "UNPCKLPSrr",
431 "VANDNPDYrr",
432 "VANDNPDrr",
433 "VANDNPSYrr",
434 "VANDNPSrr",
435 "VANDPDYrr",
436 "VANDPDrr",
437 "VANDPSYrr",
438 "VANDPSrr",
439 "VBROADCASTSSrr",
440 "VINSERTPSrr",
441 "VMOV64toPQIrr",
442 "VMOVAPDYrr",
443 "VMOVAPDrr",
444 "VMOVAPSYrr",
445 "VMOVAPSrr",
446 "VMOVDDUPYrr",
447 "VMOVDDUPrr",
448 "VMOVDI2PDIrr",
449 "VMOVHLPSrr",
450 "VMOVLHPSrr",
451 "VMOVSDrr",
452 "VMOVSHDUPYrr",
453 "VMOVSHDUPrr",
454 "VMOVSLDUPYrr",
455 "VMOVSLDUPrr",
456 "VMOVSSrr",
457 "VMOVUPDYrr",
458 "VMOVUPDrr",
459 "VMOVUPSYrr",
460 "VMOVUPSrr",
461 "VORPDYrr",
462 "VORPDrr",
463 "VORPSYrr",
464 "VORPSrr",
465 "VPACKSSDWYrr",
466 "VPACKSSDWrr",
467 "VPACKSSWBYrr",
468 "VPACKSSWBrr",
469 "VPACKUSDWYrr",
470 "VPACKUSDWrr",
471 "VPACKUSWBYrr",
472 "VPACKUSWBrr",
473 "VPALIGNRYrri",
474 "VPALIGNRrri",
475 "VPBLENDWYrri",
476 "VPBLENDWrri",
477 "VPBROADCASTDrr",
478 "VPBROADCASTQrr",
479 "VPERMILPDYri",
480 "VPERMILPDYrr",
481 "VPERMILPDri",
482 "VPERMILPDrr",
483 "VPERMILPSYri",
484 "VPERMILPSYrr",
485 "VPERMILPSri",
486 "VPERMILPSrr",
487 "VPMOVSXBDrr",
488 "VPMOVSXBQrr",
489 "VPMOVSXBWrr",
490 "VPMOVSXDQrr",
491 "VPMOVSXWDrr",
492 "VPMOVSXWQrr",
493 "VPMOVZXBDrr",
494 "VPMOVZXBQrr",
495 "VPMOVZXBWrr",
496 "VPMOVZXDQrr",
497 "VPMOVZXWDrr",
498 "VPMOVZXWQrr",
499 "VPSHUFBYrr",
500 "VPSHUFBrr",
501 "VPSHUFDYri",
502 "VPSHUFDri",
503 "VPSHUFHWYri",
504 "VPSHUFHWri",
505 "VPSHUFLWYri",
506 "VPSHUFLWri",
507 "VPSLLDQYri",
508 "VPSLLDQri",
509 "VPSRLDQYri",
510 "VPSRLDQri",
511 "VPUNPCKHBWYrr",
512 "VPUNPCKHBWrr",
513 "VPUNPCKHDQYrr",
514 "VPUNPCKHDQrr",
515 "VPUNPCKHQDQYrr",
516 "VPUNPCKHQDQrr",
517 "VPUNPCKHWDYrr",
518 "VPUNPCKHWDrr",
519 "VPUNPCKLBWYrr",
520 "VPUNPCKLBWrr",
521 "VPUNPCKLDQYrr",
522 "VPUNPCKLDQrr",
523 "VPUNPCKLQDQYrr",
524 "VPUNPCKLQDQrr",
525 "VPUNPCKLWDYrr",
526 "VPUNPCKLWDrr",
527 "VSHUFPDYrri",
528 "VSHUFPDrri",
529 "VSHUFPSYrri",
530 "VSHUFPSrri",
531 "VUNPCKHPDYrr",
532 "VUNPCKHPDrr",
533 "VUNPCKHPSYrr",
534 "VUNPCKHPSrr",
535 "VUNPCKLPDYrr",
536 "VUNPCKLPDrr",
537 "VUNPCKLPSYrr",
538 "VUNPCKLPSrr",
539 "VXORPDYrr",
540 "VXORPDrr",
541 "VXORPSYrr",
542 "VXORPSrr",
543 "XORPDrr",
544 "XORPSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]545
546def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
547 let Latency = 1;
548 let NumMicroOps = 1;
549 let ResourceCycles = [1];
550}
551def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
552
553def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
554 let Latency = 1;
555 let NumMicroOps = 1;
556 let ResourceCycles = [1];
557}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]558def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP",
559 "FNOP")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]560
561def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
562 let Latency = 1;
563 let NumMicroOps = 1;
564 let ResourceCycles = [1];
565}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]566def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
567 "ADC(16|32|64)i",
568 "ADC(8|16|32|64)rr",
569 "ADCX(32|64)rr",
570 "ADOX(32|64)rr",
571 "BT(16|32|64)ri8",
572 "BT(16|32|64)rr",
573 "BTC(16|32|64)ri8",
574 "BTC(16|32|64)rr",
575 "BTR(16|32|64)ri8",
576 "BTR(16|32|64)rr",
577 "BTS(16|32|64)ri8",
578 "BTS(16|32|64)rr",
579 "CDQ",
580 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
581 "CQO",
582 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
583 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
584 "JMP_1",
585 "JMP_4",
586 "RORX(32|64)ri",
587 "SAR(8|16|32|64)r1",
588 "SAR(8|16|32|64)ri",
589 "SARX(32|64)rr",
590 "SBB(16|32|64)ri",
591 "SBB(16|32|64)i",
592 "SBB(8|16|32|64)rr",
593 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
594 "SHL(8|16|32|64)r1",
595 "SHL(8|16|32|64)ri",
596 "SHLX(32|64)rr",
597 "SHR(8|16|32|64)r1",
598 "SHR(8|16|32|64)ri",
599 "SHRX(32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]600
601def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
602 let Latency = 1;
603 let NumMicroOps = 1;
604 let ResourceCycles = [1];
605}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]606def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
607 "BLSI(32|64)rr",
608 "BLSMSK(32|64)rr",
609 "BLSR(32|64)rr",
610 "BZHI(32|64)rr",
611 "LEA(16|32|64)(_32)?r",
612 "MMX_PABSBrr",
613 "MMX_PABSDrr",
614 "MMX_PABSWrr",
615 "MMX_PADDBirr",
616 "MMX_PADDDirr",
617 "MMX_PADDQirr",
618 "MMX_PADDSBirr",
619 "MMX_PADDSWirr",
620 "MMX_PADDUSBirr",
621 "MMX_PADDUSWirr",
622 "MMX_PADDWirr",
623 "MMX_PAVGBirr",
624 "MMX_PAVGWirr",
625 "MMX_PCMPEQBirr",
626 "MMX_PCMPEQDirr",
627 "MMX_PCMPEQWirr",
628 "MMX_PCMPGTBirr",
629 "MMX_PCMPGTDirr",
630 "MMX_PCMPGTWirr",
631 "MMX_PMAXSWirr",
632 "MMX_PMAXUBirr",
633 "MMX_PMINSWirr",
634 "MMX_PMINUBirr",
635 "MMX_PSIGNBrr",
636 "MMX_PSIGNDrr",
637 "MMX_PSIGNWrr",
638 "MMX_PSUBBirr",
639 "MMX_PSUBDirr",
640 "MMX_PSUBQirr",
641 "MMX_PSUBSBirr",
642 "MMX_PSUBSWirr",
643 "MMX_PSUBUSBirr",
644 "MMX_PSUBUSWirr",
645 "MMX_PSUBWirr",
646 "PABSBrr",
647 "PABSDrr",
648 "PABSWrr",
649 "PADDBrr",
650 "PADDDrr",
651 "PADDQrr",
652 "PADDSBrr",
653 "PADDSWrr",
654 "PADDUSBrr",
655 "PADDUSWrr",
656 "PADDWrr",
657 "PAVGBrr",
658 "PAVGWrr",
659 "PCMPEQBrr",
660 "PCMPEQDrr",
661 "PCMPEQQrr",
662 "PCMPEQWrr",
663 "PCMPGTBrr",
664 "PCMPGTDrr",
665 "PCMPGTWrr",
666 "PMAXSBrr",
667 "PMAXSDrr",
668 "PMAXSWrr",
669 "PMAXUBrr",
670 "PMAXUDrr",
671 "PMAXUWrr",
672 "PMINSBrr",
673 "PMINSDrr",
674 "PMINSWrr",
675 "PMINUBrr",
676 "PMINUDrr",
677 "PMINUWrr",
678 "PSIGNBrr",
679 "PSIGNDrr",
680 "PSIGNWrr",
681 "PSUBBrr",
682 "PSUBDrr",
683 "PSUBQrr",
684 "PSUBSBrr",
685 "PSUBSWrr",
686 "PSUBUSBrr",
687 "PSUBUSWrr",
688 "PSUBWrr",
689 "VPABSBYrr",
690 "VPABSBrr",
691 "VPABSDYrr",
692 "VPABSDrr",
693 "VPABSWYrr",
694 "VPABSWrr",
695 "VPADDBYrr",
696 "VPADDBrr",
697 "VPADDDYrr",
698 "VPADDDrr",
699 "VPADDQYrr",
700 "VPADDQrr",
701 "VPADDSBYrr",
702 "VPADDSBrr",
703 "VPADDSWYrr",
704 "VPADDSWrr",
705 "VPADDUSBYrr",
706 "VPADDUSBrr",
707 "VPADDUSWYrr",
708 "VPADDUSWrr",
709 "VPADDWYrr",
710 "VPADDWrr",
711 "VPAVGBYrr",
712 "VPAVGBrr",
713 "VPAVGWYrr",
714 "VPAVGWrr",
715 "VPCMPEQBYrr",
716 "VPCMPEQBrr",
717 "VPCMPEQDYrr",
718 "VPCMPEQDrr",
719 "VPCMPEQQYrr",
720 "VPCMPEQQrr",
721 "VPCMPEQWYrr",
722 "VPCMPEQWrr",
723 "VPCMPGTBYrr",
724 "VPCMPGTBrr",
725 "VPCMPGTDYrr",
726 "VPCMPGTDrr",
727 "VPCMPGTWYrr",
728 "VPCMPGTWrr",
729 "VPMAXSBYrr",
730 "VPMAXSBrr",
731 "VPMAXSDYrr",
732 "VPMAXSDrr",
733 "VPMAXSWYrr",
734 "VPMAXSWrr",
735 "VPMAXUBYrr",
736 "VPMAXUBrr",
737 "VPMAXUDYrr",
738 "VPMAXUDrr",
739 "VPMAXUWYrr",
740 "VPMAXUWrr",
741 "VPMINSBYrr",
742 "VPMINSBrr",
743 "VPMINSDYrr",
744 "VPMINSDrr",
745 "VPMINSWYrr",
746 "VPMINSWrr",
747 "VPMINUBYrr",
748 "VPMINUBrr",
749 "VPMINUDYrr",
750 "VPMINUDrr",
751 "VPMINUWYrr",
752 "VPMINUWrr",
753 "VPSIGNBYrr",
754 "VPSIGNBrr",
755 "VPSIGNDYrr",
756 "VPSIGNDrr",
757 "VPSIGNWYrr",
758 "VPSIGNWrr",
759 "VPSUBBYrr",
760 "VPSUBBrr",
761 "VPSUBDYrr",
762 "VPSUBDrr",
763 "VPSUBQYrr",
764 "VPSUBQrr",
765 "VPSUBSBYrr",
766 "VPSUBSBrr",
767 "VPSUBSWYrr",
768 "VPSUBSWrr",
769 "VPSUBUSBYrr",
770 "VPSUBUSBrr",
771 "VPSUBUSWYrr",
772 "VPSUBUSWrr",
773 "VPSUBWYrr",
774 "VPSUBWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]775
776def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
777 let Latency = 1;
778 let NumMicroOps = 1;
779 let ResourceCycles = [1];
780}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]781def: InstRW<[BWWriteResGroup8], (instregex "BLENDPDrri",
782 "BLENDPSrri",
783 "MMX_MOVQ64rr",
784 "MMX_PANDNirr",
785 "MMX_PANDirr",
786 "MMX_PORirr",
787 "MMX_PXORirr",
788 "MOVDQArr",
789 "MOVDQUrr",
790 "MOVPQI2QIrr",
791 "PANDNrr",
792 "PANDrr",
793 "PORrr",
794 "PXORrr",
795 "VBLENDPDYrri",
796 "VBLENDPDrri",
797 "VBLENDPSYrri",
798 "VBLENDPSrri",
799 "VMOVDQAYrr",
800 "VMOVDQArr",
801 "VMOVDQUYrr",
802 "VMOVDQUrr",
803 "VMOVPQI2QIrr",
804 "VMOVZPQILo2PQIrr",
805 "VPANDNYrr",
806 "VPANDNrr",
807 "VPANDYrr",
808 "VPANDrr",
809 "VPBLENDDYrri",
810 "VPBLENDDrri",
811 "VPORYrr",
812 "VPORrr",
813 "VPXORYrr",
814 "VPXORrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]815
816def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
817 let Latency = 1;
818 let NumMicroOps = 1;
819 let ResourceCycles = [1];
820}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]821def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]822def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
823 "ADD(8|16|32|64)rr",
824 "ADD(8|16|32|64)i",
825 "AND(8|16|32|64)ri",
826 "AND(8|16|32|64)rr",
827 "AND(8|16|32|64)i",
828 "CBW",
829 "CLC",
830 "CMC",
831 "CMP(8|16|32|64)ri",
832 "CMP(8|16|32|64)rr",
833 "CMP(8|16|32|64)i",
834 "DEC(8|16|32|64)r",
835 "INC(8|16|32|64)r",
836 "LAHF",
837 "MOV(8|16|32|64)rr",
838 "MOV(8|16|32|64)ri",
839 "MOVSX(16|32|64)rr16",
840 "MOVSX(16|32|64)rr32",
841 "MOVSX(16|32|64)rr8",
842 "MOVZX(16|32|64)rr16",
843 "MOVZX(16|32|64)rr8",
844 "NEG(8|16|32|64)r",
845 "NOOP",
846 "NOT(8|16|32|64)r",
847 "OR(8|16|32|64)ri",
848 "OR(8|16|32|64)rr",
849 "OR(8|16|32|64)i",
850 "SAHF",
851 "SGDT64m",
852 "SIDT64m",
853 "SLDT64m",
854 "SMSW16m",
855 "STC",
856 "STRm",
857 "SUB(8|16|32|64)ri",
858 "SUB(8|16|32|64)rr",
859 "SUB(8|16|32|64)i",
860 "SYSCALL",
861 "TEST(8|16|32|64)rr",
862 "TEST(8|16|32|64)i",
863 "TEST(8|16|32|64)ri",
864 "XCHG(16|32|64)rr",
865 "XOR(8|16|32|64)ri",
866 "XOR(8|16|32|64)rr",
867 "XOR(8|16|32|64)i")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]868
869def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
870 let Latency = 1;
871 let NumMicroOps = 2;
872 let ResourceCycles = [1,1];
873}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]874def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
875 "MMX_MOVD64from64rm",
876 "MMX_MOVD64mr",
877 "MMX_MOVNTQmr",
878 "MMX_MOVQ64mr",
879 "MOV(16|32|64)mr",
880 "MOV8mi",
881 "MOV8mr",
882 "MOVAPDmr",
883 "MOVAPSmr",
884 "MOVDQAmr",
885 "MOVDQUmr",
886 "MOVHPDmr",
887 "MOVHPSmr",
888 "MOVLPDmr",
889 "MOVLPSmr",
890 "MOVNTDQmr",
891 "MOVNTI_64mr",
892 "MOVNTImr",
893 "MOVNTPDmr",
894 "MOVNTPSmr",
895 "MOVPDI2DImr",
896 "MOVPQI2QImr",
897 "MOVPQIto64mr",
898 "MOVSDmr",
899 "MOVSSmr",
900 "MOVUPDmr",
901 "MOVUPSmr",
902 "ST_FP32m",
903 "ST_FP64m",
904 "ST_FP80m",
905 "VEXTRACTF128mr",
906 "VEXTRACTI128mr",
907 "VMOVAPDYmr",
908 "VMOVAPDmr",
909 "VMOVAPSYmr",
910 "VMOVAPSmr",
911 "VMOVDQAYmr",
912 "VMOVDQAmr",
913 "VMOVDQUYmr",
914 "VMOVDQUmr",
915 "VMOVHPDmr",
916 "VMOVHPSmr",
917 "VMOVLPDmr",
918 "VMOVLPSmr",
919 "VMOVNTDQYmr",
920 "VMOVNTDQmr",
921 "VMOVNTPDYmr",
922 "VMOVNTPDmr",
923 "VMOVNTPSYmr",
924 "VMOVNTPSmr",
925 "VMOVPDI2DImr",
926 "VMOVPQI2QImr",
927 "VMOVPQIto64mr",
928 "VMOVSDmr",
929 "VMOVSSmr",
930 "VMOVUPDYmr",
931 "VMOVUPDmr",
932 "VMOVUPSYmr",
933 "VMOVUPSmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]934
935def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {
936 let Latency = 2;
937 let NumMicroOps = 2;
938 let ResourceCycles = [2];
939}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]940def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0",
941 "BLENDVPSrr0",
942 "MMX_PINSRWrr",
943 "PBLENDVBrr0",
944 "PINSRBrr",
945 "PINSRDrr",
946 "PINSRQrr",
947 "PINSRWrr",
948 "VBLENDVPDYrr",
949 "VBLENDVPDrr",
950 "VBLENDVPSYrr",
951 "VBLENDVPSrr",
952 "VPBLENDVBYrr",
953 "VPBLENDVBrr",
954 "VPINSRBrr",
955 "VPINSRDrr",
956 "VPINSRQrr",
957 "VPINSRWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]958
959def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
960 let Latency = 2;
961 let NumMicroOps = 2;
962 let ResourceCycles = [2];
963}
964def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;
965
966def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
967 let Latency = 2;
968 let NumMicroOps = 2;
969 let ResourceCycles = [2];
970}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]971def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
972 "ROL(8|16|32|64)ri",
973 "ROR(8|16|32|64)r1",
974 "ROR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]975
976def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
977 let Latency = 2;
978 let NumMicroOps = 2;
979 let ResourceCycles = [2];
980}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]981def: InstRW<[BWWriteResGroup14], (instregex "LFENCE",
982 "MFENCE",
983 "WAIT",
984 "XGETBV")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]985
986def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
987 let Latency = 2;
988 let NumMicroOps = 2;
989 let ResourceCycles = [1,1];
990}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]991def: InstRW<[BWWriteResGroup15], (instregex "CVTPS2PDrr",
992 "CVTSS2SDrr",
993 "EXTRACTPSrr",
994 "MMX_PEXTRWrr",
995 "PEXTRBrr",
996 "PEXTRDrr",
997 "PEXTRQrr",
998 "PEXTRWrr",
999 "PSLLDrr",
1000 "PSLLQrr",
1001 "PSLLWrr",
1002 "PSRADrr",
1003 "PSRAWrr",
1004 "PSRLDrr",
1005 "PSRLQrr",
1006 "PSRLWrr",
1007 "PTESTrr",
1008 "VCVTPH2PSYrr",
1009 "VCVTPH2PSrr",
1010 "VCVTPS2PDrr",
1011 "VCVTSS2SDrr",
1012 "VEXTRACTPSrr",
1013 "VPEXTRBrr",
1014 "VPEXTRDrr",
1015 "VPEXTRQrr",
1016 "VPEXTRWrr",
1017 "VPSLLDrr",
1018 "VPSLLQrr",
1019 "VPSLLWrr",
1020 "VPSRADrr",
1021 "VPSRAWrr",
1022 "VPSRLDrr",
1023 "VPSRLQrr",
1024 "VPSRLWrr",
1025 "VPTESTrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1026
1027def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
1028 let Latency = 2;
1029 let NumMicroOps = 2;
1030 let ResourceCycles = [1,1];
1031}
1032def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
1033
1034def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
1035 let Latency = 2;
1036 let NumMicroOps = 2;
1037 let ResourceCycles = [1,1];
1038}
1039def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
1040
1041def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
1042 let Latency = 2;
1043 let NumMicroOps = 2;
1044 let ResourceCycles = [1,1];
1045}
1046def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;
1047
1048def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
1049 let Latency = 2;
1050 let NumMicroOps = 2;
1051 let ResourceCycles = [1,1];
1052}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1053def: InstRW<[BWWriteResGroup19], (instregex "BEXTR(32|64)rr",
1054 "BSWAP(16|32|64)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1055
1056def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
1057 let Latency = 2;
1058 let NumMicroOps = 2;
1059 let ResourceCycles = [1,1];
1060}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1061def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]1062def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1063def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
1064 "ADC8ri",
1065 "CMOV(A|BE)(16|32|64)rr",
1066 "SBB8i8",
1067 "SBB8ri",
1068 "SET(A|BE)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1069
1070def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {
1071 let Latency = 2;
1072 let NumMicroOps = 3;
1073 let ResourceCycles = [1,1,1];
1074}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1075def: InstRW<[BWWriteResGroup21], (instregex "EXTRACTPSmr",
1076 "PEXTRBmr",
1077 "PEXTRDmr",
1078 "PEXTRQmr",
1079 "PEXTRWmr",
1080 "STMXCSR",
1081 "VEXTRACTPSmr",
1082 "VPEXTRBmr",
1083 "VPEXTRDmr",
1084 "VPEXTRQmr",
1085 "VPEXTRWmr",
1086 "VSTMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1087
1088def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
1089 let Latency = 2;
1090 let NumMicroOps = 3;
1091 let ResourceCycles = [1,1,1];
1092}
1093def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
1094
1095def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
1096 let Latency = 2;
1097 let NumMicroOps = 3;
1098 let ResourceCycles = [1,1,1];
1099}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1100def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1101
1102def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
1103 let Latency = 2;
1104 let NumMicroOps = 3;
1105 let ResourceCycles = [1,1,1];
1106}
1107def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
1108
1109def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1110 let Latency = 2;
1111 let NumMicroOps = 3;
1112 let ResourceCycles = [1,1,1];
1113}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1114def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1115def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
1116 "PUSH64i8",
1117 "STOSB",
1118 "STOSL",
1119 "STOSQ",
1120 "STOSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1121
1122def BWWriteResGroup26 : SchedWriteRes<[BWPort0]> {
1123 let Latency = 3;
1124 let NumMicroOps = 1;
1125 let ResourceCycles = [1];
1126}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1127def: InstRW<[BWWriteResGroup26], (instregex "MOVMSKPDrr",
1128 "MOVMSKPSrr",
1129 "PMOVMSKBrr",
1130 "VMOVMSKPDYrr",
1131 "VMOVMSKPDrr",
1132 "VMOVMSKPSYrr",
1133 "VMOVMSKPSrr",
1134 "VPMOVMSKBYrr",
1135 "VPMOVMSKBrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1136
1137def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
1138 let Latency = 3;
1139 let NumMicroOps = 1;
1140 let ResourceCycles = [1];
1141}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1142def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1143def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
1144def: InstRW<[BWWriteResGroup27], (instregex "ADDPDrr",
1145 "ADDPSrr",
1146 "ADDSDrr",
1147 "ADDSSrr",
1148 "ADDSUBPDrr",
1149 "ADDSUBPSrr",
1150 "ADD_FPrST0",
1151 "ADD_FST0r",
1152 "ADD_FrST0",
1153 "BSF(16|32|64)rr",
1154 "BSR(16|32|64)rr",
1155 "CMPPDrri",
1156 "CMPPSrri",
1157 "CMPSDrr",
1158 "CMPSSrr",
1159 "COMISDrr",
1160 "COMISSrr",
1161 "CVTDQ2PSrr",
1162 "CVTPS2DQrr",
1163 "CVTTPS2DQrr",
1164 "LZCNT(16|32|64)rr",
1165 "MAX(C?)PDrr",
1166 "MAX(C?)PSrr",
1167 "MAX(C?)SDrr",
1168 "MAX(C?)SSrr",
1169 "MIN(C?)PDrr",
1170 "MIN(C?)PSrr",
1171 "MIN(C?)SDrr",
1172 "MIN(C?)SSrr",
1173 "MMX_CVTPI2PSirr",
1174 "PDEP(32|64)rr",
1175 "PEXT(32|64)rr",
1176 "POPCNT(16|32|64)rr",
1177 "SHLD(16|32|64)rri8",
1178 "SHRD(16|32|64)rri8",
1179 "SUBPDrr",
1180 "SUBPSrr",
1181 "SUBR_FPrST0",
1182 "SUBR_FST0r",
1183 "SUBR_FrST0",
1184 "SUBSDrr",
1185 "SUBSSrr",
1186 "SUB_FPrST0",
1187 "SUB_FST0r",
1188 "SUB_FrST0",
1189 "TZCNT(16|32|64)rr",
1190 "UCOMISDrr",
1191 "UCOMISSrr",
1192 "VADDPDYrr",
1193 "VADDPDrr",
1194 "VADDPSYrr",
1195 "VADDPSrr",
1196 "VADDSDrr",
1197 "VADDSSrr",
1198 "VADDSUBPDYrr",
1199 "VADDSUBPDrr",
1200 "VADDSUBPSYrr",
1201 "VADDSUBPSrr",
1202 "VCMPPDYrri",
1203 "VCMPPDrri",
1204 "VCMPPSYrri",
1205 "VCMPPSrri",
1206 "VCMPSDrr",
1207 "VCMPSSrr",
1208 "VCOMISDrr",
1209 "VCOMISSrr",
1210 "VCVTDQ2PSYrr",
1211 "VCVTDQ2PSrr",
1212 "VCVTPS2DQYrr",
1213 "VCVTPS2DQrr",
1214 "VCVTTPS2DQYrr",
1215 "VCVTTPS2DQrr",
1216 "VMAX(C?)PDYrr",
1217 "VMAX(C?)PDrr",
1218 "VMAX(C?)PSYrr",
1219 "VMAX(C?)PSrr",
1220 "VMAX(C?)SDrr",
1221 "VMAX(C?)SSrr",
1222 "VMIN(C?)PDYrr",
1223 "VMIN(C?)PDrr",
1224 "VMIN(C?)PSYrr",
1225 "VMIN(C?)PSrr",
1226 "VMIN(C?)SDrr",
1227 "VMIN(C?)SSrr",
1228 "VSUBPDYrr",
1229 "VSUBPDrr",
1230 "VSUBPSYrr",
1231 "VSUBPSrr",
1232 "VSUBSDrr",
1233 "VSUBSSrr",
1234 "VUCOMISDrr",
1235 "VUCOMISSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1236
1237def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
1238 let Latency = 3;
1239 let NumMicroOps = 2;
1240 let ResourceCycles = [1,1];
1241}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]1242def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1243
1244def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
1245 let Latency = 3;
1246 let NumMicroOps = 1;
1247 let ResourceCycles = [1];
1248}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1249def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr",
1250 "VBROADCASTSSYrr",
1251 "VEXTRACTF128rr",
1252 "VEXTRACTI128rr",
1253 "VINSERTF128rr",
1254 "VINSERTI128rr",
1255 "VPBROADCASTBYrr",
1256 "VPBROADCASTBrr",
1257 "VPBROADCASTDYrr",
1258 "VPBROADCASTQYrr",
1259 "VPBROADCASTWYrr",
1260 "VPBROADCASTWrr",
1261 "VPERM2F128rr",
1262 "VPERM2I128rr",
1263 "VPERMDYrr",
1264 "VPERMPDYri",
1265 "VPERMPSYrr",
1266 "VPERMQYri",
1267 "VPMOVSXBDYrr",
1268 "VPMOVSXBQYrr",
1269 "VPMOVSXBWYrr",
1270 "VPMOVSXDQYrr",
1271 "VPMOVSXWDYrr",
1272 "VPMOVSXWQYrr",
1273 "VPMOVZXBDYrr",
1274 "VPMOVZXBQYrr",
1275 "VPMOVZXBWYrr",
1276 "VPMOVZXDQYrr",
1277 "VPMOVZXWDYrr",
1278 "VPMOVZXWQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1279
1280def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
1281 let Latency = 3;
1282 let NumMicroOps = 1;
1283 let ResourceCycles = [1];
1284}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1285def: InstRW<[BWWriteResGroup29], (instregex "MULPDrr",
1286 "MULPSrr",
1287 "MULSDrr",
1288 "MULSSrr",
1289 "VMULPDYrr",
1290 "VMULPDrr",
1291 "VMULPSYrr",
1292 "VMULPSrr",
1293 "VMULSDrr",
1294 "VMULSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1295
1296def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
1297 let Latency = 3;
1298 let NumMicroOps = 3;
1299 let ResourceCycles = [3];
1300}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1301def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr",
1302 "XCHG8rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1303
1304def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
1305 let Latency = 3;
1306 let NumMicroOps = 3;
1307 let ResourceCycles = [2,1];
1308}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1309def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVDYrr",
1310 "VPSLLVDrr",
1311 "VPSRAVDYrr",
1312 "VPSRAVDrr",
1313 "VPSRLVDYrr",
1314 "VPSRLVDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1315
1316def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
1317 let Latency = 3;
1318 let NumMicroOps = 3;
1319 let ResourceCycles = [2,1];
1320}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1321def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr",
1322 "MMX_PHADDSWrr",
1323 "MMX_PHADDWrr",
1324 "MMX_PHSUBDrr",
1325 "MMX_PHSUBSWrr",
1326 "MMX_PHSUBWrr",
1327 "PHADDDrr",
1328 "PHADDSWrr",
1329 "PHADDWrr",
1330 "PHSUBDrr",
1331 "PHSUBSWrr",
1332 "PHSUBWrr",
1333 "VPHADDDYrr",
1334 "VPHADDDrr",
1335 "VPHADDSWYrr",
1336 "VPHADDSWrr",
1337 "VPHADDWYrr",
1338 "VPHADDWrr",
1339 "VPHSUBDYrr",
1340 "VPHSUBDrr",
1341 "VPHSUBSWYrr",
1342 "VPHSUBSWrr",
1343 "VPHSUBWYrr",
1344 "VPHSUBWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1345
1346def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
1347 let Latency = 3;
1348 let NumMicroOps = 3;
1349 let ResourceCycles = [2,1];
1350}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1351def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
1352 "MMX_PACKSSWBirr",
1353 "MMX_PACKUSWBirr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1354
1355def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
1356 let Latency = 3;
1357 let NumMicroOps = 3;
1358 let ResourceCycles = [1,2];
1359}
1360def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
1361
1362def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
1363 let Latency = 3;
1364 let NumMicroOps = 3;
1365 let ResourceCycles = [1,2];
1366}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1367def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
1368 "RCL(8|16|32|64)ri",
1369 "RCR(8|16|32|64)r1",
1370 "RCR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1371
1372def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
1373 let Latency = 3;
1374 let NumMicroOps = 3;
1375 let ResourceCycles = [2,1];
1376}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1377def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
1378 "ROR(8|16|32|64)rCL",
1379 "SAR(8|16|32|64)rCL",
1380 "SHL(8|16|32|64)rCL",
1381 "SHR(8|16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1382
1383def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
1384 let Latency = 3;
1385 let NumMicroOps = 4;
1386 let ResourceCycles = [1,1,1,1];
1387}
1388def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
1389
1390def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1391 let Latency = 3;
1392 let NumMicroOps = 4;
1393 let ResourceCycles = [1,1,1,1];
1394}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1395def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32",
1396 "SET(A|BE)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1397
1398def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
1399 let Latency = 4;
1400 let NumMicroOps = 2;
1401 let ResourceCycles = [1,1];
1402}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1403def: InstRW<[BWWriteResGroup39], (instregex "CVTSD2SI64rr",
1404 "CVTSD2SIrr",
1405 "CVTSS2SI64rr",
1406 "CVTSS2SIrr",
1407 "CVTTSD2SI64rr",
1408 "CVTTSD2SIrr",
1409 "CVTTSS2SI64rr",
1410 "CVTTSS2SIrr",
1411 "VCVTSD2SI64rr",
1412 "VCVTSD2SIrr",
1413 "VCVTSS2SI64rr",
1414 "VCVTSS2SIrr",
1415 "VCVTTSD2SI64rr",
1416 "VCVTTSD2SIrr",
1417 "VCVTTSS2SI64rr",
1418 "VCVTTSS2SIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1419
1420def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
1421 let Latency = 4;
1422 let NumMicroOps = 2;
1423 let ResourceCycles = [1,1];
1424}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1425def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
1426 "VPSLLDYrr",
1427 "VPSLLQYrr",
1428 "VPSLLWYrr",
1429 "VPSRADYrr",
1430 "VPSRAWYrr",
1431 "VPSRLDYrr",
1432 "VPSRLQYrr",
1433 "VPSRLWYrr",
1434 "VPTESTYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1435
1436def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
1437 let Latency = 4;
1438 let NumMicroOps = 2;
1439 let ResourceCycles = [1,1];
1440}
1441def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;
1442
1443def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
1444 let Latency = 4;
1445 let NumMicroOps = 2;
1446 let ResourceCycles = [1,1];
1447}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame^]1448def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1449def: InstRW<[BWWriteResGroup42], (instregex "CVTDQ2PDrr",
1450 "CVTPD2DQrr",
1451 "CVTPD2PSrr",
1452 "CVTSD2SSrr",
1453 "CVTSI642SDrr",
1454 "CVTSI2SDrr",
1455 "CVTSI2SSrr",
1456 "CVTTPD2DQrr",
1457 "MMX_CVTPD2PIirr",
1458 "MMX_CVTPI2PDirr",
1459 "MMX_CVTPS2PIirr",
1460 "MMX_CVTTPD2PIirr",
1461 "MMX_CVTTPS2PIirr",
1462 "VCVTDQ2PDrr",
1463 "VCVTPD2DQrr",
1464 "VCVTPD2PSrr",
1465 "VCVTPS2PHrr",
1466 "VCVTSD2SSrr",
1467 "VCVTSI642SDrr",
1468 "VCVTSI2SDrr",
1469 "VCVTSI2SSrr",
1470 "VCVTTPD2DQrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1471
1472def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1473 let Latency = 4;
1474 let NumMicroOps = 4;
1475}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1476def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1477
1478def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
1479 let Latency = 4;
1480 let NumMicroOps = 3;
1481 let ResourceCycles = [1,1,1];
1482}
1483def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;
1484
1485def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
1486 let Latency = 4;
1487 let NumMicroOps = 3;
1488 let ResourceCycles = [1,1,1];
1489}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1490def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
1491 "ISTT_FP32m",
1492 "ISTT_FP64m",
1493 "IST_F16m",
1494 "IST_F32m",
1495 "IST_FP16m",
1496 "IST_FP32m",
1497 "IST_FP64m",
1498 "VCVTPS2PHYmr",
1499 "VCVTPS2PHmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1500
1501def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
1502 let Latency = 4;
1503 let NumMicroOps = 4;
1504 let ResourceCycles = [4];
1505}
1506def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;
1507
1508def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
1509 let Latency = 4;
1510 let NumMicroOps = 4;
1511 let ResourceCycles = [1,3];
1512}
1513def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;
1514
1515def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
1516 let Latency = 5;
1517 let NumMicroOps = 1;
1518 let ResourceCycles = [1];
1519}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1520def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
1521 "MMX_PMADDWDirr",
1522 "MMX_PMULHRSWrr",
1523 "MMX_PMULHUWirr",
1524 "MMX_PMULHWirr",
1525 "MMX_PMULLWirr",
1526 "MMX_PMULUDQirr",
1527 "MMX_PSADBWirr",
1528 "MUL_FPrST0",
1529 "MUL_FST0r",
1530 "MUL_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1531 "PCMPGTQrr",
1532 "PHMINPOSUWrr",
1533 "PMADDUBSWrr",
1534 "PMADDWDrr",
1535 "PMULDQrr",
1536 "PMULHRSWrr",
1537 "PMULHUWrr",
1538 "PMULHWrr",
1539 "PMULLWrr",
1540 "PMULUDQrr",
1541 "PSADBWrr",
1542 "RCPPSr",
1543 "RCPSSr",
1544 "RSQRTPSr",
1545 "RSQRTSSr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1546 "VPCMPGTQYrr",
1547 "VPCMPGTQrr",
1548 "VPHMINPOSUWrr",
1549 "VPMADDUBSWYrr",
1550 "VPMADDUBSWrr",
1551 "VPMADDWDYrr",
1552 "VPMADDWDrr",
1553 "VPMULDQYrr",
1554 "VPMULDQrr",
1555 "VPMULHRSWYrr",
1556 "VPMULHRSWrr",
1557 "VPMULHUWYrr",
1558 "VPMULHUWrr",
1559 "VPMULHWYrr",
1560 "VPMULHWrr",
1561 "VPMULLWYrr",
1562 "VPMULLWrr",
1563 "VPMULUDQYrr",
1564 "VPMULUDQrr",
1565 "VPSADBWYrr",
1566 "VPSADBWrr",
1567 "VRCPPSr",
1568 "VRCPSSr",
1569 "VRSQRTPSr",
1570 "VRSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1571
1572def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> {
1573 let Latency = 5;
1574 let NumMicroOps = 1;
1575 let ResourceCycles = [1];
1576}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1577def: InstRW<[BWWriteResGroup48],
1578 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1579 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1580
1581def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
1582 let Latency = 5;
1583 let NumMicroOps = 1;
1584 let ResourceCycles = [1];
1585}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1586def: InstRW<[BWWriteResGroup49], (instregex "LDDQUrm",
1587 "MMX_MOVD64rm",
1588 "MMX_MOVD64to64rm",
1589 "MMX_MOVQ64rm",
1590 "MOV(16|32|64)rm",
1591 "MOV64toPQIrm",
1592 "MOV8rm",
1593 "MOVAPDrm",
1594 "MOVAPSrm",
1595 "MOVDDUPrm",
1596 "MOVDI2PDIrm",
1597 "MOVDQArm",
1598 "MOVDQUrm",
1599 "MOVNTDQArm",
1600 "MOVQI2PQIrm",
1601 "MOVSDrm",
1602 "MOVSHDUPrm",
1603 "MOVSLDUPrm",
1604 "MOVSSrm",
1605 "MOVSX(16|32|64)rm16",
1606 "MOVSX(16|32|64)rm32",
1607 "MOVSX(16|32|64)rm8",
1608 "MOVUPDrm",
1609 "MOVUPSrm",
1610 "MOVZX(16|32|64)rm16",
1611 "MOVZX(16|32|64)rm8",
1612 "PREFETCHNTA",
1613 "PREFETCHT0",
1614 "PREFETCHT1",
1615 "PREFETCHT2",
1616 "VBROADCASTSSrm",
1617 "VLDDQUrm",
1618 "VMOV64toPQIrm",
1619 "VMOVAPDrm",
1620 "VMOVAPSrm",
1621 "VMOVDDUPrm",
1622 "VMOVDI2PDIrm",
1623 "VMOVDQArm",
1624 "VMOVDQUrm",
1625 "VMOVNTDQArm",
1626 "VMOVQI2PQIrm",
1627 "VMOVSDrm",
1628 "VMOVSHDUPrm",
1629 "VMOVSLDUPrm",
1630 "VMOVSSrm",
1631 "VMOVUPDrm",
1632 "VMOVUPSrm",
1633 "VPBROADCASTDrm",
1634 "VPBROADCASTQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1635
1636def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
1637 let Latency = 5;
1638 let NumMicroOps = 3;
1639 let ResourceCycles = [1,2];
1640}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1641def: InstRW<[BWWriteResGroup50], (instregex "CVTSI642SSrr",
1642 "HADDPDrr",
1643 "HADDPSrr",
1644 "HSUBPDrr",
1645 "HSUBPSrr",
1646 "VCVTSI642SSrr",
1647 "VHADDPDYrr",
1648 "VHADDPDrr",
1649 "VHADDPSYrr",
1650 "VHADDPSrr",
1651 "VHSUBPDYrr",
1652 "VHSUBPDrr",
1653 "VHSUBPSYrr",
1654 "VHSUBPSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1655
1656def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
1657 let Latency = 5;
1658 let NumMicroOps = 3;
1659 let ResourceCycles = [1,1,1];
1660}
1661def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
1662
1663def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame^]1664 let Latency = 4;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1665 let NumMicroOps = 3;
1666 let ResourceCycles = [1,1,1];
1667}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame^]1668def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1669
1670def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {
1671 let Latency = 5;
1672 let NumMicroOps = 4;
1673 let ResourceCycles = [1,1,1,1];
1674}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1675def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPDYmr",
1676 "VMASKMOVPDmr",
1677 "VMASKMOVPSYmr",
1678 "VMASKMOVPSmr",
1679 "VPMASKMOVDYmr",
1680 "VPMASKMOVDmr",
1681 "VPMASKMOVQYmr",
1682 "VPMASKMOVQmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1683
1684def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
1685 let Latency = 5;
1686 let NumMicroOps = 5;
1687 let ResourceCycles = [1,4];
1688}
1689def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
1690
1691def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
1692 let Latency = 5;
1693 let NumMicroOps = 5;
1694 let ResourceCycles = [1,4];
1695}
1696def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;
1697
1698def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
1699 let Latency = 5;
1700 let NumMicroOps = 5;
1701 let ResourceCycles = [2,3];
1702}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1703def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1704
1705def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1706 let Latency = 5;
1707 let NumMicroOps = 6;
1708 let ResourceCycles = [1,1,4];
1709}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1710def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16", "PUSHF64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1711
1712def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
1713 let Latency = 6;
1714 let NumMicroOps = 1;
1715 let ResourceCycles = [1];
1716}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1717def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
1718 "LD_F64m",
1719 "LD_F80m",
1720 "VBROADCASTF128",
1721 "VBROADCASTI128",
1722 "VBROADCASTSDYrm",
1723 "VBROADCASTSSYrm",
1724 "VLDDQUYrm",
1725 "VMOVAPDYrm",
1726 "VMOVAPSYrm",
1727 "VMOVDDUPYrm",
1728 "VMOVDQAYrm",
1729 "VMOVDQUYrm",
1730 "VMOVNTDQAYrm",
1731 "VMOVSHDUPYrm",
1732 "VMOVSLDUPYrm",
1733 "VMOVUPDYrm",
1734 "VMOVUPSYrm",
1735 "VPBROADCASTDYrm",
1736 "VPBROADCASTQYrm",
1737 "ROUNDPDr",
1738 "ROUNDPSr",
1739 "ROUNDSDr",
1740 "ROUNDSSr",
1741 "VROUNDPDr",
1742 "VROUNDPSr",
1743 "VROUNDSDr",
1744 "VROUNDSSr",
1745 "VROUNDYPDr",
1746 "VROUNDYPSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1747
1748def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
1749 let Latency = 6;
1750 let NumMicroOps = 2;
1751 let ResourceCycles = [1,1];
1752}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1753def: InstRW<[BWWriteResGroup59], (instregex "CVTPS2PDrm",
1754 "CVTSS2SDrm",
1755 "MMX_PSLLDrm",
1756 "MMX_PSLLQrm",
1757 "MMX_PSLLWrm",
1758 "MMX_PSRADrm",
1759 "MMX_PSRAWrm",
1760 "MMX_PSRLDrm",
1761 "MMX_PSRLQrm",
1762 "MMX_PSRLWrm",
1763 "VCVTPH2PSYrm",
1764 "VCVTPH2PSrm",
1765 "VCVTPS2PDrm",
1766 "VCVTSS2SDrm",
1767 "VPSLLVQrm",
1768 "VPSRLVQrm",
1769 "VTESTPDrm",
1770 "VTESTPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1771
1772def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
1773 let Latency = 6;
1774 let NumMicroOps = 2;
1775 let ResourceCycles = [1,1];
1776}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1777def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
1778 "VCVTPD2DQYrr",
1779 "VCVTPD2PSYrr",
1780 "VCVTPS2PHYrr",
1781 "VCVTTPD2DQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1782
1783def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
1784 let Latency = 6;
1785 let NumMicroOps = 2;
1786 let ResourceCycles = [1,1];
1787}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1788def: InstRW<[BWWriteResGroup61], (instregex "ANDNPDrm",
1789 "ANDNPSrm",
1790 "ANDPDrm",
1791 "ANDPSrm",
1792 "INSERTPSrm",
1793 "MMX_PALIGNRrmi",
1794 "MMX_PINSRWrm",
1795 "MMX_PSHUFBrm",
1796 "MMX_PSHUFWmi",
1797 "MMX_PUNPCKHBWirm",
1798 "MMX_PUNPCKHDQirm",
1799 "MMX_PUNPCKHWDirm",
1800 "MMX_PUNPCKLBWirm",
1801 "MMX_PUNPCKLDQirm",
1802 "MMX_PUNPCKLWDirm",
1803 "MOVHPDrm",
1804 "MOVHPSrm",
1805 "MOVLPDrm",
1806 "MOVLPSrm",
1807 "ORPDrm",
1808 "ORPSrm",
1809 "PACKSSDWrm",
1810 "PACKSSWBrm",
1811 "PACKUSDWrm",
1812 "PACKUSWBrm",
1813 "PALIGNRrmi",
1814 "PBLENDWrmi",
1815 "PINSRBrm",
1816 "PINSRDrm",
1817 "PINSRQrm",
1818 "PINSRWrm",
1819 "PMOVSXBDrm",
1820 "PMOVSXBQrm",
1821 "PMOVSXBWrm",
1822 "PMOVSXDQrm",
1823 "PMOVSXWDrm",
1824 "PMOVSXWQrm",
1825 "PMOVZXBDrm",
1826 "PMOVZXBQrm",
1827 "PMOVZXBWrm",
1828 "PMOVZXDQrm",
1829 "PMOVZXWDrm",
1830 "PMOVZXWQrm",
1831 "PSHUFBrm",
1832 "PSHUFDmi",
1833 "PSHUFHWmi",
1834 "PSHUFLWmi",
1835 "PUNPCKHBWrm",
1836 "PUNPCKHDQrm",
1837 "PUNPCKHQDQrm",
1838 "PUNPCKHWDrm",
1839 "PUNPCKLBWrm",
1840 "PUNPCKLDQrm",
1841 "PUNPCKLQDQrm",
1842 "PUNPCKLWDrm",
1843 "SHUFPDrmi",
1844 "SHUFPSrmi",
1845 "UNPCKHPDrm",
1846 "UNPCKHPSrm",
1847 "UNPCKLPDrm",
1848 "UNPCKLPSrm",
1849 "VANDNPDrm",
1850 "VANDNPSrm",
1851 "VANDPDrm",
1852 "VANDPSrm",
1853 "VINSERTPSrm",
1854 "VMOVHPDrm",
1855 "VMOVHPSrm",
1856 "VMOVLPDrm",
1857 "VMOVLPSrm",
1858 "VORPDrm",
1859 "VORPSrm",
1860 "VPACKSSDWrm",
1861 "VPACKSSWBrm",
1862 "VPACKUSDWrm",
1863 "VPACKUSWBrm",
1864 "VPALIGNRrmi",
1865 "VPBLENDWrmi",
1866 "VPERMILPDmi",
1867 "VPERMILPDrm",
1868 "VPERMILPSmi",
1869 "VPERMILPSrm",
1870 "VPINSRBrm",
1871 "VPINSRDrm",
1872 "VPINSRQrm",
1873 "VPINSRWrm",
1874 "VPMOVSXBDrm",
1875 "VPMOVSXBQrm",
1876 "VPMOVSXBWrm",
1877 "VPMOVSXDQrm",
1878 "VPMOVSXWDrm",
1879 "VPMOVSXWQrm",
1880 "VPMOVZXBDrm",
1881 "VPMOVZXBQrm",
1882 "VPMOVZXBWrm",
1883 "VPMOVZXDQrm",
1884 "VPMOVZXWDrm",
1885 "VPMOVZXWQrm",
1886 "VPSHUFBrm",
1887 "VPSHUFDmi",
1888 "VPSHUFHWmi",
1889 "VPSHUFLWmi",
1890 "VPUNPCKHBWrm",
1891 "VPUNPCKHDQrm",
1892 "VPUNPCKHQDQrm",
1893 "VPUNPCKHWDrm",
1894 "VPUNPCKLBWrm",
1895 "VPUNPCKLDQrm",
1896 "VPUNPCKLQDQrm",
1897 "VPUNPCKLWDrm",
1898 "VSHUFPDrmi",
1899 "VSHUFPSrmi",
1900 "VUNPCKHPDrm",
1901 "VUNPCKHPSrm",
1902 "VUNPCKLPDrm",
1903 "VUNPCKLPSrm",
1904 "VXORPDrm",
1905 "VXORPSrm",
1906 "XORPDrm",
1907 "XORPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1908
1909def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1910 let Latency = 6;
1911 let NumMicroOps = 2;
1912 let ResourceCycles = [1,1];
1913}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1914def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1915 "JMP(16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1916
1917def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1918 let Latency = 6;
1919 let NumMicroOps = 2;
1920 let ResourceCycles = [1,1];
1921}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1922def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm",
1923 "ADCX(32|64)rm",
1924 "ADOX(32|64)rm",
1925 "BT(16|32|64)mi8",
1926 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1927 "RORX(32|64)mi",
1928 "SARX(32|64)rm",
1929 "SBB(8|16|32|64)rm",
1930 "SHLX(32|64)rm",
1931 "SHRX(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1932
1933def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1934 let Latency = 6;
1935 let NumMicroOps = 2;
1936 let ResourceCycles = [1,1];
1937}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1938def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1939 "BLSI(32|64)rm",
1940 "BLSMSK(32|64)rm",
1941 "BLSR(32|64)rm",
1942 "BZHI(32|64)rm",
1943 "MMX_PABSBrm",
1944 "MMX_PABSDrm",
1945 "MMX_PABSWrm",
1946 "MMX_PADDBirm",
1947 "MMX_PADDDirm",
1948 "MMX_PADDQirm",
1949 "MMX_PADDSBirm",
1950 "MMX_PADDSWirm",
1951 "MMX_PADDUSBirm",
1952 "MMX_PADDUSWirm",
1953 "MMX_PADDWirm",
1954 "MMX_PAVGBirm",
1955 "MMX_PAVGWirm",
1956 "MMX_PCMPEQBirm",
1957 "MMX_PCMPEQDirm",
1958 "MMX_PCMPEQWirm",
1959 "MMX_PCMPGTBirm",
1960 "MMX_PCMPGTDirm",
1961 "MMX_PCMPGTWirm",
1962 "MMX_PMAXSWirm",
1963 "MMX_PMAXUBirm",
1964 "MMX_PMINSWirm",
1965 "MMX_PMINUBirm",
1966 "MMX_PSIGNBrm",
1967 "MMX_PSIGNDrm",
1968 "MMX_PSIGNWrm",
1969 "MMX_PSUBBirm",
1970 "MMX_PSUBDirm",
1971 "MMX_PSUBQirm",
1972 "MMX_PSUBSBirm",
1973 "MMX_PSUBSWirm",
1974 "MMX_PSUBUSBirm",
1975 "MMX_PSUBUSWirm",
1976 "MMX_PSUBWirm",
1977 "MOVBE(16|32|64)rm",
1978 "PABSBrm",
1979 "PABSDrm",
1980 "PABSWrm",
1981 "PADDBrm",
1982 "PADDDrm",
1983 "PADDQrm",
1984 "PADDSBrm",
1985 "PADDSWrm",
1986 "PADDUSBrm",
1987 "PADDUSWrm",
1988 "PADDWrm",
1989 "PAVGBrm",
1990 "PAVGWrm",
1991 "PCMPEQBrm",
1992 "PCMPEQDrm",
1993 "PCMPEQQrm",
1994 "PCMPEQWrm",
1995 "PCMPGTBrm",
1996 "PCMPGTDrm",
1997 "PCMPGTWrm",
1998 "PMAXSBrm",
1999 "PMAXSDrm",
2000 "PMAXSWrm",
2001 "PMAXUBrm",
2002 "PMAXUDrm",
2003 "PMAXUWrm",
2004 "PMINSBrm",
2005 "PMINSDrm",
2006 "PMINSWrm",
2007 "PMINUBrm",
2008 "PMINUDrm",
2009 "PMINUWrm",
2010 "PSIGNBrm",
2011 "PSIGNDrm",
2012 "PSIGNWrm",
2013 "PSUBBrm",
2014 "PSUBDrm",
2015 "PSUBQrm",
2016 "PSUBSBrm",
2017 "PSUBSWrm",
2018 "PSUBUSBrm",
2019 "PSUBUSWrm",
2020 "PSUBWrm",
2021 "VPABSBrm",
2022 "VPABSDrm",
2023 "VPABSWrm",
2024 "VPADDBrm",
2025 "VPADDDrm",
2026 "VPADDQrm",
2027 "VPADDSBrm",
2028 "VPADDSWrm",
2029 "VPADDUSBrm",
2030 "VPADDUSWrm",
2031 "VPADDWrm",
2032 "VPAVGBrm",
2033 "VPAVGWrm",
2034 "VPCMPEQBrm",
2035 "VPCMPEQDrm",
2036 "VPCMPEQQrm",
2037 "VPCMPEQWrm",
2038 "VPCMPGTBrm",
2039 "VPCMPGTDrm",
2040 "VPCMPGTWrm",
2041 "VPMAXSBrm",
2042 "VPMAXSDrm",
2043 "VPMAXSWrm",
2044 "VPMAXUBrm",
2045 "VPMAXUDrm",
2046 "VPMAXUWrm",
2047 "VPMINSBrm",
2048 "VPMINSDrm",
2049 "VPMINSWrm",
2050 "VPMINUBrm",
2051 "VPMINUDrm",
2052 "VPMINUWrm",
2053 "VPSIGNBrm",
2054 "VPSIGNDrm",
2055 "VPSIGNWrm",
2056 "VPSUBBrm",
2057 "VPSUBDrm",
2058 "VPSUBQrm",
2059 "VPSUBSBrm",
2060 "VPSUBSWrm",
2061 "VPSUBUSBrm",
2062 "VPSUBUSWrm",
2063 "VPSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2064
2065def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
2066 let Latency = 6;
2067 let NumMicroOps = 2;
2068 let ResourceCycles = [1,1];
2069}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2070def: InstRW<[BWWriteResGroup65], (instregex "BLENDPDrmi",
2071 "BLENDPSrmi",
2072 "MMX_PANDNirm",
2073 "MMX_PANDirm",
2074 "MMX_PORirm",
2075 "MMX_PXORirm",
2076 "PANDNrm",
2077 "PANDrm",
2078 "PORrm",
2079 "PXORrm",
2080 "VBLENDPDrmi",
2081 "VBLENDPSrmi",
2082 "VINSERTF128rm",
2083 "VINSERTI128rm",
2084 "VPANDNrm",
2085 "VPANDrm",
2086 "VPBLENDDrmi",
2087 "VPORrm",
2088 "VPXORrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2089
2090def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
2091 let Latency = 6;
2092 let NumMicroOps = 2;
2093 let ResourceCycles = [1,1];
2094}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2095def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2096def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm",
2097 "AND(8|16|32|64)rm",
2098 "CMP(8|16|32|64)mi",
2099 "CMP(8|16|32|64)mr",
2100 "CMP(8|16|32|64)rm",
2101 "OR(8|16|32|64)rm",
2102 "POP(16|32|64)rmr",
2103 "SUB(8|16|32|64)rm",
2104 "TEST(8|16|32|64)mr",
2105 "TEST(8|16|32|64)mi",
2106 "XOR(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2107
2108def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2109 let Latency = 6;
2110 let NumMicroOps = 4;
2111 let ResourceCycles = [1,1,2];
2112}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2113def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL",
2114 "SHRD(16|32|64)rrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2115
2116def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
2117 let Latency = 6;
2118 let NumMicroOps = 4;
2119 let ResourceCycles = [1,1,1,1];
2120}
2121def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
2122
2123def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
2124 let Latency = 6;
2125 let NumMicroOps = 4;
2126 let ResourceCycles = [1,1,1,1];
2127}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2128def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
2129 "BTR(16|32|64)mi8",
2130 "BTS(16|32|64)mi8",
2131 "SAR(8|16|32|64)m1",
2132 "SAR(8|16|32|64)mi",
2133 "SHL(8|16|32|64)m1",
2134 "SHL(8|16|32|64)mi",
2135 "SHR(8|16|32|64)m1",
2136 "SHR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2137
2138def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2139 let Latency = 6;
2140 let NumMicroOps = 4;
2141 let ResourceCycles = [1,1,1,1];
2142}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2143def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi",
2144 "ADD(8|16|32|64)mr",
2145 "AND(8|16|32|64)mi",
2146 "AND(8|16|32|64)mr",
2147 "DEC(8|16|32|64)m",
2148 "INC(8|16|32|64)m",
2149 "NEG(8|16|32|64)m",
2150 "NOT(8|16|32|64)m",
2151 "OR(8|16|32|64)mi",
2152 "OR(8|16|32|64)mr",
2153 "POP(16|32|64)rmm",
2154 "PUSH(16|32|64)rmm",
2155 "SUB(8|16|32|64)mi",
2156 "SUB(8|16|32|64)mr",
2157 "XOR(8|16|32|64)mi",
2158 "XOR(8|16|32|64)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2159
2160def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
2161 let Latency = 6;
2162 let NumMicroOps = 6;
2163 let ResourceCycles = [1,5];
2164}
2165def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
2166
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2167def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
2168 let Latency = 7;
2169 let NumMicroOps = 2;
2170 let ResourceCycles = [1,1];
2171}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2172def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm",
2173 "VPSLLQYrm",
2174 "VPSLLVQYrm",
2175 "VPSLLWYrm",
2176 "VPSRADYrm",
2177 "VPSRAWYrm",
2178 "VPSRLDYrm",
2179 "VPSRLQYrm",
2180 "VPSRLVQYrm",
2181 "VPSRLWYrm",
2182 "VTESTPDYrm",
2183 "VTESTPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2184
2185def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
2186 let Latency = 7;
2187 let NumMicroOps = 2;
2188 let ResourceCycles = [1,1];
2189}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2190def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m",
2191 "FCOM64m",
2192 "FCOMP32m",
2193 "FCOMP64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2194
2195def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
2196 let Latency = 7;
2197 let NumMicroOps = 2;
2198 let ResourceCycles = [1,1];
2199}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2200def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm",
2201 "VANDNPSYrm",
2202 "VANDPDYrm",
2203 "VANDPSYrm",
2204 "VORPDYrm",
2205 "VORPSYrm",
2206 "VPACKSSDWYrm",
2207 "VPACKSSWBYrm",
2208 "VPACKUSDWYrm",
2209 "VPACKUSWBYrm",
2210 "VPALIGNRYrmi",
2211 "VPBLENDWYrmi",
2212 "VPERMILPDYmi",
2213 "VPERMILPDYrm",
2214 "VPERMILPSYmi",
2215 "VPERMILPSYrm",
2216 "VPSHUFBYrm",
2217 "VPSHUFDYmi",
2218 "VPSHUFHWYmi",
2219 "VPSHUFLWYmi",
2220 "VPUNPCKHBWYrm",
2221 "VPUNPCKHDQYrm",
2222 "VPUNPCKHQDQYrm",
2223 "VPUNPCKHWDYrm",
2224 "VPUNPCKLBWYrm",
2225 "VPUNPCKLDQYrm",
2226 "VPUNPCKLQDQYrm",
2227 "VPUNPCKLWDYrm",
2228 "VSHUFPDYrmi",
2229 "VSHUFPSYrmi",
2230 "VUNPCKHPDYrm",
2231 "VUNPCKHPSYrm",
2232 "VUNPCKLPDYrm",
2233 "VUNPCKLPSYrm",
2234 "VXORPDYrm",
2235 "VXORPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2236
2237def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
2238 let Latency = 7;
2239 let NumMicroOps = 2;
2240 let ResourceCycles = [1,1];
2241}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2242def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm",
2243 "VPABSDYrm",
2244 "VPABSWYrm",
2245 "VPADDBYrm",
2246 "VPADDDYrm",
2247 "VPADDQYrm",
2248 "VPADDSBYrm",
2249 "VPADDSWYrm",
2250 "VPADDUSBYrm",
2251 "VPADDUSWYrm",
2252 "VPADDWYrm",
2253 "VPAVGBYrm",
2254 "VPAVGWYrm",
2255 "VPCMPEQBYrm",
2256 "VPCMPEQDYrm",
2257 "VPCMPEQQYrm",
2258 "VPCMPEQWYrm",
2259 "VPCMPGTBYrm",
2260 "VPCMPGTDYrm",
2261 "VPCMPGTWYrm",
2262 "VPMAXSBYrm",
2263 "VPMAXSDYrm",
2264 "VPMAXSWYrm",
2265 "VPMAXUBYrm",
2266 "VPMAXUDYrm",
2267 "VPMAXUWYrm",
2268 "VPMINSBYrm",
2269 "VPMINSDYrm",
2270 "VPMINSWYrm",
2271 "VPMINUBYrm",
2272 "VPMINUDYrm",
2273 "VPMINUWYrm",
2274 "VPSIGNBYrm",
2275 "VPSIGNDYrm",
2276 "VPSIGNWYrm",
2277 "VPSUBBYrm",
2278 "VPSUBDYrm",
2279 "VPSUBQYrm",
2280 "VPSUBSBYrm",
2281 "VPSUBSWYrm",
2282 "VPSUBUSBYrm",
2283 "VPSUBUSWYrm",
2284 "VPSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2285
2286def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
2287 let Latency = 7;
2288 let NumMicroOps = 2;
2289 let ResourceCycles = [1,1];
2290}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2291def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi",
2292 "VBLENDPSYrmi",
2293 "VPANDNYrm",
2294 "VPANDYrm",
2295 "VPBLENDDYrmi",
2296 "VPORYrm",
2297 "VPXORYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2298
2299def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> {
2300 let Latency = 7;
2301 let NumMicroOps = 3;
2302 let ResourceCycles = [1,2];
2303}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2304def: InstRW<[BWWriteResGroup78], (instregex "MPSADBWrri",
2305 "VMPSADBWYrri",
2306 "VMPSADBWrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2307
2308def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
2309 let Latency = 7;
2310 let NumMicroOps = 3;
2311 let ResourceCycles = [2,1];
2312}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2313def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPDrm0",
2314 "BLENDVPSrm0",
2315 "MMX_PACKSSDWirm",
2316 "MMX_PACKSSWBirm",
2317 "MMX_PACKUSWBirm",
2318 "PBLENDVBrm0",
2319 "VBLENDVPDrm",
2320 "VBLENDVPSrm",
2321 "VMASKMOVPDrm",
2322 "VMASKMOVPSrm",
2323 "VPBLENDVBrm",
2324 "VPMASKMOVDrm",
2325 "VPMASKMOVQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2326
2327def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
2328 let Latency = 7;
2329 let NumMicroOps = 3;
2330 let ResourceCycles = [1,2];
2331}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2332def: InstRW<[BWWriteResGroup80], (instregex "LEAVE64",
2333 "SCASB",
2334 "SCASL",
2335 "SCASQ",
2336 "SCASW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2337
2338def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2339 let Latency = 7;
2340 let NumMicroOps = 3;
2341 let ResourceCycles = [1,1,1];
2342}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2343def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
2344 "PSLLQrm",
2345 "PSLLWrm",
2346 "PSRADrm",
2347 "PSRAWrm",
2348 "PSRLDrm",
2349 "PSRLQrm",
2350 "PSRLWrm",
2351 "PTESTrm",
2352 "VPSLLDrm",
2353 "VPSLLQrm",
2354 "VPSLLWrm",
2355 "VPSRADrm",
2356 "VPSRAWrm",
2357 "VPSRLDrm",
2358 "VPSRLQrm",
2359 "VPSRLWrm",
2360 "VPTESTrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2361
2362def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
2363 let Latency = 7;
2364 let NumMicroOps = 3;
2365 let ResourceCycles = [1,1,1];
2366}
2367def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
2368
2369def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {
2370 let Latency = 7;
2371 let NumMicroOps = 3;
2372 let ResourceCycles = [1,1,1];
2373}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2374def: InstRW<[BWWriteResGroup83], (instregex "(V?)LDMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2375
2376def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2377 let Latency = 7;
2378 let NumMicroOps = 3;
2379 let ResourceCycles = [1,1,1];
2380}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2381def: InstRW<[BWWriteResGroup84], (instregex "LRETQ",
2382 "RETQ")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2383
2384def BWWriteResGroup85 : SchedWriteRes<[BWPort23,BWPort06,BWPort15]> {
2385 let Latency = 7;
2386 let NumMicroOps = 3;
2387 let ResourceCycles = [1,1,1];
2388}
Craig Toppera42a2ba2017-12-16 18:35:31 +0000[diff] [blame]2389def: InstRW<[BWWriteResGroup85], (instregex "BEXTR(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2390
2391def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2392 let Latency = 7;
2393 let NumMicroOps = 3;
2394 let ResourceCycles = [1,1,1];
2395}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]2396def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2397
2398def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
2399 let Latency = 7;
2400 let NumMicroOps = 5;
2401 let ResourceCycles = [1,1,1,2];
2402}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2403def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
2404 "ROL(8|16|32|64)mi",
2405 "ROR(8|16|32|64)m1",
2406 "ROR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2407
2408def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2409 let Latency = 7;
2410 let NumMicroOps = 5;
2411 let ResourceCycles = [1,1,1,2];
2412}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2413def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2414
2415def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2416 let Latency = 7;
2417 let NumMicroOps = 5;
2418 let ResourceCycles = [1,1,1,1,1];
2419}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2420def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
2421 "FARCALL64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2422
2423def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
2424 let Latency = 7;
2425 let NumMicroOps = 7;
2426 let ResourceCycles = [2,2,1,2];
2427}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2428def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2429
2430def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
2431 let Latency = 8;
2432 let NumMicroOps = 2;
2433 let ResourceCycles = [1,1];
2434}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2435def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2436def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
2437def: InstRW<[BWWriteResGroup91], (instregex "ADDPDrm",
2438 "ADDPSrm",
2439 "ADDSDrm",
2440 "ADDSSrm",
2441 "ADDSUBPDrm",
2442 "ADDSUBPSrm",
2443 "BSF(16|32|64)rm",
2444 "BSR(16|32|64)rm",
2445 "CMPPDrmi",
2446 "CMPPSrmi",
2447 "CMPSDrm",
2448 "CMPSSrm",
2449 "COMISDrm",
2450 "COMISSrm",
2451 "CVTDQ2PSrm",
2452 "CVTPS2DQrm",
2453 "CVTTPS2DQrm",
2454 "LZCNT(16|32|64)rm",
2455 "MAX(C?)PDrm",
2456 "MAX(C?)PSrm",
2457 "MAX(C?)SDrm",
2458 "MAX(C?)SSrm",
2459 "MIN(C?)PDrm",
2460 "MIN(C?)PSrm",
2461 "MIN(C?)SDrm",
2462 "MIN(C?)SSrm",
2463 "MMX_CVTPI2PSirm",
2464 "MMX_CVTPS2PIirm",
2465 "MMX_CVTTPS2PIirm",
2466 "PDEP(32|64)rm",
2467 "PEXT(32|64)rm",
2468 "POPCNT(16|32|64)rm",
2469 "SUBPDrm",
2470 "SUBPSrm",
2471 "SUBSDrm",
2472 "SUBSSrm",
2473 "TZCNT(16|32|64)rm",
2474 "UCOMISDrm",
2475 "UCOMISSrm",
2476 "VADDPDrm",
2477 "VADDPSrm",
2478 "VADDSDrm",
2479 "VADDSSrm",
2480 "VADDSUBPDrm",
2481 "VADDSUBPSrm",
2482 "VCMPPDrmi",
2483 "VCMPPSrmi",
2484 "VCMPSDrm",
2485 "VCMPSSrm",
2486 "VCOMISDrm",
2487 "VCOMISSrm",
2488 "VCVTDQ2PSrm",
2489 "VCVTPS2DQrm",
2490 "VCVTTPS2DQrm",
2491 "VMAX(C?)PDrm",
2492 "VMAX(C?)PSrm",
2493 "VMAX(C?)SDrm",
2494 "VMAX(C?)SSrm",
2495 "VMIN(C?)PDrm",
2496 "VMIN(C?)PSrm",
2497 "VMIN(C?)SDrm",
2498 "VMIN(C?)SSrm",
2499 "VSUBPDrm",
2500 "VSUBPSrm",
2501 "VSUBSDrm",
2502 "VSUBSSrm",
2503 "VUCOMISDrm",
2504 "VUCOMISSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2505
2506def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
2507 let Latency = 8;
2508 let NumMicroOps = 3;
2509 let ResourceCycles = [1,1,1];
2510}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]2511def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2512
2513def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
2514 let Latency = 8;
2515 let NumMicroOps = 5;
2516}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2517def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2518
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2519def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
2520 let Latency = 8;
2521 let NumMicroOps = 2;
2522 let ResourceCycles = [1,1];
2523}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2524def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
2525 "VPMOVSXBQYrm",
2526 "VPMOVSXBWYrm",
2527 "VPMOVSXDQYrm",
2528 "VPMOVSXWDYrm",
2529 "VPMOVSXWQYrm",
2530 "VPMOVZXWDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2531
2532def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
2533 let Latency = 8;
2534 let NumMicroOps = 2;
2535 let ResourceCycles = [1,1];
2536}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2537def: InstRW<[BWWriteResGroup93], (instregex "MULPDrm",
2538 "MULPSrm",
2539 "MULSDrm",
2540 "MULSSrm",
2541 "VMULPDrm",
2542 "VMULPSrm",
2543 "VMULSDrm",
2544 "VMULSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2545
2546def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
2547 let Latency = 8;
2548 let NumMicroOps = 3;
2549 let ResourceCycles = [2,1];
2550}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2551def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm",
2552 "VBLENDVPSYrm",
2553 "VMASKMOVPDYrm",
2554 "VMASKMOVPSYrm",
2555 "VPBLENDVBYrm",
2556 "VPMASKMOVDYrm",
2557 "VPMASKMOVQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2558
2559def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2560 let Latency = 8;
2561 let NumMicroOps = 4;
2562 let ResourceCycles = [2,1,1];
2563}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2564def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
2565 "VPSRAVDrm",
2566 "VPSRLVDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2567
2568def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2569 let Latency = 8;
2570 let NumMicroOps = 4;
2571 let ResourceCycles = [2,1,1];
2572}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2573def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm",
2574 "MMX_PHADDSWrm",
2575 "MMX_PHADDWrm",
2576 "MMX_PHSUBDrm",
2577 "MMX_PHSUBSWrm",
2578 "MMX_PHSUBWrm",
2579 "PHADDDrm",
2580 "PHADDSWrm",
2581 "PHADDWrm",
2582 "PHSUBDrm",
2583 "PHSUBSWrm",
2584 "PHSUBWrm",
2585 "VPHADDDrm",
2586 "VPHADDSWrm",
2587 "VPHADDWrm",
2588 "VPHSUBDrm",
2589 "VPHSUBSWrm",
2590 "VPHSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2591
2592def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2593 let Latency = 8;
2594 let NumMicroOps = 5;
2595 let ResourceCycles = [1,1,1,2];
2596}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2597def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
2598 "RCL(8|16|32|64)mi",
2599 "RCR(8|16|32|64)m1",
2600 "RCR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2601
2602def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2603 let Latency = 8;
2604 let NumMicroOps = 5;
2605 let ResourceCycles = [1,1,2,1];
2606}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2607def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2608
2609def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2610 let Latency = 8;
2611 let NumMicroOps = 6;
2612 let ResourceCycles = [1,1,1,3];
2613}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2614def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi",
2615 "XCHG(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2616
2617def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2618 let Latency = 8;
2619 let NumMicroOps = 6;
2620 let ResourceCycles = [1,1,1,2,1];
2621}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2622def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr",
2623 "CMPXCHG(8|16|32|64)rm",
2624 "ROL(8|16|32|64)mCL",
2625 "SAR(8|16|32|64)mCL",
2626 "SBB(8|16|32|64)mi",
2627 "SBB(8|16|32|64)mr",
2628 "SHL(8|16|32|64)mCL",
2629 "SHR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2630
2631def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
2632 let Latency = 9;
2633 let NumMicroOps = 2;
2634 let ResourceCycles = [1,1];
2635}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2636def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
2637 "ADD_F64m",
2638 "ILD_F16m",
2639 "ILD_F32m",
2640 "ILD_F64m",
2641 "SUBR_F32m",
2642 "SUBR_F64m",
2643 "SUB_F32m",
2644 "SUB_F64m",
2645 "VADDPDYrm",
2646 "VADDPSYrm",
2647 "VADDSUBPDYrm",
2648 "VADDSUBPSYrm",
2649 "VCMPPDYrmi",
2650 "VCMPPSYrmi",
2651 "VCVTDQ2PSYrm",
2652 "VCVTPS2DQYrm",
2653 "VCVTTPS2DQYrm",
2654 "VMAX(C?)PDYrm",
2655 "VMAX(C?)PSYrm",
2656 "VMIN(C?)PDYrm",
2657 "VMIN(C?)PSYrm",
2658 "VSUBPDYrm",
2659 "VSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2660
2661def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
2662 let Latency = 9;
2663 let NumMicroOps = 2;
2664 let ResourceCycles = [1,1];
2665}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2666def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
2667 "VPERM2I128rm",
2668 "VPERMDYrm",
2669 "VPERMPDYmi",
2670 "VPERMPSYrm",
2671 "VPERMQYmi",
2672 "VPMOVZXBDYrm",
2673 "VPMOVZXBQYrm",
2674 "VPMOVZXBWYrm",
2675 "VPMOVZXDQYrm",
2676 "VPMOVZXWQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2677
2678def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
2679 let Latency = 9;
2680 let NumMicroOps = 2;
2681 let ResourceCycles = [1,1];
2682}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2683def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
2684 "VMULPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2685
2686def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2687 let Latency = 9;
2688 let NumMicroOps = 3;
2689 let ResourceCycles = [1,1,1];
2690}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2691def: InstRW<[BWWriteResGroup104], (instregex "DPPDrri",
2692 "VDPPDrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2693
2694def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2695 let Latency = 9;
2696 let NumMicroOps = 3;
2697 let ResourceCycles = [1,1,1];
2698}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2699def: InstRW<[BWWriteResGroup105], (instregex "CVTSD2SI64rm",
2700 "CVTSD2SIrm",
2701 "CVTSS2SI64rm",
2702 "CVTSS2SIrm",
2703 "CVTTSD2SI64rm",
2704 "CVTTSD2SIrm",
2705 "CVTTSS2SIrm",
2706 "VCVTSD2SI64rm",
2707 "VCVTSD2SIrm",
2708 "VCVTSS2SI64rm",
2709 "VCVTSS2SIrm",
2710 "VCVTTSD2SI64rm",
2711 "VCVTTSD2SIrm",
2712 "VCVTTSS2SI64rm",
2713 "VCVTTSS2SIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2714
2715def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2716 let Latency = 9;
2717 let NumMicroOps = 3;
2718 let ResourceCycles = [1,1,1];
2719}
2720def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
2721
2722def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2723 let Latency = 9;
2724 let NumMicroOps = 3;
2725 let ResourceCycles = [1,1,1];
2726}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame^]2727def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2728def: InstRW<[BWWriteResGroup107], (instregex "CVTDQ2PDrm",
2729 "CVTPD2DQrm",
2730 "CVTPD2PSrm",
2731 "CVTSD2SSrm",
2732 "CVTTPD2DQrm",
2733 "MMX_CVTPD2PIirm",
2734 "MMX_CVTPI2PDirm",
2735 "MMX_CVTTPD2PIirm",
2736 "VCVTDQ2PDrm",
2737 "VCVTSD2SSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2738
2739def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
2740 let Latency = 9;
2741 let NumMicroOps = 3;
2742 let ResourceCycles = [1,1,1];
2743}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2744def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTBYrm",
2745 "VPBROADCASTBrm",
2746 "VPBROADCASTWYrm",
2747 "VPBROADCASTWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2748
2749def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2750 let Latency = 9;
2751 let NumMicroOps = 4;
2752 let ResourceCycles = [2,1,1];
2753}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2754def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm",
2755 "VPSRAVDYrm",
2756 "VPSRLVDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2757
2758def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2759 let Latency = 9;
2760 let NumMicroOps = 4;
2761 let ResourceCycles = [2,1,1];
2762}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2763def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm",
2764 "VPHADDSWYrm",
2765 "VPHADDWYrm",
2766 "VPHSUBDYrm",
2767 "VPHSUBSWYrm",
2768 "VPHSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2769
2770def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
2771 let Latency = 9;
2772 let NumMicroOps = 4;
2773 let ResourceCycles = [1,1,1,1];
2774}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2775def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8",
2776 "SHRD(16|32|64)mri8")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2777
2778def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2779 let Latency = 9;
2780 let NumMicroOps = 5;
2781 let ResourceCycles = [1,1,3];
2782}
2783def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
2784
2785def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2786 let Latency = 9;
2787 let NumMicroOps = 5;
2788 let ResourceCycles = [1,2,1,1];
2789}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2790def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
2791 "LSL(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2792
2793def BWWriteResGroup114 : SchedWriteRes<[BWPort0]> {
2794 let Latency = 10;
2795 let NumMicroOps = 2;
2796 let ResourceCycles = [2];
2797}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2798def: InstRW<[BWWriteResGroup114], (instregex "PMULLDrr",
2799 "VPMULLDYrr",
2800 "VPMULLDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2801
2802def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
2803 let Latency = 10;
2804 let NumMicroOps = 2;
2805 let ResourceCycles = [1,1];
2806}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2807def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
2808 "MMX_PMADDWDirm",
2809 "MMX_PMULHRSWrm",
2810 "MMX_PMULHUWirm",
2811 "MMX_PMULHWirm",
2812 "MMX_PMULLWirm",
2813 "MMX_PMULUDQirm",
2814 "MMX_PSADBWirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2815 "PCMPGTQrm",
2816 "PHMINPOSUWrm",
2817 "PMADDUBSWrm",
2818 "PMADDWDrm",
2819 "PMULDQrm",
2820 "PMULHRSWrm",
2821 "PMULHUWrm",
2822 "PMULHWrm",
2823 "PMULLWrm",
2824 "PMULUDQrm",
2825 "PSADBWrm",
2826 "RCPPSm",
2827 "RCPSSm",
2828 "RSQRTPSm",
2829 "RSQRTSSm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2830 "VPCMPGTQrm",
2831 "VPHMINPOSUWrm",
2832 "VPMADDUBSWrm",
2833 "VPMADDWDrm",
2834 "VPMULDQrm",
2835 "VPMULHRSWrm",
2836 "VPMULHUWrm",
2837 "VPMULHWrm",
2838 "VPMULLWrm",
2839 "VPMULUDQrm",
2840 "VPSADBWrm",
2841 "VRCPPSm",
2842 "VRCPSSm",
2843 "VRSQRTPSm",
2844 "VRSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2845
2846def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
2847 let Latency = 10;
2848 let NumMicroOps = 2;
2849 let ResourceCycles = [1,1];
2850}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2851def: InstRW<[BWWriteResGroup116],
2852 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m",
2853 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2854
2855def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
2856 let Latency = 10;
2857 let NumMicroOps = 3;
2858 let ResourceCycles = [2,1];
2859}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2860def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m",
2861 "FICOM32m",
2862 "FICOMP16m",
2863 "FICOMP32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2864
2865def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2866 let Latency = 10;
2867 let NumMicroOps = 3;
2868 let ResourceCycles = [1,1,1];
2869}
2870def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
2871
2872def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2873 let Latency = 10;
2874 let NumMicroOps = 4;
2875 let ResourceCycles = [1,2,1];
2876}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2877def: InstRW<[BWWriteResGroup119], (instregex "HADDPDrm",
2878 "HADDPSrm",
2879 "HSUBPDrm",
2880 "HSUBPSrm",
2881 "VHADDPDrm",
2882 "VHADDPSrm",
2883 "VHSUBPDrm",
2884 "VHSUBPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2885
2886def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2887 let Latency = 10;
2888 let NumMicroOps = 4;
2889 let ResourceCycles = [1,1,1,1];
2890}
2891def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
2892
2893def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame^]2894 let Latency = 9;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2895 let NumMicroOps = 4;
2896 let ResourceCycles = [1,1,1,1];
2897}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame^]2898def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2899
2900def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> {
2901 let Latency = 11;
2902 let NumMicroOps = 1;
2903 let ResourceCycles = [1];
2904}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2905def: InstRW<[BWWriteResGroup122], (instregex "DIVPSrr",
2906 "DIVSSrr",
2907 "VDIVPSrr",
2908 "VDIVSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2909
2910def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
2911 let Latency = 11;
2912 let NumMicroOps = 2;
2913 let ResourceCycles = [1,1];
2914}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2915def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
2916 "MUL_F64m",
2917 "VPCMPGTQYrm",
2918 "VPMADDUBSWYrm",
2919 "VPMADDWDYrm",
2920 "VPMULDQYrm",
2921 "VPMULHRSWYrm",
2922 "VPMULHUWYrm",
2923 "VPMULHWYrm",
2924 "VPMULLWYrm",
2925 "VPMULUDQYrm",
2926 "VPSADBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2927
2928def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {
2929 let Latency = 11;
2930 let NumMicroOps = 2;
2931 let ResourceCycles = [1,1];
2932}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2933def: InstRW<[BWWriteResGroup124],
2934 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2935
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2936def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
2937 let Latency = 11;
2938 let NumMicroOps = 3;
2939 let ResourceCycles = [2,1];
2940}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2941def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr",
2942 "VRSQRTPSYr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2943
2944def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {
2945 let Latency = 11;
2946 let NumMicroOps = 3;
2947 let ResourceCycles = [2,1];
2948}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2949def: InstRW<[BWWriteResGroup127], (instregex "ROUNDPDm",
2950 "ROUNDPSm",
2951 "ROUNDSDm",
2952 "ROUNDSSm",
2953 "VROUNDPDm",
2954 "VROUNDPSm",
2955 "VROUNDSDm",
2956 "VROUNDSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2957
2958def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2959 let Latency = 11;
2960 let NumMicroOps = 3;
2961 let ResourceCycles = [1,1,1];
2962}
2963def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
2964
2965def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2966 let Latency = 11;
2967 let NumMicroOps = 4;
2968 let ResourceCycles = [1,2,1];
2969}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2970def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm",
2971 "VHADDPSYrm",
2972 "VHSUBPDYrm",
2973 "VHSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2974
2975def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2976 let Latency = 11;
2977 let NumMicroOps = 6;
2978 let ResourceCycles = [1,1,1,1,2];
2979}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2980def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL",
2981 "SHRD(16|32|64)mrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2982
2983def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2984 let Latency = 11;
2985 let NumMicroOps = 7;
2986 let ResourceCycles = [2,2,3];
2987}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2988def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
2989 "RCR(16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2990
2991def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2992 let Latency = 11;
2993 let NumMicroOps = 9;
2994 let ResourceCycles = [1,4,1,3];
2995}
2996def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
2997
2998def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
2999 let Latency = 11;
3000 let NumMicroOps = 11;
3001 let ResourceCycles = [2,9];
3002}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3003def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
3004def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3005
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3006def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
3007 let Latency = 12;
3008 let NumMicroOps = 3;
3009 let ResourceCycles = [2,1];
3010}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3011def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
3012 "ADD_FI32m",
3013 "SUBR_FI16m",
3014 "SUBR_FI32m",
3015 "SUB_FI16m",
3016 "SUB_FI32m",
3017 "VROUNDYPDm",
3018 "VROUNDYPSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3019
3020def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
3021 let Latency = 12;
3022 let NumMicroOps = 4;
3023 let ResourceCycles = [1,2,1];
3024}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3025def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3026
3027def BWWriteResGroup137 : SchedWriteRes<[BWPort0]> {
3028 let Latency = 13;
3029 let NumMicroOps = 1;
3030 let ResourceCycles = [1];
3031}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3032def: InstRW<[BWWriteResGroup137], (instregex "SQRTPSr",
3033 "SQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3034
3035def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
3036 let Latency = 13;
3037 let NumMicroOps = 4;
3038 let ResourceCycles = [1,2,1];
3039}
3040def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
3041
3042def BWWriteResGroup139 : SchedWriteRes<[BWPort0]> {
3043 let Latency = 14;
3044 let NumMicroOps = 1;
3045 let ResourceCycles = [1];
3046}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3047def: InstRW<[BWWriteResGroup139], (instregex "DIVPDrr",
3048 "DIVSDrr",
3049 "VDIVPDrr",
3050 "VDIVSDrr",
3051 "VSQRTPSr",
3052 "VSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3053
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3054def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
3055 let Latency = 14;
3056 let NumMicroOps = 3;
3057 let ResourceCycles = [1,1,1];
3058}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3059def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
3060 "MUL_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3061
3062def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
3063 let Latency = 14;
3064 let NumMicroOps = 4;
3065 let ResourceCycles = [2,1,1];
3066}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3067def: InstRW<[BWWriteResGroup142], (instregex "DPPSrri",
3068 "VDPPSYrri",
3069 "VDPPSrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3070
3071def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
3072 let Latency = 14;
3073 let NumMicroOps = 4;
3074 let ResourceCycles = [1,1,1,1];
3075}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3076def: InstRW<[BWWriteResGroup143], (instregex "(V?)DPPDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3077
3078def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
3079 let Latency = 14;
3080 let NumMicroOps = 8;
3081 let ResourceCycles = [2,2,1,3];
3082}
3083def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
3084
3085def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
3086 let Latency = 14;
3087 let NumMicroOps = 10;
3088 let ResourceCycles = [2,3,1,4];
3089}
3090def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
3091
3092def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
3093 let Latency = 14;
3094 let NumMicroOps = 12;
3095 let ResourceCycles = [2,1,4,5];
3096}
3097def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;
3098
3099def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
3100 let Latency = 15;
3101 let NumMicroOps = 1;
3102 let ResourceCycles = [1];
3103}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3104def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0",
3105 "DIVR_FST0r",
3106 "DIVR_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3107
3108def BWWriteResGroup148 : SchedWriteRes<[BWPort0,BWPort23]> {
3109 let Latency = 15;
3110 let NumMicroOps = 3;
3111 let ResourceCycles = [2,1];
3112}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3113def: InstRW<[BWWriteResGroup148], (instregex "(V?)PMULLDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3114
3115def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
3116 let Latency = 15;
3117 let NumMicroOps = 10;
3118 let ResourceCycles = [1,1,1,4,1,2];
3119}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3120def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3121
3122def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {
3123 let Latency = 16;
3124 let NumMicroOps = 2;
3125 let ResourceCycles = [1,1];
3126}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3127def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
3128 "(V?)DIVSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3129
3130def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {
3131 let Latency = 16;
3132 let NumMicroOps = 3;
3133 let ResourceCycles = [2,1];
3134}
3135def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
3136
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3137def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
3138 let Latency = 16;
3139 let NumMicroOps = 14;
3140 let ResourceCycles = [1,1,1,4,2,5];
3141}
3142def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;
3143
3144def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
3145 let Latency = 16;
3146 let NumMicroOps = 16;
3147 let ResourceCycles = [16];
3148}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3149def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3150
3151def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015]> {
3152 let Latency = 17;
3153 let NumMicroOps = 3;
3154 let ResourceCycles = [2,1];
3155}
3156def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
3157
3158def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3159 let Latency = 17;
3160 let NumMicroOps = 4;
3161 let ResourceCycles = [2,1,1];
3162}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3163def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
3164 "VRSQRTPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3165
3166def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23]> {
3167 let Latency = 18;
3168 let NumMicroOps = 2;
3169 let ResourceCycles = [1,1];
3170}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3171def: InstRW<[BWWriteResGroup157], (instregex "SQRTPSm",
3172 "SQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3173
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3174def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
3175 let Latency = 18;
3176 let NumMicroOps = 8;
3177 let ResourceCycles = [1,1,1,5];
3178}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3179def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3180def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3181
3182def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
3183 let Latency = 18;
3184 let NumMicroOps = 11;
3185 let ResourceCycles = [2,1,1,3,1,3];
3186}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3187def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3188
3189def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {
3190 let Latency = 19;
3191 let NumMicroOps = 2;
3192 let ResourceCycles = [1,1];
3193}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3194def: InstRW<[BWWriteResGroup161], (instregex "DIVPDrm",
3195 "DIVSDrm",
3196 "VDIVPDrm",
3197 "VDIVSDrm",
3198 "VSQRTPSm",
3199 "VSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3200
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3201def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
3202 let Latency = 19;
3203 let NumMicroOps = 5;
3204 let ResourceCycles = [2,1,1,1];
3205}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3206def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3207
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3208def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
3209 let Latency = 20;
3210 let NumMicroOps = 1;
3211 let ResourceCycles = [1];
3212}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3213def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0",
3214 "DIV_FST0r",
3215 "DIV_FrST0",
3216 "SQRTPDr",
3217 "SQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3218
3219def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
3220 let Latency = 20;
3221 let NumMicroOps = 5;
3222 let ResourceCycles = [2,1,1,1];
3223}
3224def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;
3225
3226def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
3227 let Latency = 20;
3228 let NumMicroOps = 8;
3229 let ResourceCycles = [1,1,1,1,1,1,2];
3230}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3231def: InstRW<[BWWriteResGroup167], (instregex "INSB",
3232 "INSL",
3233 "INSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3234
3235def BWWriteResGroup168 : SchedWriteRes<[BWPort0]> {
3236 let Latency = 21;
3237 let NumMicroOps = 1;
3238 let ResourceCycles = [1];
3239}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3240def: InstRW<[BWWriteResGroup168], (instregex "VSQRTPDr",
3241 "VSQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3242
3243def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
3244 let Latency = 21;
3245 let NumMicroOps = 2;
3246 let ResourceCycles = [1,1];
3247}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3248def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
3249 "DIV_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3250
3251def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015]> {
3252 let Latency = 21;
3253 let NumMicroOps = 3;
3254 let ResourceCycles = [2,1];
3255}
3256def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
3257
3258def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
3259 let Latency = 21;
3260 let NumMicroOps = 19;
3261 let ResourceCycles = [2,1,4,1,1,4,6];
3262}
3263def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;
3264
3265def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
3266 let Latency = 22;
3267 let NumMicroOps = 18;
3268 let ResourceCycles = [1,1,16];
3269}
3270def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
3271
3272def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015]> {
3273 let Latency = 23;
3274 let NumMicroOps = 3;
3275 let ResourceCycles = [2,1];
3276}
3277def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
3278
3279def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3280 let Latency = 23;
3281 let NumMicroOps = 4;
3282 let ResourceCycles = [2,1,1];
3283}
3284def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
3285
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3286def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
3287 let Latency = 23;
3288 let NumMicroOps = 19;
3289 let ResourceCycles = [3,1,15];
3290}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]3291def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3292
3293def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
3294 let Latency = 24;
3295 let NumMicroOps = 3;
3296 let ResourceCycles = [1,1,1];
3297}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3298def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
3299 "DIV_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3300
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3301def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23]> {
3302 let Latency = 25;
3303 let NumMicroOps = 2;
3304 let ResourceCycles = [1,1];
3305}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3306def: InstRW<[BWWriteResGroup179], (instregex "SQRTPDm",
3307 "SQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3308
3309def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
3310 let Latency = 26;
3311 let NumMicroOps = 2;
3312 let ResourceCycles = [1,1];
3313}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3314def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
3315 "DIVR_F64m",
3316 "VSQRTPDm",
3317 "VSQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3318
3319def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3320 let Latency = 27;
3321 let NumMicroOps = 4;
3322 let ResourceCycles = [2,1,1];
3323}
3324def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
3325
3326def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
3327 let Latency = 29;
3328 let NumMicroOps = 3;
3329 let ResourceCycles = [1,1,1];
3330}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3331def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
3332 "DIVR_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3333
3334def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3335 let Latency = 29;
3336 let NumMicroOps = 4;
3337 let ResourceCycles = [2,1,1];
3338}
3339def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
3340
3341def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3342 let Latency = 22;
3343 let NumMicroOps = 7;
3344 let ResourceCycles = [1,3,2,1];
3345}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3346def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3347
3348def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3349 let Latency = 23;
3350 let NumMicroOps = 9;
3351 let ResourceCycles = [1,3,4,1];
3352}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3353def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3354
3355def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3356 let Latency = 24;
3357 let NumMicroOps = 9;
3358 let ResourceCycles = [1,5,2,1];
3359}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3360def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3361
3362def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3363 let Latency = 25;
3364 let NumMicroOps = 7;
3365 let ResourceCycles = [1,3,2,1];
3366}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3367def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
3368 VGATHERDPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3369
3370def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3371 let Latency = 26;
3372 let NumMicroOps = 9;
3373 let ResourceCycles = [1,5,2,1];
3374}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3375def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3376
3377def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3378 let Latency = 26;
3379 let NumMicroOps = 14;
3380 let ResourceCycles = [1,4,8,1];
3381}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3382def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3383
3384def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
3385 let Latency = 27;
3386 let NumMicroOps = 9;
3387 let ResourceCycles = [1,5,2,1];
3388}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]3389def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3390
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3391def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
3392 let Latency = 29;
3393 let NumMicroOps = 27;
3394 let ResourceCycles = [1,5,1,1,19];
3395}
3396def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;
3397
3398def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
3399 let Latency = 30;
3400 let NumMicroOps = 28;
3401 let ResourceCycles = [1,6,1,1,19];
3402}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3403def: InstRW<[BWWriteResGroup186], (instregex "^XSAVE$", "XSAVEC", "XSAVES", "XSAVEOPT")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3404
3405def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
3406 let Latency = 31;
3407 let NumMicroOps = 31;
3408 let ResourceCycles = [8,1,21,1];
3409}
3410def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
3411
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3412def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> {
3413 let Latency = 34;
3414 let NumMicroOps = 3;
3415 let ResourceCycles = [2,1];
3416}
3417def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
3418
3419def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
3420 let Latency = 34;
3421 let NumMicroOps = 8;
3422 let ResourceCycles = [2,2,2,1,1];
3423}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3424def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3425
3426def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
3427 let Latency = 34;
3428 let NumMicroOps = 23;
3429 let ResourceCycles = [1,5,3,4,10];
3430}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3431def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
3432 "IN(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3433
3434def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
3435 let Latency = 35;
3436 let NumMicroOps = 8;
3437 let ResourceCycles = [2,2,2,1,1];
3438}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]3439def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3440
3441def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
3442 let Latency = 35;
3443 let NumMicroOps = 23;
3444 let ResourceCycles = [1,5,2,1,4,10];
3445}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]3446def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
3447 "OUT(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3448
3449def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
3450 let Latency = 40;
3451 let NumMicroOps = 4;
3452 let ResourceCycles = [2,1,1];
3453}
3454def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
3455
3456def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
3457 let Latency = 42;
3458 let NumMicroOps = 22;
3459 let ResourceCycles = [2,20];
3460}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3461def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3462
3463def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
3464 let Latency = 60;
3465 let NumMicroOps = 64;
3466 let ResourceCycles = [2,2,8,1,10,2,39];
3467}
3468def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3469
3470def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
3471 let Latency = 63;
3472 let NumMicroOps = 88;
3473 let ResourceCycles = [4,4,31,1,2,1,45];
3474}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3475def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3476
3477def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
3478 let Latency = 63;
3479 let NumMicroOps = 90;
3480 let ResourceCycles = [4,2,33,1,2,1,47];
3481}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]3482def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3483
3484def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
3485 let Latency = 75;
3486 let NumMicroOps = 15;
3487 let ResourceCycles = [6,3,6];
3488}
3489def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;
3490
3491def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
3492 let Latency = 80;
3493 let NumMicroOps = 32;
3494 let ResourceCycles = [7,7,3,3,1,11];
3495}
3496def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
3497
3498def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
3499 let Latency = 115;
3500 let NumMicroOps = 100;
3501 let ResourceCycles = [9,9,11,8,1,11,21,30];
3502}
3503def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]3504
3505} // SchedModel
3506