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Matt Arsenault0c90e952015-11-06 18:17:45 +00001//=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
Tom Stellard75aadc22012-12-11 21:25:42 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9//
10/// \file
Adrian Prantl5f8f34e42018-05-01 15:54:18 +000011/// AMDGPU specific subclass of TargetSubtarget.
Tom Stellard75aadc22012-12-11 21:25:42 +000012//
13//===----------------------------------------------------------------------===//
14
Matt Arsenault0c90e952015-11-06 18:17:45 +000015#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
Matt Arsenaultf59e5382015-11-06 18:23:00 +000017
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000018#include "AMDGPU.h"
Quentin Colombet61d71a12017-08-15 22:31:51 +000019#include "AMDGPUCallLowering.h"
Matt Arsenault43e92fe2016-06-24 06:30:11 +000020#include "R600FrameLowering.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000021#include "R600ISelLowering.h"
22#include "R600InstrInfo.h"
Matt Arsenault43e92fe2016-06-24 06:30:11 +000023#include "SIFrameLowering.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000024#include "SIISelLowering.h"
25#include "SIInstrInfo.h"
Tom Stellard347ac792015-06-26 21:15:07 +000026#include "Utils/AMDGPUBaseInfo.h"
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000027#include "llvm/ADT/Triple.h"
Quentin Colombet61d71a12017-08-15 22:31:51 +000028#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
29#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
30#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000031#include "llvm/CodeGen/MachineFunction.h"
Matt Arsenault56684d42016-08-11 17:31:42 +000032#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000033#include "llvm/MC/MCInstrItineraries.h"
34#include "llvm/Support/MathExtras.h"
35#include <cassert>
36#include <cstdint>
37#include <memory>
38#include <utility>
Tom Stellard75aadc22012-12-11 21:25:42 +000039
40#define GET_SUBTARGETINFO_HEADER
41#include "AMDGPUGenSubtargetInfo.inc"
Tom Stellardc5a154d2018-06-28 23:47:12 +000042#define GET_SUBTARGETINFO_HEADER
43#include "R600GenSubtargetInfo.inc"
Tom Stellard75aadc22012-12-11 21:25:42 +000044
Tom Stellard75aadc22012-12-11 21:25:42 +000045namespace llvm {
46
Matt Arsenault43e92fe2016-06-24 06:30:11 +000047class StringRef;
Tom Stellarde99fb652015-01-20 19:33:04 +000048
Tom Stellard5bfbae52018-07-11 20:59:01 +000049class AMDGPUSubtarget {
50public:
51 enum Generation {
52 R600 = 0,
53 R700 = 1,
Matt Arsenault4bec7d42018-07-20 09:05:08 +000054 EVERGREEN = 2,
Tom Stellard5bfbae52018-07-11 20:59:01 +000055 NORTHERN_ISLANDS = 3,
56 SOUTHERN_ISLANDS = 4,
57 SEA_ISLANDS = 5,
58 VOLCANIC_ISLANDS = 6,
59 GFX9 = 7
60 };
61
Tom Stellardc5a154d2018-06-28 23:47:12 +000062private:
63 Triple TargetTriple;
64
65protected:
Tom Stellardc5a154d2018-06-28 23:47:12 +000066 bool Has16BitInsts;
67 bool HasMadMixInsts;
68 bool FP32Denormals;
69 bool FPExceptions;
70 bool HasSDWA;
71 bool HasVOP3PInsts;
72 bool HasMulI24;
73 bool HasMulU24;
Matt Arsenault6c7ba822018-08-15 21:03:55 +000074 bool HasInv2PiInlineImm;
Tom Stellardc5a154d2018-06-28 23:47:12 +000075 bool HasFminFmaxLegacy;
76 bool EnablePromoteAlloca;
77 int LocalMemorySize;
78 unsigned WavefrontSize;
79
80public:
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +000081 AMDGPUSubtarget(const Triple &TT);
Tom Stellardc5a154d2018-06-28 23:47:12 +000082
Tom Stellard5bfbae52018-07-11 20:59:01 +000083 static const AMDGPUSubtarget &get(const MachineFunction &MF);
84 static const AMDGPUSubtarget &get(const TargetMachine &TM,
Matt Arsenault4bec7d42018-07-20 09:05:08 +000085 const Function &F);
Tom Stellardc5a154d2018-06-28 23:47:12 +000086
87 /// \returns Default range flat work group size for a calling convention.
88 std::pair<unsigned, unsigned> getDefaultFlatWorkGroupSize(CallingConv::ID CC) const;
89
90 /// \returns Subtarget's default pair of minimum/maximum flat work group sizes
91 /// for function \p F, or minimum/maximum flat work group sizes explicitly
92 /// requested using "amdgpu-flat-work-group-size" attribute attached to
93 /// function \p F.
94 ///
95 /// \returns Subtarget's default values if explicitly requested values cannot
96 /// be converted to integer, or violate subtarget's specifications.
97 std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) const;
98
99 /// \returns Subtarget's default pair of minimum/maximum number of waves per
100 /// execution unit for function \p F, or minimum/maximum number of waves per
101 /// execution unit explicitly requested using "amdgpu-waves-per-eu" attribute
102 /// attached to function \p F.
103 ///
104 /// \returns Subtarget's default values if explicitly requested values cannot
105 /// be converted to integer, violate subtarget's specifications, or are not
106 /// compatible with minimum/maximum number of waves limited by flat work group
107 /// size, register usage, and/or lds usage.
108 std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
109
110 /// Return the amount of LDS that can be used that will not restrict the
111 /// occupancy lower than WaveCount.
112 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
113 const Function &) const;
114
115 /// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
116 /// the given LDS memory size is the only constraint.
117 unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const;
118
119 unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const;
120
121 bool isAmdHsaOS() const {
122 return TargetTriple.getOS() == Triple::AMDHSA;
123 }
124
125 bool isAmdPalOS() const {
126 return TargetTriple.getOS() == Triple::AMDPAL;
127 }
128
Tom Stellardec4feae2018-07-06 17:16:17 +0000129 bool isMesa3DOS() const {
130 return TargetTriple.getOS() == Triple::Mesa3D;
131 }
132
133 bool isMesaKernel(const Function &F) const {
134 return isMesa3DOS() && !AMDGPU::isShader(F.getCallingConv());
135 }
136
137 bool isAmdCodeObjectV2(const Function &F) const {
138 return isAmdHsaOS() || isMesaKernel(F);
139 }
140
Tom Stellardc5a154d2018-06-28 23:47:12 +0000141 bool has16BitInsts() const {
142 return Has16BitInsts;
143 }
144
145 bool hasMadMixInsts() const {
146 return HasMadMixInsts;
147 }
148
149 bool hasFP32Denormals() const {
150 return FP32Denormals;
151 }
152
153 bool hasFPExceptions() const {
154 return FPExceptions;
155 }
156
157 bool hasSDWA() const {
158 return HasSDWA;
159 }
160
161 bool hasVOP3PInsts() const {
162 return HasVOP3PInsts;
163 }
164
165 bool hasMulI24() const {
166 return HasMulI24;
167 }
168
169 bool hasMulU24() const {
170 return HasMulU24;
171 }
172
Matt Arsenault6c7ba822018-08-15 21:03:55 +0000173 bool hasInv2PiInlineImm() const {
174 return HasInv2PiInlineImm;
175 }
176
Tom Stellardc5a154d2018-06-28 23:47:12 +0000177 bool hasFminFmaxLegacy() const {
178 return HasFminFmaxLegacy;
179 }
180
181 bool isPromoteAllocaEnabled() const {
182 return EnablePromoteAlloca;
183 }
184
185 unsigned getWavefrontSize() const {
186 return WavefrontSize;
187 }
188
189 int getLocalMemorySize() const {
190 return LocalMemorySize;
191 }
192
193 unsigned getAlignmentForImplicitArgPtr() const {
194 return isAmdHsaOS() ? 8 : 4;
195 }
196
Tom Stellardec4feae2018-07-06 17:16:17 +0000197 /// Returns the offset in bytes from the start of the input buffer
198 /// of the first explicit kernel argument.
199 unsigned getExplicitKernelArgOffset(const Function &F) const {
200 return isAmdCodeObjectV2(F) ? 0 : 36;
201 }
202
Tom Stellardc5a154d2018-06-28 23:47:12 +0000203 /// \returns Maximum number of work groups per compute unit supported by the
204 /// subtarget and limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000205 virtual unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const = 0;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000206
207 /// \returns Minimum flat work group size supported by the subtarget.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000208 virtual unsigned getMinFlatWorkGroupSize() const = 0;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000209
210 /// \returns Maximum flat work group size supported by the subtarget.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000211 virtual unsigned getMaxFlatWorkGroupSize() const = 0;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000212
213 /// \returns Maximum number of waves per execution unit supported by the
214 /// subtarget and limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000215 virtual unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const = 0;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000216
217 /// \returns Minimum number of waves per execution unit supported by the
218 /// subtarget.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000219 virtual unsigned getMinWavesPerEU() const = 0;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000220
221 unsigned getMaxWavesPerEU() const { return 10; }
222
223 /// Creates value range metadata on an workitemid.* inrinsic call or load.
224 bool makeLIDRangeMetadata(Instruction *I) const;
225
Matt Arsenault4bec7d42018-07-20 09:05:08 +0000226 /// \returns Number of bytes of arguments that are passed to a shader or
227 /// kernel in addition to the explicit ones declared for the function.
228 unsigned getImplicitArgNumBytes(const Function &F) const {
229 if (isMesaKernel(F))
230 return 16;
231 return AMDGPU::getIntegerAttribute(F, "amdgpu-implicitarg-num-bytes", 0);
232 }
233 uint64_t getExplicitKernArgSize(const Function &F,
234 unsigned &MaxAlign) const;
235 unsigned getKernArgSegmentSize(const Function &F,
236 unsigned &MaxAlign) const;
237
Tom Stellard5bfbae52018-07-11 20:59:01 +0000238 virtual ~AMDGPUSubtarget() {}
Tom Stellardc5a154d2018-06-28 23:47:12 +0000239};
240
Tom Stellard5bfbae52018-07-11 20:59:01 +0000241class GCNSubtarget : public AMDGPUGenSubtargetInfo,
242 public AMDGPUSubtarget {
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000243public:
Marek Olsak4d00dd22015-03-09 15:48:09 +0000244 enum {
Tom Stellard347ac792015-06-26 21:15:07 +0000245 ISAVersion0_0_0,
Wei Ding7c3e5112017-06-10 03:53:19 +0000246 ISAVersion6_0_0,
247 ISAVersion6_0_1,
Tom Stellard347ac792015-06-26 21:15:07 +0000248 ISAVersion7_0_0,
249 ISAVersion7_0_1,
Yaxun Liu94add852016-10-26 16:37:56 +0000250 ISAVersion7_0_2,
Wei Ding7c3e5112017-06-10 03:53:19 +0000251 ISAVersion7_0_3,
Konstantin Zhuravlyovc40d9f22017-12-08 20:52:28 +0000252 ISAVersion7_0_4,
Changpeng Fangc16be002016-01-13 20:39:25 +0000253 ISAVersion8_0_1,
Changpeng Fang98317d22016-10-11 16:00:47 +0000254 ISAVersion8_0_2,
Yaxun Liu94add852016-10-26 16:37:56 +0000255 ISAVersion8_0_3,
Yaxun Liu94add852016-10-26 16:37:56 +0000256 ISAVersion8_1_0,
Matt Arsenaulte823d922017-02-18 18:29:53 +0000257 ISAVersion9_0_0,
Matt Arsenault0084adc2018-04-30 19:08:16 +0000258 ISAVersion9_0_2,
259 ISAVersion9_0_4,
Konstantin Zhuravlyov1501af42018-05-01 18:47:48 +0000260 ISAVersion9_0_6,
Tom Stellard347ac792015-06-26 21:15:07 +0000261 };
262
Wei Ding205bfdb2017-02-10 02:15:29 +0000263 enum TrapHandlerAbi {
264 TrapHandlerAbiNone = 0,
265 TrapHandlerAbiHsa = 1
266 };
267
Wei Dingf2cce022017-02-22 23:22:19 +0000268 enum TrapID {
269 TrapIDHardwareReserved = 0,
270 TrapIDHSADebugTrap = 1,
271 TrapIDLLVMTrap = 2,
272 TrapIDLLVMDebugTrap = 3,
273 TrapIDDebugBreakpoint = 7,
274 TrapIDDebugReserved8 = 8,
275 TrapIDDebugReservedFE = 0xfe,
276 TrapIDDebugReservedFF = 0xff
Wei Ding205bfdb2017-02-10 02:15:29 +0000277 };
278
279 enum TrapRegValues {
Wei Dingf2cce022017-02-22 23:22:19 +0000280 LLVMTrapHandlerRegValue = 1
Wei Ding205bfdb2017-02-10 02:15:29 +0000281 };
282
Tom Stellardc5a154d2018-06-28 23:47:12 +0000283private:
Tom Stellardc5a154d2018-06-28 23:47:12 +0000284 /// GlobalISel related APIs.
285 std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
286 std::unique_ptr<InstructionSelector> InstSelector;
287 std::unique_ptr<LegalizerInfo> Legalizer;
288 std::unique_ptr<RegisterBankInfo> RegBankInfo;
289
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000290protected:
291 // Basic subtarget description.
292 Triple TargetTriple;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000293 unsigned Gen;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000294 unsigned IsaVersion;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000295 int LDSBankCount;
296 unsigned MaxPrivateElementSize;
297
298 // Possibly statically set by tablegen, but may want to be overridden.
Matt Arsenaultb035a572015-01-29 19:34:25 +0000299 bool FastFMAF32;
Matt Arsenaulte83690c2016-01-18 21:13:50 +0000300 bool HalfRate64Ops;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000301
302 // Dynamially set bits that enable features.
Matt Arsenaulta6867fd2017-01-23 22:31:03 +0000303 bool FP64FP16Denormals;
Matt Arsenault2fdf2a12017-02-21 23:35:48 +0000304 bool DX10Clamp;
Changpeng Fangb41574a2015-12-22 20:55:23 +0000305 bool FlatForGlobal;
Konstantin Zhuravlyovbe6c0ca2017-06-02 17:40:26 +0000306 bool AutoWaitcntBeforeBarrier;
Konstantin Zhuravlyoveda425e2017-10-14 15:59:07 +0000307 bool CodeObjectV3;
Tom Stellard64a9d082016-10-14 18:10:39 +0000308 bool UnalignedScratchAccess;
Matt Arsenault7f681ac2016-07-01 23:03:44 +0000309 bool UnalignedBufferAccess;
Matt Arsenaulte823d922017-02-18 18:29:53 +0000310 bool HasApertureRegs;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000311 bool EnableXNACK;
Wei Ding205bfdb2017-02-10 02:15:29 +0000312 bool TrapHandler;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000313 bool DebuggerInsertNops;
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000314 bool DebuggerEmitPrologue;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000315
316 // Used as options.
Matt Arsenault45b98182017-11-15 00:45:43 +0000317 bool EnableHugePrivateBuffer;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000318 bool EnableVGPRSpilling;
Matt Arsenault41033282014-10-10 22:01:59 +0000319 bool EnableLoadStoreOpt;
Matt Arsenault706f9302015-07-06 16:01:58 +0000320 bool EnableUnsafeDSOffsetFolding;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000321 bool EnableSIScheduler;
Marek Olsaka9a58fa2018-04-10 22:48:23 +0000322 bool EnableDS128;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000323 bool DumpCode;
324
325 // Subtarget statically properties set by tablegen
326 bool FP64;
Jan Vesely39aeab42017-12-04 23:07:28 +0000327 bool FMA;
Dmitry Preobrazhenskye3271ae2018-02-05 12:45:43 +0000328 bool MIMG_R128;
Tom Stellardd7e6f132015-04-08 01:09:26 +0000329 bool IsGCN;
Tom Stellardd7e6f132015-04-08 01:09:26 +0000330 bool GCN3Encoding;
Tom Stellardd1f0f022015-04-23 19:33:54 +0000331 bool CIInsts;
Matt Arsenault96b67842018-08-07 07:28:46 +0000332 bool VIInsts;
Matt Arsenault2021f082017-02-18 19:12:26 +0000333 bool GFX9Insts;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000334 bool SGPRInitBug;
Matt Arsenault9d82ee72016-02-27 08:53:55 +0000335 bool HasSMemRealTime;
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000336 bool HasIntClamp;
Matt Arsenault0084adc2018-04-30 19:08:16 +0000337 bool HasFmaMixInsts;
Matt Arsenaultcc88ce32016-10-12 18:00:51 +0000338 bool HasMovrel;
339 bool HasVGPRIndexMode;
Matt Arsenault7b647552016-10-28 21:55:15 +0000340 bool HasScalarStores;
Dmitry Preobrazhensky6bad04e2018-04-02 16:10:25 +0000341 bool HasScalarAtomics;
Sam Kolton3c4933f2017-06-22 06:26:41 +0000342 bool HasSDWAOmod;
343 bool HasSDWAScalar;
344 bool HasSDWASdst;
345 bool HasSDWAMac;
Sam Koltona179d252017-06-27 15:02:23 +0000346 bool HasSDWAOutModsVOPC;
Sam Kolton07dbde22017-01-20 10:01:25 +0000347 bool HasDPP;
Ryan Taylor1f334d02018-08-28 15:07:30 +0000348 bool HasR128A16;
Matt Arsenault0084adc2018-04-30 19:08:16 +0000349 bool HasDLInsts;
Konstantin Zhuravlyovc2c2eb72018-05-04 20:06:57 +0000350 bool D16PreservesUnusedBits;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000351 bool FlatAddressSpace;
Matt Arsenaultacdc7652017-05-10 21:19:05 +0000352 bool FlatInstOffsets;
353 bool FlatGlobalInsts;
354 bool FlatScratchInsts;
Matt Arsenaultc37fe662017-07-20 17:42:47 +0000355 bool AddNoCarryInsts;
Changpeng Fang44dfa1d2018-01-12 21:12:19 +0000356 bool HasUnpackedD16VMem;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000357 bool R600ALUInst;
358 bool CaymanISA;
359 bool CFALUBug;
360 bool HasVertexCache;
361 short TexVTXClauseSize;
Alexander Timofeev18009562016-12-08 17:28:47 +0000362 bool ScalarizeGlobal;
Tom Stellard75aadc22012-12-11 21:25:42 +0000363
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000364 // Dummy feature to use for assembler in tablegen.
365 bool FeatureDisable;
366
Matt Arsenault56684d42016-08-11 17:31:42 +0000367 SelectionDAGTargetInfo TSInfo;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000368private:
Tom Stellard5bfbae52018-07-11 20:59:01 +0000369 SIInstrInfo InstrInfo;
Tom Stellard752ddbd2018-07-11 22:15:15 +0000370 SITargetLowering TLInfo;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000371 SIFrameLowering FrameLowering;
Tom Stellard75aadc22012-12-11 21:25:42 +0000372
373public:
Tom Stellard5bfbae52018-07-11 20:59:01 +0000374 GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
375 const GCNTargetMachine &TM);
376 ~GCNSubtarget() override;
Eugene Zelenko2bc2f332016-12-09 22:06:55 +0000377
Tom Stellard5bfbae52018-07-11 20:59:01 +0000378 GCNSubtarget &initializeSubtargetDependencies(const Triple &TT,
Daniel Sandersa73f1fd2015-06-10 12:11:26 +0000379 StringRef GPU, StringRef FS);
Tom Stellard75aadc22012-12-11 21:25:42 +0000380
Tom Stellard5bfbae52018-07-11 20:59:01 +0000381 const SIInstrInfo *getInstrInfo() const override {
382 return &InstrInfo;
383 }
Tom Stellard000c5af2016-04-14 19:09:28 +0000384
Tom Stellardc5a154d2018-06-28 23:47:12 +0000385 const SIFrameLowering *getFrameLowering() const override {
386 return &FrameLowering;
387 }
388
Tom Stellard5bfbae52018-07-11 20:59:01 +0000389 const SITargetLowering *getTargetLowering() const override {
390 return &TLInfo;
391 }
Tom Stellardc5a154d2018-06-28 23:47:12 +0000392
Tom Stellard5bfbae52018-07-11 20:59:01 +0000393 const SIRegisterInfo *getRegisterInfo() const override {
394 return &InstrInfo.getRegisterInfo();
395 }
Tom Stellardc5a154d2018-06-28 23:47:12 +0000396
397 const CallLowering *getCallLowering() const override {
398 return CallLoweringInfo.get();
399 }
400
401 const InstructionSelector *getInstructionSelector() const override {
402 return InstSelector.get();
403 }
404
405 const LegalizerInfo *getLegalizerInfo() const override {
406 return Legalizer.get();
407 }
408
409 const RegisterBankInfo *getRegBankInfo() const override {
410 return RegBankInfo.get();
Eric Christopherd9134482014-08-04 21:25:23 +0000411 }
Matt Arsenaultd782d052014-06-27 17:57:00 +0000412
Matt Arsenault56684d42016-08-11 17:31:42 +0000413 // Nothing implemented, just prevent crashes on use.
414 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
415 return &TSInfo;
416 }
417
Craig Topperee7b0f32014-04-30 05:53:27 +0000418 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
Tom Stellard75aadc22012-12-11 21:25:42 +0000419
Matt Arsenaultd782d052014-06-27 17:57:00 +0000420 Generation getGeneration() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000421 return (Generation)Gen;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000422 }
423
Matt Arsenault4eea3f32017-11-13 22:55:05 +0000424 unsigned getWavefrontSizeLog2() const {
425 return Log2_32(WavefrontSize);
426 }
427
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000428 int getLDSBankCount() const {
429 return LDSBankCount;
430 }
431
432 unsigned getMaxPrivateElementSize() const {
433 return MaxPrivateElementSize;
434 }
435
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000436 bool hasIntClamp() const {
437 return HasIntClamp;
438 }
439
Jan Veselyd1c9b612017-12-04 22:57:29 +0000440 bool hasFP64() const {
Matt Arsenaultd782d052014-06-27 17:57:00 +0000441 return FP64;
442 }
443
Dmitry Preobrazhenskye3271ae2018-02-05 12:45:43 +0000444 bool hasMIMG_R128() const {
445 return MIMG_R128;
446 }
447
Tom Stellardc5a154d2018-06-28 23:47:12 +0000448 bool hasHWFP64() const {
449 return FP64;
450 }
451
Matt Arsenaultb035a572015-01-29 19:34:25 +0000452 bool hasFastFMAF32() const {
453 return FastFMAF32;
454 }
455
Matt Arsenaulte83690c2016-01-18 21:13:50 +0000456 bool hasHalfRate64Ops() const {
457 return HalfRate64Ops;
458 }
459
Matt Arsenault88701812016-06-09 23:42:48 +0000460 bool hasAddr64() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000461 return (getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS);
Matt Arsenault88701812016-06-09 23:42:48 +0000462 }
463
Matt Arsenaultfae02982014-03-17 18:58:11 +0000464 bool hasBFE() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000465 return true;
Matt Arsenaultfae02982014-03-17 18:58:11 +0000466 }
467
Matt Arsenault6e439652014-06-10 19:00:20 +0000468 bool hasBFI() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000469 return true;
Matt Arsenault6e439652014-06-10 19:00:20 +0000470 }
471
Matt Arsenaultfae02982014-03-17 18:58:11 +0000472 bool hasBFM() const {
473 return hasBFE();
474 }
475
Matt Arsenault60425062014-06-10 19:18:28 +0000476 bool hasBCNT(unsigned Size) const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000477 return true;
Tom Stellard50122a52014-04-07 19:45:41 +0000478 }
479
Jan Vesely6ddb8dd2014-07-15 15:51:09 +0000480 bool hasFFBL() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000481 return true;
Jan Vesely6ddb8dd2014-07-15 15:51:09 +0000482 }
483
484 bool hasFFBH() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000485 return true;
Jan Vesely6ddb8dd2014-07-15 15:51:09 +0000486 }
487
Matt Arsenault10268f92017-02-27 22:40:39 +0000488 bool hasMed3_16() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000489 return getGeneration() >= AMDGPUSubtarget::GFX9;
Matt Arsenault10268f92017-02-27 22:40:39 +0000490 }
491
Matt Arsenaultee324ff2017-05-17 19:25:06 +0000492 bool hasMin3Max3_16() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000493 return getGeneration() >= AMDGPUSubtarget::GFX9;
Matt Arsenaultd7e23032017-09-07 18:05:07 +0000494 }
495
Matt Arsenault0084adc2018-04-30 19:08:16 +0000496 bool hasFmaMixInsts() const {
497 return HasFmaMixInsts;
498 }
499
Jan Vesely808fff52015-04-30 17:15:56 +0000500 bool hasCARRY() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000501 return true;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000502 }
503
Jan Vesely39aeab42017-12-04 23:07:28 +0000504 bool hasFMA() const {
505 return FMA;
506 }
507
Wei Ding205bfdb2017-02-10 02:15:29 +0000508 TrapHandlerAbi getTrapHandlerAbi() const {
509 return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
510 }
511
Matt Arsenault45b98182017-11-15 00:45:43 +0000512 bool enableHugePrivateBuffer() const {
513 return EnableHugePrivateBuffer;
514 }
515
Matt Arsenault706f9302015-07-06 16:01:58 +0000516 bool unsafeDSOffsetFoldingEnabled() const {
517 return EnableUnsafeDSOffsetFolding;
518 }
519
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000520 bool dumpCode() const {
521 return DumpCode;
Matt Arsenaultd782d052014-06-27 17:57:00 +0000522 }
523
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000524 /// Return the amount of LDS that can be used that will not restrict the
525 /// occupancy lower than WaveCount.
Stanislav Mekhanoshin2b913b12017-02-01 22:59:50 +0000526 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
527 const Function &) const;
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000528
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000529 bool hasFP16Denormals() const {
Matt Arsenaulta6867fd2017-01-23 22:31:03 +0000530 return FP64FP16Denormals;
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000531 }
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000532
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000533 bool hasFP64Denormals() const {
Matt Arsenaulta6867fd2017-01-23 22:31:03 +0000534 return FP64FP16Denormals;
Matt Arsenault24ee0782016-02-12 02:40:47 +0000535 }
536
Stanislav Mekhanoshindc2890a2017-07-13 23:59:15 +0000537 bool supportsMinMaxDenormModes() const {
538 return getGeneration() >= AMDGPUSubtarget::GFX9;
539 }
540
Matt Arsenault2fdf2a12017-02-21 23:35:48 +0000541 bool enableDX10Clamp() const {
542 return DX10Clamp;
543 }
544
545 bool enableIEEEBit(const MachineFunction &MF) const {
Matthias Braunf1caa282017-12-15 22:22:58 +0000546 return AMDGPU::isCompute(MF.getFunction().getCallingConv());
Matt Arsenault2fdf2a12017-02-21 23:35:48 +0000547 }
548
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000549 bool useFlatForGlobal() const {
550 return FlatForGlobal;
Tom Stellardec87f842015-05-25 16:15:54 +0000551 }
552
Farhana Aleena7cb3112018-03-09 17:41:39 +0000553 /// \returns If target supports ds_read/write_b128 and user enables generation
554 /// of ds_read/write_b128.
Marek Olsaka9a58fa2018-04-10 22:48:23 +0000555 bool useDS128() const {
556 return CIInsts && EnableDS128;
Farhana Aleena7cb3112018-03-09 17:41:39 +0000557 }
558
Matt Arsenaultcaf0ed42017-11-30 00:52:40 +0000559 /// \returns If MUBUF instructions always perform range checking, even for
560 /// buffer resources used for private memory access.
561 bool privateMemoryResourceIsRangeChecked() const {
562 return getGeneration() < AMDGPUSubtarget::GFX9;
563 }
564
Konstantin Zhuravlyovbe6c0ca2017-06-02 17:40:26 +0000565 bool hasAutoWaitcntBeforeBarrier() const {
566 return AutoWaitcntBeforeBarrier;
567 }
568
Konstantin Zhuravlyoveda425e2017-10-14 15:59:07 +0000569 bool hasCodeObjectV3() const {
570 return CodeObjectV3;
571 }
572
Matt Arsenault7f681ac2016-07-01 23:03:44 +0000573 bool hasUnalignedBufferAccess() const {
574 return UnalignedBufferAccess;
575 }
576
Tom Stellard64a9d082016-10-14 18:10:39 +0000577 bool hasUnalignedScratchAccess() const {
578 return UnalignedScratchAccess;
579 }
580
Matt Arsenaulte823d922017-02-18 18:29:53 +0000581 bool hasApertureRegs() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000582 return HasApertureRegs;
Matt Arsenaulte823d922017-02-18 18:29:53 +0000583 }
584
Wei Ding205bfdb2017-02-10 02:15:29 +0000585 bool isTrapHandlerEnabled() const {
586 return TrapHandler;
587 }
588
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000589 bool isXNACKEnabled() const {
590 return EnableXNACK;
591 }
Tom Stellardb8fd6ef2014-12-02 22:00:07 +0000592
Matt Arsenaultb6491cc2017-01-31 01:20:54 +0000593 bool hasFlatAddressSpace() const {
594 return FlatAddressSpace;
595 }
596
Matt Arsenaultacdc7652017-05-10 21:19:05 +0000597 bool hasFlatInstOffsets() const {
598 return FlatInstOffsets;
599 }
600
601 bool hasFlatGlobalInsts() const {
602 return FlatGlobalInsts;
603 }
604
605 bool hasFlatScratchInsts() const {
606 return FlatScratchInsts;
607 }
608
Mark Searlesf0b93f12018-06-04 16:51:59 +0000609 bool hasFlatLgkmVMemCountInOrder() const {
610 return getGeneration() > GFX9;
611 }
612
Matt Arsenaulted6e8f02017-09-01 18:36:06 +0000613 bool hasD16LoadStore() const {
614 return getGeneration() >= GFX9;
615 }
616
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000617 /// Return if most LDS instructions have an m0 use that require m0 to be
618 /// iniitalized.
619 bool ldsRequiresM0Init() const {
620 return getGeneration() < GFX9;
621 }
622
Matt Arsenaultc37fe662017-07-20 17:42:47 +0000623 bool hasAddNoCarry() const {
624 return AddNoCarryInsts;
625 }
626
Changpeng Fang44dfa1d2018-01-12 21:12:19 +0000627 bool hasUnpackedD16VMem() const {
628 return HasUnpackedD16VMem;
629 }
630
Tom Stellard2f3f9852017-01-25 01:25:13 +0000631 // Covers VS/PS/CS graphics shaders
Matt Arsenaultceafc552018-05-29 17:42:50 +0000632 bool isMesaGfxShader(const Function &F) const {
633 return isMesa3DOS() && AMDGPU::isShader(F.getCallingConv());
Tom Stellard2f3f9852017-01-25 01:25:13 +0000634 }
635
Matt Arsenault4f6318f2017-11-06 17:04:37 +0000636 bool hasMad64_32() const {
637 return getGeneration() >= SEA_ISLANDS;
638 }
639
Sam Kolton3c4933f2017-06-22 06:26:41 +0000640 bool hasSDWAOmod() const {
641 return HasSDWAOmod;
642 }
643
644 bool hasSDWAScalar() const {
645 return HasSDWAScalar;
646 }
647
648 bool hasSDWASdst() const {
649 return HasSDWASdst;
650 }
651
652 bool hasSDWAMac() const {
653 return HasSDWAMac;
654 }
655
Sam Koltona179d252017-06-27 15:02:23 +0000656 bool hasSDWAOutModsVOPC() const {
657 return HasSDWAOutModsVOPC;
Sam Kolton3c4933f2017-06-22 06:26:41 +0000658 }
659
Mark Searles2a19af62018-04-26 16:11:19 +0000660 bool vmemWriteNeedsExpWaitcnt() const {
661 return getGeneration() < SEA_ISLANDS;
662 }
663
Matt Arsenault0084adc2018-04-30 19:08:16 +0000664 bool hasDLInsts() const {
665 return HasDLInsts;
666 }
667
Konstantin Zhuravlyovc2c2eb72018-05-04 20:06:57 +0000668 bool d16PreservesUnusedBits() const {
669 return D16PreservesUnusedBits;
670 }
671
Matt Arsenault869fec22017-04-17 19:48:24 +0000672 // Scratch is allocated in 256 dword per wave blocks for the entire
673 // wavefront. When viewed from the perspecive of an arbitrary workitem, this
674 // is 4-byte aligned.
Matt Arsenaultffb132e2018-03-29 20:22:04 +0000675 //
676 // Only 4-byte alignment is really needed to access anything. Transformations
677 // on the pointer value itself may rely on the alignment / known low bits of
678 // the pointer. Set this to something above the minimum to avoid needing
679 // dynamic realignment in common cases.
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000680 unsigned getStackAlignment() const {
Matt Arsenaultffb132e2018-03-29 20:22:04 +0000681 return 16;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000682 }
Tom Stellard347ac792015-06-26 21:15:07 +0000683
Craig Topper5656db42014-04-29 07:57:24 +0000684 bool enableMachineScheduler() const override {
Tom Stellard83f0bce2015-01-29 16:55:25 +0000685 return true;
Andrew Trick978674b2013-09-20 05:14:41 +0000686 }
687
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000688 bool enableSubRegLiveness() const override {
689 return true;
690 }
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000691
Tom Stellardc5a154d2018-06-28 23:47:12 +0000692 void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b; }
693 bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal; }
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000694
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000695 /// \returns Number of execution units per compute unit supported by the
696 /// subtarget.
697 unsigned getEUsPerCU() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000698 return AMDGPU::IsaInfo::getEUsPerCU(this);
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000699 }
700
701 /// \returns Maximum number of waves per compute unit supported by the
702 /// subtarget without any kind of limitation.
703 unsigned getMaxWavesPerCU() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000704 return AMDGPU::IsaInfo::getMaxWavesPerCU(this);
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000705 }
706
707 /// \returns Maximum number of waves per compute unit supported by the
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000708 /// subtarget and limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000709 unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000710 return AMDGPU::IsaInfo::getMaxWavesPerCU(this, FlatWorkGroupSize);
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000711 }
712
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000713 /// \returns Maximum number of waves per execution unit supported by the
714 /// subtarget without any kind of limitation.
715 unsigned getMaxWavesPerEU() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000716 return AMDGPU::IsaInfo::getMaxWavesPerEU();
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000717 }
718
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000719 /// \returns Number of waves per work group supported by the subtarget and
720 /// limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000721 unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000722 return AMDGPU::IsaInfo::getWavesPerWorkGroup(this, FlatWorkGroupSize);
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000723 }
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000724
Tom Stellardc5a154d2018-06-28 23:47:12 +0000725 // static wrappers
726 static bool hasHalfRate64Ops(const TargetSubtargetInfo &STI);
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000727
Matt Arsenault9f5e0ef2017-01-25 04:25:02 +0000728 // XXX - Why is this here if it isn't in the default pass set?
729 bool enableEarlyIfConversion() const override {
730 return true;
731 }
732
Tom Stellard83f0bce2015-01-29 16:55:25 +0000733 void overrideSchedPolicy(MachineSchedPolicy &Policy,
Tom Stellard83f0bce2015-01-29 16:55:25 +0000734 unsigned NumRegionInstrs) const override;
735
Tom Stellardc5a154d2018-06-28 23:47:12 +0000736 bool isVGPRSpillingEnabled(const Function &F) const;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000737
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000738 unsigned getMaxNumUserSGPRs() const {
739 return 16;
740 }
741
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000742 bool hasSMemRealTime() const {
743 return HasSMemRealTime;
744 }
745
Matt Arsenaultcc88ce32016-10-12 18:00:51 +0000746 bool hasMovrel() const {
747 return HasMovrel;
748 }
749
750 bool hasVGPRIndexMode() const {
751 return HasVGPRIndexMode;
752 }
753
Marek Olsake22fdb92017-03-21 17:00:32 +0000754 bool useVGPRIndexMode(bool UserEnable) const {
755 return !hasMovrel() || (UserEnable && hasVGPRIndexMode());
756 }
757
Matt Arsenault7b1dc2c2016-09-17 02:02:19 +0000758 bool hasScalarCompareEq64() const {
759 return getGeneration() >= VOLCANIC_ISLANDS;
760 }
761
Matt Arsenault7b647552016-10-28 21:55:15 +0000762 bool hasScalarStores() const {
763 return HasScalarStores;
764 }
765
Dmitry Preobrazhensky6bad04e2018-04-02 16:10:25 +0000766 bool hasScalarAtomics() const {
767 return HasScalarAtomics;
768 }
769
Matt Arsenaultc88ba362016-10-29 04:05:06 +0000770
Sam Kolton07dbde22017-01-20 10:01:25 +0000771 bool hasDPP() const {
772 return HasDPP;
773 }
774
Ryan Taylor1f334d02018-08-28 15:07:30 +0000775 bool hasR128A16() const {
776 return HasR128A16;
777 }
778
Tom Stellardde008d32016-01-21 04:28:34 +0000779 bool enableSIScheduler() const {
780 return EnableSIScheduler;
781 }
782
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000783 bool debuggerSupported() const {
Konstantin Zhuravlyove004b3d2018-06-21 20:28:19 +0000784 return debuggerInsertNops() && debuggerEmitPrologue();
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000785 }
786
Konstantin Zhuravlyov8c273ad2016-04-18 16:28:23 +0000787 bool debuggerInsertNops() const {
788 return DebuggerInsertNops;
789 }
790
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000791 bool debuggerEmitPrologue() const {
792 return DebuggerEmitPrologue;
793 }
794
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000795 bool loadStoreOptEnabled() const {
796 return EnableLoadStoreOpt;
Nicolai Haehnle5b504972016-01-04 23:35:53 +0000797 }
798
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000799 bool hasSGPRInitBug() const {
800 return SGPRInitBug;
Matt Arsenault41003af2015-11-30 21:16:07 +0000801 }
Tom Stellard0d23ebe2016-08-29 19:42:52 +0000802
Tom Stellardb133fbb2016-10-27 23:05:31 +0000803 bool has12DWordStoreHazard() const {
804 return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
805 }
806
Matt Arsenaulte823d922017-02-18 18:29:53 +0000807 bool hasSMovFedHazard() const {
808 return getGeneration() >= AMDGPUSubtarget::GFX9;
809 }
810
Matt Arsenaulta41351e2017-11-17 21:35:32 +0000811 bool hasReadM0MovRelInterpHazard() const {
Matt Arsenaulte823d922017-02-18 18:29:53 +0000812 return getGeneration() >= AMDGPUSubtarget::GFX9;
813 }
814
Matt Arsenaulta41351e2017-11-17 21:35:32 +0000815 bool hasReadM0SendMsgHazard() const {
816 return getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
817 }
818
Tom Stellardc5a154d2018-06-28 23:47:12 +0000819 /// Return the maximum number of waves per SIMD for kernels using \p SGPRs
820 /// SGPRs
Tom Stellard0d23ebe2016-08-29 19:42:52 +0000821 unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
822
Tom Stellardc5a154d2018-06-28 23:47:12 +0000823 /// Return the maximum number of waves per SIMD for kernels using \p VGPRs
824 /// VGPRs
Tom Stellard0d23ebe2016-08-29 19:42:52 +0000825 unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
Konstantin Zhuravlyovd7bdf242016-09-30 16:50:36 +0000826
Matt Arsenaulte823d922017-02-18 18:29:53 +0000827 /// \returns true if the flat_scratch register should be initialized with the
828 /// pointer to the wave's scratch memory rather than a size and offset.
829 bool flatScratchIsPointer() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000830 return getGeneration() >= AMDGPUSubtarget::GFX9;
Konstantin Zhuravlyovd7bdf242016-09-30 16:50:36 +0000831 }
Matt Arsenault4eae3012016-10-28 20:31:47 +0000832
Tim Renouf832f90f2018-02-26 14:46:43 +0000833 /// \returns true if the machine has merged shaders in which s0-s7 are
834 /// reserved by the hardware and user SGPRs start at s8
835 bool hasMergedShaders() const {
836 return getGeneration() >= GFX9;
837 }
838
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000839 /// \returns SGPR allocation granularity supported by the subtarget.
840 unsigned getSGPRAllocGranule() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000841 return AMDGPU::IsaInfo::getSGPRAllocGranule(this);
Konstantin Zhuravlyove22fbcb2017-02-08 13:18:40 +0000842 }
843
844 /// \returns SGPR encoding granularity supported by the subtarget.
845 unsigned getSGPREncodingGranule() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000846 return AMDGPU::IsaInfo::getSGPREncodingGranule(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000847 }
848
849 /// \returns Total number of SGPRs supported by the subtarget.
850 unsigned getTotalNumSGPRs() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000851 return AMDGPU::IsaInfo::getTotalNumSGPRs(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000852 }
853
854 /// \returns Addressable number of SGPRs supported by the subtarget.
855 unsigned getAddressableNumSGPRs() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000856 return AMDGPU::IsaInfo::getAddressableNumSGPRs(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000857 }
858
859 /// \returns Minimum number of SGPRs that meets the given number of waves per
860 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000861 unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000862 return AMDGPU::IsaInfo::getMinNumSGPRs(this, WavesPerEU);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000863 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000864
865 /// \returns Maximum number of SGPRs that meets the given number of waves per
866 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000867 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000868 return AMDGPU::IsaInfo::getMaxNumSGPRs(this, WavesPerEU, Addressable);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000869 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000870
871 /// \returns Reserved number of SGPRs for given function \p MF.
872 unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
873
874 /// \returns Maximum number of SGPRs that meets number of waves per execution
875 /// unit requirement for function \p MF, or number of SGPRs explicitly
876 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
877 ///
878 /// \returns Value that meets number of waves per execution unit requirement
879 /// if explicitly requested value cannot be converted to integer, violates
880 /// subtarget's specifications, or does not meet number of waves per execution
881 /// unit requirement.
882 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
883
884 /// \returns VGPR allocation granularity supported by the subtarget.
885 unsigned getVGPRAllocGranule() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000886 return AMDGPU::IsaInfo::getVGPRAllocGranule(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000887 }
888
Konstantin Zhuravlyove22fbcb2017-02-08 13:18:40 +0000889 /// \returns VGPR encoding granularity supported by the subtarget.
890 unsigned getVGPREncodingGranule() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000891 return AMDGPU::IsaInfo::getVGPREncodingGranule(this);
Konstantin Zhuravlyove22fbcb2017-02-08 13:18:40 +0000892 }
893
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000894 /// \returns Total number of VGPRs supported by the subtarget.
895 unsigned getTotalNumVGPRs() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000896 return AMDGPU::IsaInfo::getTotalNumVGPRs(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000897 }
898
899 /// \returns Addressable number of VGPRs supported by the subtarget.
900 unsigned getAddressableNumVGPRs() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000901 return AMDGPU::IsaInfo::getAddressableNumVGPRs(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000902 }
903
904 /// \returns Minimum number of VGPRs that meets given number of waves per
905 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000906 unsigned getMinNumVGPRs(unsigned WavesPerEU) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000907 return AMDGPU::IsaInfo::getMinNumVGPRs(this, WavesPerEU);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000908 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000909
910 /// \returns Maximum number of VGPRs that meets given number of waves per
911 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000912 unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000913 return AMDGPU::IsaInfo::getMaxNumVGPRs(this, WavesPerEU);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000914 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000915
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000916 /// \returns Maximum number of VGPRs that meets number of waves per execution
917 /// unit requirement for function \p MF, or number of VGPRs explicitly
918 /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
919 ///
920 /// \returns Value that meets number of waves per execution unit requirement
921 /// if explicitly requested value cannot be converted to integer, violates
922 /// subtarget's specifications, or does not meet number of waves per execution
923 /// unit requirement.
924 unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
Stanislav Mekhanoshind4ae4702017-09-19 20:54:38 +0000925
926 void getPostRAMutations(
927 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
928 const override;
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000929
930 /// \returns Maximum number of work groups per compute unit supported by the
931 /// subtarget and limited by given \p FlatWorkGroupSize.
932 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
933 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);
934 }
935
936 /// \returns Minimum flat work group size supported by the subtarget.
937 unsigned getMinFlatWorkGroupSize() const override {
938 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this);
939 }
940
941 /// \returns Maximum flat work group size supported by the subtarget.
942 unsigned getMaxFlatWorkGroupSize() const override {
943 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this);
944 }
945
946 /// \returns Maximum number of waves per execution unit supported by the
947 /// subtarget and limited by given \p FlatWorkGroupSize.
948 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const override {
949 return AMDGPU::IsaInfo::getMaxWavesPerEU(this, FlatWorkGroupSize);
950 }
951
952 /// \returns Minimum number of waves per execution unit supported by the
953 /// subtarget.
954 unsigned getMinWavesPerEU() const override {
955 return AMDGPU::IsaInfo::getMinWavesPerEU(this);
956 }
Tom Stellard75aadc22012-12-11 21:25:42 +0000957};
958
Tom Stellardc5a154d2018-06-28 23:47:12 +0000959class R600Subtarget final : public R600GenSubtargetInfo,
Tom Stellard5bfbae52018-07-11 20:59:01 +0000960 public AMDGPUSubtarget {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000961private:
962 R600InstrInfo InstrInfo;
963 R600FrameLowering FrameLowering;
964 bool FMA;
965 bool CaymanISA;
966 bool CFALUBug;
967 bool DX10Clamp;
968 bool HasVertexCache;
969 bool R600ALUInst;
970 bool FP64;
971 short TexVTXClauseSize;
972 Generation Gen;
973 R600TargetLowering TLInfo;
974 InstrItineraryData InstrItins;
975 SelectionDAGTargetInfo TSInfo;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000976
977public:
978 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
979 const TargetMachine &TM);
980
981 const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }
982
983 const R600FrameLowering *getFrameLowering() const override {
984 return &FrameLowering;
985 }
986
987 const R600TargetLowering *getTargetLowering() const override {
988 return &TLInfo;
989 }
990
991 const R600RegisterInfo *getRegisterInfo() const override {
992 return &InstrInfo.getRegisterInfo();
993 }
994
995 const InstrItineraryData *getInstrItineraryData() const override {
996 return &InstrItins;
997 }
998
999 // Nothing implemented, just prevent crashes on use.
1000 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
1001 return &TSInfo;
1002 }
1003
1004 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
1005
1006 Generation getGeneration() const {
1007 return Gen;
1008 }
1009
1010 unsigned getStackAlignment() const {
1011 return 4;
1012 }
1013
1014 R600Subtarget &initializeSubtargetDependencies(const Triple &TT,
1015 StringRef GPU, StringRef FS);
1016
1017 bool hasBFE() const {
1018 return (getGeneration() >= EVERGREEN);
1019 }
1020
1021 bool hasBFI() const {
1022 return (getGeneration() >= EVERGREEN);
1023 }
1024
1025 bool hasBCNT(unsigned Size) const {
1026 if (Size == 32)
1027 return (getGeneration() >= EVERGREEN);
1028
1029 return false;
1030 }
1031
1032 bool hasBORROW() const {
1033 return (getGeneration() >= EVERGREEN);
1034 }
1035
1036 bool hasCARRY() const {
1037 return (getGeneration() >= EVERGREEN);
1038 }
1039
1040 bool hasCaymanISA() const {
1041 return CaymanISA;
1042 }
1043
1044 bool hasFFBL() const {
1045 return (getGeneration() >= EVERGREEN);
1046 }
1047
1048 bool hasFFBH() const {
1049 return (getGeneration() >= EVERGREEN);
1050 }
1051
1052 bool hasFMA() const { return FMA; }
1053
Tom Stellardc5a154d2018-06-28 23:47:12 +00001054 bool hasCFAluBug() const { return CFALUBug; }
1055
1056 bool hasVertexCache() const { return HasVertexCache; }
1057
1058 short getTexVTXClauseSize() const { return TexVTXClauseSize; }
1059
Tom Stellardc5a154d2018-06-28 23:47:12 +00001060 bool enableMachineScheduler() const override {
1061 return true;
1062 }
1063
1064 bool enableSubRegLiveness() const override {
1065 return true;
1066 }
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +00001067
1068 /// \returns Maximum number of work groups per compute unit supported by the
1069 /// subtarget and limited by given \p FlatWorkGroupSize.
1070 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
1071 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);
1072 }
1073
1074 /// \returns Minimum flat work group size supported by the subtarget.
1075 unsigned getMinFlatWorkGroupSize() const override {
1076 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this);
1077 }
1078
1079 /// \returns Maximum flat work group size supported by the subtarget.
1080 unsigned getMaxFlatWorkGroupSize() const override {
1081 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this);
1082 }
1083
1084 /// \returns Maximum number of waves per execution unit supported by the
1085 /// subtarget and limited by given \p FlatWorkGroupSize.
1086 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const override {
1087 return AMDGPU::IsaInfo::getMaxWavesPerEU(this, FlatWorkGroupSize);
1088 }
1089
1090 /// \returns Minimum number of waves per execution unit supported by the
1091 /// subtarget.
1092 unsigned getMinWavesPerEU() const override {
1093 return AMDGPU::IsaInfo::getMinWavesPerEU(this);
1094 }
Tom Stellardc5a154d2018-06-28 23:47:12 +00001095};
1096
Eugene Zelenko2bc2f332016-12-09 22:06:55 +00001097} // end namespace llvm
Tom Stellard75aadc22012-12-11 21:25:42 +00001098
Eugene Zelenko2bc2f332016-12-09 22:06:55 +00001099#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H