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gerrit-public.fairphone.software / toolchain / llvm-project / 81b645a76b2129f9645273e7e6a13c458d0ddcf9 / . / llvm / lib / Target / Sparc / SparcInstrInfo.td
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Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Sparc instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Instruction format superclass
16//===----------------------------------------------------------------------===//
17
18include "SparcInstrFormats.td"
19
20//===----------------------------------------------------------------------===//
21// Feature predicates.
22//===----------------------------------------------------------------------===//
23
24// HasV9 - This predicate is true when the target processor supports V9
25// instructions. Note that the machine may be running in 32-bit mode.
26def HasV9 : Predicate<"Subtarget.isV9()">;
27
28// HasNoV9 - This predicate is true when the target doesn't have V9
29// instructions. Use of this is just a hack for the isel not having proper
30// costs for V8 instructions that are more expensive than their V9 ones.
31def HasNoV9 : Predicate<"!Subtarget.isV9()">;
32
33// HasVIS - This is true when the target processor has VIS extensions.
34def HasVIS : Predicate<"Subtarget.isVIS()">;
35
36// UseDeprecatedInsts - This predicate is true when the target processor is a
37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
38// to use when appropriate. In either of these cases, the instruction selector
39// will pick deprecated instructions.
40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
41
42//===----------------------------------------------------------------------===//
43// Instruction Pattern Stuff
44//===----------------------------------------------------------------------===//
45
46def simm11 : PatLeaf<(imm), [{
47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field.
48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
49}]>;
50
51def simm13 : PatLeaf<(imm), [{
52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
54}]>;
55
56def LO10 : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
58}]>;
59
60def HI22 : SDNodeXForm<imm, [{
61 // Transformation function: shift the immediate value down into the low bits.
62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
63}]>;
64
65def SETHIimm : PatLeaf<(imm), [{
66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
67}], HI22>;
68
69// Addressing modes.
70def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
Chris Lattnerfcb8a3a2006-02-10 07:35:42 +0000[diff] [blame]71def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]72
73// Address operands
74def MEMrr : Operand<i32> {
75 let PrintMethod = "printMemOperand";
76 let NumMIOperands = 2;
77 let MIOperandInfo = (ops IntRegs, IntRegs);
78}
79def MEMri : Operand<i32> {
80 let PrintMethod = "printMemOperand";
81 let NumMIOperands = 2;
82 let MIOperandInfo = (ops IntRegs, i32imm);
83}
84
85// Branch targets have OtherVT type.
86def brtarget : Operand<OtherVT>;
87def calltarget : Operand<i32>;
88
89// Operand for printing out a condition code.
90let PrintMethod = "printCCOperand" in
91 def CCOp : Operand<i32>;
92
93def SDTSPcmpfcc :
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]94SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]95def SDTSPbrcc :
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]96SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]97def SDTSPselectcc :
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]98SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]99def SDTSPFTOI :
100SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
101def SDTSPITOF :
102SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
103
104def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
105def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>;
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]106def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
107def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]108
109def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
110def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
111
112def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
113def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
114
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]115def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>;
116def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]117
118// These are target-independent nodes, but have target-specific formats.
119def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
Evan Cheng81b645a2006-08-11 09:03:33 +0000[diff] [blame^]120def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq,
121 [SDNPHasChain, SDNPOutFlag]>;
122def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq,
123 [SDNPHasChain, SDNPOutFlag]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]124
125def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
126def call : SDNode<"SPISD::CALL", SDT_SPCall,
127 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
128
129def SDT_SPRetFlag : SDTypeProfile<0, 0, []>;
130def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag,
131 [SDNPHasChain, SDNPOptInFlag]>;
132
133//===----------------------------------------------------------------------===//
134// SPARC Flag Conditions
135//===----------------------------------------------------------------------===//
136
137// Note that these values must be kept in sync with the CCOp::CondCode enum
138// values.
139class ICC_VAL<int N> : PatLeaf<(i32 N)>;
140def ICC_NE : ICC_VAL< 9>; // Not Equal
141def ICC_E : ICC_VAL< 1>; // Equal
142def ICC_G : ICC_VAL<10>; // Greater
143def ICC_LE : ICC_VAL< 2>; // Less or Equal
144def ICC_GE : ICC_VAL<11>; // Greater or Equal
145def ICC_L : ICC_VAL< 3>; // Less
146def ICC_GU : ICC_VAL<12>; // Greater Unsigned
147def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
148def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
149def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
150def ICC_POS : ICC_VAL<14>; // Positive
151def ICC_NEG : ICC_VAL< 6>; // Negative
152def ICC_VC : ICC_VAL<15>; // Overflow Clear
153def ICC_VS : ICC_VAL< 7>; // Overflow Set
154
155class FCC_VAL<int N> : PatLeaf<(i32 N)>;
156def FCC_U : FCC_VAL<23>; // Unordered
157def FCC_G : FCC_VAL<22>; // Greater
158def FCC_UG : FCC_VAL<21>; // Unordered or Greater
159def FCC_L : FCC_VAL<20>; // Less
160def FCC_UL : FCC_VAL<19>; // Unordered or Less
161def FCC_LG : FCC_VAL<18>; // Less or Greater
162def FCC_NE : FCC_VAL<17>; // Not Equal
163def FCC_E : FCC_VAL<25>; // Equal
164def FCC_UE : FCC_VAL<24>; // Unordered or Equal
165def FCC_GE : FCC_VAL<25>; // Greater or Equal
166def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
167def FCC_LE : FCC_VAL<27>; // Less or Equal
168def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
169def FCC_O : FCC_VAL<29>; // Ordered
170
171
172//===----------------------------------------------------------------------===//
173// Instructions
174//===----------------------------------------------------------------------===//
175
176// Pseudo instructions.
177class Pseudo<dag ops, string asmstr, list<dag> pattern>
178 : InstSP<ops, asmstr, pattern>;
179
180def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
181 "!ADJCALLSTACKDOWN $amt",
182 [(callseq_start imm:$amt)]>;
183def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
184 "!ADJCALLSTACKUP $amt",
185 [(callseq_end imm:$amt)]>;
186def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
187 "!IMPLICIT_DEF $dst",
188 [(set IntRegs:$dst, (undef))]>;
189def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
190 [(set FPRegs:$dst, (undef))]>;
191def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
192 [(set DFPRegs:$dst, (undef))]>;
193
194// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
195// fpmover pass.
Chris Lattner747cf602006-02-21 18:04:32 +0000[diff] [blame]196let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]197 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
198 "!FpMOVD $src, $dst", []>;
199 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
200 "!FpNEGD $src, $dst",
201 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
202 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
203 "!FpABSD $src, $dst",
204 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
205}
206
207// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
208// scheduler into a branch sequence. This has to handle all permutations of
209// selection between i32/f32/f64 on ICC and FCC.
Chris Lattner747cf602006-02-21 18:04:32 +0000[diff] [blame]210let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]211 def SELECT_CC_Int_ICC
212 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
213 "; SELECT_CC_Int_ICC PSEUDO!",
214 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]215 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]216 def SELECT_CC_Int_FCC
217 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
218 "; SELECT_CC_Int_FCC PSEUDO!",
219 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]220 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]221 def SELECT_CC_FP_ICC
222 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
223 "; SELECT_CC_FP_ICC PSEUDO!",
224 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]225 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]226 def SELECT_CC_FP_FCC
227 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
228 "; SELECT_CC_FP_FCC PSEUDO!",
229 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]230 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]231 def SELECT_CC_DFP_ICC
232 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
233 "; SELECT_CC_DFP_ICC PSEUDO!",
234 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]235 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]236 def SELECT_CC_DFP_FCC
237 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
238 "; SELECT_CC_DFP_FCC PSEUDO!",
239 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]240 imm:$Cond))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]241}
242
243
244// Section A.3 - Synthetic Instructions, p. 85
245// special cases of JMPL:
246let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
247 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
248 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
249}
250
251// Section B.1 - Load Integer Instructions, p. 90
252def LDSBrr : F3_1<3, 0b001001,
253 (ops IntRegs:$dst, MEMrr:$addr),
254 "ldsb [$addr], $dst",
255 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
256def LDSBri : F3_2<3, 0b001001,
257 (ops IntRegs:$dst, MEMri:$addr),
258 "ldsb [$addr], $dst",
259 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
260def LDSHrr : F3_1<3, 0b001010,
261 (ops IntRegs:$dst, MEMrr:$addr),
262 "ldsh [$addr], $dst",
263 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
264def LDSHri : F3_2<3, 0b001010,
265 (ops IntRegs:$dst, MEMri:$addr),
266 "ldsh [$addr], $dst",
267 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
268def LDUBrr : F3_1<3, 0b000001,
269 (ops IntRegs:$dst, MEMrr:$addr),
270 "ldub [$addr], $dst",
271 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
272def LDUBri : F3_2<3, 0b000001,
273 (ops IntRegs:$dst, MEMri:$addr),
274 "ldub [$addr], $dst",
275 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
276def LDUHrr : F3_1<3, 0b000010,
277 (ops IntRegs:$dst, MEMrr:$addr),
278 "lduh [$addr], $dst",
279 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
280def LDUHri : F3_2<3, 0b000010,
281 (ops IntRegs:$dst, MEMri:$addr),
282 "lduh [$addr], $dst",
283 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
284def LDrr : F3_1<3, 0b000000,
285 (ops IntRegs:$dst, MEMrr:$addr),
286 "ld [$addr], $dst",
287 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
288def LDri : F3_2<3, 0b000000,
289 (ops IntRegs:$dst, MEMri:$addr),
290 "ld [$addr], $dst",
291 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
292
293// Section B.2 - Load Floating-point Instructions, p. 92
294def LDFrr : F3_1<3, 0b100000,
295 (ops FPRegs:$dst, MEMrr:$addr),
296 "ld [$addr], $dst",
297 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
298def LDFri : F3_2<3, 0b100000,
299 (ops FPRegs:$dst, MEMri:$addr),
300 "ld [$addr], $dst",
301 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
302def LDDFrr : F3_1<3, 0b100011,
303 (ops DFPRegs:$dst, MEMrr:$addr),
304 "ldd [$addr], $dst",
305 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
306def LDDFri : F3_2<3, 0b100011,
307 (ops DFPRegs:$dst, MEMri:$addr),
308 "ldd [$addr], $dst",
309 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
310
311// Section B.4 - Store Integer Instructions, p. 95
312def STBrr : F3_1<3, 0b000101,
313 (ops MEMrr:$addr, IntRegs:$src),
314 "stb $src, [$addr]",
315 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
316def STBri : F3_2<3, 0b000101,
317 (ops MEMri:$addr, IntRegs:$src),
318 "stb $src, [$addr]",
319 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
320def STHrr : F3_1<3, 0b000110,
321 (ops MEMrr:$addr, IntRegs:$src),
322 "sth $src, [$addr]",
323 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
324def STHri : F3_2<3, 0b000110,
325 (ops MEMri:$addr, IntRegs:$src),
326 "sth $src, [$addr]",
327 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
328def STrr : F3_1<3, 0b000100,
329 (ops MEMrr:$addr, IntRegs:$src),
330 "st $src, [$addr]",
331 [(store IntRegs:$src, ADDRrr:$addr)]>;
332def STri : F3_2<3, 0b000100,
333 (ops MEMri:$addr, IntRegs:$src),
334 "st $src, [$addr]",
335 [(store IntRegs:$src, ADDRri:$addr)]>;
336
337// Section B.5 - Store Floating-point Instructions, p. 97
338def STFrr : F3_1<3, 0b100100,
339 (ops MEMrr:$addr, FPRegs:$src),
340 "st $src, [$addr]",
341 [(store FPRegs:$src, ADDRrr:$addr)]>;
342def STFri : F3_2<3, 0b100100,
343 (ops MEMri:$addr, FPRegs:$src),
344 "st $src, [$addr]",
345 [(store FPRegs:$src, ADDRri:$addr)]>;
346def STDFrr : F3_1<3, 0b100111,
347 (ops MEMrr:$addr, DFPRegs:$src),
348 "std $src, [$addr]",
349 [(store DFPRegs:$src, ADDRrr:$addr)]>;
350def STDFri : F3_2<3, 0b100111,
351 (ops MEMri:$addr, DFPRegs:$src),
352 "std $src, [$addr]",
353 [(store DFPRegs:$src, ADDRri:$addr)]>;
354
355// Section B.9 - SETHI Instruction, p. 104
356def SETHIi: F2_1<0b100,
357 (ops IntRegs:$dst, i32imm:$src),
358 "sethi $src, $dst",
359 [(set IntRegs:$dst, SETHIimm:$src)]>;
360
361// Section B.10 - NOP Instruction, p. 105
362// (It's a special case of SETHI)
363let rd = 0, imm22 = 0 in
364 def NOP : F2_1<0b100, (ops), "nop", []>;
365
366// Section B.11 - Logical Instructions, p. 106
367def ANDrr : F3_1<2, 0b000001,
368 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
369 "and $b, $c, $dst",
370 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
371def ANDri : F3_2<2, 0b000001,
372 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
373 "and $b, $c, $dst",
374 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
375def ANDNrr : F3_1<2, 0b000101,
376 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
377 "andn $b, $c, $dst",
378 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
379def ANDNri : F3_2<2, 0b000101,
380 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
381 "andn $b, $c, $dst", []>;
382def ORrr : F3_1<2, 0b000010,
383 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
384 "or $b, $c, $dst",
385 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
386def ORri : F3_2<2, 0b000010,
387 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
388 "or $b, $c, $dst",
389 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
390def ORNrr : F3_1<2, 0b000110,
391 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
392 "orn $b, $c, $dst",
393 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
394def ORNri : F3_2<2, 0b000110,
395 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
396 "orn $b, $c, $dst", []>;
397def XORrr : F3_1<2, 0b000011,
398 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
399 "xor $b, $c, $dst",
400 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
401def XORri : F3_2<2, 0b000011,
402 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
403 "xor $b, $c, $dst",
404 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
405def XNORrr : F3_1<2, 0b000111,
406 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
407 "xnor $b, $c, $dst",
408 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
409def XNORri : F3_2<2, 0b000111,
410 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
411 "xnor $b, $c, $dst", []>;
412
413// Section B.12 - Shift Instructions, p. 107
414def SLLrr : F3_1<2, 0b100101,
415 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
416 "sll $b, $c, $dst",
417 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
418def SLLri : F3_2<2, 0b100101,
419 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
420 "sll $b, $c, $dst",
421 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
422def SRLrr : F3_1<2, 0b100110,
423 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
424 "srl $b, $c, $dst",
425 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
426def SRLri : F3_2<2, 0b100110,
427 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
428 "srl $b, $c, $dst",
429 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
430def SRArr : F3_1<2, 0b100111,
431 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
432 "sra $b, $c, $dst",
433 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
434def SRAri : F3_2<2, 0b100111,
435 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
436 "sra $b, $c, $dst",
437 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
438
439// Section B.13 - Add Instructions, p. 108
440def ADDrr : F3_1<2, 0b000000,
441 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
442 "add $b, $c, $dst",
443 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
444def ADDri : F3_2<2, 0b000000,
445 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
446 "add $b, $c, $dst",
447 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
Chris Lattnerfcb8a3a2006-02-10 07:35:42 +0000[diff] [blame]448
449// "LEA" forms of add (patterns to make tblgen happy)
450def LEA_ADDri : F3_2<2, 0b000000,
451 (ops IntRegs:$dst, MEMri:$addr),
452 "add ${addr:arith}, $dst",
453 [(set IntRegs:$dst, ADDRri:$addr)]>;
454
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]455def ADDCCrr : F3_1<2, 0b010000,
456 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]457 "addcc $b, $c, $dst",
458 [(set IntRegs:$dst, (addc IntRegs:$b, IntRegs:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]459def ADDCCri : F3_2<2, 0b010000,
460 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]461 "addcc $b, $c, $dst",
462 [(set IntRegs:$dst, (addc IntRegs:$b, simm13:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]463def ADDXrr : F3_1<2, 0b001000,
464 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]465 "addx $b, $c, $dst",
466 [(set IntRegs:$dst, (adde IntRegs:$b, IntRegs:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]467def ADDXri : F3_2<2, 0b001000,
468 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]469 "addx $b, $c, $dst",
470 [(set IntRegs:$dst, (adde IntRegs:$b, simm13:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]471
472// Section B.15 - Subtract Instructions, p. 110
473def SUBrr : F3_1<2, 0b000100,
474 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
475 "sub $b, $c, $dst",
476 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
477def SUBri : F3_2<2, 0b000100,
478 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
479 "sub $b, $c, $dst",
480 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
481def SUBXrr : F3_1<2, 0b001100,
482 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]483 "subx $b, $c, $dst",
484 [(set IntRegs:$dst, (sube IntRegs:$b, IntRegs:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]485def SUBXri : F3_2<2, 0b001100,
486 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]487 "subx $b, $c, $dst",
488 [(set IntRegs:$dst, (sube IntRegs:$b, simm13:$c))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]489def SUBCCrr : F3_1<2, 0b010100,
490 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
491 "subcc $b, $c, $dst",
492 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, IntRegs:$c))]>;
493def SUBCCri : F3_2<2, 0b010100,
494 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
495 "subcc $b, $c, $dst",
496 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, simm13:$c))]>;
497def SUBXCCrr: F3_1<2, 0b011100,
498 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
499 "subxcc $b, $c, $dst", []>;
500
501// Section B.18 - Multiply Instructions, p. 113
502def UMULrr : F3_1<2, 0b001010,
503 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
504 "umul $b, $c, $dst", []>;
505def UMULri : F3_2<2, 0b001010,
506 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
507 "umul $b, $c, $dst", []>;
Chris Lattnerc75d5b02006-02-09 05:06:36 +0000[diff] [blame]508
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]509def SMULrr : F3_1<2, 0b001011,
510 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
511 "smul $b, $c, $dst",
512 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
513def SMULri : F3_2<2, 0b001011,
514 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
515 "smul $b, $c, $dst",
516 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
517
Chris Lattnerc75d5b02006-02-09 05:06:36 +0000[diff] [blame]518/*
519//===-------------------------
520// Sparc Example
Chris Lattner8587f882006-05-09 04:58:46 +0000[diff] [blame]521defm intinst{OPC1, OPC2}<bits Opc, string asmstr, SDNode code> {
Chris Lattnerc75d5b02006-02-09 05:06:36 +0000[diff] [blame]522 def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
523 [(set IntRegs:$dst, (code IntRegs:$b, IntRegs:$c))]>;
524 def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
525 [(set IntRegs:$dst, (code IntRegs:$b, simm13:$c))]>;
526}
Chris Lattner8587f882006-05-09 04:58:46 +0000[diff] [blame]527defm intinst_np{OPC1, OPC2}<bits Opc, string asmstr> {
Chris Lattnerc75d5b02006-02-09 05:06:36 +0000[diff] [blame]528 def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
529 []>;
530 def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
531 []>;
532}
533
Chris Lattner8587f882006-05-09 04:58:46 +0000[diff] [blame]534def { ADDXrr, ADDXri} : intinstnp<0b001000, "addx $b, $c, $dst">;
535def { SUBrr, SUBri} : intinst <0b000100, "sub $b, $c, $dst", sub>;
536def intinstnp{ SUBXrr, SUBXri}<0b001100, "subx $b, $c, $dst">;
537def intinst {SUBCCrr, SUBCCri}<0b010100, "subcc $b, $c, $dst", SPcmpicc>;
538def intinst { SMULrr, SMULri}<0b001011, "smul $b, $c, $dst", mul>;
Chris Lattnerc75d5b02006-02-09 05:06:36 +0000[diff] [blame]539
540//===-------------------------
541// X86 Example
542defm cmov32<id OPC1, id OPC2, int opc, string asmstr, PatLeaf cond> {
543 def OPC1 : I<opc, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
544 asmstr+" {$src2, $dst|$dst, $src2}",
545 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, cond))]>, TB;
546 def OPC2 : I<opc, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
547 asmstr+" {$src2, $dst|$dst, $src2}",
548 [(set R32:$dst, (X86cmov R32:$src1,
549 (loadi32 addr:$src2), cond))]>, TB;
550}
551
552def cmov<CMOVL32rr, CMOVL32rm, 0x4C, "cmovl", X86_COND_L>;
553def cmov<CMOVB32rr, CMOVB32rm, 0x4C, "cmovb", X86_COND_B>;
554
555//===-------------------------
556// PPC Example
557
558def fpunop<id OPC1, id OPC2, id FORM, int op1, int op2, int op3, string asmstr,
559 SDNode code> {
560 def OPC1 : FORM<op1, op3, (ops F4RC:$frD, F4RC:$frB),
561 asmstr+" $frD, $frB", FPGeneral,
562 [(set F4RC:$frD, (code F4RC:$frB))]>;
563 def OPC2 : FORM<op2, op3, (ops F8RC:$frD, F8RC:$frB),
564 asmstr+" $frD, $frB", FPGeneral,
565 [(set F8RC:$frD, (code F8RC:$frB))]>;
566}
567
568def fpunop< FABSS, FABSD, XForm_26, 63, 63, 264, "fabs", fabs>;
569def fpunop<FNABSS, FNABSD, XForm_26, 63, 63, 136, "fnabs", fnabs>;
570def fpunop< FNEGS, FNEGD, XForm_26, 63, 63, 40, "fneg", fneg>;
571*/
572
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]573// Section B.19 - Divide Instructions, p. 115
574def UDIVrr : F3_1<2, 0b001110,
575 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
576 "udiv $b, $c, $dst", []>;
577def UDIVri : F3_2<2, 0b001110,
578 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
579 "udiv $b, $c, $dst", []>;
580def SDIVrr : F3_1<2, 0b001111,
581 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
582 "sdiv $b, $c, $dst", []>;
583def SDIVri : F3_2<2, 0b001111,
584 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
585 "sdiv $b, $c, $dst", []>;
586
587// Section B.20 - SAVE and RESTORE, p. 117
588def SAVErr : F3_1<2, 0b111100,
589 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
590 "save $b, $c, $dst", []>;
591def SAVEri : F3_2<2, 0b111100,
592 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
593 "save $b, $c, $dst", []>;
594def RESTORErr : F3_1<2, 0b111101,
595 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
596 "restore $b, $c, $dst", []>;
597def RESTOREri : F3_2<2, 0b111101,
598 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
599 "restore $b, $c, $dst", []>;
600
601// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
602
603// conditional branch class:
604class BranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
605 : F2_2<cc, 0b010, ops, asmstr, pattern> {
606 let isBranch = 1;
607 let isTerminator = 1;
608 let hasDelaySlot = 1;
609 let noResults = 1;
610}
611
612let isBarrier = 1 in
613 def BA : BranchSP<0b1000, (ops brtarget:$dst),
614 "ba $dst",
615 [(br bb:$dst)]>;
616
617// FIXME: the encoding for the JIT should look at the condition field.
618def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc),
619 "b$cc $dst",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]620 [(SPbricc bb:$dst, imm:$cc)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]621
622
623// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
624
625// floating-point conditional branch class:
626class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
627 : F2_2<cc, 0b110, ops, asmstr, pattern> {
628 let isBranch = 1;
629 let isTerminator = 1;
630 let hasDelaySlot = 1;
631 let noResults = 1;
632}
633
634// FIXME: the encoding for the JIT should look at the condition field.
635def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc),
636 "fb$cc $dst",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]637 [(SPbrfcc bb:$dst, imm:$cc)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]638
639
640// Section B.24 - Call and Link Instruction, p. 125
641// This is the only Format 1 instruction
642let Uses = [O0, O1, O2, O3, O4, O5],
643 hasDelaySlot = 1, isCall = 1, noResults = 1,
644 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
645 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
646 def CALL : InstSP<(ops calltarget:$dst),
647 "call $dst", []> {
648 bits<30> disp;
649 let op = 1;
650 let Inst{29-0} = disp;
651 }
652
653 // indirect calls
654 def JMPLrr : F3_1<2, 0b111000,
655 (ops MEMrr:$ptr),
656 "call $ptr",
657 [(call ADDRrr:$ptr)]>;
658 def JMPLri : F3_2<2, 0b111000,
659 (ops MEMri:$ptr),
660 "call $ptr",
661 [(call ADDRri:$ptr)]>;
662}
663
664// Section B.28 - Read State Register Instructions
665def RDY : F3_1<2, 0b101000,
666 (ops IntRegs:$dst),
667 "rd %y, $dst", []>;
668
669// Section B.29 - Write State Register Instructions
670def WRYrr : F3_1<2, 0b110000,
671 (ops IntRegs:$b, IntRegs:$c),
672 "wr $b, $c, %y", []>;
673def WRYri : F3_2<2, 0b110000,
674 (ops IntRegs:$b, i32imm:$c),
675 "wr $b, $c, %y", []>;
676
677// Convert Integer to Floating-point Instructions, p. 141
678def FITOS : F3_3<2, 0b110100, 0b011000100,
679 (ops FPRegs:$dst, FPRegs:$src),
680 "fitos $src, $dst",
681 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
682def FITOD : F3_3<2, 0b110100, 0b011001000,
683 (ops DFPRegs:$dst, FPRegs:$src),
684 "fitod $src, $dst",
685 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
686
687// Convert Floating-point to Integer Instructions, p. 142
688def FSTOI : F3_3<2, 0b110100, 0b011010001,
689 (ops FPRegs:$dst, FPRegs:$src),
690 "fstoi $src, $dst",
691 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
692def FDTOI : F3_3<2, 0b110100, 0b011010010,
693 (ops FPRegs:$dst, DFPRegs:$src),
694 "fdtoi $src, $dst",
695 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
696
697// Convert between Floating-point Formats Instructions, p. 143
698def FSTOD : F3_3<2, 0b110100, 0b011001001,
699 (ops DFPRegs:$dst, FPRegs:$src),
700 "fstod $src, $dst",
701 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
702def FDTOS : F3_3<2, 0b110100, 0b011000110,
703 (ops FPRegs:$dst, DFPRegs:$src),
704 "fdtos $src, $dst",
705 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
706
707// Floating-point Move Instructions, p. 144
708def FMOVS : F3_3<2, 0b110100, 0b000000001,
709 (ops FPRegs:$dst, FPRegs:$src),
710 "fmovs $src, $dst", []>;
711def FNEGS : F3_3<2, 0b110100, 0b000000101,
712 (ops FPRegs:$dst, FPRegs:$src),
713 "fnegs $src, $dst",
714 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
715def FABSS : F3_3<2, 0b110100, 0b000001001,
716 (ops FPRegs:$dst, FPRegs:$src),
717 "fabss $src, $dst",
718 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
719
720
721// Floating-point Square Root Instructions, p.145
722def FSQRTS : F3_3<2, 0b110100, 0b000101001,
723 (ops FPRegs:$dst, FPRegs:$src),
724 "fsqrts $src, $dst",
725 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
726def FSQRTD : F3_3<2, 0b110100, 0b000101010,
727 (ops DFPRegs:$dst, DFPRegs:$src),
728 "fsqrtd $src, $dst",
729 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
730
731
732
733// Floating-point Add and Subtract Instructions, p. 146
734def FADDS : F3_3<2, 0b110100, 0b001000001,
735 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
736 "fadds $src1, $src2, $dst",
737 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
738def FADDD : F3_3<2, 0b110100, 0b001000010,
739 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
740 "faddd $src1, $src2, $dst",
741 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
742def FSUBS : F3_3<2, 0b110100, 0b001000101,
743 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
744 "fsubs $src1, $src2, $dst",
745 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
746def FSUBD : F3_3<2, 0b110100, 0b001000110,
747 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
748 "fsubd $src1, $src2, $dst",
749 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
750
751// Floating-point Multiply and Divide Instructions, p. 147
752def FMULS : F3_3<2, 0b110100, 0b001001001,
753 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
754 "fmuls $src1, $src2, $dst",
755 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
756def FMULD : F3_3<2, 0b110100, 0b001001010,
757 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
758 "fmuld $src1, $src2, $dst",
759 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
760def FSMULD : F3_3<2, 0b110100, 0b001101001,
761 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
762 "fsmuld $src1, $src2, $dst",
763 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
764 (fextend FPRegs:$src2)))]>;
765def FDIVS : F3_3<2, 0b110100, 0b001001101,
766 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
767 "fdivs $src1, $src2, $dst",
768 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
769def FDIVD : F3_3<2, 0b110100, 0b001001110,
770 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
771 "fdivd $src1, $src2, $dst",
772 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
773
774// Floating-point Compare Instructions, p. 148
775// Note: the 2nd template arg is different for these guys.
776// Note 2: the result of a FCMP is not available until the 2nd cycle
777// after the instr is retired, but there is no interlock. This behavior
778// is modelled with a forced noop after the instruction.
779def FCMPS : F3_3<2, 0b110101, 0b001010001,
780 (ops FPRegs:$src1, FPRegs:$src2),
781 "fcmps $src1, $src2\n\tnop",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]782 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]783def FCMPD : F3_3<2, 0b110101, 0b001010010,
784 (ops DFPRegs:$src1, DFPRegs:$src2),
785 "fcmpd $src1, $src2\n\tnop",
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]786 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]787
788
789//===----------------------------------------------------------------------===//
790// V9 Instructions
791//===----------------------------------------------------------------------===//
792
793// V9 Conditional Moves.
794let Predicates = [HasV9], isTwoAddress = 1 in {
795 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
796 // FIXME: Add instruction encodings for the JIT some day.
797 def MOVICCrr
798 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
799 "mov$cc %icc, $F, $dst",
800 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]801 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]802 def MOVICCri
803 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
804 "mov$cc %icc, $F, $dst",
805 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]806 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]807
808 def MOVFCCrr
809 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
810 "mov$cc %fcc0, $F, $dst",
811 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]812 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]813 def MOVFCCri
814 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
815 "mov$cc %fcc0, $F, $dst",
816 [(set IntRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]817 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]818
819 def FMOVS_ICC
820 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
821 "fmovs$cc %icc, $F, $dst",
822 [(set FPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]823 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]824 def FMOVD_ICC
825 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
826 "fmovd$cc %icc, $F, $dst",
827 [(set DFPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]828 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]829 def FMOVS_FCC
830 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
831 "fmovs$cc %fcc0, $F, $dst",
832 [(set FPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]833 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]834 def FMOVD_FCC
835 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
836 "fmovd$cc %fcc0, $F, $dst",
837 [(set DFPRegs:$dst,
Chris Lattner0c4dea42006-02-10 06:58:25 +0000[diff] [blame]838 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]839
840}
841
842// Floating-Point Move Instructions, p. 164 of the V9 manual.
843let Predicates = [HasV9] in {
844 def FMOVD : F3_3<2, 0b110100, 0b000000010,
845 (ops DFPRegs:$dst, DFPRegs:$src),
846 "fmovd $src, $dst", []>;
847 def FNEGD : F3_3<2, 0b110100, 0b000000110,
848 (ops DFPRegs:$dst, DFPRegs:$src),
849 "fnegd $src, $dst",
850 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
851 def FABSD : F3_3<2, 0b110100, 0b000001010,
852 (ops DFPRegs:$dst, DFPRegs:$src),
853 "fabsd $src, $dst",
854 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
855}
856
857// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
858// the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
859def POPCrr : F3_1<2, 0b101110,
860 (ops IntRegs:$dst, IntRegs:$src),
861 "popc $src, $dst", []>, Requires<[HasV9]>;
862def : Pat<(ctpop IntRegs:$src),
863 (POPCrr (SLLri IntRegs:$src, 0))>;
864
865//===----------------------------------------------------------------------===//
866// Non-Instruction Patterns
867//===----------------------------------------------------------------------===//
868
869// Small immediates.
870def : Pat<(i32 simm13:$val),
871 (ORri G0, imm:$val)>;
872// Arbitrary immediates.
873def : Pat<(i32 imm:$val),
874 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
875
Nate Begeman5965bd12006-02-17 05:43:56 +0000[diff] [blame]876// subc
877def : Pat<(subc IntRegs:$b, IntRegs:$c),
878 (SUBCCrr IntRegs:$b, IntRegs:$c)>;
879def : Pat<(subc IntRegs:$b, simm13:$val),
880 (SUBCCri IntRegs:$b, imm:$val)>;
881
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]882// Global addresses, constant pool entries
883def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
884def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
885def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
886def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
887
888// Add reg, lo. This is used when taking the addr of a global/constpool entry.
889def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
890 (ADDri IntRegs:$r, tglobaladdr:$in)>;
891def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
892 (ADDri IntRegs:$r, tconstpool:$in)>;
893
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]894// Calls:
895def : Pat<(call tglobaladdr:$dst),
896 (CALL tglobaladdr:$dst)>;
Chris Lattnerfcb8a3a2006-02-10 07:35:42 +0000[diff] [blame]897def : Pat<(call texternalsym:$dst),
898 (CALL texternalsym:$dst)>;
Chris Lattner158e1f52006-02-05 05:50:24 +0000[diff] [blame]899
900def : Pat<(ret), (RETL)>;
901
902// Map integer extload's to zextloads.
903def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
904def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
905def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
906def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
907def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
908def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
909
910// zextload bool -> zextload byte
911def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
912def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
913
914// truncstore bool -> truncstore byte.
915def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
916 (STBrr ADDRrr:$addr, IntRegs:$src)>;
917def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
918 (STBri ADDRri:$addr, IntRegs:$src)>;