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gerrit-public.fairphone.software / toolchain / llvm-project / d6317d22a92d596731b1dd9d4a8010879f3e43d9 / . / llvm / lib / Target / AArch64 / Disassembler / AArch64Disassembler.cpp
blob: 4102f1eb5cc12c6afdacebd52182058db2888844 [file] [log] [blame]
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Disassembler.h"
14#include "AArch64ExternalSymbolizer.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]15#include "MCTargetDesc/AArch64AddressingModes.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]16#include "MCTargetDesc/AArch64MCTargetDesc.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]17#include "Utils/AArch64BaseInfo.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]18#include "llvm-c/Disassembler.h"
19#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]20#include "llvm/MC/MCFixedLenDisassembler.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]21#include "llvm/MC/MCInst.h"
Benjamin Kramer27c769d2018-09-10 12:53:46 +0000[diff] [blame]22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]24#include "llvm/Support/Compiler.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]25#include "llvm/Support/Debug.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]26#include "llvm/Support/ErrorHandling.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]27#include "llvm/Support/TargetRegistry.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]28#include <algorithm>
29#include <memory>
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]30
31using namespace llvm;
32
33#define DEBUG_TYPE "aarch64-disassembler"
34
35// Pull DecodeStatus and its enum values into the global namespace.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]36using DecodeStatus = MCDisassembler::DecodeStatus;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]37
38// Forward declare these because the autogenerated code will reference them.
39// Definitions are further down.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]40static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]41 unsigned RegNo, uint64_t Address,
42 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]43static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]44 unsigned RegNo,
45 uint64_t Address,
46 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]47static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]48 uint64_t Address,
49 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]50static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]51 uint64_t Address,
52 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]53static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]54 uint64_t Address,
55 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]56static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]57 uint64_t Address,
58 const void *Decoder);
Sander de Smalen367694b2018-04-20 08:54:49 +0000[diff] [blame]59static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
60 uint64_t Address,
61 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]62static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]63 uint64_t Address,
64 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]65static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]66 unsigned RegNo, uint64_t Address,
67 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]68static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]69 uint64_t Address,
70 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]71static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]72 unsigned RegNo, uint64_t Address,
73 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]74static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]75 uint64_t Address,
76 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]77static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]78 uint64_t Address,
79 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]80static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]81 uint64_t Address,
82 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]83static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]84 uint64_t Address,
85 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]86static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]87 uint64_t Address,
88 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]89static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]90 uint64_t Address,
91 const void *Decoder);
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]92static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
93 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]94 const void *Decoder);
Sander de Smalen8cd1f532018-07-03 15:31:04 +0000[diff] [blame]95static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
96 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]97 const void *Decoder);
Sander de Smalen8cd1f532018-07-03 15:31:04 +0000[diff] [blame]98static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
99 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]100 const void *Decoder);
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]101static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
102 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]103 const void *Decoder);
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame]104static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
105 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]106 const void *Decoder);
Sander de Smalen7a210db2018-04-16 10:46:18 +0000[diff] [blame]107static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
108 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]109 const void *Decoder);
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]110static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
111 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]112 const void *Decoder);
Sander de Smalen906a5de2018-01-09 17:01:27 +0000[diff] [blame]113static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
114 uint64_t Address,
Fangrui Songbc5c7f22018-07-03 19:07:53 +0000[diff] [blame]115 const void *Decoder);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]116
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]117static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]118 uint64_t Address,
119 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]120static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]121 uint64_t Address,
122 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]123static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]124 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]125static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]126 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]127static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]129static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]130 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]131static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]132 uint64_t Address,
133 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]134static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]135 uint64_t Address,
136 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]137static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]138 uint64_t Address,
139 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]140static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
141 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]142 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]143static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]144 uint64_t Address,
145 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]146static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]147 uint64_t Address,
148 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]149static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
150 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]151 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]152static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
153 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]154 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]155static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]156 uint64_t Address,
157 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]158static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
159 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]160 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]161static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]163static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
164 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]165static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]166 uint64_t Address,
167 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]168static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]169 uint64_t Address,
170 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]171static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]172 uint64_t Address, const void *Decoder);
173
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]174static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]175 uint64_t Address,
176 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]177static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]178 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]179static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]180 uint64_t Addr,
181 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]182static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]183 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]184static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]185 uint64_t Addr,
186 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]187static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]188 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]189static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]190 uint64_t Addr,
191 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]192static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]193 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]194static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]195 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]196static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]197 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]198static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]199 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]200static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]201 uint64_t Addr, const void *Decoder);
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]202static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
203 unsigned RegNo,
204 uint64_t Addr,
205 const void *Decoder);
206static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
207 unsigned RegNo,
208 uint64_t Addr,
209 const void *Decoder);
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]210static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
211 uint32_t insn,
212 uint64_t Address,
213 const void *Decoder);
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]214template<int Bits>
215static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
216 uint64_t Address, const void *Decoder);
Sander de Smalen62770792018-05-25 09:47:52 +0000[diff] [blame]217template <int ElementWidth>
218static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
219 uint64_t Addr, const void *Decoder);
Sander de Smalen18ac8f92018-06-15 15:47:44 +0000[diff] [blame]220static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
221 uint64_t Addr, const void *Decoder);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]222
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]223static DecodeStatus DecodeLoadAllocTagArrayInstruction(MCInst &Inst,
224 uint32_t insn,
225 uint64_t address,
226 const void* Decoder);
227
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]228static bool Check(DecodeStatus &Out, DecodeStatus In) {
229 switch (In) {
230 case MCDisassembler::Success:
231 // Out stays the same.
232 return true;
233 case MCDisassembler::SoftFail:
234 Out = In;
235 return true;
236 case MCDisassembler::Fail:
237 Out = In;
238 return false;
239 }
240 llvm_unreachable("Invalid DecodeStatus!");
241}
242
243#include "AArch64GenDisassemblerTables.inc"
244#include "AArch64GenInstrInfo.inc"
245
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]246#define Success MCDisassembler::Success
247#define Fail MCDisassembler::Fail
248#define SoftFail MCDisassembler::SoftFail
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]249
250static MCDisassembler *createAArch64Disassembler(const Target &T,
251 const MCSubtargetInfo &STI,
252 MCContext &Ctx) {
253 return new AArch64Disassembler(STI, Ctx);
254}
255
256DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]257 ArrayRef<uint8_t> Bytes,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]258 uint64_t Address,
259 raw_ostream &OS,
260 raw_ostream &CS) const {
261 CommentStream = &CS;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]262
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]263 Size = 0;
264 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]265 if (Bytes.size() < 4)
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]266 return Fail;
267 Size = 4;
268
269 // Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]270 uint32_t Insn =
271 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]272
273 // Calling the auto-generated decoder function.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]274 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]275}
276
Daniel Sanders50f17232015-09-15 16:17:27 +0000[diff] [blame]277static MCSymbolizer *
278createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
279 LLVMSymbolLookupCallback SymbolLookUp,
280 void *DisInfo, MCContext *Ctx,
281 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]282 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
283 SymbolLookUp, DisInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]284}
285
286extern "C" void LLVMInitializeAArch64Disassembler() {
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]287 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]288 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]289 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]290 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]291 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]292 createAArch64ExternalSymbolizer);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]293 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]294 createAArch64ExternalSymbolizer);
295
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]296 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]297 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]298 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]299 createAArch64ExternalSymbolizer);
300}
301
302static const unsigned FPR128DecoderTable[] = {
303 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
304 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
305 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
306 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
307 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
308 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
309 AArch64::Q30, AArch64::Q31
310};
311
312static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
313 uint64_t Addr,
314 const void *Decoder) {
315 if (RegNo > 31)
316 return Fail;
317
318 unsigned Register = FPR128DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]319 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]320 return Success;
321}
322
323static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
324 uint64_t Addr,
325 const void *Decoder) {
326 if (RegNo > 15)
327 return Fail;
328 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
329}
330
331static const unsigned FPR64DecoderTable[] = {
332 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
333 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
334 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
335 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
336 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
337 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
338 AArch64::D30, AArch64::D31
339};
340
341static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
342 uint64_t Addr,
343 const void *Decoder) {
344 if (RegNo > 31)
345 return Fail;
346
347 unsigned Register = FPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]348 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]349 return Success;
350}
351
352static const unsigned FPR32DecoderTable[] = {
353 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
354 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
355 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
356 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
357 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
358 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
359 AArch64::S30, AArch64::S31
360};
361
362static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
363 uint64_t Addr,
364 const void *Decoder) {
365 if (RegNo > 31)
366 return Fail;
367
368 unsigned Register = FPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]369 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]370 return Success;
371}
372
373static const unsigned FPR16DecoderTable[] = {
374 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
375 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
376 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
377 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
378 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
379 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
380 AArch64::H30, AArch64::H31
381};
382
383static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
384 uint64_t Addr,
385 const void *Decoder) {
386 if (RegNo > 31)
387 return Fail;
388
389 unsigned Register = FPR16DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]390 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]391 return Success;
392}
393
394static const unsigned FPR8DecoderTable[] = {
395 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
396 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
397 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
398 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
399 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
400 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
401 AArch64::B30, AArch64::B31
402};
403
404static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
405 uint64_t Addr,
406 const void *Decoder) {
407 if (RegNo > 31)
408 return Fail;
409
410 unsigned Register = FPR8DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]411 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]412 return Success;
413}
414
415static const unsigned GPR64DecoderTable[] = {
416 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
417 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
418 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
419 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
420 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
421 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
422 AArch64::LR, AArch64::XZR
423};
424
Sander de Smalen367694b2018-04-20 08:54:49 +0000[diff] [blame]425static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
426 uint64_t Addr,
427 const void *Decoder) {
428 if (RegNo > 30)
429 return Fail;
430
431 unsigned Register = GPR64DecoderTable[RegNo];
432 Inst.addOperand(MCOperand::createReg(Register));
433 return Success;
434}
435
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]436static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
437 uint64_t Addr,
438 const void *Decoder) {
439 if (RegNo > 31)
440 return Fail;
441
442 unsigned Register = GPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]443 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]444 return Success;
445}
446
447static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
448 uint64_t Addr,
449 const void *Decoder) {
450 if (RegNo > 31)
451 return Fail;
452 unsigned Register = GPR64DecoderTable[RegNo];
453 if (Register == AArch64::XZR)
454 Register = AArch64::SP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]455 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]456 return Success;
457}
458
459static const unsigned GPR32DecoderTable[] = {
460 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
461 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
462 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
463 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
464 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
465 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
466 AArch64::W30, AArch64::WZR
467};
468
469static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
470 uint64_t Addr,
471 const void *Decoder) {
472 if (RegNo > 31)
473 return Fail;
474
475 unsigned Register = GPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]476 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]477 return Success;
478}
479
480static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
481 uint64_t Addr,
482 const void *Decoder) {
483 if (RegNo > 31)
484 return Fail;
485
486 unsigned Register = GPR32DecoderTable[RegNo];
487 if (Register == AArch64::WZR)
488 Register = AArch64::WSP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]489 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]490 return Success;
491}
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]492static const unsigned ZPRDecoderTable[] = {
493 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
494 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
495 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
496 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
497 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
498 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
499 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
500 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
501};
502
503static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
504 uint64_t Address,
505 const void* Decoder) {
506 if (RegNo > 31)
507 return Fail;
508
509 unsigned Register = ZPRDecoderTable[RegNo];
510 Inst.addOperand(MCOperand::createReg(Register));
511 return Success;
512}
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]513
Sander de Smalen8cd1f532018-07-03 15:31:04 +0000[diff] [blame]514static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
515 uint64_t Address,
516 const void *Decoder) {
517 if (RegNo > 15)
518 return Fail;
519 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
520}
521
522static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
523 uint64_t Address,
524 const void *Decoder) {
525 if (RegNo > 7)
526 return Fail;
527 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
528}
529
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]530static const unsigned ZZDecoderTable[] = {
531 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4,
532 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
533 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12,
534 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
535 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
536 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
537 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
538 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
539};
540
541static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
542 uint64_t Address,
543 const void* Decoder) {
544 if (RegNo > 31)
545 return Fail;
546 unsigned Register = ZZDecoderTable[RegNo];
547 Inst.addOperand(MCOperand::createReg(Register));
548 return Success;
549}
550
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame]551static const unsigned ZZZDecoderTable[] = {
552 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4,
553 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
554 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10,
555 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13,
556 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
557 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19,
558 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22,
559 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25,
560 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28,
561 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
562 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1
563};
564
565static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
566 uint64_t Address,
567 const void* Decoder) {
568 if (RegNo > 31)
569 return Fail;
570 unsigned Register = ZZZDecoderTable[RegNo];
571 Inst.addOperand(MCOperand::createReg(Register));
572 return Success;
573}
574
Sander de Smalen7a210db2018-04-16 10:46:18 +0000[diff] [blame]575static const unsigned ZZZZDecoderTable[] = {
576 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5,
577 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
578 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11,
579 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14,
580 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
581 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20,
582 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23,
583 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26,
584 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29,
585 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
586 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2
587};
588
589static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
590 uint64_t Address,
591 const void* Decoder) {
592 if (RegNo > 31)
593 return Fail;
594 unsigned Register = ZZZZDecoderTable[RegNo];
595 Inst.addOperand(MCOperand::createReg(Register));
596 return Success;
597}
598
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]599static const unsigned PPRDecoderTable[] = {
600 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
601 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
602 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
603 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
604};
605
606static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
607 uint64_t Addr, const void *Decoder) {
608 if (RegNo > 15)
609 return Fail;
610
611 unsigned Register = PPRDecoderTable[RegNo];
612 Inst.addOperand(MCOperand::createReg(Register));
613 return Success;
614}
615
Sander de Smalendc5e0812018-01-03 10:15:46 +0000[diff] [blame]616static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
617 uint64_t Addr,
618 const void* Decoder) {
619 if (RegNo > 7)
620 return Fail;
621
622 // Just reuse the PPR decode table
623 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
624}
625
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]626static const unsigned VectorDecoderTable[] = {
627 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
628 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
629 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
630 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
631 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
632 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
633 AArch64::Q30, AArch64::Q31
634};
635
636static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
637 uint64_t Addr,
638 const void *Decoder) {
639 if (RegNo > 31)
640 return Fail;
641
642 unsigned Register = VectorDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]643 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]644 return Success;
645}
646
647static const unsigned QQDecoderTable[] = {
648 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
649 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
650 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
651 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
652 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
653 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
654 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
655 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
656};
657
658static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
659 uint64_t Addr, const void *Decoder) {
660 if (RegNo > 31)
661 return Fail;
662 unsigned Register = QQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]663 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]664 return Success;
665}
666
667static const unsigned QQQDecoderTable[] = {
668 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
669 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
670 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
671 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
672 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
673 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
674 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
675 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
676 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
677 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
678 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
679};
680
681static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
682 uint64_t Addr, const void *Decoder) {
683 if (RegNo > 31)
684 return Fail;
685 unsigned Register = QQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]686 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]687 return Success;
688}
689
690static const unsigned QQQQDecoderTable[] = {
691 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
692 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
693 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
694 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
695 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
696 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
697 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
698 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
699 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
700 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
701 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
702};
703
704static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
705 uint64_t Addr,
706 const void *Decoder) {
707 if (RegNo > 31)
708 return Fail;
709 unsigned Register = QQQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]710 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]711 return Success;
712}
713
714static const unsigned DDDecoderTable[] = {
715 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
716 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
717 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
718 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
719 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
720 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
721 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
722 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
723};
724
725static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
726 uint64_t Addr, const void *Decoder) {
727 if (RegNo > 31)
728 return Fail;
729 unsigned Register = DDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]730 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]731 return Success;
732}
733
734static const unsigned DDDDecoderTable[] = {
735 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
736 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
737 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
738 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
739 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
740 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
741 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
742 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
743 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
744 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
745 AArch64::D30_D31_D0, AArch64::D31_D0_D1
746};
747
748static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
749 uint64_t Addr, const void *Decoder) {
750 if (RegNo > 31)
751 return Fail;
752 unsigned Register = DDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]753 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]754 return Success;
755}
756
757static const unsigned DDDDDecoderTable[] = {
758 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
759 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
760 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
761 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
762 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
763 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
764 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
765 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
766 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
767 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
768 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
769};
770
771static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
772 uint64_t Addr,
773 const void *Decoder) {
774 if (RegNo > 31)
775 return Fail;
776 unsigned Register = DDDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]777 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]778 return Success;
779}
780
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]781static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]782 uint64_t Addr,
783 const void *Decoder) {
784 // scale{5} is asserted as 1 in tblgen.
Tom Coxon2c13e712014-09-30 16:23:16 +0000[diff] [blame]785 Imm |= 0x20;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]786 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]787 return Success;
788}
789
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]790static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]791 uint64_t Addr,
792 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]793 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]794 return Success;
795}
796
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]797static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]798 uint64_t Addr, const void *Decoder) {
799 int64_t ImmVal = Imm;
800 const AArch64Disassembler *Dis =
801 static_cast<const AArch64Disassembler *>(Decoder);
802
803 // Sign-extend 19-bit immediate.
804 if (ImmVal & (1 << (19 - 1)))
805 ImmVal |= ~((1LL << 19) - 1);
806
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]807 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]808 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]809 Inst.addOperand(MCOperand::createImm(ImmVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]810 return Success;
811}
812
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]813static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]814 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]815 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
816 Inst.addOperand(MCOperand::createImm(Imm & 1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]817 return Success;
818}
819
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]820static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]821 uint64_t Address,
822 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]823 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]824
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]825 // Every system register in the encoding space is valid with the syntax
826 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
827 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]828}
829
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]830static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]831 uint64_t Address,
832 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]833 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]834
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]835 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]836}
837
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]838static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]839 uint64_t Address,
840 const void *Decoder) {
841 // This decoder exists to add the dummy Lane operand to the MCInst, which must
842 // be 1 in assembly but has no other real manifestation.
843 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
844 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
845 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
846
847 if (IsToVec) {
848 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
849 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
850 } else {
851 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
852 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
853 }
854
855 // Add the lane
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]856 Inst.addOperand(MCOperand::createImm(1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]857
858 return Success;
859}
860
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]861static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]862 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]863 Inst.addOperand(MCOperand::createImm(Add - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]864 return Success;
865}
866
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]867static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]868 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]869 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]870 return Success;
871}
872
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]873static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]874 uint64_t Addr, const void *Decoder) {
875 return DecodeVecShiftRImm(Inst, Imm, 64);
876}
877
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]878static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]879 uint64_t Addr,
880 const void *Decoder) {
881 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
882}
883
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]884static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]885 uint64_t Addr, const void *Decoder) {
886 return DecodeVecShiftRImm(Inst, Imm, 32);
887}
888
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]889static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]890 uint64_t Addr,
891 const void *Decoder) {
892 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
893}
894
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]895static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]896 uint64_t Addr, const void *Decoder) {
897 return DecodeVecShiftRImm(Inst, Imm, 16);
898}
899
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]900static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]901 uint64_t Addr,
902 const void *Decoder) {
903 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
904}
905
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]906static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]907 uint64_t Addr, const void *Decoder) {
908 return DecodeVecShiftRImm(Inst, Imm, 8);
909}
910
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]911static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]912 uint64_t Addr, const void *Decoder) {
913 return DecodeVecShiftLImm(Inst, Imm, 64);
914}
915
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]916static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]917 uint64_t Addr, const void *Decoder) {
918 return DecodeVecShiftLImm(Inst, Imm, 32);
919}
920
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]921static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]922 uint64_t Addr, const void *Decoder) {
923 return DecodeVecShiftLImm(Inst, Imm, 16);
924}
925
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]926static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]927 uint64_t Addr, const void *Decoder) {
928 return DecodeVecShiftLImm(Inst, Imm, 8);
929}
930
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]931static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
932 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]933 const void *Decoder) {
934 unsigned Rd = fieldFromInstruction(insn, 0, 5);
935 unsigned Rn = fieldFromInstruction(insn, 5, 5);
936 unsigned Rm = fieldFromInstruction(insn, 16, 5);
937 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
938 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
939 unsigned shift = (shiftHi << 6) | shiftLo;
940 switch (Inst.getOpcode()) {
941 default:
942 return Fail;
943 case AArch64::ADDWrs:
944 case AArch64::ADDSWrs:
945 case AArch64::SUBWrs:
946 case AArch64::SUBSWrs:
947 // if shift == '11' then ReservedValue()
948 if (shiftHi == 0x3)
949 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]950 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]951 case AArch64::ANDWrs:
952 case AArch64::ANDSWrs:
953 case AArch64::BICWrs:
954 case AArch64::BICSWrs:
955 case AArch64::ORRWrs:
956 case AArch64::ORNWrs:
957 case AArch64::EORWrs:
958 case AArch64::EONWrs: {
959 // if sf == '0' and imm6<5> == '1' then ReservedValue()
960 if (shiftLo >> 5 == 1)
961 return Fail;
962 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
963 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
964 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
965 break;
966 }
967 case AArch64::ADDXrs:
968 case AArch64::ADDSXrs:
969 case AArch64::SUBXrs:
970 case AArch64::SUBSXrs:
971 // if shift == '11' then ReservedValue()
972 if (shiftHi == 0x3)
973 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]974 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]975 case AArch64::ANDXrs:
976 case AArch64::ANDSXrs:
977 case AArch64::BICXrs:
978 case AArch64::BICSXrs:
979 case AArch64::ORRXrs:
980 case AArch64::ORNXrs:
981 case AArch64::EORXrs:
982 case AArch64::EONXrs:
983 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
984 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
985 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
986 break;
987 }
988
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]989 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]990 return Success;
991}
992
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]993static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]994 uint64_t Addr,
995 const void *Decoder) {
996 unsigned Rd = fieldFromInstruction(insn, 0, 5);
997 unsigned imm = fieldFromInstruction(insn, 5, 16);
998 unsigned shift = fieldFromInstruction(insn, 21, 2);
999 shift <<= 4;
1000 switch (Inst.getOpcode()) {
1001 default:
1002 return Fail;
1003 case AArch64::MOVZWi:
1004 case AArch64::MOVNWi:
1005 case AArch64::MOVKWi:
1006 if (shift & (1U << 5))
1007 return Fail;
1008 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1009 break;
1010 case AArch64::MOVZXi:
1011 case AArch64::MOVNXi:
1012 case AArch64::MOVKXi:
1013 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1014 break;
1015 }
1016
1017 if (Inst.getOpcode() == AArch64::MOVKWi ||
1018 Inst.getOpcode() == AArch64::MOVKXi)
1019 Inst.addOperand(Inst.getOperand(0));
1020
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1021 Inst.addOperand(MCOperand::createImm(imm));
1022 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1023 return Success;
1024}
1025
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1026static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
1027 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1028 const void *Decoder) {
1029 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1030 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1031 unsigned offset = fieldFromInstruction(insn, 10, 12);
1032 const AArch64Disassembler *Dis =
1033 static_cast<const AArch64Disassembler *>(Decoder);
1034
1035 switch (Inst.getOpcode()) {
1036 default:
1037 return Fail;
1038 case AArch64::PRFMui:
1039 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1040 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1041 break;
1042 case AArch64::STRBBui:
1043 case AArch64::LDRBBui:
1044 case AArch64::LDRSBWui:
1045 case AArch64::STRHHui:
1046 case AArch64::LDRHHui:
1047 case AArch64::LDRSHWui:
1048 case AArch64::STRWui:
1049 case AArch64::LDRWui:
1050 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1051 break;
1052 case AArch64::LDRSBXui:
1053 case AArch64::LDRSHXui:
1054 case AArch64::LDRSWui:
1055 case AArch64::STRXui:
1056 case AArch64::LDRXui:
1057 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1058 break;
1059 case AArch64::LDRQui:
1060 case AArch64::STRQui:
1061 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1062 break;
1063 case AArch64::LDRDui:
1064 case AArch64::STRDui:
1065 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1066 break;
1067 case AArch64::LDRSui:
1068 case AArch64::STRSui:
1069 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1070 break;
1071 case AArch64::LDRHui:
1072 case AArch64::STRHui:
1073 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1074 break;
1075 case AArch64::LDRBui:
1076 case AArch64::STRBui:
1077 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1078 break;
1079 }
1080
1081 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1082 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1083 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1084 return Success;
1085}
1086
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1087static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1088 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1089 const void *Decoder) {
1090 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1091 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1092 int64_t offset = fieldFromInstruction(insn, 12, 9);
1093
1094 // offset is a 9-bit signed immediate, so sign extend it to
1095 // fill the unsigned.
1096 if (offset & (1 << (9 - 1)))
1097 offset |= ~((1LL << 9) - 1);
1098
1099 // First operand is always the writeback to the address register, if needed.
1100 switch (Inst.getOpcode()) {
1101 default:
1102 break;
1103 case AArch64::LDRSBWpre:
1104 case AArch64::LDRSHWpre:
1105 case AArch64::STRBBpre:
1106 case AArch64::LDRBBpre:
1107 case AArch64::STRHHpre:
1108 case AArch64::LDRHHpre:
1109 case AArch64::STRWpre:
1110 case AArch64::LDRWpre:
1111 case AArch64::LDRSBWpost:
1112 case AArch64::LDRSHWpost:
1113 case AArch64::STRBBpost:
1114 case AArch64::LDRBBpost:
1115 case AArch64::STRHHpost:
1116 case AArch64::LDRHHpost:
1117 case AArch64::STRWpost:
1118 case AArch64::LDRWpost:
1119 case AArch64::LDRSBXpre:
1120 case AArch64::LDRSHXpre:
1121 case AArch64::STRXpre:
1122 case AArch64::LDRSWpre:
1123 case AArch64::LDRXpre:
1124 case AArch64::LDRSBXpost:
1125 case AArch64::LDRSHXpost:
1126 case AArch64::STRXpost:
1127 case AArch64::LDRSWpost:
1128 case AArch64::LDRXpost:
1129 case AArch64::LDRQpre:
1130 case AArch64::STRQpre:
1131 case AArch64::LDRQpost:
1132 case AArch64::STRQpost:
1133 case AArch64::LDRDpre:
1134 case AArch64::STRDpre:
1135 case AArch64::LDRDpost:
1136 case AArch64::STRDpost:
1137 case AArch64::LDRSpre:
1138 case AArch64::STRSpre:
1139 case AArch64::LDRSpost:
1140 case AArch64::STRSpost:
1141 case AArch64::LDRHpre:
1142 case AArch64::STRHpre:
1143 case AArch64::LDRHpost:
1144 case AArch64::STRHpost:
1145 case AArch64::LDRBpre:
1146 case AArch64::STRBpre:
1147 case AArch64::LDRBpost:
1148 case AArch64::STRBpost:
1149 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1150 break;
1151 }
1152
1153 switch (Inst.getOpcode()) {
1154 default:
1155 return Fail;
1156 case AArch64::PRFUMi:
1157 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1158 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1159 break;
1160 case AArch64::STURBBi:
1161 case AArch64::LDURBBi:
1162 case AArch64::LDURSBWi:
1163 case AArch64::STURHHi:
1164 case AArch64::LDURHHi:
1165 case AArch64::LDURSHWi:
1166 case AArch64::STURWi:
1167 case AArch64::LDURWi:
1168 case AArch64::LDTRSBWi:
1169 case AArch64::LDTRSHWi:
1170 case AArch64::STTRWi:
1171 case AArch64::LDTRWi:
1172 case AArch64::STTRHi:
1173 case AArch64::LDTRHi:
1174 case AArch64::LDTRBi:
1175 case AArch64::STTRBi:
1176 case AArch64::LDRSBWpre:
1177 case AArch64::LDRSHWpre:
1178 case AArch64::STRBBpre:
1179 case AArch64::LDRBBpre:
1180 case AArch64::STRHHpre:
1181 case AArch64::LDRHHpre:
1182 case AArch64::STRWpre:
1183 case AArch64::LDRWpre:
1184 case AArch64::LDRSBWpost:
1185 case AArch64::LDRSHWpost:
1186 case AArch64::STRBBpost:
1187 case AArch64::LDRBBpost:
1188 case AArch64::STRHHpost:
1189 case AArch64::LDRHHpost:
1190 case AArch64::STRWpost:
1191 case AArch64::LDRWpost:
Sjoerd Meijer83a2a622018-07-12 14:57:59 +0000[diff] [blame]1192 case AArch64::STLURBi:
1193 case AArch64::STLURHi:
Sjoerd Meijerceabd502018-07-13 15:25:42 +0000[diff] [blame]1194 case AArch64::STLURWi:
Sjoerd Meijer83a2a622018-07-12 14:57:59 +0000[diff] [blame]1195 case AArch64::LDAPURBi:
Sjoerd Meijerceabd502018-07-13 15:25:42 +0000[diff] [blame]1196 case AArch64::LDAPURSBWi:
Sjoerd Meijer83a2a622018-07-12 14:57:59 +0000[diff] [blame]1197 case AArch64::LDAPURHi:
Sjoerd Meijerceabd502018-07-13 15:25:42 +0000[diff] [blame]1198 case AArch64::LDAPURSHWi:
Sjoerd Meijer83a2a622018-07-12 14:57:59 +0000[diff] [blame]1199 case AArch64::LDAPURi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1200 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1201 break;
1202 case AArch64::LDURSBXi:
1203 case AArch64::LDURSHXi:
1204 case AArch64::LDURSWi:
1205 case AArch64::STURXi:
1206 case AArch64::LDURXi:
1207 case AArch64::LDTRSBXi:
1208 case AArch64::LDTRSHXi:
1209 case AArch64::LDTRSWi:
1210 case AArch64::STTRXi:
1211 case AArch64::LDTRXi:
1212 case AArch64::LDRSBXpre:
1213 case AArch64::LDRSHXpre:
1214 case AArch64::STRXpre:
1215 case AArch64::LDRSWpre:
1216 case AArch64::LDRXpre:
1217 case AArch64::LDRSBXpost:
1218 case AArch64::LDRSHXpost:
1219 case AArch64::STRXpost:
1220 case AArch64::LDRSWpost:
1221 case AArch64::LDRXpost:
Sjoerd Meijer83a2a622018-07-12 14:57:59 +0000[diff] [blame]1222 case AArch64::LDAPURSWi:
Sjoerd Meijerceabd502018-07-13 15:25:42 +0000[diff] [blame]1223 case AArch64::LDAPURSHXi:
1224 case AArch64::LDAPURSBXi:
1225 case AArch64::STLURXi:
1226 case AArch64::LDAPURXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1227 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1228 break;
1229 case AArch64::LDURQi:
1230 case AArch64::STURQi:
1231 case AArch64::LDRQpre:
1232 case AArch64::STRQpre:
1233 case AArch64::LDRQpost:
1234 case AArch64::STRQpost:
1235 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1236 break;
1237 case AArch64::LDURDi:
1238 case AArch64::STURDi:
1239 case AArch64::LDRDpre:
1240 case AArch64::STRDpre:
1241 case AArch64::LDRDpost:
1242 case AArch64::STRDpost:
1243 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1244 break;
1245 case AArch64::LDURSi:
1246 case AArch64::STURSi:
1247 case AArch64::LDRSpre:
1248 case AArch64::STRSpre:
1249 case AArch64::LDRSpost:
1250 case AArch64::STRSpost:
1251 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1252 break;
1253 case AArch64::LDURHi:
1254 case AArch64::STURHi:
1255 case AArch64::LDRHpre:
1256 case AArch64::STRHpre:
1257 case AArch64::LDRHpost:
1258 case AArch64::STRHpost:
1259 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1260 break;
1261 case AArch64::LDURBi:
1262 case AArch64::STURBi:
1263 case AArch64::LDRBpre:
1264 case AArch64::STRBpre:
1265 case AArch64::LDRBpost:
1266 case AArch64::STRBpost:
1267 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1268 break;
1269 }
1270
1271 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1272 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1273
1274 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1275 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1276 bool IsFP = fieldFromInstruction(insn, 26, 1);
1277
1278 // Cannot write back to a transfer register (but xzr != sp).
1279 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1280 return SoftFail;
1281
1282 return Success;
1283}
1284
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1285static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1286 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1287 const void *Decoder) {
1288 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1289 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1290 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1291 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1292
1293 unsigned Opcode = Inst.getOpcode();
1294 switch (Opcode) {
1295 default:
1296 return Fail;
1297 case AArch64::STLXRW:
1298 case AArch64::STLXRB:
1299 case AArch64::STLXRH:
1300 case AArch64::STXRW:
1301 case AArch64::STXRB:
1302 case AArch64::STXRH:
1303 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1304 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1305 case AArch64::LDARW:
1306 case AArch64::LDARB:
1307 case AArch64::LDARH:
1308 case AArch64::LDAXRW:
1309 case AArch64::LDAXRB:
1310 case AArch64::LDAXRH:
1311 case AArch64::LDXRW:
1312 case AArch64::LDXRB:
1313 case AArch64::LDXRH:
1314 case AArch64::STLRW:
1315 case AArch64::STLRB:
1316 case AArch64::STLRH:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1317 case AArch64::STLLRW:
1318 case AArch64::STLLRB:
1319 case AArch64::STLLRH:
1320 case AArch64::LDLARW:
1321 case AArch64::LDLARB:
1322 case AArch64::LDLARH:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1323 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1324 break;
1325 case AArch64::STLXRX:
1326 case AArch64::STXRX:
1327 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1328 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1329 case AArch64::LDARX:
1330 case AArch64::LDAXRX:
1331 case AArch64::LDXRX:
1332 case AArch64::STLRX:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1333 case AArch64::LDLARX:
1334 case AArch64::STLLRX:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1335 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1336 break;
1337 case AArch64::STLXPW:
1338 case AArch64::STXPW:
1339 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1340 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1341 case AArch64::LDAXPW:
1342 case AArch64::LDXPW:
1343 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1344 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1345 break;
1346 case AArch64::STLXPX:
1347 case AArch64::STXPX:
1348 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1349 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1350 case AArch64::LDAXPX:
1351 case AArch64::LDXPX:
1352 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1353 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1354 break;
1355 }
1356
1357 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1358
1359 // You shouldn't load to the same register twice in an instruction...
1360 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1361 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1362 Rt == Rt2)
1363 return SoftFail;
1364
1365 return Success;
1366}
1367
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1368static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1369 uint64_t Addr,
1370 const void *Decoder) {
1371 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1372 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1373 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1374 int64_t offset = fieldFromInstruction(insn, 15, 7);
1375 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1376
1377 // offset is a 7-bit signed immediate, so sign extend it to
1378 // fill the unsigned.
1379 if (offset & (1 << (7 - 1)))
1380 offset |= ~((1LL << 7) - 1);
1381
1382 unsigned Opcode = Inst.getOpcode();
1383 bool NeedsDisjointWritebackTransfer = false;
1384
1385 // First operand is always writeback of base register.
1386 switch (Opcode) {
1387 default:
1388 break;
1389 case AArch64::LDPXpost:
1390 case AArch64::STPXpost:
1391 case AArch64::LDPSWpost:
1392 case AArch64::LDPXpre:
1393 case AArch64::STPXpre:
1394 case AArch64::LDPSWpre:
1395 case AArch64::LDPWpost:
1396 case AArch64::STPWpost:
1397 case AArch64::LDPWpre:
1398 case AArch64::STPWpre:
1399 case AArch64::LDPQpost:
1400 case AArch64::STPQpost:
1401 case AArch64::LDPQpre:
1402 case AArch64::STPQpre:
1403 case AArch64::LDPDpost:
1404 case AArch64::STPDpost:
1405 case AArch64::LDPDpre:
1406 case AArch64::STPDpre:
1407 case AArch64::LDPSpost:
1408 case AArch64::STPSpost:
1409 case AArch64::LDPSpre:
1410 case AArch64::STPSpre:
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]1411 case AArch64::STGPpre:
1412 case AArch64::STGPpost:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1413 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1414 break;
1415 }
1416
1417 switch (Opcode) {
1418 default:
1419 return Fail;
1420 case AArch64::LDPXpost:
1421 case AArch64::STPXpost:
1422 case AArch64::LDPSWpost:
1423 case AArch64::LDPXpre:
1424 case AArch64::STPXpre:
1425 case AArch64::LDPSWpre:
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]1426 case AArch64::STGPpre:
1427 case AArch64::STGPpost:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1428 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1429 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1430 case AArch64::LDNPXi:
1431 case AArch64::STNPXi:
1432 case AArch64::LDPXi:
1433 case AArch64::STPXi:
1434 case AArch64::LDPSWi:
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]1435 case AArch64::STGPi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1436 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1437 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1438 break;
1439 case AArch64::LDPWpost:
1440 case AArch64::STPWpost:
1441 case AArch64::LDPWpre:
1442 case AArch64::STPWpre:
1443 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1444 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1445 case AArch64::LDNPWi:
1446 case AArch64::STNPWi:
1447 case AArch64::LDPWi:
1448 case AArch64::STPWi:
1449 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1450 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1451 break;
1452 case AArch64::LDNPQi:
1453 case AArch64::STNPQi:
1454 case AArch64::LDPQpost:
1455 case AArch64::STPQpost:
1456 case AArch64::LDPQi:
1457 case AArch64::STPQi:
1458 case AArch64::LDPQpre:
1459 case AArch64::STPQpre:
1460 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1461 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1462 break;
1463 case AArch64::LDNPDi:
1464 case AArch64::STNPDi:
1465 case AArch64::LDPDpost:
1466 case AArch64::STPDpost:
1467 case AArch64::LDPDi:
1468 case AArch64::STPDi:
1469 case AArch64::LDPDpre:
1470 case AArch64::STPDpre:
1471 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1472 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1473 break;
1474 case AArch64::LDNPSi:
1475 case AArch64::STNPSi:
1476 case AArch64::LDPSpost:
1477 case AArch64::STPSpost:
1478 case AArch64::LDPSi:
1479 case AArch64::STPSi:
1480 case AArch64::LDPSpre:
1481 case AArch64::STPSpre:
1482 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1483 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1484 break;
1485 }
1486
1487 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1488 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1489
1490 // You shouldn't load to the same register twice in an instruction...
1491 if (IsLoad && Rt == Rt2)
1492 return SoftFail;
1493
1494 // ... or do any operation that writes-back to a transfer register. But note
1495 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1496 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1497 return SoftFail;
1498
1499 return Success;
1500}
1501
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1502static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1503 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1504 const void *Decoder) {
1505 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1506 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1507 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1508 unsigned extend = fieldFromInstruction(insn, 10, 6);
1509
1510 unsigned shift = extend & 0x7;
1511 if (shift > 4)
1512 return Fail;
1513
1514 switch (Inst.getOpcode()) {
1515 default:
1516 return Fail;
1517 case AArch64::ADDWrx:
1518 case AArch64::SUBWrx:
1519 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1520 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1521 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1522 break;
1523 case AArch64::ADDSWrx:
1524 case AArch64::SUBSWrx:
1525 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1526 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1527 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1528 break;
1529 case AArch64::ADDXrx:
1530 case AArch64::SUBXrx:
1531 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1532 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1533 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1534 break;
1535 case AArch64::ADDSXrx:
1536 case AArch64::SUBSXrx:
1537 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1538 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1539 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1540 break;
1541 case AArch64::ADDXrx64:
1542 case AArch64::SUBXrx64:
1543 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1544 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1545 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1546 break;
1547 case AArch64::SUBSXrx64:
1548 case AArch64::ADDSXrx64:
1549 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1550 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1551 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1552 break;
1553 }
1554
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1555 Inst.addOperand(MCOperand::createImm(extend));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1556 return Success;
1557}
1558
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1559static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1560 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1561 const void *Decoder) {
1562 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1563 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1564 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1565 unsigned imm;
1566
1567 if (Datasize) {
1568 if (Inst.getOpcode() == AArch64::ANDSXri)
1569 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1570 else
1571 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1572 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1573 imm = fieldFromInstruction(insn, 10, 13);
1574 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1575 return Fail;
1576 } else {
1577 if (Inst.getOpcode() == AArch64::ANDSWri)
1578 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1579 else
1580 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1581 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1582 imm = fieldFromInstruction(insn, 10, 12);
1583 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1584 return Fail;
1585 }
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1586 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1587 return Success;
1588}
1589
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1590static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1591 uint64_t Addr,
1592 const void *Decoder) {
1593 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1594 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1595 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1596 imm |= fieldFromInstruction(insn, 5, 5);
1597
1598 if (Inst.getOpcode() == AArch64::MOVID)
1599 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1600 else
1601 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1602
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1603 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1604
1605 switch (Inst.getOpcode()) {
1606 default:
1607 break;
1608 case AArch64::MOVIv4i16:
1609 case AArch64::MOVIv8i16:
1610 case AArch64::MVNIv4i16:
1611 case AArch64::MVNIv8i16:
1612 case AArch64::MOVIv2i32:
1613 case AArch64::MOVIv4i32:
1614 case AArch64::MVNIv2i32:
1615 case AArch64::MVNIv4i32:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1616 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1617 break;
1618 case AArch64::MOVIv2s_msl:
1619 case AArch64::MOVIv4s_msl:
1620 case AArch64::MVNIv2s_msl:
1621 case AArch64::MVNIv4s_msl:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1622 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1623 break;
1624 }
1625
1626 return Success;
1627}
1628
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1629static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1630 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1631 const void *Decoder) {
1632 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1633 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1634 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1635 imm |= fieldFromInstruction(insn, 5, 5);
1636
1637 // Tied operands added twice.
1638 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1639 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1640
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1641 Inst.addOperand(MCOperand::createImm(imm));
1642 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1643
1644 return Success;
1645}
1646
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1647static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1648 uint64_t Addr, const void *Decoder) {
1649 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1650 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1651 imm |= fieldFromInstruction(insn, 29, 2);
1652 const AArch64Disassembler *Dis =
1653 static_cast<const AArch64Disassembler *>(Decoder);
1654
1655 // Sign-extend the 21-bit immediate.
1656 if (imm & (1 << (21 - 1)))
1657 imm |= ~((1LL << 21) - 1);
1658
1659 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1660 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1661 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1662
1663 return Success;
1664}
1665
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]1666static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1667 uint64_t Addr, const void *Decoder) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1668 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1669 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1670 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1671 unsigned S = fieldFromInstruction(insn, 29, 1);
1672 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1673
1674 unsigned ShifterVal = (Imm >> 12) & 3;
1675 unsigned ImmVal = Imm & 0xFFF;
1676 const AArch64Disassembler *Dis =
1677 static_cast<const AArch64Disassembler *>(Decoder);
1678
1679 if (ShifterVal != 0 && ShifterVal != 1)
1680 return Fail;
1681
1682 if (Datasize) {
1683 if (Rd == 31 && !S)
1684 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1685 else
1686 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1687 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1688 } else {
1689 if (Rd == 31 && !S)
1690 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1691 else
1692 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1693 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1694 }
1695
1696 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1697 Inst.addOperand(MCOperand::createImm(ImmVal));
1698 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1699 return Success;
1700}
1701
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1702static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1703 uint64_t Addr,
1704 const void *Decoder) {
1705 int64_t imm = fieldFromInstruction(insn, 0, 26);
1706 const AArch64Disassembler *Dis =
1707 static_cast<const AArch64Disassembler *>(Decoder);
1708
1709 // Sign-extend the 26-bit immediate.
1710 if (imm & (1 << (26 - 1)))
1711 imm |= ~((1LL << 26) - 1);
1712
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1713 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1714 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1715
1716 return Success;
1717}
1718
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1719static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1720 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1721 const void *Decoder) {
1722 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1723 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1724 uint64_t crm = fieldFromInstruction(insn, 8, 4);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1725 uint64_t pstate_field = (op1 << 3) | op2;
1726
Oliver Stannard31af1782018-09-27 09:11:27 +0000[diff] [blame]1727 switch (pstate_field) {
1728 case 0x01: // XAFlag
1729 case 0x02: // AXFlag
1730 return Fail;
1731 }
1732
Oliver Stannard911ea202015-11-26 15:32:30 +0000[diff] [blame]1733 if ((pstate_field == AArch64PState::PAN ||
Oliver Stannard8459d342018-09-27 14:05:46 +0000[diff] [blame]1734 pstate_field == AArch64PState::UAO ||
1735 pstate_field == AArch64PState::SSBS) && crm > 1)
Alexandros Lamprineas1bab1912015-10-05 13:42:31 +0000[diff] [blame]1736 return Fail;
1737
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1738 Inst.addOperand(MCOperand::createImm(pstate_field));
1739 Inst.addOperand(MCOperand::createImm(crm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1740
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1741 const AArch64Disassembler *Dis =
Vladimir Sukhareva98f6892015-04-16 12:15:27 +0000[diff] [blame]1742 static_cast<const AArch64Disassembler *>(Decoder);
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1743 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1744 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1745 return Success;
1746 return Fail;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1747}
1748
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1749static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1750 uint64_t Addr, const void *Decoder) {
1751 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1752 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1753 bit |= fieldFromInstruction(insn, 19, 5);
1754 int64_t dst = fieldFromInstruction(insn, 5, 14);
1755 const AArch64Disassembler *Dis =
1756 static_cast<const AArch64Disassembler *>(Decoder);
1757
1758 // Sign-extend 14-bit immediate.
1759 if (dst & (1 << (14 - 1)))
1760 dst |= ~((1LL << 14) - 1);
1761
1762 if (fieldFromInstruction(insn, 31, 1) == 0)
1763 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1764 else
1765 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1766 Inst.addOperand(MCOperand::createImm(bit));
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1767 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1768 Inst.addOperand(MCOperand::createImm(dst));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1769
1770 return Success;
1771}
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1772
1773static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1774 unsigned RegClassID,
1775 unsigned RegNo,
1776 uint64_t Addr,
1777 const void *Decoder) {
1778 // Register number must be even (see CASP instruction)
1779 if (RegNo & 0x1)
1780 return Fail;
1781
1782 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
1783 Inst.addOperand(MCOperand::createReg(Register));
1784 return Success;
1785}
1786
1787static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1788 unsigned RegNo,
1789 uint64_t Addr,
1790 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1791 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1792 AArch64::WSeqPairsClassRegClassID,
1793 RegNo, Addr, Decoder);
1794}
1795
1796static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1797 unsigned RegNo,
1798 uint64_t Addr,
1799 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1800 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1801 AArch64::XSeqPairsClassRegClassID,
1802 RegNo, Addr, Decoder);
1803}
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1804
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]1805static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1806 uint32_t insn,
1807 uint64_t Addr,
1808 const void *Decoder) {
1809 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1810 unsigned imm = fieldFromInstruction(insn, 5, 13);
1811 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1812 return Fail;
1813
1814 // The same (tied) operand is added twice to the instruction.
1815 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
Sander de Smalen97ca6b92018-06-01 07:25:46 +0000[diff] [blame]1816 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1817 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]1818 Inst.addOperand(MCOperand::createImm(imm));
1819 return Success;
1820}
1821
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1822template<int Bits>
1823static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1824 uint64_t Address, const void *Decoder) {
1825 if (Imm & ~((1LL << Bits) - 1))
1826 return Fail;
1827
1828 // Imm is a signed immediate, so sign extend it.
1829 if (Imm & (1 << (Bits - 1)))
1830 Imm |= ~((1LL << Bits) - 1);
1831
1832 Inst.addOperand(MCOperand::createImm(Imm));
1833 return Success;
1834}
1835
Sander de Smalen62770792018-05-25 09:47:52 +0000[diff] [blame]1836// Decode 8-bit signed/unsigned immediate for a given element width.
1837template <int ElementWidth>
1838static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
1839 uint64_t Addr, const void *Decoder) {
1840 unsigned Val = (uint8_t)Imm;
1841 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1842 if (ElementWidth == 8 && Shift)
1843 return Fail;
1844 Inst.addOperand(MCOperand::createImm(Val));
1845 Inst.addOperand(MCOperand::createImm(Shift));
1846 return Success;
1847}
Sander de Smalen18ac8f92018-06-15 15:47:44 +0000[diff] [blame]1848
1849// Decode uimm4 ranged from 1-16.
1850static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1851 uint64_t Addr, const void *Decoder) {
1852 Inst.addOperand(MCOperand::createImm(Imm + 1));
1853 return Success;
1854}
Oliver Stannardc4190282018-10-02 10:04:39 +0000[diff] [blame]1855
1856static DecodeStatus DecodeLoadAllocTagArrayInstruction(MCInst &Inst,
1857 uint32_t insn,
1858 uint64_t address,
1859 const void* Decoder) {
1860 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1861 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1862
1863 // Outputs
1864 DecodeGPR64spRegisterClass(Inst, Rn, address, Decoder);
1865 DecodeGPR64RegisterClass(Inst, Rt, address, Decoder);
1866
1867 // Input (Rn again)
1868 Inst.addOperand(Inst.getOperand(0));
1869
1870 //Do this post decode since the raw number for xzr and sp is the same
1871 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
1872 return SoftFail;
1873 } else {
1874 return Success;
1875 }
1876}