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gerrit-public.fairphone.software / toolchain / llvm-project / 818431a61a45faeffdd876e55b57bc499d5f40a6 / . / llvm / lib / Target / AArch64 / AArch64LoadStoreOptimizer.cpp
blob: 0eebec63c3aab78404094ec46f40df56e94634c5 [file] [log] [blame]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1//=- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a pass that performs load / store related peephole
11// optimizations. This pass should be run after register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AArch64InstrInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]16#include "AArch64Subtarget.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]17#include "MCTargetDesc/AArch64AddressingModes.h"
18#include "llvm/ADT/BitVector.h"
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]19#include "llvm/ADT/SmallVector.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]20#include "llvm/ADT/Statistic.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/MachineInstr.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/raw_ostream.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]29#include "llvm/Target/TargetInstrInfo.h"
30#include "llvm/Target/TargetMachine.h"
31#include "llvm/Target/TargetRegisterInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]32using namespace llvm;
33
34#define DEBUG_TYPE "aarch64-ldst-opt"
35
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]36STATISTIC(NumPairCreated, "Number of load/store pair instructions generated");
37STATISTIC(NumPostFolded, "Number of post-index updates folded");
38STATISTIC(NumPreFolded, "Number of pre-index updates folded");
39STATISTIC(NumUnscaledPairCreated,
40 "Number of load/store from unscaled generated");
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]41STATISTIC(NumNarrowLoadsPromoted, "Number of narrow loads promoted");
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]42STATISTIC(NumZeroStoresPromoted, "Number of narrow zero stores promoted");
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]43STATISTIC(NumLoadsFromStoresPromoted, "Number of loads from stores promoted");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]44
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]45// The LdStLimit limits how far we search for load/store pairs.
46static cl::opt<unsigned> LdStLimit("aarch64-load-store-scan-limit",
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]47 cl::init(20), cl::Hidden);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]48
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]49// The UpdateLimit limits how far we search for update instructions when we form
50// pre-/post-index instructions.
51static cl::opt<unsigned> UpdateLimit("aarch64-update-scan-limit", cl::init(100),
52 cl::Hidden);
53
Jun Bum Lim33be4992016-05-06 15:08:57 +0000[diff] [blame]54static cl::opt<bool> EnableNarrowLdMerge("enable-narrow-ld-merge", cl::Hidden,
Jun Bum Limb21d4e12016-05-20 18:45:49 +0000[diff] [blame]55 cl::init(false),
Jun Bum Lim33be4992016-05-06 15:08:57 +0000[diff] [blame]56 cl::desc("Enable narrow load merge"));
57
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]58#define AARCH64_LOAD_STORE_OPT_NAME "AArch64 load / store optimization pass"
59
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]60namespace {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]61
62typedef struct LdStPairFlags {
63 // If a matching instruction is found, MergeForward is set to true if the
64 // merge is to remove the first instruction and replace the second with
65 // a pair-wise insn, and false if the reverse is true.
66 bool MergeForward;
67
68 // SExtIdx gives the index of the result of the load pair that must be
69 // extended. The value of SExtIdx assumes that the paired load produces the
70 // value in this order: (I, returned iterator), i.e., -1 means no value has
71 // to be extended, 0 means I, and 1 means the returned iterator.
72 int SExtIdx;
73
74 LdStPairFlags() : MergeForward(false), SExtIdx(-1) {}
75
76 void setMergeForward(bool V = true) { MergeForward = V; }
77 bool getMergeForward() const { return MergeForward; }
78
79 void setSExtIdx(int V) { SExtIdx = V; }
80 int getSExtIdx() const { return SExtIdx; }
81
82} LdStPairFlags;
83
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]84struct AArch64LoadStoreOpt : public MachineFunctionPass {
85 static char ID;
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]86 AArch64LoadStoreOpt() : MachineFunctionPass(ID) {
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]87 initializeAArch64LoadStoreOptPass(*PassRegistry::getPassRegistry());
88 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]89
90 const AArch64InstrInfo *TII;
91 const TargetRegisterInfo *TRI;
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]92 const AArch64Subtarget *Subtarget;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]93
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]94 // Track which registers have been modified and used.
95 BitVector ModifiedRegs, UsedRegs;
96
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]97 // Scan the instructions looking for a load/store that can be combined
98 // with the current instruction into a load/store pair.
99 // Return the matching instruction if one is found, else MBB->end().
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]100 MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]101 LdStPairFlags &Flags,
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]102 unsigned Limit,
103 bool FindNarrowMerge);
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]104
105 // Scan the instructions looking for a store that writes to the address from
106 // which the current load instruction reads. Return true if one is found.
107 bool findMatchingStore(MachineBasicBlock::iterator I, unsigned Limit,
108 MachineBasicBlock::iterator &StoreI);
109
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]110 // Merge the two instructions indicated into a wider instruction.
111 MachineBasicBlock::iterator
112 mergeNarrowInsns(MachineBasicBlock::iterator I,
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]113 MachineBasicBlock::iterator MergeMI,
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]114 const LdStPairFlags &Flags);
115
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]116 // Merge the two instructions indicated into a single pair-wise instruction.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]117 MachineBasicBlock::iterator
118 mergePairedInsns(MachineBasicBlock::iterator I,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]119 MachineBasicBlock::iterator Paired,
Chad Rosierfe5399f2015-07-21 17:47:56 +0000[diff] [blame]120 const LdStPairFlags &Flags);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]121
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]122 // Promote the load that reads directly from the address stored to.
123 MachineBasicBlock::iterator
124 promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
125 MachineBasicBlock::iterator StoreI);
126
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]127 // Scan the instruction list to find a base register update that can
128 // be combined with the current instruction (a load or store) using
129 // pre or post indexed addressing with writeback. Scan forwards.
130 MachineBasicBlock::iterator
Chad Rosier234bf6f2016-01-18 21:56:40 +0000[diff] [blame]131 findMatchingUpdateInsnForward(MachineBasicBlock::iterator I,
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]132 int UnscaledOffset, unsigned Limit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]133
134 // Scan the instruction list to find a base register update that can
135 // be combined with the current instruction (a load or store) using
136 // pre or post indexed addressing with writeback. Scan backwards.
137 MachineBasicBlock::iterator
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]138 findMatchingUpdateInsnBackward(MachineBasicBlock::iterator I, unsigned Limit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]139
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]140 // Find an instruction that updates the base register of the ld/st
141 // instruction.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]142 bool isMatchingUpdateInsn(MachineInstr &MemMI, MachineInstr &MI,
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]143 unsigned BaseReg, int Offset);
144
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]145 // Merge a pre- or post-index base register update into a ld/st instruction.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]146 MachineBasicBlock::iterator
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]147 mergeUpdateInsn(MachineBasicBlock::iterator I,
148 MachineBasicBlock::iterator Update, bool IsPreIdx);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]149
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]150 // Find and merge foldable ldr/str instructions.
151 bool tryToMergeLdStInst(MachineBasicBlock::iterator &MBBI);
152
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]153 // Find and pair ldr/str instructions.
154 bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
155
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]156 // Find and promote load instructions which read directly from store.
157 bool tryToPromoteLoadFromStore(MachineBasicBlock::iterator &MBBI);
158
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]159 bool optimizeBlock(MachineBasicBlock &MBB, bool enableNarrowLdOpt);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]160
161 bool runOnMachineFunction(MachineFunction &Fn) override;
162
Derek Schuff1dbf7a52016-04-04 17:09:25 +0000[diff] [blame]163 MachineFunctionProperties getRequiredProperties() const override {
164 return MachineFunctionProperties().set(
Matthias Braun1eb47362016-08-25 01:27:13 +0000[diff] [blame]165 MachineFunctionProperties::Property::NoVRegs);
Derek Schuff1dbf7a52016-04-04 17:09:25 +0000[diff] [blame]166 }
167
Mehdi Amini117296c2016-10-01 02:56:57 +0000[diff] [blame]168 StringRef getPassName() const override { return AARCH64_LOAD_STORE_OPT_NAME; }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]169};
170char AArch64LoadStoreOpt::ID = 0;
Jim Grosbach1eee3df2014-08-11 22:42:31 +0000[diff] [blame]171} // namespace
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]172
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]173INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
174 AARCH64_LOAD_STORE_OPT_NAME, false, false)
175
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]176static unsigned getBitExtrOpcode(MachineInstr &MI) {
177 switch (MI.getOpcode()) {
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]178 default:
179 llvm_unreachable("Unexpected opcode.");
180 case AArch64::LDRBBui:
181 case AArch64::LDURBBi:
182 case AArch64::LDRHHui:
183 case AArch64::LDURHHi:
184 return AArch64::UBFMWri;
185 case AArch64::LDRSBWui:
186 case AArch64::LDURSBWi:
187 case AArch64::LDRSHWui:
188 case AArch64::LDURSHWi:
189 return AArch64::SBFMWri;
190 }
191}
192
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]193static bool isNarrowStore(unsigned Opc) {
194 switch (Opc) {
195 default:
196 return false;
197 case AArch64::STRBBui:
198 case AArch64::STURBBi:
199 case AArch64::STRHHui:
200 case AArch64::STURHHi:
201 return true;
202 }
203}
204
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]205static bool isNarrowLoad(unsigned Opc) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]206 switch (Opc) {
207 default:
208 return false;
209 case AArch64::LDRHHui:
210 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]211 case AArch64::LDRBBui:
212 case AArch64::LDURBBi:
213 case AArch64::LDRSHWui:
214 case AArch64::LDURSHWi:
215 case AArch64::LDRSBWui:
216 case AArch64::LDURSBWi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]217 return true;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]218 }
219}
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]220
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]221static bool isNarrowLoad(MachineInstr &MI) {
222 return isNarrowLoad(MI.getOpcode());
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]223}
224
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]225static bool isNarrowLoadOrStore(unsigned Opc) {
226 return isNarrowLoad(Opc) || isNarrowStore(Opc);
227}
228
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]229// Scaling factor for unscaled load or store.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]230static int getMemScale(MachineInstr &MI) {
231 switch (MI.getOpcode()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]232 default:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]233 llvm_unreachable("Opcode has unknown scale!");
234 case AArch64::LDRBBui:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]235 case AArch64::LDURBBi:
236 case AArch64::LDRSBWui:
237 case AArch64::LDURSBWi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]238 case AArch64::STRBBui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]239 case AArch64::STURBBi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]240 return 1;
241 case AArch64::LDRHHui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]242 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]243 case AArch64::LDRSHWui:
244 case AArch64::LDURSHWi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]245 case AArch64::STRHHui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]246 case AArch64::STURHHi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]247 return 2;
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]248 case AArch64::LDRSui:
249 case AArch64::LDURSi:
250 case AArch64::LDRSWui:
251 case AArch64::LDURSWi:
252 case AArch64::LDRWui:
253 case AArch64::LDURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]254 case AArch64::STRSui:
255 case AArch64::STURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]256 case AArch64::STRWui:
257 case AArch64::STURWi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]258 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]259 case AArch64::LDPSWi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]260 case AArch64::LDPWi:
261 case AArch64::STPSi:
262 case AArch64::STPWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]263 return 4;
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]264 case AArch64::LDRDui:
265 case AArch64::LDURDi:
266 case AArch64::LDRXui:
267 case AArch64::LDURXi:
268 case AArch64::STRDui:
269 case AArch64::STURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]270 case AArch64::STRXui:
271 case AArch64::STURXi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]272 case AArch64::LDPDi:
273 case AArch64::LDPXi:
274 case AArch64::STPDi:
275 case AArch64::STPXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]276 return 8;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]277 case AArch64::LDRQui:
278 case AArch64::LDURQi:
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]279 case AArch64::STRQui:
280 case AArch64::STURQi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]281 case AArch64::LDPQi:
282 case AArch64::STPQi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]283 return 16;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]284 }
285}
286
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]287static unsigned getMatchingNonSExtOpcode(unsigned Opc,
288 bool *IsValidLdStrOpc = nullptr) {
289 if (IsValidLdStrOpc)
290 *IsValidLdStrOpc = true;
291 switch (Opc) {
292 default:
293 if (IsValidLdStrOpc)
294 *IsValidLdStrOpc = false;
295 return UINT_MAX;
296 case AArch64::STRDui:
297 case AArch64::STURDi:
298 case AArch64::STRQui:
299 case AArch64::STURQi:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]300 case AArch64::STRBBui:
301 case AArch64::STURBBi:
302 case AArch64::STRHHui:
303 case AArch64::STURHHi:
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]304 case AArch64::STRWui:
305 case AArch64::STURWi:
306 case AArch64::STRXui:
307 case AArch64::STURXi:
308 case AArch64::LDRDui:
309 case AArch64::LDURDi:
310 case AArch64::LDRQui:
311 case AArch64::LDURQi:
312 case AArch64::LDRWui:
313 case AArch64::LDURWi:
314 case AArch64::LDRXui:
315 case AArch64::LDURXi:
316 case AArch64::STRSui:
317 case AArch64::STURSi:
318 case AArch64::LDRSui:
319 case AArch64::LDURSi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]320 case AArch64::LDRHHui:
321 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]322 case AArch64::LDRBBui:
323 case AArch64::LDURBBi:
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]324 return Opc;
325 case AArch64::LDRSWui:
326 return AArch64::LDRWui;
327 case AArch64::LDURSWi:
328 return AArch64::LDURWi;
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]329 case AArch64::LDRSBWui:
330 return AArch64::LDRBBui;
331 case AArch64::LDRSHWui:
332 return AArch64::LDRHHui;
333 case AArch64::LDURSBWi:
334 return AArch64::LDURBBi;
335 case AArch64::LDURSHWi:
336 return AArch64::LDURHHi;
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]337 }
338}
339
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame]340static unsigned getMatchingWideOpcode(unsigned Opc) {
341 switch (Opc) {
342 default:
343 llvm_unreachable("Opcode has no wide equivalent!");
344 case AArch64::STRBBui:
345 return AArch64::STRHHui;
346 case AArch64::STRHHui:
347 return AArch64::STRWui;
348 case AArch64::STURBBi:
349 return AArch64::STURHHi;
350 case AArch64::STURHHi:
351 return AArch64::STURWi;
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]352 case AArch64::STURWi:
353 return AArch64::STURXi;
354 case AArch64::STRWui:
355 return AArch64::STRXui;
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame]356 case AArch64::LDRHHui:
357 case AArch64::LDRSHWui:
358 return AArch64::LDRWui;
359 case AArch64::LDURHHi:
360 case AArch64::LDURSHWi:
361 return AArch64::LDURWi;
362 case AArch64::LDRBBui:
363 case AArch64::LDRSBWui:
364 return AArch64::LDRHHui;
365 case AArch64::LDURBBi:
366 case AArch64::LDURSBWi:
367 return AArch64::LDURHHi;
368 }
369}
370
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]371static unsigned getMatchingPairOpcode(unsigned Opc) {
372 switch (Opc) {
373 default:
374 llvm_unreachable("Opcode has no pairwise equivalent!");
375 case AArch64::STRSui:
376 case AArch64::STURSi:
377 return AArch64::STPSi;
378 case AArch64::STRDui:
379 case AArch64::STURDi:
380 return AArch64::STPDi;
381 case AArch64::STRQui:
382 case AArch64::STURQi:
383 return AArch64::STPQi;
384 case AArch64::STRWui:
385 case AArch64::STURWi:
386 return AArch64::STPWi;
387 case AArch64::STRXui:
388 case AArch64::STURXi:
389 return AArch64::STPXi;
390 case AArch64::LDRSui:
391 case AArch64::LDURSi:
392 return AArch64::LDPSi;
393 case AArch64::LDRDui:
394 case AArch64::LDURDi:
395 return AArch64::LDPDi;
396 case AArch64::LDRQui:
397 case AArch64::LDURQi:
398 return AArch64::LDPQi;
399 case AArch64::LDRWui:
400 case AArch64::LDURWi:
401 return AArch64::LDPWi;
402 case AArch64::LDRXui:
403 case AArch64::LDURXi:
404 return AArch64::LDPXi;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]405 case AArch64::LDRSWui:
406 case AArch64::LDURSWi:
407 return AArch64::LDPSWi;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]408 }
409}
410
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]411static unsigned isMatchingStore(MachineInstr &LoadInst,
412 MachineInstr &StoreInst) {
413 unsigned LdOpc = LoadInst.getOpcode();
414 unsigned StOpc = StoreInst.getOpcode();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]415 switch (LdOpc) {
416 default:
417 llvm_unreachable("Unsupported load instruction!");
418 case AArch64::LDRBBui:
419 return StOpc == AArch64::STRBBui || StOpc == AArch64::STRHHui ||
420 StOpc == AArch64::STRWui || StOpc == AArch64::STRXui;
421 case AArch64::LDURBBi:
422 return StOpc == AArch64::STURBBi || StOpc == AArch64::STURHHi ||
423 StOpc == AArch64::STURWi || StOpc == AArch64::STURXi;
424 case AArch64::LDRHHui:
425 return StOpc == AArch64::STRHHui || StOpc == AArch64::STRWui ||
426 StOpc == AArch64::STRXui;
427 case AArch64::LDURHHi:
428 return StOpc == AArch64::STURHHi || StOpc == AArch64::STURWi ||
429 StOpc == AArch64::STURXi;
430 case AArch64::LDRWui:
431 return StOpc == AArch64::STRWui || StOpc == AArch64::STRXui;
432 case AArch64::LDURWi:
433 return StOpc == AArch64::STURWi || StOpc == AArch64::STURXi;
434 case AArch64::LDRXui:
435 return StOpc == AArch64::STRXui;
436 case AArch64::LDURXi:
437 return StOpc == AArch64::STURXi;
438 }
439}
440
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]441static unsigned getPreIndexedOpcode(unsigned Opc) {
442 switch (Opc) {
443 default:
444 llvm_unreachable("Opcode has no pre-indexed equivalent!");
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]445 case AArch64::STRSui:
446 return AArch64::STRSpre;
447 case AArch64::STRDui:
448 return AArch64::STRDpre;
449 case AArch64::STRQui:
450 return AArch64::STRQpre;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]451 case AArch64::STRBBui:
452 return AArch64::STRBBpre;
453 case AArch64::STRHHui:
454 return AArch64::STRHHpre;
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]455 case AArch64::STRWui:
456 return AArch64::STRWpre;
457 case AArch64::STRXui:
458 return AArch64::STRXpre;
459 case AArch64::LDRSui:
460 return AArch64::LDRSpre;
461 case AArch64::LDRDui:
462 return AArch64::LDRDpre;
463 case AArch64::LDRQui:
464 return AArch64::LDRQpre;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]465 case AArch64::LDRBBui:
466 return AArch64::LDRBBpre;
467 case AArch64::LDRHHui:
468 return AArch64::LDRHHpre;
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]469 case AArch64::LDRWui:
470 return AArch64::LDRWpre;
471 case AArch64::LDRXui:
472 return AArch64::LDRXpre;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]473 case AArch64::LDRSWui:
474 return AArch64::LDRSWpre;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]475 case AArch64::LDPSi:
476 return AArch64::LDPSpre;
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]477 case AArch64::LDPSWi:
478 return AArch64::LDPSWpre;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]479 case AArch64::LDPDi:
480 return AArch64::LDPDpre;
481 case AArch64::LDPQi:
482 return AArch64::LDPQpre;
483 case AArch64::LDPWi:
484 return AArch64::LDPWpre;
485 case AArch64::LDPXi:
486 return AArch64::LDPXpre;
487 case AArch64::STPSi:
488 return AArch64::STPSpre;
489 case AArch64::STPDi:
490 return AArch64::STPDpre;
491 case AArch64::STPQi:
492 return AArch64::STPQpre;
493 case AArch64::STPWi:
494 return AArch64::STPWpre;
495 case AArch64::STPXi:
496 return AArch64::STPXpre;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]497 }
498}
499
500static unsigned getPostIndexedOpcode(unsigned Opc) {
501 switch (Opc) {
502 default:
503 llvm_unreachable("Opcode has no post-indexed wise equivalent!");
504 case AArch64::STRSui:
505 return AArch64::STRSpost;
506 case AArch64::STRDui:
507 return AArch64::STRDpost;
508 case AArch64::STRQui:
509 return AArch64::STRQpost;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]510 case AArch64::STRBBui:
511 return AArch64::STRBBpost;
512 case AArch64::STRHHui:
513 return AArch64::STRHHpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]514 case AArch64::STRWui:
515 return AArch64::STRWpost;
516 case AArch64::STRXui:
517 return AArch64::STRXpost;
518 case AArch64::LDRSui:
519 return AArch64::LDRSpost;
520 case AArch64::LDRDui:
521 return AArch64::LDRDpost;
522 case AArch64::LDRQui:
523 return AArch64::LDRQpost;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]524 case AArch64::LDRBBui:
525 return AArch64::LDRBBpost;
526 case AArch64::LDRHHui:
527 return AArch64::LDRHHpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]528 case AArch64::LDRWui:
529 return AArch64::LDRWpost;
530 case AArch64::LDRXui:
531 return AArch64::LDRXpost;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]532 case AArch64::LDRSWui:
533 return AArch64::LDRSWpost;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]534 case AArch64::LDPSi:
535 return AArch64::LDPSpost;
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]536 case AArch64::LDPSWi:
537 return AArch64::LDPSWpost;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]538 case AArch64::LDPDi:
539 return AArch64::LDPDpost;
540 case AArch64::LDPQi:
541 return AArch64::LDPQpost;
542 case AArch64::LDPWi:
543 return AArch64::LDPWpost;
544 case AArch64::LDPXi:
545 return AArch64::LDPXpost;
546 case AArch64::STPSi:
547 return AArch64::STPSpost;
548 case AArch64::STPDi:
549 return AArch64::STPDpost;
550 case AArch64::STPQi:
551 return AArch64::STPQpost;
552 case AArch64::STPWi:
553 return AArch64::STPWpost;
554 case AArch64::STPXi:
555 return AArch64::STPXpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]556 }
557}
558
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]559static bool isPairedLdSt(const MachineInstr &MI) {
560 switch (MI.getOpcode()) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]561 default:
562 return false;
563 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]564 case AArch64::LDPSWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]565 case AArch64::LDPDi:
566 case AArch64::LDPQi:
567 case AArch64::LDPWi:
568 case AArch64::LDPXi:
569 case AArch64::STPSi:
570 case AArch64::STPDi:
571 case AArch64::STPQi:
572 case AArch64::STPWi:
573 case AArch64::STPXi:
574 return true;
575 }
576}
577
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]578static const MachineOperand &getLdStRegOp(const MachineInstr &MI,
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]579 unsigned PairedRegOp = 0) {
580 assert(PairedRegOp < 2 && "Unexpected register operand idx.");
581 unsigned Idx = isPairedLdSt(MI) ? PairedRegOp : 0;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]582 return MI.getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]583}
584
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]585static const MachineOperand &getLdStBaseOp(const MachineInstr &MI) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]586 unsigned Idx = isPairedLdSt(MI) ? 2 : 1;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]587 return MI.getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]588}
589
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]590static const MachineOperand &getLdStOffsetOp(const MachineInstr &MI) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]591 unsigned Idx = isPairedLdSt(MI) ? 3 : 2;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]592 return MI.getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]593}
594
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]595static bool isLdOffsetInRangeOfSt(MachineInstr &LoadInst,
596 MachineInstr &StoreInst,
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]597 const AArch64InstrInfo *TII) {
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]598 assert(isMatchingStore(LoadInst, StoreInst) && "Expect only matched ld/st.");
599 int LoadSize = getMemScale(LoadInst);
600 int StoreSize = getMemScale(StoreInst);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]601 int UnscaledStOffset = TII->isUnscaledLdSt(StoreInst)
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]602 ? getLdStOffsetOp(StoreInst).getImm()
603 : getLdStOffsetOp(StoreInst).getImm() * StoreSize;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]604 int UnscaledLdOffset = TII->isUnscaledLdSt(LoadInst)
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]605 ? getLdStOffsetOp(LoadInst).getImm()
606 : getLdStOffsetOp(LoadInst).getImm() * LoadSize;
607 return (UnscaledStOffset <= UnscaledLdOffset) &&
608 (UnscaledLdOffset + LoadSize <= (UnscaledStOffset + StoreSize));
609}
610
Jun Bum Lim33be4992016-05-06 15:08:57 +0000[diff] [blame]611static bool isPromotableZeroStoreOpcode(unsigned Opc) {
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]612 return isNarrowStore(Opc) || Opc == AArch64::STRWui || Opc == AArch64::STURWi;
613}
614
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]615static bool isPromotableZeroStoreOpcode(MachineInstr &MI) {
616 return isPromotableZeroStoreOpcode(MI.getOpcode());
Jun Bum Lim33be4992016-05-06 15:08:57 +0000[diff] [blame]617}
618
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]619static bool isPromotableZeroStoreInst(MachineInstr &MI) {
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]620 return (isPromotableZeroStoreOpcode(MI)) &&
621 getLdStRegOp(MI).getReg() == AArch64::WZR;
622}
623
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]624MachineBasicBlock::iterator
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]625AArch64LoadStoreOpt::mergeNarrowInsns(MachineBasicBlock::iterator I,
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]626 MachineBasicBlock::iterator MergeMI,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]627 const LdStPairFlags &Flags) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]628 MachineBasicBlock::iterator NextI = I;
629 ++NextI;
630 // If NextI is the second of the two instructions to be merged, we need
631 // to skip one further. Either way we merge will invalidate the iterator,
632 // and we don't need to scan the new instruction, as it's a pairwise
633 // instruction, which we're not considering for further action anyway.
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]634 if (NextI == MergeMI)
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]635 ++NextI;
636
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]637 unsigned Opc = I->getOpcode();
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]638 bool IsScaled = !TII->isUnscaledLdSt(Opc);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]639 int OffsetStride = IsScaled ? 1 : getMemScale(*I);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]640
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]641 bool MergeForward = Flags.getMergeForward();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]642 // Insert our new paired instruction after whichever of the paired
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]643 // instructions MergeForward indicates.
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]644 MachineBasicBlock::iterator InsertionPoint = MergeForward ? MergeMI : I;
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]645 // Also based on MergeForward is from where we copy the base register operand
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]646 // so we get the flags compatible with the input code.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]647 const MachineOperand &BaseRegOp =
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]648 MergeForward ? getLdStBaseOp(*MergeMI) : getLdStBaseOp(*I);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]649
650 // Which register is Rt and which is Rt2 depends on the offset order.
651 MachineInstr *RtMI, *Rt2MI;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]652 if (getLdStOffsetOp(*I).getImm() ==
653 getLdStOffsetOp(*MergeMI).getImm() + OffsetStride) {
654 RtMI = &*MergeMI;
655 Rt2MI = &*I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]656 } else {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]657 RtMI = &*I;
658 Rt2MI = &*MergeMI;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]659 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]660
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]661 int OffsetImm = getLdStOffsetOp(*RtMI).getImm();
Chad Rosier11eedc92016-02-09 19:17:18 +0000[diff] [blame]662 // Change the scaled offset from small to large type.
663 if (IsScaled) {
664 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge");
665 OffsetImm /= 2;
666 }
667
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]668 DebugLoc DL = I->getDebugLoc();
669 MachineBasicBlock *MBB = I->getParent();
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]670 if (isNarrowLoad(Opc)) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]671 MachineInstr *RtNewDest = &*(MergeForward ? I : MergeMI);
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]672 // When merging small (< 32 bit) loads for big-endian targets, the order of
673 // the component parts gets swapped.
674 if (!Subtarget->isLittleEndian())
675 std::swap(RtMI, Rt2MI);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]676 // Construct the new load instruction.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]677 MachineInstr *NewMemMI, *BitExtMI1, *BitExtMI2;
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]678 NewMemMI =
679 BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingWideOpcode(Opc)))
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]680 .addOperand(getLdStRegOp(*RtNewDest))
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]681 .addOperand(BaseRegOp)
682 .addImm(OffsetImm)
683 .setMemRefs(I->mergeMemRefsWith(*MergeMI));
Chad Rosierf7ac5f22016-03-30 18:08:51 +0000[diff] [blame]684 (void)NewMemMI;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]685
686 DEBUG(
687 dbgs()
688 << "Creating the new load and extract. Replacing instructions:\n ");
689 DEBUG(I->print(dbgs()));
690 DEBUG(dbgs() << " ");
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]691 DEBUG(MergeMI->print(dbgs()));
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]692 DEBUG(dbgs() << " with instructions:\n ");
693 DEBUG((NewMemMI)->print(dbgs()));
694
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]695 int Width = getMemScale(*I) == 1 ? 8 : 16;
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]696 int LSBLow = 0;
697 int LSBHigh = Width;
698 int ImmsLow = LSBLow + Width - 1;
699 int ImmsHigh = LSBHigh + Width - 1;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]700 MachineInstr *ExtDestMI = &*(MergeForward ? MergeMI : I);
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]701 if ((ExtDestMI == Rt2MI) == Subtarget->isLittleEndian()) {
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]702 // Create the bitfield extract for high bits.
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]703 BitExtMI1 =
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]704 BuildMI(*MBB, InsertionPoint, DL, TII->get(getBitExtrOpcode(*Rt2MI)))
705 .addOperand(getLdStRegOp(*Rt2MI))
706 .addReg(getLdStRegOp(*RtNewDest).getReg())
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]707 .addImm(LSBHigh)
708 .addImm(ImmsHigh);
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]709 // Create the bitfield extract for low bits.
710 if (RtMI->getOpcode() == getMatchingNonSExtOpcode(RtMI->getOpcode())) {
711 // For unsigned, prefer to use AND for low bits.
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]712 BitExtMI2 = BuildMI(*MBB, InsertionPoint, DL, TII->get(AArch64::ANDWri))
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]713 .addOperand(getLdStRegOp(*RtMI))
714 .addReg(getLdStRegOp(*RtNewDest).getReg())
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]715 .addImm(ImmsLow);
716 } else {
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]717 BitExtMI2 =
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]718 BuildMI(*MBB, InsertionPoint, DL, TII->get(getBitExtrOpcode(*RtMI)))
719 .addOperand(getLdStRegOp(*RtMI))
720 .addReg(getLdStRegOp(*RtNewDest).getReg())
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]721 .addImm(LSBLow)
722 .addImm(ImmsLow);
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]723 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]724 } else {
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]725 // Create the bitfield extract for low bits.
726 if (RtMI->getOpcode() == getMatchingNonSExtOpcode(RtMI->getOpcode())) {
727 // For unsigned, prefer to use AND for low bits.
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]728 BitExtMI1 = BuildMI(*MBB, InsertionPoint, DL, TII->get(AArch64::ANDWri))
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]729 .addOperand(getLdStRegOp(*RtMI))
730 .addReg(getLdStRegOp(*RtNewDest).getReg())
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]731 .addImm(ImmsLow);
732 } else {
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]733 BitExtMI1 =
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]734 BuildMI(*MBB, InsertionPoint, DL, TII->get(getBitExtrOpcode(*RtMI)))
735 .addOperand(getLdStRegOp(*RtMI))
736 .addReg(getLdStRegOp(*RtNewDest).getReg())
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]737 .addImm(LSBLow)
738 .addImm(ImmsLow);
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]739 }
740
741 // Create the bitfield extract for high bits.
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]742 BitExtMI2 =
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]743 BuildMI(*MBB, InsertionPoint, DL, TII->get(getBitExtrOpcode(*Rt2MI)))
744 .addOperand(getLdStRegOp(*Rt2MI))
745 .addReg(getLdStRegOp(*RtNewDest).getReg())
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]746 .addImm(LSBHigh)
747 .addImm(ImmsHigh);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]748 }
Chad Rosierf7ac5f22016-03-30 18:08:51 +0000[diff] [blame]749 (void)BitExtMI1;
750 (void)BitExtMI2;
751
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]752 DEBUG(dbgs() << " ");
753 DEBUG((BitExtMI1)->print(dbgs()));
754 DEBUG(dbgs() << " ");
755 DEBUG((BitExtMI2)->print(dbgs()));
756 DEBUG(dbgs() << "\n");
757
758 // Erase the old instructions.
759 I->eraseFromParent();
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]760 MergeMI->eraseFromParent();
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]761 return NextI;
762 }
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]763 assert(isPromotableZeroStoreInst(*I) && isPromotableZeroStoreInst(*MergeMI) &&
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]764 "Expected promotable zero store");
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]765
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]766 // Construct the new instruction.
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]767 MachineInstrBuilder MIB;
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]768 MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingWideOpcode(Opc)))
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]769 .addReg(isNarrowStore(Opc) ? AArch64::WZR : AArch64::XZR)
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]770 .addOperand(BaseRegOp)
771 .addImm(OffsetImm)
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]772 .setMemRefs(I->mergeMemRefsWith(*MergeMI));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]773 (void)MIB;
774
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]775 DEBUG(dbgs() << "Creating wider load/store. Replacing instructions:\n ");
776 DEBUG(I->print(dbgs()));
777 DEBUG(dbgs() << " ");
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]778 DEBUG(MergeMI->print(dbgs()));
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]779 DEBUG(dbgs() << " with instruction:\n ");
780 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
781 DEBUG(dbgs() << "\n");
782
783 // Erase the old instructions.
784 I->eraseFromParent();
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]785 MergeMI->eraseFromParent();
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]786 return NextI;
787}
788
789MachineBasicBlock::iterator
790AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
791 MachineBasicBlock::iterator Paired,
792 const LdStPairFlags &Flags) {
793 MachineBasicBlock::iterator NextI = I;
794 ++NextI;
795 // If NextI is the second of the two instructions to be merged, we need
796 // to skip one further. Either way we merge will invalidate the iterator,
797 // and we don't need to scan the new instruction, as it's a pairwise
798 // instruction, which we're not considering for further action anyway.
799 if (NextI == Paired)
800 ++NextI;
801
802 int SExtIdx = Flags.getSExtIdx();
803 unsigned Opc =
804 SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]805 bool IsUnscaled = TII->isUnscaledLdSt(Opc);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]806 int OffsetStride = IsUnscaled ? getMemScale(*I) : 1;
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]807
808 bool MergeForward = Flags.getMergeForward();
809 // Insert our new paired instruction after whichever of the paired
810 // instructions MergeForward indicates.
811 MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
812 // Also based on MergeForward is from where we copy the base register operand
813 // so we get the flags compatible with the input code.
814 const MachineOperand &BaseRegOp =
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]815 MergeForward ? getLdStBaseOp(*Paired) : getLdStBaseOp(*I);
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]816
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]817 int Offset = getLdStOffsetOp(*I).getImm();
818 int PairedOffset = getLdStOffsetOp(*Paired).getImm();
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]819 bool PairedIsUnscaled = TII->isUnscaledLdSt(Paired->getOpcode());
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]820 if (IsUnscaled != PairedIsUnscaled) {
821 // We're trying to pair instructions that differ in how they are scaled. If
822 // I is scaled then scale the offset of Paired accordingly. Otherwise, do
823 // the opposite (i.e., make Paired's offset unscaled).
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]824 int MemSize = getMemScale(*Paired);
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]825 if (PairedIsUnscaled) {
826 // If the unscaled offset isn't a multiple of the MemSize, we can't
827 // pair the operations together.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]828 assert(!(PairedOffset % getMemScale(*Paired)) &&
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]829 "Offset should be a multiple of the stride!");
830 PairedOffset /= MemSize;
831 } else {
832 PairedOffset *= MemSize;
833 }
834 }
835
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]836 // Which register is Rt and which is Rt2 depends on the offset order.
837 MachineInstr *RtMI, *Rt2MI;
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]838 if (Offset == PairedOffset + OffsetStride) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]839 RtMI = &*Paired;
840 Rt2MI = &*I;
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]841 // Here we swapped the assumption made for SExtIdx.
842 // I.e., we turn ldp I, Paired into ldp Paired, I.
843 // Update the index accordingly.
844 if (SExtIdx != -1)
845 SExtIdx = (SExtIdx + 1) % 2;
846 } else {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]847 RtMI = &*I;
848 Rt2MI = &*Paired;
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]849 }
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]850 int OffsetImm = getLdStOffsetOp(*RtMI).getImm();
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]851 // Scale the immediate offset, if necessary.
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]852 if (TII->isUnscaledLdSt(RtMI->getOpcode())) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]853 assert(!(OffsetImm % getMemScale(*RtMI)) &&
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]854 "Unscaled offset cannot be scaled.");
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]855 OffsetImm /= getMemScale(*RtMI);
Chad Rosier87e33412016-02-09 20:18:07 +0000[diff] [blame]856 }
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]857
858 // Construct the new instruction.
859 MachineInstrBuilder MIB;
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]860 DebugLoc DL = I->getDebugLoc();
861 MachineBasicBlock *MBB = I->getParent();
862 MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingPairOpcode(Opc)))
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]863 .addOperand(getLdStRegOp(*RtMI))
864 .addOperand(getLdStRegOp(*Rt2MI))
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]865 .addOperand(BaseRegOp)
Chad Rosiere40b9512016-03-08 17:16:38 +0000[diff] [blame]866 .addImm(OffsetImm)
867 .setMemRefs(I->mergeMemRefsWith(*Paired));
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]868
869 (void)MIB;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]870
871 DEBUG(dbgs() << "Creating pair load/store. Replacing instructions:\n ");
872 DEBUG(I->print(dbgs()));
873 DEBUG(dbgs() << " ");
874 DEBUG(Paired->print(dbgs()));
875 DEBUG(dbgs() << " with instruction:\n ");
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]876 if (SExtIdx != -1) {
877 // Generate the sign extension for the proper result of the ldp.
878 // I.e., with X1, that would be:
879 // %W1<def> = KILL %W1, %X1<imp-def>
880 // %X1<def> = SBFMXri %X1<kill>, 0, 31
881 MachineOperand &DstMO = MIB->getOperand(SExtIdx);
882 // Right now, DstMO has the extended register, since it comes from an
883 // extended opcode.
884 unsigned DstRegX = DstMO.getReg();
885 // Get the W variant of that register.
886 unsigned DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);
887 // Update the result of LDP to use the W instead of the X variant.
888 DstMO.setReg(DstRegW);
889 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
890 DEBUG(dbgs() << "\n");
891 // Make the machine verifier happy by providing a definition for
892 // the X register.
893 // Insert this definition right after the generated LDP, i.e., before
894 // InsertionPoint.
895 MachineInstrBuilder MIBKill =
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]896 BuildMI(*MBB, InsertionPoint, DL, TII->get(TargetOpcode::KILL), DstRegW)
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]897 .addReg(DstRegW)
898 .addReg(DstRegX, RegState::Define);
899 MIBKill->getOperand(2).setImplicit();
900 // Create the sign extension.
901 MachineInstrBuilder MIBSXTW =
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]902 BuildMI(*MBB, InsertionPoint, DL, TII->get(AArch64::SBFMXri), DstRegX)
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]903 .addReg(DstRegX)
904 .addImm(0)
905 .addImm(31);
906 (void)MIBSXTW;
907 DEBUG(dbgs() << " Extend operand:\n ");
908 DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]909 } else {
910 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]911 }
Chad Rosier1c44c5982016-02-09 20:27:45 +0000[diff] [blame]912 DEBUG(dbgs() << "\n");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]913
914 // Erase the old instructions.
915 I->eraseFromParent();
916 Paired->eraseFromParent();
917
918 return NextI;
919}
920
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]921MachineBasicBlock::iterator
922AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
923 MachineBasicBlock::iterator StoreI) {
924 MachineBasicBlock::iterator NextI = LoadI;
925 ++NextI;
926
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]927 int LoadSize = getMemScale(*LoadI);
928 int StoreSize = getMemScale(*StoreI);
929 unsigned LdRt = getLdStRegOp(*LoadI).getReg();
930 unsigned StRt = getLdStRegOp(*StoreI).getReg();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]931 bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt);
932
933 assert((IsStoreXReg ||
934 TRI->getRegClass(AArch64::GPR32RegClassID)->contains(StRt)) &&
935 "Unexpected RegClass");
936
937 MachineInstr *BitExtMI;
938 if (LoadSize == StoreSize && (LoadSize == 4 || LoadSize == 8)) {
939 // Remove the load, if the destination register of the loads is the same
940 // register for stored value.
941 if (StRt == LdRt && LoadSize == 8) {
942 DEBUG(dbgs() << "Remove load instruction:\n ");
943 DEBUG(LoadI->print(dbgs()));
944 DEBUG(dbgs() << "\n");
945 LoadI->eraseFromParent();
946 return NextI;
947 }
948 // Replace the load with a mov if the load and store are in the same size.
949 BitExtMI =
950 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
951 TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
952 .addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
953 .addReg(StRt)
954 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
955 } else {
956 // FIXME: Currently we disable this transformation in big-endian targets as
957 // performance and correctness are verified only in little-endian.
958 if (!Subtarget->isLittleEndian())
959 return NextI;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]960 bool IsUnscaled = TII->isUnscaledLdSt(*LoadI);
961 assert(IsUnscaled == TII->isUnscaledLdSt(*StoreI) &&
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]962 "Unsupported ld/st match");
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]963 assert(LoadSize <= StoreSize && "Invalid load size");
964 int UnscaledLdOffset = IsUnscaled
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]965 ? getLdStOffsetOp(*LoadI).getImm()
966 : getLdStOffsetOp(*LoadI).getImm() * LoadSize;
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]967 int UnscaledStOffset = IsUnscaled
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]968 ? getLdStOffsetOp(*StoreI).getImm()
969 : getLdStOffsetOp(*StoreI).getImm() * StoreSize;
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]970 int Width = LoadSize * 8;
971 int Immr = 8 * (UnscaledLdOffset - UnscaledStOffset);
972 int Imms = Immr + Width - 1;
973 unsigned DestReg = IsStoreXReg
974 ? TRI->getMatchingSuperReg(LdRt, AArch64::sub_32,
975 &AArch64::GPR64RegClass)
976 : LdRt;
977
978 assert((UnscaledLdOffset >= UnscaledStOffset &&
979 (UnscaledLdOffset + LoadSize) <= UnscaledStOffset + StoreSize) &&
980 "Invalid offset");
981
982 Immr = 8 * (UnscaledLdOffset - UnscaledStOffset);
983 Imms = Immr + Width - 1;
984 if (UnscaledLdOffset == UnscaledStOffset) {
985 uint32_t AndMaskEncoded = ((IsStoreXReg ? 1 : 0) << 12) // N
986 | ((Immr) << 6) // immr
987 | ((Imms) << 0) // imms
988 ;
989
990 BitExtMI =
991 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
992 TII->get(IsStoreXReg ? AArch64::ANDXri : AArch64::ANDWri),
993 DestReg)
994 .addReg(StRt)
995 .addImm(AndMaskEncoded);
996 } else {
997 BitExtMI =
998 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
999 TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri),
1000 DestReg)
1001 .addReg(StRt)
1002 .addImm(Immr)
1003 .addImm(Imms);
1004 }
1005 }
Chad Rosierf7ac5f22016-03-30 18:08:51 +0000[diff] [blame]1006 (void)BitExtMI;
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1007
1008 DEBUG(dbgs() << "Promoting load by replacing :\n ");
1009 DEBUG(StoreI->print(dbgs()));
1010 DEBUG(dbgs() << " ");
1011 DEBUG(LoadI->print(dbgs()));
1012 DEBUG(dbgs() << " with instructions:\n ");
1013 DEBUG(StoreI->print(dbgs()));
1014 DEBUG(dbgs() << " ");
1015 DEBUG((BitExtMI)->print(dbgs()));
1016 DEBUG(dbgs() << "\n");
1017
1018 // Erase the old instructions.
1019 LoadI->eraseFromParent();
1020 return NextI;
1021}
1022
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1023/// trackRegDefsUses - Remember what registers the specified instruction uses
1024/// and modifies.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1025static void trackRegDefsUses(const MachineInstr &MI, BitVector &ModifiedRegs,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1026 BitVector &UsedRegs,
1027 const TargetRegisterInfo *TRI) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1028 for (const MachineOperand &MO : MI.operands()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1029 if (MO.isRegMask())
1030 ModifiedRegs.setBitsNotInMask(MO.getRegMask());
1031
1032 if (!MO.isReg())
1033 continue;
1034 unsigned Reg = MO.getReg();
Geoff Berry173b14d2016-02-09 20:47:21 +0000[diff] [blame]1035 if (!Reg)
1036 continue;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1037 if (MO.isDef()) {
1038 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
1039 ModifiedRegs.set(*AI);
1040 } else {
1041 assert(MO.isUse() && "Reg operand not a def and not a use?!?");
1042 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
1043 UsedRegs.set(*AI);
1044 }
1045 }
1046}
1047
1048static bool inBoundsForPair(bool IsUnscaled, int Offset, int OffsetStride) {
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]1049 // Convert the byte-offset used by unscaled into an "element" offset used
1050 // by the scaled pair load/store instructions.
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1051 if (IsUnscaled) {
1052 // If the byte-offset isn't a multiple of the stride, there's no point
1053 // trying to match it.
1054 if (Offset % OffsetStride)
1055 return false;
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]1056 Offset /= OffsetStride;
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1057 }
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]1058 return Offset <= 63 && Offset >= -64;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1059}
1060
1061// Do alignment, specialized to power of 2 and for signed ints,
1062// avoiding having to do a C-style cast from uint_64t to int when
Rui Ueyamada00f2f2016-01-14 21:06:47 +0000[diff] [blame]1063// using alignTo from include/llvm/Support/MathExtras.h.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1064// FIXME: Move this function to include/MathExtras.h?
1065static int alignTo(int Num, int PowOf2) {
1066 return (Num + PowOf2 - 1) & ~(PowOf2 - 1);
1067}
1068
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]1069static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb,
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1070 const AArch64InstrInfo *TII) {
1071 // One of the instructions must modify memory.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]1072 if (!MIa.mayStore() && !MIb.mayStore())
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1073 return false;
1074
1075 // Both instructions must be memory operations.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]1076 if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore())
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1077 return false;
1078
1079 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb);
1080}
1081
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]1082static bool mayAlias(MachineInstr &MIa,
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1083 SmallVectorImpl<MachineInstr *> &MemInsns,
1084 const AArch64InstrInfo *TII) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]1085 for (MachineInstr *MIb : MemInsns)
1086 if (mayAlias(MIa, *MIb, TII))
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1087 return true;
1088
1089 return false;
1090}
1091
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1092bool AArch64LoadStoreOpt::findMatchingStore(
1093 MachineBasicBlock::iterator I, unsigned Limit,
1094 MachineBasicBlock::iterator &StoreI) {
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1095 MachineBasicBlock::iterator B = I->getParent()->begin();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1096 MachineBasicBlock::iterator MBBI = I;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1097 MachineInstr &LoadMI = *I;
Chad Rosier5c6a66c2016-02-09 15:59:57 +0000[diff] [blame]1098 unsigned BaseReg = getLdStBaseOp(LoadMI).getReg();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1099
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1100 // If the load is the first instruction in the block, there's obviously
1101 // not any matching store.
1102 if (MBBI == B)
1103 return false;
1104
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1105 // Track which registers have been modified and used between the first insn
1106 // and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1107 ModifiedRegs.reset();
1108 UsedRegs.reset();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1109
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1110 unsigned Count = 0;
1111 do {
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1112 --MBBI;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1113 MachineInstr &MI = *MBBI;
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1114
Geoff Berry4ff2e362016-07-21 15:20:25 +0000[diff] [blame]1115 // Don't count transient instructions towards the search limit since there
1116 // may be different numbers of them if e.g. debug information is present.
1117 if (!MI.isTransient())
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1118 ++Count;
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1119
1120 // If the load instruction reads directly from the address to which the
1121 // store instruction writes and the stored value is not modified, we can
1122 // promote the load. Since we do not handle stores with pre-/post-index,
1123 // it's unnecessary to check if BaseReg is modified by the store itself.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1124 if (MI.mayStore() && isMatchingStore(LoadMI, MI) &&
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1125 BaseReg == getLdStBaseOp(MI).getReg() &&
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]1126 isLdOffsetInRangeOfSt(LoadMI, MI, TII) &&
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1127 !ModifiedRegs[getLdStRegOp(MI).getReg()]) {
1128 StoreI = MBBI;
1129 return true;
1130 }
1131
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1132 if (MI.isCall())
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1133 return false;
1134
1135 // Update modified / uses register lists.
1136 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1137
1138 // Otherwise, if the base register is modified, we have no match, so
1139 // return early.
1140 if (ModifiedRegs[BaseReg])
1141 return false;
1142
1143 // If we encounter a store aliased with the load, return early.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1144 if (MI.mayStore() && mayAlias(LoadMI, MI, TII))
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1145 return false;
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1146 } while (MBBI != B && Count < Limit);
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1147 return false;
1148}
1149
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1150// Returns true if FirstMI and MI are candidates for merging or pairing.
1151// Otherwise, returns false.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1152static bool areCandidatesToMergeOrPair(MachineInstr &FirstMI, MachineInstr &MI,
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1153 LdStPairFlags &Flags,
1154 const AArch64InstrInfo *TII) {
1155 // If this is volatile or if pairing is suppressed, not a candidate.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1156 if (MI.hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI))
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1157 return false;
1158
1159 // We should have already checked FirstMI for pair suppression and volatility.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1160 assert(!FirstMI.hasOrderedMemoryRef() &&
1161 !TII->isLdStPairSuppressed(FirstMI) &&
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1162 "FirstMI shouldn't get here if either of these checks are true.");
1163
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1164 unsigned OpcA = FirstMI.getOpcode();
1165 unsigned OpcB = MI.getOpcode();
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1166
Chad Rosierc3f6cb92016-02-10 19:45:48 +0000[diff] [blame]1167 // Opcodes match: nothing more to check.
1168 if (OpcA == OpcB)
1169 return true;
1170
1171 // Try to match a sign-extended load/store with a zero-extended load/store.
1172 bool IsValidLdStrOpc, PairIsValidLdStrOpc;
1173 unsigned NonSExtOpc = getMatchingNonSExtOpcode(OpcA, &IsValidLdStrOpc);
1174 assert(IsValidLdStrOpc &&
1175 "Given Opc should be a Load or Store with an immediate");
1176 // OpcA will be the first instruction in the pair.
1177 if (NonSExtOpc == getMatchingNonSExtOpcode(OpcB, &PairIsValidLdStrOpc)) {
1178 Flags.setSExtIdx(NonSExtOpc == (unsigned)OpcA ? 1 : 0);
1179 return true;
1180 }
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1181
1182 // If the second instruction isn't even a load/store, bail out.
1183 if (!PairIsValidLdStrOpc)
1184 return false;
1185
1186 // FIXME: We don't support merging narrow loads/stores with mixed
1187 // scaled/unscaled offsets.
1188 if (isNarrowLoadOrStore(OpcA) || isNarrowLoadOrStore(OpcB))
1189 return false;
1190
1191 // Try to match an unscaled load/store with a scaled load/store.
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]1192 return TII->isUnscaledLdSt(OpcA) != TII->isUnscaledLdSt(OpcB) &&
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1193 getMatchingPairOpcode(OpcA) == getMatchingPairOpcode(OpcB);
1194
1195 // FIXME: Can we also match a mixed sext/zext unscaled/scaled pair?
Chad Rosierc3f6cb92016-02-10 19:45:48 +0000[diff] [blame]1196}
1197
Chad Rosier9f4ec2e2016-02-10 18:49:28 +0000[diff] [blame]1198/// Scan the instructions looking for a load/store that can be combined with the
1199/// current instruction into a wider equivalent or a load/store pair.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1200MachineBasicBlock::iterator
1201AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1202 LdStPairFlags &Flags, unsigned Limit,
1203 bool FindNarrowMerge) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1204 MachineBasicBlock::iterator E = I->getParent()->end();
1205 MachineBasicBlock::iterator MBBI = I;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1206 MachineInstr &FirstMI = *I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1207 ++MBBI;
1208
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1209 bool MayLoad = FirstMI.mayLoad();
1210 bool IsUnscaled = TII->isUnscaledLdSt(FirstMI);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1211 unsigned Reg = getLdStRegOp(FirstMI).getReg();
1212 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
1213 int Offset = getLdStOffsetOp(FirstMI).getImm();
Chad Rosierf11d0402015-10-01 18:17:12 +0000[diff] [blame]1214 int OffsetStride = IsUnscaled ? getMemScale(FirstMI) : 1;
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]1215 bool IsPromotableZeroStore = isPromotableZeroStoreInst(FirstMI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1216
1217 // Track which registers have been modified and used between the first insn
1218 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1219 ModifiedRegs.reset();
1220 UsedRegs.reset();
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1221
1222 // Remember any instructions that read/write memory between FirstMI and MI.
1223 SmallVector<MachineInstr *, 4> MemInsns;
1224
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1225 for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1226 MachineInstr &MI = *MBBI;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1227
Geoff Berry4ff2e362016-07-21 15:20:25 +0000[diff] [blame]1228 // Don't count transient instructions towards the search limit since there
1229 // may be different numbers of them if e.g. debug information is present.
1230 if (!MI.isTransient())
1231 ++Count;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1232
Chad Rosier18896c02016-02-04 16:01:40 +0000[diff] [blame]1233 Flags.setSExtIdx(-1);
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1234 if (areCandidatesToMergeOrPair(FirstMI, MI, Flags, TII) &&
Chad Rosierc3f6cb92016-02-10 19:45:48 +0000[diff] [blame]1235 getLdStOffsetOp(MI).isImm()) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1236 assert(MI.mayLoadOrStore() && "Expected memory operation.");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1237 // If we've found another instruction with the same opcode, check to see
1238 // if the base and offset are compatible with our starting instruction.
1239 // These instructions all have scaled immediate operands, so we just
1240 // check for +1/-1. Make sure to check the new instruction offset is
1241 // actually an immediate and not a symbolic reference destined for
1242 // a relocation.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1243 unsigned MIBaseReg = getLdStBaseOp(MI).getReg();
1244 int MIOffset = getLdStOffsetOp(MI).getImm();
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1245 bool MIIsUnscaled = TII->isUnscaledLdSt(MI);
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1246 if (IsUnscaled != MIIsUnscaled) {
1247 // We're trying to pair instructions that differ in how they are scaled.
1248 // If FirstMI is scaled then scale the offset of MI accordingly.
1249 // Otherwise, do the opposite (i.e., make MI's offset unscaled).
1250 int MemSize = getMemScale(MI);
1251 if (MIIsUnscaled) {
1252 // If the unscaled offset isn't a multiple of the MemSize, we can't
1253 // pair the operations together: bail and keep looking.
Eli Friedmanf184e4b2016-08-12 20:39:51 +0000[diff] [blame]1254 if (MIOffset % MemSize) {
1255 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1256 MemInsns.push_back(&MI);
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1257 continue;
Eli Friedmanf184e4b2016-08-12 20:39:51 +0000[diff] [blame]1258 }
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1259 MIOffset /= MemSize;
1260 } else {
1261 MIOffset *= MemSize;
1262 }
1263 }
1264
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1265 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
1266 (Offset + OffsetStride == MIOffset))) {
1267 int MinOffset = Offset < MIOffset ? Offset : MIOffset;
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1268 if (FindNarrowMerge) {
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1269 // If the alignment requirements of the scaled wide load/store
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1270 // instruction can't express the offset of the scaled narrow input,
1271 // bail and keep looking. For promotable zero stores, allow only when
1272 // the stored value is the same (i.e., WZR).
1273 if ((!IsUnscaled && alignTo(MinOffset, 2) != MinOffset) ||
1274 (IsPromotableZeroStore && Reg != getLdStRegOp(MI).getReg())) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1275 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1276 MemInsns.push_back(&MI);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1277 continue;
1278 }
1279 } else {
Chad Rosierd1f6c842016-06-10 20:49:18 +0000[diff] [blame]1280 // Pairwise instructions have a 7-bit signed offset field. Single
1281 // insns have a 12-bit unsigned offset field. If the resultant
1282 // immediate offset of merging these instructions is out of range for
1283 // a pairwise instruction, bail and keep looking.
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1284 if (!inBoundsForPair(IsUnscaled, MinOffset, OffsetStride)) {
1285 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1286 MemInsns.push_back(&MI);
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1287 continue;
1288 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1289 // If the alignment requirements of the paired (scaled) instruction
1290 // can't express the offset of the unscaled input, bail and keep
1291 // looking.
1292 if (IsUnscaled && (alignTo(MinOffset, OffsetStride) != MinOffset)) {
1293 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1294 MemInsns.push_back(&MI);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1295 continue;
1296 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1297 }
1298 // If the destination register of the loads is the same register, bail
1299 // and keep looking. A load-pair instruction with both destination
1300 // registers the same is UNPREDICTABLE and will result in an exception.
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1301 if (MayLoad && Reg == getLdStRegOp(MI).getReg()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1302 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1303 MemInsns.push_back(&MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1304 continue;
1305 }
1306
1307 // If the Rt of the second instruction was not modified or used between
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1308 // the two instructions and none of the instructions between the second
1309 // and first alias with the second, we can combine the second into the
1310 // first.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1311 if (!ModifiedRegs[getLdStRegOp(MI).getReg()] &&
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1312 !(MI.mayLoad() && UsedRegs[getLdStRegOp(MI).getReg()]) &&
1313 !mayAlias(MI, MemInsns, TII)) {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]1314 Flags.setMergeForward(false);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1315 return MBBI;
1316 }
1317
1318 // Likewise, if the Rt of the first instruction is not modified or used
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1319 // between the two instructions and none of the instructions between the
1320 // first and the second alias with the first, we can combine the first
1321 // into the second.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1322 if (!ModifiedRegs[getLdStRegOp(FirstMI).getReg()] &&
Chad Rosier5f668e12015-09-03 14:19:43 +0000[diff] [blame]1323 !(MayLoad && UsedRegs[getLdStRegOp(FirstMI).getReg()]) &&
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1324 !mayAlias(FirstMI, MemInsns, TII)) {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]1325 Flags.setMergeForward(true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1326 return MBBI;
1327 }
1328 // Unable to combine these instructions due to interference in between.
1329 // Keep looking.
1330 }
1331 }
1332
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1333 // If the instruction wasn't a matching load or store. Stop searching if we
1334 // encounter a call instruction that might modify memory.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1335 if (MI.isCall())
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1336 return E;
1337
1338 // Update modified / uses register lists.
1339 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1340
1341 // Otherwise, if the base register is modified, we have no match, so
1342 // return early.
1343 if (ModifiedRegs[BaseReg])
1344 return E;
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1345
1346 // Update list of instructions that read/write memory.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1347 if (MI.mayLoadOrStore())
1348 MemInsns.push_back(&MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1349 }
1350 return E;
1351}
1352
1353MachineBasicBlock::iterator
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1354AArch64LoadStoreOpt::mergeUpdateInsn(MachineBasicBlock::iterator I,
1355 MachineBasicBlock::iterator Update,
1356 bool IsPreIdx) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1357 assert((Update->getOpcode() == AArch64::ADDXri ||
1358 Update->getOpcode() == AArch64::SUBXri) &&
1359 "Unexpected base register update instruction to merge!");
1360 MachineBasicBlock::iterator NextI = I;
1361 // Return the instruction following the merged instruction, which is
1362 // the instruction following our unmerged load. Unless that's the add/sub
1363 // instruction we're merging, in which case it's the one after that.
1364 if (++NextI == Update)
1365 ++NextI;
1366
1367 int Value = Update->getOperand(2).getImm();
1368 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1369 "Can't merge 1 << 12 offset into pre-/post-indexed load / store");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1370 if (Update->getOpcode() == AArch64::SUBXri)
1371 Value = -Value;
1372
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1373 unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode(I->getOpcode())
1374 : getPostIndexedOpcode(I->getOpcode());
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1375 MachineInstrBuilder MIB;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1376 if (!isPairedLdSt(*I)) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1377 // Non-paired instruction.
1378 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1379 .addOperand(getLdStRegOp(*Update))
1380 .addOperand(getLdStRegOp(*I))
1381 .addOperand(getLdStBaseOp(*I))
Chad Rosier3ada75f2016-01-28 15:38:24 +0000[diff] [blame]1382 .addImm(Value)
1383 .setMemRefs(I->memoperands_begin(), I->memoperands_end());
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1384 } else {
1385 // Paired instruction.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1386 int Scale = getMemScale(*I);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1387 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1388 .addOperand(getLdStRegOp(*Update))
1389 .addOperand(getLdStRegOp(*I, 0))
1390 .addOperand(getLdStRegOp(*I, 1))
1391 .addOperand(getLdStBaseOp(*I))
Chad Rosier3ada75f2016-01-28 15:38:24 +0000[diff] [blame]1392 .addImm(Value / Scale)
1393 .setMemRefs(I->memoperands_begin(), I->memoperands_end());
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1394 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1395 (void)MIB;
1396
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1397 if (IsPreIdx)
1398 DEBUG(dbgs() << "Creating pre-indexed load/store.");
1399 else
1400 DEBUG(dbgs() << "Creating post-indexed load/store.");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1401 DEBUG(dbgs() << " Replacing instructions:\n ");
1402 DEBUG(I->print(dbgs()));
1403 DEBUG(dbgs() << " ");
1404 DEBUG(Update->print(dbgs()));
1405 DEBUG(dbgs() << " with instruction:\n ");
1406 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
1407 DEBUG(dbgs() << "\n");
1408
1409 // Erase the old instructions for the block.
1410 I->eraseFromParent();
1411 Update->eraseFromParent();
1412
1413 return NextI;
1414}
1415
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1416bool AArch64LoadStoreOpt::isMatchingUpdateInsn(MachineInstr &MemMI,
1417 MachineInstr &MI,
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1418 unsigned BaseReg, int Offset) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1419 switch (MI.getOpcode()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1420 default:
1421 break;
1422 case AArch64::SUBXri:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1423 case AArch64::ADDXri:
1424 // Make sure it's a vanilla immediate operand, not a relocation or
1425 // anything else we can't handle.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1426 if (!MI.getOperand(2).isImm())
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1427 break;
1428 // Watch out for 1 << 12 shifted value.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1429 if (AArch64_AM::getShiftValue(MI.getOperand(3).getImm()))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1430 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1431
1432 // The update instruction source and destination register must be the
1433 // same as the load/store base register.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1434 if (MI.getOperand(0).getReg() != BaseReg ||
1435 MI.getOperand(1).getReg() != BaseReg)
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1436 break;
1437
1438 bool IsPairedInsn = isPairedLdSt(MemMI);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1439 int UpdateOffset = MI.getOperand(2).getImm();
Eli Friedman8585e9d2016-08-12 20:28:02 +0000[diff] [blame]1440 if (MI.getOpcode() == AArch64::SUBXri)
1441 UpdateOffset = -UpdateOffset;
1442
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1443 // For non-paired load/store instructions, the immediate must fit in a
1444 // signed 9-bit integer.
1445 if (!IsPairedInsn && (UpdateOffset > 255 || UpdateOffset < -256))
1446 break;
1447
1448 // For paired load/store instructions, the immediate must be a multiple of
1449 // the scaling factor. The scaled offset must also fit into a signed 7-bit
1450 // integer.
1451 if (IsPairedInsn) {
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]1452 int Scale = getMemScale(MemMI);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1453 if (UpdateOffset % Scale != 0)
1454 break;
1455
1456 int ScaledOffset = UpdateOffset / Scale;
Eli Friedman8585e9d2016-08-12 20:28:02 +0000[diff] [blame]1457 if (ScaledOffset > 63 || ScaledOffset < -64)
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1458 break;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1459 }
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1460
1461 // If we have a non-zero Offset, we check that it matches the amount
1462 // we're adding to the register.
Eli Friedman8585e9d2016-08-12 20:28:02 +0000[diff] [blame]1463 if (!Offset || Offset == UpdateOffset)
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1464 return true;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1465 break;
1466 }
1467 return false;
1468}
1469
1470MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1471 MachineBasicBlock::iterator I, int UnscaledOffset, unsigned Limit) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1472 MachineBasicBlock::iterator E = I->getParent()->end();
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1473 MachineInstr &MemMI = *I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1474 MachineBasicBlock::iterator MBBI = I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1475
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1476 unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1477 int MIUnscaledOffset = getLdStOffsetOp(MemMI).getImm() * getMemScale(MemMI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1478
Chad Rosierb7c5b912015-10-01 13:43:05 +0000[diff] [blame]1479 // Scan forward looking for post-index opportunities. Updating instructions
1480 // can't be formed if the memory instruction doesn't have the offset we're
1481 // looking for.
1482 if (MIUnscaledOffset != UnscaledOffset)
1483 return E;
1484
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1485 // If the base register overlaps a destination register, we can't
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1486 // merge the update.
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1487 bool IsPairedInsn = isPairedLdSt(MemMI);
1488 for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
1489 unsigned DestReg = getLdStRegOp(MemMI, i).getReg();
1490 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
1491 return E;
1492 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1493
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1494 // Track which registers have been modified and used between the first insn
1495 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1496 ModifiedRegs.reset();
1497 UsedRegs.reset();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1498 ++MBBI;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1499 for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1500 MachineInstr &MI = *MBBI;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1501
Geoff Berry4ff2e362016-07-21 15:20:25 +0000[diff] [blame]1502 // Don't count transient instructions towards the search limit since there
1503 // may be different numbers of them if e.g. debug information is present.
1504 if (!MI.isTransient())
1505 ++Count;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1506
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1507 // If we found a match, return it.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1508 if (isMatchingUpdateInsn(*I, MI, BaseReg, UnscaledOffset))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1509 return MBBI;
1510
1511 // Update the status of what the instruction clobbered and used.
1512 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1513
1514 // Otherwise, if the base register is used or modified, we have no match, so
1515 // return early.
1516 if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
1517 return E;
1518 }
1519 return E;
1520}
1521
1522MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1523 MachineBasicBlock::iterator I, unsigned Limit) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1524 MachineBasicBlock::iterator B = I->getParent()->begin();
1525 MachineBasicBlock::iterator E = I->getParent()->end();
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1526 MachineInstr &MemMI = *I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1527 MachineBasicBlock::iterator MBBI = I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1528
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1529 unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
1530 int Offset = getLdStOffsetOp(MemMI).getImm();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1531
1532 // If the load/store is the first instruction in the block, there's obviously
1533 // not any matching update. Ditto if the memory offset isn't zero.
1534 if (MBBI == B || Offset != 0)
1535 return E;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1536 // If the base register overlaps a destination register, we can't
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1537 // merge the update.
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1538 bool IsPairedInsn = isPairedLdSt(MemMI);
1539 for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
1540 unsigned DestReg = getLdStRegOp(MemMI, i).getReg();
1541 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
1542 return E;
1543 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1544
1545 // Track which registers have been modified and used between the first insn
1546 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1547 ModifiedRegs.reset();
1548 UsedRegs.reset();
Geoff Berry173b14d2016-02-09 20:47:21 +0000[diff] [blame]1549 unsigned Count = 0;
1550 do {
1551 --MBBI;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1552 MachineInstr &MI = *MBBI;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1553
Geoff Berry4ff2e362016-07-21 15:20:25 +0000[diff] [blame]1554 // Don't count transient instructions towards the search limit since there
1555 // may be different numbers of them if e.g. debug information is present.
1556 if (!MI.isTransient())
Geoff Berry173b14d2016-02-09 20:47:21 +0000[diff] [blame]1557 ++Count;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1558
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1559 // If we found a match, return it.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1560 if (isMatchingUpdateInsn(*I, MI, BaseReg, Offset))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1561 return MBBI;
1562
1563 // Update the status of what the instruction clobbered and used.
1564 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1565
1566 // Otherwise, if the base register is used or modified, we have no match, so
1567 // return early.
1568 if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
1569 return E;
Geoff Berry173b14d2016-02-09 20:47:21 +0000[diff] [blame]1570 } while (MBBI != B && Count < Limit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1571 return E;
1572}
1573
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1574bool AArch64LoadStoreOpt::tryToPromoteLoadFromStore(
1575 MachineBasicBlock::iterator &MBBI) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1576 MachineInstr &MI = *MBBI;
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1577 // If this is a volatile load, don't mess with it.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1578 if (MI.hasOrderedMemoryRef())
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1579 return false;
1580
1581 // Make sure this is a reg+imm.
1582 // FIXME: It is possible to extend it to handle reg+reg cases.
1583 if (!getLdStOffsetOp(MI).isImm())
1584 return false;
1585
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1586 // Look backward up to LdStLimit instructions.
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1587 MachineBasicBlock::iterator StoreI;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1588 if (findMatchingStore(MBBI, LdStLimit, StoreI)) {
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1589 ++NumLoadsFromStoresPromoted;
1590 // Promote the load. Keeping the iterator straight is a
1591 // pain, so we let the merge routine tell us what the next instruction
1592 // is after it's done mucking about.
1593 MBBI = promoteLoadFromStore(MBBI, StoreI);
1594 return true;
1595 }
1596 return false;
1597}
1598
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1599// Find narrow loads that can be converted into a single wider load with
1600// bitfield extract instructions. Also merge adjacent zero stores into a wider
1601// store.
1602bool AArch64LoadStoreOpt::tryToMergeLdStInst(
1603 MachineBasicBlock::iterator &MBBI) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1604 assert((isNarrowLoad(*MBBI) || isPromotableZeroStoreOpcode(*MBBI)) &&
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]1605 "Expected narrow op.");
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1606 MachineInstr &MI = *MBBI;
1607 MachineBasicBlock::iterator E = MI.getParent()->end();
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1608
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1609 if (!TII->isCandidateToMergeOrPair(MI))
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1610 return false;
1611
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]1612 // For promotable zero stores, the stored value should be WZR.
1613 if (isPromotableZeroStoreOpcode(MI) &&
1614 getLdStRegOp(MI).getReg() != AArch64::WZR)
Chad Rosierf7cd8ea2016-02-09 21:20:12 +0000[diff] [blame]1615 return false;
1616
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1617 // Look ahead up to LdStLimit instructions for a mergable instruction.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1618 LdStPairFlags Flags;
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]1619 MachineBasicBlock::iterator MergeMI =
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1620 findMatchingInsn(MBBI, Flags, LdStLimit, /* FindNarrowMerge = */ true);
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]1621 if (MergeMI != E) {
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1622 if (isNarrowLoad(MI)) {
1623 ++NumNarrowLoadsPromoted;
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]1624 } else if (isPromotableZeroStoreInst(MI)) {
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1625 ++NumZeroStoresPromoted;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1626 }
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1627 // Keeping the iterator straight is a pain, so we let the merge routine tell
1628 // us what the next instruction is after it's done mucking about.
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]1629 MBBI = mergeNarrowInsns(MBBI, MergeMI, Flags);
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1630 return true;
1631 }
1632 return false;
1633}
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1634
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1635// Find loads and stores that can be merged into a single load or store pair
1636// instruction.
1637bool AArch64LoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1638 MachineInstr &MI = *MBBI;
1639 MachineBasicBlock::iterator E = MI.getParent()->end();
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1640
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1641 if (!TII->isCandidateToMergeOrPair(MI))
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1642 return false;
1643
Chad Rosierfc3bf1f2016-02-10 15:52:46 +0000[diff] [blame]1644 // Early exit if the offset is not possible to match. (6 bits of positive
1645 // range, plus allow an extra one in case we find a later insn that matches
1646 // with Offset-1)
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1647 bool IsUnscaled = TII->isUnscaledLdSt(MI);
Chad Rosierfc3bf1f2016-02-10 15:52:46 +0000[diff] [blame]1648 int Offset = getLdStOffsetOp(MI).getImm();
1649 int OffsetStride = IsUnscaled ? getMemScale(MI) : 1;
1650 if (!inBoundsForPair(IsUnscaled, Offset, OffsetStride))
1651 return false;
1652
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1653 // Look ahead up to LdStLimit instructions for a pairable instruction.
1654 LdStPairFlags Flags;
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1655 MachineBasicBlock::iterator Paired =
1656 findMatchingInsn(MBBI, Flags, LdStLimit, /* FindNarrowMerge = */ false);
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1657 if (Paired != E) {
1658 ++NumPairCreated;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1659 if (TII->isUnscaledLdSt(MI))
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1660 ++NumUnscaledPairCreated;
1661 // Keeping the iterator straight is a pain, so we let the merge routine tell
1662 // us what the next instruction is after it's done mucking about.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1663 MBBI = mergePairedInsns(MBBI, Paired, Flags);
1664 return true;
1665 }
1666 return false;
1667}
1668
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1669bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
1670 bool enableNarrowLdOpt) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1671 bool Modified = false;
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1672 // Four tranformations to do here:
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1673 // 1) Find loads that directly read from stores and promote them by
1674 // replacing with mov instructions. If the store is wider than the load,
1675 // the load will be replaced with a bitfield extract.
1676 // e.g.,
1677 // str w1, [x0, #4]
1678 // ldrh w2, [x0, #6]
1679 // ; becomes
1680 // str w1, [x0, #4]
NAKAMURA Takumife1202c2016-06-20 00:37:41 +0000[diff] [blame]1681 // lsr w2, w1, #16
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1682 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1683 MBBI != E;) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1684 MachineInstr &MI = *MBBI;
1685 switch (MI.getOpcode()) {
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1686 default:
1687 // Just move on to the next instruction.
1688 ++MBBI;
1689 break;
1690 // Scaled instructions.
1691 case AArch64::LDRBBui:
1692 case AArch64::LDRHHui:
1693 case AArch64::LDRWui:
1694 case AArch64::LDRXui:
1695 // Unscaled instructions.
1696 case AArch64::LDURBBi:
1697 case AArch64::LDURHHi:
1698 case AArch64::LDURWi:
1699 case AArch64::LDURXi: {
1700 if (tryToPromoteLoadFromStore(MBBI)) {
1701 Modified = true;
1702 break;
1703 }
1704 ++MBBI;
1705 break;
1706 }
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1707 }
1708 }
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1709 // 2) Find narrow loads that can be converted into a single wider load
1710 // with bitfield extract instructions.
1711 // e.g.,
1712 // ldrh w0, [x2]
1713 // ldrh w1, [x2, #2]
1714 // ; becomes
1715 // ldr w0, [x2]
1716 // ubfx w1, w0, #16, #16
1717 // and w0, w0, #ffff
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame]1718 //
1719 // Also merge adjacent zero stores into a wider store.
1720 // e.g.,
1721 // strh wzr, [x0]
1722 // strh wzr, [x0, #2]
1723 // ; becomes
1724 // str wzr, [x0]
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1725 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1726 enableNarrowLdOpt && MBBI != E;) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1727 MachineInstr &MI = *MBBI;
1728 unsigned Opc = MI.getOpcode();
Jun Bum Lim33be4992016-05-06 15:08:57 +0000[diff] [blame]1729 if (isPromotableZeroStoreOpcode(Opc) ||
1730 (EnableNarrowLdMerge && isNarrowLoad(Opc))) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1731 if (tryToMergeLdStInst(MBBI)) {
1732 Modified = true;
Jun Bum Lim33be4992016-05-06 15:08:57 +0000[diff] [blame]1733 } else
1734 ++MBBI;
1735 } else
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1736 ++MBBI;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1737 }
Jun Bum Lim33be4992016-05-06 15:08:57 +0000[diff] [blame]1738
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1739 // 3) Find loads and stores that can be merged into a single load or store
1740 // pair instruction.
1741 // e.g.,
1742 // ldr x0, [x2]
1743 // ldr x1, [x2, #8]
1744 // ; becomes
1745 // ldp x0, x1, [x2]
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1746 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1747 MBBI != E;) {
Geoff Berry22dfbc52016-08-12 15:26:00 +0000[diff] [blame]1748 if (TII->isPairableLdStInst(*MBBI) && tryToPairLdStInst(MBBI))
1749 Modified = true;
1750 else
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1751 ++MBBI;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1752 }
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1753 // 4) Find base register updates that can be merged into the load or store
1754 // as a base-reg writeback.
1755 // e.g.,
1756 // ldr x0, [x2]
1757 // add x2, x2, #4
1758 // ; becomes
1759 // ldr x0, [x2], #4
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1760 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1761 MBBI != E;) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1762 MachineInstr &MI = *MBBI;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1763 // Do update merging. It's simpler to keep this separate from the above
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1764 // switchs, though not strictly necessary.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1765 unsigned Opc = MI.getOpcode();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1766 switch (Opc) {
1767 default:
1768 // Just move on to the next instruction.
1769 ++MBBI;
1770 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1771 // Scaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1772 case AArch64::STRSui:
1773 case AArch64::STRDui:
1774 case AArch64::STRQui:
1775 case AArch64::STRXui:
1776 case AArch64::STRWui:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]1777 case AArch64::STRHHui:
1778 case AArch64::STRBBui:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1779 case AArch64::LDRSui:
1780 case AArch64::LDRDui:
1781 case AArch64::LDRQui:
1782 case AArch64::LDRXui:
1783 case AArch64::LDRWui:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]1784 case AArch64::LDRHHui:
1785 case AArch64::LDRBBui:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1786 // Unscaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1787 case AArch64::STURSi:
1788 case AArch64::STURDi:
1789 case AArch64::STURQi:
1790 case AArch64::STURWi:
1791 case AArch64::STURXi:
1792 case AArch64::LDURSi:
1793 case AArch64::LDURDi:
1794 case AArch64::LDURQi:
1795 case AArch64::LDURWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1796 case AArch64::LDURXi:
1797 // Paired instructions.
1798 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]1799 case AArch64::LDPSWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1800 case AArch64::LDPDi:
1801 case AArch64::LDPQi:
1802 case AArch64::LDPWi:
1803 case AArch64::LDPXi:
1804 case AArch64::STPSi:
1805 case AArch64::STPDi:
1806 case AArch64::STPQi:
1807 case AArch64::STPWi:
1808 case AArch64::STPXi: {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1809 // Make sure this is a reg+imm (as opposed to an address reloc).
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1810 if (!getLdStOffsetOp(MI).isImm()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1811 ++MBBI;
1812 break;
1813 }
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1814 // Look forward to try to form a post-index instruction. For example,
1815 // ldr x0, [x20]
1816 // add x20, x20, #32
1817 // merged into:
1818 // ldr x0, [x20], #32
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1819 MachineBasicBlock::iterator Update =
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1820 findMatchingUpdateInsnForward(MBBI, 0, UpdateLimit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1821 if (Update != E) {
1822 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1823 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/false);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1824 Modified = true;
1825 ++NumPostFolded;
1826 break;
1827 }
1828 // Don't know how to handle pre/post-index versions, so move to the next
1829 // instruction.
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]1830 if (TII->isUnscaledLdSt(Opc)) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1831 ++MBBI;
1832 break;
1833 }
1834
1835 // Look back to try to find a pre-index instruction. For example,
1836 // add x0, x0, #8
1837 // ldr x1, [x0]
1838 // merged into:
1839 // ldr x1, [x0, #8]!
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1840 Update = findMatchingUpdateInsnBackward(MBBI, UpdateLimit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1841 if (Update != E) {
1842 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1843 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1844 Modified = true;
1845 ++NumPreFolded;
1846 break;
1847 }
Chad Rosier7a83d772015-10-01 13:09:44 +0000[diff] [blame]1848 // The immediate in the load/store is scaled by the size of the memory
1849 // operation. The immediate in the add we're looking for,
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1850 // however, is not, so adjust here.
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1851 int UnscaledOffset = getLdStOffsetOp(MI).getImm() * getMemScale(MI);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1852
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1853 // Look forward to try to find a post-index instruction. For example,
1854 // ldr x1, [x0, #64]
1855 // add x0, x0, #64
1856 // merged into:
1857 // ldr x1, [x0, #64]!
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1858 Update = findMatchingUpdateInsnForward(MBBI, UnscaledOffset, UpdateLimit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1859 if (Update != E) {
1860 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1861 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1862 Modified = true;
1863 ++NumPreFolded;
1864 break;
1865 }
1866
1867 // Nothing found. Just move to the next instruction.
1868 ++MBBI;
1869 break;
1870 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1871 }
1872 }
1873
1874 return Modified;
1875}
1876
1877bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
Andrew Kaylor1ac98bb2016-04-25 21:58:52 +0000[diff] [blame]1878 if (skipFunction(*Fn.getFunction()))
1879 return false;
1880
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]1881 Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
1882 TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
1883 TRI = Subtarget->getRegisterInfo();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1884
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1885 // Resize the modified and used register bitfield trackers. We do this once
1886 // per function and then clear the bitfield each time we optimize a load or
1887 // store.
1888 ModifiedRegs.resize(TRI->getNumRegs());
1889 UsedRegs.resize(TRI->getNumRegs());
1890
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1891 bool Modified = false;
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]1892 bool enableNarrowLdOpt =
1893 Subtarget->mergeNarrowLoads() && !Subtarget->requiresStrictAlign();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1894 for (auto &MBB : Fn)
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1895 Modified |= optimizeBlock(MBB, enableNarrowLdOpt);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1896
1897 return Modified;
1898}
1899
1900// FIXME: Do we need/want a pre-alloc pass like ARM has to try to keep
1901// loads and stores near one another?
1902
Chad Rosier3f8b09d2016-02-09 19:42:19 +0000[diff] [blame]1903// FIXME: When pairing store instructions it's very possible for this pass to
1904// hoist a store with a KILL marker above another use (without a KILL marker).
1905// The resulting IR is invalid, but nothing uses the KILL markers after this
1906// pass, so it's never caused a problem in practice.
1907
Chad Rosier43f5c842015-08-05 12:40:13 +0000[diff] [blame]1908/// createAArch64LoadStoreOptimizationPass - returns an instance of the
1909/// load / store optimization pass.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1910FunctionPass *llvm::createAArch64LoadStoreOptimizationPass() {
1911 return new AArch64LoadStoreOpt();
1912}