Blame - llvm/lib/Target/R600/AMDGPU.td - toolchain/llvm-project

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Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1	//===-- AMDIL.td - AMDIL Tablegen files --- tablegen --------------------===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//==-----------------------------------------------------------------------===//
				9
Tom Stellard	bc5b537	2014-06-13 16:38:59 +0000	[diff] [blame]	10	include "llvm/Target/Target.td"
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	11
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	12	//===----------------------------------------------------------------------===//
				13	// Subtarget Features
				14	//===----------------------------------------------------------------------===//
				15
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	16	// Debugging Features
				17
				18	def FeatureDumpCode : SubtargetFeature <"DumpCode",
				19	"DumpCode",
				20	"true",
				21	"Dump MachineInstrs in the CodeEmitter">;
				22
Tom Stellard	66df8a2	2013-11-18 19:43:44 +0000	[diff] [blame]	23	def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
Tom Stellard	ed0ceec	2013-10-10 17:11:12 +0000	[diff] [blame]	24	"EnableIRStructurizer",
Tom Stellard	66df8a2	2013-11-18 19:43:44 +0000	[diff] [blame]	25	"false",
				26	"Disable IR Structurizer">;
Tom Stellard	ed0ceec	2013-10-10 17:11:12 +0000	[diff] [blame]	27
Matt Arsenault	d9a23ab	2014-07-13 02:08:26 +0000	[diff] [blame]	28	def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
				29	"EnablePromoteAlloca",
				30	"true",
				31	"Enable promote alloca pass">;
				32
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	33	// Target features
				34
Tom Stellard	783893a	2013-11-18 19:43:33 +0000	[diff] [blame]	35	def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
				36	"EnableIfCvt",
				37	"false",
				38	"Disable the if conversion pass">;
				39
Matt Arsenault	f5e2997	2014-06-20 06:50:05 +0000	[diff] [blame]	40	def FeatureFP64 : SubtargetFeature<"fp64",
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	41	"FP64",
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	42	"true",
Matt Arsenault	f5e2997	2014-06-20 06:50:05 +0000	[diff] [blame]	43	"Enable double precision operations">;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	44
Matt Arsenault	f171cf2	2014-07-14 23:40:49 +0000	[diff] [blame]	45	def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
				46	"FP64Denormals",
				47	"true",
				48	"Enable double precision denormal handling",
				49	[FeatureFP64]>;
				50
				51	// Some instructions do not support denormals despite this flag. Using
				52	// fp32 denormals also causes instructions to run at the double
				53	// precision rate for the device.
				54	def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
				55	"FP32Denormals",
				56	"true",
				57	"Enable single precision denormal handling">;
				58
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	59	def Feature64BitPtr : SubtargetFeature<"64BitPtr",
				60	"Is64bit",
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	61	"true",
Matt Arsenault	f5e2997	2014-06-20 06:50:05 +0000	[diff] [blame]	62	"Specify if 64-bit addressing should be used">;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	63
				64	def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
				65	"R600ALUInst",
				66	"false",
Matt Arsenault	f5e2997	2014-06-20 06:50:05 +0000	[diff] [blame]	67	"Older version of ALU instructions encoding">;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	68
				69	def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
				70	"HasVertexCache",
				71	"true",
Matt Arsenault	f5e2997	2014-06-20 06:50:05 +0000	[diff] [blame]	72	"Specify use of dedicated vertex cache">;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	73
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	74	def FeatureCaymanISA : SubtargetFeature<"caymanISA",
				75	"CaymanISA",
				76	"true",
				77	"Use Cayman ISA">;
				78
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	79	def FeatureCFALUBug : SubtargetFeature<"cfalubug",
				80	"CFALUBug",
				81	"true",
				82	"GPU has CF_ALU bug">;
				83
Matt Arsenault	4103328	2014-10-10 22:01:59 +0000	[diff] [blame]	84	// XXX - This should probably be removed once enabled by default
				85	def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
				86	"EnableLoadStoreOpt",
				87	"true",
				88	"Enable SI load/store optimizer pass">;
				89
Matt Arsenault	3f98140	2014-09-15 15:41:53 +0000	[diff] [blame]	90	def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
				91	"FlatAddressSpace",
				92	"true",
				93	"Support flat address space">;
				94
Tom Stellard	e99fb65	2015-01-20 19:33:04 +0000	[diff] [blame^]	95	def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
				96	"EnableVGPRSpilling",
				97	"true",
				98	"Enable spilling of VGPRs to scratch memory">;
				99
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	100	class SubtargetFeatureFetchLimit <string Value> :
				101	SubtargetFeature <"fetch"#Value,
				102	"TexVTXClauseSize",
				103	Value,
				104	"Limit the maximum number of fetches in a clause to "#Value>;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	105
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	106	def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
				107	def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
				108
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	109	class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
				110	"wavefrontsize"#Value,
				111	"WavefrontSize",
				112	!cast<string>(Value),
				113	"The number of threads per wavefront">;
				114
				115	def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
				116	def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
				117	def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
				118
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	119	class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
				120	"localmemorysize"#Value,
				121	"LocalMemorySize",
				122	!cast<string>(Value),
				123	"The size of local memory in bytes">;
				124
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	125	class SubtargetFeatureGeneration <string Value,
				126	list<SubtargetFeature> Implies> :
				127	SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
				128	Value#" GPU generation", Implies>;
				129
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	130	def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
				131	def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
				132	def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
				133
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	134	def FeatureR600 : SubtargetFeatureGeneration<"R600",
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	135	[FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	136
				137	def FeatureR700 : SubtargetFeatureGeneration<"R700",
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	138	[FeatureFetchLimit16, FeatureLocalMemorySize0]>;
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	139
				140	def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	141	[FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	142
				143	def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
Tom Stellard	880a80a	2014-06-17 16:53:14 +0000	[diff] [blame]	144	[FeatureFetchLimit16, FeatureWavefrontSize64,
				145	FeatureLocalMemorySize32768]
				146	>;
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	147
				148	def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
Tom Stellard	42639a5	2014-07-21 15:44:58 +0000	[diff] [blame]	149	[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
				150	FeatureWavefrontSize64]>;
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	151
Tom Stellard	6e1ee47	2013-10-29 16:37:28 +0000	[diff] [blame]	152	def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
Tom Stellard	42639a5	2014-07-21 15:44:58 +0000	[diff] [blame]	153	[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
Matt Arsenault	3f98140	2014-09-15 15:41:53 +0000	[diff] [blame]	154	FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	155
				156	def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
				157	[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
				158	FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
				159
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	160	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	161
				162	def AMDGPUInstrInfo : InstrInfo {
				163	let guessInstructionProperties = 1;
				164	}
				165
Tom Stellard	9d7ddd5	2014-11-14 14:08:00 +0000	[diff] [blame]	166	def AMDGPUAsmParser : AsmParser {
				167	// Some of the R600 registers have the same name, so this crashes.
				168	// For example T0_XYZW and T0_XY both have the asm name T0.
				169	let ShouldEmitMatchRegisterName = 0;
				170	}
				171
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	172	def AMDGPU : Target {
				173	// Pull in Instruction Info:
				174	let InstructionSet = AMDGPUInstrInfo;
Tom Stellard	9d7ddd5	2014-11-14 14:08:00 +0000	[diff] [blame]	175	let AssemblyParsers = [AMDGPUAsmParser];
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	176	}
				177
Tom Stellard	bc5b537	2014-06-13 16:38:59 +0000	[diff] [blame]	178	// Dummy Instruction itineraries for pseudo instructions
				179	def ALU_NULL : FuncUnit;
				180	def NullALU : InstrItinClass;
				181
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	182	//===----------------------------------------------------------------------===//
				183	// Predicate helper class
				184	//===----------------------------------------------------------------------===//
				185
				186	class PredicateControl {
				187	Predicate SubtargetPredicate;
				188	list<Predicate> OtherPredicates = [];
				189	list<Predicate> Predicates = !listconcat([SubtargetPredicate],
				190	OtherPredicates);
				191	}
				192
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	193	// Include AMDGPU TD files
				194	include "R600Schedule.td"
				195	include "SISchedule.td"
				196	include "Processors.td"
				197	include "AMDGPUInstrInfo.td"
				198	include "AMDGPUIntrinsics.td"
				199	include "AMDGPURegisterInfo.td"
				200	include "AMDGPUInstructions.td"
Christian Konig	2c8f6d5	2013-03-07 09:03:52 +0000	[diff] [blame]	201	include "AMDGPUCallingConv.td"