Chris Lattner | 1e60a91 | 2003-12-20 01:22:19 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 2 | // |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 7 | // |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 9 | // |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 10 | // This file contains the X86 implementation of the TargetInstrInfo class. |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef X86INSTRUCTIONINFO_H |
| 15 | #define X86INSTRUCTIONINFO_H |
| 16 | |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 17 | #include "llvm/Target/TargetInstrInfo.h" |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 18 | #include "X86RegisterInfo.h" |
| 19 | |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 20 | namespace llvm { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 21 | class X86RegisterInfo; |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 22 | class X86TargetMachine; |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 23 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 24 | namespace X86 { |
| 25 | // X86 specific condition code. These correspond to X86_*_COND in |
| 26 | // X86InstrInfo.td. They must be kept in synch. |
| 27 | enum CondCode { |
| 28 | COND_A = 0, |
| 29 | COND_AE = 1, |
| 30 | COND_B = 2, |
| 31 | COND_BE = 3, |
| 32 | COND_E = 4, |
| 33 | COND_G = 5, |
| 34 | COND_GE = 6, |
| 35 | COND_L = 7, |
| 36 | COND_LE = 8, |
| 37 | COND_NE = 9, |
| 38 | COND_NO = 10, |
| 39 | COND_NP = 11, |
| 40 | COND_NS = 12, |
| 41 | COND_O = 13, |
| 42 | COND_P = 14, |
| 43 | COND_S = 15, |
| 44 | COND_INVALID |
| 45 | }; |
| 46 | |
| 47 | // Turn condition code into conditional branch opcode. |
| 48 | unsigned GetCondBranchFromCond(CondCode CC); |
Chris Lattner | 9cd6875 | 2006-10-21 05:52:40 +0000 | [diff] [blame] | 49 | |
| 50 | /// GetOppositeBranchCondition - Return the inverse of the specified cond, |
| 51 | /// e.g. turning COND_E to COND_NE. |
| 52 | CondCode GetOppositeBranchCondition(X86::CondCode CC); |
| 53 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 54 | } |
| 55 | |
Chris Lattner | 9d17740 | 2002-10-30 01:09:34 +0000 | [diff] [blame] | 56 | /// X86II - This namespace holds all of the target specific flags that |
| 57 | /// instruction info tracks. |
| 58 | /// |
| 59 | namespace X86II { |
| 60 | enum { |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 61 | //===------------------------------------------------------------------===// |
| 62 | // Instruction types. These are the standard/most common forms for X86 |
| 63 | // instructions. |
| 64 | // |
| 65 | |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 66 | // PseudoFrm - This represents an instruction that is a pseudo instruction |
| 67 | // or one that has not been implemented yet. It is illegal to code generate |
| 68 | // it, but tolerated for intermediate implementation stages. |
| 69 | Pseudo = 0, |
| 70 | |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 71 | /// Raw - This form is for instructions that don't have any operands, so |
| 72 | /// they are just a fixed opcode value, like 'leave'. |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 73 | RawFrm = 1, |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 74 | |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 75 | /// AddRegFrm - This form is used for instructions like 'push r32' that have |
| 76 | /// their one register operand added to their opcode. |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 77 | AddRegFrm = 2, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 78 | |
| 79 | /// MRMDestReg - This form is used for instructions that use the Mod/RM byte |
| 80 | /// to specify a destination, which in this case is a register. |
| 81 | /// |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 82 | MRMDestReg = 3, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 83 | |
| 84 | /// MRMDestMem - This form is used for instructions that use the Mod/RM byte |
| 85 | /// to specify a destination, which in this case is memory. |
| 86 | /// |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 87 | MRMDestMem = 4, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 88 | |
| 89 | /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte |
| 90 | /// to specify a source, which in this case is a register. |
| 91 | /// |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 92 | MRMSrcReg = 5, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 93 | |
| 94 | /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte |
| 95 | /// to specify a source, which in this case is memory. |
| 96 | /// |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 97 | MRMSrcMem = 6, |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 98 | |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 99 | /// MRM[0-7][rm] - These forms are used to represent instructions that use |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 100 | /// a Mod/RM byte, and use the middle field to hold extended opcode |
| 101 | /// information. In the intel manual these are represented as /0, /1, ... |
| 102 | /// |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 103 | |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 104 | // First, instructions that operate on a register r/m operand... |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 105 | MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 |
| 106 | MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 107 | |
| 108 | // Next, instructions that operate on a memory r/m operand... |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 109 | MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 |
| 110 | MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 111 | |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 112 | // MRMInitReg - This form is used for instructions whose source and |
| 113 | // destinations are the same register. |
| 114 | MRMInitReg = 32, |
| 115 | |
| 116 | FormMask = 63, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 117 | |
| 118 | //===------------------------------------------------------------------===// |
| 119 | // Actual flags... |
| 120 | |
Chris Lattner | 11e53e3 | 2002-11-21 01:32:55 +0000 | [diff] [blame] | 121 | // OpSize - Set if this instruction requires an operand size prefix (0x66), |
| 122 | // which most often indicates that the instruction operates on 16 bit data |
| 123 | // instead of 32 bit data. |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 124 | OpSize = 1 << 6, |
Brian Gaeke | 86764d7 | 2002-12-05 08:30:40 +0000 | [diff] [blame] | 125 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 126 | // AsSize - Set if this instruction requires an operand size prefix (0x67), |
| 127 | // which most often indicates that the instruction address 16 bit address |
| 128 | // instead of 32 bit address (or 32 bit address in 64 bit mode). |
| 129 | AdSize = 1 << 7, |
| 130 | |
| 131 | //===------------------------------------------------------------------===// |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 132 | // Op0Mask - There are several prefix bytes that are used to form two byte |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 133 | // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is |
| 134 | // used to obtain the setting of this field. If no bits in this field is |
| 135 | // set, there is no prefix byte for obtaining a multibyte opcode. |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 136 | // |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 137 | Op0Shift = 8, |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 138 | Op0Mask = 0xF << Op0Shift, |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 139 | |
| 140 | // TB - TwoByte - Set if this instruction has a two byte opcode, which |
| 141 | // starts with a 0x0F byte before the real opcode. |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 142 | TB = 1 << Op0Shift, |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 143 | |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 144 | // REP - The 0xF3 prefix byte indicating repetition of the following |
| 145 | // instruction. |
| 146 | REP = 2 << Op0Shift, |
| 147 | |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 148 | // D8-DF - These escape opcodes are used by the floating point unit. These |
| 149 | // values must remain sequential. |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 150 | D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, |
| 151 | DA = 5 << Op0Shift, DB = 6 << Op0Shift, |
| 152 | DC = 7 << Op0Shift, DD = 8 << Op0Shift, |
| 153 | DE = 9 << Op0Shift, DF = 10 << Op0Shift, |
Jeff Cohen | 9eb59ec | 2005-07-27 05:53:44 +0000 | [diff] [blame] | 154 | |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 155 | // XS, XD - These prefix codes are for single and double precision scalar |
| 156 | // floating point operations performed in the SSE registers. |
Bill Wendling | bb1ee05 | 2007-04-10 22:10:25 +0000 | [diff] [blame] | 157 | XD = 11 << Op0Shift, XS = 12 << Op0Shift, |
| 158 | |
| 159 | // T8, TA - Prefix after the 0x0F prefix. |
| 160 | T8 = 13 << Op0Shift, TA = 14 << Op0Shift, |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 161 | |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 162 | //===------------------------------------------------------------------===// |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 163 | // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. |
| 164 | // They are used to specify GPRs and SSE registers, 64-bit operand size, |
| 165 | // etc. We only cares about REX.W and REX.R bits and only the former is |
| 166 | // statically determined. |
| 167 | // |
| 168 | REXShift = 12, |
| 169 | REX_W = 1 << REXShift, |
| 170 | |
| 171 | //===------------------------------------------------------------------===// |
| 172 | // This three-bit field describes the size of an immediate operand. Zero is |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 173 | // unused so that we can tell if we forgot to set a value. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 174 | ImmShift = 13, |
| 175 | ImmMask = 7 << ImmShift, |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 176 | Imm8 = 1 << ImmShift, |
| 177 | Imm16 = 2 << ImmShift, |
| 178 | Imm32 = 3 << ImmShift, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 179 | Imm64 = 4 << ImmShift, |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 180 | |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 181 | //===------------------------------------------------------------------===// |
| 182 | // FP Instruction Classification... Zero is non-fp instruction. |
| 183 | |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 184 | // FPTypeMask - Mask for all of the FP types... |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 185 | FPTypeShift = 16, |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 186 | FPTypeMask = 7 << FPTypeShift, |
| 187 | |
Chris Lattner | 79b1373 | 2004-01-30 22:24:18 +0000 | [diff] [blame] | 188 | // NotFP - The default, set for instructions that do not use FP registers. |
| 189 | NotFP = 0 << FPTypeShift, |
| 190 | |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 191 | // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 192 | ZeroArgFP = 1 << FPTypeShift, |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 193 | |
| 194 | // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 195 | OneArgFP = 2 << FPTypeShift, |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 196 | |
| 197 | // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a |
| 198 | // result back to ST(0). For example, fcos, fsqrt, etc. |
| 199 | // |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 200 | OneArgFPRW = 3 << FPTypeShift, |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 201 | |
| 202 | // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an |
| 203 | // explicit argument, storing the result to either ST(0) or the implicit |
| 204 | // argument. For example: fadd, fsub, fmul, etc... |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 205 | TwoArgFP = 4 << FPTypeShift, |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 206 | |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 207 | // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an |
| 208 | // explicit argument, but have no destination. Example: fucom, fucomi, ... |
| 209 | CompareFP = 5 << FPTypeShift, |
| 210 | |
Chris Lattner | 1c54a85 | 2004-03-31 22:02:13 +0000 | [diff] [blame] | 211 | // CondMovFP - "2 operand" floating point conditional move instructions. |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 212 | CondMovFP = 6 << FPTypeShift, |
Chris Lattner | 1c54a85 | 2004-03-31 22:02:13 +0000 | [diff] [blame] | 213 | |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 214 | // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 215 | SpecialFP = 7 << FPTypeShift, |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 216 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 217 | // Bits 19 -> 23 are unused |
| 218 | OpcodeShift = 24, |
Chris Lattner | d74ea2b | 2006-05-24 17:04:05 +0000 | [diff] [blame] | 219 | OpcodeMask = 0xFF << OpcodeShift |
Chris Lattner | 9d17740 | 2002-10-30 01:09:34 +0000 | [diff] [blame] | 220 | }; |
| 221 | } |
| 222 | |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 223 | class X86InstrInfo : public TargetInstrInfo { |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 224 | X86TargetMachine &TM; |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 225 | const X86RegisterInfo RI; |
| 226 | public: |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 227 | X86InstrInfo(X86TargetMachine &tm); |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 228 | |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 229 | /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 230 | /// such, whenever a client has an instance of instruction info, it should |
| 231 | /// always be able to get register info as well (through this method). |
| 232 | /// |
| 233 | virtual const MRegisterInfo &getRegisterInfo() const { return RI; } |
| 234 | |
Alkis Evlogimenos | 5e30002 | 2003-12-28 17:35:08 +0000 | [diff] [blame] | 235 | // Return true if the instruction is a register to register move and |
| 236 | // leave the source and dest operands in the passed parameters. |
| 237 | // |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 238 | bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, |
| 239 | unsigned& destReg) const; |
| 240 | unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; |
| 241 | unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 242 | bool isOtherReMaterializableLoad(MachineInstr *MI) const; |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 243 | |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 244 | /// convertToThreeAddress - This method must be implemented by targets that |
| 245 | /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target |
| 246 | /// may be able to convert a two-address instruction into a true |
| 247 | /// three-address instruction on demand. This allows the X86 target (for |
| 248 | /// example) to convert ADD and SHL instructions into LEA instructions if they |
| 249 | /// would require register copies due to two-addressness. |
| 250 | /// |
| 251 | /// This method returns a null pointer if the transformation cannot be |
| 252 | /// performed, otherwise it returns the new instruction. |
| 253 | /// |
Evan Cheng | ba59a1e | 2006-12-01 21:52:58 +0000 | [diff] [blame] | 254 | virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, |
| 255 | MachineBasicBlock::iterator &MBBI, |
| 256 | LiveVariables &LV) const; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 257 | |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 258 | /// commuteInstruction - We have a few instructions that must be hacked on to |
| 259 | /// commute them. |
| 260 | /// |
| 261 | virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; |
| 262 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 263 | // Branch analysis. |
| 264 | virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
| 265 | MachineBasicBlock *&FBB, |
| 266 | std::vector<MachineOperand> &Cond) const; |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 267 | virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; |
| 268 | virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
| 269 | MachineBasicBlock *FBB, |
| 270 | const std::vector<MachineOperand> &Cond) const; |
Chris Lattner | c24ff8e | 2006-10-28 17:29:57 +0000 | [diff] [blame] | 271 | virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 272 | virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 273 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 274 | const TargetRegisterClass *getPointerRegClass() const; |
| 275 | |
Chris Lattner | f21dfcd | 2002-11-18 06:56:24 +0000 | [diff] [blame] | 276 | // getBaseOpcodeFor - This function returns the "base" X86 opcode for the |
| 277 | // specified opcode number. |
| 278 | // |
Evan Cheng | 19f2ffc | 2006-12-05 04:01:03 +0000 | [diff] [blame] | 279 | unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const { |
| 280 | return TID->TSFlags >> X86II::OpcodeShift; |
Chris Lattner | 4d18d5c | 2003-08-03 21:56:22 +0000 | [diff] [blame] | 281 | } |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 282 | }; |
| 283 | |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 284 | } // End llvm namespace |
| 285 | |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 286 | #endif |