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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00007//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Owen Anderson1ed5b712009-03-11 22:31:21 +000019#define DEBUG_TYPE "virtregmap"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Evan Chengc781a242009-05-03 18:32:42 +000022#include "llvm/CodeGen/LiveIntervalAnalysis.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000023#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000024#include "llvm/CodeGen/MachineFunction.h"
Evan Cheng4cce6b42008-04-11 17:53:36 +000025#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000026#include "llvm/CodeGen/MachineRegisterInfo.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000027#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000028#include "llvm/Target/TargetInstrInfo.h"
Mike Stumpfe095f32009-05-04 18:40:41 +000029#include "llvm/Target/TargetRegisterInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000030#include "llvm/Support/CommandLine.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000031#include "llvm/Support/Compiler.h"
Evan Cheng752272a2009-02-11 08:24:21 +000032#include "llvm/Support/Debug.h"
Evan Cheng957840b2007-02-21 02:22:03 +000033#include "llvm/ADT/BitVector.h"
Evan Chengcb742662008-06-04 09:16:33 +000034#include "llvm/ADT/DenseMap.h"
Evan Cheng752272a2009-02-11 08:24:21 +000035#include "llvm/ADT/DepthFirstIterator.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000036#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000038#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000039#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000040using namespace llvm;
41
Evan Cheng87bb9912008-06-13 23:58:02 +000042STATISTIC(NumSpills , "Number of register spills");
Dan Gohman844731a2008-05-13 00:00:25 +000043
Chris Lattner8c4d88d2004-09-30 01:54:45 +000044//===----------------------------------------------------------------------===//
45// VirtRegMap implementation
46//===----------------------------------------------------------------------===//
47
Owen Anderson49c8aa02009-03-13 05:55:11 +000048char VirtRegMap::ID = 0;
49
50static RegisterPass<VirtRegMap>
51X("virtregmap", "Virtual Register Map");
52
53bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
Evan Cheng90f95f82009-06-14 20:22:55 +000054 MRI = &mf.getRegInfo();
Owen Anderson49c8aa02009-03-13 05:55:11 +000055 TII = mf.getTarget().getInstrInfo();
Mike Stumpfe095f32009-05-04 18:40:41 +000056 TRI = mf.getTarget().getRegisterInfo();
Owen Anderson49c8aa02009-03-13 05:55:11 +000057 MF = &mf;
58
59 ReMatId = MAX_STACK_SLOT+1;
60 LowSpillSlot = HighSpillSlot = NO_STACK_SLOT;
61
62 Virt2PhysMap.clear();
63 Virt2StackSlotMap.clear();
64 Virt2ReMatIdMap.clear();
65 Virt2SplitMap.clear();
66 Virt2SplitKillMap.clear();
67 ReMatMap.clear();
68 ImplicitDefed.clear();
69 SpillSlotToUsesMap.clear();
70 MI2VirtMap.clear();
71 SpillPt2VirtMap.clear();
72 RestorePt2VirtMap.clear();
73 EmergencySpillMap.clear();
74 EmergencySpillSlots.clear();
75
Evan Chengd3653122008-02-27 03:04:06 +000076 SpillSlotToUsesMap.resize(8);
Owen Anderson49c8aa02009-03-13 05:55:11 +000077 ImplicitDefed.resize(MF->getRegInfo().getLastVirtReg()+1-
Evan Cheng4cce6b42008-04-11 17:53:36 +000078 TargetRegisterInfo::FirstVirtualRegister);
Mike Stumpfe095f32009-05-04 18:40:41 +000079
80 allocatableRCRegs.clear();
81 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
82 E = TRI->regclass_end(); I != E; ++I)
83 allocatableRCRegs.insert(std::make_pair(*I,
84 TRI->getAllocatableSet(mf, *I)));
85
Chris Lattner29268692006-09-05 02:12:02 +000086 grow();
Owen Anderson49c8aa02009-03-13 05:55:11 +000087
88 return false;
Chris Lattner29268692006-09-05 02:12:02 +000089}
90
Chris Lattner8c4d88d2004-09-30 01:54:45 +000091void VirtRegMap::grow() {
Owen Anderson49c8aa02009-03-13 05:55:11 +000092 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
Evan Cheng549f27d32007-08-13 23:45:17 +000093 Virt2PhysMap.grow(LastVirtReg);
94 Virt2StackSlotMap.grow(LastVirtReg);
95 Virt2ReMatIdMap.grow(LastVirtReg);
Evan Cheng81a03822007-11-17 00:40:40 +000096 Virt2SplitMap.grow(LastVirtReg);
Evan Chengadf85902007-12-05 09:51:10 +000097 Virt2SplitKillMap.grow(LastVirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +000098 ReMatMap.grow(LastVirtReg);
Evan Cheng4cce6b42008-04-11 17:53:36 +000099 ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1);
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000100}
101
Evan Cheng90f95f82009-06-14 20:22:55 +0000102unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
103 std::pair<MachineRegisterInfo::RegAllocHintType, unsigned> Hint =
104 MRI->getRegAllocationHint(virtReg);
105 switch (Hint.first) {
106 default: assert(0);
107 case MachineRegisterInfo::RA_None:
108 return 0;
109 case MachineRegisterInfo::RA_Preference:
110 if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
111 return Hint.second;
112 if (hasPhys(Hint.second))
113 return getPhys(Hint.second);
114 case MachineRegisterInfo::RA_PairEven: {
115 unsigned physReg = Hint.second;
116 if (TargetRegisterInfo::isPhysicalRegister(physReg))
117 return TRI->getRegisterPairEven(*MF, physReg);
118 else if (hasPhys(physReg))
119 return TRI->getRegisterPairEven(*MF, getPhys(physReg));
120 return 0;
121 }
122 case MachineRegisterInfo::RA_PairOdd: {
123 unsigned physReg = Hint.second;
124 if (TargetRegisterInfo::isPhysicalRegister(physReg))
125 return TRI->getRegisterPairOdd(*MF, physReg);
126 else if (hasPhys(physReg))
127 return TRI->getRegisterPairOdd(*MF, getPhys(physReg));
128 return 0;
129 }
130 }
131 // Shouldn't reach here.
132 return 0;
133}
134
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000135int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000136 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000137 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000138 "attempt to assign stack slot to already spilled register");
Owen Anderson49c8aa02009-03-13 05:55:11 +0000139 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
140 int SS = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
Evan Chengd3653122008-02-27 03:04:06 +0000141 RC->getAlignment());
142 if (LowSpillSlot == NO_STACK_SLOT)
143 LowSpillSlot = SS;
144 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
145 HighSpillSlot = SS;
146 unsigned Idx = SS-LowSpillSlot;
147 while (Idx >= SpillSlotToUsesMap.size())
148 SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
149 Virt2StackSlotMap[virtReg] = SS;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000150 ++NumSpills;
Evan Chengd3653122008-02-27 03:04:06 +0000151 return SS;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000152}
153
Evan Chengd3653122008-02-27 03:04:06 +0000154void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000155 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000156 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000157 "attempt to assign stack slot to already spilled register");
Evan Chengd3653122008-02-27 03:04:06 +0000158 assert((SS >= 0 ||
Owen Anderson49c8aa02009-03-13 05:55:11 +0000159 (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
Evan Cheng91935142007-04-04 07:40:01 +0000160 "illegal fixed frame index");
Evan Chengd3653122008-02-27 03:04:06 +0000161 Virt2StackSlotMap[virtReg] = SS;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +0000162}
163
Evan Cheng2638e1a2007-03-20 08:13:50 +0000164int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000165 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000166 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
Evan Cheng2638e1a2007-03-20 08:13:50 +0000167 "attempt to assign re-mat id to already spilled register");
Evan Cheng549f27d32007-08-13 23:45:17 +0000168 Virt2ReMatIdMap[virtReg] = ReMatId;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000169 return ReMatId++;
170}
171
Evan Cheng549f27d32007-08-13 23:45:17 +0000172void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000173 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000174 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
175 "attempt to assign re-mat id to already spilled register");
176 Virt2ReMatIdMap[virtReg] = id;
177}
178
Evan Cheng676dd7c2008-03-11 07:19:34 +0000179int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
180 std::map<const TargetRegisterClass*, int>::iterator I =
181 EmergencySpillSlots.find(RC);
182 if (I != EmergencySpillSlots.end())
183 return I->second;
Owen Anderson49c8aa02009-03-13 05:55:11 +0000184 int SS = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
Evan Cheng676dd7c2008-03-11 07:19:34 +0000185 RC->getAlignment());
186 if (LowSpillSlot == NO_STACK_SLOT)
187 LowSpillSlot = SS;
188 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
189 HighSpillSlot = SS;
Dan Gohman4daa9072008-10-06 18:00:07 +0000190 EmergencySpillSlots[RC] = SS;
Evan Cheng676dd7c2008-03-11 07:19:34 +0000191 return SS;
192}
193
Evan Chengd3653122008-02-27 03:04:06 +0000194void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
Owen Anderson49c8aa02009-03-13 05:55:11 +0000195 if (!MF->getFrameInfo()->isFixedObjectIndex(FI)) {
David Greenecff86082008-05-22 21:12:21 +0000196 // If FI < LowSpillSlot, this stack reference was produced by
197 // instruction selection and is not a spill
198 if (FI >= LowSpillSlot) {
199 assert(FI >= 0 && "Spill slot index should not be negative!");
Bill Wendlingf3061f82008-05-23 01:29:08 +0000200 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
David Greenecff86082008-05-22 21:12:21 +0000201 && "Invalid spill slot");
202 SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
203 }
Evan Chengd3653122008-02-27 03:04:06 +0000204 }
205}
206
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000207void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Evan Chengaee4af62007-12-02 08:30:39 +0000208 MachineInstr *NewMI, ModRef MRInfo) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000209 // Move previous memory references folded to new instruction.
210 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000211 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000212 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
213 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000214 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000215 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000216
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000217 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000218 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000219}
220
Evan Cheng7f566252007-10-13 02:50:24 +0000221void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
222 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
223 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
224}
225
Evan Chengd3653122008-02-27 03:04:06 +0000226void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
227 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
228 MachineOperand &MO = MI->getOperand(i);
Dan Gohmand735b802008-10-03 15:45:36 +0000229 if (!MO.isFI())
Evan Chengd3653122008-02-27 03:04:06 +0000230 continue;
231 int FI = MO.getIndex();
Owen Anderson49c8aa02009-03-13 05:55:11 +0000232 if (MF->getFrameInfo()->isFixedObjectIndex(FI))
Evan Chengd3653122008-02-27 03:04:06 +0000233 continue;
David Greenecff86082008-05-22 21:12:21 +0000234 // This stack reference was produced by instruction selection and
Bill Wendlinge67f5e42009-03-31 08:41:31 +0000235 // is not a spill
David Greenecff86082008-05-22 21:12:21 +0000236 if (FI < LowSpillSlot)
237 continue;
Bill Wendlingf3061f82008-05-23 01:29:08 +0000238 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
David Greenecff86082008-05-22 21:12:21 +0000239 && "Invalid spill slot");
Evan Chengd3653122008-02-27 03:04:06 +0000240 SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
241 }
242 MI2VirtMap.erase(MI);
243 SpillPt2VirtMap.erase(MI);
244 RestorePt2VirtMap.erase(MI);
Evan Cheng676dd7c2008-03-11 07:19:34 +0000245 EmergencySpillMap.erase(MI);
Evan Chengd3653122008-02-27 03:04:06 +0000246}
247
Evan Chengc781a242009-05-03 18:32:42 +0000248/// FindUnusedRegisters - Gather a list of allocatable registers that
249/// have not been allocated to any virtual register.
Evan Cheng90f95f82009-06-14 20:22:55 +0000250bool VirtRegMap::FindUnusedRegisters(LiveIntervals* LIs) {
Evan Chengc781a242009-05-03 18:32:42 +0000251 unsigned NumRegs = TRI->getNumRegs();
252 UnusedRegs.reset();
253 UnusedRegs.resize(NumRegs);
254
255 BitVector Used(NumRegs);
256 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
257 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
258 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
259 Used.set(Virt2PhysMap[i]);
260
261 BitVector Allocatable = TRI->getAllocatableSet(*MF);
262 bool AnyUnused = false;
263 for (unsigned Reg = 1; Reg < NumRegs; ++Reg) {
264 if (Allocatable[Reg] && !Used[Reg] && !LIs->hasInterval(Reg)) {
265 bool ReallyUnused = true;
266 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
267 if (Used[*AS] || LIs->hasInterval(*AS)) {
268 ReallyUnused = false;
269 break;
270 }
271 }
272 if (ReallyUnused) {
273 AnyUnused = true;
274 UnusedRegs.set(Reg);
275 }
276 }
277 }
278
279 return AnyUnused;
280}
281
Owen Anderson49c8aa02009-03-13 05:55:11 +0000282void VirtRegMap::print(std::ostream &OS, const Module* M) const {
283 const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000284
Chris Lattner7f690e62004-09-30 02:15:18 +0000285 OS << "********** REGISTER MAP **********\n";
Dan Gohman6f0d0242008-02-10 18:45:23 +0000286 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
Owen Anderson49c8aa02009-03-13 05:55:11 +0000287 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i) {
Chris Lattner7f690e62004-09-30 02:15:18 +0000288 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
Bill Wendlinge6d088a2008-02-26 21:47:57 +0000289 OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
Bill Wendling74ab84c2008-02-26 21:11:01 +0000290 << "]\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000291 }
292
Dan Gohman6f0d0242008-02-10 18:45:23 +0000293 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
Owen Anderson49c8aa02009-03-13 05:55:11 +0000294 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
Chris Lattner7f690e62004-09-30 02:15:18 +0000295 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
296 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
297 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000298}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000299
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000300void VirtRegMap::dump() const {
Dan Gohmanb5769312008-03-12 20:52:10 +0000301 print(cerr);
Daniel Dunbarcfbf05e2009-03-14 01:53:05 +0000302}