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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Evan Chengb6ca4b32007-08-14 23:25:37 +000039STATISTIC(NumDRM , "Number of re-materializable defs elided");
Chris Lattnercd3245a2006-12-19 22:41:21 +000040STATISTIC(NumStores, "Number of stores added");
41STATISTIC(NumLoads , "Number of loads added");
42STATISTIC(NumReused, "Number of values reused");
43STATISTIC(NumDSE , "Number of dead stores elided");
44STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000045
Chris Lattnercd3245a2006-12-19 22:41:21 +000046namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000047 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000048
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000049 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000050 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000051 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000052 cl::Prefix,
53 cl::values(clEnumVal(simple, " simple spiller"),
54 clEnumVal(local, " local spiller"),
55 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000056 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000057}
58
Chris Lattner8c4d88d2004-09-30 01:54:45 +000059//===----------------------------------------------------------------------===//
60// VirtRegMap implementation
61//===----------------------------------------------------------------------===//
62
Chris Lattner29268692006-09-05 02:12:02 +000063VirtRegMap::VirtRegMap(MachineFunction &mf)
64 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000065 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
Evan Cheng549f27d32007-08-13 23:45:17 +000066 Virt2ReMatIdMap(NO_STACK_SLOT), ReMatMap(NULL),
Evan Cheng2638e1a2007-03-20 08:13:50 +000067 ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000068 grow();
69}
70
Chris Lattner8c4d88d2004-09-30 01:54:45 +000071void VirtRegMap::grow() {
Evan Cheng549f27d32007-08-13 23:45:17 +000072 unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg();
73 Virt2PhysMap.grow(LastVirtReg);
74 Virt2StackSlotMap.grow(LastVirtReg);
75 Virt2ReMatIdMap.grow(LastVirtReg);
76 ReMatMap.grow(LastVirtReg);
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000077}
78
Chris Lattner8c4d88d2004-09-30 01:54:45 +000079int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
80 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000081 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000082 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000083 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
84 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
85 RC->getAlignment());
86 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000087 ++NumSpills;
88 return frameIndex;
89}
90
91void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
92 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000093 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000094 "attempt to assign stack slot to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +000095 assert((frameIndex >= 0 ||
96 (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) &&
97 "illegal fixed frame index");
Chris Lattner7f690e62004-09-30 02:15:18 +000098 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000099}
100
Evan Cheng2638e1a2007-03-20 08:13:50 +0000101int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
102 assert(MRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000103 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
Evan Cheng2638e1a2007-03-20 08:13:50 +0000104 "attempt to assign re-mat id to already spilled register");
Evan Cheng549f27d32007-08-13 23:45:17 +0000105 Virt2ReMatIdMap[virtReg] = ReMatId;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000106 return ReMatId++;
107}
108
Evan Cheng549f27d32007-08-13 23:45:17 +0000109void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
110 assert(MRegisterInfo::isVirtualRegister(virtReg));
111 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
112 "attempt to assign re-mat id to already spilled register");
113 Virt2ReMatIdMap[virtReg] = id;
114}
115
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000116void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +0000117 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000118 // Move previous memory references folded to new instruction.
119 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000120 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000121 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
122 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000123 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000124 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000125
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000126 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000127 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
128 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000129 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000130 // Folded a two-address operand.
131 MRInfo = isModRef;
132 } else if (OldMI->getOperand(OpNo).isDef()) {
133 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000134 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000135 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000136 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000137
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000138 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000139 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000140}
141
Evan Cheng7f566252007-10-13 02:50:24 +0000142void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
143 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
144 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
145}
146
Chris Lattner7f690e62004-09-30 02:15:18 +0000147void VirtRegMap::print(std::ostream &OS) const {
148 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000149
Chris Lattner7f690e62004-09-30 02:15:18 +0000150 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000151 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000152 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
153 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
154 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000155
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000156 }
157
158 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000159 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
160 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
161 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
162 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000163}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000164
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000165void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000166 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000167}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000168
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000169
170//===----------------------------------------------------------------------===//
171// Simple Spiller Implementation
172//===----------------------------------------------------------------------===//
173
174Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000175
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000176namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000177 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000178 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000179 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000180}
181
Chris Lattner35f27052006-05-01 21:16:03 +0000182bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000183 DOUT << "********** REWRITE MACHINE CODE **********\n";
184 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000185 const TargetMachine &TM = MF.getTarget();
186 const MRegisterInfo &MRI = *TM.getRegisterInfo();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000187
Chris Lattner4ea1b822004-09-30 02:33:48 +0000188 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
189 // each vreg once (in the case where a spilled vreg is used by multiple
190 // operands). This is always smaller than the number of operands to the
191 // current machine instr, so it should be small.
192 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000193
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000194 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
195 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000196 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000197 MachineBasicBlock &MBB = *MBBI;
198 for (MachineBasicBlock::iterator MII = MBB.begin(),
199 E = MBB.end(); MII != E; ++MII) {
200 MachineInstr &MI = *MII;
201 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000202 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000203 if (MO.isRegister() && MO.getReg())
204 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
205 unsigned VirtReg = MO.getReg();
206 unsigned PhysReg = VRM.getPhys(VirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000207 if (!VRM.isAssignedReg(VirtReg)) {
Chris Lattner886dd912005-04-04 21:35:34 +0000208 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000209 const TargetRegisterClass* RC =
210 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000211
Chris Lattner886dd912005-04-04 21:35:34 +0000212 if (MO.isUse() &&
213 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
214 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000215 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000216 LoadedRegs.push_back(VirtReg);
217 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000218 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000219 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000220
Chris Lattner886dd912005-04-04 21:35:34 +0000221 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000222 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000223 ++NumStores;
224 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000225 }
Evan Cheng6c087e52007-04-25 22:13:27 +0000226 MF.setPhysRegUsed(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000227 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000228 } else {
Evan Cheng6c087e52007-04-25 22:13:27 +0000229 MF.setPhysRegUsed(MO.getReg());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000230 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000231 }
Chris Lattner886dd912005-04-04 21:35:34 +0000232
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000233 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000234 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000235 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000236 }
237 return true;
238}
239
240//===----------------------------------------------------------------------===//
241// Local Spiller Implementation
242//===----------------------------------------------------------------------===//
243
244namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000245 /// LocalSpiller - This spiller does a simple pass over the machine basic
246 /// block to attempt to keep spills in registers as much as possible for
247 /// blocks that have low register pressure (the vreg may be spilled due to
248 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000249 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Evan Cheng32dfbea2007-10-12 08:50:34 +0000250 SSARegMap *RegMap;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000251 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000252 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000253 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000254 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Evan Cheng32dfbea2007-10-12 08:50:34 +0000255 RegMap = MF.getSSARegMap();
Chris Lattner7fb64342004-10-01 19:04:51 +0000256 MRI = MF.getTarget().getRegisterInfo();
257 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000258 DOUT << "\n**** Local spiller rewriting function '"
259 << MF.getFunction()->getName() << "':\n";
David Greene04fa32f2007-09-06 16:36:39 +0000260 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!) ****\n";
261 DEBUG(MF.dump());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000262
Chris Lattner7fb64342004-10-01 19:04:51 +0000263 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
264 MBB != E; ++MBB)
Evan Cheng549f27d32007-08-13 23:45:17 +0000265 RewriteMBB(*MBB, VRM);
David Greene04fa32f2007-09-06 16:36:39 +0000266
267 DOUT << "**** Post Machine Instrs ****\n";
268 DEBUG(MF.dump());
269
Chris Lattner7fb64342004-10-01 19:04:51 +0000270 return true;
271 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000272 private:
Evan Cheng549f27d32007-08-13 23:45:17 +0000273 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000274 };
275}
276
Chris Lattner66cf80f2006-02-03 23:13:58 +0000277/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
Evan Cheng549f27d32007-08-13 23:45:17 +0000278/// top down, keep track of which spills slots or remat are available in each
279/// register.
Chris Lattner593c9582006-02-03 23:28:46 +0000280///
281/// Note that not all physregs are created equal here. In particular, some
282/// physregs are reloads that we are allowed to clobber or ignore at any time.
283/// Other physregs are values that the register allocated program is using that
284/// we cannot CHANGE, but we can read if we like. We keep track of this on a
Evan Cheng549f27d32007-08-13 23:45:17 +0000285/// per-stack-slot / remat id basis as the low bit in the value of the
286/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
287/// this bit and addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000288namespace {
289class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000290 const MRegisterInfo *MRI;
291 const TargetInstrInfo *TII;
292
Evan Cheng549f27d32007-08-13 23:45:17 +0000293 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
294 // or remat'ed virtual register values that are still available, due to being
295 // loaded or stored to, but not invalidated yet.
296 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000297
Evan Cheng549f27d32007-08-13 23:45:17 +0000298 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
299 // indicating which stack slot values are currently held by a physreg. This
300 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
301 // physreg is modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000302 std::multimap<unsigned, int> PhysRegsAvailable;
303
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000304 void disallowClobberPhysRegOnly(unsigned PhysReg);
305
Chris Lattner66cf80f2006-02-03 23:13:58 +0000306 void ClobberPhysRegOnly(unsigned PhysReg);
307public:
308 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
309 : MRI(mri), TII(tii) {
310 }
311
Evan Cheng91e23902007-02-23 01:13:26 +0000312 const MRegisterInfo *getRegInfo() const { return MRI; }
313
Evan Cheng549f27d32007-08-13 23:45:17 +0000314 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
315 /// available in a physical register, return that PhysReg, otherwise
316 /// return 0.
317 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
318 std::map<int, unsigned>::const_iterator I =
319 SpillSlotsOrReMatsAvailable.find(Slot);
320 if (I != SpillSlotsOrReMatsAvailable.end()) {
Evan Chengb9591c62007-07-11 08:47:44 +0000321 return I->second >> 1; // Remove the CanClobber bit.
Evan Cheng91e23902007-02-23 01:13:26 +0000322 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000323 return 0;
324 }
Evan Chengde4e9422007-02-25 09:51:27 +0000325
Evan Cheng549f27d32007-08-13 23:45:17 +0000326 /// addAvailable - Mark that the specified stack slot / remat is available in
327 /// the specified physreg. If CanClobber is true, the physreg can be modified
328 /// at any time without changing the semantics of the program.
329 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg,
Evan Cheng91e23902007-02-23 01:13:26 +0000330 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000331 // If this stack slot is thought to be available in some other physreg,
332 // remove its record.
Evan Cheng549f27d32007-08-13 23:45:17 +0000333 ModifyStackSlotOrReMat(SlotOrReMat);
Chris Lattner86662492006-02-03 23:50:46 +0000334
Evan Cheng549f27d32007-08-13 23:45:17 +0000335 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
Evan Cheng90a43c32007-08-15 20:20:34 +0000336 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000337
Evan Cheng549f27d32007-08-13 23:45:17 +0000338 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
339 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000340 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000341 DOUT << "Remembering SS#" << SlotOrReMat;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000342 DOUT << " in physreg " << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000343 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000344
Chris Lattner593c9582006-02-03 23:28:46 +0000345 /// canClobberPhysReg - Return true if the spiller is allowed to change the
346 /// value of the specified stackslot register if it desires. The specified
347 /// stack slot must be available in a physreg for this query to make sense.
Evan Cheng549f27d32007-08-13 23:45:17 +0000348 bool canClobberPhysReg(int SlotOrReMat) const {
Evan Cheng90a43c32007-08-15 20:20:34 +0000349 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
350 "Value not available!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000351 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000352 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000353
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000354 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
355 /// stackslot register. The register is still available but is no longer
356 /// allowed to be modifed.
357 void disallowClobberPhysReg(unsigned PhysReg);
358
Chris Lattner66cf80f2006-02-03 23:13:58 +0000359 /// ClobberPhysReg - This is called when the specified physreg changes
360 /// value. We use this to invalidate any info about stuff we thing lives in
361 /// it and any of its aliases.
362 void ClobberPhysReg(unsigned PhysReg);
363
Evan Cheng90a43c32007-08-15 20:20:34 +0000364 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
365 /// slot changes. This removes information about which register the previous
366 /// value for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000367 void ModifyStackSlotOrReMat(int SlotOrReMat);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000368};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000369}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000370
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000371/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
372/// stackslot register. The register is still available but is no longer
373/// allowed to be modifed.
374void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
375 std::multimap<unsigned, int>::iterator I =
376 PhysRegsAvailable.lower_bound(PhysReg);
377 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000378 int SlotOrReMat = I->second;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000379 I++;
Evan Cheng549f27d32007-08-13 23:45:17 +0000380 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000381 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000382 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000383 DOUT << "PhysReg " << MRI->getName(PhysReg)
384 << " copied, it is available for use but can no longer be modified\n";
385 }
386}
387
388/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
389/// stackslot register and its aliases. The register and its aliases may
390/// still available but is no longer allowed to be modifed.
391void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
392 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
393 disallowClobberPhysRegOnly(*AS);
394 disallowClobberPhysRegOnly(PhysReg);
395}
396
Chris Lattner66cf80f2006-02-03 23:13:58 +0000397/// ClobberPhysRegOnly - This is called when the specified physreg changes
398/// value. We use this to invalidate any info about stuff we thing lives in it.
399void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
400 std::multimap<unsigned, int>::iterator I =
401 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000402 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000403 int SlotOrReMat = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000404 PhysRegsAvailable.erase(I++);
Evan Cheng549f27d32007-08-13 23:45:17 +0000405 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000406 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000407 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000408 DOUT << "PhysReg " << MRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000409 << " clobbered, invalidating ";
Evan Cheng549f27d32007-08-13 23:45:17 +0000410 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
411 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
Evan Cheng2638e1a2007-03-20 08:13:50 +0000412 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000413 DOUT << "SS#" << SlotOrReMat << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000414 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000415}
416
Chris Lattner66cf80f2006-02-03 23:13:58 +0000417/// ClobberPhysReg - This is called when the specified physreg changes
418/// value. We use this to invalidate any info about stuff we thing lives in
419/// it and any of its aliases.
420void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000421 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000422 ClobberPhysRegOnly(*AS);
423 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000424}
425
Evan Cheng90a43c32007-08-15 20:20:34 +0000426/// ModifyStackSlotOrReMat - This method is called when the value in a stack
427/// slot changes. This removes information about which register the previous
428/// value for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000429void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
Evan Cheng90a43c32007-08-15 20:20:34 +0000430 std::map<int, unsigned>::iterator It =
431 SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
Evan Cheng549f27d32007-08-13 23:45:17 +0000432 if (It == SpillSlotsOrReMatsAvailable.end()) return;
Evan Chengb9591c62007-07-11 08:47:44 +0000433 unsigned Reg = It->second >> 1;
Evan Cheng549f27d32007-08-13 23:45:17 +0000434 SpillSlotsOrReMatsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000435
436 // This register may hold the value of multiple stack slots, only remove this
437 // stack slot from the set of values the register contains.
438 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
439 for (; ; ++I) {
440 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
441 "Map inverse broken!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000442 if (I->second == SlotOrReMat) break;
Chris Lattner07cf1412006-02-03 00:36:31 +0000443 }
444 PhysRegsAvailable.erase(I);
445}
446
447
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000448
Evan Cheng28bb4622007-07-11 19:17:18 +0000449/// InvalidateKills - MI is going to be deleted. If any of its operands are
450/// marked kill, then invalidate the information.
451static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
Evan Chengc91f0b82007-08-14 20:23:13 +0000452 std::vector<MachineOperand*> &KillOps,
Evan Chengb6ca4b32007-08-14 23:25:37 +0000453 SmallVector<unsigned, 1> *KillRegs = NULL) {
Evan Cheng28bb4622007-07-11 19:17:18 +0000454 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
455 MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000456 if (!MO.isRegister() || !MO.isUse() || !MO.isKill())
Evan Cheng28bb4622007-07-11 19:17:18 +0000457 continue;
458 unsigned Reg = MO.getReg();
Evan Chengb6ca4b32007-08-14 23:25:37 +0000459 if (KillRegs)
460 KillRegs->push_back(Reg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000461 if (KillOps[Reg] == &MO) {
462 RegKills.reset(Reg);
463 KillOps[Reg] = NULL;
464 }
465 }
466}
467
Evan Chengb6ca4b32007-08-14 23:25:37 +0000468/// InvalidateRegDef - If the def operand of the specified def MI is now dead
469/// (since it's spill instruction is removed), mark it isDead. Also checks if
470/// the def MI has other definition operands that are not dead. Returns it by
471/// reference.
472static bool InvalidateRegDef(MachineBasicBlock::iterator I,
473 MachineInstr &NewDef, unsigned Reg,
474 bool &HasLiveDef) {
475 // Due to remat, it's possible this reg isn't being reused. That is,
476 // the def of this reg (by prev MI) is now dead.
477 MachineInstr *DefMI = I;
478 MachineOperand *DefOp = NULL;
479 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
480 MachineOperand &MO = DefMI->getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000481 if (MO.isRegister() && MO.isDef()) {
Evan Chengb6ca4b32007-08-14 23:25:37 +0000482 if (MO.getReg() == Reg)
483 DefOp = &MO;
484 else if (!MO.isDead())
485 HasLiveDef = true;
486 }
487 }
488 if (!DefOp)
489 return false;
490
491 bool FoundUse = false, Done = false;
492 MachineBasicBlock::iterator E = NewDef;
493 ++I; ++E;
494 for (; !Done && I != E; ++I) {
495 MachineInstr *NMI = I;
496 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
497 MachineOperand &MO = NMI->getOperand(j);
Dan Gohman92dfe202007-09-14 20:33:02 +0000498 if (!MO.isRegister() || MO.getReg() != Reg)
Evan Chengb6ca4b32007-08-14 23:25:37 +0000499 continue;
500 if (MO.isUse())
501 FoundUse = true;
502 Done = true; // Stop after scanning all the operands of this MI.
503 }
504 }
505 if (!FoundUse) {
506 // Def is dead!
507 DefOp->setIsDead();
508 return true;
509 }
510 return false;
511}
512
Evan Cheng28bb4622007-07-11 19:17:18 +0000513/// UpdateKills - Track and update kill info. If a MI reads a register that is
514/// marked kill, then it must be due to register reuse. Transfer the kill info
515/// over.
516static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
517 std::vector<MachineOperand*> &KillOps) {
518 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
519 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
520 MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000521 if (!MO.isRegister() || !MO.isUse())
Evan Cheng28bb4622007-07-11 19:17:18 +0000522 continue;
523 unsigned Reg = MO.getReg();
524 if (Reg == 0)
525 continue;
526
527 if (RegKills[Reg]) {
528 // That can't be right. Register is killed but not re-defined and it's
529 // being reused. Let's fix that.
530 KillOps[Reg]->unsetIsKill();
531 if (i < TID->numOperands &&
532 TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
533 // Unless it's a two-address operand, this is the new kill.
534 MO.setIsKill();
535 }
536
537 if (MO.isKill()) {
538 RegKills.set(Reg);
539 KillOps[Reg] = &MO;
540 }
541 }
542
543 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
544 const MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000545 if (!MO.isRegister() || !MO.isDef())
Evan Cheng28bb4622007-07-11 19:17:18 +0000546 continue;
547 unsigned Reg = MO.getReg();
548 RegKills.reset(Reg);
549 KillOps[Reg] = NULL;
550 }
551}
552
553
Chris Lattner7fb64342004-10-01 19:04:51 +0000554// ReusedOp - For each reused operand, we keep track of a bit of information, in
555// case we need to rollback upon processing a new operand. See comments below.
556namespace {
557 struct ReusedOp {
558 // The MachineInstr operand that reused an available value.
559 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000560
Evan Cheng549f27d32007-08-13 23:45:17 +0000561 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
562 unsigned StackSlotOrReMat;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000563
Chris Lattner7fb64342004-10-01 19:04:51 +0000564 // PhysRegReused - The physical register the value was available in.
565 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000566
Chris Lattner7fb64342004-10-01 19:04:51 +0000567 // AssignedPhysReg - The physreg that was assigned for use by the reload.
568 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000569
570 // VirtReg - The virtual register itself.
571 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000572
Chris Lattner8a61a752005-10-06 17:19:06 +0000573 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
574 unsigned vreg)
Evan Cheng90a43c32007-08-15 20:20:34 +0000575 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
576 AssignedPhysReg(apr), VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000577 };
Chris Lattner540fec62006-02-25 01:51:33 +0000578
579 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
580 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000581 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000582 MachineInstr &MI;
583 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000584 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000585 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000586 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000587 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000588 }
Chris Lattner540fec62006-02-25 01:51:33 +0000589
590 bool hasReuses() const {
591 return !Reuses.empty();
592 }
593
594 /// addReuse - If we choose to reuse a virtual register that is already
595 /// available instead of reloading it, remember that we did so.
Evan Cheng549f27d32007-08-13 23:45:17 +0000596 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
Chris Lattner540fec62006-02-25 01:51:33 +0000597 unsigned PhysRegReused, unsigned AssignedPhysReg,
598 unsigned VirtReg) {
599 // If the reload is to the assigned register anyway, no undo will be
600 // required.
601 if (PhysRegReused == AssignedPhysReg) return;
602
603 // Otherwise, remember this.
Evan Cheng549f27d32007-08-13 23:45:17 +0000604 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
Chris Lattner540fec62006-02-25 01:51:33 +0000605 AssignedPhysReg, VirtReg));
606 }
Evan Chenge077ef62006-11-04 00:21:55 +0000607
608 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000609 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000610 }
611
612 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000613 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000614 }
Chris Lattner540fec62006-02-25 01:51:33 +0000615
616 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
617 /// is some other operand that is using the specified register, either pick
618 /// a new register to use, or evict the previous reload and use this reg.
619 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
620 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000621 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000622 SmallSet<unsigned, 8> &Rejected,
623 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000624 std::vector<MachineOperand*> &KillOps,
625 VirtRegMap &VRM) {
Chris Lattner540fec62006-02-25 01:51:33 +0000626 if (Reuses.empty()) return PhysReg; // This is most often empty.
627
628 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
629 ReusedOp &Op = Reuses[ro];
630 // If we find some other reuse that was supposed to use this register
631 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000632 // register. That is, unless its reload register has already been
633 // considered and subsequently rejected because it has also been reused
634 // by another operand.
635 if (Op.PhysRegReused == PhysReg &&
636 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000637 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000638 unsigned NewReg = Op.AssignedPhysReg;
639 Rejected.insert(PhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000640 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000641 RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000642 } else {
643 // Otherwise, we might also have a problem if a previously reused
644 // value aliases the new register. If so, codegen the previous reload
645 // and use this one.
646 unsigned PRRU = Op.PhysRegReused;
647 const MRegisterInfo *MRI = Spills.getRegInfo();
648 if (MRI->areAliases(PRRU, PhysReg)) {
649 // Okay, we found out that an alias of a reused register
650 // was used. This isn't good because it means we have
651 // to undo a previous reuse.
652 MachineBasicBlock *MBB = MI->getParent();
653 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000654 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
655
656 // Copy Op out of the vector and remove it, we're going to insert an
657 // explicit load for it.
658 ReusedOp NewOp = Op;
659 Reuses.erase(Reuses.begin()+ro);
660
661 // Ok, we're going to try to reload the assigned physreg into the
662 // slot that we were supposed to in the first place. However, that
663 // register could hold a reuse. Check to see if it conflicts or
664 // would prefer us to use a different register.
665 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng28bb4622007-07-11 19:17:18 +0000666 MI, Spills, MaybeDeadStores,
Evan Cheng549f27d32007-08-13 23:45:17 +0000667 Rejected, RegKills, KillOps, VRM);
Chris Lattner28bad082006-02-25 02:17:31 +0000668
Evan Cheng549f27d32007-08-13 23:45:17 +0000669 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
670 MRI->reMaterialize(*MBB, MI, NewPhysReg,
671 VRM.getReMaterializedMI(NewOp.VirtReg));
672 ++NumReMats;
673 } else {
674 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
675 NewOp.StackSlotOrReMat, AliasRC);
Evan Chengfff3e192007-08-14 09:11:18 +0000676 // Any stores to this stack slot are not dead anymore.
677 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +0000678 ++NumLoads;
679 }
Chris Lattner28bad082006-02-25 02:17:31 +0000680 Spills.ClobberPhysReg(NewPhysReg);
681 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000682
Chris Lattnere53f4a02006-05-04 17:52:23 +0000683 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000684
Evan Cheng549f27d32007-08-13 23:45:17 +0000685 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000686 MachineBasicBlock::iterator MII = MI;
687 --MII;
688 UpdateKills(*MII, RegKills, KillOps);
689 DOUT << '\t' << *MII;
Chris Lattner540fec62006-02-25 01:51:33 +0000690
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000691 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000692 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000693
694 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000695 return PhysReg;
696 }
697 }
698 }
699 return PhysReg;
700 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000701
702 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
703 /// 'Rejected' set to remember which registers have been considered and
704 /// rejected for the reload. This avoids infinite looping in case like
705 /// this:
706 /// t1 := op t2, t3
707 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
708 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
709 /// t1 <- desires r1
710 /// sees r1 is taken by t2, tries t2's reload register r0
711 /// sees r0 is taken by t3, tries t3's reload register r1
712 /// sees r1 is taken by t2, tries t2's reload register r0 ...
713 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
714 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000715 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000716 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000717 std::vector<MachineOperand*> &KillOps,
718 VirtRegMap &VRM) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000719 SmallSet<unsigned, 8> Rejected;
Evan Cheng28bb4622007-07-11 19:17:18 +0000720 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000721 RegKills, KillOps, VRM);
Evan Cheng3c82cab2007-01-19 22:40:14 +0000722 }
Chris Lattner540fec62006-02-25 01:51:33 +0000723 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000724}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000725
Chris Lattner7fb64342004-10-01 19:04:51 +0000726
727/// rewriteMBB - Keep track of which spills are available even after the
728/// register allocator is done with them. If possible, avoid reloading vregs.
Evan Cheng549f27d32007-08-13 23:45:17 +0000729void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000730 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000731
Evan Chengfff3e192007-08-14 09:11:18 +0000732 MachineFunction &MF = *MBB.getParent();
733
Chris Lattner66cf80f2006-02-03 23:13:58 +0000734 // Spills - Keep track of which spilled values are available in physregs so
735 // that we can choose to reuse the physregs instead of emitting reloads.
736 AvailableSpills Spills(MRI, TII);
737
Chris Lattner52b25db2004-10-01 19:47:12 +0000738 // MaybeDeadStores - When we need to write a value back into a stack slot,
739 // keep track of the inserted store. If the stack slot value is never read
740 // (because the value was used from some available register, for example), and
741 // subsequently stored to, the original store is dead. This map keeps track
742 // of inserted stores that are not used. If we see a subsequent store to the
743 // same stack slot, the original store is deleted.
Evan Chengfff3e192007-08-14 09:11:18 +0000744 std::vector<MachineInstr*> MaybeDeadStores;
745 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
Chris Lattner52b25db2004-10-01 19:47:12 +0000746
Evan Chengb6ca4b32007-08-14 23:25:37 +0000747 // ReMatDefs - These are rematerializable def MIs which are not deleted.
748 SmallSet<MachineInstr*, 4> ReMatDefs;
749
Evan Cheng0c40d722007-07-11 05:28:39 +0000750 // Keep track of kill information.
751 BitVector RegKills(MRI->getNumRegs());
752 std::vector<MachineOperand*> KillOps;
753 KillOps.resize(MRI->getNumRegs(), NULL);
754
Chris Lattner7fb64342004-10-01 19:04:51 +0000755 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
756 MII != E; ) {
757 MachineInstr &MI = *MII;
758 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
Evan Cheng0c40d722007-07-11 05:28:39 +0000759 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
760
761 bool Erased = false;
762 bool BackTracked = false;
Chris Lattner7fb64342004-10-01 19:04:51 +0000763
Chris Lattner540fec62006-02-25 01:51:33 +0000764 /// ReusedOperands - Keep track of operand reuse in case we need to undo
765 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000766 ReuseInfo ReusedOperands(MI, MRI);
767
768 // Loop over all of the implicit defs, clearing them from our available
769 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000770 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
Evan Cheng0c40d722007-07-11 05:28:39 +0000771 if (TID->ImplicitDefs) {
772 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000773 for ( ; *ImpDef; ++ImpDef) {
Evan Cheng6c087e52007-04-25 22:13:27 +0000774 MF.setPhysRegUsed(*ImpDef);
Evan Chenge077ef62006-11-04 00:21:55 +0000775 ReusedOperands.markClobbered(*ImpDef);
776 Spills.ClobberPhysReg(*ImpDef);
777 }
778 }
779
Chris Lattner7fb64342004-10-01 19:04:51 +0000780 // Process all of the spilled uses and all non spilled reg references.
781 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
782 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000783 if (!MO.isRegister() || MO.getReg() == 0)
784 continue; // Ignore non-register operands.
785
Evan Cheng32dfbea2007-10-12 08:50:34 +0000786 unsigned VirtReg = MO.getReg();
787 if (MRegisterInfo::isPhysicalRegister(VirtReg)) {
Chris Lattner50ea01e2005-09-09 20:29:51 +0000788 // Ignore physregs for spilling, but remember that it is used by this
789 // function.
Evan Cheng32dfbea2007-10-12 08:50:34 +0000790 MF.setPhysRegUsed(VirtReg);
791 ReusedOperands.markClobbered(VirtReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000792 continue;
793 }
794
Evan Cheng32dfbea2007-10-12 08:50:34 +0000795 assert(MRegisterInfo::isVirtualRegister(VirtReg) &&
Chris Lattner50ea01e2005-09-09 20:29:51 +0000796 "Not a virtual or a physical register?");
797
Evan Cheng32dfbea2007-10-12 08:50:34 +0000798 unsigned SubIdx = 0;
799 bool isSubReg = RegMap->isSubRegister(VirtReg);
800 if (isSubReg) {
801 SubIdx = RegMap->getSubRegisterIndex(VirtReg);
802 VirtReg = RegMap->getSuperRegister(VirtReg);
803 }
804
Evan Cheng549f27d32007-08-13 23:45:17 +0000805 if (VRM.isAssignedReg(VirtReg)) {
Chris Lattner50ea01e2005-09-09 20:29:51 +0000806 // This virtual register was assigned a physreg!
807 unsigned Phys = VRM.getPhys(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +0000808 MF.setPhysRegUsed(Phys);
Evan Chenge077ef62006-11-04 00:21:55 +0000809 if (MO.isDef())
810 ReusedOperands.markClobbered(Phys);
Evan Cheng32dfbea2007-10-12 08:50:34 +0000811 unsigned RReg = isSubReg ? MRI->getSubReg(Phys, SubIdx) : Phys;
812 MI.getOperand(i).setReg(RReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000813 continue;
814 }
815
816 // This virtual register is now known to be a spilled value.
817 if (!MO.isUse())
818 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000819
Evan Cheng549f27d32007-08-13 23:45:17 +0000820 bool DoReMat = VRM.isReMaterialized(VirtReg);
821 int SSorRMId = DoReMat
822 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
Evan Chengdc6be192007-08-14 05:42:54 +0000823 int ReuseSlot = SSorRMId;
Chris Lattner7fb64342004-10-01 19:04:51 +0000824
Chris Lattner50ea01e2005-09-09 20:29:51 +0000825 // Check to see if this stack slot is available.
Evan Chengdc6be192007-08-14 05:42:54 +0000826 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
827 if (!PhysReg && DoReMat) {
828 // This use is rematerializable. But perhaps the value is available in
829 // stack if the definition is not deleted. If so, check if we can
830 // reuse the value.
831 ReuseSlot = VRM.getStackSlot(VirtReg);
832 if (ReuseSlot != VirtRegMap::NO_STACK_SLOT)
833 PhysReg = Spills.getSpillSlotOrReMatPhysReg(ReuseSlot);
834 }
Evan Cheng32dfbea2007-10-12 08:50:34 +0000835
836 // If this is a sub-register use, make sure the reuse register is in the
837 // right register class. For example, for x86 not all of the 32-bit
838 // registers have accessible sub-registers.
839 // Similarly so for EXTRACT_SUBREG. Consider this:
840 // EDI = op
841 // MOV32_mr fi#1, EDI
842 // ...
843 // = EXTRACT_SUBREG fi#1
844 // fi#1 is available in EDI, but it cannot be reused because it's not in
845 // the right register file.
846 if (PhysReg &&
847 (isSubReg || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
848 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
849 if (!RC->contains(PhysReg))
850 PhysReg = 0;
851 }
852
Evan Chengdc6be192007-08-14 05:42:54 +0000853 if (PhysReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000854 // This spilled operand might be part of a two-address operand. If this
855 // is the case, then changing it will necessarily require changing the
856 // def part of the instruction as well. However, in some cases, we
857 // aren't allowed to modify the reused register. If none of these cases
858 // apply, reuse it.
859 bool CanReuse = true;
Evan Cheng32dfbea2007-10-12 08:50:34 +0000860
Evan Cheng86facc22006-12-15 06:41:01 +0000861 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000862 if (ti != -1 &&
Dan Gohman92dfe202007-09-14 20:33:02 +0000863 MI.getOperand(ti).isRegister() &&
Evan Cheng360c2dd2006-11-01 23:06:55 +0000864 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000865 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000866 // long as we are allowed to clobber the value and there isn't an
867 // earlier def that has already clobbered the physreg.
Evan Chengdc6be192007-08-14 05:42:54 +0000868 CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
Evan Chenge077ef62006-11-04 00:21:55 +0000869 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000870 }
871
872 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000873 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +0000874 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
875 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000876 else
Evan Chengdc6be192007-08-14 05:42:54 +0000877 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000878 DOUT << " from physreg "
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000879 << MRI->getName(PhysReg) << " for vreg"
880 << VirtReg <<" instead of reloading into physreg "
881 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Evan Cheng32dfbea2007-10-12 08:50:34 +0000882 unsigned RReg = isSubReg ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
883 MI.getOperand(i).setReg(RReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000884
885 // The only technical detail we have is that we don't know that
886 // PhysReg won't be clobbered by a reloaded stack slot that occurs
887 // later in the instruction. In particular, consider 'op V1, V2'.
888 // If V1 is available in physreg R0, we would choose to reuse it
889 // here, instead of reloading it into the register the allocator
890 // indicated (say R1). However, V2 might have to be reloaded
891 // later, and it might indicate that it needs to live in R0. When
892 // this occurs, we need to have information available that
893 // indicates it is safe to use R1 for the reload instead of R0.
894 //
895 // To further complicate matters, we might conflict with an alias,
896 // or R0 and R1 might not be compatible with each other. In this
897 // case, we actually insert a reload for V1 in R1, ensuring that
898 // we can get at R0 or its alias.
Evan Chengdc6be192007-08-14 05:42:54 +0000899 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
Chris Lattneraddc55a2006-04-28 01:46:50 +0000900 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000901 if (ti != -1)
902 // Only mark it clobbered if this is a use&def operand.
903 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000904 ++NumReused;
Evan Chengfff3e192007-08-14 09:11:18 +0000905
906 if (MI.getOperand(i).isKill() &&
907 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
908 // This was the last use and the spilled value is still available
909 // for reuse. That means the spill was unnecessary!
910 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot];
911 if (DeadStore) {
912 DOUT << "Removed dead store:\t" << *DeadStore;
913 InvalidateKills(*DeadStore, RegKills, KillOps);
914 MBB.erase(DeadStore);
915 VRM.RemoveFromFoldedVirtMap(DeadStore);
916 MaybeDeadStores[ReuseSlot] = NULL;
917 ++NumDSE;
918 }
919 }
Chris Lattneraddc55a2006-04-28 01:46:50 +0000920 continue;
Evan Cheng32dfbea2007-10-12 08:50:34 +0000921 } // CanReuse
Chris Lattneraddc55a2006-04-28 01:46:50 +0000922
923 // Otherwise we have a situation where we have a two-address instruction
924 // whose mod/ref operand needs to be reloaded. This reload is already
925 // available in some register "PhysReg", but if we used PhysReg as the
926 // operand to our 2-addr instruction, the instruction would modify
927 // PhysReg. This isn't cool if something later uses PhysReg and expects
928 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000929 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000930 // To avoid this problem, and to avoid doing a load right after a store,
931 // we emit a copy from PhysReg into the designated register for this
932 // operand.
933 unsigned DesignatedReg = VRM.getPhys(VirtReg);
934 assert(DesignatedReg && "Must map virtreg to physreg!");
935
936 // Note that, if we reused a register for a previous operand, the
937 // register we want to reload into might not actually be
938 // available. If this occurs, use the register indicated by the
939 // reuser.
940 if (ReusedOperands.hasReuses())
941 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +0000942 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000943
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000944 // If the mapped designated register is actually the physreg we have
945 // incoming, we don't need to inserted a dead copy.
946 if (DesignatedReg == PhysReg) {
947 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +0000948 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
949 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000950 else
Evan Chengdc6be192007-08-14 05:42:54 +0000951 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000952 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000953 << VirtReg
954 << " instead of reloading into same physreg.\n";
Evan Cheng32dfbea2007-10-12 08:50:34 +0000955 unsigned RReg = isSubReg ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
956 MI.getOperand(i).setReg(RReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000957 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000958 ++NumReused;
959 continue;
960 }
961
Evan Cheng32dfbea2007-10-12 08:50:34 +0000962 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +0000963 MF.setPhysRegUsed(DesignatedReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000964 ReusedOperands.markClobbered(DesignatedReg);
Evan Cheng9efce632007-09-26 06:25:56 +0000965 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
Evan Chengde4e9422007-02-25 09:51:27 +0000966
Evan Cheng6b448092007-03-02 08:52:00 +0000967 MachineInstr *CopyMI = prior(MII);
Evan Cheng0c40d722007-07-11 05:28:39 +0000968 UpdateKills(*CopyMI, RegKills, KillOps);
Evan Chengde4e9422007-02-25 09:51:27 +0000969
Chris Lattneraddc55a2006-04-28 01:46:50 +0000970 // This invalidates DesignatedReg.
971 Spills.ClobberPhysReg(DesignatedReg);
972
Evan Chengdc6be192007-08-14 05:42:54 +0000973 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
Evan Cheng32dfbea2007-10-12 08:50:34 +0000974 unsigned RReg =
975 isSubReg ? MRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
976 MI.getOperand(i).setReg(RReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000977 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000978 ++NumReused;
979 continue;
Evan Cheng32dfbea2007-10-12 08:50:34 +0000980 } // is (PhysReg)
Chris Lattner50ea01e2005-09-09 20:29:51 +0000981
982 // Otherwise, reload it and remember that we have it.
983 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000984 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattner7fb64342004-10-01 19:04:51 +0000985
Chris Lattner50ea01e2005-09-09 20:29:51 +0000986 // Note that, if we reused a register for a previous operand, the
987 // register we want to reload into might not actually be
988 // available. If this occurs, use the register indicated by the
989 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000990 if (ReusedOperands.hasReuses())
991 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +0000992 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000993
Evan Cheng6c087e52007-04-25 22:13:27 +0000994 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000995 ReusedOperands.markClobbered(PhysReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000996 if (DoReMat) {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000997 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
Evan Cheng91935142007-04-04 07:40:01 +0000998 ++NumReMats;
999 } else {
Evan Cheng32dfbea2007-10-12 08:50:34 +00001000 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +00001001 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
Evan Cheng91935142007-04-04 07:40:01 +00001002 ++NumLoads;
1003 }
Chris Lattner50ea01e2005-09-09 20:29:51 +00001004 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001005 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001006
1007 // Any stores to this stack slot are not dead anymore.
Evan Cheng549f27d32007-08-13 23:45:17 +00001008 if (!DoReMat)
Evan Chengfff3e192007-08-14 09:11:18 +00001009 MaybeDeadStores[SSorRMId] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +00001010 Spills.addAvailable(SSorRMId, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +00001011 // Assumes this is the last use. IsKill will be unset if reg is reused
1012 // unless it's a two-address operand.
1013 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
1014 MI.getOperand(i).setIsKill();
Evan Cheng32dfbea2007-10-12 08:50:34 +00001015 unsigned RReg = isSubReg ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1016 MI.getOperand(i).setReg(RReg);
Evan Cheng0c40d722007-07-11 05:28:39 +00001017 UpdateKills(*prior(MII), RegKills, KillOps);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001018 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001019 }
1020
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001021 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001022
Chris Lattner7fb64342004-10-01 19:04:51 +00001023 // If we have folded references to memory operands, make sure we clear all
1024 // physical registers that may contain the value of the spilled virtual
1025 // register
Evan Cheng90a43c32007-08-15 20:20:34 +00001026 SmallSet<int, 1> FoldedSS;
Chris Lattner8f1d6402005-01-14 15:54:24 +00001027 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001028 DOUT << "Folded vreg: " << I->second.first << " MR: "
1029 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +00001030 unsigned VirtReg = I->second.first;
1031 VirtRegMap::ModRef MR = I->second.second;
Evan Cheng549f27d32007-08-13 23:45:17 +00001032 if (VRM.isAssignedReg(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001033 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +00001034 continue;
1035 }
1036 int SS = VRM.getStackSlot(VirtReg);
Evan Cheng90a43c32007-08-15 20:20:34 +00001037 FoldedSS.insert(SS);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001038 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +00001039
1040 // If this folded instruction is just a use, check to see if it's a
1041 // straight load from the virt reg slot.
1042 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
1043 int FrameIdx;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001044 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
1045 if (DestReg && FrameIdx == SS) {
1046 // If this spill slot is available, turn it into a copy (or nothing)
1047 // instead of leaving it as a load!
1048 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
1049 DOUT << "Promoted Load To Copy: " << MI;
1050 if (DestReg != InReg) {
1051 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
1052 MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
1053 // Revisit the copy so we make sure to notice the effects of the
1054 // operation on the destreg (either needing to RA it if it's
1055 // virtual or needing to clobber any values if it's physical).
1056 NextMII = &MI;
1057 --NextMII; // backtrack to the copy.
1058 BackTracked = true;
1059 } else
1060 DOUT << "Removing now-noop copy: " << MI;
Evan Chengde4e9422007-02-25 09:51:27 +00001061
Evan Cheng32dfbea2007-10-12 08:50:34 +00001062 VRM.RemoveFromFoldedVirtMap(&MI);
1063 MBB.erase(&MI);
1064 Erased = true;
1065 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +00001066 }
Evan Cheng7f566252007-10-13 02:50:24 +00001067 } else {
1068 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1069 SmallVector<MachineInstr*, 4> NewMIs;
1070 if (PhysReg &&
1071 MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
1072 MBB.insert(MII, NewMIs[0]);
1073 VRM.RemoveFromFoldedVirtMap(&MI);
1074 MBB.erase(&MI);
1075 Erased = true;
1076 --NextMII; // backtrack to the unfolded instruction.
1077 BackTracked = true;
1078 goto ProcessNextInst;
1079 }
Chris Lattnercea86882005-09-19 06:56:21 +00001080 }
1081 }
1082
1083 // If this reference is not a use, any previous store is now dead.
1084 // Otherwise, the store to this stack slot is not dead anymore.
Evan Chengfff3e192007-08-14 09:11:18 +00001085 MachineInstr* DeadStore = MaybeDeadStores[SS];
1086 if (DeadStore) {
Evan Cheng7f566252007-10-13 02:50:24 +00001087 bool isDead = true;
1088 MachineInstr *NewStore = NULL;
1089 if (MR & VirtRegMap::isRef) {
1090 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1091 SmallVector<MachineInstr*, 4> NewMIs;
1092 if (PhysReg &&
1093 DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 &&
1094 MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) {
1095 MBB.insert(MII, NewMIs[0]);
1096 NewStore = NewMIs[1];
1097 MBB.insert(MII, NewStore);
1098 VRM.RemoveFromFoldedVirtMap(&MI);
1099 MBB.erase(&MI);
1100 Erased = true;
1101 --NextMII;
1102 --NextMII; // backtrack to the unfolded instruction.
1103 BackTracked = true;
1104 } else
1105 isDead = false;
1106 }
1107
1108 if (isDead) { // Previous store is dead.
Chris Lattnercea86882005-09-19 06:56:21 +00001109 // If we get here, the store is dead, nuke it now.
Evan Chengfff3e192007-08-14 09:11:18 +00001110 DOUT << "Removed dead store:\t" << *DeadStore;
1111 InvalidateKills(*DeadStore, RegKills, KillOps);
Evan Chengfff3e192007-08-14 09:11:18 +00001112 VRM.RemoveFromFoldedVirtMap(DeadStore);
Evan Cheng7f566252007-10-13 02:50:24 +00001113 MBB.erase(DeadStore);
1114 if (!NewStore)
1115 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +00001116 }
Evan Cheng7f566252007-10-13 02:50:24 +00001117
Evan Chengfff3e192007-08-14 09:11:18 +00001118 MaybeDeadStores[SS] = NULL;
Evan Cheng7f566252007-10-13 02:50:24 +00001119 if (NewStore) {
1120 // Treat this store as a spill merged into a copy. That makes the
1121 // stack slot value available.
1122 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
1123 goto ProcessNextInst;
1124 }
Chris Lattnercea86882005-09-19 06:56:21 +00001125 }
1126
1127 // If the spill slot value is available, and this is a new definition of
1128 // the value, the value is not available anymore.
1129 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +00001130 // Notice that the value in this stack slot has been modified.
Evan Cheng549f27d32007-08-13 23:45:17 +00001131 Spills.ModifyStackSlotOrReMat(SS);
Chris Lattnercd816392006-02-02 23:29:36 +00001132
1133 // If this is *just* a mod of the value, check to see if this is just a
1134 // store to the spill slot (i.e. the spill got merged into the copy). If
1135 // so, realize that the vreg is available now, and add the store to the
1136 // MaybeDeadStore info.
1137 int StackSlot;
1138 if (!(MR & VirtRegMap::isRef)) {
1139 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1140 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
1141 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +00001142 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +00001143 // this as a potentially dead store in case there is a subsequent
1144 // store into the stack slot without a read from it.
1145 MaybeDeadStores[StackSlot] = &MI;
1146
Chris Lattnercd816392006-02-02 23:29:36 +00001147 // If the stack slot value was previously available in some other
1148 // register, change it now. Otherwise, make the register available,
1149 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +00001150 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +00001151 }
1152 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001153 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001154 }
1155
Chris Lattner7fb64342004-10-01 19:04:51 +00001156 // Process all of the spilled defs.
1157 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1158 MachineOperand &MO = MI.getOperand(i);
1159 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
1160 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001161
Chris Lattner7fb64342004-10-01 19:04:51 +00001162 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +00001163 // Check to see if this is a noop copy. If so, eliminate the
1164 // instruction before considering the dest reg to be changed.
1165 unsigned Src, Dst;
1166 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1167 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001168 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +00001169 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001170 Erased = true;
Chris Lattner29268692006-09-05 02:12:02 +00001171 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +00001172 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +00001173 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001174 }
Chris Lattner6ec36262006-10-12 17:45:38 +00001175
1176 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +00001177 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001178 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001179
1180 // Check to see if this instruction is a load from a stack slot into
1181 // a register. If so, this provides the stack slot value in the reg.
1182 int FrameIdx;
1183 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1184 assert(DestReg == VirtReg && "Unknown load situation!");
Evan Cheng90a43c32007-08-15 20:20:34 +00001185
1186 // If it is a folded reference, then it's not safe to clobber.
1187 bool Folded = FoldedSS.count(FrameIdx);
Chris Lattner6ec36262006-10-12 17:45:38 +00001188 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng90a43c32007-08-15 20:20:34 +00001189 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded);
Chris Lattner6ec36262006-10-12 17:45:38 +00001190 goto ProcessNextInst;
1191 }
1192
Chris Lattner29268692006-09-05 02:12:02 +00001193 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +00001194 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001195
Evan Chengb6ca4b32007-08-14 23:25:37 +00001196 bool DoReMat = VRM.isReMaterialized(VirtReg);
1197 if (DoReMat)
1198 ReMatDefs.insert(&MI);
1199
Chris Lattner84e752a2006-02-03 03:06:49 +00001200 // The only vregs left are stack slot definitions.
1201 int StackSlot = VRM.getStackSlot(VirtReg);
Evan Cheng32dfbea2007-10-12 08:50:34 +00001202 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001203
Chris Lattner29268692006-09-05 02:12:02 +00001204 // If this def is part of a two-address operand, make sure to execute
1205 // the store from the correct physical register.
1206 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +00001207 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001208 if (TiedOp != -1)
1209 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +00001210 else {
Chris Lattner29268692006-09-05 02:12:02 +00001211 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001212 if (ReusedOperands.isClobbered(PhysReg)) {
1213 // Another def has taken the assigned physreg. It must have been a
1214 // use&def which got it due to reuse. Undo the reuse!
1215 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +00001216 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Evan Chenge077ef62006-11-04 00:21:55 +00001217 }
1218 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001219
Evan Cheng6c087e52007-04-25 22:13:27 +00001220 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001221 ReusedOperands.markClobbered(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +00001222 MI.getOperand(i).setReg(PhysReg);
Evan Chengb6ca4b32007-08-14 23:25:37 +00001223 if (!MO.isDead()) {
1224 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
1225 DOUT << "Store:\t" << *next(MII);
Chris Lattner7fb64342004-10-01 19:04:51 +00001226
Evan Chengb6ca4b32007-08-14 23:25:37 +00001227 // If there is a dead store to this stack slot, nuke it now.
1228 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1229 if (LastStore) {
1230 DOUT << "Removed dead store:\t" << *LastStore;
1231 ++NumDSE;
1232 SmallVector<unsigned, 1> KillRegs;
1233 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs);
1234 MachineBasicBlock::iterator PrevMII = LastStore;
1235 bool CheckDef = PrevMII != MBB.begin();
1236 if (CheckDef)
1237 --PrevMII;
1238 MBB.erase(LastStore);
1239 VRM.RemoveFromFoldedVirtMap(LastStore);
1240 if (CheckDef) {
1241 // Look at defs of killed registers on the store. Mark the defs
1242 // as dead since the store has been deleted and they aren't
1243 // being reused.
1244 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
1245 bool HasOtherDef = false;
1246 if (InvalidateRegDef(PrevMII, MI, KillRegs[j], HasOtherDef)) {
1247 MachineInstr *DeadDef = PrevMII;
1248 if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
1249 // FIXME: This assumes a remat def does not have side
1250 // effects.
1251 MBB.erase(DeadDef);
1252 VRM.RemoveFromFoldedVirtMap(DeadDef);
1253 ++NumDRM;
1254 }
1255 }
1256 }
1257 }
Evan Chengf50d09a2007-02-08 06:04:54 +00001258 }
Evan Chengb6ca4b32007-08-14 23:25:37 +00001259 LastStore = next(MII);
1260
1261 // If the stack slot value was previously available in some other
1262 // register, change it now. Otherwise, make the register available,
1263 // in PhysReg.
1264 Spills.ModifyStackSlotOrReMat(StackSlot);
1265 Spills.ClobberPhysReg(PhysReg);
1266 Spills.addAvailable(StackSlot, LastStore, PhysReg);
1267 ++NumStores;
1268
1269 // Check to see if this is a noop copy. If so, eliminate the
1270 // instruction before considering the dest reg to be changed.
1271 {
1272 unsigned Src, Dst;
1273 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1274 ++NumDCE;
1275 DOUT << "Removing now-noop copy: " << MI;
1276 MBB.erase(&MI);
1277 Erased = true;
1278 VRM.RemoveFromFoldedVirtMap(&MI);
1279 UpdateKills(*LastStore, RegKills, KillOps);
1280 goto ProcessNextInst;
1281 }
1282 }
1283 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001284 }
1285 }
Chris Lattnercea86882005-09-19 06:56:21 +00001286 ProcessNextInst:
Evan Cheng0c40d722007-07-11 05:28:39 +00001287 if (!Erased && !BackTracked)
1288 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
1289 UpdateKills(*II, RegKills, KillOps);
Chris Lattner7fb64342004-10-01 19:04:51 +00001290 MII = NextMII;
1291 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001292}
1293
Chris Lattnerf7da2c72006-08-24 22:43:55 +00001294
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001295llvm::Spiller* llvm::createSpiller() {
1296 switch (SpillerOpt) {
1297 default: assert(0 && "Unreachable!");
1298 case local:
1299 return new LocalSpiller();
1300 case simple:
1301 return new SimpleSpiller();
1302 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001303}