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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
38STATISTIC(NumStores, "Number of stores added");
39STATISTIC(NumLoads , "Number of loads added");
40STATISTIC(NumReused, "Number of values reused");
41STATISTIC(NumDSE , "Number of dead stores elided");
42STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000043
Chris Lattnercd3245a2006-12-19 22:41:21 +000044namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000045 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000046
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000047 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000048 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000049 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000050 cl::Prefix,
51 cl::values(clEnumVal(simple, " simple spiller"),
52 clEnumVal(local, " local spiller"),
53 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000054 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000055}
56
Chris Lattner8c4d88d2004-09-30 01:54:45 +000057//===----------------------------------------------------------------------===//
58// VirtRegMap implementation
59//===----------------------------------------------------------------------===//
60
Chris Lattner29268692006-09-05 02:12:02 +000061VirtRegMap::VirtRegMap(MachineFunction &mf)
62 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
63 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) {
64 grow();
65}
66
Chris Lattner8c4d88d2004-09-30 01:54:45 +000067void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000068 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
69 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000070}
71
Chris Lattner8c4d88d2004-09-30 01:54:45 +000072int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
73 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000074 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000075 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000076 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
77 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
78 RC->getAlignment());
79 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000080 ++NumSpills;
81 return frameIndex;
82}
83
84void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
85 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000086 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000087 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000088 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000089}
90
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000091void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +000092 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000093 // Move previous memory references folded to new instruction.
94 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +000095 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000096 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
97 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +000098 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +000099 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000100
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000101 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000102 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
103 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000104 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000105 // Folded a two-address operand.
106 MRInfo = isModRef;
107 } else if (OldMI->getOperand(OpNo).isDef()) {
108 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000109 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000110 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000111 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000112
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000113 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000114 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000115}
116
Chris Lattner7f690e62004-09-30 02:15:18 +0000117void VirtRegMap::print(std::ostream &OS) const {
118 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000119
Chris Lattner7f690e62004-09-30 02:15:18 +0000120 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000121 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000122 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
123 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
124 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000125
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000126 }
127
128 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000129 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
130 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
131 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
132 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000133}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000134
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000135void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000136 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000137}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000138
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000139
140//===----------------------------------------------------------------------===//
141// Simple Spiller Implementation
142//===----------------------------------------------------------------------===//
143
144Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000145
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000146namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000147 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000148 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000149 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000150}
151
Chris Lattner35f27052006-05-01 21:16:03 +0000152bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000153 DOUT << "********** REWRITE MACHINE CODE **********\n";
154 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000155 const TargetMachine &TM = MF.getTarget();
156 const MRegisterInfo &MRI = *TM.getRegisterInfo();
157 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000158
Chris Lattner4ea1b822004-09-30 02:33:48 +0000159 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
160 // each vreg once (in the case where a spilled vreg is used by multiple
161 // operands). This is always smaller than the number of operands to the
162 // current machine instr, so it should be small.
163 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000164
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000165 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
166 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000167 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000168 MachineBasicBlock &MBB = *MBBI;
169 for (MachineBasicBlock::iterator MII = MBB.begin(),
170 E = MBB.end(); MII != E; ++MII) {
171 MachineInstr &MI = *MII;
172 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000173 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000174 if (MO.isRegister() && MO.getReg())
175 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
176 unsigned VirtReg = MO.getReg();
177 unsigned PhysReg = VRM.getPhys(VirtReg);
178 if (VRM.hasStackSlot(VirtReg)) {
179 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000180 const TargetRegisterClass* RC =
181 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000182
Chris Lattner886dd912005-04-04 21:35:34 +0000183 if (MO.isUse() &&
184 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
185 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000186 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000187 LoadedRegs.push_back(VirtReg);
188 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000189 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000190 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000191
Chris Lattner886dd912005-04-04 21:35:34 +0000192 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000193 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000194 ++NumStores;
195 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000196 }
Chris Lattner886dd912005-04-04 21:35:34 +0000197 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000198 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000199 } else {
200 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000201 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000202 }
Chris Lattner886dd912005-04-04 21:35:34 +0000203
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000204 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000205 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000206 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000207 }
208 return true;
209}
210
211//===----------------------------------------------------------------------===//
212// Local Spiller Implementation
213//===----------------------------------------------------------------------===//
214
215namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000216 /// LocalSpiller - This spiller does a simple pass over the machine basic
217 /// block to attempt to keep spills in registers as much as possible for
218 /// blocks that have low register pressure (the vreg may be spilled due to
219 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000220 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000221 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000222 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000223 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000224 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000225 MRI = MF.getTarget().getRegisterInfo();
226 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000227 DOUT << "\n**** Local spiller rewriting function '"
228 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000229
Chris Lattner7fb64342004-10-01 19:04:51 +0000230 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
231 MBB != E; ++MBB)
232 RewriteMBB(*MBB, VRM);
233 return true;
234 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000235 private:
Chris Lattner35f27052006-05-01 21:16:03 +0000236 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000237 };
238}
239
Chris Lattner66cf80f2006-02-03 23:13:58 +0000240/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
241/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000242///
243/// Note that not all physregs are created equal here. In particular, some
244/// physregs are reloads that we are allowed to clobber or ignore at any time.
245/// Other physregs are values that the register allocated program is using that
246/// we cannot CHANGE, but we can read if we like. We keep track of this on a
247/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
248/// entries. The predicate 'canClobberPhysReg()' checks this bit and
249/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000250namespace {
251class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000252 const MRegisterInfo *MRI;
253 const TargetInstrInfo *TII;
254
255 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
256 // register values that are still available, due to being loaded or stored to,
257 // but not invalidated yet.
258 std::map<int, unsigned> SpillSlotsAvailable;
259
260 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
261 // which stack slot values are currently held by a physreg. This is used to
262 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
263 std::multimap<unsigned, int> PhysRegsAvailable;
264
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000265 void disallowClobberPhysRegOnly(unsigned PhysReg);
266
Chris Lattner66cf80f2006-02-03 23:13:58 +0000267 void ClobberPhysRegOnly(unsigned PhysReg);
268public:
269 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
270 : MRI(mri), TII(tii) {
271 }
272
273 /// getSpillSlotPhysReg - If the specified stack slot is available in a
274 /// physical register, return that PhysReg, otherwise return 0.
275 unsigned getSpillSlotPhysReg(int Slot) const {
276 std::map<int, unsigned>::const_iterator I = SpillSlotsAvailable.find(Slot);
277 if (I != SpillSlotsAvailable.end())
Chris Lattner593c9582006-02-03 23:28:46 +0000278 return I->second >> 1; // Remove the CanClobber bit.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000279 return 0;
280 }
Chris Lattner540fec62006-02-25 01:51:33 +0000281
282 const MRegisterInfo *getRegInfo() const { return MRI; }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000283
284 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000285 /// specified physreg. If CanClobber is true, the physreg can be modified at
286 /// any time without changing the semantics of the program.
287 void addAvailable(int Slot, unsigned Reg, bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000288 // If this stack slot is thought to be available in some other physreg,
289 // remove its record.
290 ModifyStackSlot(Slot);
291
Chris Lattner66cf80f2006-02-03 23:13:58 +0000292 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Jeff Cohen003cecb2006-02-04 03:27:39 +0000293 SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000294
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000295 DOUT << "Remembering SS#" << Slot << " in physreg "
296 << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000297 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000298
Chris Lattner593c9582006-02-03 23:28:46 +0000299 /// canClobberPhysReg - Return true if the spiller is allowed to change the
300 /// value of the specified stackslot register if it desires. The specified
301 /// stack slot must be available in a physreg for this query to make sense.
302 bool canClobberPhysReg(int Slot) const {
303 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
304 return SpillSlotsAvailable.find(Slot)->second & 1;
305 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000306
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000307 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
308 /// stackslot register. The register is still available but is no longer
309 /// allowed to be modifed.
310 void disallowClobberPhysReg(unsigned PhysReg);
311
Chris Lattner66cf80f2006-02-03 23:13:58 +0000312 /// ClobberPhysReg - This is called when the specified physreg changes
313 /// value. We use this to invalidate any info about stuff we thing lives in
314 /// it and any of its aliases.
315 void ClobberPhysReg(unsigned PhysReg);
316
317 /// ModifyStackSlot - This method is called when the value in a stack slot
318 /// changes. This removes information about which register the previous value
319 /// for this slot lives in (as the previous value is dead now).
320 void ModifyStackSlot(int Slot);
321};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000322}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000323
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000324/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
325/// stackslot register. The register is still available but is no longer
326/// allowed to be modifed.
327void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
328 std::multimap<unsigned, int>::iterator I =
329 PhysRegsAvailable.lower_bound(PhysReg);
330 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
331 int Slot = I->second;
332 I++;
333 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
334 "Bidirectional map mismatch!");
335 SpillSlotsAvailable[Slot] &= ~1;
336 DOUT << "PhysReg " << MRI->getName(PhysReg)
337 << " copied, it is available for use but can no longer be modified\n";
338 }
339}
340
341/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
342/// stackslot register and its aliases. The register and its aliases may
343/// still available but is no longer allowed to be modifed.
344void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
345 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
346 disallowClobberPhysRegOnly(*AS);
347 disallowClobberPhysRegOnly(PhysReg);
348}
349
Chris Lattner66cf80f2006-02-03 23:13:58 +0000350/// ClobberPhysRegOnly - This is called when the specified physreg changes
351/// value. We use this to invalidate any info about stuff we thing lives in it.
352void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
353 std::multimap<unsigned, int>::iterator I =
354 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000355 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000356 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000357 PhysRegsAvailable.erase(I++);
Chris Lattner593c9582006-02-03 23:28:46 +0000358 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000359 "Bidirectional map mismatch!");
360 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000361 DOUT << "PhysReg " << MRI->getName(PhysReg)
362 << " clobbered, invalidating SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000363 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000364}
365
Chris Lattner66cf80f2006-02-03 23:13:58 +0000366/// ClobberPhysReg - This is called when the specified physreg changes
367/// value. We use this to invalidate any info about stuff we thing lives in
368/// it and any of its aliases.
369void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000370 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000371 ClobberPhysRegOnly(*AS);
372 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000373}
374
Chris Lattner07cf1412006-02-03 00:36:31 +0000375/// ModifyStackSlot - This method is called when the value in a stack slot
376/// changes. This removes information about which register the previous value
377/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000378void AvailableSpills::ModifyStackSlot(int Slot) {
379 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(Slot);
380 if (It == SpillSlotsAvailable.end()) return;
Chris Lattner593c9582006-02-03 23:28:46 +0000381 unsigned Reg = It->second >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000382 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000383
384 // This register may hold the value of multiple stack slots, only remove this
385 // stack slot from the set of values the register contains.
386 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
387 for (; ; ++I) {
388 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
389 "Map inverse broken!");
390 if (I->second == Slot) break;
391 }
392 PhysRegsAvailable.erase(I);
393}
394
395
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000396
Chris Lattner7fb64342004-10-01 19:04:51 +0000397// ReusedOp - For each reused operand, we keep track of a bit of information, in
398// case we need to rollback upon processing a new operand. See comments below.
399namespace {
400 struct ReusedOp {
401 // The MachineInstr operand that reused an available value.
402 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000403
Chris Lattner7fb64342004-10-01 19:04:51 +0000404 // StackSlot - The spill slot of the value being reused.
405 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000406
Chris Lattner7fb64342004-10-01 19:04:51 +0000407 // PhysRegReused - The physical register the value was available in.
408 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000409
Chris Lattner7fb64342004-10-01 19:04:51 +0000410 // AssignedPhysReg - The physreg that was assigned for use by the reload.
411 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000412
413 // VirtReg - The virtual register itself.
414 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000415
Chris Lattner8a61a752005-10-06 17:19:06 +0000416 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
417 unsigned vreg)
418 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
419 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000420 };
Chris Lattner540fec62006-02-25 01:51:33 +0000421
422 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
423 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000424 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000425 MachineInstr &MI;
426 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000427 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000428 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000429 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000430 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000431 }
Chris Lattner540fec62006-02-25 01:51:33 +0000432
433 bool hasReuses() const {
434 return !Reuses.empty();
435 }
436
437 /// addReuse - If we choose to reuse a virtual register that is already
438 /// available instead of reloading it, remember that we did so.
439 void addReuse(unsigned OpNo, unsigned StackSlot,
440 unsigned PhysRegReused, unsigned AssignedPhysReg,
441 unsigned VirtReg) {
442 // If the reload is to the assigned register anyway, no undo will be
443 // required.
444 if (PhysRegReused == AssignedPhysReg) return;
445
446 // Otherwise, remember this.
447 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
448 AssignedPhysReg, VirtReg));
449 }
Evan Chenge077ef62006-11-04 00:21:55 +0000450
451 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000452 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000453 }
454
455 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000456 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000457 }
Chris Lattner540fec62006-02-25 01:51:33 +0000458
459 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
460 /// is some other operand that is using the specified register, either pick
461 /// a new register to use, or evict the previous reload and use this reg.
462 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
463 AvailableSpills &Spills,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000464 std::map<int, MachineInstr*> &MaybeDeadStores,
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000465 SmallSet<unsigned, 8> &Rejected) {
Chris Lattner540fec62006-02-25 01:51:33 +0000466 if (Reuses.empty()) return PhysReg; // This is most often empty.
467
468 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
469 ReusedOp &Op = Reuses[ro];
470 // If we find some other reuse that was supposed to use this register
471 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000472 // register. That is, unless its reload register has already been
473 // considered and subsequently rejected because it has also been reused
474 // by another operand.
475 if (Op.PhysRegReused == PhysReg &&
476 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000477 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000478 unsigned NewReg = Op.AssignedPhysReg;
479 Rejected.insert(PhysReg);
480 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner540fec62006-02-25 01:51:33 +0000481 } else {
482 // Otherwise, we might also have a problem if a previously reused
483 // value aliases the new register. If so, codegen the previous reload
484 // and use this one.
485 unsigned PRRU = Op.PhysRegReused;
486 const MRegisterInfo *MRI = Spills.getRegInfo();
487 if (MRI->areAliases(PRRU, PhysReg)) {
488 // Okay, we found out that an alias of a reused register
489 // was used. This isn't good because it means we have
490 // to undo a previous reuse.
491 MachineBasicBlock *MBB = MI->getParent();
492 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000493 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
494
495 // Copy Op out of the vector and remove it, we're going to insert an
496 // explicit load for it.
497 ReusedOp NewOp = Op;
498 Reuses.erase(Reuses.begin()+ro);
499
500 // Ok, we're going to try to reload the assigned physreg into the
501 // slot that we were supposed to in the first place. However, that
502 // register could hold a reuse. Check to see if it conflicts or
503 // would prefer us to use a different register.
504 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000505 MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner28bad082006-02-25 02:17:31 +0000506
507 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
508 NewOp.StackSlot, AliasRC);
509 Spills.ClobberPhysReg(NewPhysReg);
510 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000511
512 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000513 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000514
Chris Lattnere53f4a02006-05-04 17:52:23 +0000515 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000516
Chris Lattner28bad082006-02-25 02:17:31 +0000517 Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000518 ++NumLoads;
519 DEBUG(MachineBasicBlock::iterator MII = MI;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000520 DOUT << '\t' << *prior(MII));
Chris Lattner540fec62006-02-25 01:51:33 +0000521
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000522 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000523 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000524
525 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000526 return PhysReg;
527 }
528 }
529 }
530 return PhysReg;
531 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000532
533 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
534 /// 'Rejected' set to remember which registers have been considered and
535 /// rejected for the reload. This avoids infinite looping in case like
536 /// this:
537 /// t1 := op t2, t3
538 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
539 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
540 /// t1 <- desires r1
541 /// sees r1 is taken by t2, tries t2's reload register r0
542 /// sees r0 is taken by t3, tries t3's reload register r1
543 /// sees r1 is taken by t2, tries t2's reload register r0 ...
544 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
545 AvailableSpills &Spills,
546 std::map<int, MachineInstr*> &MaybeDeadStores) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000547 SmallSet<unsigned, 8> Rejected;
Evan Cheng3c82cab2007-01-19 22:40:14 +0000548 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected);
549 }
Chris Lattner540fec62006-02-25 01:51:33 +0000550 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000551}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000552
Chris Lattner7fb64342004-10-01 19:04:51 +0000553
554/// rewriteMBB - Keep track of which spills are available even after the
555/// register allocator is done with them. If possible, avoid reloading vregs.
Chris Lattner35f27052006-05-01 21:16:03 +0000556void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000557
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000558 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000559
Chris Lattner66cf80f2006-02-03 23:13:58 +0000560 // Spills - Keep track of which spilled values are available in physregs so
561 // that we can choose to reuse the physregs instead of emitting reloads.
562 AvailableSpills Spills(MRI, TII);
563
Chris Lattner52b25db2004-10-01 19:47:12 +0000564 // MaybeDeadStores - When we need to write a value back into a stack slot,
565 // keep track of the inserted store. If the stack slot value is never read
566 // (because the value was used from some available register, for example), and
567 // subsequently stored to, the original store is dead. This map keeps track
568 // of inserted stores that are not used. If we see a subsequent store to the
569 // same stack slot, the original store is deleted.
570 std::map<int, MachineInstr*> MaybeDeadStores;
571
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000572 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
573
Chris Lattner7fb64342004-10-01 19:04:51 +0000574 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
575 MII != E; ) {
576 MachineInstr &MI = *MII;
577 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
578
Chris Lattner540fec62006-02-25 01:51:33 +0000579 /// ReusedOperands - Keep track of operand reuse in case we need to undo
580 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000581 ReuseInfo ReusedOperands(MI, MRI);
582
583 // Loop over all of the implicit defs, clearing them from our available
584 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000585 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
586 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000587 if (ImpDef) {
588 for ( ; *ImpDef; ++ImpDef) {
589 PhysRegsUsed[*ImpDef] = true;
590 ReusedOperands.markClobbered(*ImpDef);
591 Spills.ClobberPhysReg(*ImpDef);
592 }
593 }
594
Chris Lattner7fb64342004-10-01 19:04:51 +0000595 // Process all of the spilled uses and all non spilled reg references.
596 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
597 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000598 if (!MO.isRegister() || MO.getReg() == 0)
599 continue; // Ignore non-register operands.
600
601 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
602 // Ignore physregs for spilling, but remember that it is used by this
603 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000604 PhysRegsUsed[MO.getReg()] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000605 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000606 continue;
607 }
608
609 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
610 "Not a virtual or a physical register?");
611
612 unsigned VirtReg = MO.getReg();
613 if (!VRM.hasStackSlot(VirtReg)) {
614 // This virtual register was assigned a physreg!
615 unsigned Phys = VRM.getPhys(VirtReg);
616 PhysRegsUsed[Phys] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000617 if (MO.isDef())
618 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000619 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000620 continue;
621 }
622
623 // This virtual register is now known to be a spilled value.
624 if (!MO.isUse())
625 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000626
Chris Lattner50ea01e2005-09-09 20:29:51 +0000627 int StackSlot = VRM.getStackSlot(VirtReg);
628 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000629
Chris Lattner50ea01e2005-09-09 20:29:51 +0000630 // Check to see if this stack slot is available.
Chris Lattneraddc55a2006-04-28 01:46:50 +0000631 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000632
Chris Lattner29268692006-09-05 02:12:02 +0000633 // This spilled operand might be part of a two-address operand. If this
634 // is the case, then changing it will necessarily require changing the
635 // def part of the instruction as well. However, in some cases, we
636 // aren't allowed to modify the reused register. If none of these cases
637 // apply, reuse it.
638 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000639 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000640 if (ti != -1 &&
641 MI.getOperand(ti).isReg() &&
642 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000643 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000644 // long as we are allowed to clobber the value and there isn't an
645 // earlier def that has already clobbered the physreg.
Evan Chenge077ef62006-11-04 00:21:55 +0000646 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
647 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000648 }
649
650 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000651 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000652 DOUT << "Reusing SS#" << StackSlot << " from physreg "
653 << MRI->getName(PhysReg) << " for vreg"
654 << VirtReg <<" instead of reloading into physreg "
655 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000656 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000657
658 // The only technical detail we have is that we don't know that
659 // PhysReg won't be clobbered by a reloaded stack slot that occurs
660 // later in the instruction. In particular, consider 'op V1, V2'.
661 // If V1 is available in physreg R0, we would choose to reuse it
662 // here, instead of reloading it into the register the allocator
663 // indicated (say R1). However, V2 might have to be reloaded
664 // later, and it might indicate that it needs to live in R0. When
665 // this occurs, we need to have information available that
666 // indicates it is safe to use R1 for the reload instead of R0.
667 //
668 // To further complicate matters, we might conflict with an alias,
669 // or R0 and R1 might not be compatible with each other. In this
670 // case, we actually insert a reload for V1 in R1, ensuring that
671 // we can get at R0 or its alias.
672 ReusedOperands.addReuse(i, StackSlot, PhysReg,
673 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000674 if (ti != -1)
675 // Only mark it clobbered if this is a use&def operand.
676 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000677 ++NumReused;
678 continue;
679 }
680
681 // Otherwise we have a situation where we have a two-address instruction
682 // whose mod/ref operand needs to be reloaded. This reload is already
683 // available in some register "PhysReg", but if we used PhysReg as the
684 // operand to our 2-addr instruction, the instruction would modify
685 // PhysReg. This isn't cool if something later uses PhysReg and expects
686 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000687 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000688 // To avoid this problem, and to avoid doing a load right after a store,
689 // we emit a copy from PhysReg into the designated register for this
690 // operand.
691 unsigned DesignatedReg = VRM.getPhys(VirtReg);
692 assert(DesignatedReg && "Must map virtreg to physreg!");
693
694 // Note that, if we reused a register for a previous operand, the
695 // register we want to reload into might not actually be
696 // available. If this occurs, use the register indicated by the
697 // reuser.
698 if (ReusedOperands.hasReuses())
699 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
700 Spills, MaybeDeadStores);
701
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000702 // If the mapped designated register is actually the physreg we have
703 // incoming, we don't need to inserted a dead copy.
704 if (DesignatedReg == PhysReg) {
705 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000706 DOUT << "Reusing SS#" << StackSlot << " from physreg "
707 << MRI->getName(PhysReg) << " for vreg"
708 << VirtReg
709 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000710 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000711 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000712 ++NumReused;
713 continue;
714 }
715
Chris Lattneraddc55a2006-04-28 01:46:50 +0000716 const TargetRegisterClass* RC =
717 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
718
719 PhysRegsUsed[DesignatedReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000720 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000721 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
722
723 // This invalidates DesignatedReg.
724 Spills.ClobberPhysReg(DesignatedReg);
725
726 Spills.addAvailable(StackSlot, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000727 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000728 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000729 ++NumReused;
730 continue;
731 }
732
733 // Otherwise, reload it and remember that we have it.
734 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000735 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000736 const TargetRegisterClass* RC =
737 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000738
Chris Lattner50ea01e2005-09-09 20:29:51 +0000739 // Note that, if we reused a register for a previous operand, the
740 // register we want to reload into might not actually be
741 // available. If this occurs, use the register indicated by the
742 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000743 if (ReusedOperands.hasReuses())
744 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
745 Spills, MaybeDeadStores);
746
Chris Lattner50ea01e2005-09-09 20:29:51 +0000747 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000748 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000749 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000750 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000751 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000752
753 // Any stores to this stack slot are not dead anymore.
754 MaybeDeadStores.erase(StackSlot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000755 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000756 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000757 MI.getOperand(i).setReg(PhysReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000758 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000759 }
760
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000761 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000762
Chris Lattner7fb64342004-10-01 19:04:51 +0000763 // If we have folded references to memory operands, make sure we clear all
764 // physical registers that may contain the value of the spilled virtual
765 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000766 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
767 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000768 DOUT << "Folded vreg: " << I->second.first << " MR: "
769 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000770 unsigned VirtReg = I->second.first;
771 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000772 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000773 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000774 continue;
775 }
776 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000777 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000778
779 // If this folded instruction is just a use, check to see if it's a
780 // straight load from the virt reg slot.
781 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
782 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000783 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000784 if (FrameIdx == SS) {
785 // If this spill slot is available, turn it into a copy (or nothing)
786 // instead of leaving it as a load!
787 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000788 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000789 MachineFunction &MF = *MBB.getParent();
790 if (DestReg != InReg) {
791 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
792 MF.getSSARegMap()->getRegClass(VirtReg));
793 // Revisit the copy so we make sure to notice the effects of the
794 // operation on the destreg (either needing to RA it if it's
795 // virtual or needing to clobber any values if it's physical).
796 NextMII = &MI;
797 --NextMII; // backtrack to the copy.
798 }
799 VRM.RemoveFromFoldedVirtMap(&MI);
800 MBB.erase(&MI);
801 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000802 }
Chris Lattnercea86882005-09-19 06:56:21 +0000803 }
804 }
805 }
806
807 // If this reference is not a use, any previous store is now dead.
808 // Otherwise, the store to this stack slot is not dead anymore.
809 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
810 if (MDSI != MaybeDeadStores.end()) {
811 if (MR & VirtRegMap::isRef) // Previous store is not dead.
812 MaybeDeadStores.erase(MDSI);
813 else {
814 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000815 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000816 DOUT << "Removed dead store:\t" << *MDSI->second;
Chris Lattner35f27052006-05-01 21:16:03 +0000817 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000818 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000819 MaybeDeadStores.erase(MDSI);
820 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000821 }
822 }
823
824 // If the spill slot value is available, and this is a new definition of
825 // the value, the value is not available anymore.
826 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000827 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000828 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000829
830 // If this is *just* a mod of the value, check to see if this is just a
831 // store to the spill slot (i.e. the spill got merged into the copy). If
832 // so, realize that the vreg is available now, and add the store to the
833 // MaybeDeadStore info.
834 int StackSlot;
835 if (!(MR & VirtRegMap::isRef)) {
836 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
837 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
838 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000839 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000840 // this as a potentially dead store in case there is a subsequent
841 // store into the stack slot without a read from it.
842 MaybeDeadStores[StackSlot] = &MI;
843
Chris Lattnercd816392006-02-02 23:29:36 +0000844 // If the stack slot value was previously available in some other
845 // register, change it now. Otherwise, make the register available,
846 // in PhysReg.
Chris Lattner593c9582006-02-03 23:28:46 +0000847 Spills.addAvailable(StackSlot, SrcReg, false /*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +0000848 }
849 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000850 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000851 }
852
Chris Lattner7fb64342004-10-01 19:04:51 +0000853 // Process all of the spilled defs.
854 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
855 MachineOperand &MO = MI.getOperand(i);
856 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
857 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000858
Chris Lattner7fb64342004-10-01 19:04:51 +0000859 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +0000860 // Check to see if this is a noop copy. If so, eliminate the
861 // instruction before considering the dest reg to be changed.
862 unsigned Src, Dst;
863 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
864 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000865 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +0000866 MBB.erase(&MI);
867 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000868 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +0000869 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +0000870 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000871
872 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +0000873 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000874 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +0000875
876 // Check to see if this instruction is a load from a stack slot into
877 // a register. If so, this provides the stack slot value in the reg.
878 int FrameIdx;
879 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
880 assert(DestReg == VirtReg && "Unknown load situation!");
881
882 // Otherwise, if it wasn't available, remember that it is now!
883 Spills.addAvailable(FrameIdx, DestReg);
884 goto ProcessNextInst;
885 }
886
Chris Lattner29268692006-09-05 02:12:02 +0000887 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000888 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000889
Chris Lattner84e752a2006-02-03 03:06:49 +0000890 // The only vregs left are stack slot definitions.
891 int StackSlot = VRM.getStackSlot(VirtReg);
892 const TargetRegisterClass *RC =
893 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000894
Chris Lattner29268692006-09-05 02:12:02 +0000895 // If this def is part of a two-address operand, make sure to execute
896 // the store from the correct physical register.
897 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +0000898 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000899 if (TiedOp != -1)
900 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +0000901 else {
Chris Lattner29268692006-09-05 02:12:02 +0000902 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000903 if (ReusedOperands.isClobbered(PhysReg)) {
904 // Another def has taken the assigned physreg. It must have been a
905 // use&def which got it due to reuse. Undo the reuse!
906 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
907 Spills, MaybeDeadStores);
908 }
909 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000910
Chris Lattner84e752a2006-02-03 03:06:49 +0000911 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000912 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000913 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000914 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000915 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000916
Chris Lattner84e752a2006-02-03 03:06:49 +0000917 // If there is a dead store to this stack slot, nuke it now.
918 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
919 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000920 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +0000921 ++NumDSE;
922 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +0000923 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +0000924 }
Chris Lattner84e752a2006-02-03 03:06:49 +0000925 LastStore = next(MII);
926
927 // If the stack slot value was previously available in some other
928 // register, change it now. Otherwise, make the register available,
929 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000930 Spills.ModifyStackSlot(StackSlot);
931 Spills.ClobberPhysReg(PhysReg);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000932 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000933 ++NumStores;
Evan Chengf50d09a2007-02-08 06:04:54 +0000934
935 // Check to see if this is a noop copy. If so, eliminate the
936 // instruction before considering the dest reg to be changed.
937 {
938 unsigned Src, Dst;
939 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
940 ++NumDCE;
941 DOUT << "Removing now-noop copy: " << MI;
942 MBB.erase(&MI);
943 VRM.RemoveFromFoldedVirtMap(&MI);
944 goto ProcessNextInst;
945 }
946 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000947 }
948 }
Chris Lattnercea86882005-09-19 06:56:21 +0000949 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +0000950 MII = NextMII;
951 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000952}
953
Chris Lattnerf7da2c72006-08-24 22:43:55 +0000954
955
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000956llvm::Spiller* llvm::createSpiller() {
957 switch (SpillerOpt) {
958 default: assert(0 && "Unreachable!");
959 case local:
960 return new LocalSpiller();
961 case simple:
962 return new SimpleSpiller();
963 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000964}