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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000030#include "llvm/ADT/Statistic.h"
31#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000032#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000033#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000034using namespace llvm;
35
Chris Lattnercd3245a2006-12-19 22:41:21 +000036STATISTIC(NumSpills, "Number of register spills");
37STATISTIC(NumStores, "Number of stores added");
38STATISTIC(NumLoads , "Number of loads added");
39STATISTIC(NumReused, "Number of values reused");
40STATISTIC(NumDSE , "Number of dead stores elided");
41STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000042
Chris Lattnercd3245a2006-12-19 22:41:21 +000043namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000044 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000045
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000046 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000047 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000048 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000049 cl::Prefix,
50 cl::values(clEnumVal(simple, " simple spiller"),
51 clEnumVal(local, " local spiller"),
52 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000053 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000054}
55
Chris Lattner8c4d88d2004-09-30 01:54:45 +000056//===----------------------------------------------------------------------===//
57// VirtRegMap implementation
58//===----------------------------------------------------------------------===//
59
Chris Lattner29268692006-09-05 02:12:02 +000060VirtRegMap::VirtRegMap(MachineFunction &mf)
61 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
62 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) {
63 grow();
64}
65
Chris Lattner8c4d88d2004-09-30 01:54:45 +000066void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000067 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
68 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000069}
70
Chris Lattner8c4d88d2004-09-30 01:54:45 +000071int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
72 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000073 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000074 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000075 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
76 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
77 RC->getAlignment());
78 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000079 ++NumSpills;
80 return frameIndex;
81}
82
83void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
84 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000085 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000086 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000087 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000088}
89
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000090void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +000091 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000092 // Move previous memory references folded to new instruction.
93 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +000094 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000095 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
96 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +000097 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +000098 }
Chris Lattnerdbea9732004-09-30 16:35:08 +000099
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000100 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000101 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
102 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000103 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000104 // Folded a two-address operand.
105 MRInfo = isModRef;
106 } else if (OldMI->getOperand(OpNo).isDef()) {
107 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000108 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000109 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000110 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000111
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000112 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000113 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000114}
115
Chris Lattner7f690e62004-09-30 02:15:18 +0000116void VirtRegMap::print(std::ostream &OS) const {
117 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000118
Chris Lattner7f690e62004-09-30 02:15:18 +0000119 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000120 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000121 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
122 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
123 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000124
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000125 }
126
127 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000128 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
129 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
130 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
131 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000132}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000133
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000134void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000135 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000136}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000137
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000138
139//===----------------------------------------------------------------------===//
140// Simple Spiller Implementation
141//===----------------------------------------------------------------------===//
142
143Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000144
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000145namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000146 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000147 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000148 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000149}
150
Chris Lattner35f27052006-05-01 21:16:03 +0000151bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000152 DOUT << "********** REWRITE MACHINE CODE **********\n";
153 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000154 const TargetMachine &TM = MF.getTarget();
155 const MRegisterInfo &MRI = *TM.getRegisterInfo();
156 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000157
Chris Lattner4ea1b822004-09-30 02:33:48 +0000158 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
159 // each vreg once (in the case where a spilled vreg is used by multiple
160 // operands). This is always smaller than the number of operands to the
161 // current machine instr, so it should be small.
162 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000163
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000164 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
165 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000166 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000167 MachineBasicBlock &MBB = *MBBI;
168 for (MachineBasicBlock::iterator MII = MBB.begin(),
169 E = MBB.end(); MII != E; ++MII) {
170 MachineInstr &MI = *MII;
171 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000172 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000173 if (MO.isRegister() && MO.getReg())
174 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
175 unsigned VirtReg = MO.getReg();
176 unsigned PhysReg = VRM.getPhys(VirtReg);
177 if (VRM.hasStackSlot(VirtReg)) {
178 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000179 const TargetRegisterClass* RC =
180 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000181
Chris Lattner886dd912005-04-04 21:35:34 +0000182 if (MO.isUse() &&
183 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
184 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000185 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000186 LoadedRegs.push_back(VirtReg);
187 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000188 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000189 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000190
Chris Lattner886dd912005-04-04 21:35:34 +0000191 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000192 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000193 ++NumStores;
194 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000195 }
Chris Lattner886dd912005-04-04 21:35:34 +0000196 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000197 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000198 } else {
199 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000200 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000201 }
Chris Lattner886dd912005-04-04 21:35:34 +0000202
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000203 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000204 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000205 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000206 }
207 return true;
208}
209
210//===----------------------------------------------------------------------===//
211// Local Spiller Implementation
212//===----------------------------------------------------------------------===//
213
214namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000215 /// LocalSpiller - This spiller does a simple pass over the machine basic
216 /// block to attempt to keep spills in registers as much as possible for
217 /// blocks that have low register pressure (the vreg may be spilled due to
218 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000219 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000220 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000221 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000222 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000223 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000224 MRI = MF.getTarget().getRegisterInfo();
225 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000226 DOUT << "\n**** Local spiller rewriting function '"
227 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000228
Chris Lattner7fb64342004-10-01 19:04:51 +0000229 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
230 MBB != E; ++MBB)
231 RewriteMBB(*MBB, VRM);
232 return true;
233 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000234 private:
Chris Lattner35f27052006-05-01 21:16:03 +0000235 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner7fb64342004-10-01 19:04:51 +0000236 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000237 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner7fb64342004-10-01 19:04:51 +0000238 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000239 std::multimap<unsigned, int> &PhysRegs);
240 void ModifyStackSlot(int Slot, std::map<int, unsigned> &SpillSlots,
241 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000242 };
243}
244
Chris Lattner66cf80f2006-02-03 23:13:58 +0000245/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
246/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000247///
248/// Note that not all physregs are created equal here. In particular, some
249/// physregs are reloads that we are allowed to clobber or ignore at any time.
250/// Other physregs are values that the register allocated program is using that
251/// we cannot CHANGE, but we can read if we like. We keep track of this on a
252/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
253/// entries. The predicate 'canClobberPhysReg()' checks this bit and
254/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000255namespace {
256class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000257 const MRegisterInfo *MRI;
258 const TargetInstrInfo *TII;
259
260 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
261 // register values that are still available, due to being loaded or stored to,
262 // but not invalidated yet.
263 std::map<int, unsigned> SpillSlotsAvailable;
264
265 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
266 // which stack slot values are currently held by a physreg. This is used to
267 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
268 std::multimap<unsigned, int> PhysRegsAvailable;
269
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000270 void disallowClobberPhysRegOnly(unsigned PhysReg);
271
Chris Lattner66cf80f2006-02-03 23:13:58 +0000272 void ClobberPhysRegOnly(unsigned PhysReg);
273public:
274 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
275 : MRI(mri), TII(tii) {
276 }
277
278 /// getSpillSlotPhysReg - If the specified stack slot is available in a
279 /// physical register, return that PhysReg, otherwise return 0.
280 unsigned getSpillSlotPhysReg(int Slot) const {
281 std::map<int, unsigned>::const_iterator I = SpillSlotsAvailable.find(Slot);
282 if (I != SpillSlotsAvailable.end())
Chris Lattner593c9582006-02-03 23:28:46 +0000283 return I->second >> 1; // Remove the CanClobber bit.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000284 return 0;
285 }
Chris Lattner540fec62006-02-25 01:51:33 +0000286
287 const MRegisterInfo *getRegInfo() const { return MRI; }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000288
289 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000290 /// specified physreg. If CanClobber is true, the physreg can be modified at
291 /// any time without changing the semantics of the program.
292 void addAvailable(int Slot, unsigned Reg, bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000293 // If this stack slot is thought to be available in some other physreg,
294 // remove its record.
295 ModifyStackSlot(Slot);
296
Chris Lattner66cf80f2006-02-03 23:13:58 +0000297 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Jeff Cohen003cecb2006-02-04 03:27:39 +0000298 SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000299
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000300 DOUT << "Remembering SS#" << Slot << " in physreg "
301 << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000302 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000303
Chris Lattner593c9582006-02-03 23:28:46 +0000304 /// canClobberPhysReg - Return true if the spiller is allowed to change the
305 /// value of the specified stackslot register if it desires. The specified
306 /// stack slot must be available in a physreg for this query to make sense.
307 bool canClobberPhysReg(int Slot) const {
308 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
309 return SpillSlotsAvailable.find(Slot)->second & 1;
310 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000311
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000312 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
313 /// stackslot register. The register is still available but is no longer
314 /// allowed to be modifed.
315 void disallowClobberPhysReg(unsigned PhysReg);
316
Chris Lattner66cf80f2006-02-03 23:13:58 +0000317 /// ClobberPhysReg - This is called when the specified physreg changes
318 /// value. We use this to invalidate any info about stuff we thing lives in
319 /// it and any of its aliases.
320 void ClobberPhysReg(unsigned PhysReg);
321
322 /// ModifyStackSlot - This method is called when the value in a stack slot
323 /// changes. This removes information about which register the previous value
324 /// for this slot lives in (as the previous value is dead now).
325 void ModifyStackSlot(int Slot);
326};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000327}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000328
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000329/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
330/// stackslot register. The register is still available but is no longer
331/// allowed to be modifed.
332void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
333 std::multimap<unsigned, int>::iterator I =
334 PhysRegsAvailable.lower_bound(PhysReg);
335 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
336 int Slot = I->second;
337 I++;
338 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
339 "Bidirectional map mismatch!");
340 SpillSlotsAvailable[Slot] &= ~1;
341 DOUT << "PhysReg " << MRI->getName(PhysReg)
342 << " copied, it is available for use but can no longer be modified\n";
343 }
344}
345
346/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
347/// stackslot register and its aliases. The register and its aliases may
348/// still available but is no longer allowed to be modifed.
349void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
350 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
351 disallowClobberPhysRegOnly(*AS);
352 disallowClobberPhysRegOnly(PhysReg);
353}
354
Chris Lattner66cf80f2006-02-03 23:13:58 +0000355/// ClobberPhysRegOnly - This is called when the specified physreg changes
356/// value. We use this to invalidate any info about stuff we thing lives in it.
357void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
358 std::multimap<unsigned, int>::iterator I =
359 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000360 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000361 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000362 PhysRegsAvailable.erase(I++);
Chris Lattner593c9582006-02-03 23:28:46 +0000363 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000364 "Bidirectional map mismatch!");
365 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000366 DOUT << "PhysReg " << MRI->getName(PhysReg)
367 << " clobbered, invalidating SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000368 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000369}
370
Chris Lattner66cf80f2006-02-03 23:13:58 +0000371/// ClobberPhysReg - This is called when the specified physreg changes
372/// value. We use this to invalidate any info about stuff we thing lives in
373/// it and any of its aliases.
374void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000375 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000376 ClobberPhysRegOnly(*AS);
377 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000378}
379
Chris Lattner07cf1412006-02-03 00:36:31 +0000380/// ModifyStackSlot - This method is called when the value in a stack slot
381/// changes. This removes information about which register the previous value
382/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000383void AvailableSpills::ModifyStackSlot(int Slot) {
384 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(Slot);
385 if (It == SpillSlotsAvailable.end()) return;
Chris Lattner593c9582006-02-03 23:28:46 +0000386 unsigned Reg = It->second >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000387 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000388
389 // This register may hold the value of multiple stack slots, only remove this
390 // stack slot from the set of values the register contains.
391 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
392 for (; ; ++I) {
393 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
394 "Map inverse broken!");
395 if (I->second == Slot) break;
396 }
397 PhysRegsAvailable.erase(I);
398}
399
400
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000401
Chris Lattner7fb64342004-10-01 19:04:51 +0000402// ReusedOp - For each reused operand, we keep track of a bit of information, in
403// case we need to rollback upon processing a new operand. See comments below.
404namespace {
405 struct ReusedOp {
406 // The MachineInstr operand that reused an available value.
407 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000408
Chris Lattner7fb64342004-10-01 19:04:51 +0000409 // StackSlot - The spill slot of the value being reused.
410 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000411
Chris Lattner7fb64342004-10-01 19:04:51 +0000412 // PhysRegReused - The physical register the value was available in.
413 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000414
Chris Lattner7fb64342004-10-01 19:04:51 +0000415 // AssignedPhysReg - The physreg that was assigned for use by the reload.
416 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000417
418 // VirtReg - The virtual register itself.
419 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000420
Chris Lattner8a61a752005-10-06 17:19:06 +0000421 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
422 unsigned vreg)
423 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
424 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000425 };
Chris Lattner540fec62006-02-25 01:51:33 +0000426
427 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
428 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000429 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000430 MachineInstr &MI;
431 std::vector<ReusedOp> Reuses;
Evan Chenge077ef62006-11-04 00:21:55 +0000432 bool *PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000433 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000434 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
435 PhysRegsClobbered = new bool[mri->getNumRegs()];
436 std::fill(PhysRegsClobbered, PhysRegsClobbered+mri->getNumRegs(), false);
437 }
438 ~ReuseInfo() {
439 delete[] PhysRegsClobbered;
440 }
Chris Lattner540fec62006-02-25 01:51:33 +0000441
442 bool hasReuses() const {
443 return !Reuses.empty();
444 }
445
446 /// addReuse - If we choose to reuse a virtual register that is already
447 /// available instead of reloading it, remember that we did so.
448 void addReuse(unsigned OpNo, unsigned StackSlot,
449 unsigned PhysRegReused, unsigned AssignedPhysReg,
450 unsigned VirtReg) {
451 // If the reload is to the assigned register anyway, no undo will be
452 // required.
453 if (PhysRegReused == AssignedPhysReg) return;
454
455 // Otherwise, remember this.
456 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
457 AssignedPhysReg, VirtReg));
458 }
Evan Chenge077ef62006-11-04 00:21:55 +0000459
460 void markClobbered(unsigned PhysReg) {
461 PhysRegsClobbered[PhysReg] = true;
462 }
463
464 bool isClobbered(unsigned PhysReg) const {
465 return PhysRegsClobbered[PhysReg];
466 }
Chris Lattner540fec62006-02-25 01:51:33 +0000467
468 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
469 /// is some other operand that is using the specified register, either pick
470 /// a new register to use, or evict the previous reload and use this reg.
471 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
472 AvailableSpills &Spills,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000473 std::map<int, MachineInstr*> &MaybeDeadStores,
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000474 SmallSet<unsigned, 8> &Rejected) {
Chris Lattner540fec62006-02-25 01:51:33 +0000475 if (Reuses.empty()) return PhysReg; // This is most often empty.
476
477 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
478 ReusedOp &Op = Reuses[ro];
479 // If we find some other reuse that was supposed to use this register
480 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000481 // register. That is, unless its reload register has already been
482 // considered and subsequently rejected because it has also been reused
483 // by another operand.
484 if (Op.PhysRegReused == PhysReg &&
485 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000486 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000487 unsigned NewReg = Op.AssignedPhysReg;
488 Rejected.insert(PhysReg);
489 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner540fec62006-02-25 01:51:33 +0000490 } else {
491 // Otherwise, we might also have a problem if a previously reused
492 // value aliases the new register. If so, codegen the previous reload
493 // and use this one.
494 unsigned PRRU = Op.PhysRegReused;
495 const MRegisterInfo *MRI = Spills.getRegInfo();
496 if (MRI->areAliases(PRRU, PhysReg)) {
497 // Okay, we found out that an alias of a reused register
498 // was used. This isn't good because it means we have
499 // to undo a previous reuse.
500 MachineBasicBlock *MBB = MI->getParent();
501 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000502 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
503
504 // Copy Op out of the vector and remove it, we're going to insert an
505 // explicit load for it.
506 ReusedOp NewOp = Op;
507 Reuses.erase(Reuses.begin()+ro);
508
509 // Ok, we're going to try to reload the assigned physreg into the
510 // slot that we were supposed to in the first place. However, that
511 // register could hold a reuse. Check to see if it conflicts or
512 // would prefer us to use a different register.
513 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000514 MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner28bad082006-02-25 02:17:31 +0000515
516 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
517 NewOp.StackSlot, AliasRC);
518 Spills.ClobberPhysReg(NewPhysReg);
519 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000520
521 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000522 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000523
Chris Lattnere53f4a02006-05-04 17:52:23 +0000524 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000525
Chris Lattner28bad082006-02-25 02:17:31 +0000526 Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000527 ++NumLoads;
528 DEBUG(MachineBasicBlock::iterator MII = MI;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000529 DOUT << '\t' << *prior(MII));
Chris Lattner540fec62006-02-25 01:51:33 +0000530
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000531 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000532 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000533
534 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000535 return PhysReg;
536 }
537 }
538 }
539 return PhysReg;
540 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000541
542 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
543 /// 'Rejected' set to remember which registers have been considered and
544 /// rejected for the reload. This avoids infinite looping in case like
545 /// this:
546 /// t1 := op t2, t3
547 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
548 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
549 /// t1 <- desires r1
550 /// sees r1 is taken by t2, tries t2's reload register r0
551 /// sees r0 is taken by t3, tries t3's reload register r1
552 /// sees r1 is taken by t2, tries t2's reload register r0 ...
553 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
554 AvailableSpills &Spills,
555 std::map<int, MachineInstr*> &MaybeDeadStores) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000556 SmallSet<unsigned, 8> Rejected;
Evan Cheng3c82cab2007-01-19 22:40:14 +0000557 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected);
558 }
Chris Lattner540fec62006-02-25 01:51:33 +0000559 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000560}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000561
Chris Lattner7fb64342004-10-01 19:04:51 +0000562
563/// rewriteMBB - Keep track of which spills are available even after the
564/// register allocator is done with them. If possible, avoid reloading vregs.
Chris Lattner35f27052006-05-01 21:16:03 +0000565void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000566
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000567 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000568
Chris Lattner66cf80f2006-02-03 23:13:58 +0000569 // Spills - Keep track of which spilled values are available in physregs so
570 // that we can choose to reuse the physregs instead of emitting reloads.
571 AvailableSpills Spills(MRI, TII);
572
Chris Lattner52b25db2004-10-01 19:47:12 +0000573 // MaybeDeadStores - When we need to write a value back into a stack slot,
574 // keep track of the inserted store. If the stack slot value is never read
575 // (because the value was used from some available register, for example), and
576 // subsequently stored to, the original store is dead. This map keeps track
577 // of inserted stores that are not used. If we see a subsequent store to the
578 // same stack slot, the original store is deleted.
579 std::map<int, MachineInstr*> MaybeDeadStores;
580
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000581 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
582
Chris Lattner7fb64342004-10-01 19:04:51 +0000583 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
584 MII != E; ) {
585 MachineInstr &MI = *MII;
586 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
587
Chris Lattner540fec62006-02-25 01:51:33 +0000588 /// ReusedOperands - Keep track of operand reuse in case we need to undo
589 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000590 ReuseInfo ReusedOperands(MI, MRI);
591
592 // Loop over all of the implicit defs, clearing them from our available
593 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000594 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
595 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000596 if (ImpDef) {
597 for ( ; *ImpDef; ++ImpDef) {
598 PhysRegsUsed[*ImpDef] = true;
599 ReusedOperands.markClobbered(*ImpDef);
600 Spills.ClobberPhysReg(*ImpDef);
601 }
602 }
603
Chris Lattner7fb64342004-10-01 19:04:51 +0000604 // Process all of the spilled uses and all non spilled reg references.
605 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
606 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000607 if (!MO.isRegister() || MO.getReg() == 0)
608 continue; // Ignore non-register operands.
609
610 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
611 // Ignore physregs for spilling, but remember that it is used by this
612 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000613 PhysRegsUsed[MO.getReg()] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000614 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000615 continue;
616 }
617
618 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
619 "Not a virtual or a physical register?");
620
621 unsigned VirtReg = MO.getReg();
622 if (!VRM.hasStackSlot(VirtReg)) {
623 // This virtual register was assigned a physreg!
624 unsigned Phys = VRM.getPhys(VirtReg);
625 PhysRegsUsed[Phys] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000626 if (MO.isDef())
627 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000628 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000629 continue;
630 }
631
632 // This virtual register is now known to be a spilled value.
633 if (!MO.isUse())
634 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000635
Chris Lattner50ea01e2005-09-09 20:29:51 +0000636 int StackSlot = VRM.getStackSlot(VirtReg);
637 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000638
Chris Lattner50ea01e2005-09-09 20:29:51 +0000639 // Check to see if this stack slot is available.
Chris Lattneraddc55a2006-04-28 01:46:50 +0000640 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000641
Chris Lattner29268692006-09-05 02:12:02 +0000642 // This spilled operand might be part of a two-address operand. If this
643 // is the case, then changing it will necessarily require changing the
644 // def part of the instruction as well. However, in some cases, we
645 // aren't allowed to modify the reused register. If none of these cases
646 // apply, reuse it.
647 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000648 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000649 if (ti != -1 &&
650 MI.getOperand(ti).isReg() &&
651 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000652 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000653 // long as we are allowed to clobber the value and there isn't an
654 // earlier def that has already clobbered the physreg.
Evan Chenge077ef62006-11-04 00:21:55 +0000655 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
656 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000657 }
658
659 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000660 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000661 DOUT << "Reusing SS#" << StackSlot << " from physreg "
662 << MRI->getName(PhysReg) << " for vreg"
663 << VirtReg <<" instead of reloading into physreg "
664 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000665 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000666
667 // The only technical detail we have is that we don't know that
668 // PhysReg won't be clobbered by a reloaded stack slot that occurs
669 // later in the instruction. In particular, consider 'op V1, V2'.
670 // If V1 is available in physreg R0, we would choose to reuse it
671 // here, instead of reloading it into the register the allocator
672 // indicated (say R1). However, V2 might have to be reloaded
673 // later, and it might indicate that it needs to live in R0. When
674 // this occurs, we need to have information available that
675 // indicates it is safe to use R1 for the reload instead of R0.
676 //
677 // To further complicate matters, we might conflict with an alias,
678 // or R0 and R1 might not be compatible with each other. In this
679 // case, we actually insert a reload for V1 in R1, ensuring that
680 // we can get at R0 or its alias.
681 ReusedOperands.addReuse(i, StackSlot, PhysReg,
682 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000683 if (ti != -1)
684 // Only mark it clobbered if this is a use&def operand.
685 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000686 ++NumReused;
687 continue;
688 }
689
690 // Otherwise we have a situation where we have a two-address instruction
691 // whose mod/ref operand needs to be reloaded. This reload is already
692 // available in some register "PhysReg", but if we used PhysReg as the
693 // operand to our 2-addr instruction, the instruction would modify
694 // PhysReg. This isn't cool if something later uses PhysReg and expects
695 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000696 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000697 // To avoid this problem, and to avoid doing a load right after a store,
698 // we emit a copy from PhysReg into the designated register for this
699 // operand.
700 unsigned DesignatedReg = VRM.getPhys(VirtReg);
701 assert(DesignatedReg && "Must map virtreg to physreg!");
702
703 // Note that, if we reused a register for a previous operand, the
704 // register we want to reload into might not actually be
705 // available. If this occurs, use the register indicated by the
706 // reuser.
707 if (ReusedOperands.hasReuses())
708 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
709 Spills, MaybeDeadStores);
710
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000711 // If the mapped designated register is actually the physreg we have
712 // incoming, we don't need to inserted a dead copy.
713 if (DesignatedReg == PhysReg) {
714 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000715 DOUT << "Reusing SS#" << StackSlot << " from physreg "
716 << MRI->getName(PhysReg) << " for vreg"
717 << VirtReg
718 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000719 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000720 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000721 ++NumReused;
722 continue;
723 }
724
Chris Lattneraddc55a2006-04-28 01:46:50 +0000725 const TargetRegisterClass* RC =
726 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
727
728 PhysRegsUsed[DesignatedReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000729 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000730 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
731
732 // This invalidates DesignatedReg.
733 Spills.ClobberPhysReg(DesignatedReg);
734
735 Spills.addAvailable(StackSlot, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000736 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000737 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000738 ++NumReused;
739 continue;
740 }
741
742 // Otherwise, reload it and remember that we have it.
743 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000744 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000745 const TargetRegisterClass* RC =
746 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000747
Chris Lattner50ea01e2005-09-09 20:29:51 +0000748 // Note that, if we reused a register for a previous operand, the
749 // register we want to reload into might not actually be
750 // available. If this occurs, use the register indicated by the
751 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000752 if (ReusedOperands.hasReuses())
753 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
754 Spills, MaybeDeadStores);
755
Chris Lattner50ea01e2005-09-09 20:29:51 +0000756 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000757 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000758 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000759 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000760 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000761
762 // Any stores to this stack slot are not dead anymore.
763 MaybeDeadStores.erase(StackSlot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000764 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000765 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000766 MI.getOperand(i).setReg(PhysReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000767 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000768 }
769
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000770 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000771
Chris Lattner7fb64342004-10-01 19:04:51 +0000772 // If we have folded references to memory operands, make sure we clear all
773 // physical registers that may contain the value of the spilled virtual
774 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000775 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
776 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000777 DOUT << "Folded vreg: " << I->second.first << " MR: "
778 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000779 unsigned VirtReg = I->second.first;
780 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000781 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000782 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000783 continue;
784 }
785 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000786 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000787
788 // If this folded instruction is just a use, check to see if it's a
789 // straight load from the virt reg slot.
790 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
791 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000792 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000793 if (FrameIdx == SS) {
794 // If this spill slot is available, turn it into a copy (or nothing)
795 // instead of leaving it as a load!
796 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000797 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000798 MachineFunction &MF = *MBB.getParent();
799 if (DestReg != InReg) {
800 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
801 MF.getSSARegMap()->getRegClass(VirtReg));
802 // Revisit the copy so we make sure to notice the effects of the
803 // operation on the destreg (either needing to RA it if it's
804 // virtual or needing to clobber any values if it's physical).
805 NextMII = &MI;
806 --NextMII; // backtrack to the copy.
807 }
808 VRM.RemoveFromFoldedVirtMap(&MI);
809 MBB.erase(&MI);
810 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000811 }
Chris Lattnercea86882005-09-19 06:56:21 +0000812 }
813 }
814 }
815
816 // If this reference is not a use, any previous store is now dead.
817 // Otherwise, the store to this stack slot is not dead anymore.
818 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
819 if (MDSI != MaybeDeadStores.end()) {
820 if (MR & VirtRegMap::isRef) // Previous store is not dead.
821 MaybeDeadStores.erase(MDSI);
822 else {
823 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000824 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000825 DOUT << "Removed dead store:\t" << *MDSI->second;
Chris Lattner35f27052006-05-01 21:16:03 +0000826 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000827 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000828 MaybeDeadStores.erase(MDSI);
829 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000830 }
831 }
832
833 // If the spill slot value is available, and this is a new definition of
834 // the value, the value is not available anymore.
835 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000836 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000837 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000838
839 // If this is *just* a mod of the value, check to see if this is just a
840 // store to the spill slot (i.e. the spill got merged into the copy). If
841 // so, realize that the vreg is available now, and add the store to the
842 // MaybeDeadStore info.
843 int StackSlot;
844 if (!(MR & VirtRegMap::isRef)) {
845 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
846 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
847 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000848 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000849 // this as a potentially dead store in case there is a subsequent
850 // store into the stack slot without a read from it.
851 MaybeDeadStores[StackSlot] = &MI;
852
Chris Lattnercd816392006-02-02 23:29:36 +0000853 // If the stack slot value was previously available in some other
854 // register, change it now. Otherwise, make the register available,
855 // in PhysReg.
Chris Lattner593c9582006-02-03 23:28:46 +0000856 Spills.addAvailable(StackSlot, SrcReg, false /*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +0000857 }
858 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000859 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000860 }
861
Chris Lattner7fb64342004-10-01 19:04:51 +0000862 // Process all of the spilled defs.
863 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
864 MachineOperand &MO = MI.getOperand(i);
865 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
866 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000867
Chris Lattner7fb64342004-10-01 19:04:51 +0000868 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +0000869 // Check to see if this is a noop copy. If so, eliminate the
870 // instruction before considering the dest reg to be changed.
871 unsigned Src, Dst;
872 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
873 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000874 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +0000875 MBB.erase(&MI);
876 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000877 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +0000878 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +0000879 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000880
881 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +0000882 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000883 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +0000884
885 // Check to see if this instruction is a load from a stack slot into
886 // a register. If so, this provides the stack slot value in the reg.
887 int FrameIdx;
888 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
889 assert(DestReg == VirtReg && "Unknown load situation!");
890
891 // Otherwise, if it wasn't available, remember that it is now!
892 Spills.addAvailable(FrameIdx, DestReg);
893 goto ProcessNextInst;
894 }
895
Chris Lattner29268692006-09-05 02:12:02 +0000896 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000897 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000898
Chris Lattner84e752a2006-02-03 03:06:49 +0000899 // The only vregs left are stack slot definitions.
900 int StackSlot = VRM.getStackSlot(VirtReg);
901 const TargetRegisterClass *RC =
902 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000903
Chris Lattner29268692006-09-05 02:12:02 +0000904 // If this def is part of a two-address operand, make sure to execute
905 // the store from the correct physical register.
906 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +0000907 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000908 if (TiedOp != -1)
909 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +0000910 else {
Chris Lattner29268692006-09-05 02:12:02 +0000911 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000912 if (ReusedOperands.isClobbered(PhysReg)) {
913 // Another def has taken the assigned physreg. It must have been a
914 // use&def which got it due to reuse. Undo the reuse!
915 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
916 Spills, MaybeDeadStores);
917 }
918 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000919
Chris Lattner84e752a2006-02-03 03:06:49 +0000920 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000921 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000922 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000923 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000924 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000925
Chris Lattner109afed2006-02-03 03:16:14 +0000926 // Check to see if this is a noop copy. If so, eliminate the
927 // instruction before considering the dest reg to be changed.
928 {
929 unsigned Src, Dst;
930 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
931 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000932 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner109afed2006-02-03 03:16:14 +0000933 MBB.erase(&MI);
Chris Lattner229924a2006-05-01 22:03:24 +0000934 VRM.RemoveFromFoldedVirtMap(&MI);
Chris Lattner109afed2006-02-03 03:16:14 +0000935 goto ProcessNextInst;
936 }
937 }
938
Chris Lattner84e752a2006-02-03 03:06:49 +0000939 // If there is a dead store to this stack slot, nuke it now.
940 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
941 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000942 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +0000943 ++NumDSE;
944 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +0000945 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +0000946 }
Chris Lattner84e752a2006-02-03 03:06:49 +0000947 LastStore = next(MII);
948
949 // If the stack slot value was previously available in some other
950 // register, change it now. Otherwise, make the register available,
951 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000952 Spills.ModifyStackSlot(StackSlot);
953 Spills.ClobberPhysReg(PhysReg);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000954 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000955 ++NumStores;
Chris Lattner7fb64342004-10-01 19:04:51 +0000956 }
957 }
Chris Lattnercea86882005-09-19 06:56:21 +0000958 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +0000959 MII = NextMII;
960 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000961}
962
Chris Lattnerf7da2c72006-08-24 22:43:55 +0000963
964
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000965llvm::Spiller* llvm::createSpiller() {
966 switch (SpillerOpt) {
967 default: assert(0 && "Unreachable!");
968 case local:
969 return new LocalSpiller();
970 case simple:
971 return new SimpleSpiller();
972 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000973}