blob: 911c5c6b79232d97de7b36f9b2b0c65c70cc78ee [file] [log] [blame]
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000030#include "llvm/ADT/Statistic.h"
31#include "llvm/ADT/STLExtras.h"
Chris Lattner27f29162004-10-26 15:35:58 +000032#include <algorithm>
Chris Lattner2c2c6c62006-01-22 23:41:00 +000033#include <iostream>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000034using namespace llvm;
35
36namespace {
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000037 static Statistic<> NumSpills("spiller", "Number of register spills");
38 static Statistic<> NumStores("spiller", "Number of stores added");
39 static Statistic<> NumLoads ("spiller", "Number of loads added");
40 static Statistic<> NumReused("spiller", "Number of values reused");
41 static Statistic<> NumDSE ("spiller", "Number of dead stores elided");
42 static Statistic<> NumDCE ("spiller", "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000043
Chris Lattner8c4d88d2004-09-30 01:54:45 +000044 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000045
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000046 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000047 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000048 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000049 cl::Prefix,
50 cl::values(clEnumVal(simple, " simple spiller"),
51 clEnumVal(local, " local spiller"),
52 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000053 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000054}
55
Chris Lattner8c4d88d2004-09-30 01:54:45 +000056//===----------------------------------------------------------------------===//
57// VirtRegMap implementation
58//===----------------------------------------------------------------------===//
59
Chris Lattner29268692006-09-05 02:12:02 +000060VirtRegMap::VirtRegMap(MachineFunction &mf)
61 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
62 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) {
63 grow();
64}
65
Chris Lattner8c4d88d2004-09-30 01:54:45 +000066void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000067 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
68 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000069}
70
Chris Lattner8c4d88d2004-09-30 01:54:45 +000071int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
72 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000073 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000074 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000075 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
76 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
77 RC->getAlignment());
78 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000079 ++NumSpills;
80 return frameIndex;
81}
82
83void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
84 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000085 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000086 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000087 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000088}
89
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000090void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +000091 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000092 // Move previous memory references folded to new instruction.
93 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +000094 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000095 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
96 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +000097 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +000098 }
Chris Lattnerdbea9732004-09-30 16:35:08 +000099
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000100 ModRef MRInfo;
Evan Cheng360c2dd2006-11-01 23:06:55 +0000101 if (TII.getOperandConstraint(OldMI->getOpcode(), OpNo,
102 TargetInstrInfo::TIED_TO)) {
Chris Lattner29268692006-09-05 02:12:02 +0000103 // Folded a two-address operand.
104 MRInfo = isModRef;
105 } else if (OldMI->getOperand(OpNo).isDef()) {
106 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000107 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000108 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000109 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000110
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000111 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000112 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000113}
114
Chris Lattner7f690e62004-09-30 02:15:18 +0000115void VirtRegMap::print(std::ostream &OS) const {
116 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000117
Chris Lattner7f690e62004-09-30 02:15:18 +0000118 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000119 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000120 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
121 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
122 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000123
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000124 }
125
126 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000127 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
128 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
129 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
130 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000131}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000132
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000133void VirtRegMap::dump() const { print(std::cerr); }
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000134
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000135
136//===----------------------------------------------------------------------===//
137// Simple Spiller Implementation
138//===----------------------------------------------------------------------===//
139
140Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000141
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000142namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000143 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000144 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000145 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000146}
147
Chris Lattner35f27052006-05-01 21:16:03 +0000148bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000149 DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
150 DEBUG(std::cerr << "********** Function: "
151 << MF.getFunction()->getName() << '\n');
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000152 const TargetMachine &TM = MF.getTarget();
153 const MRegisterInfo &MRI = *TM.getRegisterInfo();
154 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000155
Chris Lattner4ea1b822004-09-30 02:33:48 +0000156 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
157 // each vreg once (in the case where a spilled vreg is used by multiple
158 // operands). This is always smaller than the number of operands to the
159 // current machine instr, so it should be small.
160 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000161
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000162 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
163 MBBI != E; ++MBBI) {
164 DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n");
165 MachineBasicBlock &MBB = *MBBI;
166 for (MachineBasicBlock::iterator MII = MBB.begin(),
167 E = MBB.end(); MII != E; ++MII) {
168 MachineInstr &MI = *MII;
169 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000170 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000171 if (MO.isRegister() && MO.getReg())
172 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
173 unsigned VirtReg = MO.getReg();
174 unsigned PhysReg = VRM.getPhys(VirtReg);
175 if (VRM.hasStackSlot(VirtReg)) {
176 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000177 const TargetRegisterClass* RC =
178 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000179
Chris Lattner886dd912005-04-04 21:35:34 +0000180 if (MO.isUse() &&
181 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
182 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000183 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000184 LoadedRegs.push_back(VirtReg);
185 ++NumLoads;
186 DEBUG(std::cerr << '\t' << *prior(MII));
187 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000188
Chris Lattner886dd912005-04-04 21:35:34 +0000189 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000190 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000191 ++NumStores;
192 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000193 }
Chris Lattner886dd912005-04-04 21:35:34 +0000194 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000195 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000196 } else {
197 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000198 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000199 }
Chris Lattner886dd912005-04-04 21:35:34 +0000200
Chris Lattner477e4552004-09-30 16:10:45 +0000201 DEBUG(std::cerr << '\t' << MI);
Chris Lattner4ea1b822004-09-30 02:33:48 +0000202 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000203 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000204 }
205 return true;
206}
207
208//===----------------------------------------------------------------------===//
209// Local Spiller Implementation
210//===----------------------------------------------------------------------===//
211
212namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000213 /// LocalSpiller - This spiller does a simple pass over the machine basic
214 /// block to attempt to keep spills in registers as much as possible for
215 /// blocks that have low register pressure (the vreg may be spilled due to
216 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000217 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000218 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000219 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000220 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000221 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000222 MRI = MF.getTarget().getRegisterInfo();
223 TII = MF.getTarget().getInstrInfo();
224 DEBUG(std::cerr << "\n**** Local spiller rewriting function '"
225 << MF.getFunction()->getName() << "':\n");
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000226
Chris Lattner7fb64342004-10-01 19:04:51 +0000227 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
228 MBB != E; ++MBB)
229 RewriteMBB(*MBB, VRM);
230 return true;
231 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000232 private:
Chris Lattner35f27052006-05-01 21:16:03 +0000233 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner7fb64342004-10-01 19:04:51 +0000234 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000235 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner7fb64342004-10-01 19:04:51 +0000236 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000237 std::multimap<unsigned, int> &PhysRegs);
238 void ModifyStackSlot(int Slot, std::map<int, unsigned> &SpillSlots,
239 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000240 };
241}
242
Chris Lattner66cf80f2006-02-03 23:13:58 +0000243/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
244/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000245///
246/// Note that not all physregs are created equal here. In particular, some
247/// physregs are reloads that we are allowed to clobber or ignore at any time.
248/// Other physregs are values that the register allocated program is using that
249/// we cannot CHANGE, but we can read if we like. We keep track of this on a
250/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
251/// entries. The predicate 'canClobberPhysReg()' checks this bit and
252/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000253namespace {
254class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000255 const MRegisterInfo *MRI;
256 const TargetInstrInfo *TII;
257
258 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
259 // register values that are still available, due to being loaded or stored to,
260 // but not invalidated yet.
261 std::map<int, unsigned> SpillSlotsAvailable;
262
263 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
264 // which stack slot values are currently held by a physreg. This is used to
265 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
266 std::multimap<unsigned, int> PhysRegsAvailable;
267
268 void ClobberPhysRegOnly(unsigned PhysReg);
269public:
270 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
271 : MRI(mri), TII(tii) {
272 }
273
274 /// getSpillSlotPhysReg - If the specified stack slot is available in a
275 /// physical register, return that PhysReg, otherwise return 0.
276 unsigned getSpillSlotPhysReg(int Slot) const {
277 std::map<int, unsigned>::const_iterator I = SpillSlotsAvailable.find(Slot);
278 if (I != SpillSlotsAvailable.end())
Chris Lattner593c9582006-02-03 23:28:46 +0000279 return I->second >> 1; // Remove the CanClobber bit.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000280 return 0;
281 }
Chris Lattner540fec62006-02-25 01:51:33 +0000282
283 const MRegisterInfo *getRegInfo() const { return MRI; }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000284
285 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000286 /// specified physreg. If CanClobber is true, the physreg can be modified at
287 /// any time without changing the semantics of the program.
288 void addAvailable(int Slot, unsigned Reg, bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000289 // If this stack slot is thought to be available in some other physreg,
290 // remove its record.
291 ModifyStackSlot(Slot);
292
Chris Lattner66cf80f2006-02-03 23:13:58 +0000293 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Jeff Cohen003cecb2006-02-04 03:27:39 +0000294 SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000295
296 DEBUG(std::cerr << "Remembering SS#" << Slot << " in physreg "
297 << MRI->getName(Reg) << "\n");
298 }
299
Chris Lattner593c9582006-02-03 23:28:46 +0000300 /// canClobberPhysReg - Return true if the spiller is allowed to change the
301 /// value of the specified stackslot register if it desires. The specified
302 /// stack slot must be available in a physreg for this query to make sense.
303 bool canClobberPhysReg(int Slot) const {
304 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
305 return SpillSlotsAvailable.find(Slot)->second & 1;
306 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000307
308 /// ClobberPhysReg - This is called when the specified physreg changes
309 /// value. We use this to invalidate any info about stuff we thing lives in
310 /// it and any of its aliases.
311 void ClobberPhysReg(unsigned PhysReg);
312
313 /// ModifyStackSlot - This method is called when the value in a stack slot
314 /// changes. This removes information about which register the previous value
315 /// for this slot lives in (as the previous value is dead now).
316 void ModifyStackSlot(int Slot);
317};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000318}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000319
320/// ClobberPhysRegOnly - This is called when the specified physreg changes
321/// value. We use this to invalidate any info about stuff we thing lives in it.
322void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
323 std::multimap<unsigned, int>::iterator I =
324 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000325 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000326 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000327 PhysRegsAvailable.erase(I++);
Chris Lattner593c9582006-02-03 23:28:46 +0000328 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000329 "Bidirectional map mismatch!");
330 SpillSlotsAvailable.erase(Slot);
Chris Lattner7fb64342004-10-01 19:04:51 +0000331 DEBUG(std::cerr << "PhysReg " << MRI->getName(PhysReg)
Chris Lattner07cf1412006-02-03 00:36:31 +0000332 << " clobbered, invalidating SS#" << Slot << "\n");
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000333 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000334}
335
Chris Lattner66cf80f2006-02-03 23:13:58 +0000336/// ClobberPhysReg - This is called when the specified physreg changes
337/// value. We use this to invalidate any info about stuff we thing lives in
338/// it and any of its aliases.
339void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000340 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000341 ClobberPhysRegOnly(*AS);
342 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000343}
344
Chris Lattner07cf1412006-02-03 00:36:31 +0000345/// ModifyStackSlot - This method is called when the value in a stack slot
346/// changes. This removes information about which register the previous value
347/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000348void AvailableSpills::ModifyStackSlot(int Slot) {
349 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(Slot);
350 if (It == SpillSlotsAvailable.end()) return;
Chris Lattner593c9582006-02-03 23:28:46 +0000351 unsigned Reg = It->second >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000352 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000353
354 // This register may hold the value of multiple stack slots, only remove this
355 // stack slot from the set of values the register contains.
356 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
357 for (; ; ++I) {
358 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
359 "Map inverse broken!");
360 if (I->second == Slot) break;
361 }
362 PhysRegsAvailable.erase(I);
363}
364
365
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000366
Chris Lattner7fb64342004-10-01 19:04:51 +0000367// ReusedOp - For each reused operand, we keep track of a bit of information, in
368// case we need to rollback upon processing a new operand. See comments below.
369namespace {
370 struct ReusedOp {
371 // The MachineInstr operand that reused an available value.
372 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000373
Chris Lattner7fb64342004-10-01 19:04:51 +0000374 // StackSlot - The spill slot of the value being reused.
375 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000376
Chris Lattner7fb64342004-10-01 19:04:51 +0000377 // PhysRegReused - The physical register the value was available in.
378 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000379
Chris Lattner7fb64342004-10-01 19:04:51 +0000380 // AssignedPhysReg - The physreg that was assigned for use by the reload.
381 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000382
383 // VirtReg - The virtual register itself.
384 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000385
Chris Lattner8a61a752005-10-06 17:19:06 +0000386 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
387 unsigned vreg)
388 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
389 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000390 };
Chris Lattner540fec62006-02-25 01:51:33 +0000391
392 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
393 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000394 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000395 MachineInstr &MI;
396 std::vector<ReusedOp> Reuses;
397 public:
398 ReuseInfo(MachineInstr &mi) : MI(mi) {}
399
400 bool hasReuses() const {
401 return !Reuses.empty();
402 }
403
404 /// addReuse - If we choose to reuse a virtual register that is already
405 /// available instead of reloading it, remember that we did so.
406 void addReuse(unsigned OpNo, unsigned StackSlot,
407 unsigned PhysRegReused, unsigned AssignedPhysReg,
408 unsigned VirtReg) {
409 // If the reload is to the assigned register anyway, no undo will be
410 // required.
411 if (PhysRegReused == AssignedPhysReg) return;
412
413 // Otherwise, remember this.
414 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
415 AssignedPhysReg, VirtReg));
416 }
417
418 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
419 /// is some other operand that is using the specified register, either pick
420 /// a new register to use, or evict the previous reload and use this reg.
421 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
422 AvailableSpills &Spills,
423 std::map<int, MachineInstr*> &MaybeDeadStores) {
424 if (Reuses.empty()) return PhysReg; // This is most often empty.
425
426 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
427 ReusedOp &Op = Reuses[ro];
428 // If we find some other reuse that was supposed to use this register
429 // exactly for its reload, we can change this reload to use ITS reload
430 // register.
431 if (Op.PhysRegReused == PhysReg) {
432 // Yup, use the reload register that we didn't use before.
Chris Lattner47cb7172006-02-25 02:03:40 +0000433 unsigned NewReg = Op.AssignedPhysReg;
434
435 // Remove the record for the previous reuse. We know it can never be
436 // invalidated now.
437 Reuses.erase(Reuses.begin()+ro);
438 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores);
Chris Lattner540fec62006-02-25 01:51:33 +0000439 } else {
440 // Otherwise, we might also have a problem if a previously reused
441 // value aliases the new register. If so, codegen the previous reload
442 // and use this one.
443 unsigned PRRU = Op.PhysRegReused;
444 const MRegisterInfo *MRI = Spills.getRegInfo();
445 if (MRI->areAliases(PRRU, PhysReg)) {
446 // Okay, we found out that an alias of a reused register
447 // was used. This isn't good because it means we have
448 // to undo a previous reuse.
449 MachineBasicBlock *MBB = MI->getParent();
450 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000451 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
452
453 // Copy Op out of the vector and remove it, we're going to insert an
454 // explicit load for it.
455 ReusedOp NewOp = Op;
456 Reuses.erase(Reuses.begin()+ro);
457
458 // Ok, we're going to try to reload the assigned physreg into the
459 // slot that we were supposed to in the first place. However, that
460 // register could hold a reuse. Check to see if it conflicts or
461 // would prefer us to use a different register.
462 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
463 MI, Spills, MaybeDeadStores);
464
465 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
466 NewOp.StackSlot, AliasRC);
467 Spills.ClobberPhysReg(NewPhysReg);
468 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000469
470 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000471 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000472
Chris Lattnere53f4a02006-05-04 17:52:23 +0000473 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000474
Chris Lattner28bad082006-02-25 02:17:31 +0000475 Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000476 ++NumLoads;
477 DEBUG(MachineBasicBlock::iterator MII = MI;
478 std::cerr << '\t' << *prior(MII));
479
480 DEBUG(std::cerr << "Reuse undone!\n");
Chris Lattner540fec62006-02-25 01:51:33 +0000481 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000482
483 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000484 return PhysReg;
485 }
486 }
487 }
488 return PhysReg;
489 }
490 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000491}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000492
Chris Lattner7fb64342004-10-01 19:04:51 +0000493
494/// rewriteMBB - Keep track of which spills are available even after the
495/// register allocator is done with them. If possible, avoid reloading vregs.
Chris Lattner35f27052006-05-01 21:16:03 +0000496void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000497
Chris Lattner7fb64342004-10-01 19:04:51 +0000498 DEBUG(std::cerr << MBB.getBasicBlock()->getName() << ":\n");
499
Chris Lattner66cf80f2006-02-03 23:13:58 +0000500 // Spills - Keep track of which spilled values are available in physregs so
501 // that we can choose to reuse the physregs instead of emitting reloads.
502 AvailableSpills Spills(MRI, TII);
503
Chris Lattner52b25db2004-10-01 19:47:12 +0000504 // MaybeDeadStores - When we need to write a value back into a stack slot,
505 // keep track of the inserted store. If the stack slot value is never read
506 // (because the value was used from some available register, for example), and
507 // subsequently stored to, the original store is dead. This map keeps track
508 // of inserted stores that are not used. If we see a subsequent store to the
509 // same stack slot, the original store is deleted.
510 std::map<int, MachineInstr*> MaybeDeadStores;
511
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000512 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
513
Chris Lattner7fb64342004-10-01 19:04:51 +0000514 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
515 MII != E; ) {
516 MachineInstr &MI = *MII;
517 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
518
Chris Lattner540fec62006-02-25 01:51:33 +0000519 /// ReusedOperands - Keep track of operand reuse in case we need to undo
520 /// reuse.
521 ReuseInfo ReusedOperands(MI);
522
Chris Lattner7fb64342004-10-01 19:04:51 +0000523 // Process all of the spilled uses and all non spilled reg references.
524 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
525 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000526 if (!MO.isRegister() || MO.getReg() == 0)
527 continue; // Ignore non-register operands.
528
529 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
530 // Ignore physregs for spilling, but remember that it is used by this
531 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000532 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner50ea01e2005-09-09 20:29:51 +0000533 continue;
534 }
535
536 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
537 "Not a virtual or a physical register?");
538
539 unsigned VirtReg = MO.getReg();
540 if (!VRM.hasStackSlot(VirtReg)) {
541 // This virtual register was assigned a physreg!
542 unsigned Phys = VRM.getPhys(VirtReg);
543 PhysRegsUsed[Phys] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000544 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000545 continue;
546 }
547
548 // This virtual register is now known to be a spilled value.
549 if (!MO.isUse())
550 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000551
Chris Lattner50ea01e2005-09-09 20:29:51 +0000552 int StackSlot = VRM.getStackSlot(VirtReg);
553 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000554
Chris Lattner50ea01e2005-09-09 20:29:51 +0000555 // Check to see if this stack slot is available.
Chris Lattneraddc55a2006-04-28 01:46:50 +0000556 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000557
Chris Lattner29268692006-09-05 02:12:02 +0000558 // This spilled operand might be part of a two-address operand. If this
559 // is the case, then changing it will necessarily require changing the
560 // def part of the instruction as well. However, in some cases, we
561 // aren't allowed to modify the reused register. If none of these cases
562 // apply, reuse it.
563 bool CanReuse = true;
Evan Cheng360c2dd2006-11-01 23:06:55 +0000564 int ti = TII->getOperandConstraint(MI.getOpcode(), i,
565 TargetInstrInfo::TIED_TO);
566 if (ti != -1 &&
567 MI.getOperand(ti).isReg() &&
568 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000569 // Okay, we have a two address operand. We can reuse this physreg as
570 // long as we are allowed to clobber the value.
571 CanReuse = Spills.canClobberPhysReg(StackSlot);
572 }
573
574 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000575 // If this stack slot value is already available, reuse it!
576 DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg "
577 << MRI->getName(PhysReg) << " for vreg"
578 << VirtReg <<" instead of reloading into physreg "
579 << MRI->getName(VRM.getPhys(VirtReg)) << "\n");
Chris Lattnere53f4a02006-05-04 17:52:23 +0000580 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000581
582 // The only technical detail we have is that we don't know that
583 // PhysReg won't be clobbered by a reloaded stack slot that occurs
584 // later in the instruction. In particular, consider 'op V1, V2'.
585 // If V1 is available in physreg R0, we would choose to reuse it
586 // here, instead of reloading it into the register the allocator
587 // indicated (say R1). However, V2 might have to be reloaded
588 // later, and it might indicate that it needs to live in R0. When
589 // this occurs, we need to have information available that
590 // indicates it is safe to use R1 for the reload instead of R0.
591 //
592 // To further complicate matters, we might conflict with an alias,
593 // or R0 and R1 might not be compatible with each other. In this
594 // case, we actually insert a reload for V1 in R1, ensuring that
595 // we can get at R0 or its alias.
596 ReusedOperands.addReuse(i, StackSlot, PhysReg,
597 VRM.getPhys(VirtReg), VirtReg);
598 ++NumReused;
599 continue;
600 }
601
602 // Otherwise we have a situation where we have a two-address instruction
603 // whose mod/ref operand needs to be reloaded. This reload is already
604 // available in some register "PhysReg", but if we used PhysReg as the
605 // operand to our 2-addr instruction, the instruction would modify
606 // PhysReg. This isn't cool if something later uses PhysReg and expects
607 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000608 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000609 // To avoid this problem, and to avoid doing a load right after a store,
610 // we emit a copy from PhysReg into the designated register for this
611 // operand.
612 unsigned DesignatedReg = VRM.getPhys(VirtReg);
613 assert(DesignatedReg && "Must map virtreg to physreg!");
614
615 // Note that, if we reused a register for a previous operand, the
616 // register we want to reload into might not actually be
617 // available. If this occurs, use the register indicated by the
618 // reuser.
619 if (ReusedOperands.hasReuses())
620 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
621 Spills, MaybeDeadStores);
622
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000623 // If the mapped designated register is actually the physreg we have
624 // incoming, we don't need to inserted a dead copy.
625 if (DesignatedReg == PhysReg) {
626 // If this stack slot value is already available, reuse it!
627 DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg "
628 << MRI->getName(PhysReg) << " for vreg"
629 << VirtReg
630 << " instead of reloading into same physreg.\n");
Chris Lattnere53f4a02006-05-04 17:52:23 +0000631 MI.getOperand(i).setReg(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000632 ++NumReused;
633 continue;
634 }
635
Chris Lattneraddc55a2006-04-28 01:46:50 +0000636 const TargetRegisterClass* RC =
637 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
638
639 PhysRegsUsed[DesignatedReg] = true;
640 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
641
642 // This invalidates DesignatedReg.
643 Spills.ClobberPhysReg(DesignatedReg);
644
645 Spills.addAvailable(StackSlot, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000646 MI.getOperand(i).setReg(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000647 DEBUG(std::cerr << '\t' << *prior(MII));
Chris Lattner50ea01e2005-09-09 20:29:51 +0000648 ++NumReused;
649 continue;
650 }
651
652 // Otherwise, reload it and remember that we have it.
653 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000654 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000655 const TargetRegisterClass* RC =
656 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000657
Chris Lattner50ea01e2005-09-09 20:29:51 +0000658 // Note that, if we reused a register for a previous operand, the
659 // register we want to reload into might not actually be
660 // available. If this occurs, use the register indicated by the
661 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000662 if (ReusedOperands.hasReuses())
663 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
664 Spills, MaybeDeadStores);
665
Chris Lattner50ea01e2005-09-09 20:29:51 +0000666 PhysRegsUsed[PhysReg] = true;
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000667 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000668 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000669 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000670
671 // Any stores to this stack slot are not dead anymore.
672 MaybeDeadStores.erase(StackSlot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000673 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000674 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000675 MI.getOperand(i).setReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000676 DEBUG(std::cerr << '\t' << *prior(MII));
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000677 }
678
Chris Lattner7fb64342004-10-01 19:04:51 +0000679 // Loop over all of the implicit defs, clearing them from our available
680 // sets.
Jim Laskeycd4317e2006-07-21 21:15:20 +0000681 const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
682 if (ImpDef) {
683 for ( ; *ImpDef; ++ImpDef) {
684 PhysRegsUsed[*ImpDef] = true;
685 Spills.ClobberPhysReg(*ImpDef);
686 }
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000687 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000688
Chris Lattner7fb64342004-10-01 19:04:51 +0000689 DEBUG(std::cerr << '\t' << MI);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000690
Chris Lattner7fb64342004-10-01 19:04:51 +0000691 // If we have folded references to memory operands, make sure we clear all
692 // physical registers that may contain the value of the spilled virtual
693 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000694 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
695 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000696 DEBUG(std::cerr << "Folded vreg: " << I->second.first << " MR: "
697 << I->second.second);
698 unsigned VirtReg = I->second.first;
699 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000700 if (!VRM.hasStackSlot(VirtReg)) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000701 DEBUG(std::cerr << ": No stack slot!\n");
Chris Lattnercea86882005-09-19 06:56:21 +0000702 continue;
703 }
704 int SS = VRM.getStackSlot(VirtReg);
705 DEBUG(std::cerr << " - StackSlot: " << SS << "\n");
706
707 // If this folded instruction is just a use, check to see if it's a
708 // straight load from the virt reg slot.
709 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
710 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000711 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000712 if (FrameIdx == SS) {
713 // If this spill slot is available, turn it into a copy (or nothing)
714 // instead of leaving it as a load!
715 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS)) {
716 DEBUG(std::cerr << "Promoted Load To Copy: " << MI);
717 MachineFunction &MF = *MBB.getParent();
718 if (DestReg != InReg) {
719 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
720 MF.getSSARegMap()->getRegClass(VirtReg));
721 // Revisit the copy so we make sure to notice the effects of the
722 // operation on the destreg (either needing to RA it if it's
723 // virtual or needing to clobber any values if it's physical).
724 NextMII = &MI;
725 --NextMII; // backtrack to the copy.
726 }
727 VRM.RemoveFromFoldedVirtMap(&MI);
728 MBB.erase(&MI);
729 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000730 }
Chris Lattnercea86882005-09-19 06:56:21 +0000731 }
732 }
733 }
734
735 // If this reference is not a use, any previous store is now dead.
736 // Otherwise, the store to this stack slot is not dead anymore.
737 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
738 if (MDSI != MaybeDeadStores.end()) {
739 if (MR & VirtRegMap::isRef) // Previous store is not dead.
740 MaybeDeadStores.erase(MDSI);
741 else {
742 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000743 assert(VirtRegMap::isMod && "Can't be modref!");
744 DEBUG(std::cerr << "Removed dead store:\t" << *MDSI->second);
745 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000746 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000747 MaybeDeadStores.erase(MDSI);
748 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000749 }
750 }
751
752 // If the spill slot value is available, and this is a new definition of
753 // the value, the value is not available anymore.
754 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000755 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000756 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000757
758 // If this is *just* a mod of the value, check to see if this is just a
759 // store to the spill slot (i.e. the spill got merged into the copy). If
760 // so, realize that the vreg is available now, and add the store to the
761 // MaybeDeadStore info.
762 int StackSlot;
763 if (!(MR & VirtRegMap::isRef)) {
764 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
765 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
766 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000767 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000768 // this as a potentially dead store in case there is a subsequent
769 // store into the stack slot without a read from it.
770 MaybeDeadStores[StackSlot] = &MI;
771
Chris Lattnercd816392006-02-02 23:29:36 +0000772 // If the stack slot value was previously available in some other
773 // register, change it now. Otherwise, make the register available,
774 // in PhysReg.
Chris Lattner593c9582006-02-03 23:28:46 +0000775 Spills.addAvailable(StackSlot, SrcReg, false /*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +0000776 }
777 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000778 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000779 }
780
Chris Lattner7fb64342004-10-01 19:04:51 +0000781 // Process all of the spilled defs.
782 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
783 MachineOperand &MO = MI.getOperand(i);
784 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
785 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000786
Chris Lattner7fb64342004-10-01 19:04:51 +0000787 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +0000788 // Check to see if this is a noop copy. If so, eliminate the
789 // instruction before considering the dest reg to be changed.
790 unsigned Src, Dst;
791 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
792 ++NumDCE;
793 DEBUG(std::cerr << "Removing now-noop copy: " << MI);
794 MBB.erase(&MI);
795 VRM.RemoveFromFoldedVirtMap(&MI);
796 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +0000797 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000798
799 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +0000800 Spills.ClobberPhysReg(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +0000801
802 // Check to see if this instruction is a load from a stack slot into
803 // a register. If so, this provides the stack slot value in the reg.
804 int FrameIdx;
805 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
806 assert(DestReg == VirtReg && "Unknown load situation!");
807
808 // Otherwise, if it wasn't available, remember that it is now!
809 Spills.addAvailable(FrameIdx, DestReg);
810 goto ProcessNextInst;
811 }
812
Chris Lattner29268692006-09-05 02:12:02 +0000813 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000814 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000815
Chris Lattner84e752a2006-02-03 03:06:49 +0000816 // The only vregs left are stack slot definitions.
817 int StackSlot = VRM.getStackSlot(VirtReg);
818 const TargetRegisterClass *RC =
819 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000820
Chris Lattner29268692006-09-05 02:12:02 +0000821 // If this def is part of a two-address operand, make sure to execute
822 // the store from the correct physical register.
823 unsigned PhysReg;
Evan Cheng360c2dd2006-11-01 23:06:55 +0000824 int TiedOp = TII->getTiedToSrcOperand(MI.getOpcode(), i);
825 if (TiedOp != -1)
826 PhysReg = MI.getOperand(TiedOp).getReg();
Chris Lattner84e752a2006-02-03 03:06:49 +0000827 else
Chris Lattner29268692006-09-05 02:12:02 +0000828 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000829
Chris Lattner84e752a2006-02-03 03:06:49 +0000830 PhysRegsUsed[PhysReg] = true;
831 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
832 DEBUG(std::cerr << "Store:\t" << *next(MII));
Chris Lattnere53f4a02006-05-04 17:52:23 +0000833 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000834
Chris Lattner109afed2006-02-03 03:16:14 +0000835 // Check to see if this is a noop copy. If so, eliminate the
836 // instruction before considering the dest reg to be changed.
837 {
838 unsigned Src, Dst;
839 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
840 ++NumDCE;
841 DEBUG(std::cerr << "Removing now-noop copy: " << MI);
842 MBB.erase(&MI);
Chris Lattner229924a2006-05-01 22:03:24 +0000843 VRM.RemoveFromFoldedVirtMap(&MI);
Chris Lattner109afed2006-02-03 03:16:14 +0000844 goto ProcessNextInst;
845 }
846 }
847
Chris Lattner84e752a2006-02-03 03:06:49 +0000848 // If there is a dead store to this stack slot, nuke it now.
849 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
850 if (LastStore) {
Chris Lattner35f27052006-05-01 21:16:03 +0000851 DEBUG(std::cerr << "Removed dead store:\t" << *LastStore);
Chris Lattner84e752a2006-02-03 03:06:49 +0000852 ++NumDSE;
853 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +0000854 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +0000855 }
Chris Lattner84e752a2006-02-03 03:06:49 +0000856 LastStore = next(MII);
857
858 // If the stack slot value was previously available in some other
859 // register, change it now. Otherwise, make the register available,
860 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000861 Spills.ModifyStackSlot(StackSlot);
862 Spills.ClobberPhysReg(PhysReg);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000863 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000864 ++NumStores;
Chris Lattner7fb64342004-10-01 19:04:51 +0000865 }
866 }
Chris Lattnercea86882005-09-19 06:56:21 +0000867 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +0000868 MII = NextMII;
869 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000870}
871
Chris Lattnerf7da2c72006-08-24 22:43:55 +0000872
873
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000874llvm::Spiller* llvm::createSpiller() {
875 switch (SpillerOpt) {
876 default: assert(0 && "Unreachable!");
877 case local:
878 return new LocalSpiller();
879 case simple:
880 return new SimpleSpiller();
881 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000882}