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Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]6 <title>The LLVM Target-Independent Code Generator</title>
7 <link rel="stylesheet" href="llvm.css" type="text/css">
8</head>
9<body>
10
11<div class="doc_title">
12 The LLVM Target-Independent Code Generator
13</div>
14
15<ol>
16 <li><a href="#introduction">Introduction</a>
17 <ul>
18 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]19 <li><a href="#high-level-design">The high-level design of the code
20 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]21 <li><a href="#tablegen">Using TableGen for target description</a></li>
22 </ul>
23 </li>
24 <li><a href="#targetdesc">Target description classes</a>
25 <ul>
26 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
27 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]28 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]29 <li><a href="#targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]30 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
31 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]32 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]33 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
34 </ul>
35 </li>
36 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]37 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]38 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]39 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
40 class</a></li>
41 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]42 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]43 </li>
44 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]45 <ul>
46 <li><a href="#instselect">Instruction Selection</a>
47 <ul>
48 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
49 <li><a href="#selectiondag_process">SelectionDAG Code Generation
50 Process</a></li>
51 <li><a href="#selectiondag_build">Initial SelectionDAG
52 Construction</a></li>
53 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
54 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]55 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]56 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]57 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]58 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]59 <li><a href="#selectiondag_future">Future directions for the
60 SelectionDAG</a></li>
61 </ul></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]62 <li><a href="#liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]63 <ul>
64 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]65 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]66 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]67 <li><a href="#regalloc">Register Allocation</a>
68 <ul>
69 <li><a href="#regAlloc_represent">How registers are represented in
70 LLVM</a></li>
71 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
72 registers</a></li>
73 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
74 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
75 <li><a href="#regAlloc_fold">Instruction folding</a></li>
76 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
77 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]78 <li><a href="#codeemit">Code Emission</a>
79 <ul>
80 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
81 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
82 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]83 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]84 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]85 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]86 <ul>
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]87 <li><a href="#tailcallopt">Tail call optimization</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]88 <li><a href="#x86">The X86 backend</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]89 <li><a href="#ppc">The PowerPC backend</a>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]90 <ul>
91 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
92 <li><a href="#ppc_frame">Frame Layout</a></li>
93 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
94 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]95 </ul></li>
96 </ul></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]97
98</ol>
99
100<div class="doc_author">
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]101 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a>,
Jim Laskeyd201f4e2007-03-14 19:30:33 +0000[diff] [blame]102 <a href="mailto:isanbard@gmail.com">Bill Wendling</a>,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]103 <a href="mailto:pronesto@gmail.com">Fernando Magno Quintao
Jim Laskeyd201f4e2007-03-14 19:30:33 +0000[diff] [blame]104 Pereira</a> and
105 <a href="mailto:jlaskey@mac.com">Jim Laskey</a></p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]106</div>
107
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]108<div class="doc_warning">
109 <p>Warning: This is a work in progress.</p>
110</div>
111
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]112<!-- *********************************************************************** -->
113<div class="doc_section">
114 <a name="introduction">Introduction</a>
115</div>
116<!-- *********************************************************************** -->
117
118<div class="doc_text">
119
120<p>The LLVM target-independent code generator is a framework that provides a
121suite of reusable components for translating the LLVM internal representation to
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]122the machine code for a specified target&mdash;either in assembly form (suitable
123for a static compiler) or in binary machine code format (usable for a JIT
124compiler). The LLVM target-independent code generator consists of five main
125components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]126
127<ol>
128<li><a href="#targetdesc">Abstract target description</a> interfaces which
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]129capture important properties about various aspects of the machine, independently
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]130of how they will be used. These interfaces are defined in
131<tt>include/llvm/Target/</tt>.</li>
132
133<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]134generated for a target. These classes are intended to be abstract enough to
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]135represent the machine code for <i>any</i> target machine. These classes are
136defined in <tt>include/llvm/CodeGen/</tt>.</li>
137
138<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
139various phases of native code generation (register allocation, scheduling, stack
140frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
141
142<li><a href="#targetimpls">Implementations of the abstract target description
143interfaces</a> for particular targets. These machine descriptions make use of
144the components provided by LLVM, and can optionally provide custom
145target-specific passes, to build complete code generators for a specific target.
146Target descriptions live in <tt>lib/Target/</tt>.</li>
147
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]148<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
149completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
150interface for target-specific issues. The code for the target-independent
151JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
152
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]153</ol>
154
155<p>
156Depending on which part of the code generator you are interested in working on,
157different pieces of this will be useful to you. In any case, you should be
158familiar with the <a href="#targetdesc">target description</a> and <a
159href="#codegendesc">machine code representation</a> classes. If you want to add
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]160a backend for a new target, you will need to <a href="#targetimpls">implement the
161target description</a> classes for your new target and understand the <a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]162href="LangRef.html">LLVM code representation</a>. If you are interested in
163implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
164should only depend on the target-description and machine code representation
165classes, ensuring that it is portable.
166</p>
167
168</div>
169
170<!-- ======================================================================= -->
171<div class="doc_subsection">
172 <a name="required">Required components in the code generator</a>
173</div>
174
175<div class="doc_text">
176
177<p>The two pieces of the LLVM code generator are the high-level interface to the
178code generator and the set of reusable components that can be used to build
179target-specific backends. The two most important interfaces (<a
180href="#targetmachine"><tt>TargetMachine</tt></a> and <a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]181href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]182required to be defined for a backend to fit into the LLVM system, but the others
183must be defined if the reusable code generator components are going to be
184used.</p>
185
186<p>This design has two important implications. The first is that LLVM can
187support completely non-traditional code generation targets. For example, the C
188backend does not require register allocation, instruction selection, or any of
189the other standard components provided by the system. As such, it only
190implements these two interfaces, and does its own thing. Another example of a
191code generator like this is a (purely hypothetical) backend that converts LLVM
192to the GCC RTL form and uses GCC to emit machine code for a target.</p>
193
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]194<p>This design also implies that it is possible to design and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]195implement radically different code generators in the LLVM system that do not
196make use of any of the built-in components. Doing so is not recommended at all,
197but could be required for radically different targets that do not fit into the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]198LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]199
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]200</div>
201
202<!-- ======================================================================= -->
203<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]204 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]205</div>
206
207<div class="doc_text">
208
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]209<p>The LLVM target-independent code generator is designed to support efficient and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]210quality code generation for standard register-based microprocessors. Code
211generation in this model is divided into the following stages:</p>
212
213<ol>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]214<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
215determines an efficient way to express the input LLVM code in the target
216instruction set.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]217This stage produces the initial code for the program in the target instruction
218set, then makes use of virtual registers in SSA form and physical registers that
219represent any required register assignments due to target constraints or calling
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]220conventions. This step turns the LLVM code into a DAG of target
221instructions.</li>
222
223<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
224phase takes the DAG of target instructions produced by the instruction selection
225phase, determines an ordering of the instructions, then emits the instructions
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]226as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
227that we describe this in the <a href="#instselect">instruction selection
228section</a> because it operates on a <a
229href="#selectiondag_intro">SelectionDAG</a>.
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]230</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]231
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]232<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
233optional stage consists of a series of machine-code optimizations that
234operate on the SSA-form produced by the instruction selector. Optimizations
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]235like modulo-scheduling or peephole optimization work here.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]236</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]237
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]238<li><b><a href="#regalloc">Register Allocation</a></b> - The
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]239target code is transformed from an infinite virtual register file in SSA form
240to the concrete register file used by the target. This phase introduces spill
241code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]242
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]243<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]244machine code has been generated for the function and the amount of stack space
245required is known (used for LLVM alloca's and spill slots), the prolog and
246epilog code for the function can be inserted and "abstract stack location
247references" can be eliminated. This stage is responsible for implementing
248optimizations like frame-pointer elimination and stack packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]249
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]250<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]251that operate on "final" machine code can go here, such as spill code scheduling
252and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]253
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]254<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]255puts out the code for the current function, either in the target assembler
256format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]257
258</ol>
259
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]260<p>The code generator is based on the assumption that the instruction selector
261will use an optimal pattern matching selector to create high-quality sequences of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]262native instructions. Alternative code generator designs based on pattern
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]263expansion and aggressive iterative peephole optimization are much slower. This
264design permits efficient compilation (important for JIT environments) and
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]265aggressive optimization (used when generating code offline) by allowing
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]266components of varying levels of sophistication to be used for any step of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]267compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]268
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]269<p>In addition to these stages, target implementations can insert arbitrary
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]270target-specific passes into the flow. For example, the X86 target uses a
271special pass to handle the 80x87 floating point stack architecture. Other
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]272targets with unusual requirements can be supported with custom passes as
273needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]274
275</div>
276
277
278<!-- ======================================================================= -->
279<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]280 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]281</div>
282
283<div class="doc_text">
284
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]285<p>The target description classes require a detailed description of the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]286architecture. These target descriptions often have a large amount of common
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]287information (e.g., an <tt>add</tt> instruction is almost identical to a
288<tt>sub</tt> instruction).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]289In order to allow the maximum amount of commonality to be factored out, the LLVM
290code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]291describe big chunks of the target machine, which allows the use of
292domain-specific and target-specific abstractions to reduce the amount of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]293repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]294
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]295<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]296of the target description to the <tt>.td</tt> form. Doing so gives us a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]297number of advantages. The most important is that it makes it easier to port
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]298LLVM because it reduces the amount of C++ code that has to be written, and the
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]299surface area of the code generator that needs to be understood before someone
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]300can get something working. Second, it makes it easier to change things. In
301particular, if tables and other things are all emitted by <tt>tblgen</tt>, we
302only need a change in one place (<tt>tblgen</tt>) to update all of the targets
303to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]304
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]305</div>
306
307<!-- *********************************************************************** -->
308<div class="doc_section">
309 <a name="targetdesc">Target description classes</a>
310</div>
311<!-- *********************************************************************** -->
312
313<div class="doc_text">
314
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]315<p>The LLVM target description classes (located in the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]316<tt>include/llvm/Target</tt> directory) provide an abstract description of the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]317target machine independent of any particular client. These classes are
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]318designed to capture the <i>abstract</i> properties of the target (such as the
319instructions and registers it has), and do not incorporate any particular pieces
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]320of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]321
322<p>All of the target description classes (except the <tt><a
323href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
324the concrete target implementation, and have virtual methods implemented. To
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]325get to these implementations, the <tt><a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]326href="#targetmachine">TargetMachine</a></tt> class provides accessors that
327should be implemented by the target.</p>
328
329</div>
330
331<!-- ======================================================================= -->
332<div class="doc_subsection">
333 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
334</div>
335
336<div class="doc_text">
337
338<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
339access the target-specific implementations of the various target description
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]340classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
341<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
342designed to be specialized by
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]343a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
344implements the various virtual methods. The only required target description
345class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
346code generator components are to be used, the other interfaces should be
347implemented as well.</p>
348
349</div>
350
351
352<!-- ======================================================================= -->
353<div class="doc_subsection">
354 <a name="targetdata">The <tt>TargetData</tt> class</a>
355</div>
356
357<div class="doc_text">
358
359<p>The <tt>TargetData</tt> class is the only required target description class,
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]360and it is the only class that is not extensible (you cannot derived a new
361class from it). <tt>TargetData</tt> specifies information about how the target
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]362lays out memory for structures, the alignment requirements for various data
363types, the size of pointers in the target, and whether the target is
364little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]365
366</div>
367
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]368<!-- ======================================================================= -->
369<div class="doc_subsection">
370 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
371</div>
372
373<div class="doc_text">
374
375<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
376selectors primarily to describe how LLVM code should be lowered to SelectionDAG
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]377operations. Among other things, this class indicates:</p>
378
379<ul>
380 <li>an initial register class to use for various <tt>ValueType</tt>s</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]381 <li>which operations are natively supported by the target machine</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]382 <li>the return type of <tt>setcc</tt> operations</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]383 <li>the type to use for shift amounts</li>
384 <li>various high-level characteristics, like whether it is profitable to turn
385 division by a constant into a multiplication sequence</li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]386</ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]387
388</div>
389
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]390<!-- ======================================================================= -->
391<div class="doc_subsection">
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]392 <a name="targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]393</div>
394
395<div class="doc_text">
396
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]397<p>The <tt>TargetRegisterInfo</tt> class is used to describe the register
398file of the target and any interactions between the registers.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]399
400<p>Registers in the code generator are represented in the code generator by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]401unsigned integers. Physical registers (those that actually exist in the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]402description) are unique small numbers, and virtual registers are generally
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]403large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]404
405<p>Each register in the processor description has an associated
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]406<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
407register (used for assembly output and debugging dumps) and a set of aliases
408(used to indicate whether one register overlaps with another).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]409</p>
410
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]411<p>In addition to the per-register description, the <tt>TargetRegisterInfo</tt>
412class exposes a set of processor specific register classes (instances of the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]413<tt>TargetRegisterClass</tt> class). Each register class contains sets of
414registers that have the same properties (for example, they are all 32-bit
415integer registers). Each SSA virtual register created by the instruction
416selector has an associated register class. When the register allocator runs, it
417replaces virtual registers with a physical register in the set.</p>
418
419<p>
420The target-specific implementations of these classes is auto-generated from a <a
421href="TableGenFundamentals.html">TableGen</a> description of the register file.
422</p>
423
424</div>
425
426<!-- ======================================================================= -->
427<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]428 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]429</div>
430
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]431<div class="doc_text">
432 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
433 instructions supported by the target. It is essentially an array of
434 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
435 instruction the target supports. Descriptors define things like the mnemonic
Chris Lattnera3079782005-07-19 03:37:48 +0000[diff] [blame]436 for the opcode, the number of operands, the list of implicit register uses
437 and defs, whether the instruction has certain target-independent properties
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]438 (accesses memory, is commutable, etc), and holds any target-specific
439 flags.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]440</div>
441
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]442<!-- ======================================================================= -->
443<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]444 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]445</div>
446
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]447<div class="doc_text">
448 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
449 stack frame layout of the target. It holds the direction of stack growth,
450 the known stack alignment on entry to each function, and the offset to the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]451 local area. The offset to the local area is the offset from the stack
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]452 pointer on function entry to the first location where function data (local
453 variables, spill locations) can be stored.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]454</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]455
456<!-- ======================================================================= -->
457<div class="doc_subsection">
458 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
459</div>
460
461<div class="doc_text">
Jim Laskey82d61a12005-10-17 12:19:10 +0000[diff] [blame]462 <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
463 specific chip set being targeted. A sub-target informs code generation of
464 which instructions are supported, instruction latencies and instruction
465 execution itinerary; i.e., which processing units are used, in what order, and
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]466 for how long.</p>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]467</div>
468
469
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]470<!-- ======================================================================= -->
471<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]472 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]473</div>
474
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]475<div class="doc_text">
476 <p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
477 Just-In-Time code generator to perform target-specific activities, such as
478 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
479 should provide one of these objects through the <tt>getJITInfo</tt>
480 method.</p>
481</div>
482
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]483<!-- *********************************************************************** -->
484<div class="doc_section">
485 <a name="codegendesc">Machine code description classes</a>
486</div>
487<!-- *********************************************************************** -->
488
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]489<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]490
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]491<p>At the high-level, LLVM code is translated to a machine specific
492representation formed out of
493<a href="#machinefunction"><tt>MachineFunction</tt></a>,
494<a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>, and <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]495href="#machineinstr"><tt>MachineInstr</tt></a> instances
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]496(defined in <tt>include/llvm/CodeGen</tt>). This representation is completely
497target agnostic, representing instructions in their most abstract form: an
498opcode and a series of operands. This representation is designed to support
499both an SSA representation for machine code, as well as a register allocated,
500non-SSA form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]501
502</div>
503
504<!-- ======================================================================= -->
505<div class="doc_subsection">
506 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
507</div>
508
509<div class="doc_text">
510
511<p>Target machine instructions are represented as instances of the
512<tt>MachineInstr</tt> class. This class is an extremely abstract way of
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]513representing machine instructions. In particular, it only keeps track of
514an opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]515
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]516<p>The opcode number is a simple unsigned integer that only has meaning to a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]517specific backend. All of the instructions for a target should be defined in
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]518the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]519are auto-generated from this description. The <tt>MachineInstr</tt> class does
520not have any information about how to interpret the instruction (i.e., what the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]521semantics of the instruction are); for that you must refer to the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]522<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
523
524<p>The operands of a machine instruction can be of several different types:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]525a register reference, a constant integer, a basic block reference, etc. In
526addition, a machine operand should be marked as a def or a use of the value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]527(though only registers are allowed to be defs).</p>
528
529<p>By convention, the LLVM code generator orders instruction operands so that
530all register definitions come before the register uses, even on architectures
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]531that are normally printed in other orders. For example, the SPARC add
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]532instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
533and stores the result into the "%i3" register. In the LLVM code generator,
534the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
535first.</p>
536
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]537<p>Keeping destination (definition) operands at the beginning of the operand
538list has several advantages. In particular, the debugging printer will print
539the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]540
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]541<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]542<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]543%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]544</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]545</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]546
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]547<p>Also if the first operand is a def, it is easier to <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]548href="#buildmi">create instructions</a> whose only def is the first
549operand.</p>
550
551</div>
552
553<!-- _______________________________________________________________________ -->
554<div class="doc_subsubsection">
555 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
556</div>
557
558<div class="doc_text">
559
560<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
561located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
562<tt>BuildMI</tt> functions make it easy to build arbitrary machine
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]563instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]564
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]565<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]566<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]567// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
568// instruction. The '1' specifies how many operands will be added.
569MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]570
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]571// Create the same instr, but insert it at the end of a basic block.
572MachineBasicBlock &amp;MBB = ...
573BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]574
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]575// Create the same instr, but insert it before a specified iterator point.
576MachineBasicBlock::iterator MBBI = ...
577BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]578
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]579// Create a 'cmp Reg, 0' instruction, no destination reg.
580MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
581// Create an 'sahf' instruction which takes no operands and stores nothing.
582MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]583
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]584// Create a self looping branch instruction.
585BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]586</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]587</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]588
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]589<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
590have to specify the number of operands that the machine instruction will take.
591This allows for efficient memory allocation. You also need to specify if
592operands default to be uses of values, not definitions. If you need to add a
593definition operand (other than the optional destination register), you must
594explicitly mark it as such:</p>
595
596<div class="doc_code">
597<pre>
598MI.addReg(Reg, MachineOperand::Def);
599</pre>
600</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]601
602</div>
603
604<!-- _______________________________________________________________________ -->
605<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]606 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]607</div>
608
609<div class="doc_text">
610
611<p>One important issue that the code generator needs to be aware of is the
612presence of fixed registers. In particular, there are often places in the
613instruction stream where the register allocator <em>must</em> arrange for a
614particular value to be in a particular register. This can occur due to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]615limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]616with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
617conventions. In any case, the instruction selector should emit code that
618copies a virtual register into or out of a physical register when needed.</p>
619
620<p>For example, consider this simple LLVM example:</p>
621
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]622<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]623<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]624int %test(int %X, int %Y) {
625 %Z = div int %X, %Y
626 ret int %Z
627}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]628</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]629</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]630
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]631<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
632and <tt>ret</tt> (use
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]633"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
634
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]635<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]636<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]637;; Start of div
638%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
639%reg1027 = sar %reg1024, 31
640%EDX = mov %reg1027 ;; Sign extend X into EDX
641idiv %reg1025 ;; Divide by Y (in reg1025)
642%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]643
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]644;; Start of ret
645%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
646ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]647</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]648</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]649
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]650<p>By the end of code generation, the register allocator has coalesced
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]651the registers and deleted the resultant identity moves producing the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]652following code:</p>
653
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]654<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]655<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]656;; X is in EAX, Y is in ECX
657mov %EAX, %EDX
658sar %EDX, 31
659idiv %ECX
660ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]661</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]662</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]663
664<p>This approach is extremely general (if it can handle the X86 architecture,
665it can handle anything!) and allows all of the target specific
666knowledge about the instruction stream to be isolated in the instruction
667selector. Note that physical registers should have a short lifetime for good
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]668code generation, and all physical registers are assumed dead on entry to and
669exit from basic blocks (before register allocation). Thus, if you need a value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]670to be live across basic block boundaries, it <em>must</em> live in a virtual
671register.</p>
672
673</div>
674
675<!-- _______________________________________________________________________ -->
676<div class="doc_subsubsection">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]677 <a name="ssa">Machine code in SSA form</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]678</div>
679
680<div class="doc_text">
681
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]682<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]683are maintained in SSA-form until register allocation happens. For the most
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]684part, this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]685become machine code PHI nodes, and virtual registers are only allowed to have a
686single definition.</p>
687
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]688<p>After register allocation, machine code is no longer in SSA-form because there
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]689are no virtual registers left in the code.</p>
690
691</div>
692
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]693<!-- ======================================================================= -->
694<div class="doc_subsection">
695 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
696</div>
697
698<div class="doc_text">
699
700<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]701(<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
702corresponds to the LLVM code input to the instruction selector, but there can be
703a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
704basic blocks). The <tt>MachineBasicBlock</tt> class has a
705"<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
706comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]707
708</div>
709
710<!-- ======================================================================= -->
711<div class="doc_subsection">
712 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
713</div>
714
715<div class="doc_text">
716
717<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]718(<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
719corresponds one-to-one with the LLVM function input to the instruction selector.
720In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
721a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]722<tt>MachineFunctionInfo</tt>, and a <tt>MachineRegisterInfo</tt>. See
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]723<tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]724
725</div>
726
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]727<!-- *********************************************************************** -->
728<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]729 <a name="codegenalgs">Target-independent code generation algorithms</a>
730</div>
731<!-- *********************************************************************** -->
732
733<div class="doc_text">
734
735<p>This section documents the phases described in the <a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]736href="#high-level-design">high-level design of the code generator</a>. It
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]737explains how they work and some of the rationale behind their design.</p>
738
739</div>
740
741<!-- ======================================================================= -->
742<div class="doc_subsection">
743 <a name="instselect">Instruction Selection</a>
744</div>
745
746<div class="doc_text">
747<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]748Instruction Selection is the process of translating LLVM code presented to the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]749code generator into target-specific machine instructions. There are several
Evan Cheng77949352007-10-08 17:54:24 +0000[diff] [blame]750well-known ways to do this in the literature. LLVM uses a SelectionDAG based
751instruction selector.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]752</p>
753
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]754<p>Portions of the DAG instruction selector are generated from the target
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]755description (<tt>*.td</tt>) files. Our goal is for the entire instruction
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame]756selector to be generated from these <tt>.td</tt> files, though currently
757there are still things that require custom C++ code.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]758</div>
759
760<!-- _______________________________________________________________________ -->
761<div class="doc_subsubsection">
762 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
763</div>
764
765<div class="doc_text">
766
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]767<p>The SelectionDAG provides an abstraction for code representation in a way
768that is amenable to instruction selection using automatic techniques
769(e.g. dynamic-programming based optimal pattern matching selectors). It is also
770well-suited to other phases of code generation; in particular,
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]771instruction scheduling (SelectionDAG's are very close to scheduling DAGs
772post-selection). Additionally, the SelectionDAG provides a host representation
773where a large variety of very-low-level (but target-independent)
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]774<a href="#selectiondag_optimize">optimizations</a> may be
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]775performed; ones which require extensive information about the instructions
776efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]777
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]778<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]779<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]780operation code (Opcode) that indicates what operation the node performs and
781the operands to the operation.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]782The various operation node types are described at the top of the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]783<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]784
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]785<p>Although most operations define a single value, each node in the graph may
786define multiple values. For example, a combined div/rem operation will define
787both the dividend and the remainder. Many other situations require multiple
788values as well. Each node also has some number of operands, which are edges
789to the node defining the used value. Because nodes may define multiple values,
790edges are represented by instances of the <tt>SDOperand</tt> class, which is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]791a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node and result
792value being used, respectively. Each value produced by an <tt>SDNode</tt> has
793an associated <tt>MVT::ValueType</tt> indicating what type the value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]794
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]795<p>SelectionDAGs contain two different kinds of values: those that represent
796data flow and those that represent control flow dependencies. Data values are
797simple edges with an integer or floating point value type. Control edges are
798represented as "chain" edges which are of type <tt>MVT::Other</tt>. These edges
799provide an ordering between nodes that have side effects (such as
800loads, stores, calls, returns, etc). All nodes that have side effects should
801take a token chain as input and produce a new one as output. By convention,
802token chain inputs are always operand #0, and chain results are always the last
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]803value produced by an operation.</p>
804
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]805<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
806always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root node
807is the final side-effecting node in the token chain. For example, in a single
808basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]809
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]810<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
811"illegal" DAG. A legal DAG for a target is one that only uses supported
812operations and supported types. On a 32-bit PowerPC, for example, a DAG with
813a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that uses a
814SREM or UREM operation. The
815<a href="#selectiondag_legalize">legalize</a> phase is responsible for turning
816an illegal DAG into a legal DAG.</p>
817
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]818</div>
819
820<!-- _______________________________________________________________________ -->
821<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]822 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]823</div>
824
825<div class="doc_text">
826
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]827<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]828
829<ol>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]830<li><a href="#selectiondag_build">Build initial DAG</a> - This stage
831 performs a simple translation from the input LLVM code to an illegal
832 SelectionDAG.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]833<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]834 performs simple optimizations on the SelectionDAG to simplify it, and
835 recognize meta instructions (like rotates and <tt>div</tt>/<tt>rem</tt>
836 pairs) for targets that support these meta operations. This makes the
837 resultant code more efficient and the <a href="#selectiondag_select">select
838 instructions from DAG</a> phase (below) simpler.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]839<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]840 converts the illegal SelectionDAG to a legal SelectionDAG by eliminating
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]841 unsupported operations and data types.</li>
842<li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]843 second run of the SelectionDAG optimizes the newly legalized DAG to
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]844 eliminate inefficiencies introduced by legalization.</li>
845<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
846 the target instruction selector matches the DAG operations to target
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]847 instructions. This process translates the target-independent input DAG into
848 another DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]849<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]850 - The last phase assigns a linear order to the instructions in the
851 target-instruction DAG and emits them into the MachineFunction being
852 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]853</ol>
854
855<p>After all of these steps are complete, the SelectionDAG is destroyed and the
856rest of the code generation passes are run.</p>
857
Chris Lattnerdf921f02005-10-17 01:40:33 +0000[diff] [blame]858<p>One great way to visualize what is going on here is to take advantage of a
859few LLC command line options. In particular, the <tt>-view-isel-dags</tt>
860option pops up a window with the SelectionDAG input to the Select phase for all
861of the code compiled (if you only get errors printed to the console while using
862this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
863your system</a> to add support for it). The <tt>-view-sched-dags</tt> option
864views the SelectionDAG output from the Select phase and input to the Scheduler
Dan Gohmane9bb13d2007-10-15 21:07:59 +0000[diff] [blame]865phase. The <tt>-view-sunit-dags</tt> option views the ScheduleDAG, which is
866based on the final SelectionDAG, with nodes that must be scheduled as a unit
867bundled together into a single node, and with immediate operands and other
868nodes that aren't relevent for scheduling omitted.
869</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]870
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]871</div>
872
873<!-- _______________________________________________________________________ -->
874<div class="doc_subsubsection">
875 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
876</div>
877
878<div class="doc_text">
879
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]880<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
881input by the <tt>SelectionDAGLowering</tt> class in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]882<tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of this
883pass is to expose as much low-level, target-specific details to the SelectionDAG
884as possible. This pass is mostly hard-coded (e.g. an LLVM <tt>add</tt> turns
885into an <tt>SDNode add</tt> while a <tt>geteelementptr</tt> is expanded into the
886obvious arithmetic). This pass requires target-specific hooks to lower calls,
887returns, varargs, etc. For these features, the
888<tt><a href="#targetlowering">TargetLowering</a></tt> interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]889
890</div>
891
892<!-- _______________________________________________________________________ -->
893<div class="doc_subsubsection">
894 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
895</div>
896
897<div class="doc_text">
898
899<p>The Legalize phase is in charge of converting a DAG to only use the types and
900operations that are natively supported by the target. This involves two major
901tasks:</p>
902
903<ol>
904<li><p>Convert values of unsupported types to values of supported types.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]905 <p>There are two main ways of doing this: converting small types to
906 larger types ("promoting"), and breaking up large integer types
907 into smaller ones ("expanding"). For example, a target might require
908 that all f32 values are promoted to f64 and that all i1/i8/i16 values
909 are promoted to i32. The same target might require that all i64 values
910 be expanded into i32 values. These changes can insert sign and zero
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]911 extensions as needed to make sure that the final code has the same
912 behavior as the input.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]913 <p>A target implementation tells the legalizer which types are supported
914 (and which register class to use for them) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]915 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]916</li>
917
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]918<li><p>Eliminate operations that are not supported by the target.</p>
919 <p>Targets often have weird constraints, such as not supporting every
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]920 operation on every supported datatype (e.g. X86 does not support byte
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]921 conditional moves and PowerPC does not support sign-extending loads from
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]922 a 16-bit memory location). Legalize takes care of this by open-coding
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]923 another sequence of operations to emulate the operation ("expansion"), by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]924 promoting one type to a larger type that supports the operation
925 ("promotion"), or by using a target-specific hook to implement the
926 legalization ("custom").</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]927 <p>A target implementation tells the legalizer which operations are not
928 supported (and which of the above three actions to take) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]929 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
930 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]931</li>
932</ol>
933
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]934<p>Prior to the existance of the Legalize pass, we required that every target
935<a href="#selectiondag_optimize">selector</a> supported and handled every
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]936operator and type even if they are not natively supported. The introduction of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]937the Legalize phase allows all of the cannonicalization patterns to be shared
938across targets, and makes it very easy to optimize the cannonicalized code
939because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]940
941</div>
942
943<!-- _______________________________________________________________________ -->
944<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]945 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
946 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]947</div>
948
949<div class="doc_text">
950
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]951<p>The SelectionDAG optimization phase is run twice for code generation: once
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]952immediately after the DAG is built and once after legalization. The first run
953of the pass allows the initial code to be cleaned up (e.g. performing
954optimizations that depend on knowing that the operators have restricted type
955inputs). The second run of the pass cleans up the messy code generated by the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]956Legalize pass, which allows Legalize to be very simple (it can focus on making
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]957code legal instead of focusing on generating <em>good</em> and legal code).</p>
958
959<p>One important class of optimizations performed is optimizing inserted sign
960and zero extension instructions. We currently use ad-hoc techniques, but could
961move to more rigorous techniques in the future. Here are some good papers on
962the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]963
964<p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]965 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
966 integer arithmetic</a>"<br>
967 Kevin Redwine and Norman Ramsey<br>
968 International Conference on Compiler Construction (CC) 2004
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]969</p>
970
971
972<p>
973 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
974 sign extension elimination</a>"<br>
975 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
976 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
977 and Implementation.
978</p>
979
980</div>
981
982<!-- _______________________________________________________________________ -->
983<div class="doc_subsubsection">
984 <a name="selectiondag_select">SelectionDAG Select Phase</a>
985</div>
986
987<div class="doc_text">
988
989<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]990selection. This phase takes a legal SelectionDAG as input, pattern matches the
991instructions supported by the target to this DAG, and produces a new DAG of
992target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]993
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]994<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]995<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]996%t1 = add float %W, %X
997%t2 = mul float %t1, %Y
998%t3 = add float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]999</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1000</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1001
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1002<p>This LLVM code corresponds to a SelectionDAG that looks basically like
1003this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1004
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1005<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1006<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1007(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1008</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1009</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1010
Chris Lattnera1ff9312005-10-17 15:19:24 +0000[diff] [blame]1011<p>If a target supports floating point multiply-and-add (FMA) operations, one
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1012of the adds can be merged with the multiply. On the PowerPC, for example, the
1013output of the instruction selector might look like this DAG:</p>
1014
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1015<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1016<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1017(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1018</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1019</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1020
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1021<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1022first two operands and adds the third (as single-precision floating-point
1023numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1024add instruction. To perform this pattern match, the PowerPC backend includes
1025the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1026
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1027<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1028<pre>
1029def FMADDS : AForm_1&lt;59, 29,
1030 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1031 "fmadds $FRT, $FRA, $FRC, $FRB",
1032 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1033 F4RC:$FRB))</b>]&gt;;
1034def FADDS : AForm_2&lt;59, 21,
1035 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1036 "fadds $FRT, $FRA, $FRB",
1037 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1038</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1039</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1040
1041<p>The portion of the instruction definition in bold indicates the pattern used
1042to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
1043are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
1044"<tt>F4RC</tt>" is the register class of the input and result values.<p>
1045
1046<p>The TableGen DAG instruction selector generator reads the instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1047patterns in the <tt>.td</tt> file and automatically builds parts of the pattern
1048matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1049
1050<ul>
1051<li>At compiler-compiler time, it analyzes your instruction patterns and tells
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1052 you if your patterns make sense or not.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1053<li>It can handle arbitrary constraints on operands for the pattern match. In
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1054 particular, it is straight-forward to say things like "match any immediate
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1055 that is a 13-bit sign-extended value". For examples, see the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1056 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1057 backend.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1058<li>It knows several important identities for the patterns defined. For
1059 example, it knows that addition is commutative, so it allows the
1060 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1061 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1062 to specially handle this case.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1063<li>It has a full-featured type-inferencing system. In particular, you should
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1064 rarely have to explicitly tell the system what type parts of your patterns
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1065 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1066 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'. It
1067 was able to infer and propagate this knowledge from the fact that
1068 <tt>F4RC</tt> has type 'f32'.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1069<li>Targets can define their own (and rely on built-in) "pattern fragments".
1070 Pattern fragments are chunks of reusable patterns that get inlined into your
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1071 patterns during compiler-compiler time. For example, the integer
1072 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment that
1073 expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not have a
1074 native '<tt>not</tt>' operation. Targets can define their own short-hand
1075 fragments as they see fit. See the definition of '<tt>not</tt>' and
1076 '<tt>ineg</tt>' for examples.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1077<li>In addition to instructions, targets can specify arbitrary patterns that
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1078 map to one or more instructions using the 'Pat' class. For example,
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1079 the PowerPC has no way to load an arbitrary integer immediate into a
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1080 register in one instruction. To tell tblgen how to do this, it defines:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1081 <br>
1082 <br>
1083 <div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1084 <pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1085// Arbitrary immediate support. Implement in terms of LIS/ORI.
1086def : Pat&lt;(i32 imm:$imm),
1087 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1088 </pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1089 </div>
1090 <br>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1091 If none of the single-instruction patterns for loading an immediate into a
1092 register match, this will be used. This rule says "match an arbitrary i32
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1093 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and an
1094 <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to the
1095 left 16 bits') instruction". To make this work, the
1096 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate the
1097 input immediate (in this case, take the high or low 16-bits of the
1098 immediate).</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1099<li>While the system does automate a lot, it still allows you to write custom
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1100 C++ code to match special cases if there is something that is hard to
1101 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1102</ul>
1103
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1104<p>While it has many strengths, the system currently has some limitations,
1105primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1106
1107<ul>
1108<li>Overall, there is no way to define or match SelectionDAG nodes that define
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1109 multiple values (e.g. <tt>ADD_PARTS</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
1110 etc). This is the biggest reason that you currently still <em>have to</em>
1111 write custom C++ code for your instruction selector.</li>
1112<li>There is no great way to support matching complex addressing modes yet. In
1113 the future, we will extend pattern fragments to allow them to define
1114 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame]1115 addressing mode</a>, which are currently matched with custom C++ code).
1116 In addition, we'll extend fragments so that a
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1117 fragment can match multiple different patterns.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1118<li>We don't automatically infer flags like isStore/isLoad yet.</li>
1119<li>We don't automatically generate the set of supported registers and
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1120 operations for the <a href="#selectiondag_legalize">Legalizer</a> yet.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1121<li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1122</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1123
1124<p>Despite these limitations, the instruction selector generator is still quite
1125useful for most of the binary and logical operations in typical instruction
1126sets. If you run into any problems or can't figure out how to do something,
1127please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1128
1129</div>
1130
1131<!-- _______________________________________________________________________ -->
1132<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1133 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1134</div>
1135
1136<div class="doc_text">
1137
1138<p>The scheduling phase takes the DAG of target instructions from the selection
1139phase and assigns an order. The scheduler can pick an order depending on
1140various constraints of the machines (i.e. order for minimal register pressure or
1141try to cover instruction latencies). Once an order is established, the DAG is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1142converted to a list of <tt><a href="#machineinstr">MachineInstr</a></tt>s and
1143the SelectionDAG is destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1144
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1145<p>Note that this phase is logically separate from the instruction selection
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1146phase, but is tied to it closely in the code because it operates on
1147SelectionDAGs.</p>
1148
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1149</div>
1150
1151<!-- _______________________________________________________________________ -->
1152<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1153 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1154</div>
1155
1156<div class="doc_text">
1157
1158<ol>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1159<li>Optional function-at-a-time selection.</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1160<li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1161</ol>
1162
1163</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1164
1165<!-- ======================================================================= -->
1166<div class="doc_subsection">
1167 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1168</div>
1169<div class="doc_text"><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1170
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1171<!-- ======================================================================= -->
1172<div class="doc_subsection">
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1173 <a name="liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1174</div>
1175
1176<div class="doc_text">
1177
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1178<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
1179They are used by some <a href="#regalloc">register allocator</a> passes to
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1180determine if two or more virtual registers which require the same physical
Bill Wendling41b32522006-09-07 08:39:35 +0000[diff] [blame]1181register are live at the same point in the program (i.e., they conflict). When
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1182this situation occurs, one virtual register must be <i>spilled</i>.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1183
1184</div>
1185
1186<!-- _______________________________________________________________________ -->
1187<div class="doc_subsubsection">
1188 <a name="livevariable_analysis">Live Variable Analysis</a>
1189</div>
1190
1191<div class="doc_text">
1192
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1193<p>The first step in determining the live intervals of variables is to
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1194calculate the set of registers that are immediately dead after the
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1195instruction (i.e., the instruction calculates the value, but it is
1196never used) and the set of registers that are used by the instruction,
1197but are never used after the instruction (i.e., they are killed). Live
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1198variable information is computed for each <i>virtual</i> register and
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1199<i>register allocatable</i> physical register in the function. This
1200is done in a very efficient manner because it uses SSA to sparsely
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1201compute lifetime information for virtual registers (which are in SSA
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1202form) and only has to track physical registers within a block. Before
1203register allocation, LLVM can assume that physical registers are only
1204live within a single basic block. This allows it to do a single,
1205local analysis to resolve physical register lifetimes within each
1206basic block. If a physical register is not register allocatable (e.g.,
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1207a stack pointer or condition codes), it is not tracked.</p>
1208
1209<p>Physical registers may be live in to or out of a function. Live in values
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1210are typically arguments in registers. Live out values are typically return
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1211values in registers. Live in values are marked as such, and are given a dummy
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1212"defining" instruction during live intervals analysis. If the last basic block
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1213of a function is a <tt>return</tt>, then it's marked as using all live out
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1214values in the function.</p>
1215
1216<p><tt>PHI</tt> nodes need to be handled specially, because the calculation
1217of the live variable information from a depth first traversal of the CFG of
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1218the function won't guarantee that a virtual register used by the <tt>PHI</tt>
1219node is defined before it's used. When a <tt>PHI</tt> node is encounted, only
1220the definition is handled, because the uses will be handled in other basic
1221blocks.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1222
1223<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
1224assignment at the end of the current basic block and traverse the successor
1225basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1226the <tt>PHI</tt> node's operands is coming from the current basic block,
1227then the variable is marked as <i>alive</i> within the current basic block
1228and all of its predecessor basic blocks, until the basic block with the
1229defining instruction is encountered.</p>
1230
1231</div>
1232
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1233<!-- _______________________________________________________________________ -->
1234<div class="doc_subsubsection">
1235 <a name="liveintervals_analysis">Live Intervals Analysis</a>
1236</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1237
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1238<div class="doc_text">
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1239
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1240<p>We now have the information available to perform the live intervals analysis
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1241and build the live intervals themselves. We start off by numbering the basic
1242blocks and machine instructions. We then handle the "live-in" values. These
1243are in physical registers, so the physical register is assumed to be killed by
1244the end of the basic block. Live intervals for virtual registers are computed
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1245for some ordering of the machine instructions <tt>[1, N]</tt>. A live interval
1246is an interval <tt>[i, j)</tt>, where <tt>1 <= i <= j < N</tt>, for which a
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1247variable is live.</p>
1248
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1249<p><i><b>More to come...</b></i></p>
1250
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1251</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1252
1253<!-- ======================================================================= -->
1254<div class="doc_subsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1255 <a name="regalloc">Register Allocation</a>
1256</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1257
1258<div class="doc_text">
1259
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1260<p>The <i>Register Allocation problem</i> consists in mapping a program
1261<i>P<sub>v</sub></i>, that can use an unbounded number of virtual
1262registers, to a program <i>P<sub>p</sub></i> that contains a finite
1263(possibly small) number of physical registers. Each target architecture has
1264a different number of physical registers. If the number of physical
1265registers is not enough to accommodate all the virtual registers, some of
1266them will have to be mapped into memory. These virtuals are called
1267<i>spilled virtuals</i>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1268
1269</div>
1270
1271<!-- _______________________________________________________________________ -->
1272
1273<div class="doc_subsubsection">
1274 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1275</div>
1276
1277<div class="doc_text">
1278
1279<p>In LLVM, physical registers are denoted by integer numbers that
1280normally range from 1 to 1023. To see how this numbering is defined
1281for a particular architecture, you can read the
1282<tt>GenRegisterNames.inc</tt> file for that architecture. For
1283instance, by inspecting
1284<tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the 32-bit
1285register <tt>EAX</tt> is denoted by 15, and the MMX register
1286<tt>MM0</tt> is mapped to 48.</p>
1287
1288<p>Some architectures contain registers that share the same physical
1289location. A notable example is the X86 platform. For instance, in the
1290X86 architecture, the registers <tt>EAX</tt>, <tt>AX</tt> and
1291<tt>AL</tt> share the first eight bits. These physical registers are
1292marked as <i>aliased</i> in LLVM. Given a particular architecture, you
1293can check which registers are aliased by inspecting its
1294<tt>RegisterInfo.td</tt> file. Moreover, the method
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1295<tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1296all the physical registers aliased to the register <tt>p_reg</tt>.</p>
1297
1298<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
1299Elements in the same register class are functionally equivalent, and can
1300be interchangeably used. Each virtual register can only be mapped to
1301physical registers of a particular class. For instance, in the X86
1302architecture, some virtuals can only be allocated to 8 bit registers.
1303A register class is described by <tt>TargetRegisterClass</tt> objects.
1304To discover if a virtual register is compatible with a given physical,
1305this code can be used:
1306</p>
1307
1308<div class="doc_code">
1309<pre>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1310bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1311 unsigned v_reg,
1312 unsigned p_reg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1313 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1314 "Target register must be physical");
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]1315 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1316 return trc-&gt;contains(p_reg);
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1317}
1318</pre>
1319</div>
1320
1321<p>Sometimes, mostly for debugging purposes, it is useful to change
1322the number of physical registers available in the target
1323architecture. This must be done statically, inside the
1324<tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt> for
1325<tt>RegisterClass</tt>, the last parameter of which is a list of
1326registers. Just commenting some out is one simple way to avoid them
1327being used. A more polite way is to explicitly exclude some registers
1328from the <i>allocation order</i>. See the definition of the
1329<tt>GR</tt> register class in
1330<tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
1331(e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
1332
1333<p>Virtual registers are also denoted by integer numbers. Contrary to
1334physical registers, different virtual registers never share the same
1335number. The smallest virtual register is normally assigned the number
13361024. This may change, so, in order to know which is the first virtual
1337register, you should access
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1338<tt>TargetRegisterInfo::FirstVirtualRegister</tt>. Any register whose
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1339number is greater than or equal to
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1340<tt>TargetRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1341register. Whereas physical registers are statically defined in a
1342<tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1343application developer, that is not the case with virtual registers.
1344In order to create new virtual registers, use the method
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]1345<tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method will return a
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1346virtual register with the highest code.
1347</p>
1348
1349<p>Before register allocation, the operands of an instruction are
1350mostly virtual registers, although physical registers may also be
1351used. In order to check if a given machine operand is a register, use
1352the boolean function <tt>MachineOperand::isRegister()</tt>. To obtain
1353the integer code of a register, use
1354<tt>MachineOperand::getReg()</tt>. An instruction may define or use a
1355register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1356defines the registers 1024, and uses registers 1025 and 1026. Given a
1357register operand, the method <tt>MachineOperand::isUse()</tt> informs
1358if that register is being used by the instruction. The method
1359<tt>MachineOperand::isDef()</tt> informs if that registers is being
1360defined.</p>
1361
Gabor Greif04367bf2007-07-06 22:07:22 +0000[diff] [blame]1362<p>We will call physical registers present in the LLVM bitcode before
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1363register allocation <i>pre-colored registers</i>. Pre-colored
1364registers are used in many different situations, for instance, to pass
1365parameters of functions calls, and to store results of particular
1366instructions. There are two types of pre-colored registers: the ones
1367<i>implicitly</i> defined, and those <i>explicitly</i>
1368defined. Explicitly defined registers are normal operands, and can be
1369accessed with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In
1370order to check which registers are implicitly defined by an
1371instruction, use the
1372<tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>, where
1373<tt>opcode</tt> is the opcode of the target instruction. One important
1374difference between explicit and implicit physical registers is that
1375the latter are defined statically for each instruction, whereas the
1376former may vary depending on the program being compiled. For example,
1377an instruction that represents a function call will always implicitly
1378define or use the same set of physical registers. To read the
1379registers implicitly used by an instruction, use
1380<tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1381registers impose constraints on any register allocation algorithm. The
1382register allocator must make sure that none of them is been
1383overwritten by the values of virtual registers while still alive.</p>
1384
1385</div>
1386
1387<!-- _______________________________________________________________________ -->
1388
1389<div class="doc_subsubsection">
1390 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1391</div>
1392
1393<div class="doc_text">
1394
1395<p>There are two ways to map virtual registers to physical registers (or to
1396memory slots). The first way, that we will call <i>direct mapping</i>,
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1397is based on the use of methods of the classes <tt>TargetRegisterInfo</tt>,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1398and <tt>MachineOperand</tt>. The second way, that we will call
1399<i>indirect mapping</i>, relies on the <tt>VirtRegMap</tt> class in
1400order to insert loads and stores sending and getting values to and from
1401memory.</p>
1402
1403<p>The direct mapping provides more flexibility to the developer of
1404the register allocator; however, it is more error prone, and demands
1405more implementation work. Basically, the programmer will have to
1406specify where load and store instructions should be inserted in the
1407target function being compiled in order to get and store values in
1408memory. To assign a physical register to a virtual register present in
1409a given operand, use <tt>MachineOperand::setReg(p_reg)</tt>. To insert
1410a store instruction, use
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1411<tt>TargetRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
1412instruction, use <tt>TargetRegisterInfo::loadRegFromStackSlot</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1413
1414<p>The indirect mapping shields the application developer from the
1415complexities of inserting load and store instructions. In order to map
1416a virtual register to a physical one, use
1417<tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In order to map a
1418certain virtual register to memory, use
1419<tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will
1420return the stack slot where <tt>vreg</tt>'s value will be located. If
1421it is necessary to map another virtual register to the same stack
1422slot, use <tt>VirtRegMap::assignVirt2StackSlot(vreg,
1423stack_location)</tt>. One important point to consider when using the
1424indirect mapping, is that even if a virtual register is mapped to
1425memory, it still needs to be mapped to a physical register. This
1426physical register is the location where the virtual register is
1427supposed to be found before being stored or after being reloaded.</p>
1428
1429<p>If the indirect strategy is used, after all the virtual registers
1430have been mapped to physical registers or stack slots, it is necessary
1431to use a spiller object to place load and store instructions in the
1432code. Every virtual that has been mapped to a stack slot will be
1433stored to memory after been defined and will be loaded before being
1434used. The implementation of the spiller tries to recycle load/store
1435instructions, avoiding unnecessary instructions. For an example of how
1436to invoke the spiller, see
1437<tt>RegAllocLinearScan::runOnMachineFunction</tt> in
1438<tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
1439
1440</div>
1441
1442<!-- _______________________________________________________________________ -->
1443<div class="doc_subsubsection">
1444 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1445</div>
1446
1447<div class="doc_text">
1448
1449<p>With very rare exceptions (e.g., function calls), the LLVM machine
1450code instructions are three address instructions. That is, each
1451instruction is expected to define at most one register, and to use at
1452most two registers. However, some architectures use two address
1453instructions. In this case, the defined register is also one of the
1454used register. For instance, an instruction such as <tt>ADD %EAX,
1455%EBX</tt>, in X86 is actually equivalent to <tt>%EAX = %EAX +
1456%EBX</tt>.</p>
1457
1458<p>In order to produce correct code, LLVM must convert three address
1459instructions that represent two address instructions into true two
1460address instructions. LLVM provides the pass
1461<tt>TwoAddressInstructionPass</tt> for this specific purpose. It must
1462be run before register allocation takes place. After its execution,
1463the resulting code may no longer be in SSA form. This happens, for
1464instance, in situations where an instruction such as <tt>%a = ADD %b
1465%c</tt> is converted to two instructions such as:</p>
1466
1467<div class="doc_code">
1468<pre>
1469%a = MOVE %b
1470%a = ADD %a %b
1471</pre>
1472</div>
1473
1474<p>Notice that, internally, the second instruction is represented as
1475<tt>ADD %a[def/use] %b</tt>. I.e., the register operand <tt>%a</tt> is
1476both used and defined by the instruction.</p>
1477
1478</div>
1479
1480<!-- _______________________________________________________________________ -->
1481<div class="doc_subsubsection">
1482 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1483</div>
1484
1485<div class="doc_text">
1486
1487<p>An important transformation that happens during register allocation is called
1488the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many
1489analyses that are performed on the control flow graph of
1490programs. However, traditional instruction sets do not implement
1491PHI instructions. Thus, in order to generate executable code, compilers
1492must replace PHI instructions with other instructions that preserve their
1493semantics.</p>
1494
1495<p>There are many ways in which PHI instructions can safely be removed
1496from the target code. The most traditional PHI deconstruction
1497algorithm replaces PHI instructions with copy instructions. That is
1498the strategy adopted by LLVM. The SSA deconstruction algorithm is
1499implemented in n<tt>lib/CodeGen/>PHIElimination.cpp</tt>. In order to
1500invoke this pass, the identifier <tt>PHIEliminationID</tt> must be
1501marked as required in the code of the register allocator.</p>
1502
1503</div>
1504
1505<!-- _______________________________________________________________________ -->
1506<div class="doc_subsubsection">
1507 <a name="regAlloc_fold">Instruction folding</a>
1508</div>
1509
1510<div class="doc_text">
1511
1512<p><i>Instruction folding</i> is an optimization performed during
1513register allocation that removes unnecessary copy instructions. For
1514instance, a sequence of instructions such as:</p>
1515
1516<div class="doc_code">
1517<pre>
1518%EBX = LOAD %mem_address
1519%EAX = COPY %EBX
1520</pre>
1521</div>
1522
1523<p>can be safely substituted by the single instruction:
1524
1525<div class="doc_code">
1526<pre>
1527%EAX = LOAD %mem_address
1528</pre>
1529</div>
1530
1531<p>Instructions can be folded with the
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1532<tt>TargetRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1533taken when folding instructions; a folded instruction can be quite
1534different from the original instruction. See
1535<tt>LiveIntervals::addIntervalsForSpills</tt> in
1536<tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its use.</p>
1537
1538</div>
1539
1540<!-- _______________________________________________________________________ -->
1541
1542<div class="doc_subsubsection">
1543 <a name="regAlloc_builtIn">Built in register allocators</a>
1544</div>
1545
1546<div class="doc_text">
1547
1548<p>The LLVM infrastructure provides the application developer with
1549three different register allocators:</p>
1550
1551<ul>
1552 <li><i>Simple</i> - This is a very simple implementation that does
1553 not keep values in registers across instructions. This register
1554 allocator immediately spills every value right after it is
1555 computed, and reloads all used operands from memory to temporary
1556 registers before each instruction.</li>
1557 <li><i>Local</i> - This register allocator is an improvement on the
1558 <i>Simple</i> implementation. It allocates registers on a basic
1559 block level, attempting to keep values in registers and reusing
1560 registers as appropriate.</li>
1561 <li><i>Linear Scan</i> - <i>The default allocator</i>. This is the
1562 well-know linear scan register allocator. Whereas the
1563 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1564 implementation technique, the <i>Linear Scan</i> implementation
1565 uses a spiller in order to place load and stores.</li>
1566</ul>
1567
1568<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
1569command line option <tt>-regalloc=...</tt>:</p>
1570
1571<div class="doc_code">
1572<pre>
1573$ llc -f -regalloc=simple file.bc -o sp.s;
1574$ llc -f -regalloc=local file.bc -o lc.s;
1575$ llc -f -regalloc=linearscan file.bc -o ln.s;
1576</pre>
1577</div>
1578
1579</div>
1580
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1581<!-- ======================================================================= -->
1582<div class="doc_subsection">
1583 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1584</div>
1585<div class="doc_text"><p>To Be Written</p></div>
1586<!-- ======================================================================= -->
1587<div class="doc_subsection">
1588 <a name="latemco">Late Machine Code Optimizations</a>
1589</div>
1590<div class="doc_text"><p>To Be Written</p></div>
1591<!-- ======================================================================= -->
1592<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1593 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1594</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1595<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1596<!-- _______________________________________________________________________ -->
1597<div class="doc_subsubsection">
1598 <a name="codeemit_asm">Generating Assembly Code</a>
1599</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1600<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1601<!-- _______________________________________________________________________ -->
1602<div class="doc_subsubsection">
1603 <a name="codeemit_bin">Generating Binary Machine Code</a>
1604</div>
1605
1606<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1607 <p>For the JIT or <tt>.o</tt> file writer</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1608</div>
1609
1610
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1611<!-- *********************************************************************** -->
1612<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1613 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1614</div>
1615<!-- *********************************************************************** -->
1616
1617<div class="doc_text">
1618
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1619<p>This section of the document explains features or design decisions that
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1620are specific to the code generator for a particular target.</p>
1621
1622</div>
1623
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]1624<!-- ======================================================================= -->
1625<div class="doc_subsection">
1626 <a name="tailcallopt">Tail call optimization</a>
1627</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1628
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]1629<div class="doc_text">
1630 <p>Tail call optimization, callee reusing the stack of the caller, is currently supported on x86/x86-64 and PowerPC. It is performed if:
1631 <ul>
1632 <li>Caller and callee have the calling convention <tt>fastcc</tt>.</li>
1633 <li>The call is a tail call - in tail position (ret immediately follows call and ret uses value of call or is void).</li>
1634 <li>Option <tt>-tailcallopt</tt> is enabled.</li>
1635 <li>Platform specific constraints are met.</li>
1636 </ul>
1637 </p>
1638
1639 <p>x86/x86-64 constraints:
1640 <ul>
1641 <li>No variable argument lists are used.</li>
1642 <li>On x86-64 when generating GOT/PIC code only module-local calls (visibility = hidden or protected) are supported.</li>
1643 </ul>
1644 </p>
1645 <p>PowerPC constraints:
1646 <ul>
1647 <li>No variable argument lists are used.</li>
1648 <li>No byval parameters are used.</li>
1649 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
1650 </ul>
1651 </p>
1652 <p>Example:</p>
1653 <p>Call as <tt>llc -tailcallopt test.ll</tt>.
1654 <div class="doc_code">
1655 <pre>
1656declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
1657
1658define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
1659 %l1 = add i32 %in1, %in2
1660 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
1661 ret i32 %tmp
1662}</pre>
1663 </div>
1664 </p>
1665 <p>Implications of <tt>-tailcallopt</tt>:</p>
1666 <p>To support tail call optimization in situations where the callee has more arguments than the caller a 'callee pops arguments' convention is used. This currently causes each <tt>fastcc</tt> call that is not tail call optimized (because one or more of above constraints are not met) to be followed by a readjustment of the stack. So performance might be worse in such cases.</p>
1667 <p>On x86 and x86-64 one register is reserved for indirect tail calls (e.g via a function pointer). So there is one less register for integer argument passing. For x86 this means 2 registers (if <tt>inreg</tt> parameter attribute is used) and for x86-64 this means 5 register are used.</p>
1668</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1669<!-- ======================================================================= -->
1670<div class="doc_subsection">
1671 <a name="x86">The X86 backend</a>
1672</div>
1673
1674<div class="doc_text">
1675
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1676<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame]1677code generator is capable of targeting a variety of x86-32 and x86-64
1678processors, and includes support for ISA extensions such as MMX and SSE.
1679</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1680
1681</div>
1682
1683<!-- _______________________________________________________________________ -->
1684<div class="doc_subsubsection">
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1685 <a name="x86_tt">X86 Target Triples Supported</a>
1686</div>
1687
1688<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1689
1690<p>The following are the known target triples that are supported by the X86
1691backend. This is not an exhaustive list, and it would be useful to add those
1692that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1693
1694<ul>
1695<li><b>i686-pc-linux-gnu</b> - Linux</li>
1696<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1697<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1698<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1699<li><b>i386-pc-mingw32msvc</b> - MingW crosscompiler on Linux</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1700<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1701</ul>
1702
1703</div>
1704
1705<!-- _______________________________________________________________________ -->
1706<div class="doc_subsubsection">
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1707 <a name="x86_cc">X86 Calling Conventions supported</a>
1708</div>
1709
1710
1711<div class="doc_text">
1712
1713<p>The folowing target-specific calling conventions are known to backend:</p>
1714
1715<ul>
1716<li><b>x86_StdCall</b> - stdcall calling convention seen on Microsoft Windows
1717platform (CC ID = 64).</li>
1718<li><b>x86_FastCall</b> - fastcall calling convention seen on Microsoft Windows
1719platform (CC ID = 65).</li>
1720</ul>
1721
1722</div>
1723
1724<!-- _______________________________________________________________________ -->
1725<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1726 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1727</div>
1728
1729<div class="doc_text">
1730
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1731<p>The x86 has a very flexible way of accessing memory. It is capable of
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1732forming memory addresses of the following expression directly in integer
1733instructions (which use ModR/M addressing):</p>
1734
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1735<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1736<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1737Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1738</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1739</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1740
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1741<p>In order to represent this, LLVM tracks no less than 4 operands for each
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1742memory operand of this form. This means that the "load" form of '<tt>mov</tt>'
1743has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1744
1745<pre>
1746Index: 0 | 1 2 3 4
1747Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1748OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1749</pre>
1750
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1751<p>Stores, and all other instructions, treat the four memory operands in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1752same way and in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1753
1754</div>
1755
1756<!-- _______________________________________________________________________ -->
1757<div class="doc_subsubsection">
1758 <a name="x86_names">Instruction naming</a>
1759</div>
1760
1761<div class="doc_text">
1762
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1763<p>An instruction name consists of the base name, a default operand size, and a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1764a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1765
1766<p>
1767<tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>
1768<tt>IMUL16rmi</tt> -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1769<tt>IMUL16rmi8</tt> -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1770<tt>MOVSX32rm16</tt> -&gt; movsx, 32-bit register, 16-bit memory
1771</p>
1772
1773</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1774
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1775<!-- ======================================================================= -->
1776<div class="doc_subsection">
1777 <a name="ppc">The PowerPC backend</a>
1778</div>
1779
1780<div class="doc_text">
1781<p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
1782code generation is retargetable to several variations or <i>subtargets</i> of
1783the PowerPC ISA; including ppc32, ppc64 and altivec.
1784</p>
1785</div>
1786
1787<!-- _______________________________________________________________________ -->
1788<div class="doc_subsubsection">
1789 <a name="ppc_abi">LLVM PowerPC ABI</a>
1790</div>
1791
1792<div class="doc_text">
1793<p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
1794relative (PIC) or static addressing for accessing global values, so no TOC (r2)
1795is used. Second, r31 is used as a frame pointer to allow dynamic growth of a
1796stack frame. LLVM takes advantage of having no TOC to provide space to save
1797the frame pointer in the PowerPC linkage area of the caller frame. Other
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1798details of PowerPC ABI can be found at <a href=
1799"http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
1800>PowerPC ABI.</a> Note: This link describes the 32 bit ABI. The
180164 bit ABI is similar except space for GPRs are 8 bytes wide (not 4) and r13 is
1802reserved for system use.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1803</div>
1804
1805<!-- _______________________________________________________________________ -->
1806<div class="doc_subsubsection">
1807 <a name="ppc_frame">Frame Layout</a>
1808</div>
1809
1810<div class="doc_text">
1811<p>The size of a PowerPC frame is usually fixed for the duration of a
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1812function&rsquo;s invocation. Since the frame is fixed size, all references into
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1813the frame can be accessed via fixed offsets from the stack pointer. The
1814exception to this is when dynamic alloca or variable sized arrays are present,
1815then a base pointer (r31) is used as a proxy for the stack pointer and stack
1816pointer is free to grow or shrink. A base pointer is also used if llvm-gcc is
1817not passed the -fomit-frame-pointer flag. The stack pointer is always aligned to
181816 bytes, so that space allocated for altivec vectors will be properly
1819aligned.</p>
1820<p>An invocation frame is layed out as follows (low memory at top);</p>
1821</div>
1822
1823<div class="doc_text">
1824<table class="layout">
1825 <tr>
1826 <td>Linkage<br><br></td>
1827 </tr>
1828 <tr>
1829 <td>Parameter area<br><br></td>
1830 </tr>
1831 <tr>
1832 <td>Dynamic area<br><br></td>
1833 </tr>
1834 <tr>
1835 <td>Locals area<br><br></td>
1836 </tr>
1837 <tr>
1838 <td>Saved registers area<br><br></td>
1839 </tr>
1840 <tr style="border-style: none hidden none hidden;">
1841 <td><br></td>
1842 </tr>
1843 <tr>
1844 <td>Previous Frame<br><br></td>
1845 </tr>
1846</table>
1847</div>
1848
1849<div class="doc_text">
1850<p>The <i>linkage</i> area is used by a callee to save special registers prior
1851to allocating its own frame. Only three entries are relevant to LLVM. The
1852first entry is the previous stack pointer (sp), aka link. This allows probing
1853tools like gdb or exception handlers to quickly scan the frames in the stack. A
1854function epilog can also use the link to pop the frame from the stack. The
1855third entry in the linkage area is used to save the return address from the lr
1856register. Finally, as mentioned above, the last entry is used to save the
1857previous frame pointer (r31.) The entries in the linkage area are the size of a
1858GPR, thus the linkage area is 24 bytes long in 32 bit mode and 48 bytes in 64
1859bit mode.</p>
1860</div>
1861
1862<div class="doc_text">
1863<p>32 bit linkage area</p>
1864<table class="layout">
1865 <tr>
1866 <td>0</td>
1867 <td>Saved SP (r1)</td>
1868 </tr>
1869 <tr>
1870 <td>4</td>
1871 <td>Saved CR</td>
1872 </tr>
1873 <tr>
1874 <td>8</td>
1875 <td>Saved LR</td>
1876 </tr>
1877 <tr>
1878 <td>12</td>
1879 <td>Reserved</td>
1880 </tr>
1881 <tr>
1882 <td>16</td>
1883 <td>Reserved</td>
1884 </tr>
1885 <tr>
1886 <td>20</td>
1887 <td>Saved FP (r31)</td>
1888 </tr>
1889</table>
1890</div>
1891
1892<div class="doc_text">
1893<p>64 bit linkage area</p>
1894<table class="layout">
1895 <tr>
1896 <td>0</td>
1897 <td>Saved SP (r1)</td>
1898 </tr>
1899 <tr>
1900 <td>8</td>
1901 <td>Saved CR</td>
1902 </tr>
1903 <tr>
1904 <td>16</td>
1905 <td>Saved LR</td>
1906 </tr>
1907 <tr>
1908 <td>24</td>
1909 <td>Reserved</td>
1910 </tr>
1911 <tr>
1912 <td>32</td>
1913 <td>Reserved</td>
1914 </tr>
1915 <tr>
1916 <td>40</td>
1917 <td>Saved FP (r31)</td>
1918 </tr>
1919</table>
1920</div>
1921
1922<div class="doc_text">
1923<p>The <i>parameter area</i> is used to store arguments being passed to a callee
1924function. Following the PowerPC ABI, the first few arguments are actually
1925passed in registers, with the space in the parameter area unused. However, if
1926there are not enough registers or the callee is a thunk or vararg function,
1927these register arguments can be spilled into the parameter area. Thus, the
1928parameter area must be large enough to store all the parameters for the largest
1929call sequence made by the caller. The size must also be mimimally large enough
1930to spill registers r3-r10. This allows callees blind to the call signature,
1931such as thunks and vararg functions, enough space to cache the argument
1932registers. Therefore, the parameter area is minimally 32 bytes (64 bytes in 64
1933bit mode.) Also note that since the parameter area is a fixed offset from the
1934top of the frame, that a callee can access its spilt arguments using fixed
1935offsets from the stack pointer (or base pointer.)</p>
1936</div>
1937
1938<div class="doc_text">
1939<p>Combining the information about the linkage, parameter areas and alignment. A
1940stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
1941mode.</p>
1942</div>
1943
1944<div class="doc_text">
1945<p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
1946alloca then space is added to the stack, the linkage and parameter areas are
1947shifted to top of stack, and the new space is available immediately below the
1948linkage and parameter areas. The cost of shifting the linkage and parameter
1949areas is minor since only the link value needs to be copied. The link value can
1950be easily fetched by adding the original frame size to the base pointer. Note
1951that allocations in the dynamic space need to observe 16 byte aligment.</p>
1952</div>
1953
1954<div class="doc_text">
1955<p>The <i>locals area</i> is where the llvm compiler reserves space for local
1956variables.</p>
1957</div>
1958
1959<div class="doc_text">
1960<p>The <i>saved registers area</i> is where the llvm compiler spills callee saved
1961registers on entry to the callee.</p>
1962</div>
1963
1964<!-- _______________________________________________________________________ -->
1965<div class="doc_subsubsection">
1966 <a name="ppc_prolog">Prolog/Epilog</a>
1967</div>
1968
1969<div class="doc_text">
1970<p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
1971the following exceptions. Callee saved registers are spilled after the frame is
1972created. This allows the llvm epilog/prolog support to be common with other
1973targets. The base pointer callee saved register r31 is saved in the TOC slot of
1974linkage area. This simplifies allocation of space for the base pointer and
1975makes it convenient to locate programatically and during debugging.</p>
1976</div>
1977
1978<!-- _______________________________________________________________________ -->
1979<div class="doc_subsubsection">
1980 <a name="ppc_dynamic">Dynamic Allocation</a>
1981</div>
1982
1983<div class="doc_text">
1984<p></p>
1985</div>
1986
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1987<div class="doc_text">
1988<p><i>TODO - More to come.</i></p>
1989</div>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1990
1991
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1992<!-- *********************************************************************** -->
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1999
2000 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]2001 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
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