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Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]6 <title>The LLVM Target-Independent Code Generator</title>
7 <link rel="stylesheet" href="llvm.css" type="text/css">
8</head>
9<body>
10
11<div class="doc_title">
12 The LLVM Target-Independent Code Generator
13</div>
14
15<ol>
16 <li><a href="#introduction">Introduction</a>
17 <ul>
18 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]19 <li><a href="#high-level-design">The high-level design of the code
20 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]21 <li><a href="#tablegen">Using TableGen for target description</a></li>
22 </ul>
23 </li>
24 <li><a href="#targetdesc">Target description classes</a>
25 <ul>
26 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
27 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]28 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]29 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
30 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
31 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]32 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]33 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
34 </ul>
35 </li>
36 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]37 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]38 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]39 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
40 class</a></li>
41 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]42 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]43 </li>
44 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]45 <ul>
46 <li><a href="#instselect">Instruction Selection</a>
47 <ul>
48 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
49 <li><a href="#selectiondag_process">SelectionDAG Code Generation
50 Process</a></li>
51 <li><a href="#selectiondag_build">Initial SelectionDAG
52 Construction</a></li>
53 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
54 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]55 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]56 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]57 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]58 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]59 <li><a href="#selectiondag_future">Future directions for the
60 SelectionDAG</a></li>
61 </ul></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]62 <li><a href="#liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]63 <ul>
64 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]65 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]66 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]67 <li><a href="#regalloc">Register Allocation</a>
68 <ul>
69 <li><a href="#regAlloc_represent">How registers are represented in
70 LLVM</a></li>
71 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
72 registers</a></li>
73 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
74 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
75 <li><a href="#regAlloc_fold">Instruction folding</a></li>
76 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
77 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]78 <li><a href="#codeemit">Code Emission</a>
79 <ul>
80 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
81 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
82 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]83 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]84 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]85 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]86 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]87 <li><a href="#x86">The X86 backend</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]88 <li><a href="#ppc">The PowerPC backend</a>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]89 <ul>
90 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
91 <li><a href="#ppc_frame">Frame Layout</a></li>
92 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
93 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]94 </ul></li>
95 </ul></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]96
97</ol>
98
99<div class="doc_author">
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]100 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a>,
Jim Laskeyd201f4e2007-03-14 19:30:33 +0000[diff] [blame]101 <a href="mailto:isanbard@gmail.com">Bill Wendling</a>,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]102 <a href="mailto:pronesto@gmail.com">Fernando Magno Quintao
Jim Laskeyd201f4e2007-03-14 19:30:33 +0000[diff] [blame]103 Pereira</a> and
104 <a href="mailto:jlaskey@mac.com">Jim Laskey</a></p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]105</div>
106
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]107<div class="doc_warning">
108 <p>Warning: This is a work in progress.</p>
109</div>
110
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]111<!-- *********************************************************************** -->
112<div class="doc_section">
113 <a name="introduction">Introduction</a>
114</div>
115<!-- *********************************************************************** -->
116
117<div class="doc_text">
118
119<p>The LLVM target-independent code generator is a framework that provides a
120suite of reusable components for translating the LLVM internal representation to
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]121the machine code for a specified target&mdash;either in assembly form (suitable
122for a static compiler) or in binary machine code format (usable for a JIT
123compiler). The LLVM target-independent code generator consists of five main
124components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]125
126<ol>
127<li><a href="#targetdesc">Abstract target description</a> interfaces which
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]128capture important properties about various aspects of the machine, independently
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]129of how they will be used. These interfaces are defined in
130<tt>include/llvm/Target/</tt>.</li>
131
132<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]133generated for a target. These classes are intended to be abstract enough to
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]134represent the machine code for <i>any</i> target machine. These classes are
135defined in <tt>include/llvm/CodeGen/</tt>.</li>
136
137<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
138various phases of native code generation (register allocation, scheduling, stack
139frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
140
141<li><a href="#targetimpls">Implementations of the abstract target description
142interfaces</a> for particular targets. These machine descriptions make use of
143the components provided by LLVM, and can optionally provide custom
144target-specific passes, to build complete code generators for a specific target.
145Target descriptions live in <tt>lib/Target/</tt>.</li>
146
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]147<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
148completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
149interface for target-specific issues. The code for the target-independent
150JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
151
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]152</ol>
153
154<p>
155Depending on which part of the code generator you are interested in working on,
156different pieces of this will be useful to you. In any case, you should be
157familiar with the <a href="#targetdesc">target description</a> and <a
158href="#codegendesc">machine code representation</a> classes. If you want to add
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]159a backend for a new target, you will need to <a href="#targetimpls">implement the
160target description</a> classes for your new target and understand the <a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]161href="LangRef.html">LLVM code representation</a>. If you are interested in
162implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
163should only depend on the target-description and machine code representation
164classes, ensuring that it is portable.
165</p>
166
167</div>
168
169<!-- ======================================================================= -->
170<div class="doc_subsection">
171 <a name="required">Required components in the code generator</a>
172</div>
173
174<div class="doc_text">
175
176<p>The two pieces of the LLVM code generator are the high-level interface to the
177code generator and the set of reusable components that can be used to build
178target-specific backends. The two most important interfaces (<a
179href="#targetmachine"><tt>TargetMachine</tt></a> and <a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]180href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]181required to be defined for a backend to fit into the LLVM system, but the others
182must be defined if the reusable code generator components are going to be
183used.</p>
184
185<p>This design has two important implications. The first is that LLVM can
186support completely non-traditional code generation targets. For example, the C
187backend does not require register allocation, instruction selection, or any of
188the other standard components provided by the system. As such, it only
189implements these two interfaces, and does its own thing. Another example of a
190code generator like this is a (purely hypothetical) backend that converts LLVM
191to the GCC RTL form and uses GCC to emit machine code for a target.</p>
192
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]193<p>This design also implies that it is possible to design and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]194implement radically different code generators in the LLVM system that do not
195make use of any of the built-in components. Doing so is not recommended at all,
196but could be required for radically different targets that do not fit into the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]197LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]198
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]199</div>
200
201<!-- ======================================================================= -->
202<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]203 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]204</div>
205
206<div class="doc_text">
207
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]208<p>The LLVM target-independent code generator is designed to support efficient and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]209quality code generation for standard register-based microprocessors. Code
210generation in this model is divided into the following stages:</p>
211
212<ol>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]213<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
214determines an efficient way to express the input LLVM code in the target
215instruction set.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]216This stage produces the initial code for the program in the target instruction
217set, then makes use of virtual registers in SSA form and physical registers that
218represent any required register assignments due to target constraints or calling
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]219conventions. This step turns the LLVM code into a DAG of target
220instructions.</li>
221
222<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
223phase takes the DAG of target instructions produced by the instruction selection
224phase, determines an ordering of the instructions, then emits the instructions
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]225as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
226that we describe this in the <a href="#instselect">instruction selection
227section</a> because it operates on a <a
228href="#selectiondag_intro">SelectionDAG</a>.
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]229</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]230
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]231<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
232optional stage consists of a series of machine-code optimizations that
233operate on the SSA-form produced by the instruction selector. Optimizations
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]234like modulo-scheduling or peephole optimization work here.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]235</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]236
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]237<li><b><a href="#regalloc">Register Allocation</a></b> - The
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]238target code is transformed from an infinite virtual register file in SSA form
239to the concrete register file used by the target. This phase introduces spill
240code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]241
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]242<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]243machine code has been generated for the function and the amount of stack space
244required is known (used for LLVM alloca's and spill slots), the prolog and
245epilog code for the function can be inserted and "abstract stack location
246references" can be eliminated. This stage is responsible for implementing
247optimizations like frame-pointer elimination and stack packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]248
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]249<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]250that operate on "final" machine code can go here, such as spill code scheduling
251and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]252
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]253<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]254puts out the code for the current function, either in the target assembler
255format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]256
257</ol>
258
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]259<p>The code generator is based on the assumption that the instruction selector
260will use an optimal pattern matching selector to create high-quality sequences of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]261native instructions. Alternative code generator designs based on pattern
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]262expansion and aggressive iterative peephole optimization are much slower. This
263design permits efficient compilation (important for JIT environments) and
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]264aggressive optimization (used when generating code offline) by allowing
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]265components of varying levels of sophistication to be used for any step of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]266compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]267
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]268<p>In addition to these stages, target implementations can insert arbitrary
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]269target-specific passes into the flow. For example, the X86 target uses a
270special pass to handle the 80x87 floating point stack architecture. Other
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]271targets with unusual requirements can be supported with custom passes as
272needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]273
274</div>
275
276
277<!-- ======================================================================= -->
278<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]279 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]280</div>
281
282<div class="doc_text">
283
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]284<p>The target description classes require a detailed description of the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]285architecture. These target descriptions often have a large amount of common
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]286information (e.g., an <tt>add</tt> instruction is almost identical to a
287<tt>sub</tt> instruction).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]288In order to allow the maximum amount of commonality to be factored out, the LLVM
289code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]290describe big chunks of the target machine, which allows the use of
291domain-specific and target-specific abstractions to reduce the amount of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]292repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]293
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]294<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]295of the target description to the <tt>.td</tt> form. Doing so gives us a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]296number of advantages. The most important is that it makes it easier to port
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]297LLVM because it reduces the amount of C++ code that has to be written, and the
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]298surface area of the code generator that needs to be understood before someone
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]299can get something working. Second, it makes it easier to change things. In
300particular, if tables and other things are all emitted by <tt>tblgen</tt>, we
301only need a change in one place (<tt>tblgen</tt>) to update all of the targets
302to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]303
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]304</div>
305
306<!-- *********************************************************************** -->
307<div class="doc_section">
308 <a name="targetdesc">Target description classes</a>
309</div>
310<!-- *********************************************************************** -->
311
312<div class="doc_text">
313
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]314<p>The LLVM target description classes (located in the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]315<tt>include/llvm/Target</tt> directory) provide an abstract description of the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]316target machine independent of any particular client. These classes are
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]317designed to capture the <i>abstract</i> properties of the target (such as the
318instructions and registers it has), and do not incorporate any particular pieces
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]319of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]320
321<p>All of the target description classes (except the <tt><a
322href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
323the concrete target implementation, and have virtual methods implemented. To
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]324get to these implementations, the <tt><a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]325href="#targetmachine">TargetMachine</a></tt> class provides accessors that
326should be implemented by the target.</p>
327
328</div>
329
330<!-- ======================================================================= -->
331<div class="doc_subsection">
332 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
333</div>
334
335<div class="doc_text">
336
337<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
338access the target-specific implementations of the various target description
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]339classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
340<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
341designed to be specialized by
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]342a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
343implements the various virtual methods. The only required target description
344class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
345code generator components are to be used, the other interfaces should be
346implemented as well.</p>
347
348</div>
349
350
351<!-- ======================================================================= -->
352<div class="doc_subsection">
353 <a name="targetdata">The <tt>TargetData</tt> class</a>
354</div>
355
356<div class="doc_text">
357
358<p>The <tt>TargetData</tt> class is the only required target description class,
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]359and it is the only class that is not extensible (you cannot derived a new
360class from it). <tt>TargetData</tt> specifies information about how the target
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]361lays out memory for structures, the alignment requirements for various data
362types, the size of pointers in the target, and whether the target is
363little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]364
365</div>
366
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]367<!-- ======================================================================= -->
368<div class="doc_subsection">
369 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
370</div>
371
372<div class="doc_text">
373
374<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
375selectors primarily to describe how LLVM code should be lowered to SelectionDAG
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]376operations. Among other things, this class indicates:</p>
377
378<ul>
379 <li>an initial register class to use for various <tt>ValueType</tt>s</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]380 <li>which operations are natively supported by the target machine</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]381 <li>the return type of <tt>setcc</tt> operations</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]382 <li>the type to use for shift amounts</li>
383 <li>various high-level characteristics, like whether it is profitable to turn
384 division by a constant into a multiplication sequence</li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]385</ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]386
387</div>
388
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]389<!-- ======================================================================= -->
390<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]391 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]392</div>
393
394<div class="doc_text">
395
396<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
397<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
398target and any interactions between the registers.</p>
399
400<p>Registers in the code generator are represented in the code generator by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]401unsigned integers. Physical registers (those that actually exist in the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]402description) are unique small numbers, and virtual registers are generally
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]403large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]404
405<p>Each register in the processor description has an associated
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]406<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
407register (used for assembly output and debugging dumps) and a set of aliases
408(used to indicate whether one register overlaps with another).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]409</p>
410
411<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
412exposes a set of processor specific register classes (instances of the
413<tt>TargetRegisterClass</tt> class). Each register class contains sets of
414registers that have the same properties (for example, they are all 32-bit
415integer registers). Each SSA virtual register created by the instruction
416selector has an associated register class. When the register allocator runs, it
417replaces virtual registers with a physical register in the set.</p>
418
419<p>
420The target-specific implementations of these classes is auto-generated from a <a
421href="TableGenFundamentals.html">TableGen</a> description of the register file.
422</p>
423
424</div>
425
426<!-- ======================================================================= -->
427<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]428 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]429</div>
430
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]431<div class="doc_text">
432 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
433 instructions supported by the target. It is essentially an array of
434 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
435 instruction the target supports. Descriptors define things like the mnemonic
Chris Lattnera3079782005-07-19 03:37:48 +0000[diff] [blame]436 for the opcode, the number of operands, the list of implicit register uses
437 and defs, whether the instruction has certain target-independent properties
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]438 (accesses memory, is commutable, etc), and holds any target-specific
439 flags.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]440</div>
441
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]442<!-- ======================================================================= -->
443<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]444 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]445</div>
446
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]447<div class="doc_text">
448 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
449 stack frame layout of the target. It holds the direction of stack growth,
450 the known stack alignment on entry to each function, and the offset to the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]451 local area. The offset to the local area is the offset from the stack
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]452 pointer on function entry to the first location where function data (local
453 variables, spill locations) can be stored.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]454</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]455
456<!-- ======================================================================= -->
457<div class="doc_subsection">
458 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
459</div>
460
461<div class="doc_text">
Jim Laskey82d61a12005-10-17 12:19:10 +0000[diff] [blame]462 <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
463 specific chip set being targeted. A sub-target informs code generation of
464 which instructions are supported, instruction latencies and instruction
465 execution itinerary; i.e., which processing units are used, in what order, and
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]466 for how long.</p>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]467</div>
468
469
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]470<!-- ======================================================================= -->
471<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]472 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]473</div>
474
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]475<div class="doc_text">
476 <p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
477 Just-In-Time code generator to perform target-specific activities, such as
478 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
479 should provide one of these objects through the <tt>getJITInfo</tt>
480 method.</p>
481</div>
482
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]483<!-- *********************************************************************** -->
484<div class="doc_section">
485 <a name="codegendesc">Machine code description classes</a>
486</div>
487<!-- *********************************************************************** -->
488
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]489<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]490
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]491<p>At the high-level, LLVM code is translated to a machine specific
492representation formed out of
493<a href="#machinefunction"><tt>MachineFunction</tt></a>,
494<a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>, and <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]495href="#machineinstr"><tt>MachineInstr</tt></a> instances
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]496(defined in <tt>include/llvm/CodeGen</tt>). This representation is completely
497target agnostic, representing instructions in their most abstract form: an
498opcode and a series of operands. This representation is designed to support
499both an SSA representation for machine code, as well as a register allocated,
500non-SSA form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]501
502</div>
503
504<!-- ======================================================================= -->
505<div class="doc_subsection">
506 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
507</div>
508
509<div class="doc_text">
510
511<p>Target machine instructions are represented as instances of the
512<tt>MachineInstr</tt> class. This class is an extremely abstract way of
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]513representing machine instructions. In particular, it only keeps track of
514an opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]515
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]516<p>The opcode number is a simple unsigned integer that only has meaning to a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]517specific backend. All of the instructions for a target should be defined in
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]518the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]519are auto-generated from this description. The <tt>MachineInstr</tt> class does
520not have any information about how to interpret the instruction (i.e., what the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]521semantics of the instruction are); for that you must refer to the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]522<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
523
524<p>The operands of a machine instruction can be of several different types:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]525a register reference, a constant integer, a basic block reference, etc. In
526addition, a machine operand should be marked as a def or a use of the value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]527(though only registers are allowed to be defs).</p>
528
529<p>By convention, the LLVM code generator orders instruction operands so that
530all register definitions come before the register uses, even on architectures
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]531that are normally printed in other orders. For example, the SPARC add
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]532instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
533and stores the result into the "%i3" register. In the LLVM code generator,
534the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
535first.</p>
536
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]537<p>Keeping destination (definition) operands at the beginning of the operand
538list has several advantages. In particular, the debugging printer will print
539the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]540
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]541<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]542<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]543%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]544</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]545</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]546
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]547<p>Also if the first operand is a def, it is easier to <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]548href="#buildmi">create instructions</a> whose only def is the first
549operand.</p>
550
551</div>
552
553<!-- _______________________________________________________________________ -->
554<div class="doc_subsubsection">
555 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
556</div>
557
558<div class="doc_text">
559
560<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
561located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
562<tt>BuildMI</tt> functions make it easy to build arbitrary machine
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]563instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]564
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]565<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]566<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]567// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
568// instruction. The '1' specifies how many operands will be added.
569MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]570
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]571// Create the same instr, but insert it at the end of a basic block.
572MachineBasicBlock &amp;MBB = ...
573BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]574
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]575// Create the same instr, but insert it before a specified iterator point.
576MachineBasicBlock::iterator MBBI = ...
577BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]578
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]579// Create a 'cmp Reg, 0' instruction, no destination reg.
580MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
581// Create an 'sahf' instruction which takes no operands and stores nothing.
582MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]583
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]584// Create a self looping branch instruction.
585BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]586</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]587</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]588
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]589<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
590have to specify the number of operands that the machine instruction will take.
591This allows for efficient memory allocation. You also need to specify if
592operands default to be uses of values, not definitions. If you need to add a
593definition operand (other than the optional destination register), you must
594explicitly mark it as such:</p>
595
596<div class="doc_code">
597<pre>
598MI.addReg(Reg, MachineOperand::Def);
599</pre>
600</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]601
602</div>
603
604<!-- _______________________________________________________________________ -->
605<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]606 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]607</div>
608
609<div class="doc_text">
610
611<p>One important issue that the code generator needs to be aware of is the
612presence of fixed registers. In particular, there are often places in the
613instruction stream where the register allocator <em>must</em> arrange for a
614particular value to be in a particular register. This can occur due to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]615limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]616with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
617conventions. In any case, the instruction selector should emit code that
618copies a virtual register into or out of a physical register when needed.</p>
619
620<p>For example, consider this simple LLVM example:</p>
621
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]622<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]623<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]624int %test(int %X, int %Y) {
625 %Z = div int %X, %Y
626 ret int %Z
627}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]628</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]629</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]630
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]631<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
632and <tt>ret</tt> (use
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]633"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
634
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]635<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]636<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]637;; Start of div
638%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
639%reg1027 = sar %reg1024, 31
640%EDX = mov %reg1027 ;; Sign extend X into EDX
641idiv %reg1025 ;; Divide by Y (in reg1025)
642%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]643
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]644;; Start of ret
645%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
646ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]647</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]648</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]649
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]650<p>By the end of code generation, the register allocator has coalesced
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]651the registers and deleted the resultant identity moves producing the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]652following code:</p>
653
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]654<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]655<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]656;; X is in EAX, Y is in ECX
657mov %EAX, %EDX
658sar %EDX, 31
659idiv %ECX
660ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]661</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]662</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]663
664<p>This approach is extremely general (if it can handle the X86 architecture,
665it can handle anything!) and allows all of the target specific
666knowledge about the instruction stream to be isolated in the instruction
667selector. Note that physical registers should have a short lifetime for good
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]668code generation, and all physical registers are assumed dead on entry to and
669exit from basic blocks (before register allocation). Thus, if you need a value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]670to be live across basic block boundaries, it <em>must</em> live in a virtual
671register.</p>
672
673</div>
674
675<!-- _______________________________________________________________________ -->
676<div class="doc_subsubsection">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]677 <a name="ssa">Machine code in SSA form</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]678</div>
679
680<div class="doc_text">
681
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]682<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]683are maintained in SSA-form until register allocation happens. For the most
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]684part, this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]685become machine code PHI nodes, and virtual registers are only allowed to have a
686single definition.</p>
687
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]688<p>After register allocation, machine code is no longer in SSA-form because there
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]689are no virtual registers left in the code.</p>
690
691</div>
692
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]693<!-- ======================================================================= -->
694<div class="doc_subsection">
695 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
696</div>
697
698<div class="doc_text">
699
700<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]701(<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
702corresponds to the LLVM code input to the instruction selector, but there can be
703a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
704basic blocks). The <tt>MachineBasicBlock</tt> class has a
705"<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
706comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]707
708</div>
709
710<!-- ======================================================================= -->
711<div class="doc_subsection">
712 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
713</div>
714
715<div class="doc_text">
716
717<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]718(<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
719corresponds one-to-one with the LLVM function input to the instruction selector.
720In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
721a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
722<tt>MachineFunctionInfo</tt>, a <tt>SSARegMap</tt>, and a set of live in and
723live out registers for the function. See
724<tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]725
726</div>
727
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]728<!-- *********************************************************************** -->
729<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]730 <a name="codegenalgs">Target-independent code generation algorithms</a>
731</div>
732<!-- *********************************************************************** -->
733
734<div class="doc_text">
735
736<p>This section documents the phases described in the <a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]737href="#high-level-design">high-level design of the code generator</a>. It
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]738explains how they work and some of the rationale behind their design.</p>
739
740</div>
741
742<!-- ======================================================================= -->
743<div class="doc_subsection">
744 <a name="instselect">Instruction Selection</a>
745</div>
746
747<div class="doc_text">
748<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]749Instruction Selection is the process of translating LLVM code presented to the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]750code generator into target-specific machine instructions. There are several
Evan Cheng77949352007-10-08 17:54:24 +0000[diff] [blame]751well-known ways to do this in the literature. LLVM uses a SelectionDAG based
752instruction selector.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]753</p>
754
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]755<p>Portions of the DAG instruction selector are generated from the target
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]756description (<tt>*.td</tt>) files. Our goal is for the entire instruction
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame^]757selector to be generated from these <tt>.td</tt> files, though currently
758there are still things that require custom C++ code.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]759</div>
760
761<!-- _______________________________________________________________________ -->
762<div class="doc_subsubsection">
763 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
764</div>
765
766<div class="doc_text">
767
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]768<p>The SelectionDAG provides an abstraction for code representation in a way
769that is amenable to instruction selection using automatic techniques
770(e.g. dynamic-programming based optimal pattern matching selectors). It is also
771well-suited to other phases of code generation; in particular,
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]772instruction scheduling (SelectionDAG's are very close to scheduling DAGs
773post-selection). Additionally, the SelectionDAG provides a host representation
774where a large variety of very-low-level (but target-independent)
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]775<a href="#selectiondag_optimize">optimizations</a> may be
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]776performed; ones which require extensive information about the instructions
777efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]778
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]779<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]780<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]781operation code (Opcode) that indicates what operation the node performs and
782the operands to the operation.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]783The various operation node types are described at the top of the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]784<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]785
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]786<p>Although most operations define a single value, each node in the graph may
787define multiple values. For example, a combined div/rem operation will define
788both the dividend and the remainder. Many other situations require multiple
789values as well. Each node also has some number of operands, which are edges
790to the node defining the used value. Because nodes may define multiple values,
791edges are represented by instances of the <tt>SDOperand</tt> class, which is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]792a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node and result
793value being used, respectively. Each value produced by an <tt>SDNode</tt> has
794an associated <tt>MVT::ValueType</tt> indicating what type the value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]795
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]796<p>SelectionDAGs contain two different kinds of values: those that represent
797data flow and those that represent control flow dependencies. Data values are
798simple edges with an integer or floating point value type. Control edges are
799represented as "chain" edges which are of type <tt>MVT::Other</tt>. These edges
800provide an ordering between nodes that have side effects (such as
801loads, stores, calls, returns, etc). All nodes that have side effects should
802take a token chain as input and produce a new one as output. By convention,
803token chain inputs are always operand #0, and chain results are always the last
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]804value produced by an operation.</p>
805
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]806<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
807always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root node
808is the final side-effecting node in the token chain. For example, in a single
809basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]810
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]811<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
812"illegal" DAG. A legal DAG for a target is one that only uses supported
813operations and supported types. On a 32-bit PowerPC, for example, a DAG with
814a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that uses a
815SREM or UREM operation. The
816<a href="#selectiondag_legalize">legalize</a> phase is responsible for turning
817an illegal DAG into a legal DAG.</p>
818
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]819</div>
820
821<!-- _______________________________________________________________________ -->
822<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]823 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]824</div>
825
826<div class="doc_text">
827
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]828<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]829
830<ol>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]831<li><a href="#selectiondag_build">Build initial DAG</a> - This stage
832 performs a simple translation from the input LLVM code to an illegal
833 SelectionDAG.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]834<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]835 performs simple optimizations on the SelectionDAG to simplify it, and
836 recognize meta instructions (like rotates and <tt>div</tt>/<tt>rem</tt>
837 pairs) for targets that support these meta operations. This makes the
838 resultant code more efficient and the <a href="#selectiondag_select">select
839 instructions from DAG</a> phase (below) simpler.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]840<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]841 converts the illegal SelectionDAG to a legal SelectionDAG by eliminating
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]842 unsupported operations and data types.</li>
843<li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]844 second run of the SelectionDAG optimizes the newly legalized DAG to
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]845 eliminate inefficiencies introduced by legalization.</li>
846<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
847 the target instruction selector matches the DAG operations to target
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]848 instructions. This process translates the target-independent input DAG into
849 another DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]850<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]851 - The last phase assigns a linear order to the instructions in the
852 target-instruction DAG and emits them into the MachineFunction being
853 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]854</ol>
855
856<p>After all of these steps are complete, the SelectionDAG is destroyed and the
857rest of the code generation passes are run.</p>
858
Chris Lattnerdf921f02005-10-17 01:40:33 +0000[diff] [blame]859<p>One great way to visualize what is going on here is to take advantage of a
860few LLC command line options. In particular, the <tt>-view-isel-dags</tt>
861option pops up a window with the SelectionDAG input to the Select phase for all
862of the code compiled (if you only get errors printed to the console while using
863this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
864your system</a> to add support for it). The <tt>-view-sched-dags</tt> option
865views the SelectionDAG output from the Select phase and input to the Scheduler
Dan Gohmane9bb13d2007-10-15 21:07:59 +0000[diff] [blame]866phase. The <tt>-view-sunit-dags</tt> option views the ScheduleDAG, which is
867based on the final SelectionDAG, with nodes that must be scheduled as a unit
868bundled together into a single node, and with immediate operands and other
869nodes that aren't relevent for scheduling omitted.
870</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]871
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]872</div>
873
874<!-- _______________________________________________________________________ -->
875<div class="doc_subsubsection">
876 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
877</div>
878
879<div class="doc_text">
880
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]881<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
882input by the <tt>SelectionDAGLowering</tt> class in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]883<tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of this
884pass is to expose as much low-level, target-specific details to the SelectionDAG
885as possible. This pass is mostly hard-coded (e.g. an LLVM <tt>add</tt> turns
886into an <tt>SDNode add</tt> while a <tt>geteelementptr</tt> is expanded into the
887obvious arithmetic). This pass requires target-specific hooks to lower calls,
888returns, varargs, etc. For these features, the
889<tt><a href="#targetlowering">TargetLowering</a></tt> interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]890
891</div>
892
893<!-- _______________________________________________________________________ -->
894<div class="doc_subsubsection">
895 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
896</div>
897
898<div class="doc_text">
899
900<p>The Legalize phase is in charge of converting a DAG to only use the types and
901operations that are natively supported by the target. This involves two major
902tasks:</p>
903
904<ol>
905<li><p>Convert values of unsupported types to values of supported types.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]906 <p>There are two main ways of doing this: converting small types to
907 larger types ("promoting"), and breaking up large integer types
908 into smaller ones ("expanding"). For example, a target might require
909 that all f32 values are promoted to f64 and that all i1/i8/i16 values
910 are promoted to i32. The same target might require that all i64 values
911 be expanded into i32 values. These changes can insert sign and zero
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]912 extensions as needed to make sure that the final code has the same
913 behavior as the input.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]914 <p>A target implementation tells the legalizer which types are supported
915 (and which register class to use for them) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]916 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]917</li>
918
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]919<li><p>Eliminate operations that are not supported by the target.</p>
920 <p>Targets often have weird constraints, such as not supporting every
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]921 operation on every supported datatype (e.g. X86 does not support byte
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]922 conditional moves and PowerPC does not support sign-extending loads from
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]923 a 16-bit memory location). Legalize takes care of this by open-coding
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]924 another sequence of operations to emulate the operation ("expansion"), by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]925 promoting one type to a larger type that supports the operation
926 ("promotion"), or by using a target-specific hook to implement the
927 legalization ("custom").</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]928 <p>A target implementation tells the legalizer which operations are not
929 supported (and which of the above three actions to take) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]930 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
931 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]932</li>
933</ol>
934
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]935<p>Prior to the existance of the Legalize pass, we required that every target
936<a href="#selectiondag_optimize">selector</a> supported and handled every
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]937operator and type even if they are not natively supported. The introduction of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]938the Legalize phase allows all of the cannonicalization patterns to be shared
939across targets, and makes it very easy to optimize the cannonicalized code
940because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]941
942</div>
943
944<!-- _______________________________________________________________________ -->
945<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]946 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
947 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]948</div>
949
950<div class="doc_text">
951
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]952<p>The SelectionDAG optimization phase is run twice for code generation: once
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]953immediately after the DAG is built and once after legalization. The first run
954of the pass allows the initial code to be cleaned up (e.g. performing
955optimizations that depend on knowing that the operators have restricted type
956inputs). The second run of the pass cleans up the messy code generated by the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]957Legalize pass, which allows Legalize to be very simple (it can focus on making
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]958code legal instead of focusing on generating <em>good</em> and legal code).</p>
959
960<p>One important class of optimizations performed is optimizing inserted sign
961and zero extension instructions. We currently use ad-hoc techniques, but could
962move to more rigorous techniques in the future. Here are some good papers on
963the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]964
965<p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]966 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
967 integer arithmetic</a>"<br>
968 Kevin Redwine and Norman Ramsey<br>
969 International Conference on Compiler Construction (CC) 2004
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]970</p>
971
972
973<p>
974 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
975 sign extension elimination</a>"<br>
976 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
977 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
978 and Implementation.
979</p>
980
981</div>
982
983<!-- _______________________________________________________________________ -->
984<div class="doc_subsubsection">
985 <a name="selectiondag_select">SelectionDAG Select Phase</a>
986</div>
987
988<div class="doc_text">
989
990<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]991selection. This phase takes a legal SelectionDAG as input, pattern matches the
992instructions supported by the target to this DAG, and produces a new DAG of
993target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]994
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]995<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]996<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]997%t1 = add float %W, %X
998%t2 = mul float %t1, %Y
999%t3 = add float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1000</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1001</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1002
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1003<p>This LLVM code corresponds to a SelectionDAG that looks basically like
1004this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1005
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1006<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1007<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1008(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1009</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1010</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1011
Chris Lattnera1ff9312005-10-17 15:19:24 +0000[diff] [blame]1012<p>If a target supports floating point multiply-and-add (FMA) operations, one
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1013of the adds can be merged with the multiply. On the PowerPC, for example, the
1014output of the instruction selector might look like this DAG:</p>
1015
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1016<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1017<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1018(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1019</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1020</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1021
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1022<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1023first two operands and adds the third (as single-precision floating-point
1024numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1025add instruction. To perform this pattern match, the PowerPC backend includes
1026the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1027
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1028<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1029<pre>
1030def FMADDS : AForm_1&lt;59, 29,
1031 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1032 "fmadds $FRT, $FRA, $FRC, $FRB",
1033 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1034 F4RC:$FRB))</b>]&gt;;
1035def FADDS : AForm_2&lt;59, 21,
1036 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1037 "fadds $FRT, $FRA, $FRB",
1038 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1039</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1040</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1041
1042<p>The portion of the instruction definition in bold indicates the pattern used
1043to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
1044are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
1045"<tt>F4RC</tt>" is the register class of the input and result values.<p>
1046
1047<p>The TableGen DAG instruction selector generator reads the instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1048patterns in the <tt>.td</tt> file and automatically builds parts of the pattern
1049matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1050
1051<ul>
1052<li>At compiler-compiler time, it analyzes your instruction patterns and tells
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1053 you if your patterns make sense or not.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1054<li>It can handle arbitrary constraints on operands for the pattern match. In
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1055 particular, it is straight-forward to say things like "match any immediate
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1056 that is a 13-bit sign-extended value". For examples, see the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1057 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1058 backend.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1059<li>It knows several important identities for the patterns defined. For
1060 example, it knows that addition is commutative, so it allows the
1061 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1062 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1063 to specially handle this case.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1064<li>It has a full-featured type-inferencing system. In particular, you should
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1065 rarely have to explicitly tell the system what type parts of your patterns
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1066 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1067 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'. It
1068 was able to infer and propagate this knowledge from the fact that
1069 <tt>F4RC</tt> has type 'f32'.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1070<li>Targets can define their own (and rely on built-in) "pattern fragments".
1071 Pattern fragments are chunks of reusable patterns that get inlined into your
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1072 patterns during compiler-compiler time. For example, the integer
1073 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment that
1074 expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not have a
1075 native '<tt>not</tt>' operation. Targets can define their own short-hand
1076 fragments as they see fit. See the definition of '<tt>not</tt>' and
1077 '<tt>ineg</tt>' for examples.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1078<li>In addition to instructions, targets can specify arbitrary patterns that
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1079 map to one or more instructions using the 'Pat' class. For example,
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1080 the PowerPC has no way to load an arbitrary integer immediate into a
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1081 register in one instruction. To tell tblgen how to do this, it defines:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1082 <br>
1083 <br>
1084 <div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1085 <pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1086// Arbitrary immediate support. Implement in terms of LIS/ORI.
1087def : Pat&lt;(i32 imm:$imm),
1088 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1089 </pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1090 </div>
1091 <br>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1092 If none of the single-instruction patterns for loading an immediate into a
1093 register match, this will be used. This rule says "match an arbitrary i32
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1094 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and an
1095 <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to the
1096 left 16 bits') instruction". To make this work, the
1097 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate the
1098 input immediate (in this case, take the high or low 16-bits of the
1099 immediate).</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1100<li>While the system does automate a lot, it still allows you to write custom
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1101 C++ code to match special cases if there is something that is hard to
1102 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1103</ul>
1104
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1105<p>While it has many strengths, the system currently has some limitations,
1106primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1107
1108<ul>
1109<li>Overall, there is no way to define or match SelectionDAG nodes that define
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1110 multiple values (e.g. <tt>ADD_PARTS</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
1111 etc). This is the biggest reason that you currently still <em>have to</em>
1112 write custom C++ code for your instruction selector.</li>
1113<li>There is no great way to support matching complex addressing modes yet. In
1114 the future, we will extend pattern fragments to allow them to define
1115 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame^]1116 addressing mode</a>, which are currently matched with custom C++ code).
1117 In addition, we'll extend fragments so that a
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1118 fragment can match multiple different patterns.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1119<li>We don't automatically infer flags like isStore/isLoad yet.</li>
1120<li>We don't automatically generate the set of supported registers and
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1121 operations for the <a href="#selectiondag_legalize">Legalizer</a> yet.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1122<li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1123</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1124
1125<p>Despite these limitations, the instruction selector generator is still quite
1126useful for most of the binary and logical operations in typical instruction
1127sets. If you run into any problems or can't figure out how to do something,
1128please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1129
1130</div>
1131
1132<!-- _______________________________________________________________________ -->
1133<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1134 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1135</div>
1136
1137<div class="doc_text">
1138
1139<p>The scheduling phase takes the DAG of target instructions from the selection
1140phase and assigns an order. The scheduler can pick an order depending on
1141various constraints of the machines (i.e. order for minimal register pressure or
1142try to cover instruction latencies). Once an order is established, the DAG is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1143converted to a list of <tt><a href="#machineinstr">MachineInstr</a></tt>s and
1144the SelectionDAG is destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1145
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1146<p>Note that this phase is logically separate from the instruction selection
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1147phase, but is tied to it closely in the code because it operates on
1148SelectionDAGs.</p>
1149
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1150</div>
1151
1152<!-- _______________________________________________________________________ -->
1153<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1154 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1155</div>
1156
1157<div class="doc_text">
1158
1159<ol>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1160<li>Optional function-at-a-time selection.</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1161<li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1162</ol>
1163
1164</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1165
1166<!-- ======================================================================= -->
1167<div class="doc_subsection">
1168 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1169</div>
1170<div class="doc_text"><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1171
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1172<!-- ======================================================================= -->
1173<div class="doc_subsection">
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1174 <a name="liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1175</div>
1176
1177<div class="doc_text">
1178
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1179<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
1180They are used by some <a href="#regalloc">register allocator</a> passes to
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1181determine if two or more virtual registers which require the same physical
Bill Wendling41b32522006-09-07 08:39:35 +0000[diff] [blame]1182register are live at the same point in the program (i.e., they conflict). When
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1183this situation occurs, one virtual register must be <i>spilled</i>.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1184
1185</div>
1186
1187<!-- _______________________________________________________________________ -->
1188<div class="doc_subsubsection">
1189 <a name="livevariable_analysis">Live Variable Analysis</a>
1190</div>
1191
1192<div class="doc_text">
1193
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1194<p>The first step in determining the live intervals of variables is to
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1195calculate the set of registers that are immediately dead after the
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1196instruction (i.e., the instruction calculates the value, but it is
1197never used) and the set of registers that are used by the instruction,
1198but are never used after the instruction (i.e., they are killed). Live
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1199variable information is computed for each <i>virtual</i> register and
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1200<i>register allocatable</i> physical register in the function. This
1201is done in a very efficient manner because it uses SSA to sparsely
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1202compute lifetime information for virtual registers (which are in SSA
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1203form) and only has to track physical registers within a block. Before
1204register allocation, LLVM can assume that physical registers are only
1205live within a single basic block. This allows it to do a single,
1206local analysis to resolve physical register lifetimes within each
1207basic block. If a physical register is not register allocatable (e.g.,
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1208a stack pointer or condition codes), it is not tracked.</p>
1209
1210<p>Physical registers may be live in to or out of a function. Live in values
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1211are typically arguments in registers. Live out values are typically return
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1212values in registers. Live in values are marked as such, and are given a dummy
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1213"defining" instruction during live intervals analysis. If the last basic block
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1214of a function is a <tt>return</tt>, then it's marked as using all live out
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1215values in the function.</p>
1216
1217<p><tt>PHI</tt> nodes need to be handled specially, because the calculation
1218of the live variable information from a depth first traversal of the CFG of
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1219the function won't guarantee that a virtual register used by the <tt>PHI</tt>
1220node is defined before it's used. When a <tt>PHI</tt> node is encounted, only
1221the definition is handled, because the uses will be handled in other basic
1222blocks.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1223
1224<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
1225assignment at the end of the current basic block and traverse the successor
1226basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1227the <tt>PHI</tt> node's operands is coming from the current basic block,
1228then the variable is marked as <i>alive</i> within the current basic block
1229and all of its predecessor basic blocks, until the basic block with the
1230defining instruction is encountered.</p>
1231
1232</div>
1233
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1234<!-- _______________________________________________________________________ -->
1235<div class="doc_subsubsection">
1236 <a name="liveintervals_analysis">Live Intervals Analysis</a>
1237</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1238
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1239<div class="doc_text">
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1240
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1241<p>We now have the information available to perform the live intervals analysis
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1242and build the live intervals themselves. We start off by numbering the basic
1243blocks and machine instructions. We then handle the "live-in" values. These
1244are in physical registers, so the physical register is assumed to be killed by
1245the end of the basic block. Live intervals for virtual registers are computed
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1246for some ordering of the machine instructions <tt>[1, N]</tt>. A live interval
1247is an interval <tt>[i, j)</tt>, where <tt>1 <= i <= j < N</tt>, for which a
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1248variable is live.</p>
1249
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1250<p><i><b>More to come...</b></i></p>
1251
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1252</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1253
1254<!-- ======================================================================= -->
1255<div class="doc_subsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1256 <a name="regalloc">Register Allocation</a>
1257</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1258
1259<div class="doc_text">
1260
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1261<p>The <i>Register Allocation problem</i> consists in mapping a program
1262<i>P<sub>v</sub></i>, that can use an unbounded number of virtual
1263registers, to a program <i>P<sub>p</sub></i> that contains a finite
1264(possibly small) number of physical registers. Each target architecture has
1265a different number of physical registers. If the number of physical
1266registers is not enough to accommodate all the virtual registers, some of
1267them will have to be mapped into memory. These virtuals are called
1268<i>spilled virtuals</i>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1269
1270</div>
1271
1272<!-- _______________________________________________________________________ -->
1273
1274<div class="doc_subsubsection">
1275 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1276</div>
1277
1278<div class="doc_text">
1279
1280<p>In LLVM, physical registers are denoted by integer numbers that
1281normally range from 1 to 1023. To see how this numbering is defined
1282for a particular architecture, you can read the
1283<tt>GenRegisterNames.inc</tt> file for that architecture. For
1284instance, by inspecting
1285<tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the 32-bit
1286register <tt>EAX</tt> is denoted by 15, and the MMX register
1287<tt>MM0</tt> is mapped to 48.</p>
1288
1289<p>Some architectures contain registers that share the same physical
1290location. A notable example is the X86 platform. For instance, in the
1291X86 architecture, the registers <tt>EAX</tt>, <tt>AX</tt> and
1292<tt>AL</tt> share the first eight bits. These physical registers are
1293marked as <i>aliased</i> in LLVM. Given a particular architecture, you
1294can check which registers are aliased by inspecting its
1295<tt>RegisterInfo.td</tt> file. Moreover, the method
1296<tt>MRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1297all the physical registers aliased to the register <tt>p_reg</tt>.</p>
1298
1299<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
1300Elements in the same register class are functionally equivalent, and can
1301be interchangeably used. Each virtual register can only be mapped to
1302physical registers of a particular class. For instance, in the X86
1303architecture, some virtuals can only be allocated to 8 bit registers.
1304A register class is described by <tt>TargetRegisterClass</tt> objects.
1305To discover if a virtual register is compatible with a given physical,
1306this code can be used:
1307</p>
1308
1309<div class="doc_code">
1310<pre>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1311bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1312 unsigned v_reg,
1313 unsigned p_reg) {
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1314 assert(MRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1315 "Target register must be physical");
1316 const TargetRegisterClass *trc = mf.getSSARegMap()->getRegClass(v_reg);
1317 return trc->contains(p_reg);
1318}
1319</pre>
1320</div>
1321
1322<p>Sometimes, mostly for debugging purposes, it is useful to change
1323the number of physical registers available in the target
1324architecture. This must be done statically, inside the
1325<tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt> for
1326<tt>RegisterClass</tt>, the last parameter of which is a list of
1327registers. Just commenting some out is one simple way to avoid them
1328being used. A more polite way is to explicitly exclude some registers
1329from the <i>allocation order</i>. See the definition of the
1330<tt>GR</tt> register class in
1331<tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
1332(e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
1333
1334<p>Virtual registers are also denoted by integer numbers. Contrary to
1335physical registers, different virtual registers never share the same
1336number. The smallest virtual register is normally assigned the number
13371024. This may change, so, in order to know which is the first virtual
1338register, you should access
1339<tt>MRegisterInfo::FirstVirtualRegister</tt>. Any register whose
1340number is greater than or equal to
1341<tt>MRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
1342register. Whereas physical registers are statically defined in a
1343<tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1344application developer, that is not the case with virtual registers.
1345In order to create new virtual registers, use the method
1346<tt>SSARegMap::createVirtualRegister()</tt>. This method will return a
1347virtual register with the highest code.
1348</p>
1349
1350<p>Before register allocation, the operands of an instruction are
1351mostly virtual registers, although physical registers may also be
1352used. In order to check if a given machine operand is a register, use
1353the boolean function <tt>MachineOperand::isRegister()</tt>. To obtain
1354the integer code of a register, use
1355<tt>MachineOperand::getReg()</tt>. An instruction may define or use a
1356register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1357defines the registers 1024, and uses registers 1025 and 1026. Given a
1358register operand, the method <tt>MachineOperand::isUse()</tt> informs
1359if that register is being used by the instruction. The method
1360<tt>MachineOperand::isDef()</tt> informs if that registers is being
1361defined.</p>
1362
Gabor Greif04367bf2007-07-06 22:07:22 +0000[diff] [blame]1363<p>We will call physical registers present in the LLVM bitcode before
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1364register allocation <i>pre-colored registers</i>. Pre-colored
1365registers are used in many different situations, for instance, to pass
1366parameters of functions calls, and to store results of particular
1367instructions. There are two types of pre-colored registers: the ones
1368<i>implicitly</i> defined, and those <i>explicitly</i>
1369defined. Explicitly defined registers are normal operands, and can be
1370accessed with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In
1371order to check which registers are implicitly defined by an
1372instruction, use the
1373<tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>, where
1374<tt>opcode</tt> is the opcode of the target instruction. One important
1375difference between explicit and implicit physical registers is that
1376the latter are defined statically for each instruction, whereas the
1377former may vary depending on the program being compiled. For example,
1378an instruction that represents a function call will always implicitly
1379define or use the same set of physical registers. To read the
1380registers implicitly used by an instruction, use
1381<tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1382registers impose constraints on any register allocation algorithm. The
1383register allocator must make sure that none of them is been
1384overwritten by the values of virtual registers while still alive.</p>
1385
1386</div>
1387
1388<!-- _______________________________________________________________________ -->
1389
1390<div class="doc_subsubsection">
1391 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1392</div>
1393
1394<div class="doc_text">
1395
1396<p>There are two ways to map virtual registers to physical registers (or to
1397memory slots). The first way, that we will call <i>direct mapping</i>,
1398is based on the use of methods of the classes <tt>MRegisterInfo</tt>,
1399and <tt>MachineOperand</tt>. The second way, that we will call
1400<i>indirect mapping</i>, relies on the <tt>VirtRegMap</tt> class in
1401order to insert loads and stores sending and getting values to and from
1402memory.</p>
1403
1404<p>The direct mapping provides more flexibility to the developer of
1405the register allocator; however, it is more error prone, and demands
1406more implementation work. Basically, the programmer will have to
1407specify where load and store instructions should be inserted in the
1408target function being compiled in order to get and store values in
1409memory. To assign a physical register to a virtual register present in
1410a given operand, use <tt>MachineOperand::setReg(p_reg)</tt>. To insert
1411a store instruction, use
1412<tt>MRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
1413instruction, use <tt>MRegisterInfo::loadRegFromStackSlot</tt>.</p>
1414
1415<p>The indirect mapping shields the application developer from the
1416complexities of inserting load and store instructions. In order to map
1417a virtual register to a physical one, use
1418<tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In order to map a
1419certain virtual register to memory, use
1420<tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will
1421return the stack slot where <tt>vreg</tt>'s value will be located. If
1422it is necessary to map another virtual register to the same stack
1423slot, use <tt>VirtRegMap::assignVirt2StackSlot(vreg,
1424stack_location)</tt>. One important point to consider when using the
1425indirect mapping, is that even if a virtual register is mapped to
1426memory, it still needs to be mapped to a physical register. This
1427physical register is the location where the virtual register is
1428supposed to be found before being stored or after being reloaded.</p>
1429
1430<p>If the indirect strategy is used, after all the virtual registers
1431have been mapped to physical registers or stack slots, it is necessary
1432to use a spiller object to place load and store instructions in the
1433code. Every virtual that has been mapped to a stack slot will be
1434stored to memory after been defined and will be loaded before being
1435used. The implementation of the spiller tries to recycle load/store
1436instructions, avoiding unnecessary instructions. For an example of how
1437to invoke the spiller, see
1438<tt>RegAllocLinearScan::runOnMachineFunction</tt> in
1439<tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
1440
1441</div>
1442
1443<!-- _______________________________________________________________________ -->
1444<div class="doc_subsubsection">
1445 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1446</div>
1447
1448<div class="doc_text">
1449
1450<p>With very rare exceptions (e.g., function calls), the LLVM machine
1451code instructions are three address instructions. That is, each
1452instruction is expected to define at most one register, and to use at
1453most two registers. However, some architectures use two address
1454instructions. In this case, the defined register is also one of the
1455used register. For instance, an instruction such as <tt>ADD %EAX,
1456%EBX</tt>, in X86 is actually equivalent to <tt>%EAX = %EAX +
1457%EBX</tt>.</p>
1458
1459<p>In order to produce correct code, LLVM must convert three address
1460instructions that represent two address instructions into true two
1461address instructions. LLVM provides the pass
1462<tt>TwoAddressInstructionPass</tt> for this specific purpose. It must
1463be run before register allocation takes place. After its execution,
1464the resulting code may no longer be in SSA form. This happens, for
1465instance, in situations where an instruction such as <tt>%a = ADD %b
1466%c</tt> is converted to two instructions such as:</p>
1467
1468<div class="doc_code">
1469<pre>
1470%a = MOVE %b
1471%a = ADD %a %b
1472</pre>
1473</div>
1474
1475<p>Notice that, internally, the second instruction is represented as
1476<tt>ADD %a[def/use] %b</tt>. I.e., the register operand <tt>%a</tt> is
1477both used and defined by the instruction.</p>
1478
1479</div>
1480
1481<!-- _______________________________________________________________________ -->
1482<div class="doc_subsubsection">
1483 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1484</div>
1485
1486<div class="doc_text">
1487
1488<p>An important transformation that happens during register allocation is called
1489the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many
1490analyses that are performed on the control flow graph of
1491programs. However, traditional instruction sets do not implement
1492PHI instructions. Thus, in order to generate executable code, compilers
1493must replace PHI instructions with other instructions that preserve their
1494semantics.</p>
1495
1496<p>There are many ways in which PHI instructions can safely be removed
1497from the target code. The most traditional PHI deconstruction
1498algorithm replaces PHI instructions with copy instructions. That is
1499the strategy adopted by LLVM. The SSA deconstruction algorithm is
1500implemented in n<tt>lib/CodeGen/>PHIElimination.cpp</tt>. In order to
1501invoke this pass, the identifier <tt>PHIEliminationID</tt> must be
1502marked as required in the code of the register allocator.</p>
1503
1504</div>
1505
1506<!-- _______________________________________________________________________ -->
1507<div class="doc_subsubsection">
1508 <a name="regAlloc_fold">Instruction folding</a>
1509</div>
1510
1511<div class="doc_text">
1512
1513<p><i>Instruction folding</i> is an optimization performed during
1514register allocation that removes unnecessary copy instructions. For
1515instance, a sequence of instructions such as:</p>
1516
1517<div class="doc_code">
1518<pre>
1519%EBX = LOAD %mem_address
1520%EAX = COPY %EBX
1521</pre>
1522</div>
1523
1524<p>can be safely substituted by the single instruction:
1525
1526<div class="doc_code">
1527<pre>
1528%EAX = LOAD %mem_address
1529</pre>
1530</div>
1531
1532<p>Instructions can be folded with the
1533<tt>MRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1534taken when folding instructions; a folded instruction can be quite
1535different from the original instruction. See
1536<tt>LiveIntervals::addIntervalsForSpills</tt> in
1537<tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its use.</p>
1538
1539</div>
1540
1541<!-- _______________________________________________________________________ -->
1542
1543<div class="doc_subsubsection">
1544 <a name="regAlloc_builtIn">Built in register allocators</a>
1545</div>
1546
1547<div class="doc_text">
1548
1549<p>The LLVM infrastructure provides the application developer with
1550three different register allocators:</p>
1551
1552<ul>
1553 <li><i>Simple</i> - This is a very simple implementation that does
1554 not keep values in registers across instructions. This register
1555 allocator immediately spills every value right after it is
1556 computed, and reloads all used operands from memory to temporary
1557 registers before each instruction.</li>
1558 <li><i>Local</i> - This register allocator is an improvement on the
1559 <i>Simple</i> implementation. It allocates registers on a basic
1560 block level, attempting to keep values in registers and reusing
1561 registers as appropriate.</li>
1562 <li><i>Linear Scan</i> - <i>The default allocator</i>. This is the
1563 well-know linear scan register allocator. Whereas the
1564 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1565 implementation technique, the <i>Linear Scan</i> implementation
1566 uses a spiller in order to place load and stores.</li>
1567</ul>
1568
1569<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
1570command line option <tt>-regalloc=...</tt>:</p>
1571
1572<div class="doc_code">
1573<pre>
1574$ llc -f -regalloc=simple file.bc -o sp.s;
1575$ llc -f -regalloc=local file.bc -o lc.s;
1576$ llc -f -regalloc=linearscan file.bc -o ln.s;
1577</pre>
1578</div>
1579
1580</div>
1581
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1582<!-- ======================================================================= -->
1583<div class="doc_subsection">
1584 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1585</div>
1586<div class="doc_text"><p>To Be Written</p></div>
1587<!-- ======================================================================= -->
1588<div class="doc_subsection">
1589 <a name="latemco">Late Machine Code Optimizations</a>
1590</div>
1591<div class="doc_text"><p>To Be Written</p></div>
1592<!-- ======================================================================= -->
1593<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1594 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1595</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1596<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1597<!-- _______________________________________________________________________ -->
1598<div class="doc_subsubsection">
1599 <a name="codeemit_asm">Generating Assembly Code</a>
1600</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1601<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1602<!-- _______________________________________________________________________ -->
1603<div class="doc_subsubsection">
1604 <a name="codeemit_bin">Generating Binary Machine Code</a>
1605</div>
1606
1607<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1608 <p>For the JIT or <tt>.o</tt> file writer</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1609</div>
1610
1611
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1612<!-- *********************************************************************** -->
1613<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1614 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1615</div>
1616<!-- *********************************************************************** -->
1617
1618<div class="doc_text">
1619
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1620<p>This section of the document explains features or design decisions that
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1621are specific to the code generator for a particular target.</p>
1622
1623</div>
1624
1625
1626<!-- ======================================================================= -->
1627<div class="doc_subsection">
1628 <a name="x86">The X86 backend</a>
1629</div>
1630
1631<div class="doc_text">
1632
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1633<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Dan Gohmanfd800722007-12-13 20:43:47 +0000[diff] [blame^]1634code generator is capable of targeting a variety of x86-32 and x86-64
1635processors, and includes support for ISA extensions such as MMX and SSE.
1636</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1637
1638</div>
1639
1640<!-- _______________________________________________________________________ -->
1641<div class="doc_subsubsection">
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1642 <a name="x86_tt">X86 Target Triples Supported</a>
1643</div>
1644
1645<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1646
1647<p>The following are the known target triples that are supported by the X86
1648backend. This is not an exhaustive list, and it would be useful to add those
1649that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1650
1651<ul>
1652<li><b>i686-pc-linux-gnu</b> - Linux</li>
1653<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1654<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1655<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1656<li><b>i386-pc-mingw32msvc</b> - MingW crosscompiler on Linux</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1657<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1658</ul>
1659
1660</div>
1661
1662<!-- _______________________________________________________________________ -->
1663<div class="doc_subsubsection">
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1664 <a name="x86_cc">X86 Calling Conventions supported</a>
1665</div>
1666
1667
1668<div class="doc_text">
1669
1670<p>The folowing target-specific calling conventions are known to backend:</p>
1671
1672<ul>
1673<li><b>x86_StdCall</b> - stdcall calling convention seen on Microsoft Windows
1674platform (CC ID = 64).</li>
1675<li><b>x86_FastCall</b> - fastcall calling convention seen on Microsoft Windows
1676platform (CC ID = 65).</li>
1677</ul>
1678
1679</div>
1680
1681<!-- _______________________________________________________________________ -->
1682<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1683 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1684</div>
1685
1686<div class="doc_text">
1687
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1688<p>The x86 has a very flexible way of accessing memory. It is capable of
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1689forming memory addresses of the following expression directly in integer
1690instructions (which use ModR/M addressing):</p>
1691
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1692<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1693<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1694Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1695</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1696</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1697
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1698<p>In order to represent this, LLVM tracks no less than 4 operands for each
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1699memory operand of this form. This means that the "load" form of '<tt>mov</tt>'
1700has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1701
1702<pre>
1703Index: 0 | 1 2 3 4
1704Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1705OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1706</pre>
1707
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1708<p>Stores, and all other instructions, treat the four memory operands in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1709same way and in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1710
1711</div>
1712
1713<!-- _______________________________________________________________________ -->
1714<div class="doc_subsubsection">
1715 <a name="x86_names">Instruction naming</a>
1716</div>
1717
1718<div class="doc_text">
1719
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1720<p>An instruction name consists of the base name, a default operand size, and a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1721a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1722
1723<p>
1724<tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>
1725<tt>IMUL16rmi</tt> -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1726<tt>IMUL16rmi8</tt> -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1727<tt>MOVSX32rm16</tt> -&gt; movsx, 32-bit register, 16-bit memory
1728</p>
1729
1730</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1731
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1732<!-- ======================================================================= -->
1733<div class="doc_subsection">
1734 <a name="ppc">The PowerPC backend</a>
1735</div>
1736
1737<div class="doc_text">
1738<p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
1739code generation is retargetable to several variations or <i>subtargets</i> of
1740the PowerPC ISA; including ppc32, ppc64 and altivec.
1741</p>
1742</div>
1743
1744<!-- _______________________________________________________________________ -->
1745<div class="doc_subsubsection">
1746 <a name="ppc_abi">LLVM PowerPC ABI</a>
1747</div>
1748
1749<div class="doc_text">
1750<p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
1751relative (PIC) or static addressing for accessing global values, so no TOC (r2)
1752is used. Second, r31 is used as a frame pointer to allow dynamic growth of a
1753stack frame. LLVM takes advantage of having no TOC to provide space to save
1754the frame pointer in the PowerPC linkage area of the caller frame. Other
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1755details of PowerPC ABI can be found at <a href=
1756"http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
1757>PowerPC ABI.</a> Note: This link describes the 32 bit ABI. The
175864 bit ABI is similar except space for GPRs are 8 bytes wide (not 4) and r13 is
1759reserved for system use.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1760</div>
1761
1762<!-- _______________________________________________________________________ -->
1763<div class="doc_subsubsection">
1764 <a name="ppc_frame">Frame Layout</a>
1765</div>
1766
1767<div class="doc_text">
1768<p>The size of a PowerPC frame is usually fixed for the duration of a
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1769function&rsquo;s invocation. Since the frame is fixed size, all references into
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1770the frame can be accessed via fixed offsets from the stack pointer. The
1771exception to this is when dynamic alloca or variable sized arrays are present,
1772then a base pointer (r31) is used as a proxy for the stack pointer and stack
1773pointer is free to grow or shrink. A base pointer is also used if llvm-gcc is
1774not passed the -fomit-frame-pointer flag. The stack pointer is always aligned to
177516 bytes, so that space allocated for altivec vectors will be properly
1776aligned.</p>
1777<p>An invocation frame is layed out as follows (low memory at top);</p>
1778</div>
1779
1780<div class="doc_text">
1781<table class="layout">
1782 <tr>
1783 <td>Linkage<br><br></td>
1784 </tr>
1785 <tr>
1786 <td>Parameter area<br><br></td>
1787 </tr>
1788 <tr>
1789 <td>Dynamic area<br><br></td>
1790 </tr>
1791 <tr>
1792 <td>Locals area<br><br></td>
1793 </tr>
1794 <tr>
1795 <td>Saved registers area<br><br></td>
1796 </tr>
1797 <tr style="border-style: none hidden none hidden;">
1798 <td><br></td>
1799 </tr>
1800 <tr>
1801 <td>Previous Frame<br><br></td>
1802 </tr>
1803</table>
1804</div>
1805
1806<div class="doc_text">
1807<p>The <i>linkage</i> area is used by a callee to save special registers prior
1808to allocating its own frame. Only three entries are relevant to LLVM. The
1809first entry is the previous stack pointer (sp), aka link. This allows probing
1810tools like gdb or exception handlers to quickly scan the frames in the stack. A
1811function epilog can also use the link to pop the frame from the stack. The
1812third entry in the linkage area is used to save the return address from the lr
1813register. Finally, as mentioned above, the last entry is used to save the
1814previous frame pointer (r31.) The entries in the linkage area are the size of a
1815GPR, thus the linkage area is 24 bytes long in 32 bit mode and 48 bytes in 64
1816bit mode.</p>
1817</div>
1818
1819<div class="doc_text">
1820<p>32 bit linkage area</p>
1821<table class="layout">
1822 <tr>
1823 <td>0</td>
1824 <td>Saved SP (r1)</td>
1825 </tr>
1826 <tr>
1827 <td>4</td>
1828 <td>Saved CR</td>
1829 </tr>
1830 <tr>
1831 <td>8</td>
1832 <td>Saved LR</td>
1833 </tr>
1834 <tr>
1835 <td>12</td>
1836 <td>Reserved</td>
1837 </tr>
1838 <tr>
1839 <td>16</td>
1840 <td>Reserved</td>
1841 </tr>
1842 <tr>
1843 <td>20</td>
1844 <td>Saved FP (r31)</td>
1845 </tr>
1846</table>
1847</div>
1848
1849<div class="doc_text">
1850<p>64 bit linkage area</p>
1851<table class="layout">
1852 <tr>
1853 <td>0</td>
1854 <td>Saved SP (r1)</td>
1855 </tr>
1856 <tr>
1857 <td>8</td>
1858 <td>Saved CR</td>
1859 </tr>
1860 <tr>
1861 <td>16</td>
1862 <td>Saved LR</td>
1863 </tr>
1864 <tr>
1865 <td>24</td>
1866 <td>Reserved</td>
1867 </tr>
1868 <tr>
1869 <td>32</td>
1870 <td>Reserved</td>
1871 </tr>
1872 <tr>
1873 <td>40</td>
1874 <td>Saved FP (r31)</td>
1875 </tr>
1876</table>
1877</div>
1878
1879<div class="doc_text">
1880<p>The <i>parameter area</i> is used to store arguments being passed to a callee
1881function. Following the PowerPC ABI, the first few arguments are actually
1882passed in registers, with the space in the parameter area unused. However, if
1883there are not enough registers or the callee is a thunk or vararg function,
1884these register arguments can be spilled into the parameter area. Thus, the
1885parameter area must be large enough to store all the parameters for the largest
1886call sequence made by the caller. The size must also be mimimally large enough
1887to spill registers r3-r10. This allows callees blind to the call signature,
1888such as thunks and vararg functions, enough space to cache the argument
1889registers. Therefore, the parameter area is minimally 32 bytes (64 bytes in 64
1890bit mode.) Also note that since the parameter area is a fixed offset from the
1891top of the frame, that a callee can access its spilt arguments using fixed
1892offsets from the stack pointer (or base pointer.)</p>
1893</div>
1894
1895<div class="doc_text">
1896<p>Combining the information about the linkage, parameter areas and alignment. A
1897stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
1898mode.</p>
1899</div>
1900
1901<div class="doc_text">
1902<p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
1903alloca then space is added to the stack, the linkage and parameter areas are
1904shifted to top of stack, and the new space is available immediately below the
1905linkage and parameter areas. The cost of shifting the linkage and parameter
1906areas is minor since only the link value needs to be copied. The link value can
1907be easily fetched by adding the original frame size to the base pointer. Note
1908that allocations in the dynamic space need to observe 16 byte aligment.</p>
1909</div>
1910
1911<div class="doc_text">
1912<p>The <i>locals area</i> is where the llvm compiler reserves space for local
1913variables.</p>
1914</div>
1915
1916<div class="doc_text">
1917<p>The <i>saved registers area</i> is where the llvm compiler spills callee saved
1918registers on entry to the callee.</p>
1919</div>
1920
1921<!-- _______________________________________________________________________ -->
1922<div class="doc_subsubsection">
1923 <a name="ppc_prolog">Prolog/Epilog</a>
1924</div>
1925
1926<div class="doc_text">
1927<p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
1928the following exceptions. Callee saved registers are spilled after the frame is
1929created. This allows the llvm epilog/prolog support to be common with other
1930targets. The base pointer callee saved register r31 is saved in the TOC slot of
1931linkage area. This simplifies allocation of space for the base pointer and
1932makes it convenient to locate programatically and during debugging.</p>
1933</div>
1934
1935<!-- _______________________________________________________________________ -->
1936<div class="doc_subsubsection">
1937 <a name="ppc_dynamic">Dynamic Allocation</a>
1938</div>
1939
1940<div class="doc_text">
1941<p></p>
1942</div>
1943
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1944<div class="doc_text">
1945<p><i>TODO - More to come.</i></p>
1946</div>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1947
1948
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1949<!-- *********************************************************************** -->
1950<hr>
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1956
1957 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]1958 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1959 Last modified: $Date$
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