Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 763a75dbf719242e7f99c6447d20b9bffb75dfa2 / . / lib / Target / ARM / ARMISelLowering.h
blob: d11171ef110cc06b1a77028c3a9e18c2449fa56b [file] [log] [blame]
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
Craig Topperc1f6f422012-03-17 07:33:42 +0000[diff] [blame]18#include "ARM.h"
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]19#include "ARMSubtarget.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]20#include "llvm/Target/TargetLowering.h"
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]21#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]22#include "llvm/CodeGen/FastISel.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]23#include "llvm/CodeGen/SelectionDAG.h"
Bob Wilson1f595bb2009-04-17 19:07:39 +0000[diff] [blame]24#include "llvm/CodeGen/CallingConvLower.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]25#include <vector>
26
27namespace llvm {
28 class ARMConstantPoolValue;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]29
30 namespace ARMISD {
31 // ARM Specific DAG Nodes
32 enum NodeType {
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]33 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohman0ba2bcf2008-09-23 18:42:32 +0000[diff] [blame]34 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]35
36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
37 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Cheng53519f02011-01-21 18:55:51 +0000[diff] [blame]38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
39 // DYN mode.
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000[diff] [blame]40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
41 // PIC mode.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]43
Manman Ren763a75d2012-06-01 02:44:42 +0000[diff] [blame^]44 // Add pseudo op to model memcpy for struct byval.
45 COPY_STRUCT_BYVAL,
46
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]47 CALL, // Function call.
Evan Cheng277f0742007-06-19 21:05:09 +0000[diff] [blame]48 CALL_PRED, // Function call that's predicable.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]49 CALL_NOLINK, // Function call with branch not branch-and-link.
50 tCALL, // Thumb function call.
51 BRCOND, // Conditional branch.
52 BR_JT, // Jumptable branch.
Evan Cheng5657c012009-07-29 02:18:14 +0000[diff] [blame]53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]54 RET_FLAG, // Return with a flag operand.
55
56 PIC_ADD, // Add with a PC operand and a PIC label.
57
58 CMP, // ARM compare instructions.
David Goodwinc0309b42009-06-29 15:33:01 +0000[diff] [blame]59 CMPZ, // ARM compare that sets only Z flag.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]60 CMPFP, // ARM VFP compare instruction, sets FPSCR.
61 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
62 FMSTAT, // ARM fmstat instruction.
Evan Chengc892aeb2012-02-23 01:19:06 +0000[diff] [blame]63
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]64 CMOV, // ARM conditional move instructions.
Evan Chengc892aeb2012-02-23 01:19:06 +0000[diff] [blame]65 CAND, // ARM conditional and instructions.
66 COR, // ARM conditional or instructions.
67 CXOR, // ARM conditional xor instructions.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]68
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]69 BCC_i64,
70
Jim Grosbach3482c802010-01-18 19:58:49 +0000[diff] [blame]71 RBIT, // ARM bitreverse instruction
72
Bob Wilson76a312b2010-03-19 22:51:32 +0000[diff] [blame]73 FTOSI, // FP to sint within a FP register.
74 FTOUI, // FP to uint within a FP register.
75 SITOF, // sint to FP within a FP register.
76 UITOF, // uint to FP within a FP register.
77
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]78 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
79 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
80 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]81
Evan Cheng342e3162011-08-30 01:34:54 +0000[diff] [blame]82 ADDC, // Add with carry
83 ADDE, // Add using carry
84 SUBC, // Sub with carry
85 SUBE, // Sub using carry
86
Jim Grosbache5165492009-11-09 00:11:35 +0000[diff] [blame]87 VMOVRRD, // double to two gprs.
88 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +0000[diff] [blame]89
Jim Grosbache4ad3872010-10-19 23:27:08 +0000[diff] [blame]90 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
91 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Jim Grosbach0e0da732009-05-12 23:59:14 +0000[diff] [blame]92
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]93 TC_RETURN, // Tail call return pseudo.
94
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]95 THREAD_POINTER,
96
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]97 DYN_ALLOC, // Dynamic allocation on the stack.
98
Bob Wilsonf74a4292010-10-30 00:54:37 +0000[diff] [blame]99 MEMBARRIER, // Memory barrier (DMB)
100 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Chengdfed19f2010-11-03 06:34:55 +0000[diff] [blame]101
102 PRELOAD, // Preload
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]103
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]104 VCEQ, // Vector compare equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]105 VCEQZ, // Vector compare equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]106 VCGE, // Vector compare greater than or equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]107 VCGEZ, // Vector compare greater than or equal to zero.
108 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]109 VCGEU, // Vector compare unsigned greater than or equal.
110 VCGT, // Vector compare greater than.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]111 VCGTZ, // Vector compare greater than zero.
112 VCLTZ, // Vector compare less than zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]113 VCGTU, // Vector compare unsigned greater than.
114 VTST, // Vector test bits.
115
116 // Vector shift by immediate:
117 VSHL, // ...left
118 VSHRs, // ...right (signed)
119 VSHRu, // ...right (unsigned)
120 VSHLLs, // ...left long (signed)
121 VSHLLu, // ...left long (unsigned)
122 VSHLLi, // ...left long (with maximum shift count)
123 VSHRN, // ...right narrow
124
125 // Vector rounding shift by immediate:
126 VRSHRs, // ...right (signed)
127 VRSHRu, // ...right (unsigned)
128 VRSHRN, // ...right narrow
129
130 // Vector saturating shift by immediate:
131 VQSHLs, // ...left (signed)
132 VQSHLu, // ...left (unsigned)
133 VQSHLsu, // ...left (signed to unsigned)
134 VQSHRNs, // ...right narrow (signed)
135 VQSHRNu, // ...right narrow (unsigned)
136 VQSHRNsu, // ...right narrow (signed to unsigned)
137
138 // Vector saturating rounding shift by immediate:
139 VQRSHRNs, // ...right narrow (signed)
140 VQRSHRNu, // ...right narrow (unsigned)
141 VQRSHRNsu, // ...right narrow (signed to unsigned)
142
143 // Vector shift and insert:
144 VSLI, // ...left
145 VSRI, // ...right
146
147 // Vector get lane (VMOV scalar to ARM core register)
148 // (These are used for 8- and 16-bit element types only.)
149 VGETLANEu, // zero-extend vector extract element
150 VGETLANEs, // sign-extend vector extract element
151
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]152 // Vector move immediate and move negated immediate:
Bob Wilsoncba270d2010-07-13 21:16:48 +0000[diff] [blame]153 VMOVIMM,
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]154 VMVNIMM,
155
Evan Chengeaa192a2011-11-15 02:12:34 +0000[diff] [blame]156 // Vector move f32 immediate:
157 VMOVFPIMM,
158
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]159 // Vector duplicate:
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000[diff] [blame]160 VDUP,
Bob Wilson0ce37102009-08-14 05:08:32 +0000[diff] [blame]161 VDUPLANE,
Bob Wilsona599bff2009-08-04 00:36:16 +0000[diff] [blame]162
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]163 // Vector shuffles:
Bob Wilsonde95c1b82009-08-19 17:03:43 +0000[diff] [blame]164 VEXT, // extract
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]165 VREV64, // reverse elements within 64-bit doublewords
166 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +0000[diff] [blame]167 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsonc692cb72009-08-21 20:54:19 +0000[diff] [blame]168 VZIP, // zip (interleave)
169 VUZP, // unzip (deinterleave)
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]170 VTRN, // transpose
Bill Wendling69a05a72011-03-14 23:02:38 +0000[diff] [blame]171 VTBL1, // 1-register shuffle with mask
172 VTBL2, // 2-register shuffle with mask
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]173
Bob Wilsond0b69cf2010-09-01 23:50:19 +0000[diff] [blame]174 // Vector multiply long:
175 VMULLs, // ...signed
176 VMULLu, // ...unsigned
177
Bob Wilson40cbe7d2010-06-04 00:04:02 +0000[diff] [blame]178 // Operands of the standard BUILD_VECTOR node are not legalized, which
179 // is fine if BUILD_VECTORs are always lowered to shuffles or other
180 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
181 // operands need to be legalized. Define an ARM-specific version of
182 // BUILD_VECTOR for this purpose.
183 BUILD_VECTOR,
184
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]185 // Floating-point max and min:
186 FMAX,
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]187 FMIN,
188
189 // Bit-field insert
Owen Andersond9668172010-11-03 22:44:51 +0000[diff] [blame]190 BFI,
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]191
Owen Andersond9668172010-11-03 22:44:51 +0000[diff] [blame]192 // Vector OR with immediate
Owen Anderson080c0922010-11-05 19:27:46 +0000[diff] [blame]193 VORRIMM,
194 // Vector AND with NOT of immediate
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +0000[diff] [blame]195 VBICIMM,
196
Cameron Zwarichc0e6d782011-03-30 23:01:21 +0000[diff] [blame]197 // Vector bitwise select
198 VBSL,
199
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +0000[diff] [blame]200 // Vector load N-element structure to all lanes:
201 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
202 VLD3DUP,
Bob Wilson1c3ef902011-02-07 17:43:21 +0000[diff] [blame]203 VLD4DUP,
204
205 // NEON loads with post-increment base updates:
206 VLD1_UPD,
207 VLD2_UPD,
208 VLD3_UPD,
209 VLD4_UPD,
210 VLD2LN_UPD,
211 VLD3LN_UPD,
212 VLD4LN_UPD,
213 VLD2DUP_UPD,
214 VLD3DUP_UPD,
215 VLD4DUP_UPD,
216
217 // NEON stores with post-increment base updates:
218 VST1_UPD,
219 VST2_UPD,
220 VST3_UPD,
221 VST4_UPD,
222 VST2LN_UPD,
223 VST3LN_UPD,
Eli Friedman2bdffe42011-08-31 00:31:29 +0000[diff] [blame]224 VST4LN_UPD,
225
226 // 64-bit atomic ops (value split into two registers)
227 ATOMADD64_DAG,
228 ATOMSUB64_DAG,
229 ATOMOR64_DAG,
230 ATOMXOR64_DAG,
231 ATOMAND64_DAG,
232 ATOMNAND64_DAG,
233 ATOMSWAP64_DAG,
234 ATOMCMPXCHG64_DAG
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]235 };
236 }
237
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]238 /// Define some predicates that are used for node matching.
239 namespace ARM {
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]240 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]241 }
242
Bob Wilson261f2a22009-05-20 16:30:25 +0000[diff] [blame]243 //===--------------------------------------------------------------------===//
Dale Johannesen80dae192007-03-20 00:30:56 +0000[diff] [blame]244 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]245
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]246 class ARMTargetLowering : public TargetLowering {
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]247 public:
Dan Gohman61e729e2007-08-02 21:21:54 +0000[diff] [blame]248 explicit ARMTargetLowering(TargetMachine &TM);
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]249
Jim Grosbache1102ca2010-07-19 17:20:38 +0000[diff] [blame]250 virtual unsigned getJumpTableEncoding(void) const;
251
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]252 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]253
254 /// ReplaceNodeResults - Replace the results of node with an illegal result
255 /// type with new values built out of custom code.
256 ///
257 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]258 SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]259
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]260 virtual const char *getTargetNodeName(unsigned Opcode) const;
261
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]262 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
263 virtual EVT getSetCCResultType(EVT VT) const;
264
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000[diff] [blame]265 virtual MachineBasicBlock *
266 EmitInstrWithCustomInserter(MachineInstr *MI,
267 MachineBasicBlock *MBB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]268
Evan Cheng37fefc22011-08-30 19:09:48 +0000[diff] [blame]269 virtual void
270 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
271
Evan Chenge721f5c2011-07-13 00:42:17 +0000[diff] [blame]272 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
Evan Cheng31959b12011-02-02 01:06:55 +0000[diff] [blame]273 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
274
275 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
276
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]277 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
278 /// unaligned memory accesses. of the specified type.
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]279 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
280
Lang Hames1a1d1fc2011-11-02 22:52:45 +0000[diff] [blame]281 virtual EVT getOptimalMemOpType(uint64_t Size,
282 unsigned DstAlign, unsigned SrcAlign,
Lang Hamesa1e78882011-11-02 23:37:04 +0000[diff] [blame]283 bool IsZeroVal,
Lang Hames1a1d1fc2011-11-02 22:52:45 +0000[diff] [blame]284 bool MemcpyStrSrc,
285 MachineFunction &MF) const;
286
Chris Lattnerc9addb72007-03-30 23:15:24 +0000[diff] [blame]287 /// isLegalAddressingMode - Return true if the addressing mode represented
288 /// by AM is legal for this target, for a load/store of the specified type.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]289 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
Evan Chenge6c835f2009-08-14 20:09:37 +0000[diff] [blame]290 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]291
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]292 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]293 /// icmp immediate, that is the target has icmp instructions which can
294 /// compare a register against the immediate without having to materialize
295 /// the immediate into a register.
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]296 virtual bool isLegalICmpImmediate(int64_t Imm) const;
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]297
Dan Gohmancca82142011-05-03 00:46:49 +0000[diff] [blame]298 /// isLegalAddImmediate - Return true if the specified immediate is legal
299 /// add immediate, that is the target has add instructions which can
300 /// add a register and the immediate without having to materialize
301 /// the immediate into a register.
302 virtual bool isLegalAddImmediate(int64_t Imm) const;
303
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]304 /// getPreIndexedAddressParts - returns true by value, base pointer and
305 /// offset pointer and addressing mode by reference if the node's address
306 /// can be legally represented as pre-indexed load / store address.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]307 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
308 SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]309 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]310 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]311
312 /// getPostIndexedAddressParts - returns true by value, base pointer and
313 /// offset pointer and addressing mode by reference if this node can be
314 /// combined with a load / store to form a post-indexed load / store.
315 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]316 SDValue &Base, SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]317 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]318 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]319
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]320 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]321 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]322 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]323 const SelectionDAG &DAG,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]324 unsigned Depth) const;
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]325
326
Evan Cheng55d42002011-01-08 01:24:27 +0000[diff] [blame]327 virtual bool ExpandInlineAsm(CallInst *CI) const;
328
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]329 ConstraintType getConstraintType(const std::string &Constraint) const;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]330
331 /// Examine constraint string and operand type and determine a weight value.
332 /// The operand object must already have been set up with the operand type.
333 ConstraintWeight getSingleConstraintMatchWeight(
334 AsmOperandInfo &info, const char *constraint) const;
335
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]336 std::pair<unsigned, const TargetRegisterClass*>
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]337 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]338 EVT VT) const;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]339
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]340 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
341 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
342 /// true it means one of the asm constraint of the inline asm instruction
343 /// being processed is 'm'.
344 virtual void LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]345 std::string &Constraint,
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]346 std::vector<SDValue> &Ops,
347 SelectionDAG &DAG) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]348
Dan Gohman419e4f92010-05-11 16:21:03 +0000[diff] [blame]349 const ARMSubtarget* getSubtarget() const {
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]350 return Subtarget;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]351 }
352
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]353 /// getRegClassFor - Return the register class that should be used for the
354 /// specified value type.
Craig Topper44d23822012-02-22 05:59:10 +0000[diff] [blame]355 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]356
Anton Korobeynikovcec36f42010-07-24 21:52:08 +0000[diff] [blame]357 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
358 /// be used for loads / stores from the global.
359 virtual unsigned getMaximalGlobalOffset() const;
360
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]361 /// createFastISel - This method returns a target specific FastISel object,
362 /// or null if the target does not support "fast" ISel.
363 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
364
Evan Cheng1cc39842010-05-20 23:26:43 +0000[diff] [blame]365 Sched::Preference getSchedulingPreference(SDNode *N) const;
366
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +0000[diff] [blame]367 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
Anton Korobeynikov48e19352009-09-23 19:04:09 +0000[diff] [blame]368 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]369
370 /// isFPImmLegal - Returns true if the target can instruction select the
371 /// specified FP immediate natively. If false, the legalizer will
372 /// materialize the FP immediate as a load from a constant pool.
373 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
374
Bob Wilson65ffec42010-09-21 17:56:22 +0000[diff] [blame]375 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
376 const CallInst &I,
377 unsigned Intrinsic) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]378 protected:
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]379 std::pair<const TargetRegisterClass*, uint8_t>
380 findRepresentativeClass(EVT VT) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]381
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]382 private:
383 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
384 /// make the right decision when generating code for different targets.
385 const ARMSubtarget *Subtarget;
386
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]387 const TargetRegisterInfo *RegInfo;
388
Evan Cheng3ef1c872010-09-10 01:29:16 +0000[diff] [blame]389 const InstrItineraryData *Itins;
390
Bob Wilsond2559bf2009-07-13 18:11:36 +0000[diff] [blame]391 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]392 ///
393 unsigned ARMPCLabelIndex;
394
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]395 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
396 void addDRTypeForNEON(EVT VT);
397 void addQRTypeForNEON(EVT VT);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]398
399 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]400 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]401 SDValue Chain, SDValue &Arg,
402 RegsToPassVector &RegsToPass,
403 CCValAssign &VA, CCValAssign &NextVA,
404 SDValue &StackPtr,
405 SmallVector<SDValue, 8> &MemOpChains,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]406 ISD::ArgFlagsTy Flags) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]407 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]408 SDValue &Root, SelectionDAG &DAG,
409 DebugLoc dl) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]410
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]411 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
412 bool isVarArg) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]413 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
414 DebugLoc dl, SelectionDAG &DAG,
415 const CCValAssign &VA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]416 ISD::ArgFlagsTy Flags) const;
Jim Grosbach23ff7cf2010-05-26 20:22:18 +0000[diff] [blame]417 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5eb19512010-05-22 01:06:18 +0000[diff] [blame]418 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha87ded22010-02-08 23:22:00 +0000[diff] [blame]419 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]420 const ARMSubtarget *Subtarget) const;
421 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]425 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]426 SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]427 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Hans Wennborgfd5abd52012-05-04 09:40:39 +0000[diff] [blame]428 SelectionDAG &DAG,
429 TLSModel::Model model) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]430 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
431 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Bill Wendlingde2b1512010-08-11 08:43:16 +0000[diff] [blame]432 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]433 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
434 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng515fe3a2010-07-08 02:08:50 +0000[diff] [blame]435 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng2457f2c2010-05-22 01:47:14 +0000[diff] [blame]436 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]437 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]438 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemand1fb5832010-08-03 21:31:55 +0000[diff] [blame]440 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Lang Hames45b5f882012-03-15 18:49:02 +0000[diff] [blame]441 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
442 const ARMSubtarget *ST) const;
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]443 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Bob Wilson11a1dff2011-01-07 21:37:30 +0000[diff] [blame]444 const ARMSubtarget *ST) const;
445
446 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola7b73a5d2007-10-19 14:35:17 +0000[diff] [blame]447
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]448 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]449 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]450 const SmallVectorImpl<ISD::InputArg> &Ins,
451 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]452 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]453
454 virtual SDValue
455 LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]456 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]457 const SmallVectorImpl<ISD::InputArg> &Ins,
458 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]459 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]460
Stuart Hastingsc7315872011-04-20 16:47:52 +0000[diff] [blame]461 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
462 DebugLoc dl, SDValue &Chain, unsigned ArgOffset)
463 const;
464
465 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
466 unsigned &VARegSize, unsigned &VARegSaveSize) const;
467
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]468 virtual SDValue
Justin Holewinskid2ea0e12012-05-25 16:35:28 +0000[diff] [blame]469 LowerCall(TargetLowering::CallLoweringInfo &CLI,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]470 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]471
Stuart Hastingsf222e592011-02-28 17:17:53 +0000[diff] [blame]472 /// HandleByVal - Target-specific cleanup for ByVal support.
Stuart Hastingsc7315872011-04-20 16:47:52 +0000[diff] [blame]473 virtual void HandleByVal(CCState *, unsigned &) const;
Stuart Hastingsf222e592011-02-28 17:17:53 +0000[diff] [blame]474
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]475 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
476 /// for tail call optimization. Targets which want to do tail call
477 /// optimization should implement this function.
478 bool IsEligibleForTailCallOptimization(SDValue Callee,
479 CallingConv::ID CalleeCC,
480 bool isVarArg,
481 bool isCalleeStructRet,
482 bool isCallerStructRet,
483 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]484 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]485 const SmallVectorImpl<ISD::InputArg> &Ins,
486 SelectionDAG& DAG) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]487 virtual SDValue
488 LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]489 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]490 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]491 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]492 DebugLoc dl, SelectionDAG &DAG) const;
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]493
Evan Chengbf010eb2012-04-10 01:51:00 +0000[diff] [blame]494 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
Evan Cheng3d2125c2010-11-30 23:55:39 +0000[diff] [blame]495
Evan Cheng485fafc2011-03-21 01:19:09 +0000[diff] [blame]496 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
497
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]498 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]499 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
500 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
501 SelectionDAG &DAG, DebugLoc dl) const;
Bob Wilson79f56c92011-03-08 01:17:20 +0000[diff] [blame]502 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]503
504 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]505
Jim Grosbache801dc42009-12-12 01:40:06 +0000[diff] [blame]506 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
507 MachineBasicBlock *BB,
508 unsigned Size) const;
509 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
510 MachineBasicBlock *BB,
511 unsigned Size,
512 unsigned BinOpcode) const;
Eli Friedman2bdffe42011-08-31 00:31:29 +0000[diff] [blame]513 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
514 MachineBasicBlock *BB,
515 unsigned Op1,
516 unsigned Op2,
Eli Friedman4d3f3292011-08-31 17:52:22 +0000[diff] [blame]517 bool NeedsCarry = false,
518 bool IsCmpxchg = false) const;
Jim Grosbachf7da8822011-04-26 19:44:18 +0000[diff] [blame]519 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
520 MachineBasicBlock *BB,
521 unsigned Size,
522 bool signExtend,
523 ARMCC::CondCodes Cond) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]524
Bill Wendlinge29fa1d2011-10-06 22:18:16 +0000[diff] [blame]525 void SetupEntryBlockForSjLj(MachineInstr *MI,
526 MachineBasicBlock *MBB,
527 MachineBasicBlock *DispatchBB, int FI) const;
528
Bill Wendlingf7e4aef2011-10-03 21:25:38 +0000[diff] [blame]529 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
530 MachineBasicBlock *MBB) const;
531
Andrew Trick1c3af772011-04-23 03:55:32 +0000[diff] [blame]532 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]533 };
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]534
Owen Anderson36fa3ea2010-11-05 21:57:54 +0000[diff] [blame]535 enum NEONModImmType {
536 VMOVModImm,
537 VMVNModImm,
538 OtherModImm
539 };
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]540
541
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]542 namespace ARM {
543 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
544 }
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]545}
546
547#endif // ARMISELLOWERING_H