Blame - drivers/irqchip/Kconfig - kernel/msm-4.19

blob: d1f43cb92e4d8905ed4300d79566274848df57a7 [file] [log] [blame]

Thomas Petazzoni	f6e916b	2012-11-20 23:00:52 +0100	[diff] [blame]	1	config IRQCHIP
				2	def_bool y
				3	depends on OF_IRQ
				4
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	5	config ARM_GIC
				6	bool
				7	select IRQ_DOMAIN
Yingjoe Chen	9a1091e	2014-11-25 16:04:19 +0800	[diff] [blame]	8	select IRQ_DOMAIN_HIERARCHY
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	9	select MULTI_IRQ_HANDLER
				10
Jon Hunter	9c8eddd	2016-06-07 16:12:34 +0100	[diff] [blame]	11	config ARM_GIC_PM
				12	bool
				13	depends on PM
				14	select ARM_GIC
				15	select PM_CLK
				16
Linus Walleij	a27d21e	2015-12-18 10:44:53 +0100	[diff] [blame]	17	config ARM_GIC_MAX_NR
				18	int
				19	default 2 if ARCH_REALVIEW
				20	default 1
				21
Suravee Suthikulpanit	853a33c	2014-11-25 18:47:22 +0000	[diff] [blame]	22	config ARM_GIC_V2M
				23	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	24	depends on PCI
				25	select ARM_GIC
				26	select PCI_MSI
Suravee Suthikulpanit	853a33c	2014-11-25 18:47:22 +0000	[diff] [blame]	27
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	28	config GIC_NON_BANKED
				29	bool
				30
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	31	config ARM_GIC_V3
				32	bool
				33	select IRQ_DOMAIN
				34	select MULTI_IRQ_HANDLER
Marc Zyngier	443acc4	2014-11-24 14:35:09 +0000	[diff] [blame]	35	select IRQ_DOMAIN_HIERARCHY
Marc Zyngier	e3825ba	2016-04-11 09:57:54 +0100	[diff] [blame]	36	select PARTITION_PERCPU
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	37
Marc Zyngier	1981272	2014-11-24 14:35:19 +0000	[diff] [blame]	38	config ARM_GIC_V3_ITS
				39	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	40	depends on PCI
				41	depends on PCI_MSI
Uwe Kleine-König	292ec08	2013-06-26 09:18:48 +0200	[diff] [blame]	42
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	43	config ARM_NVIC
				44	bool
				45	select IRQ_DOMAIN
Stefan Agner	2d9f59f	2015-05-16 11:44:16 +0200	[diff] [blame]	46	select IRQ_DOMAIN_HIERARCHY
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	47	select GENERIC_IRQ_CHIP
				48
				49	config ARM_VIC
				50	bool
				51	select IRQ_DOMAIN
				52	select MULTI_IRQ_HANDLER
				53
				54	config ARM_VIC_NR
				55	int
				56	default 4 if ARCH_S5PV210
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	57	default 2
				58	depends on ARM_VIC
				59	help
				60	The maximum number of VICs available in the system, for
				61	power management.
				62
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	63	config ARMADA_370_XP_IRQ
				64	bool
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	65	select GENERIC_IRQ_CHIP
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	66	select PCI_MSI if PCI
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	67
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	68	config ALPINE_MSI
				69	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	70	depends on PCI
				71	select PCI_MSI
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	72	select GENERIC_IRQ_CHIP
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	73
Boris BREZILLON	b1479eb	2014-07-10 19:14:18 +0200	[diff] [blame]	74	config ATMEL_AIC_IRQ
				75	bool
				76	select GENERIC_IRQ_CHIP
				77	select IRQ_DOMAIN
				78	select MULTI_IRQ_HANDLER
				79	select SPARSE_IRQ
				80
				81	config ATMEL_AIC5_IRQ
				82	bool
				83	select GENERIC_IRQ_CHIP
				84	select IRQ_DOMAIN
				85	select MULTI_IRQ_HANDLER
				86	select SPARSE_IRQ
				87
Ralf Baechle	0509cfd	2015-07-08 14:46:08 +0200	[diff] [blame]	88	config I8259
				89	bool
				90	select IRQ_DOMAIN
				91
Simon Arlott	c7c42ec	2015-11-22 14:30:14 +0000	[diff] [blame]	92	config BCM6345_L1_IRQ
				93	bool
				94	select GENERIC_IRQ_CHIP
				95	select IRQ_DOMAIN
				96
Kevin Cernekee	5f7f031	2014-12-25 09:49:06 -0800	[diff] [blame]	97	config BCM7038_L1_IRQ
				98	bool
				99	select GENERIC_IRQ_CHIP
				100	select IRQ_DOMAIN
				101
Kevin Cernekee	a4fcbb8	2014-11-06 22:44:27 -0800	[diff] [blame]	102	config BCM7120_L2_IRQ
				103	bool
				104	select GENERIC_IRQ_CHIP
				105	select IRQ_DOMAIN
				106
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	107	config BRCMSTB_L2_IRQ
				108	bool
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	109	select GENERIC_IRQ_CHIP
				110	select IRQ_DOMAIN
				111
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	112	config DW_APB_ICTL
				113	bool
Jisheng Zhang	e158849	2014-10-22 20:59:10 +0800	[diff] [blame]	114	select GENERIC_IRQ_CHIP
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	115	select IRQ_DOMAIN
				116
Linus Walleij	6ee532e	2017-03-18 17:53:24 +0100	[diff] [blame]	117	config FARADAY_FTINTC010
				118	bool
				119	select IRQ_DOMAIN
				120	select MULTI_IRQ_HANDLER
				121	select SPARSE_IRQ
				122
MaJun	9a7c4ab	2016-03-23 17:06:33 +0800	[diff] [blame]	123	config HISILICON_IRQ_MBIGEN
				124	bool
				125	select ARM_GIC_V3
				126	select ARM_GIC_V3_ITS
MaJun	9a7c4ab	2016-03-23 17:06:33 +0800	[diff] [blame]	127
James Hogan	b6ef916	2013-04-22 15:43:50 +0100	[diff] [blame]	128	config IMGPDC_IRQ
				129	bool
				130	select GENERIC_IRQ_CHIP
				131	select IRQ_DOMAIN
				132
Ralf Baechle	67e38cf	2015-05-26 18:20:06 +0200	[diff] [blame]	133	config IRQ_MIPS_CPU
				134	bool
				135	select GENERIC_IRQ_CHIP
Paul Burton	3838a54	2017-03-30 12:06:11 -0700	[diff] [blame]	136	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
Ralf Baechle	67e38cf	2015-05-26 18:20:06 +0200	[diff] [blame]	137	select IRQ_DOMAIN
Paul Burton	3838a54	2017-03-30 12:06:11 -0700	[diff] [blame]	138	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
Ralf Baechle	67e38cf	2015-05-26 18:20:06 +0200	[diff] [blame]	139
Alexander Shiyan	afc98d9	2014-02-02 12:07:46 +0400	[diff] [blame]	140	config CLPS711X_IRQCHIP
				141	bool
				142	depends on ARCH_CLPS711X
				143	select IRQ_DOMAIN
				144	select MULTI_IRQ_HANDLER
				145	select SPARSE_IRQ
				146	default y
				147
Stefan Kristiansson	4db8e6d	2014-05-26 23:31:42 +0300	[diff] [blame]	148	config OR1K_PIC
				149	bool
				150	select IRQ_DOMAIN
				151
Felipe Balbi	8598066	2014-09-15 16:15:02 -0500	[diff] [blame]	152	config OMAP_IRQCHIP
				153	bool
				154	select GENERIC_IRQ_CHIP
				155	select IRQ_DOMAIN
				156
Sebastian Hesselbarth	9dbd90f	2013-06-06 18:27:09 +0200	[diff] [blame]	157	config ORION_IRQCHIP
				158	bool
				159	select IRQ_DOMAIN
				160	select MULTI_IRQ_HANDLER
				161
Cristian Birsan	aaa8666	2016-01-13 18:15:35 -0700	[diff] [blame]	162	config PIC32_EVIC
				163	bool
				164	select GENERIC_IRQ_CHIP
				165	select IRQ_DOMAIN
				166
Rich Felker	981b58f	2016-08-04 04:30:37 +0000	[diff] [blame]	167	config JCORE_AIC
Rich Felker	3602ffd	2016-10-19 17:53:52 +0000	[diff] [blame]	168	bool "J-Core integrated AIC" if COMPILE_TEST
				169	depends on OF
Rich Felker	981b58f	2016-08-04 04:30:37 +0000	[diff] [blame]	170	select IRQ_DOMAIN
				171	help
				172	Support for the J-Core integrated AIC.
				173
Magnus Damm	4435804	2013-02-18 23:28:34 +0900	[diff] [blame]	174	config RENESAS_INTC_IRQPIN
				175	bool
				176	select IRQ_DOMAIN
				177
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	178	config RENESAS_IRQC
				179	bool
Magnus Damm	99c221d	2015-09-28 18:42:37 +0900	[diff] [blame]	180	select GENERIC_IRQ_CHIP
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	181	select IRQ_DOMAIN
				182
Lee Jones	0708848	2015-02-18 15:13:58 +0000	[diff] [blame]	183	config ST_IRQCHIP
				184	bool
				185	select REGMAP
				186	select MFD_SYSCON
				187	help
				188	Enables SysCfg Controlled IRQs on STi based platforms.
				189
Mans Rullgard	4bba668	2016-01-20 18:07:17 +0000	[diff] [blame]	190	config TANGO_IRQ
				191	bool
				192	select IRQ_DOMAIN
				193	select GENERIC_IRQ_CHIP
				194
Christian Ruppert	b06eb01	2013-06-25 18:29:57 +0200	[diff] [blame]	195	config TB10X_IRQC
				196	bool
				197	select IRQ_DOMAIN
				198	select GENERIC_IRQ_CHIP
				199
Damien Riegel	d01f863	2015-12-21 15:11:23 -0500	[diff] [blame]	200	config TS4800_IRQ
				201	tristate "TS-4800 IRQ controller"
				202	select IRQ_DOMAIN
Richard Weinberger	0df337c	2016-01-25 23:24:17 +0100	[diff] [blame]	203	depends on HAS_IOMEM
Jean Delvare	d2b383d	2016-02-09 11:19:20 +0100	[diff] [blame]	204	depends on SOC_IMX51 \|\| COMPILE_TEST
Damien Riegel	d01f863	2015-12-21 15:11:23 -0500	[diff] [blame]	205	help
				206	Support for the TS-4800 FPGA IRQ controller
				207
Linus Walleij	2389d50	2012-10-31 22:04:31 +0100	[diff] [blame]	208	config VERSATILE_FPGA_IRQ
				209	bool
				210	select IRQ_DOMAIN
				211
				212	config VERSATILE_FPGA_IRQ_NR
				213	int
				214	default 4
				215	depends on VERSATILE_FPGA_IRQ
Max Filippov	26a8e96	2013-12-01 12:04:57 +0400	[diff] [blame]	216
				217	config XTENSA_MX
				218	bool
				219	select IRQ_DOMAIN
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	220
Zubair Lutfullah Kakakhel	0547dc7	2016-11-14 12:13:45 +0000	[diff] [blame]	221	config XILINX_INTC
				222	bool
				223	select IRQ_DOMAIN
				224
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	225	config IRQ_CROSSBAR
				226	bool
				227	help
Masanari Iida	f54619f	2014-09-18 12:09:42 +0900	[diff] [blame]	228	Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	229	The primary irqchip invokes the crossbar's callback which inturn allocates
				230	a free irq and configures the IP. Thus the peripheral interrupts are
				231	routed to one of the free irqchip interrupt lines.
Grygorii Strashko	89323f8	2014-07-23 17:40:30 +0300	[diff] [blame]	232
				233	config KEYSTONE_IRQ
				234	tristate "Keystone 2 IRQ controller IP"
				235	depends on ARCH_KEYSTONE
				236	help
				237	Support for Texas Instruments Keystone 2 IRQ controller IP which
				238	is part of the Keystone 2 IPC mechanism
Andrew Bresticker	8a19b8f	2014-09-18 14:47:19 -0700	[diff] [blame]	239
				240	config MIPS_GIC
				241	bool
Qais Yousef	bb11cff	2015-12-08 13:20:28 +0000	[diff] [blame]	242	select GENERIC_IRQ_IPI
Qais Yousef	2af70a9	2015-12-08 13:20:23 +0000	[diff] [blame]	243	select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker	8a19b8f	2014-09-18 14:47:19 -0700	[diff] [blame]	244	select MIPS_CM
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	245
Paul Burton	44e08e7	2015-05-24 16:11:31 +0100	[diff] [blame]	246	config INGENIC_IRQ
				247	bool
				248	depends on MACH_INGENIC
				249	default y
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	250
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	251	config RENESAS_H8300H_INTC
				252	bool
				253	select IRQ_DOMAIN
				254
				255	config RENESAS_H8S_INTC
				256	bool
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	257	select IRQ_DOMAIN
Shenwei Wang	e324c4d	2015-08-24 14:04:15 -0500	[diff] [blame]	258
				259	config IMX_GPCV2
				260	bool
				261	select IRQ_DOMAIN
				262	help
				263	Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel	7e4ac67	2015-10-12 21:15:34 +0200	[diff] [blame]	264
				265	config IRQ_MXS
				266	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
				267	select IRQ_DOMAIN
				268	select STMP_DEVICE
Thomas Petazzoni	c27f29b	2016-02-19 14:34:43 +0100	[diff] [blame]	269
Thomas Petazzoni	a68a63c	2017-06-21 15:29:14 +0200	[diff] [blame]	270	config MVEBU_GICP
				271	bool
				272
Thomas Petazzoni	e0de91a	2017-06-21 15:29:15 +0200	[diff] [blame]	273	config MVEBU_ICU
				274	bool
				275
Thomas Petazzoni	c27f29b	2016-02-19 14:34:43 +0100	[diff] [blame]	276	config MVEBU_ODMI
				277	bool
Arnd Bergmann	fa23b9d	2017-03-14 13:54:12 +0100	[diff] [blame]	278	select GENERIC_MSI_IRQ_DOMAIN
Marc Zyngier	9e2c986	2016-04-11 09:57:53 +0100	[diff] [blame]	279
Thomas Petazzoni	a109893	2016-08-05 16:55:19 +0200	[diff] [blame]	280	config MVEBU_PIC
				281	bool
				282
Minghuan Lian	b8f3ebe	2016-03-23 19:08:20 +0800	[diff] [blame]	283	config LS_SCFG_MSI
				284	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
				285	depends on PCI && PCI_MSI
Minghuan Lian	b8f3ebe	2016-03-23 19:08:20 +0800	[diff] [blame]	286
Marc Zyngier	9e2c986	2016-04-11 09:57:53 +0100	[diff] [blame]	287	config PARTITION_PERCPU
				288	bool
Linus Torvalds	0efacbb	2016-05-19 09:46:18 -0700	[diff] [blame]	289
Noam Camus	44df427c	2015-10-29 00:26:22 +0200	[diff] [blame]	290	config EZNPS_GIC
				291	bool "NPS400 Global Interrupt Manager (GIM)"
Arnd Bergmann	ffd565e	2016-05-12 23:03:35 +0200	[diff] [blame]	292	depends on ARC \|\| (COMPILE_TEST && !64BIT)
Noam Camus	44df427c	2015-10-29 00:26:22 +0200	[diff] [blame]	293	select IRQ_DOMAIN
				294	help
				295	Support the EZchip NPS400 global interrupt controller
Alexandre TORGUE	e0720416	2016-09-20 18:00:57 +0200	[diff] [blame]	296
				297	config STM32_EXTI
				298	bool
				299	select IRQ_DOMAIN
Agustin Vega-Frias	f20cc9b	2017-02-02 18:23:59 -0500	[diff] [blame]	300
				301	config QCOM_IRQ_COMBINER
				302	bool "QCOM IRQ combiner support"
				303	depends on ARCH_QCOM && ACPI
				304	select IRQ_DOMAIN
				305	select IRQ_DOMAIN_HIERARCHY
				306	help
				307	Say yes here to add support for the IRQ combiner devices embedded
				308	in Qualcomm Technologies chips.
Masahiro Yamada	5ed34d3	2017-08-23 10:31:47 +0900	[diff] [blame^]	309
				310	config IRQ_UNIPHIER_AIDET
				311	bool "UniPhier AIDET support" if COMPILE_TEST
				312	depends on ARCH_UNIPHIER \|\| COMPILE_TEST
				313	default ARCH_UNIPHIER
				314	select IRQ_DOMAIN_HIERARCHY
				315	help
				316	Support for the UniPhier AIDET (ARM Interrupt Detector).