blob: f39cae620f61568688c79415c6dbf9ebbf96ff90 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
Ayaz Abdulla87046e52006-12-19 23:33:32 -05006 * and Andrew de Quincey.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
Manfred Spraul18360982005-12-24 14:19:24 +010012 * Copyright (C) 2003,4,5 Manfred Spraul
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
Ayaz Abdullaf1405d322009-01-09 11:03:54 +000016 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
Jeff Kirsher0ab75ae2013-12-06 06:28:43 -080029 * along with this program; if not, see <http://www.gnu.org/licenses/>.
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070031 * Known bugs:
32 * We suspect that on some hardware no TX done interrupts are generated.
33 * This means recovery from netif_stop_queue only happens if the hw timer
34 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
35 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
36 * If your hardware reliably generates tx done interrupts, then you can remove
37 * DEV_NEED_TIMERIRQ from the driver_data flags.
38 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
39 * superfluous timer interrupts from the nic.
40 */
Joe Perches294a5542010-11-29 07:41:56 +000041
42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
Ayaz Abdulla3e1a3ce2009-03-05 08:02:38 +000044#define FORCEDETH_VERSION "0.64"
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#define DRV_NAME "forcedeth"
46
47#include <linux/module.h>
48#include <linux/types.h>
49#include <linux/pci.h>
50#include <linux/interrupt.h>
51#include <linux/netdevice.h>
52#include <linux/etherdevice.h>
53#include <linux/delay.h>
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040054#include <linux/sched.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070055#include <linux/spinlock.h>
56#include <linux/ethtool.h>
57#include <linux/timer.h>
58#include <linux/skbuff.h>
59#include <linux/mii.h>
60#include <linux/random.h>
Manfred Spraul22c6d142005-04-19 21:17:09 +020061#include <linux/if_vlan.h>
Matthias Gehre910638a2006-03-28 01:56:48 -080062#include <linux/dma-mapping.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090063#include <linux/slab.h>
Szymon Janc5504e132010-11-27 08:39:45 +000064#include <linux/uaccess.h>
Paul Gortmaker70c71602011-05-22 16:47:17 -040065#include <linux/prefetch.h>
david decotignyf5d827a2011-11-16 12:15:13 +000066#include <linux/u64_stats_sync.h>
67#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070068
69#include <asm/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070070
Stephen Hemmingerbea33482007-10-03 16:41:36 -070071#define TX_WORK_PER_LOOP 64
72#define RX_WORK_PER_LOOP 64
Linus Torvalds1da177e2005-04-16 15:20:36 -070073
74/*
75 * Hardware access:
76 */
77
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +000078#define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
79#define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
80#define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
81#define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
82#define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
83#define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
84#define DEV_HAS_MSI 0x0000040 /* device supports MSI */
85#define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
86#define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
87#define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
Mike Ditto7b5e0782010-07-25 21:54:28 -070088#define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
89#define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
90#define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
91#define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +000092#define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
93#define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
94#define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
95#define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
96#define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
97#define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
98#define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
99#define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
100#define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
101#define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
102#define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
103#define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
104#define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
106enum {
107 NvRegIrqStatus = 0x000,
108#define NVREG_IRQSTAT_MIIEVENT 0x040
Ayaz Abdulladaa91a92009-02-07 00:25:00 -0800109#define NVREG_IRQSTAT_MASK 0x83ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110 NvRegIrqMask = 0x004,
111#define NVREG_IRQ_RX_ERROR 0x0001
112#define NVREG_IRQ_RX 0x0002
113#define NVREG_IRQ_RX_NOBUF 0x0004
114#define NVREG_IRQ_TX_ERR 0x0008
Manfred Spraulc2dba062005-07-31 18:29:47 +0200115#define NVREG_IRQ_TX_OK 0x0010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116#define NVREG_IRQ_TIMER 0x0020
117#define NVREG_IRQ_LINK 0x0040
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500118#define NVREG_IRQ_RX_FORCED 0x0080
119#define NVREG_IRQ_TX_FORCED 0x0100
Ayaz Abdulladaa91a92009-02-07 00:25:00 -0800120#define NVREG_IRQ_RECOVER_ERROR 0x8200
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500121#define NVREG_IRQMASK_THROUGHPUT 0x00df
Ayaz Abdulla096a4582007-05-21 20:23:11 -0400122#define NVREG_IRQMASK_CPU 0x0060
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500123#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
124#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500125#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200126
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127 NvRegUnknownSetupReg6 = 0x008,
128#define NVREG_UNKSETUP6_VAL 3
129
130/*
131 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
132 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
133 */
134 NvRegPollingInterval = 0x00c,
Ayaz Abdulla6cef67a2009-03-05 08:02:30 +0000135#define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500136#define NVREG_POLL_DEFAULT_CPU 13
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500137 NvRegMSIMap0 = 0x020,
138 NvRegMSIMap1 = 0x024,
139 NvRegMSIIrqMask = 0x030,
140#define NVREG_MSI_VECTOR_0_ENABLED 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141 NvRegMisc1 = 0x080,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400142#define NVREG_MISC1_PAUSE_TX 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143#define NVREG_MISC1_HD 0x02
144#define NVREG_MISC1_FORCE 0x3b0f3c
145
Ayaz Abdulla0a626772008-01-13 16:02:42 -0500146 NvRegMacReset = 0x34,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400147#define NVREG_MAC_RESET_ASSERT 0x0F3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148 NvRegTransmitterControl = 0x084,
149#define NVREG_XMITCTL_START 0x01
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500150#define NVREG_XMITCTL_MGMT_ST 0x40000000
151#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
152#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
153#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
154#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
155#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
156#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
157#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
158#define NVREG_XMITCTL_HOST_LOADED 0x00004000
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500159#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800160#define NVREG_XMITCTL_DATA_START 0x00100000
161#define NVREG_XMITCTL_DATA_READY 0x00010000
162#define NVREG_XMITCTL_DATA_ERROR 0x00020000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163 NvRegTransmitterStatus = 0x088,
164#define NVREG_XMITSTAT_BUSY 0x01
165
166 NvRegPacketFilterFlags = 0x8c,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400167#define NVREG_PFF_PAUSE_RX 0x08
168#define NVREG_PFF_ALWAYS 0x7F0000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169#define NVREG_PFF_PROMISC 0x80
170#define NVREG_PFF_MYADDR 0x20
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400171#define NVREG_PFF_LOOPBACK 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172
173 NvRegOffloadConfig = 0x90,
174#define NVREG_OFFLOAD_HOMEPHY 0x601
175#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
176 NvRegReceiverControl = 0x094,
177#define NVREG_RCVCTL_START 0x01
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500178#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 NvRegReceiverStatus = 0x98,
180#define NVREG_RCVSTAT_BUSY 0x01
181
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700182 NvRegSlotTime = 0x9c,
183#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
184#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
Szymon Janc78aea4f2010-11-27 08:39:43 +0000185#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700186#define NVREG_SLOTTIME_HALF 0x0000ff00
Szymon Janc78aea4f2010-11-27 08:39:43 +0000187#define NVREG_SLOTTIME_DEFAULT 0x00007f00
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700188#define NVREG_SLOTTIME_MASK 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400190 NvRegTxDeferral = 0xA0,
Ayaz Abdullafd9b5582008-02-05 12:29:49 -0500191#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
192#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
193#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
194#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
195#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
196#define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400197 NvRegRxDeferral = 0xA4,
198#define NVREG_RX_DEFERRAL_DEFAULT 0x16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199 NvRegMacAddrA = 0xA8,
200 NvRegMacAddrB = 0xAC,
201 NvRegMulticastAddrA = 0xB0,
202#define NVREG_MCASTADDRA_FORCE 0x01
203 NvRegMulticastAddrB = 0xB4,
204 NvRegMulticastMaskA = 0xB8,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500205#define NVREG_MCASTMASKA_NONE 0xffffffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206 NvRegMulticastMaskB = 0xBC,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500207#define NVREG_MCASTMASKB_NONE 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208
209 NvRegPhyInterface = 0xC0,
210#define PHY_RGMII 0x10000000
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700211 NvRegBackOffControl = 0xC4,
212#define NVREG_BKOFFCTRL_DEFAULT 0x70000000
213#define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
214#define NVREG_BKOFFCTRL_SELECT 24
215#define NVREG_BKOFFCTRL_GEAR 12
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216
217 NvRegTxRingPhysAddr = 0x100,
218 NvRegRxRingPhysAddr = 0x104,
219 NvRegRingSizes = 0x108,
220#define NVREG_RINGSZ_TXSHIFT 0
221#define NVREG_RINGSZ_RXSHIFT 16
Ayaz Abdulla5070d342006-07-31 12:05:01 -0400222 NvRegTransmitPoll = 0x10c,
223#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 NvRegLinkSpeed = 0x110,
225#define NVREG_LINKSPEED_FORCE 0x10000
226#define NVREG_LINKSPEED_10 1000
227#define NVREG_LINKSPEED_100 100
228#define NVREG_LINKSPEED_1000 50
229#define NVREG_LINKSPEED_MASK (0xFFF)
230 NvRegUnknownSetupReg5 = 0x130,
231#define NVREG_UNKSETUP5_BIT31 (1<<31)
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400232 NvRegTxWatermark = 0x13c,
233#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
234#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
235#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236 NvRegTxRxControl = 0x144,
237#define NVREG_TXRXCTL_KICK 0x0001
238#define NVREG_TXRXCTL_BIT1 0x0002
239#define NVREG_TXRXCTL_BIT2 0x0004
240#define NVREG_TXRXCTL_IDLE 0x0008
241#define NVREG_TXRXCTL_RESET 0x0010
242#define NVREG_TXRXCTL_RXCHECK 0x0400
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400243#define NVREG_TXRXCTL_DESC_1 0
Ayaz Abdullad2f78412007-01-09 13:30:02 -0500244#define NVREG_TXRXCTL_DESC_2 0x002100
245#define NVREG_TXRXCTL_DESC_3 0xc02200
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500246#define NVREG_TXRXCTL_VLANSTRIP 0x00040
247#define NVREG_TXRXCTL_VLANINS 0x00080
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500248 NvRegTxRingPhysAddrHigh = 0x148,
249 NvRegRxRingPhysAddrHigh = 0x14C,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400250 NvRegTxPauseFrame = 0x170,
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -0500251#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
252#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
253#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
254#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
Ayaz Abdulla9a33e882008-08-06 12:12:34 -0400255 NvRegTxPauseFrameLimit = 0x174,
256#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257 NvRegMIIStatus = 0x180,
258#define NVREG_MIISTAT_ERROR 0x0001
259#define NVREG_MIISTAT_LINKCHANGE 0x0008
Ayaz Abdullaeb798422008-02-04 15:14:04 -0500260#define NVREG_MIISTAT_MASK_RW 0x0007
261#define NVREG_MIISTAT_MASK_ALL 0x000f
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500262 NvRegMIIMask = 0x184,
263#define NVREG_MII_LINKCHANGE 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264
265 NvRegAdapterControl = 0x188,
266#define NVREG_ADAPTCTL_START 0x02
267#define NVREG_ADAPTCTL_LINKUP 0x04
268#define NVREG_ADAPTCTL_PHYVALID 0x40000
269#define NVREG_ADAPTCTL_RUNNING 0x100000
270#define NVREG_ADAPTCTL_PHYSHIFT 24
271 NvRegMIISpeed = 0x18c,
272#define NVREG_MIISPEED_BIT8 (1<<8)
273#define NVREG_MIIDELAY 5
274 NvRegMIIControl = 0x190,
275#define NVREG_MIICTL_INUSE 0x08000
276#define NVREG_MIICTL_WRITE 0x00400
277#define NVREG_MIICTL_ADDRSHIFT 5
278 NvRegMIIData = 0x194,
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400279 NvRegTxUnicast = 0x1a0,
280 NvRegTxMulticast = 0x1a4,
281 NvRegTxBroadcast = 0x1a8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 NvRegWakeUpFlags = 0x200,
283#define NVREG_WAKEUPFLAGS_VAL 0x7770
284#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
285#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
286#define NVREG_WAKEUPFLAGS_D3SHIFT 12
287#define NVREG_WAKEUPFLAGS_D2SHIFT 8
288#define NVREG_WAKEUPFLAGS_D1SHIFT 4
289#define NVREG_WAKEUPFLAGS_D0SHIFT 0
290#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
291#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
292#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
293#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
294
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800295 NvRegMgmtUnitGetVersion = 0x204,
Szymon Janc78aea4f2010-11-27 08:39:43 +0000296#define NVREG_MGMTUNITGETVERSION 0x01
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800297 NvRegMgmtUnitVersion = 0x208,
298#define NVREG_MGMTUNITVERSION 0x08
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 NvRegPowerCap = 0x268,
300#define NVREG_POWERCAP_D3SUPP (1<<30)
301#define NVREG_POWERCAP_D2SUPP (1<<26)
302#define NVREG_POWERCAP_D1SUPP (1<<25)
303 NvRegPowerState = 0x26c,
304#define NVREG_POWERSTATE_POWEREDUP 0x8000
305#define NVREG_POWERSTATE_VALID 0x0100
306#define NVREG_POWERSTATE_MASK 0x0003
307#define NVREG_POWERSTATE_D0 0x0000
308#define NVREG_POWERSTATE_D1 0x0001
309#define NVREG_POWERSTATE_D2 0x0002
310#define NVREG_POWERSTATE_D3 0x0003
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800311 NvRegMgmtUnitControl = 0x278,
312#define NVREG_MGMTUNITCONTROL_INUSE 0x20000
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400313 NvRegTxCnt = 0x280,
314 NvRegTxZeroReXmt = 0x284,
315 NvRegTxOneReXmt = 0x288,
316 NvRegTxManyReXmt = 0x28c,
317 NvRegTxLateCol = 0x290,
318 NvRegTxUnderflow = 0x294,
319 NvRegTxLossCarrier = 0x298,
320 NvRegTxExcessDef = 0x29c,
321 NvRegTxRetryErr = 0x2a0,
322 NvRegRxFrameErr = 0x2a4,
323 NvRegRxExtraByte = 0x2a8,
324 NvRegRxLateCol = 0x2ac,
325 NvRegRxRunt = 0x2b0,
326 NvRegRxFrameTooLong = 0x2b4,
327 NvRegRxOverflow = 0x2b8,
328 NvRegRxFCSErr = 0x2bc,
329 NvRegRxFrameAlignErr = 0x2c0,
330 NvRegRxLenErr = 0x2c4,
331 NvRegRxUnicast = 0x2c8,
332 NvRegRxMulticast = 0x2cc,
333 NvRegRxBroadcast = 0x2d0,
334 NvRegTxDef = 0x2d4,
335 NvRegTxFrame = 0x2d8,
336 NvRegRxCnt = 0x2dc,
337 NvRegTxPause = 0x2e0,
338 NvRegRxPause = 0x2e4,
339 NvRegRxDropFrame = 0x2e8,
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500340 NvRegVlanControl = 0x300,
341#define NVREG_VLANCONTROL_ENABLE 0x2000
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500342 NvRegMSIXMap0 = 0x3e0,
343 NvRegMSIXMap1 = 0x3e4,
344 NvRegMSIXIrqStatus = 0x3f0,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400345
346 NvRegPowerState2 = 0x600,
Ayaz Abdulla1545e202008-09-22 09:55:35 -0400347#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400348#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400349#define NVREG_POWERSTATE2_PHY_RESET 0x0004
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +0000350#define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351};
352
353/* Big endian: should work, but is untested */
354struct ring_desc {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700355 __le32 buf;
356 __le32 flaglen;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357};
358
Manfred Spraulee733622005-07-31 18:32:26 +0200359struct ring_desc_ex {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700360 __le32 bufhigh;
361 __le32 buflow;
362 __le32 txvlan;
363 __le32 flaglen;
Manfred Spraulee733622005-07-31 18:32:26 +0200364};
365
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700366union ring_type {
Szymon Janc78aea4f2010-11-27 08:39:43 +0000367 struct ring_desc *orig;
368 struct ring_desc_ex *ex;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700369};
Manfred Spraulee733622005-07-31 18:32:26 +0200370
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371#define FLAG_MASK_V1 0xffff0000
372#define FLAG_MASK_V2 0xffffc000
373#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
374#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
375
376#define NV_TX_LASTPACKET (1<<16)
377#define NV_TX_RETRYERROR (1<<19)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700378#define NV_TX_RETRYCOUNT_MASK (0xF<<20)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200379#define NV_TX_FORCED_INTERRUPT (1<<24)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380#define NV_TX_DEFERRED (1<<26)
381#define NV_TX_CARRIERLOST (1<<27)
382#define NV_TX_LATECOLLISION (1<<28)
383#define NV_TX_UNDERFLOW (1<<29)
384#define NV_TX_ERROR (1<<30)
385#define NV_TX_VALID (1<<31)
386
387#define NV_TX2_LASTPACKET (1<<29)
388#define NV_TX2_RETRYERROR (1<<18)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700389#define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200390#define NV_TX2_FORCED_INTERRUPT (1<<30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391#define NV_TX2_DEFERRED (1<<25)
392#define NV_TX2_CARRIERLOST (1<<26)
393#define NV_TX2_LATECOLLISION (1<<27)
394#define NV_TX2_UNDERFLOW (1<<28)
395/* error and valid are the same for both */
396#define NV_TX2_ERROR (1<<30)
397#define NV_TX2_VALID (1<<31)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400398#define NV_TX2_TSO (1<<28)
399#define NV_TX2_TSO_SHIFT 14
Ayaz Abdullafa454592006-01-05 22:45:45 -0800400#define NV_TX2_TSO_MAX_SHIFT 14
401#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400402#define NV_TX2_CHECKSUM_L3 (1<<27)
403#define NV_TX2_CHECKSUM_L4 (1<<26)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500405#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
406
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407#define NV_RX_DESCRIPTORVALID (1<<16)
408#define NV_RX_MISSEDFRAME (1<<17)
Antonio Ospitecef33c82014-06-04 14:03:47 +0200409#define NV_RX_SUBTRACT1 (1<<18)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410#define NV_RX_ERROR1 (1<<23)
411#define NV_RX_ERROR2 (1<<24)
412#define NV_RX_ERROR3 (1<<25)
413#define NV_RX_ERROR4 (1<<26)
414#define NV_RX_CRCERR (1<<27)
415#define NV_RX_OVERFLOW (1<<28)
416#define NV_RX_FRAMINGERR (1<<29)
417#define NV_RX_ERROR (1<<30)
418#define NV_RX_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400419#define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420
421#define NV_RX2_CHECKSUMMASK (0x1C000000)
Ayaz Abdullabfaffe82008-01-13 16:02:55 -0500422#define NV_RX2_CHECKSUM_IP (0x10000000)
423#define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
424#define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425#define NV_RX2_DESCRIPTORVALID (1<<29)
Antonio Ospitecef33c82014-06-04 14:03:47 +0200426#define NV_RX2_SUBTRACT1 (1<<25)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427#define NV_RX2_ERROR1 (1<<18)
428#define NV_RX2_ERROR2 (1<<19)
429#define NV_RX2_ERROR3 (1<<20)
430#define NV_RX2_ERROR4 (1<<21)
431#define NV_RX2_CRCERR (1<<22)
432#define NV_RX2_OVERFLOW (1<<23)
433#define NV_RX2_FRAMINGERR (1<<24)
434/* error and avail are the same for both */
435#define NV_RX2_ERROR (1<<30)
436#define NV_RX2_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400437#define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500439#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
440#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
441
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300442/* Miscellaneous hardware related defines: */
Szymon Janc78aea4f2010-11-27 08:39:43 +0000443#define NV_PCI_REGSZ_VER1 0x270
444#define NV_PCI_REGSZ_VER2 0x2d4
445#define NV_PCI_REGSZ_VER3 0x604
446#define NV_PCI_REGSZ_MAX 0x604
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447
448/* various timeout delays: all in usec */
449#define NV_TXRX_RESET_DELAY 4
450#define NV_TXSTOP_DELAY1 10
451#define NV_TXSTOP_DELAY1MAX 500000
452#define NV_TXSTOP_DELAY2 100
453#define NV_RXSTOP_DELAY1 10
454#define NV_RXSTOP_DELAY1MAX 500000
455#define NV_RXSTOP_DELAY2 100
456#define NV_SETUP5_DELAY 5
457#define NV_SETUP5_DELAYMAX 50000
458#define NV_POWERUP_DELAY 5
459#define NV_POWERUP_DELAYMAX 5000
460#define NV_MIIBUSY_DELAY 50
461#define NV_MIIPHY_DELAY 10
462#define NV_MIIPHY_DELAYMAX 10000
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400463#define NV_MAC_RESET_DELAY 64
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464
465#define NV_WAKEUPPATTERNS 5
466#define NV_WAKEUPMASKENTRIES 4
467
468/* General driver defaults */
469#define NV_WATCHDOG_TIMEO (5*HZ)
470
Ayaz Abdulla6cef67a2009-03-05 08:02:30 +0000471#define RX_RING_DEFAULT 512
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400472#define TX_RING_DEFAULT 256
473#define RX_RING_MIN 128
474#define TX_RING_MIN 64
475#define RING_MAX_DESC_VER_1 1024
476#define RING_MAX_DESC_VER_2_3 16384
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477
478/* rx/tx mac addr + type + vlan + align + slack*/
Manfred Sprauld81c0982005-07-31 18:20:30 +0200479#define NV_RX_HEADERS (64)
480/* even more slack. */
481#define NV_RX_ALLOC_PAD (64)
482
483/* maximum mtu size */
484#define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
485#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486
487#define OOM_REFILL (1+HZ/20)
488#define POLL_WAIT (1+HZ/100)
489#define LINK_TIMEOUT (3*HZ)
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400490#define STATS_INTERVAL (10*HZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400492/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493 * desc_ver values:
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400494 * The nic supports three different descriptor types:
495 * - DESC_VER_1: Original
496 * - DESC_VER_2: support for jumbo frames.
497 * - DESC_VER_3: 64-bit format.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498 */
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400499#define DESC_VER_1 1
500#define DESC_VER_2 2
501#define DESC_VER_3 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502
503/* PHY defines */
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400504#define PHY_OUI_MARVELL 0x5043
505#define PHY_OUI_CICADA 0x03f1
506#define PHY_OUI_VITESSE 0x01c1
507#define PHY_OUI_REALTEK 0x0732
508#define PHY_OUI_REALTEK2 0x0020
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509#define PHYID1_OUI_MASK 0x03ff
510#define PHYID1_OUI_SHFT 6
511#define PHYID2_OUI_MASK 0xfc00
512#define PHYID2_OUI_SHFT 10
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400513#define PHYID2_MODEL_MASK 0x03f0
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400514#define PHY_MODEL_REALTEK_8211 0x0110
515#define PHY_REV_MASK 0x0001
516#define PHY_REV_REALTEK_8211B 0x0000
517#define PHY_REV_REALTEK_8211C 0x0001
518#define PHY_MODEL_REALTEK_8201 0x0200
519#define PHY_MODEL_MARVELL_E3016 0x0220
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400520#define PHY_MARVELL_E3016_INITMASK 0x0300
Ayaz Abdulla14a67f32007-07-15 06:50:28 -0400521#define PHY_CICADA_INIT1 0x0f000
522#define PHY_CICADA_INIT2 0x0e00
523#define PHY_CICADA_INIT3 0x01000
524#define PHY_CICADA_INIT4 0x0200
525#define PHY_CICADA_INIT5 0x0004
526#define PHY_CICADA_INIT6 0x02000
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400527#define PHY_VITESSE_INIT_REG1 0x1f
528#define PHY_VITESSE_INIT_REG2 0x10
529#define PHY_VITESSE_INIT_REG3 0x11
530#define PHY_VITESSE_INIT_REG4 0x12
531#define PHY_VITESSE_INIT_MSK1 0xc
532#define PHY_VITESSE_INIT_MSK2 0x0180
533#define PHY_VITESSE_INIT1 0x52b5
534#define PHY_VITESSE_INIT2 0xaf8a
535#define PHY_VITESSE_INIT3 0x8
536#define PHY_VITESSE_INIT4 0x8f8a
537#define PHY_VITESSE_INIT5 0xaf86
538#define PHY_VITESSE_INIT6 0x8f86
539#define PHY_VITESSE_INIT7 0xaf82
540#define PHY_VITESSE_INIT8 0x0100
541#define PHY_VITESSE_INIT9 0x8f82
542#define PHY_VITESSE_INIT10 0x0
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400543#define PHY_REALTEK_INIT_REG1 0x1f
544#define PHY_REALTEK_INIT_REG2 0x19
545#define PHY_REALTEK_INIT_REG3 0x13
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400546#define PHY_REALTEK_INIT_REG4 0x14
547#define PHY_REALTEK_INIT_REG5 0x18
548#define PHY_REALTEK_INIT_REG6 0x11
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400549#define PHY_REALTEK_INIT_REG7 0x01
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400550#define PHY_REALTEK_INIT1 0x0000
551#define PHY_REALTEK_INIT2 0x8e00
552#define PHY_REALTEK_INIT3 0x0001
553#define PHY_REALTEK_INIT4 0xad17
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400554#define PHY_REALTEK_INIT5 0xfb54
555#define PHY_REALTEK_INIT6 0xf5c7
556#define PHY_REALTEK_INIT7 0x1000
557#define PHY_REALTEK_INIT8 0x0003
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400558#define PHY_REALTEK_INIT9 0x0008
559#define PHY_REALTEK_INIT10 0x0005
560#define PHY_REALTEK_INIT11 0x0200
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400561#define PHY_REALTEK_INIT_MSK1 0x0003
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400562
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563#define PHY_GIGABIT 0x0100
564
565#define PHY_TIMEOUT 0x1
566#define PHY_ERROR 0x2
567
568#define PHY_100 0x1
569#define PHY_1000 0x2
570#define PHY_HALF 0x100
571
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400572#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
573#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
574#define NV_PAUSEFRAME_RX_ENABLE 0x0004
575#define NV_PAUSEFRAME_TX_ENABLE 0x0008
Ayaz Abdullab6d07732006-06-10 22:47:42 -0400576#define NV_PAUSEFRAME_RX_REQ 0x0010
577#define NV_PAUSEFRAME_TX_REQ 0x0020
578#define NV_PAUSEFRAME_AUTONEG 0x0040
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500580/* MSI/MSI-X defines */
581#define NV_MSI_X_MAX_VECTORS 8
582#define NV_MSI_X_VECTORS_MASK 0x000f
583#define NV_MSI_CAPABLE 0x0010
584#define NV_MSI_X_CAPABLE 0x0020
585#define NV_MSI_ENABLED 0x0040
586#define NV_MSI_X_ENABLED 0x0080
587
588#define NV_MSI_X_VECTOR_ALL 0x0
589#define NV_MSI_X_VECTOR_RX 0x0
590#define NV_MSI_X_VECTOR_TX 0x1
591#define NV_MSI_X_VECTOR_OTHER 0x2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592
Ayaz Abdullab6e44052009-02-07 00:24:15 -0800593#define NV_MSI_PRIV_OFFSET 0x68
594#define NV_MSI_PRIV_VALUE 0xffffffff
595
Ayaz Abdullab2976d22008-02-04 15:13:59 -0500596#define NV_RESTART_TX 0x1
597#define NV_RESTART_RX 0x2
598
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500599#define NV_TX_LIMIT_COUNT 16
600
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000601#define NV_DYNAMIC_THRESHOLD 4
602#define NV_DYNAMIC_MAX_QUIET_COUNT 2048
603
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400604/* statistics */
605struct nv_ethtool_str {
606 char name[ETH_GSTRING_LEN];
607};
608
609static const struct nv_ethtool_str nv_estats_str[] = {
david decotigny674aee32011-11-16 12:15:07 +0000610 { "tx_bytes" }, /* includes Ethernet FCS CRC */
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400611 { "tx_zero_rexmt" },
612 { "tx_one_rexmt" },
613 { "tx_many_rexmt" },
614 { "tx_late_collision" },
615 { "tx_fifo_errors" },
616 { "tx_carrier_errors" },
617 { "tx_excess_deferral" },
618 { "tx_retry_error" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400619 { "rx_frame_error" },
620 { "rx_extra_byte" },
621 { "rx_late_collision" },
622 { "rx_runt" },
623 { "rx_frame_too_long" },
624 { "rx_over_errors" },
625 { "rx_crc_errors" },
626 { "rx_frame_align_error" },
627 { "rx_length_error" },
628 { "rx_unicast" },
629 { "rx_multicast" },
630 { "rx_broadcast" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400631 { "rx_packets" },
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500632 { "rx_errors_total" },
633 { "tx_errors_total" },
634
635 /* version 2 stats */
636 { "tx_deferral" },
637 { "tx_packets" },
david decotigny674aee32011-11-16 12:15:07 +0000638 { "rx_bytes" }, /* includes Ethernet FCS CRC */
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500639 { "tx_pause" },
640 { "rx_pause" },
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400641 { "rx_drop_frame" },
642
643 /* version 3 stats */
644 { "tx_unicast" },
645 { "tx_multicast" },
646 { "tx_broadcast" }
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400647};
648
649struct nv_ethtool_stats {
david decotigny674aee32011-11-16 12:15:07 +0000650 u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400651 u64 tx_zero_rexmt;
652 u64 tx_one_rexmt;
653 u64 tx_many_rexmt;
654 u64 tx_late_collision;
655 u64 tx_fifo_errors;
656 u64 tx_carrier_errors;
657 u64 tx_excess_deferral;
658 u64 tx_retry_error;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400659 u64 rx_frame_error;
660 u64 rx_extra_byte;
661 u64 rx_late_collision;
662 u64 rx_runt;
663 u64 rx_frame_too_long;
664 u64 rx_over_errors;
665 u64 rx_crc_errors;
666 u64 rx_frame_align_error;
667 u64 rx_length_error;
668 u64 rx_unicast;
669 u64 rx_multicast;
670 u64 rx_broadcast;
david decotigny674aee32011-11-16 12:15:07 +0000671 u64 rx_packets; /* should be ifconfig->rx_packets */
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400672 u64 rx_errors_total;
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500673 u64 tx_errors_total;
674
675 /* version 2 stats */
676 u64 tx_deferral;
david decotigny674aee32011-11-16 12:15:07 +0000677 u64 tx_packets; /* should be ifconfig->tx_packets */
678 u64 rx_bytes; /* should be ifconfig->rx_bytes + 4*rx_packets */
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500679 u64 tx_pause;
680 u64 rx_pause;
681 u64 rx_drop_frame;
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400682
683 /* version 3 stats */
684 u64 tx_unicast;
685 u64 tx_multicast;
686 u64 tx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400687};
688
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400689#define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
690#define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500691#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
692
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400693/* diagnostics */
694#define NV_TEST_COUNT_BASE 3
695#define NV_TEST_COUNT_EXTENDED 4
696
697static const struct nv_ethtool_str nv_etests_str[] = {
698 { "link (online/offline)" },
699 { "register (offline) " },
700 { "interrupt (offline) " },
701 { "loopback (offline) " }
702};
703
704struct register_test {
Al Viro5bb7ea22007-12-09 16:06:41 +0000705 __u32 reg;
706 __u32 mask;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400707};
708
709static const struct register_test nv_registers_test[] = {
710 { NvRegUnknownSetupReg6, 0x01 },
711 { NvRegMisc1, 0x03c },
712 { NvRegOffloadConfig, 0x03ff },
713 { NvRegMulticastAddrA, 0xffffffff },
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400714 { NvRegTxWatermark, 0x0ff },
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400715 { NvRegWakeUpFlags, 0x07777 },
Szymon Janc78aea4f2010-11-27 08:39:43 +0000716 { 0, 0 }
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400717};
718
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500719struct nv_skb_map {
720 struct sk_buff *skb;
721 dma_addr_t dma;
Eric Dumazet73a37072009-06-17 21:17:59 +0000722 unsigned int dma_len:31;
723 unsigned int dma_single:1;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500724 struct ring_desc_ex *first_tx_desc;
725 struct nv_skb_map *next_tx_ctx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500726};
727
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728/*
729 * SMP locking:
Wang Chenb74ca3a2008-12-08 01:14:16 -0800730 * All hardware access under netdev_priv(dev)->lock, except the performance
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731 * critical parts:
732 * - rx is (pseudo-) lockless: it relies on the single-threading provided
733 * by the arch code for interrupts.
Herbert Xu932ff272006-06-09 12:20:56 -0700734 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
Wang Chenb74ca3a2008-12-08 01:14:16 -0800735 * needs netdev_priv(dev)->lock :-(
Herbert Xu932ff272006-06-09 12:20:56 -0700736 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
david decotignyf5d827a2011-11-16 12:15:13 +0000737 *
738 * Hardware stats updates are protected by hwstats_lock:
739 * - updated by nv_do_stats_poll (timer). This is meant to avoid
740 * integer wraparound in the NIC stats registers, at low frequency
741 * (0.1 Hz)
742 * - updated by nv_get_ethtool_stats + nv_get_stats64
743 *
744 * Software stats are accessed only through 64b synchronization points
745 * and are not subject to other synchronization techniques (single
746 * update thread on the TX or RX paths).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747 */
748
749/* in dev: base, irq */
750struct fe_priv {
751 spinlock_t lock;
752
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700753 struct net_device *dev;
754 struct napi_struct napi;
755
david decotignyf5d827a2011-11-16 12:15:13 +0000756 /* hardware stats are updated in syscall and timer */
757 spinlock_t hwstats_lock;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400758 struct nv_ethtool_stats estats;
david decotignyf5d827a2011-11-16 12:15:13 +0000759
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760 int in_shutdown;
761 u32 linkspeed;
762 int duplex;
763 int autoneg;
764 int fixed_mode;
765 int phyaddr;
766 int wolenabled;
767 unsigned int phy_oui;
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400768 unsigned int phy_model;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400769 unsigned int phy_rev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 u16 gigabit;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400771 int intr_test;
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500772 int recover_error;
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000773 int quiet_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774
775 /* General data: RO fields */
776 dma_addr_t ring_addr;
777 struct pci_dev *pci_dev;
778 u32 orig_mac[2];
Ayaz Abdulla582806b2009-03-05 08:02:03 +0000779 u32 events;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780 u32 irqmask;
781 u32 desc_ver;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400782 u32 txrxctl_bits;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500783 u32 vlanctl_bits;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400784 u32 driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400785 u32 device_id;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400786 u32 register_size;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500787 u32 mac_in_use;
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800788 int mgmt_version;
789 int mgmt_sema;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790
791 void __iomem *base;
792
793 /* rx specific fields.
794 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
795 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500796 union ring_type get_rx, put_rx, first_rx, last_rx;
797 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
798 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
799 struct nv_skb_map *rx_skb;
800
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700801 union ring_type rx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 unsigned int rx_buf_sz;
Manfred Sprauld81c0982005-07-31 18:20:30 +0200803 unsigned int pkt_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 struct timer_list oom_kick;
805 struct timer_list nic_poll;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400806 struct timer_list stats_poll;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500807 u32 nic_poll_irq;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400808 int rx_ring_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809
david decotignyf5d827a2011-11-16 12:15:13 +0000810 /* RX software stats */
811 struct u64_stats_sync swstats_rx_syncp;
812 u64 stat_rx_packets;
813 u64 stat_rx_bytes; /* not always available in HW */
814 u64 stat_rx_missed_errors;
david decotigny0a1f2222011-11-16 12:15:14 +0000815 u64 stat_rx_dropped;
david decotignyf5d827a2011-11-16 12:15:13 +0000816
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817 /* media detection workaround.
818 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
819 */
820 int need_linktimer;
821 unsigned long link_timeout;
822 /*
823 * tx specific fields.
824 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500825 union ring_type get_tx, put_tx, first_tx, last_tx;
826 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
827 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
828 struct nv_skb_map *tx_skb;
829
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700830 union ring_type tx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831 u32 tx_flags;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400832 int tx_ring_size;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500833 int tx_limit;
834 u32 tx_pkts_in_progress;
835 struct nv_skb_map *tx_change_owner;
836 struct nv_skb_map *tx_end_flip;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -0500837 int tx_stop;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500838
david decotignyf5d827a2011-11-16 12:15:13 +0000839 /* TX software stats */
840 struct u64_stats_sync swstats_tx_syncp;
841 u64 stat_tx_packets; /* not always available in HW */
842 u64 stat_tx_bytes;
843 u64 stat_tx_dropped;
844
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500845 /* msi/msi-x fields */
846 u32 msi_flags;
847 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400848
849 /* flow control */
850 u32 pause_flags;
Tobias Diedrich1a1ca862008-05-18 15:03:44 +0200851
852 /* power saved state */
853 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
Yinghai Luddb213f2009-02-06 01:29:23 -0800854
855 /* for different msi-x irq type */
856 char name_rx[IFNAMSIZ + 3]; /* -rx */
857 char name_tx[IFNAMSIZ + 3]; /* -tx */
858 char name_other[IFNAMSIZ + 6]; /* -other */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859};
860
861/*
862 * Maximum number of loops until we assume that a bit in the irq mask
863 * is stuck. Overridable with module param.
864 */
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000865static int max_interrupt_work = 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500867/*
868 * Optimization can be either throuput mode or cpu mode
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400869 *
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500870 * Throughput Mode: Every tx and rx packet will generate an interrupt.
871 * CPU Mode: Interrupts are controlled by a timer.
872 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400873enum {
874 NV_OPTIMIZATION_MODE_THROUGHPUT,
Ayaz Abdulla9e184762009-03-05 08:02:18 +0000875 NV_OPTIMIZATION_MODE_CPU,
876 NV_OPTIMIZATION_MODE_DYNAMIC
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400877};
Ayaz Abdulla9e184762009-03-05 08:02:18 +0000878static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500879
880/*
881 * Poll interval for timer irq
882 *
883 * This interval determines how frequent an interrupt is generated.
884 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
885 * Min = 0, and Max = 65535
886 */
887static int poll_interval = -1;
888
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500889/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400890 * MSI interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500891 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400892enum {
893 NV_MSI_INT_DISABLED,
894 NV_MSI_INT_ENABLED
895};
896static int msi = NV_MSI_INT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500897
898/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400899 * MSIX interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500900 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400901enum {
902 NV_MSIX_INT_DISABLED,
903 NV_MSIX_INT_ENABLED
904};
Yinghai Lu39482792009-02-06 01:31:12 -0800905static int msix = NV_MSIX_INT_ENABLED;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400906
907/*
908 * DMA 64bit
909 */
910enum {
911 NV_DMA_64BIT_DISABLED,
912 NV_DMA_64BIT_ENABLED
913};
914static int dma_64bit = NV_DMA_64BIT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500915
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400916/*
Sameer Nanda1ec4f2d2011-11-16 12:15:12 +0000917 * Debug output control for tx_timeout
918 */
919static bool debug_tx_timeout = false;
920
921/*
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400922 * Crossover Detection
923 * Realtek 8201 phy + some OEM boards do not work properly.
924 */
925enum {
926 NV_CROSSOVER_DETECTION_DISABLED,
927 NV_CROSSOVER_DETECTION_ENABLED
928};
929static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
930
Ed Swierk5a9a8e32009-06-02 00:19:52 -0700931/*
932 * Power down phy when interface is down (persists through reboot;
933 * older Linux and other OSes may not power it up again)
934 */
Szymon Janc78aea4f2010-11-27 08:39:43 +0000935static int phy_power_down;
Ed Swierk5a9a8e32009-06-02 00:19:52 -0700936
Linus Torvalds1da177e2005-04-16 15:20:36 -0700937static inline struct fe_priv *get_nvpriv(struct net_device *dev)
938{
939 return netdev_priv(dev);
940}
941
942static inline u8 __iomem *get_hwbase(struct net_device *dev)
943{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400944 return ((struct fe_priv *)netdev_priv(dev))->base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700945}
946
947static inline void pci_push(u8 __iomem *base)
948{
949 /* force out pending posted writes */
950 readl(base);
951}
952
953static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
954{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700955 return le32_to_cpu(prd->flaglen)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
957}
958
Manfred Spraulee733622005-07-31 18:32:26 +0200959static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
960{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700961 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
Manfred Spraulee733622005-07-31 18:32:26 +0200962}
963
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400964static bool nv_optimized(struct fe_priv *np)
965{
966 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
967 return false;
968 return true;
969}
970
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
Joe Perches344d0dc2010-11-29 07:41:52 +0000972 int delay, int delaymax)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973{
974 u8 __iomem *base = get_hwbase(dev);
975
976 pci_push(base);
977 do {
978 udelay(delay);
979 delaymax -= delay;
Joe Perches344d0dc2010-11-29 07:41:52 +0000980 if (delaymax < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982 } while ((readl(base + offset) & mask) != target);
983 return 0;
984}
985
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500986#define NV_SETUP_RX_RING 0x01
987#define NV_SETUP_TX_RING 0x02
988
Al Viro5bb7ea22007-12-09 16:06:41 +0000989static inline u32 dma_low(dma_addr_t addr)
990{
991 return addr;
992}
993
994static inline u32 dma_high(dma_addr_t addr)
995{
996 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
997}
998
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500999static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
1000{
1001 struct fe_priv *np = get_nvpriv(dev);
1002 u8 __iomem *base = get_hwbase(dev);
1003
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001004 if (!nv_optimized(np)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00001005 if (rxtx_flags & NV_SETUP_RX_RING)
Al Viro5bb7ea22007-12-09 16:06:41 +00001006 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001007 if (rxtx_flags & NV_SETUP_TX_RING)
Al Viro5bb7ea22007-12-09 16:06:41 +00001008 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05001009 } else {
1010 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +00001011 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1012 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05001013 }
1014 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +00001015 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1016 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05001017 }
1018 }
1019}
1020
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001021static void free_rings(struct net_device *dev)
1022{
1023 struct fe_priv *np = get_nvpriv(dev);
1024
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001025 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001026 if (np->rx_ring.orig)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001027 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1028 np->rx_ring.orig, np->ring_addr);
1029 } else {
1030 if (np->rx_ring.ex)
1031 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1032 np->rx_ring.ex, np->ring_addr);
1033 }
Szymon Janc9b03b062010-11-27 08:39:44 +00001034 kfree(np->rx_skb);
1035 kfree(np->tx_skb);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001036}
1037
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001038static int using_multi_irqs(struct net_device *dev)
1039{
1040 struct fe_priv *np = get_nvpriv(dev);
1041
1042 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1043 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1044 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1045 return 0;
1046 else
1047 return 1;
1048}
1049
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00001050static void nv_txrx_gate(struct net_device *dev, bool gate)
1051{
1052 struct fe_priv *np = get_nvpriv(dev);
1053 u8 __iomem *base = get_hwbase(dev);
1054 u32 powerstate;
1055
1056 if (!np->mac_in_use &&
1057 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1058 powerstate = readl(base + NvRegPowerState2);
1059 if (gate)
1060 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1061 else
1062 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1063 writel(powerstate, base + NvRegPowerState2);
1064 }
1065}
1066
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001067static void nv_enable_irq(struct net_device *dev)
1068{
1069 struct fe_priv *np = get_nvpriv(dev);
1070
1071 if (!using_multi_irqs(dev)) {
1072 if (np->msi_flags & NV_MSI_X_ENABLED)
1073 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1074 else
Manfred Spraula7475902007-10-17 21:52:33 +02001075 enable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001076 } else {
1077 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1078 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1079 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1080 }
1081}
1082
1083static void nv_disable_irq(struct net_device *dev)
1084{
1085 struct fe_priv *np = get_nvpriv(dev);
1086
1087 if (!using_multi_irqs(dev)) {
1088 if (np->msi_flags & NV_MSI_X_ENABLED)
1089 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1090 else
Manfred Spraula7475902007-10-17 21:52:33 +02001091 disable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001092 } else {
1093 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1094 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1095 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1096 }
1097}
1098
1099/* In MSIX mode, a write to irqmask behaves as XOR */
1100static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1101{
1102 u8 __iomem *base = get_hwbase(dev);
1103
1104 writel(mask, base + NvRegIrqMask);
1105}
1106
1107static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1108{
1109 struct fe_priv *np = get_nvpriv(dev);
1110 u8 __iomem *base = get_hwbase(dev);
1111
1112 if (np->msi_flags & NV_MSI_X_ENABLED) {
1113 writel(mask, base + NvRegIrqMask);
1114 } else {
1115 if (np->msi_flags & NV_MSI_ENABLED)
1116 writel(0, base + NvRegMSIIrqMask);
1117 writel(0, base + NvRegIrqMask);
1118 }
1119}
1120
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001121static void nv_napi_enable(struct net_device *dev)
1122{
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001123 struct fe_priv *np = get_nvpriv(dev);
1124
1125 napi_enable(&np->napi);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001126}
1127
1128static void nv_napi_disable(struct net_device *dev)
1129{
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001130 struct fe_priv *np = get_nvpriv(dev);
1131
1132 napi_disable(&np->napi);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001133}
1134
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135#define MII_READ (-1)
1136/* mii_rw: read/write a register on the PHY.
1137 *
1138 * Caller must guarantee serialization
1139 */
1140static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1141{
1142 u8 __iomem *base = get_hwbase(dev);
1143 u32 reg;
1144 int retval;
1145
Ayaz Abdullaeb798422008-02-04 15:14:04 -05001146 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147
1148 reg = readl(base + NvRegMIIControl);
1149 if (reg & NVREG_MIICTL_INUSE) {
1150 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1151 udelay(NV_MIIBUSY_DELAY);
1152 }
1153
1154 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1155 if (value != MII_READ) {
1156 writel(value, base + NvRegMIIData);
1157 reg |= NVREG_MIICTL_WRITE;
1158 }
1159 writel(reg, base + NvRegMIIControl);
1160
1161 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
Joe Perches344d0dc2010-11-29 07:41:52 +00001162 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001163 retval = -1;
1164 } else if (value != MII_READ) {
1165 /* it was a write operation - fewer failures are detectable */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166 retval = 0;
1167 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168 retval = -1;
1169 } else {
1170 retval = readl(base + NvRegMIIData);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171 }
1172
1173 return retval;
1174}
1175
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001176static int phy_reset(struct net_device *dev, u32 bmcr_setup)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001177{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001178 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179 u32 miicontrol;
1180 unsigned int tries = 0;
1181
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001182 miicontrol = BMCR_RESET | bmcr_setup;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001183 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001184 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001185
1186 /* wait for 500ms */
1187 msleep(500);
1188
1189 /* must wait till reset is deasserted */
1190 while (miicontrol & BMCR_RESET) {
Szymon Jancde855b92010-11-27 08:39:48 +00001191 usleep_range(10000, 20000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001192 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1193 /* FIXME: 100 tries seem excessive */
1194 if (tries++ > 100)
1195 return -1;
1196 }
1197 return 0;
1198}
1199
Joe Perchesc41d41e2010-11-29 07:41:58 +00001200static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1201{
1202 static const struct {
1203 int reg;
1204 int init;
1205 } ri[] = {
1206 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1207 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1208 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1209 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1210 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1211 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1212 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1213 };
1214 int i;
1215
1216 for (i = 0; i < ARRAY_SIZE(ri); i++) {
Joe Perchescd663282010-11-29 07:41:59 +00001217 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
Joe Perchesc41d41e2010-11-29 07:41:58 +00001218 return PHY_ERROR;
Joe Perchesc41d41e2010-11-29 07:41:58 +00001219 }
1220
1221 return 0;
1222}
1223
Joe Perchescd663282010-11-29 07:41:59 +00001224static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1225{
1226 u32 reg;
1227 u8 __iomem *base = get_hwbase(dev);
1228 u32 powerstate = readl(base + NvRegPowerState2);
1229
1230 /* need to perform hw phy reset */
1231 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1232 writel(powerstate, base + NvRegPowerState2);
1233 msleep(25);
1234
1235 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1236 writel(powerstate, base + NvRegPowerState2);
1237 msleep(25);
1238
1239 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1240 reg |= PHY_REALTEK_INIT9;
1241 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1242 return PHY_ERROR;
1243 if (mii_rw(dev, np->phyaddr,
1244 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1245 return PHY_ERROR;
1246 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1247 if (!(reg & PHY_REALTEK_INIT11)) {
1248 reg |= PHY_REALTEK_INIT11;
1249 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1250 return PHY_ERROR;
1251 }
1252 if (mii_rw(dev, np->phyaddr,
1253 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1254 return PHY_ERROR;
1255
1256 return 0;
1257}
1258
1259static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1260{
1261 u32 phy_reserved;
1262
1263 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1264 phy_reserved = mii_rw(dev, np->phyaddr,
1265 PHY_REALTEK_INIT_REG6, MII_READ);
1266 phy_reserved |= PHY_REALTEK_INIT7;
1267 if (mii_rw(dev, np->phyaddr,
1268 PHY_REALTEK_INIT_REG6, phy_reserved))
1269 return PHY_ERROR;
1270 }
1271
1272 return 0;
1273}
1274
1275static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1276{
1277 u32 phy_reserved;
1278
1279 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1280 if (mii_rw(dev, np->phyaddr,
1281 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1282 return PHY_ERROR;
1283 phy_reserved = mii_rw(dev, np->phyaddr,
1284 PHY_REALTEK_INIT_REG2, MII_READ);
1285 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1286 phy_reserved |= PHY_REALTEK_INIT3;
1287 if (mii_rw(dev, np->phyaddr,
1288 PHY_REALTEK_INIT_REG2, phy_reserved))
1289 return PHY_ERROR;
1290 if (mii_rw(dev, np->phyaddr,
1291 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1292 return PHY_ERROR;
1293 }
1294
1295 return 0;
1296}
1297
1298static int init_cicada(struct net_device *dev, struct fe_priv *np,
1299 u32 phyinterface)
1300{
1301 u32 phy_reserved;
1302
1303 if (phyinterface & PHY_RGMII) {
1304 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1305 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1306 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1307 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1308 return PHY_ERROR;
1309 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1310 phy_reserved |= PHY_CICADA_INIT5;
1311 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1312 return PHY_ERROR;
1313 }
1314 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1315 phy_reserved |= PHY_CICADA_INIT6;
1316 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1317 return PHY_ERROR;
1318
1319 return 0;
1320}
1321
1322static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1323{
1324 u32 phy_reserved;
1325
1326 if (mii_rw(dev, np->phyaddr,
1327 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1328 return PHY_ERROR;
1329 if (mii_rw(dev, np->phyaddr,
1330 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1331 return PHY_ERROR;
1332 phy_reserved = mii_rw(dev, np->phyaddr,
1333 PHY_VITESSE_INIT_REG4, MII_READ);
1334 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1335 return PHY_ERROR;
1336 phy_reserved = mii_rw(dev, np->phyaddr,
1337 PHY_VITESSE_INIT_REG3, MII_READ);
1338 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1339 phy_reserved |= PHY_VITESSE_INIT3;
1340 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1341 return PHY_ERROR;
1342 if (mii_rw(dev, np->phyaddr,
1343 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1344 return PHY_ERROR;
1345 if (mii_rw(dev, np->phyaddr,
1346 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1347 return PHY_ERROR;
1348 phy_reserved = mii_rw(dev, np->phyaddr,
1349 PHY_VITESSE_INIT_REG4, MII_READ);
1350 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1351 phy_reserved |= PHY_VITESSE_INIT3;
1352 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1353 return PHY_ERROR;
1354 phy_reserved = mii_rw(dev, np->phyaddr,
1355 PHY_VITESSE_INIT_REG3, MII_READ);
1356 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1357 return PHY_ERROR;
1358 if (mii_rw(dev, np->phyaddr,
1359 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1360 return PHY_ERROR;
1361 if (mii_rw(dev, np->phyaddr,
1362 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1363 return PHY_ERROR;
1364 phy_reserved = mii_rw(dev, np->phyaddr,
1365 PHY_VITESSE_INIT_REG4, MII_READ);
1366 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1367 return PHY_ERROR;
1368 phy_reserved = mii_rw(dev, np->phyaddr,
1369 PHY_VITESSE_INIT_REG3, MII_READ);
1370 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1371 phy_reserved |= PHY_VITESSE_INIT8;
1372 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1373 return PHY_ERROR;
1374 if (mii_rw(dev, np->phyaddr,
1375 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1376 return PHY_ERROR;
1377 if (mii_rw(dev, np->phyaddr,
1378 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1379 return PHY_ERROR;
1380
1381 return 0;
1382}
1383
Linus Torvalds1da177e2005-04-16 15:20:36 -07001384static int phy_init(struct net_device *dev)
1385{
1386 struct fe_priv *np = get_nvpriv(dev);
1387 u8 __iomem *base = get_hwbase(dev);
Joe Perchescd663282010-11-29 07:41:59 +00001388 u32 phyinterface;
1389 u32 mii_status, mii_control, mii_control_1000, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001391 /* phy errata for E3016 phy */
1392 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1393 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1394 reg &= ~PHY_MARVELL_E3016_INITMASK;
1395 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001396 netdev_info(dev, "%s: phy write to errata reg failed\n",
1397 pci_name(np->pci_dev));
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001398 return PHY_ERROR;
1399 }
1400 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001401 if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001402 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1403 np->phy_rev == PHY_REV_REALTEK_8211B) {
Joe Perchescd663282010-11-29 07:41:59 +00001404 if (init_realtek_8211b(dev, np)) {
1405 netdev_info(dev, "%s: phy init failed\n",
1406 pci_name(np->pci_dev));
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001407 return PHY_ERROR;
Joe Perchescd663282010-11-29 07:41:59 +00001408 }
Joe Perchesc41d41e2010-11-29 07:41:58 +00001409 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1410 np->phy_rev == PHY_REV_REALTEK_8211C) {
Joe Perchescd663282010-11-29 07:41:59 +00001411 if (init_realtek_8211c(dev, np)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001412 netdev_info(dev, "%s: phy init failed\n",
1413 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001414 return PHY_ERROR;
1415 }
Joe Perchescd663282010-11-29 07:41:59 +00001416 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1417 if (init_realtek_8201(dev, np)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001418 netdev_info(dev, "%s: phy init failed\n",
1419 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001420 return PHY_ERROR;
1421 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001422 }
1423 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001424
Linus Torvalds1da177e2005-04-16 15:20:36 -07001425 /* set advertise register */
1426 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Joe Perchescd663282010-11-29 07:41:59 +00001427 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1428 ADVERTISE_100HALF | ADVERTISE_100FULL |
1429 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001430 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001431 netdev_info(dev, "%s: phy write to advertise failed\n",
1432 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433 return PHY_ERROR;
1434 }
1435
1436 /* get phy interface type */
1437 phyinterface = readl(base + NvRegPhyInterface);
1438
1439 /* see if gigabit phy */
1440 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1441 if (mii_status & PHY_GIGABIT) {
1442 np->gigabit = PHY_GIGABIT;
Joe Perchescd663282010-11-29 07:41:59 +00001443 mii_control_1000 = mii_rw(dev, np->phyaddr,
1444 MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001445 mii_control_1000 &= ~ADVERTISE_1000HALF;
1446 if (phyinterface & PHY_RGMII)
1447 mii_control_1000 |= ADVERTISE_1000FULL;
1448 else
1449 mii_control_1000 &= ~ADVERTISE_1000FULL;
1450
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001451 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001452 netdev_info(dev, "%s: phy init failed\n",
1453 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454 return PHY_ERROR;
1455 }
Szymon Janc78aea4f2010-11-27 08:39:43 +00001456 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001457 np->gigabit = 0;
1458
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001459 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1460 mii_control |= BMCR_ANENABLE;
1461
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001462 if (np->phy_oui == PHY_OUI_REALTEK &&
1463 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1464 np->phy_rev == PHY_REV_REALTEK_8211C) {
1465 /* start autoneg since we already performed hw reset above */
1466 mii_control |= BMCR_ANRESTART;
1467 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001468 netdev_info(dev, "%s: phy init failed\n",
1469 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001470 return PHY_ERROR;
1471 }
1472 } else {
1473 /* reset the phy
1474 * (certain phys need bmcr to be setup with reset)
1475 */
1476 if (phy_reset(dev, mii_control)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001477 netdev_info(dev, "%s: phy reset failed\n",
1478 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001479 return PHY_ERROR;
1480 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481 }
1482
1483 /* phy vendor specific configuration */
David Woodd46781b2014-09-01 15:31:55 -07001484 if (np->phy_oui == PHY_OUI_CICADA) {
Joe Perchescd663282010-11-29 07:41:59 +00001485 if (init_cicada(dev, np, phyinterface)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001486 netdev_info(dev, "%s: phy init failed\n",
1487 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488 return PHY_ERROR;
1489 }
Joe Perchescd663282010-11-29 07:41:59 +00001490 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1491 if (init_vitesse(dev, np)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001492 netdev_info(dev, "%s: phy init failed\n",
1493 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494 return PHY_ERROR;
1495 }
Joe Perchescd663282010-11-29 07:41:59 +00001496 } else if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001497 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1498 np->phy_rev == PHY_REV_REALTEK_8211B) {
1499 /* reset could have cleared these out, set them back */
Joe Perchescd663282010-11-29 07:41:59 +00001500 if (init_realtek_8211b(dev, np)) {
1501 netdev_info(dev, "%s: phy init failed\n",
1502 pci_name(np->pci_dev));
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001503 return PHY_ERROR;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001504 }
Joe Perchescd663282010-11-29 07:41:59 +00001505 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1506 if (init_realtek_8201(dev, np) ||
1507 init_realtek_8201_cross(dev, np)) {
1508 netdev_info(dev, "%s: phy init failed\n",
1509 pci_name(np->pci_dev));
1510 return PHY_ERROR;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001511 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001512 }
1513 }
1514
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001515 /* some phys clear out pause advertisement on reset, set it back */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001516 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001517
Ed Swierkcb52deb2008-12-01 12:24:43 +00001518 /* restart auto negotiation, power down phy */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001519 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ed Swierk5a9a8e32009-06-02 00:19:52 -07001520 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001521 if (phy_power_down)
Ed Swierk5a9a8e32009-06-02 00:19:52 -07001522 mii_control |= BMCR_PDOWN;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001523 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524 return PHY_ERROR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001525
1526 return 0;
1527}
1528
1529static void nv_start_rx(struct net_device *dev)
1530{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001531 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001533 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534
Linus Torvalds1da177e2005-04-16 15:20:36 -07001535 /* Already running? Stop it. */
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001536 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1537 rx_ctrl &= ~NVREG_RCVCTL_START;
1538 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001539 pci_push(base);
1540 }
1541 writel(np->linkspeed, base + NvRegLinkSpeed);
1542 pci_push(base);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001543 rx_ctrl |= NVREG_RCVCTL_START;
1544 if (np->mac_in_use)
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001545 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1546 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001547 pci_push(base);
1548}
1549
1550static void nv_stop_rx(struct net_device *dev)
1551{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001552 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001554 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001555
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001556 if (!np->mac_in_use)
1557 rx_ctrl &= ~NVREG_RCVCTL_START;
1558 else
1559 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1560 writel(rx_ctrl, base + NvRegReceiverControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00001561 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1562 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
Joe Perches1d397f32010-11-29 07:41:57 +00001563 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1564 __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001565
1566 udelay(NV_RXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001567 if (!np->mac_in_use)
1568 writel(0, base + NvRegLinkSpeed);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001569}
1570
1571static void nv_start_tx(struct net_device *dev)
1572{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001573 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001574 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001575 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001577 tx_ctrl |= NVREG_XMITCTL_START;
1578 if (np->mac_in_use)
1579 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1580 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001581 pci_push(base);
1582}
1583
1584static void nv_stop_tx(struct net_device *dev)
1585{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001586 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001587 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001588 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001589
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001590 if (!np->mac_in_use)
1591 tx_ctrl &= ~NVREG_XMITCTL_START;
1592 else
1593 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1594 writel(tx_ctrl, base + NvRegTransmitterControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00001595 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1596 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
Joe Perches1d397f32010-11-29 07:41:57 +00001597 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1598 __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599
1600 udelay(NV_TXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001601 if (!np->mac_in_use)
1602 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1603 base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604}
1605
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001606static void nv_start_rxtx(struct net_device *dev)
1607{
1608 nv_start_rx(dev);
1609 nv_start_tx(dev);
1610}
1611
1612static void nv_stop_rxtx(struct net_device *dev)
1613{
1614 nv_stop_rx(dev);
1615 nv_stop_tx(dev);
1616}
1617
Linus Torvalds1da177e2005-04-16 15:20:36 -07001618static void nv_txrx_reset(struct net_device *dev)
1619{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001620 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001621 u8 __iomem *base = get_hwbase(dev);
1622
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001623 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001624 pci_push(base);
1625 udelay(NV_TXRX_RESET_DELAY);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001626 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001627 pci_push(base);
1628}
1629
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001630static void nv_mac_reset(struct net_device *dev)
1631{
1632 struct fe_priv *np = netdev_priv(dev);
1633 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001634 u32 temp1, temp2, temp3;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001635
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001636 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1637 pci_push(base);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001638
1639 /* save registers since they will be cleared on reset */
1640 temp1 = readl(base + NvRegMacAddrA);
1641 temp2 = readl(base + NvRegMacAddrB);
1642 temp3 = readl(base + NvRegTransmitPoll);
1643
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001644 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1645 pci_push(base);
1646 udelay(NV_MAC_RESET_DELAY);
1647 writel(0, base + NvRegMacReset);
1648 pci_push(base);
1649 udelay(NV_MAC_RESET_DELAY);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001650
1651 /* restore saved registers */
1652 writel(temp1, base + NvRegMacAddrA);
1653 writel(temp2, base + NvRegMacAddrB);
1654 writel(temp3, base + NvRegTransmitPoll);
1655
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001656 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1657 pci_push(base);
1658}
1659
david decotignyf5d827a2011-11-16 12:15:13 +00001660/* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1661static void nv_update_stats(struct net_device *dev)
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001662{
1663 struct fe_priv *np = netdev_priv(dev);
1664 u8 __iomem *base = get_hwbase(dev);
1665
david decotignyf5d827a2011-11-16 12:15:13 +00001666 /* If it happens that this is run in top-half context, then
1667 * replace the spin_lock of hwstats_lock with
1668 * spin_lock_irqsave() in calling functions. */
1669 WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1670 assert_spin_locked(&np->hwstats_lock);
1671
1672 /* query hardware */
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001673 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1674 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1675 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1676 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1677 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1678 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1679 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1680 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1681 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1682 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1683 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1684 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1685 np->estats.rx_runt += readl(base + NvRegRxRunt);
1686 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1687 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1688 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1689 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1690 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1691 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1692 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1693 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1694 np->estats.rx_packets =
1695 np->estats.rx_unicast +
1696 np->estats.rx_multicast +
1697 np->estats.rx_broadcast;
1698 np->estats.rx_errors_total =
1699 np->estats.rx_crc_errors +
1700 np->estats.rx_over_errors +
1701 np->estats.rx_frame_error +
1702 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1703 np->estats.rx_late_collision +
1704 np->estats.rx_runt +
1705 np->estats.rx_frame_too_long;
1706 np->estats.tx_errors_total =
1707 np->estats.tx_late_collision +
1708 np->estats.tx_fifo_errors +
1709 np->estats.tx_carrier_errors +
1710 np->estats.tx_excess_deferral +
1711 np->estats.tx_retry_error;
1712
1713 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1714 np->estats.tx_deferral += readl(base + NvRegTxDef);
1715 np->estats.tx_packets += readl(base + NvRegTxFrame);
1716 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1717 np->estats.tx_pause += readl(base + NvRegTxPause);
1718 np->estats.rx_pause += readl(base + NvRegRxPause);
1719 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
Mandeep Baines0bdfea82011-11-05 14:38:23 +00001720 np->estats.rx_errors_total += np->estats.rx_drop_frame;
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001721 }
Ayaz Abdulla9c662432008-08-06 12:11:42 -04001722
1723 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1724 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1725 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1726 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1727 }
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001728}
1729
Linus Torvalds1da177e2005-04-16 15:20:36 -07001730/*
david decotignyf5d827a2011-11-16 12:15:13 +00001731 * nv_get_stats64: dev->ndo_get_stats64 function
Linus Torvalds1da177e2005-04-16 15:20:36 -07001732 * Get latest stats value from the nic.
1733 * Called with read_lock(&dev_base_lock) held for read -
1734 * only synchronized against unregister_netdevice.
1735 */
david decotignyf5d827a2011-11-16 12:15:13 +00001736static struct rtnl_link_stats64*
1737nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage)
1738 __acquires(&netdev_priv(dev)->hwstats_lock)
1739 __releases(&netdev_priv(dev)->hwstats_lock)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001740{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001741 struct fe_priv *np = netdev_priv(dev);
david decotignyf5d827a2011-11-16 12:15:13 +00001742 unsigned int syncp_start;
1743
1744 /*
1745 * Note: because HW stats are not always available and for
1746 * consistency reasons, the following ifconfig stats are
1747 * managed by software: rx_bytes, tx_bytes, rx_packets and
1748 * tx_packets. The related hardware stats reported by ethtool
1749 * should be equivalent to these ifconfig stats, with 4
1750 * additional bytes per packet (Ethernet FCS CRC), except for
1751 * tx_packets when TSO kicks in.
1752 */
1753
1754 /* software stats */
1755 do {
Eric W. Biederman57a77442014-03-13 21:26:42 -07001756 syncp_start = u64_stats_fetch_begin_irq(&np->swstats_rx_syncp);
david decotignyf5d827a2011-11-16 12:15:13 +00001757 storage->rx_packets = np->stat_rx_packets;
1758 storage->rx_bytes = np->stat_rx_bytes;
david decotigny0a1f2222011-11-16 12:15:14 +00001759 storage->rx_dropped = np->stat_rx_dropped;
david decotignyf5d827a2011-11-16 12:15:13 +00001760 storage->rx_missed_errors = np->stat_rx_missed_errors;
Eric W. Biederman57a77442014-03-13 21:26:42 -07001761 } while (u64_stats_fetch_retry_irq(&np->swstats_rx_syncp, syncp_start));
david decotignyf5d827a2011-11-16 12:15:13 +00001762
1763 do {
Eric W. Biederman57a77442014-03-13 21:26:42 -07001764 syncp_start = u64_stats_fetch_begin_irq(&np->swstats_tx_syncp);
david decotignyf5d827a2011-11-16 12:15:13 +00001765 storage->tx_packets = np->stat_tx_packets;
1766 storage->tx_bytes = np->stat_tx_bytes;
1767 storage->tx_dropped = np->stat_tx_dropped;
Eric W. Biederman57a77442014-03-13 21:26:42 -07001768 } while (u64_stats_fetch_retry_irq(&np->swstats_tx_syncp, syncp_start));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001769
Ayaz Abdulla21828162007-01-23 12:27:21 -05001770 /* If the nic supports hw counters then retrieve latest values */
david decotignyf5d827a2011-11-16 12:15:13 +00001771 if (np->driver_data & DEV_HAS_STATISTICS_V123) {
1772 spin_lock_bh(&np->hwstats_lock);
Ayaz Abdulla21828162007-01-23 12:27:21 -05001773
david decotignyf5d827a2011-11-16 12:15:13 +00001774 nv_update_stats(dev);
david decotigny674aee32011-11-16 12:15:07 +00001775
david decotignyf5d827a2011-11-16 12:15:13 +00001776 /* generic stats */
1777 storage->rx_errors = np->estats.rx_errors_total;
1778 storage->tx_errors = np->estats.tx_errors_total;
1779
1780 /* meaningful only when NIC supports stats v3 */
1781 storage->multicast = np->estats.rx_multicast;
1782
1783 /* detailed rx_errors */
1784 storage->rx_length_errors = np->estats.rx_length_error;
1785 storage->rx_over_errors = np->estats.rx_over_errors;
1786 storage->rx_crc_errors = np->estats.rx_crc_errors;
1787 storage->rx_frame_errors = np->estats.rx_frame_align_error;
1788 storage->rx_fifo_errors = np->estats.rx_drop_frame;
1789
1790 /* detailed tx_errors */
1791 storage->tx_carrier_errors = np->estats.tx_carrier_errors;
1792 storage->tx_fifo_errors = np->estats.tx_fifo_errors;
1793
1794 spin_unlock_bh(&np->hwstats_lock);
Ayaz Abdulla21828162007-01-23 12:27:21 -05001795 }
Jeff Garzik8148ff42007-10-16 20:56:09 -04001796
david decotignyf5d827a2011-11-16 12:15:13 +00001797 return storage;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001798}
1799
1800/*
1801 * nv_alloc_rx: fill rx ring entries.
1802 * Return 1 if the allocations for the skbs failed and the
1803 * rx engine is without Available descriptors
1804 */
1805static int nv_alloc_rx(struct net_device *dev)
1806{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001807 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001808 struct ring_desc *less_rx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001809
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001810 less_rx = np->get_rx.orig;
1811 if (less_rx-- == np->first_rx.orig)
1812 less_rx = np->last_rx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001813
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001814 while (np->put_rx.orig != less_rx) {
Pradeep A. Dalvidae2e9f2012-02-06 11:16:13 +00001815 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001816 if (skb) {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001817 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001818 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1819 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001820 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001821 PCI_DMA_FROMDEVICE);
Larry Finger612a7c42012-12-27 17:25:41 +00001822 if (pci_dma_mapping_error(np->pci_dev,
1823 np->put_rx_ctx->dma)) {
1824 kfree_skb(skb);
1825 goto packet_dropped;
1826 }
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001827 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001828 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1829 wmb();
1830 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001831 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001832 np->put_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001833 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001834 np->put_rx_ctx = np->first_rx_ctx;
david decotigny0a1f2222011-11-16 12:15:14 +00001835 } else {
Larry Finger612a7c42012-12-27 17:25:41 +00001836packet_dropped:
david decotigny0a1f2222011-11-16 12:15:14 +00001837 u64_stats_update_begin(&np->swstats_rx_syncp);
1838 np->stat_rx_dropped++;
1839 u64_stats_update_end(&np->swstats_rx_syncp);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001840 return 1;
david decotigny0a1f2222011-11-16 12:15:14 +00001841 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001842 }
1843 return 0;
1844}
1845
1846static int nv_alloc_rx_optimized(struct net_device *dev)
1847{
1848 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001849 struct ring_desc_ex *less_rx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001850
1851 less_rx = np->get_rx.ex;
1852 if (less_rx-- == np->first_rx.ex)
1853 less_rx = np->last_rx.ex;
1854
1855 while (np->put_rx.ex != less_rx) {
Pradeep A. Dalvidae2e9f2012-02-06 11:16:13 +00001856 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001857 if (skb) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001858 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001859 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1860 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001861 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001862 PCI_DMA_FROMDEVICE);
Larry Finger612a7c42012-12-27 17:25:41 +00001863 if (pci_dma_mapping_error(np->pci_dev,
1864 np->put_rx_ctx->dma)) {
1865 kfree_skb(skb);
1866 goto packet_dropped;
1867 }
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001868 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Al Viro5bb7ea22007-12-09 16:06:41 +00001869 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1870 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001871 wmb();
1872 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001873 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001874 np->put_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001875 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001876 np->put_rx_ctx = np->first_rx_ctx;
david decotigny0a1f2222011-11-16 12:15:14 +00001877 } else {
Larry Finger612a7c42012-12-27 17:25:41 +00001878packet_dropped:
david decotigny0a1f2222011-11-16 12:15:14 +00001879 u64_stats_update_begin(&np->swstats_rx_syncp);
1880 np->stat_rx_dropped++;
1881 u64_stats_update_end(&np->swstats_rx_syncp);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001882 return 1;
david decotigny0a1f2222011-11-16 12:15:14 +00001883 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001884 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001885 return 0;
1886}
1887
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001888/* If rx bufs are exhausted called after 50ms to attempt to refresh */
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001889static void nv_do_rx_refill(unsigned long data)
1890{
1891 struct net_device *dev = (struct net_device *) data;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001892 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001893
1894 /* Just reschedule NAPI rx processing */
Ben Hutchings288379f2009-01-19 16:43:59 -08001895 napi_schedule(&np->napi);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001896}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001897
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001898static void nv_init_rx(struct net_device *dev)
Manfred Sprauld81c0982005-07-31 18:20:30 +02001899{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001900 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02001901 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001902
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001903 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001904
1905 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001906 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1907 else
1908 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1909 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1910 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
Manfred Sprauld81c0982005-07-31 18:20:30 +02001911
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001912 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001913 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001914 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001915 np->rx_ring.orig[i].buf = 0;
1916 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001917 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001918 np->rx_ring.ex[i].txvlan = 0;
1919 np->rx_ring.ex[i].bufhigh = 0;
1920 np->rx_ring.ex[i].buflow = 0;
1921 }
1922 np->rx_skb[i].skb = NULL;
1923 np->rx_skb[i].dma = 0;
1924 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001925}
1926
1927static void nv_init_tx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001928{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001929 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001930 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001931
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001932 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001933
1934 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001935 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1936 else
1937 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1938 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1939 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
Tom Herbertb8bfca92011-11-28 16:33:23 +00001940 netdev_reset_queue(np->dev);
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001941 np->tx_pkts_in_progress = 0;
1942 np->tx_change_owner = NULL;
1943 np->tx_end_flip = NULL;
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00001944 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001945
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001946 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001947 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001948 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001949 np->tx_ring.orig[i].buf = 0;
1950 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001951 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001952 np->tx_ring.ex[i].txvlan = 0;
1953 np->tx_ring.ex[i].bufhigh = 0;
1954 np->tx_ring.ex[i].buflow = 0;
1955 }
1956 np->tx_skb[i].skb = NULL;
1957 np->tx_skb[i].dma = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001958 np->tx_skb[i].dma_len = 0;
Eric Dumazet73a37072009-06-17 21:17:59 +00001959 np->tx_skb[i].dma_single = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001960 np->tx_skb[i].first_tx_desc = NULL;
1961 np->tx_skb[i].next_tx_ctx = NULL;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001962 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001963}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001964
Manfred Sprauld81c0982005-07-31 18:20:30 +02001965static int nv_init_ring(struct net_device *dev)
1966{
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001967 struct fe_priv *np = netdev_priv(dev);
1968
Manfred Sprauld81c0982005-07-31 18:20:30 +02001969 nv_init_tx(dev);
1970 nv_init_rx(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001971
1972 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001973 return nv_alloc_rx(dev);
1974 else
1975 return nv_alloc_rx_optimized(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001976}
1977
Eric Dumazet73a37072009-06-17 21:17:59 +00001978static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001979{
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001980 if (tx_skb->dma) {
Eric Dumazet73a37072009-06-17 21:17:59 +00001981 if (tx_skb->dma_single)
1982 pci_unmap_single(np->pci_dev, tx_skb->dma,
1983 tx_skb->dma_len,
1984 PCI_DMA_TODEVICE);
1985 else
1986 pci_unmap_page(np->pci_dev, tx_skb->dma,
1987 tx_skb->dma_len,
1988 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001989 tx_skb->dma = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001990 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001991}
1992
1993static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1994{
1995 nv_unmap_txskb(np, tx_skb);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001996 if (tx_skb->skb) {
1997 dev_kfree_skb_any(tx_skb->skb);
1998 tx_skb->skb = NULL;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001999 return 1;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002000 }
Eric Dumazet73a37072009-06-17 21:17:59 +00002001 return 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002002}
2003
Linus Torvalds1da177e2005-04-16 15:20:36 -07002004static void nv_drain_tx(struct net_device *dev)
2005{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002006 struct fe_priv *np = netdev_priv(dev);
2007 unsigned int i;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002008
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002009 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002010 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002011 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002012 np->tx_ring.orig[i].buf = 0;
2013 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002014 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002015 np->tx_ring.ex[i].txvlan = 0;
2016 np->tx_ring.ex[i].bufhigh = 0;
2017 np->tx_ring.ex[i].buflow = 0;
2018 }
david decotignyf5d827a2011-11-16 12:15:13 +00002019 if (nv_release_txskb(np, &np->tx_skb[i])) {
2020 u64_stats_update_begin(&np->swstats_tx_syncp);
2021 np->stat_tx_dropped++;
2022 u64_stats_update_end(&np->swstats_tx_syncp);
2023 }
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002024 np->tx_skb[i].dma = 0;
2025 np->tx_skb[i].dma_len = 0;
Eric Dumazet73a37072009-06-17 21:17:59 +00002026 np->tx_skb[i].dma_single = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002027 np->tx_skb[i].first_tx_desc = NULL;
2028 np->tx_skb[i].next_tx_ctx = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002029 }
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002030 np->tx_pkts_in_progress = 0;
2031 np->tx_change_owner = NULL;
2032 np->tx_end_flip = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002033}
2034
2035static void nv_drain_rx(struct net_device *dev)
2036{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002037 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002038 int i;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002039
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002040 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002041 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002042 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002043 np->rx_ring.orig[i].buf = 0;
2044 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002045 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002046 np->rx_ring.ex[i].txvlan = 0;
2047 np->rx_ring.ex[i].bufhigh = 0;
2048 np->rx_ring.ex[i].buflow = 0;
2049 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002050 wmb();
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002051 if (np->rx_skb[i].skb) {
2052 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07002053 (skb_end_pointer(np->rx_skb[i].skb) -
2054 np->rx_skb[i].skb->data),
2055 PCI_DMA_FROMDEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002056 dev_kfree_skb(np->rx_skb[i].skb);
2057 np->rx_skb[i].skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002058 }
2059 }
2060}
2061
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002062static void nv_drain_rxtx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002063{
2064 nv_drain_tx(dev);
2065 nv_drain_rx(dev);
2066}
2067
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002068static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2069{
2070 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2071}
2072
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002073static void nv_legacybackoff_reseed(struct net_device *dev)
2074{
2075 u8 __iomem *base = get_hwbase(dev);
2076 u32 reg;
2077 u32 low;
2078 int tx_status = 0;
2079
2080 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2081 get_random_bytes(&low, sizeof(low));
2082 reg |= low & NVREG_SLOTTIME_MASK;
2083
2084 /* Need to stop tx before change takes effect.
2085 * Caller has already gained np->lock.
2086 */
2087 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2088 if (tx_status)
2089 nv_stop_tx(dev);
2090 nv_stop_rx(dev);
2091 writel(reg, base + NvRegSlotTime);
2092 if (tx_status)
2093 nv_start_tx(dev);
2094 nv_start_rx(dev);
2095}
2096
2097/* Gear Backoff Seeds */
2098#define BACKOFF_SEEDSET_ROWS 8
2099#define BACKOFF_SEEDSET_LFSRS 15
2100
2101/* Known Good seed sets */
2102static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002103 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2104 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2105 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2106 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2107 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2108 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2109 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2110 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002111
2112static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002113 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2114 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2115 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2116 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2117 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2118 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2119 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2120 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002121
2122static void nv_gear_backoff_reseed(struct net_device *dev)
2123{
2124 u8 __iomem *base = get_hwbase(dev);
2125 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2126 u32 temp, seedset, combinedSeed;
2127 int i;
2128
2129 /* Setup seed for free running LFSR */
2130 /* We are going to read the time stamp counter 3 times
2131 and swizzle bits around to increase randomness */
2132 get_random_bytes(&miniseed1, sizeof(miniseed1));
2133 miniseed1 &= 0x0fff;
2134 if (miniseed1 == 0)
2135 miniseed1 = 0xabc;
2136
2137 get_random_bytes(&miniseed2, sizeof(miniseed2));
2138 miniseed2 &= 0x0fff;
2139 if (miniseed2 == 0)
2140 miniseed2 = 0xabc;
2141 miniseed2_reversed =
2142 ((miniseed2 & 0xF00) >> 8) |
2143 (miniseed2 & 0x0F0) |
2144 ((miniseed2 & 0x00F) << 8);
2145
2146 get_random_bytes(&miniseed3, sizeof(miniseed3));
2147 miniseed3 &= 0x0fff;
2148 if (miniseed3 == 0)
2149 miniseed3 = 0xabc;
2150 miniseed3_reversed =
2151 ((miniseed3 & 0xF00) >> 8) |
2152 (miniseed3 & 0x0F0) |
2153 ((miniseed3 & 0x00F) << 8);
2154
2155 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2156 (miniseed2 ^ miniseed3_reversed);
2157
2158 /* Seeds can not be zero */
2159 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2160 combinedSeed |= 0x08;
2161 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2162 combinedSeed |= 0x8000;
2163
2164 /* No need to disable tx here */
2165 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2166 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2167 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002168 writel(temp, base + NvRegBackOffControl);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002169
Szymon Janc78aea4f2010-11-27 08:39:43 +00002170 /* Setup seeds for all gear LFSRs. */
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002171 get_random_bytes(&seedset, sizeof(seedset));
2172 seedset = seedset % BACKOFF_SEEDSET_ROWS;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002173 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002174 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2175 temp |= main_seedset[seedset][i-1] & 0x3ff;
2176 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2177 writel(temp, base + NvRegBackOffControl);
2178 }
2179}
2180
Linus Torvalds1da177e2005-04-16 15:20:36 -07002181/*
2182 * nv_start_xmit: dev->hard_start_xmit function
Herbert Xu932ff272006-06-09 12:20:56 -07002183 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002184 */
Stephen Hemminger613573252009-08-31 19:50:58 +00002185static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002186{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002187 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002188 u32 tx_flags = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002189 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2190 unsigned int fragments = skb_shinfo(skb)->nr_frags;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002191 unsigned int i;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002192 u32 offset = 0;
2193 u32 bcnt;
Eric Dumazete743d312010-04-14 15:59:40 -07002194 u32 size = skb_headlen(skb);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002195 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002196 u32 empty_slots;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002197 struct ring_desc *put_tx;
2198 struct ring_desc *start_tx;
2199 struct ring_desc *prev_tx;
2200 struct nv_skb_map *prev_tx_ctx;
Neil Hormanf7f22872013-04-01 04:31:58 +00002201 struct nv_skb_map *tmp_tx_ctx = NULL, *start_tx_ctx = NULL;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002202 unsigned long flags;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002203
2204 /* add fragments to entries count */
2205 for (i = 0; i < fragments; i++) {
david decotignye45a6182011-11-05 14:38:24 +00002206 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
Eric Dumazet9e903e02011-10-18 21:00:24 +00002207
david decotignye45a6182011-11-05 14:38:24 +00002208 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2209 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002210 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002211
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002212 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002213 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002214 if (unlikely(empty_slots <= entries)) {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002215 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002216 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002217 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002218 return NETDEV_TX_BUSY;
2219 }
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002220 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002221
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002222 start_tx = put_tx = np->put_tx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002223
Ayaz Abdullafa454592006-01-05 22:45:45 -08002224 /* setup the header buffer */
2225 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002226 prev_tx = put_tx;
2227 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002228 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002229 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
Ayaz Abdullafa454592006-01-05 22:45:45 -08002230 PCI_DMA_TODEVICE);
Larry Finger612a7c42012-12-27 17:25:41 +00002231 if (pci_dma_mapping_error(np->pci_dev,
2232 np->put_tx_ctx->dma)) {
2233 /* on DMA mapping error - drop the packet */
Eric W. Biederman16165662014-03-15 17:54:27 -07002234 dev_kfree_skb_any(skb);
Larry Finger612a7c42012-12-27 17:25:41 +00002235 u64_stats_update_begin(&np->swstats_tx_syncp);
2236 np->stat_tx_dropped++;
2237 u64_stats_update_end(&np->swstats_tx_syncp);
2238 return NETDEV_TX_OK;
2239 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002240 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002241 np->put_tx_ctx->dma_single = 1;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002242 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2243 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002244
Ayaz Abdullafa454592006-01-05 22:45:45 -08002245 tx_flags = np->tx_flags;
2246 offset += bcnt;
2247 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002248 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002249 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002250 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002251 np->put_tx_ctx = np->first_tx_ctx;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002252 } while (size);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002253
2254 /* setup the fragments */
2255 for (i = 0; i < fragments; i++) {
Eric Dumazet9e903e02011-10-18 21:00:24 +00002256 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
david decotignye45a6182011-11-05 14:38:24 +00002257 u32 frag_size = skb_frag_size(frag);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002258 offset = 0;
2259
2260 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002261 prev_tx = put_tx;
2262 prev_tx_ctx = np->put_tx_ctx;
Neil Hormanf7f22872013-04-01 04:31:58 +00002263 if (!start_tx_ctx)
2264 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
2265
david decotignye45a6182011-11-05 14:38:24 +00002266 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
Ian Campbell671173c2011-08-29 23:18:28 +00002267 np->put_tx_ctx->dma = skb_frag_dma_map(
2268 &np->pci_dev->dev,
2269 frag, offset,
2270 bcnt,
Ian Campbell5d6bcdf2011-10-06 11:10:48 +01002271 DMA_TO_DEVICE);
Neil Hormanf7f22872013-04-01 04:31:58 +00002272 if (dma_mapping_error(&np->pci_dev->dev, np->put_tx_ctx->dma)) {
2273
2274 /* Unwind the mapped fragments */
2275 do {
2276 nv_unmap_txskb(np, start_tx_ctx);
2277 if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2278 tmp_tx_ctx = np->first_tx_ctx;
2279 } while (tmp_tx_ctx != np->put_tx_ctx);
Eric W. Biederman16165662014-03-15 17:54:27 -07002280 dev_kfree_skb_any(skb);
Neil Hormanf7f22872013-04-01 04:31:58 +00002281 np->put_tx_ctx = start_tx_ctx;
2282 u64_stats_update_begin(&np->swstats_tx_syncp);
2283 np->stat_tx_dropped++;
2284 u64_stats_update_end(&np->swstats_tx_syncp);
2285 return NETDEV_TX_OK;
2286 }
2287
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002288 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002289 np->put_tx_ctx->dma_single = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002290 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2291 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002292
Ayaz Abdullafa454592006-01-05 22:45:45 -08002293 offset += bcnt;
david decotignye45a6182011-11-05 14:38:24 +00002294 frag_size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002295 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002296 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002297 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002298 np->put_tx_ctx = np->first_tx_ctx;
david decotignye45a6182011-11-05 14:38:24 +00002299 } while (frag_size);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002300 }
2301
Ayaz Abdullafa454592006-01-05 22:45:45 -08002302 /* set last fragment flag */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002303 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002304
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002305 /* save skb in this slot's context area */
2306 prev_tx_ctx->skb = skb;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002307
Herbert Xu89114af2006-07-08 13:34:32 -07002308 if (skb_is_gso(skb))
Herbert Xu79671682006-06-22 02:40:14 -07002309 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
Manfred Spraulee733622005-07-31 18:32:26 +02002310 else
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002311 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
Patrick McHardy84fa7932006-08-29 16:44:56 -07002312 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002313
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002314 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla164a86e2007-01-09 13:30:10 -05002315
Ayaz Abdullafa454592006-01-05 22:45:45 -08002316 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002317 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
Tom Herbertb8bfca92011-11-28 16:33:23 +00002318
2319 netdev_sent_queue(np->dev, skb->len);
2320
Willem de Bruijn49cbb1c2012-04-27 09:04:07 +00002321 skb_tx_timestamp(skb);
2322
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002323 np->put_tx.orig = put_tx;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002324
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002325 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002326
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002327 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002328 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002329}
2330
Stephen Hemminger613573252009-08-31 19:50:58 +00002331static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2332 struct net_device *dev)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002333{
2334 struct fe_priv *np = netdev_priv(dev);
2335 u32 tx_flags = 0;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002336 u32 tx_flags_extra;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002337 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2338 unsigned int i;
2339 u32 offset = 0;
2340 u32 bcnt;
Eric Dumazete743d312010-04-14 15:59:40 -07002341 u32 size = skb_headlen(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002342 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2343 u32 empty_slots;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002344 struct ring_desc_ex *put_tx;
2345 struct ring_desc_ex *start_tx;
2346 struct ring_desc_ex *prev_tx;
2347 struct nv_skb_map *prev_tx_ctx;
Neil Hormanf7f22872013-04-01 04:31:58 +00002348 struct nv_skb_map *start_tx_ctx = NULL;
2349 struct nv_skb_map *tmp_tx_ctx = NULL;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002350 unsigned long flags;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002351
2352 /* add fragments to entries count */
2353 for (i = 0; i < fragments; i++) {
david decotignye45a6182011-11-05 14:38:24 +00002354 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
Eric Dumazet9e903e02011-10-18 21:00:24 +00002355
david decotignye45a6182011-11-05 14:38:24 +00002356 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2357 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002358 }
2359
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002360 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002361 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002362 if (unlikely(empty_slots <= entries)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002363 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002364 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002365 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002366 return NETDEV_TX_BUSY;
2367 }
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002368 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002369
2370 start_tx = put_tx = np->put_tx.ex;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002371 start_tx_ctx = np->put_tx_ctx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002372
2373 /* setup the header buffer */
2374 do {
2375 prev_tx = put_tx;
2376 prev_tx_ctx = np->put_tx_ctx;
2377 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2378 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2379 PCI_DMA_TODEVICE);
Larry Finger612a7c42012-12-27 17:25:41 +00002380 if (pci_dma_mapping_error(np->pci_dev,
2381 np->put_tx_ctx->dma)) {
2382 /* on DMA mapping error - drop the packet */
Eric W. Biederman16165662014-03-15 17:54:27 -07002383 dev_kfree_skb_any(skb);
Larry Finger612a7c42012-12-27 17:25:41 +00002384 u64_stats_update_begin(&np->swstats_tx_syncp);
2385 np->stat_tx_dropped++;
2386 u64_stats_update_end(&np->swstats_tx_syncp);
2387 return NETDEV_TX_OK;
2388 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002389 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002390 np->put_tx_ctx->dma_single = 1;
Al Viro5bb7ea22007-12-09 16:06:41 +00002391 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2392 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002393 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002394
2395 tx_flags = NV_TX2_VALID;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002396 offset += bcnt;
2397 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002398 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002399 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002400 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002401 np->put_tx_ctx = np->first_tx_ctx;
2402 } while (size);
2403
2404 /* setup the fragments */
2405 for (i = 0; i < fragments; i++) {
2406 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
david decotignye45a6182011-11-05 14:38:24 +00002407 u32 frag_size = skb_frag_size(frag);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002408 offset = 0;
2409
2410 do {
2411 prev_tx = put_tx;
2412 prev_tx_ctx = np->put_tx_ctx;
david decotignye45a6182011-11-05 14:38:24 +00002413 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
Neil Hormanf7f22872013-04-01 04:31:58 +00002414 if (!start_tx_ctx)
2415 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
Ian Campbell671173c2011-08-29 23:18:28 +00002416 np->put_tx_ctx->dma = skb_frag_dma_map(
2417 &np->pci_dev->dev,
2418 frag, offset,
2419 bcnt,
Ian Campbell5d6bcdf2011-10-06 11:10:48 +01002420 DMA_TO_DEVICE);
Neil Hormanf7f22872013-04-01 04:31:58 +00002421
2422 if (dma_mapping_error(&np->pci_dev->dev, np->put_tx_ctx->dma)) {
2423
2424 /* Unwind the mapped fragments */
2425 do {
2426 nv_unmap_txskb(np, start_tx_ctx);
2427 if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2428 tmp_tx_ctx = np->first_tx_ctx;
2429 } while (tmp_tx_ctx != np->put_tx_ctx);
Eric W. Biederman16165662014-03-15 17:54:27 -07002430 dev_kfree_skb_any(skb);
Neil Hormanf7f22872013-04-01 04:31:58 +00002431 np->put_tx_ctx = start_tx_ctx;
2432 u64_stats_update_begin(&np->swstats_tx_syncp);
2433 np->stat_tx_dropped++;
2434 u64_stats_update_end(&np->swstats_tx_syncp);
2435 return NETDEV_TX_OK;
2436 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002437 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002438 np->put_tx_ctx->dma_single = 0;
Al Viro5bb7ea22007-12-09 16:06:41 +00002439 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2440 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002441 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002442
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002443 offset += bcnt;
david decotignye45a6182011-11-05 14:38:24 +00002444 frag_size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002445 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002446 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002447 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002448 np->put_tx_ctx = np->first_tx_ctx;
david decotignye45a6182011-11-05 14:38:24 +00002449 } while (frag_size);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002450 }
2451
2452 /* set last fragment flag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002453 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002454
2455 /* save skb in this slot's context area */
2456 prev_tx_ctx->skb = skb;
2457
2458 if (skb_is_gso(skb))
2459 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2460 else
2461 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2462 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2463
2464 /* vlan tag */
Jesse Grosseab6d182010-10-20 13:56:03 +00002465 if (vlan_tx_tag_present(skb))
2466 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2467 vlan_tx_tag_get(skb));
2468 else
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002469 start_tx->txvlan = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002470
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002471 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002472
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002473 if (np->tx_limit) {
2474 /* Limit the number of outstanding tx. Setup all fragments, but
2475 * do not set the VALID bit on the first descriptor. Save a pointer
2476 * to that descriptor and also for next skb_map element.
2477 */
2478
2479 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2480 if (!np->tx_change_owner)
2481 np->tx_change_owner = start_tx_ctx;
2482
2483 /* remove VALID bit */
2484 tx_flags &= ~NV_TX2_VALID;
2485 start_tx_ctx->first_tx_desc = start_tx;
2486 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2487 np->tx_end_flip = np->put_tx_ctx;
2488 } else {
2489 np->tx_pkts_in_progress++;
2490 }
2491 }
2492
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002493 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002494 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
Tom Herbertb8bfca92011-11-28 16:33:23 +00002495
2496 netdev_sent_queue(np->dev, skb->len);
2497
Willem de Bruijn49cbb1c2012-04-27 09:04:07 +00002498 skb_tx_timestamp(skb);
2499
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002500 np->put_tx.ex = put_tx;
2501
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002502 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002503
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002504 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002505 return NETDEV_TX_OK;
2506}
2507
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002508static inline void nv_tx_flip_ownership(struct net_device *dev)
2509{
2510 struct fe_priv *np = netdev_priv(dev);
2511
2512 np->tx_pkts_in_progress--;
2513 if (np->tx_change_owner) {
Al Viro30ecce92008-03-26 05:57:12 +00002514 np->tx_change_owner->first_tx_desc->flaglen |=
2515 cpu_to_le32(NV_TX2_VALID);
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002516 np->tx_pkts_in_progress++;
2517
2518 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2519 if (np->tx_change_owner == np->tx_end_flip)
2520 np->tx_change_owner = NULL;
2521
2522 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2523 }
2524}
2525
Linus Torvalds1da177e2005-04-16 15:20:36 -07002526/*
2527 * nv_tx_done: check for completed packets, release the skbs.
2528 *
2529 * Caller must own np->lock.
2530 */
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002531static int nv_tx_done(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002532{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002533 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002534 u32 flags;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002535 int tx_work = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002536 struct ring_desc *orig_get_tx = np->get_tx.orig;
Tom Herbertb8bfca92011-11-28 16:33:23 +00002537 unsigned int bytes_compl = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002538
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002539 while ((np->get_tx.orig != np->put_tx.orig) &&
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002540 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2541 (tx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002542
Eric Dumazet73a37072009-06-17 21:17:59 +00002543 nv_unmap_txskb(np, np->get_tx_ctx);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002544
Linus Torvalds1da177e2005-04-16 15:20:36 -07002545 if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002546 if (flags & NV_TX_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002547 if (flags & NV_TX_ERROR) {
david decotignyf5d827a2011-11-16 12:15:13 +00002548 if ((flags & NV_TX_RETRYERROR)
2549 && !(flags & NV_TX_RETRYCOUNT_MASK))
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002550 nv_legacybackoff_reseed(dev);
david decotigny674aee32011-11-16 12:15:07 +00002551 } else {
david decotignyf5d827a2011-11-16 12:15:13 +00002552 u64_stats_update_begin(&np->swstats_tx_syncp);
2553 np->stat_tx_packets++;
2554 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2555 u64_stats_update_end(&np->swstats_tx_syncp);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002556 }
Tom Herbertb8bfca92011-11-28 16:33:23 +00002557 bytes_compl += np->get_tx_ctx->skb->len;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002558 dev_kfree_skb_any(np->get_tx_ctx->skb);
2559 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002560 tx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002561 }
2562 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002563 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002564 if (flags & NV_TX2_ERROR) {
david decotignyf5d827a2011-11-16 12:15:13 +00002565 if ((flags & NV_TX2_RETRYERROR)
2566 && !(flags & NV_TX2_RETRYCOUNT_MASK))
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002567 nv_legacybackoff_reseed(dev);
david decotigny674aee32011-11-16 12:15:07 +00002568 } else {
david decotignyf5d827a2011-11-16 12:15:13 +00002569 u64_stats_update_begin(&np->swstats_tx_syncp);
2570 np->stat_tx_packets++;
2571 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2572 u64_stats_update_end(&np->swstats_tx_syncp);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002573 }
Tom Herbertb8bfca92011-11-28 16:33:23 +00002574 bytes_compl += np->get_tx_ctx->skb->len;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002575 dev_kfree_skb_any(np->get_tx_ctx->skb);
2576 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002577 tx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002578 }
2579 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002580 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002581 np->get_tx.orig = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002582 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002583 np->get_tx_ctx = np->first_tx_ctx;
2584 }
Tom Herbertb8bfca92011-11-28 16:33:23 +00002585
2586 netdev_completed_queue(np->dev, tx_work, bytes_compl);
2587
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002588 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002589 np->tx_stop = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002590 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002591 }
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002592 return tx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002593}
2594
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002595static int nv_tx_done_optimized(struct net_device *dev, int limit)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002596{
2597 struct fe_priv *np = netdev_priv(dev);
2598 u32 flags;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002599 int tx_work = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002600 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
Tom Herbertb8bfca92011-11-28 16:33:23 +00002601 unsigned long bytes_cleaned = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002602
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002603 while ((np->get_tx.ex != np->put_tx.ex) &&
Julia Lawall217d32d2010-07-05 22:15:47 -07002604 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002605 (tx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002606
Eric Dumazet73a37072009-06-17 21:17:59 +00002607 nv_unmap_txskb(np, np->get_tx_ctx);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002608
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002609 if (flags & NV_TX2_LASTPACKET) {
david decotigny4687f3f2011-11-05 14:38:22 +00002610 if (flags & NV_TX2_ERROR) {
david decotignyf5d827a2011-11-16 12:15:13 +00002611 if ((flags & NV_TX2_RETRYERROR)
2612 && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002613 if (np->driver_data & DEV_HAS_GEAR_MODE)
2614 nv_gear_backoff_reseed(dev);
2615 else
2616 nv_legacybackoff_reseed(dev);
2617 }
david decotigny674aee32011-11-16 12:15:07 +00002618 } else {
David S. Millerefd0bf92011-11-21 13:50:33 -05002619 u64_stats_update_begin(&np->swstats_tx_syncp);
2620 np->stat_tx_packets++;
2621 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2622 u64_stats_update_end(&np->swstats_tx_syncp);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002623 }
2624
Tom Herbertb8bfca92011-11-28 16:33:23 +00002625 bytes_cleaned += np->get_tx_ctx->skb->len;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002626 dev_kfree_skb_any(np->get_tx_ctx->skb);
2627 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002628 tx_work++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002629
Szymon Janc78aea4f2010-11-27 08:39:43 +00002630 if (np->tx_limit)
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002631 nv_tx_flip_ownership(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002632 }
Tom Herbertb8bfca92011-11-28 16:33:23 +00002633
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002634 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002635 np->get_tx.ex = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002636 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002637 np->get_tx_ctx = np->first_tx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002638 }
Igor Maravic7505afe2011-12-01 23:48:20 +00002639
2640 netdev_completed_queue(np->dev, tx_work, bytes_cleaned);
2641
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002642 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002643 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002644 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002645 }
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002646 return tx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002647}
2648
2649/*
2650 * nv_tx_timeout: dev->tx_timeout function
Herbert Xu932ff272006-06-09 12:20:56 -07002651 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002652 */
2653static void nv_tx_timeout(struct net_device *dev)
2654{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002655 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002656 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002657 u32 status;
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002658 union ring_type put_tx;
2659 int saved_tx_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002660
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002661 if (np->msi_flags & NV_MSI_X_ENABLED)
2662 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2663 else
2664 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2665
Sameer Nanda1ec4f2d2011-11-16 12:15:12 +00002666 netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002667
Sameer Nanda1ec4f2d2011-11-16 12:15:12 +00002668 if (unlikely(debug_tx_timeout)) {
2669 int i;
2670
2671 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2672 netdev_info(dev, "Dumping tx registers\n");
2673 for (i = 0; i <= np->register_size; i += 32) {
Joe Perches1d397f32010-11-29 07:41:57 +00002674 netdev_info(dev,
Sameer Nanda1ec4f2d2011-11-16 12:15:12 +00002675 "%3x: %08x %08x %08x %08x "
2676 "%08x %08x %08x %08x\n",
Joe Perches1d397f32010-11-29 07:41:57 +00002677 i,
Sameer Nanda1ec4f2d2011-11-16 12:15:12 +00002678 readl(base + i + 0), readl(base + i + 4),
2679 readl(base + i + 8), readl(base + i + 12),
2680 readl(base + i + 16), readl(base + i + 20),
2681 readl(base + i + 24), readl(base + i + 28));
2682 }
2683 netdev_info(dev, "Dumping tx ring\n");
2684 for (i = 0; i < np->tx_ring_size; i += 4) {
2685 if (!nv_optimized(np)) {
2686 netdev_info(dev,
2687 "%03x: %08x %08x // %08x %08x "
2688 "// %08x %08x // %08x %08x\n",
2689 i,
2690 le32_to_cpu(np->tx_ring.orig[i].buf),
2691 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2692 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2693 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2694 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2695 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2696 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2697 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2698 } else {
2699 netdev_info(dev,
2700 "%03x: %08x %08x %08x "
2701 "// %08x %08x %08x "
2702 "// %08x %08x %08x "
2703 "// %08x %08x %08x\n",
2704 i,
2705 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2706 le32_to_cpu(np->tx_ring.ex[i].buflow),
2707 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2708 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2709 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2710 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2711 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2712 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2713 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2714 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2715 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2716 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2717 }
Manfred Spraulc2dba062005-07-31 18:29:47 +02002718 }
2719 }
2720
Linus Torvalds1da177e2005-04-16 15:20:36 -07002721 spin_lock_irq(&np->lock);
2722
2723 /* 1) stop tx engine */
2724 nv_stop_tx(dev);
2725
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002726 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2727 saved_tx_limit = np->tx_limit;
2728 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2729 np->tx_stop = 0; /* prevent waking tx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002730 if (!nv_optimized(np))
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002731 nv_tx_done(dev, np->tx_ring_size);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002732 else
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002733 nv_tx_done_optimized(dev, np->tx_ring_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002734
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002735 /* save current HW position */
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002736 if (np->tx_change_owner)
2737 put_tx.ex = np->tx_change_owner->first_tx_desc;
2738 else
2739 put_tx = np->put_tx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002740
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002741 /* 3) clear all tx state */
2742 nv_drain_tx(dev);
2743 nv_init_tx(dev);
Ayaz Abdulla3ba4d092007-03-23 05:50:02 -05002744
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002745 /* 4) restore state to current HW position */
2746 np->get_tx = np->put_tx = put_tx;
2747 np->tx_limit = saved_tx_limit;
2748
2749 /* 5) restart tx engine */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002750 nv_start_tx(dev);
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002751 netif_wake_queue(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002752 spin_unlock_irq(&np->lock);
2753}
2754
Manfred Spraul22c6d142005-04-19 21:17:09 +02002755/*
2756 * Called when the nic notices a mismatch between the actual data len on the
2757 * wire and the len indicated in the 802 header
2758 */
2759static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2760{
2761 int hdrlen; /* length of the 802 header */
2762 int protolen; /* length as stored in the proto field */
2763
2764 /* 1) calculate len according to header */
Szymon Janc78aea4f2010-11-27 08:39:43 +00002765 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2766 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002767 hdrlen = VLAN_HLEN;
2768 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002769 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002770 hdrlen = ETH_HLEN;
2771 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02002772 if (protolen > ETH_DATA_LEN)
2773 return datalen; /* Value in proto field not a len, no checks possible */
2774
2775 protolen += hdrlen;
2776 /* consistency checks: */
2777 if (datalen > ETH_ZLEN) {
2778 if (datalen >= protolen) {
2779 /* more data on wire than in 802 header, trim of
2780 * additional data.
2781 */
Manfred Spraul22c6d142005-04-19 21:17:09 +02002782 return protolen;
2783 } else {
2784 /* less data on wire than mentioned in header.
2785 * Discard the packet.
2786 */
Manfred Spraul22c6d142005-04-19 21:17:09 +02002787 return -1;
2788 }
2789 } else {
2790 /* short packet. Accept only if 802 values are also short */
2791 if (protolen > ETH_ZLEN) {
Manfred Spraul22c6d142005-04-19 21:17:09 +02002792 return -1;
2793 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02002794 return datalen;
2795 }
2796}
2797
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002798static int nv_rx_process(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002799{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002800 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002801 u32 flags;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002802 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002803 struct sk_buff *skb;
2804 int len;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05002805
Szymon Janc78aea4f2010-11-27 08:39:43 +00002806 while ((np->get_rx.orig != np->put_rx.orig) &&
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002807 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002808 (rx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002809
Linus Torvalds1da177e2005-04-16 15:20:36 -07002810 /*
2811 * the packet is for us - immediately tear down the pci mapping.
2812 * TODO: check if a prefetch of the first cacheline improves
2813 * the performance.
2814 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002815 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2816 np->get_rx_ctx->dma_len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002817 PCI_DMA_FROMDEVICE);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002818 skb = np->get_rx_ctx->skb;
2819 np->get_rx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002820
Linus Torvalds1da177e2005-04-16 15:20:36 -07002821 /* look at what we actually got: */
2822 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002823 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2824 len = flags & LEN_MASK_V1;
2825 if (unlikely(flags & NV_RX_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002826 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002827 len = nv_getlen(dev, skb->data, len);
2828 if (len < 0) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002829 dev_kfree_skb(skb);
2830 goto next_pkt;
2831 }
2832 }
2833 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002834 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
Antonio Ospitecef33c82014-06-04 14:03:47 +02002835 if (flags & NV_RX_SUBTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002836 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002837 }
2838 /* the rest are hard errors */
2839 else {
david decotignyf5d827a2011-11-16 12:15:13 +00002840 if (flags & NV_RX_MISSEDFRAME) {
2841 u64_stats_update_begin(&np->swstats_rx_syncp);
2842 np->stat_rx_missed_errors++;
2843 u64_stats_update_end(&np->swstats_rx_syncp);
2844 }
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002845 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002846 goto next_pkt;
2847 }
2848 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002849 } else {
2850 dev_kfree_skb(skb);
2851 goto next_pkt;
Manfred Spraul22c6d142005-04-19 21:17:09 +02002852 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002853 } else {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002854 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2855 len = flags & LEN_MASK_V2;
2856 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002857 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002858 len = nv_getlen(dev, skb->data, len);
2859 if (len < 0) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002860 dev_kfree_skb(skb);
2861 goto next_pkt;
2862 }
2863 }
2864 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002865 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Antonio Ospitecef33c82014-06-04 14:03:47 +02002866 if (flags & NV_RX2_SUBTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002867 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002868 }
2869 /* the rest are hard errors */
2870 else {
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002871 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002872 goto next_pkt;
2873 }
2874 }
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002875 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2876 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002877 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002878 } else {
2879 dev_kfree_skb(skb);
2880 goto next_pkt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002881 }
2882 }
2883 /* got a valid packet - forward it to the network core */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002884 skb_put(skb, len);
2885 skb->protocol = eth_type_trans(skb, dev);
Tom Herbert53f224c2010-05-03 19:08:45 +00002886 napi_gro_receive(&np->napi, skb);
david decotignyf5d827a2011-11-16 12:15:13 +00002887 u64_stats_update_begin(&np->swstats_rx_syncp);
2888 np->stat_rx_packets++;
2889 np->stat_rx_bytes += len;
2890 u64_stats_update_end(&np->swstats_rx_syncp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002891next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002892 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002893 np->get_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002894 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002895 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002896
2897 rx_work++;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002898 }
2899
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002900 return rx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002901}
2902
2903static int nv_rx_process_optimized(struct net_device *dev, int limit)
2904{
2905 struct fe_priv *np = netdev_priv(dev);
2906 u32 flags;
2907 u32 vlanflags = 0;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002908 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002909 struct sk_buff *skb;
2910 int len;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002911
Szymon Janc78aea4f2010-11-27 08:39:43 +00002912 while ((np->get_rx.ex != np->put_rx.ex) &&
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002913 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
Ingo Molnarc1b71512007-10-17 12:18:23 +02002914 (rx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002915
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002916 /*
2917 * the packet is for us - immediately tear down the pci mapping.
2918 * TODO: check if a prefetch of the first cacheline improves
2919 * the performance.
2920 */
2921 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2922 np->get_rx_ctx->dma_len,
2923 PCI_DMA_FROMDEVICE);
2924 skb = np->get_rx_ctx->skb;
2925 np->get_rx_ctx->skb = NULL;
2926
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002927 /* look at what we actually got: */
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002928 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2929 len = flags & LEN_MASK_V2;
2930 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002931 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002932 len = nv_getlen(dev, skb->data, len);
2933 if (len < 0) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002934 dev_kfree_skb(skb);
2935 goto next_pkt;
2936 }
2937 }
2938 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002939 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Antonio Ospitecef33c82014-06-04 14:03:47 +02002940 if (flags & NV_RX2_SUBTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002941 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002942 }
2943 /* the rest are hard errors */
2944 else {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002945 dev_kfree_skb(skb);
2946 goto next_pkt;
2947 }
2948 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002949
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002950 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2951 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002952 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002953
2954 /* got a valid packet - forward it to the network core */
2955 skb_put(skb, len);
2956 skb->protocol = eth_type_trans(skb, dev);
2957 prefetch(skb->data);
2958
Jiri Pirko3326c782011-07-20 04:54:38 +00002959 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
Jiri Pirko0891b0e2011-07-26 10:19:28 +00002960
2961 /*
Patrick McHardyf6469682013-04-19 02:04:27 +00002962 * There's need to check for NETIF_F_HW_VLAN_CTAG_RX
2963 * here. Even if vlan rx accel is disabled,
Jiri Pirko0891b0e2011-07-26 10:19:28 +00002964 * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2965 */
Patrick McHardyf6469682013-04-19 02:04:27 +00002966 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
Jiri Pirko0891b0e2011-07-26 10:19:28 +00002967 vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
Jiri Pirko3326c782011-07-20 04:54:38 +00002968 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2969
Patrick McHardy86a9bad2013-04-19 02:04:30 +00002970 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002971 }
Jiri Pirko3326c782011-07-20 04:54:38 +00002972 napi_gro_receive(&np->napi, skb);
david decotignyf5d827a2011-11-16 12:15:13 +00002973 u64_stats_update_begin(&np->swstats_rx_syncp);
2974 np->stat_rx_packets++;
2975 np->stat_rx_bytes += len;
2976 u64_stats_update_end(&np->swstats_rx_syncp);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002977 } else {
2978 dev_kfree_skb(skb);
2979 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002980next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002981 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002982 np->get_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002983 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002984 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002985
2986 rx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002987 }
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002988
Ingo Molnarc1b71512007-10-17 12:18:23 +02002989 return rx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002990}
2991
Manfred Sprauld81c0982005-07-31 18:20:30 +02002992static void set_bufsize(struct net_device *dev)
2993{
2994 struct fe_priv *np = netdev_priv(dev);
2995
2996 if (dev->mtu <= ETH_DATA_LEN)
2997 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2998 else
2999 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
3000}
3001
Linus Torvalds1da177e2005-04-16 15:20:36 -07003002/*
3003 * nv_change_mtu: dev->change_mtu function
3004 * Called with dev_base_lock held for read.
3005 */
3006static int nv_change_mtu(struct net_device *dev, int new_mtu)
3007{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003008 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003009 int old_mtu;
3010
3011 if (new_mtu < 64 || new_mtu > np->pkt_limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003012 return -EINVAL;
Manfred Sprauld81c0982005-07-31 18:20:30 +02003013
3014 old_mtu = dev->mtu;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003015 dev->mtu = new_mtu;
Manfred Sprauld81c0982005-07-31 18:20:30 +02003016
3017 /* return early if the buffer sizes will not change */
3018 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
3019 return 0;
3020 if (old_mtu == new_mtu)
3021 return 0;
3022
3023 /* synchronized against open : rtnl_lock() held by caller */
3024 if (netif_running(dev)) {
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01003025 u8 __iomem *base = get_hwbase(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003026 /*
3027 * It seems that the nic preloads valid ring entries into an
3028 * internal buffer. The procedure for flushing everything is
3029 * guessed, there is probably a simpler approach.
3030 * Changing the MTU is a rare event, it shouldn't matter.
3031 */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003032 nv_disable_irq(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00003033 nv_napi_disable(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07003034 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07003035 netif_addr_lock(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003036 spin_lock(&np->lock);
3037 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003038 nv_stop_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003039 nv_txrx_reset(dev);
3040 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003041 nv_drain_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003042 /* reinit driver view of the rx queue */
Manfred Sprauld81c0982005-07-31 18:20:30 +02003043 set_bufsize(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04003044 if (nv_init_ring(dev)) {
Manfred Sprauld81c0982005-07-31 18:20:30 +02003045 if (!np->in_shutdown)
3046 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3047 }
3048 /* reinit nic view of the rx queue */
3049 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05003050 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00003051 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Manfred Sprauld81c0982005-07-31 18:20:30 +02003052 base + NvRegRingSizes);
3053 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04003054 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003055 pci_push(base);
3056
3057 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003058 nv_start_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003059 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07003060 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07003061 netif_tx_unlock_bh(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00003062 nv_napi_enable(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003063 nv_enable_irq(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003064 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003065 return 0;
3066}
3067
Manfred Spraul72b31782005-07-31 18:33:34 +02003068static void nv_copy_mac_to_hw(struct net_device *dev)
3069{
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01003070 u8 __iomem *base = get_hwbase(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02003071 u32 mac[2];
3072
3073 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3074 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3075 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3076
3077 writel(mac[0], base + NvRegMacAddrA);
3078 writel(mac[1], base + NvRegMacAddrB);
3079}
3080
3081/*
3082 * nv_set_mac_address: dev->set_mac_address function
3083 * Called with rtnl_lock() held.
3084 */
3085static int nv_set_mac_address(struct net_device *dev, void *addr)
3086{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003087 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00003088 struct sockaddr *macaddr = (struct sockaddr *)addr;
Manfred Spraul72b31782005-07-31 18:33:34 +02003089
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003090 if (!is_valid_ether_addr(macaddr->sa_data))
Manfred Spraul72b31782005-07-31 18:33:34 +02003091 return -EADDRNOTAVAIL;
3092
3093 /* synchronized against open : rtnl_lock() held by caller */
3094 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3095
3096 if (netif_running(dev)) {
Herbert Xu932ff272006-06-09 12:20:56 -07003097 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07003098 netif_addr_lock(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02003099 spin_lock_irq(&np->lock);
3100
3101 /* stop rx engine */
3102 nv_stop_rx(dev);
3103
3104 /* set mac address */
3105 nv_copy_mac_to_hw(dev);
3106
3107 /* restart rx engine */
3108 nv_start_rx(dev);
3109 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07003110 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07003111 netif_tx_unlock_bh(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02003112 } else {
3113 nv_copy_mac_to_hw(dev);
3114 }
3115 return 0;
3116}
3117
Linus Torvalds1da177e2005-04-16 15:20:36 -07003118/*
3119 * nv_set_multicast: dev->set_multicast function
Herbert Xu932ff272006-06-09 12:20:56 -07003120 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003121 */
3122static void nv_set_multicast(struct net_device *dev)
3123{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003124 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003125 u8 __iomem *base = get_hwbase(dev);
3126 u32 addr[2];
3127 u32 mask[2];
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003128 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003129
3130 memset(addr, 0, sizeof(addr));
3131 memset(mask, 0, sizeof(mask));
3132
3133 if (dev->flags & IFF_PROMISC) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003134 pff |= NVREG_PFF_PROMISC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003135 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003136 pff |= NVREG_PFF_MYADDR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003137
Jiri Pirko48e2f182010-02-22 09:22:26 +00003138 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003139 u32 alwaysOff[2];
3140 u32 alwaysOn[2];
3141
3142 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3143 if (dev->flags & IFF_ALLMULTI) {
3144 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3145 } else {
Jiri Pirko22bedad32010-04-01 21:22:57 +00003146 struct netdev_hw_addr *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003147
Jiri Pirko22bedad32010-04-01 21:22:57 +00003148 netdev_for_each_mc_addr(ha, dev) {
david decotignye45a6182011-11-05 14:38:24 +00003149 unsigned char *hw_addr = ha->addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003150 u32 a, b;
Jiri Pirko22bedad32010-04-01 21:22:57 +00003151
david decotignye45a6182011-11-05 14:38:24 +00003152 a = le32_to_cpu(*(__le32 *) hw_addr);
3153 b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07003154 alwaysOn[0] &= a;
3155 alwaysOff[0] &= ~a;
3156 alwaysOn[1] &= b;
3157 alwaysOff[1] &= ~b;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003158 }
3159 }
3160 addr[0] = alwaysOn[0];
3161 addr[1] = alwaysOn[1];
3162 mask[0] = alwaysOn[0] | alwaysOff[0];
3163 mask[1] = alwaysOn[1] | alwaysOff[1];
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05003164 } else {
3165 mask[0] = NVREG_MCASTMASKA_NONE;
3166 mask[1] = NVREG_MCASTMASKB_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003167 }
3168 }
3169 addr[0] |= NVREG_MCASTADDRA_FORCE;
3170 pff |= NVREG_PFF_ALWAYS;
3171 spin_lock_irq(&np->lock);
3172 nv_stop_rx(dev);
3173 writel(addr[0], base + NvRegMulticastAddrA);
3174 writel(addr[1], base + NvRegMulticastAddrB);
3175 writel(mask[0], base + NvRegMulticastMaskA);
3176 writel(mask[1], base + NvRegMulticastMaskB);
3177 writel(pff, base + NvRegPacketFilterFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003178 nv_start_rx(dev);
3179 spin_unlock_irq(&np->lock);
3180}
3181
Adrian Bunkc7985052006-06-22 12:03:29 +02003182static void nv_update_pause(struct net_device *dev, u32 pause_flags)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003183{
3184 struct fe_priv *np = netdev_priv(dev);
3185 u8 __iomem *base = get_hwbase(dev);
3186
3187 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3188
3189 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3190 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3191 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3192 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3193 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3194 } else {
3195 writel(pff, base + NvRegPacketFilterFlags);
3196 }
3197 }
3198 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3199 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3200 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003201 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3202 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3203 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003204 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003205 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003206 /* limit the number of tx pause frames to a default of 8 */
3207 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3208 }
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003209 writel(pause_enable, base + NvRegTxPauseFrame);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003210 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3211 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3212 } else {
3213 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3214 writel(regmisc, base + NvRegMisc1);
3215 }
3216 }
3217}
3218
Sanjay Hortikare19df762011-11-11 16:11:21 +00003219static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3220{
3221 struct fe_priv *np = netdev_priv(dev);
3222 u8 __iomem *base = get_hwbase(dev);
3223 u32 phyreg, txreg;
3224 int mii_status;
3225
3226 np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3227 np->duplex = duplex;
3228
3229 /* see if gigabit phy */
3230 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3231 if (mii_status & PHY_GIGABIT) {
3232 np->gigabit = PHY_GIGABIT;
3233 phyreg = readl(base + NvRegSlotTime);
3234 phyreg &= ~(0x3FF00);
3235 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3236 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3237 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3238 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3239 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3240 phyreg |= NVREG_SLOTTIME_1000_FULL;
3241 writel(phyreg, base + NvRegSlotTime);
3242 }
3243
3244 phyreg = readl(base + NvRegPhyInterface);
3245 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3246 if (np->duplex == 0)
3247 phyreg |= PHY_HALF;
3248 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3249 phyreg |= PHY_100;
3250 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3251 NVREG_LINKSPEED_1000)
3252 phyreg |= PHY_1000;
3253 writel(phyreg, base + NvRegPhyInterface);
3254
3255 if (phyreg & PHY_RGMII) {
3256 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3257 NVREG_LINKSPEED_1000)
3258 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3259 else
3260 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3261 } else {
3262 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3263 }
3264 writel(txreg, base + NvRegTxDeferral);
3265
3266 if (np->desc_ver == DESC_VER_1) {
3267 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3268 } else {
3269 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3270 NVREG_LINKSPEED_1000)
3271 txreg = NVREG_TX_WM_DESC2_3_1000;
3272 else
3273 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3274 }
3275 writel(txreg, base + NvRegTxWatermark);
3276
3277 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3278 base + NvRegMisc1);
3279 pci_push(base);
3280 writel(np->linkspeed, base + NvRegLinkSpeed);
3281 pci_push(base);
3282
3283 return;
3284}
3285
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003286/**
Ben Hutchings49ce9c22012-07-10 10:56:00 +00003287 * nv_update_linkspeed - Setup the MAC according to the link partner
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003288 * @dev: Network device to be configured
3289 *
3290 * The function queries the PHY and checks if there is a link partner.
3291 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3292 * set to 10 MBit HD.
3293 *
3294 * The function returns 0 if there is no link partner and 1 if there is
3295 * a good link partner.
3296 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003297static int nv_update_linkspeed(struct net_device *dev)
3298{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003299 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003300 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003301 int adv = 0;
3302 int lpa = 0;
3303 int adv_lpa, adv_pause, lpa_pause;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003304 int newls = np->linkspeed;
3305 int newdup = np->duplex;
3306 int mii_status;
Sanjay Hortikare19df762011-11-11 16:11:21 +00003307 u32 bmcr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003308 int retval = 0;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003309 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003310 u32 txrxFlags = 0;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003311 u32 phy_exp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003312
Sanjay Hortikare19df762011-11-11 16:11:21 +00003313 /* If device loopback is enabled, set carrier on and enable max link
3314 * speed.
3315 */
3316 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3317 if (bmcr & BMCR_LOOPBACK) {
3318 if (netif_running(dev)) {
3319 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3320 if (!netif_carrier_ok(dev))
3321 netif_carrier_on(dev);
3322 }
3323 return 1;
3324 }
3325
Linus Torvalds1da177e2005-04-16 15:20:36 -07003326 /* BMSR_LSTATUS is latched, read it twice:
3327 * we want the current value.
3328 */
3329 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3330 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3331
3332 if (!(mii_status & BMSR_LSTATUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003333 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3334 newdup = 0;
3335 retval = 0;
3336 goto set_speed;
3337 }
3338
3339 if (np->autoneg == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003340 if (np->fixed_mode & LPA_100FULL) {
3341 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3342 newdup = 1;
3343 } else if (np->fixed_mode & LPA_100HALF) {
3344 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3345 newdup = 0;
3346 } else if (np->fixed_mode & LPA_10FULL) {
3347 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3348 newdup = 1;
3349 } else {
3350 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3351 newdup = 0;
3352 }
3353 retval = 1;
3354 goto set_speed;
3355 }
3356 /* check auto negotiation is complete */
3357 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3358 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3359 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3360 newdup = 0;
3361 retval = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003362 goto set_speed;
3363 }
3364
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003365 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3366 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003367
Linus Torvalds1da177e2005-04-16 15:20:36 -07003368 retval = 1;
3369 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003370 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3371 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003372
3373 if ((control_1000 & ADVERTISE_1000FULL) &&
3374 (status_1000 & LPA_1000FULL)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003375 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3376 newdup = 1;
3377 goto set_speed;
3378 }
3379 }
3380
Linus Torvalds1da177e2005-04-16 15:20:36 -07003381 /* FIXME: handle parallel detection properly */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003382 adv_lpa = lpa & adv;
3383 if (adv_lpa & LPA_100FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003384 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3385 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003386 } else if (adv_lpa & LPA_100HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003387 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3388 newdup = 0;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003389 } else if (adv_lpa & LPA_10FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003390 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3391 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003392 } else if (adv_lpa & LPA_10HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003393 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3394 newdup = 0;
3395 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003396 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3397 newdup = 0;
3398 }
3399
3400set_speed:
3401 if (np->duplex == newdup && np->linkspeed == newls)
3402 return retval;
3403
Linus Torvalds1da177e2005-04-16 15:20:36 -07003404 np->duplex = newdup;
3405 np->linkspeed = newls;
3406
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003407 /* The transmitter and receiver must be restarted for safe update */
3408 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3409 txrxFlags |= NV_RESTART_TX;
3410 nv_stop_tx(dev);
3411 }
3412 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3413 txrxFlags |= NV_RESTART_RX;
3414 nv_stop_rx(dev);
3415 }
3416
Linus Torvalds1da177e2005-04-16 15:20:36 -07003417 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003418 phyreg = readl(base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003419 phyreg &= ~(0x3FF00);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003420 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3421 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3422 phyreg |= NVREG_SLOTTIME_10_100_FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003423 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003424 phyreg |= NVREG_SLOTTIME_1000_FULL;
3425 writel(phyreg, base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003426 }
3427
3428 phyreg = readl(base + NvRegPhyInterface);
3429 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3430 if (np->duplex == 0)
3431 phyreg |= PHY_HALF;
3432 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3433 phyreg |= PHY_100;
3434 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3435 phyreg |= PHY_1000;
3436 writel(phyreg, base + NvRegPhyInterface);
3437
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003438 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003439 if (phyreg & PHY_RGMII) {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003440 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003441 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003442 } else {
3443 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3444 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3445 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3446 else
3447 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3448 } else {
3449 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3450 }
3451 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003452 } else {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003453 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3454 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3455 else
3456 txreg = NVREG_TX_DEFERRAL_DEFAULT;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003457 }
3458 writel(txreg, base + NvRegTxDeferral);
3459
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04003460 if (np->desc_ver == DESC_VER_1) {
3461 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3462 } else {
3463 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3464 txreg = NVREG_TX_WM_DESC2_3_1000;
3465 else
3466 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3467 }
3468 writel(txreg, base + NvRegTxWatermark);
3469
Szymon Janc78aea4f2010-11-27 08:39:43 +00003470 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
Linus Torvalds1da177e2005-04-16 15:20:36 -07003471 base + NvRegMisc1);
3472 pci_push(base);
3473 writel(np->linkspeed, base + NvRegLinkSpeed);
3474 pci_push(base);
3475
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003476 pause_flags = 0;
3477 /* setup pause frame */
david decotigny1ff39eb2012-08-24 17:22:52 +00003478 if (netif_running(dev) && (np->duplex != 0)) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003479 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003480 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3481 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003482
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003483 switch (adv_pause) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003484 case ADVERTISE_PAUSE_CAP:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003485 if (lpa_pause & LPA_PAUSE_CAP) {
3486 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3487 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3488 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3489 }
3490 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003491 case ADVERTISE_PAUSE_ASYM:
Szymon Janc78aea4f2010-11-27 08:39:43 +00003492 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003493 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003494 break;
Szymon Janc78aea4f2010-11-27 08:39:43 +00003495 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3496 if (lpa_pause & LPA_PAUSE_CAP) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003497 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3498 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3499 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3500 }
3501 if (lpa_pause == LPA_PAUSE_ASYM)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003502 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003503 break;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003504 }
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003505 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003506 pause_flags = np->pause_flags;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003507 }
3508 }
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003509 nv_update_pause(dev, pause_flags);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003510
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003511 if (txrxFlags & NV_RESTART_TX)
3512 nv_start_tx(dev);
3513 if (txrxFlags & NV_RESTART_RX)
3514 nv_start_rx(dev);
3515
Linus Torvalds1da177e2005-04-16 15:20:36 -07003516 return retval;
3517}
3518
3519static void nv_linkchange(struct net_device *dev)
3520{
3521 if (nv_update_linkspeed(dev)) {
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003522 if (!netif_carrier_ok(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003523 netif_carrier_on(dev);
Joe Perches1d397f32010-11-29 07:41:57 +00003524 netdev_info(dev, "link up\n");
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00003525 nv_txrx_gate(dev, false);
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003526 nv_start_rx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003527 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003528 } else {
3529 if (netif_carrier_ok(dev)) {
3530 netif_carrier_off(dev);
Joe Perches1d397f32010-11-29 07:41:57 +00003531 netdev_info(dev, "link down\n");
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00003532 nv_txrx_gate(dev, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003533 nv_stop_rx(dev);
3534 }
3535 }
3536}
3537
3538static void nv_link_irq(struct net_device *dev)
3539{
3540 u8 __iomem *base = get_hwbase(dev);
3541 u32 miistat;
3542
3543 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05003544 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003545
3546 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3547 nv_linkchange(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003548}
3549
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003550static void nv_msi_workaround(struct fe_priv *np)
3551{
3552
3553 /* Need to toggle the msi irq mask within the ethernet device,
3554 * otherwise, future interrupts will not be detected.
3555 */
3556 if (np->msi_flags & NV_MSI_ENABLED) {
3557 u8 __iomem *base = np->base;
3558
3559 writel(0, base + NvRegMSIIrqMask);
3560 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3561 }
3562}
3563
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003564static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3565{
3566 struct fe_priv *np = netdev_priv(dev);
3567
3568 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3569 if (total_work > NV_DYNAMIC_THRESHOLD) {
3570 /* transition to poll based interrupts */
3571 np->quiet_count = 0;
3572 if (np->irqmask != NVREG_IRQMASK_CPU) {
3573 np->irqmask = NVREG_IRQMASK_CPU;
3574 return 1;
3575 }
3576 } else {
3577 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3578 np->quiet_count++;
3579 } else {
3580 /* reached a period of low activity, switch
3581 to per tx/rx packet interrupts */
3582 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3583 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3584 return 1;
3585 }
3586 }
3587 }
3588 }
3589 return 0;
3590}
3591
David Howells7d12e782006-10-05 14:55:46 +01003592static irqreturn_t nv_nic_irq(int foo, void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003593{
3594 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003595 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003596 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003597
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003598 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3599 np->events = readl(base + NvRegIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003600 writel(np->events, base + NvRegIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003601 } else {
3602 np->events = readl(base + NvRegMSIXIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003603 writel(np->events, base + NvRegMSIXIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003604 }
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003605 if (!(np->events & np->irqmask))
3606 return IRQ_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003607
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003608 nv_msi_workaround(np);
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003609
Eric Dumazet78c29bd2009-07-02 04:04:45 +00003610 if (napi_schedule_prep(&np->napi)) {
3611 /*
3612 * Disable further irq's (msix not enabled with napi)
3613 */
3614 writel(0, base + NvRegIrqMask);
3615 __napi_schedule(&np->napi);
3616 }
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003617
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003618 return IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003619}
3620
Ben Hutchings1aa8b472012-07-10 10:56:59 +00003621/* All _optimized functions are used to help increase performance
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003622 * (reduce CPU and increase throughput). They use descripter version 3,
3623 * compiler directives, and reduce memory accesses.
3624 */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003625static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3626{
3627 struct net_device *dev = (struct net_device *) data;
3628 struct fe_priv *np = netdev_priv(dev);
3629 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003630
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003631 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3632 np->events = readl(base + NvRegIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003633 writel(np->events, base + NvRegIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003634 } else {
3635 np->events = readl(base + NvRegMSIXIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003636 writel(np->events, base + NvRegMSIXIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003637 }
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003638 if (!(np->events & np->irqmask))
3639 return IRQ_NONE;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003640
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003641 nv_msi_workaround(np);
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003642
Eric Dumazet78c29bd2009-07-02 04:04:45 +00003643 if (napi_schedule_prep(&np->napi)) {
3644 /*
3645 * Disable further irq's (msix not enabled with napi)
3646 */
3647 writel(0, base + NvRegIrqMask);
3648 __napi_schedule(&np->napi);
3649 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003650
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003651 return IRQ_HANDLED;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003652}
3653
David Howells7d12e782006-10-05 14:55:46 +01003654static irqreturn_t nv_nic_irq_tx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003655{
3656 struct net_device *dev = (struct net_device *) data;
3657 struct fe_priv *np = netdev_priv(dev);
3658 u8 __iomem *base = get_hwbase(dev);
3659 u32 events;
3660 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003661 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003662
Szymon Janc78aea4f2010-11-27 08:39:43 +00003663 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003664 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
Mike Ditto2a4e7a02011-11-05 14:38:21 +00003665 writel(events, base + NvRegMSIXIrqStatus);
3666 netdev_dbg(dev, "tx irq events: %08x\n", events);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003667 if (!(events & np->irqmask))
3668 break;
3669
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003670 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003671 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003672 spin_unlock_irqrestore(&np->lock, flags);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003673
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003674 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003675 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003676 /* disable interrupts on the nic */
3677 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3678 pci_push(base);
3679
3680 if (!np->in_shutdown) {
3681 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3682 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3683 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003684 spin_unlock_irqrestore(&np->lock, flags);
Joe Perchesc20ec762010-11-29 07:42:02 +00003685 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3686 __func__, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003687 break;
3688 }
3689
3690 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003691
3692 return IRQ_RETVAL(i);
3693}
3694
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003695static int nv_napi_poll(struct napi_struct *napi, int budget)
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003696{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003697 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3698 struct net_device *dev = np->dev;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003699 u8 __iomem *base = get_hwbase(dev);
Francois Romieud15e9c42006-12-17 23:03:15 +01003700 unsigned long flags;
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003701 int retcode;
Szymon Janc78aea4f2010-11-27 08:39:43 +00003702 int rx_count, tx_work = 0, rx_work = 0;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003703
stephen hemminger81a2e362010-04-28 08:25:28 +00003704 do {
3705 if (!nv_optimized(np)) {
3706 spin_lock_irqsave(&np->lock, flags);
3707 tx_work += nv_tx_done(dev, np->tx_ring_size);
3708 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003709
Tom Herbertd951f722010-05-05 18:15:21 +00003710 rx_count = nv_rx_process(dev, budget - rx_work);
stephen hemminger81a2e362010-04-28 08:25:28 +00003711 retcode = nv_alloc_rx(dev);
3712 } else {
3713 spin_lock_irqsave(&np->lock, flags);
3714 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3715 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003716
Tom Herbertd951f722010-05-05 18:15:21 +00003717 rx_count = nv_rx_process_optimized(dev,
3718 budget - rx_work);
stephen hemminger81a2e362010-04-28 08:25:28 +00003719 retcode = nv_alloc_rx_optimized(dev);
3720 }
3721 } while (retcode == 0 &&
3722 rx_count > 0 && (rx_work += rx_count) < budget);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003723
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003724 if (retcode) {
Francois Romieud15e9c42006-12-17 23:03:15 +01003725 spin_lock_irqsave(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003726 if (!np->in_shutdown)
3727 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Francois Romieud15e9c42006-12-17 23:03:15 +01003728 spin_unlock_irqrestore(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003729 }
3730
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003731 nv_change_interrupt_mode(dev, tx_work + rx_work);
3732
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003733 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3734 spin_lock_irqsave(&np->lock, flags);
3735 nv_link_irq(dev);
3736 spin_unlock_irqrestore(&np->lock, flags);
3737 }
3738 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3739 spin_lock_irqsave(&np->lock, flags);
3740 nv_linkchange(dev);
3741 spin_unlock_irqrestore(&np->lock, flags);
3742 np->link_timeout = jiffies + LINK_TIMEOUT;
3743 }
3744 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3745 spin_lock_irqsave(&np->lock, flags);
3746 if (!np->in_shutdown) {
3747 np->nic_poll_irq = np->irqmask;
3748 np->recover_error = 1;
3749 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3750 }
3751 spin_unlock_irqrestore(&np->lock, flags);
David S. Miller6c2da9c2009-04-09 01:09:33 -07003752 napi_complete(napi);
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003753 return rx_work;
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003754 }
3755
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003756 if (rx_work < budget) {
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003757 /* re-enable interrupts
3758 (msix not enabled in napi) */
David S. Miller6c2da9c2009-04-09 01:09:33 -07003759 napi_complete(napi);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003760
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003761 writel(np->irqmask, base + NvRegIrqMask);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003762 }
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003763 return rx_work;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003764}
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003765
David Howells7d12e782006-10-05 14:55:46 +01003766static irqreturn_t nv_nic_irq_rx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003767{
3768 struct net_device *dev = (struct net_device *) data;
3769 struct fe_priv *np = netdev_priv(dev);
3770 u8 __iomem *base = get_hwbase(dev);
3771 u32 events;
3772 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003773 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003774
Szymon Janc78aea4f2010-11-27 08:39:43 +00003775 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003776 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
Mike Ditto2a4e7a02011-11-05 14:38:21 +00003777 writel(events, base + NvRegMSIXIrqStatus);
3778 netdev_dbg(dev, "rx irq events: %08x\n", events);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003779 if (!(events & np->irqmask))
3780 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003781
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003782 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003783 if (unlikely(nv_alloc_rx_optimized(dev))) {
3784 spin_lock_irqsave(&np->lock, flags);
3785 if (!np->in_shutdown)
3786 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3787 spin_unlock_irqrestore(&np->lock, flags);
3788 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003789 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003790
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003791 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003792 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003793 /* disable interrupts on the nic */
3794 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3795 pci_push(base);
3796
3797 if (!np->in_shutdown) {
3798 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3799 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3800 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003801 spin_unlock_irqrestore(&np->lock, flags);
Joe Perchesc20ec762010-11-29 07:42:02 +00003802 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3803 __func__, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003804 break;
3805 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003806 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003807
3808 return IRQ_RETVAL(i);
3809}
3810
David Howells7d12e782006-10-05 14:55:46 +01003811static irqreturn_t nv_nic_irq_other(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003812{
3813 struct net_device *dev = (struct net_device *) data;
3814 struct fe_priv *np = netdev_priv(dev);
3815 u8 __iomem *base = get_hwbase(dev);
3816 u32 events;
3817 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003818 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003819
Szymon Janc78aea4f2010-11-27 08:39:43 +00003820 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003821 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
Mike Ditto2a4e7a02011-11-05 14:38:21 +00003822 writel(events, base + NvRegMSIXIrqStatus);
3823 netdev_dbg(dev, "irq events: %08x\n", events);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003824 if (!(events & np->irqmask))
3825 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003826
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003827 /* check tx in case we reached max loop limit in tx isr */
3828 spin_lock_irqsave(&np->lock, flags);
3829 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3830 spin_unlock_irqrestore(&np->lock, flags);
3831
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003832 if (events & NVREG_IRQ_LINK) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003833 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003834 nv_link_irq(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003835 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003836 }
3837 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003838 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003839 nv_linkchange(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003840 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003841 np->link_timeout = jiffies + LINK_TIMEOUT;
3842 }
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003843 if (events & NVREG_IRQ_RECOVER_ERROR) {
Denis Efremov186e8682012-07-21 01:54:34 +04003844 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003845 /* disable interrupts on the nic */
3846 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3847 pci_push(base);
3848
3849 if (!np->in_shutdown) {
3850 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3851 np->recover_error = 1;
3852 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3853 }
Denis Efremov186e8682012-07-21 01:54:34 +04003854 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003855 break;
3856 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003857 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003858 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003859 /* disable interrupts on the nic */
3860 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3861 pci_push(base);
3862
3863 if (!np->in_shutdown) {
3864 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3865 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3866 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003867 spin_unlock_irqrestore(&np->lock, flags);
Joe Perchesc20ec762010-11-29 07:42:02 +00003868 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3869 __func__, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003870 break;
3871 }
3872
3873 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003874
3875 return IRQ_RETVAL(i);
3876}
3877
David Howells7d12e782006-10-05 14:55:46 +01003878static irqreturn_t nv_nic_irq_test(int foo, void *data)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003879{
3880 struct net_device *dev = (struct net_device *) data;
3881 struct fe_priv *np = netdev_priv(dev);
3882 u8 __iomem *base = get_hwbase(dev);
3883 u32 events;
3884
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003885 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3886 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
Mike Ditto2a4e7a02011-11-05 14:38:21 +00003887 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003888 } else {
3889 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
Mike Ditto2a4e7a02011-11-05 14:38:21 +00003890 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003891 }
3892 pci_push(base);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003893 if (!(events & NVREG_IRQ_TIMER))
3894 return IRQ_RETVAL(0);
3895
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003896 nv_msi_workaround(np);
3897
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003898 spin_lock(&np->lock);
3899 np->intr_test = 1;
3900 spin_unlock(&np->lock);
3901
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003902 return IRQ_RETVAL(1);
3903}
3904
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003905static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3906{
3907 u8 __iomem *base = get_hwbase(dev);
3908 int i;
3909 u32 msixmap = 0;
3910
3911 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3912 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3913 * the remaining 8 interrupts.
3914 */
3915 for (i = 0; i < 8; i++) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003916 if ((irqmask >> i) & 0x1)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003917 msixmap |= vector << (i << 2);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003918 }
3919 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3920
3921 msixmap = 0;
3922 for (i = 0; i < 8; i++) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003923 if ((irqmask >> (i + 8)) & 0x1)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003924 msixmap |= vector << (i << 2);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003925 }
3926 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3927}
3928
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003929static int nv_request_irq(struct net_device *dev, int intr_test)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003930{
3931 struct fe_priv *np = get_nvpriv(dev);
3932 u8 __iomem *base = get_hwbase(dev);
Alexander Gordeevd9bd00a2014-02-18 11:11:53 +01003933 int ret;
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003934 int i;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003935 irqreturn_t (*handler)(int foo, void *data);
3936
3937 if (intr_test) {
3938 handler = nv_nic_irq_test;
3939 } else {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003940 if (nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003941 handler = nv_nic_irq_optimized;
3942 else
3943 handler = nv_nic_irq;
3944 }
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003945
3946 if (np->msi_flags & NV_MSI_X_CAPABLE) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003947 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003948 np->msi_x_entry[i].entry = i;
Alexander Gordeev04698ef2014-02-18 11:11:54 +01003949 ret = pci_enable_msix_range(np->pci_dev,
3950 np->msi_x_entry,
3951 np->msi_flags & NV_MSI_X_VECTORS_MASK,
3952 np->msi_flags & NV_MSI_X_VECTORS_MASK);
3953 if (ret > 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003954 np->msi_flags |= NV_MSI_X_ENABLED;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003955 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003956 /* Request irq for rx handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003957 sprintf(np->name_rx, "%s-rx", dev->name);
Alexander Gordeev61c94712014-02-18 11:11:52 +01003958 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3959 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev);
3960 if (ret) {
Joe Perches1d397f32010-11-29 07:41:57 +00003961 netdev_info(dev,
3962 "request_irq failed for rx %d\n",
3963 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003964 pci_disable_msix(np->pci_dev);
3965 np->msi_flags &= ~NV_MSI_X_ENABLED;
3966 goto out_err;
3967 }
3968 /* Request irq for tx handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003969 sprintf(np->name_tx, "%s-tx", dev->name);
Alexander Gordeev61c94712014-02-18 11:11:52 +01003970 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3971 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev);
3972 if (ret) {
Joe Perches1d397f32010-11-29 07:41:57 +00003973 netdev_info(dev,
3974 "request_irq failed for tx %d\n",
3975 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003976 pci_disable_msix(np->pci_dev);
3977 np->msi_flags &= ~NV_MSI_X_ENABLED;
3978 goto out_free_rx;
3979 }
3980 /* Request irq for link and timer handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003981 sprintf(np->name_other, "%s-other", dev->name);
Alexander Gordeev61c94712014-02-18 11:11:52 +01003982 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3983 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev);
3984 if (ret) {
Joe Perches1d397f32010-11-29 07:41:57 +00003985 netdev_info(dev,
3986 "request_irq failed for link %d\n",
3987 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003988 pci_disable_msix(np->pci_dev);
3989 np->msi_flags &= ~NV_MSI_X_ENABLED;
3990 goto out_free_tx;
3991 }
3992 /* map interrupts to their respective vector */
3993 writel(0, base + NvRegMSIXMap0);
3994 writel(0, base + NvRegMSIXMap1);
3995 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3996 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3997 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3998 } else {
3999 /* Request irq for all interrupts */
Alexander Gordeev61c94712014-02-18 11:11:52 +01004000 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector,
4001 handler, IRQF_SHARED, dev->name, dev);
4002 if (ret) {
Joe Perches1d397f32010-11-29 07:41:57 +00004003 netdev_info(dev,
4004 "request_irq failed %d\n",
4005 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004006 pci_disable_msix(np->pci_dev);
4007 np->msi_flags &= ~NV_MSI_X_ENABLED;
4008 goto out_err;
4009 }
4010
4011 /* map interrupts to vector 0 */
4012 writel(0, base + NvRegMSIXMap0);
4013 writel(0, base + NvRegMSIXMap1);
4014 }
Mike Ditto89328782011-11-16 12:15:11 +00004015 netdev_info(dev, "MSI-X enabled\n");
Alexander Gordeevd9bd00a2014-02-18 11:11:53 +01004016 return 0;
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004017 }
4018 }
Alexander Gordeevd9bd00a2014-02-18 11:11:53 +01004019 if (np->msi_flags & NV_MSI_CAPABLE) {
Szymon Janc34cf97e2010-11-27 08:39:46 +00004020 ret = pci_enable_msi(np->pci_dev);
4021 if (ret == 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004022 np->msi_flags |= NV_MSI_ENABLED;
Alexander Gordeev61c94712014-02-18 11:11:52 +01004023 ret = request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev);
4024 if (ret) {
Joe Perches1d397f32010-11-29 07:41:57 +00004025 netdev_info(dev, "request_irq failed %d\n",
4026 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004027 pci_disable_msi(np->pci_dev);
4028 np->msi_flags &= ~NV_MSI_ENABLED;
4029 goto out_err;
4030 }
4031
4032 /* map interrupts to vector 0 */
4033 writel(0, base + NvRegMSIMap0);
4034 writel(0, base + NvRegMSIMap1);
4035 /* enable msi vector 0 */
4036 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
Mike Ditto89328782011-11-16 12:15:11 +00004037 netdev_info(dev, "MSI enabled\n");
Alexander Gordeevd9bd00a2014-02-18 11:11:53 +01004038 return 0;
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004039 }
4040 }
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004041
Alexander Gordeevd9bd00a2014-02-18 11:11:53 +01004042 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4043 goto out_err;
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004044
4045 return 0;
4046out_free_tx:
4047 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4048out_free_rx:
4049 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4050out_err:
4051 return 1;
4052}
4053
4054static void nv_free_irq(struct net_device *dev)
4055{
4056 struct fe_priv *np = get_nvpriv(dev);
4057 int i;
4058
4059 if (np->msi_flags & NV_MSI_X_ENABLED) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004060 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004061 free_irq(np->msi_x_entry[i].vector, dev);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004062 pci_disable_msix(np->pci_dev);
4063 np->msi_flags &= ~NV_MSI_X_ENABLED;
4064 } else {
4065 free_irq(np->pci_dev->irq, dev);
4066 if (np->msi_flags & NV_MSI_ENABLED) {
4067 pci_disable_msi(np->pci_dev);
4068 np->msi_flags &= ~NV_MSI_ENABLED;
4069 }
4070 }
4071}
4072
Linus Torvalds1da177e2005-04-16 15:20:36 -07004073static void nv_do_nic_poll(unsigned long data)
4074{
4075 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004076 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004077 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004078 u32 mask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004079
Linus Torvalds1da177e2005-04-16 15:20:36 -07004080 /*
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004081 * First disable irq(s) and then
Linus Torvalds1da177e2005-04-16 15:20:36 -07004082 * reenable interrupts on the nic, we have to do this before calling
4083 * nv_nic_irq because that may decide to do otherwise
4084 */
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004085
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004086 if (!using_multi_irqs(dev)) {
4087 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004088 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004089 else
Manfred Spraula7475902007-10-17 21:52:33 +02004090 disable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004091 mask = np->irqmask;
4092 } else {
4093 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004094 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004095 mask |= NVREG_IRQ_RX_ALL;
4096 }
4097 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004098 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004099 mask |= NVREG_IRQ_TX_ALL;
4100 }
4101 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004102 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004103 mask |= NVREG_IRQ_OTHER;
4104 }
4105 }
Manfred Spraula7475902007-10-17 21:52:33 +02004106 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4107
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004108 if (np->recover_error) {
4109 np->recover_error = 0;
Joe Perches1d397f32010-11-29 07:41:57 +00004110 netdev_info(dev, "MAC in recoverable error state\n");
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004111 if (netif_running(dev)) {
4112 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004113 netif_addr_lock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004114 spin_lock(&np->lock);
4115 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004116 nv_stop_rxtx(dev);
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08004117 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4118 nv_mac_reset(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004119 nv_txrx_reset(dev);
4120 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004121 nv_drain_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004122 /* reinit driver view of the rx queue */
4123 set_bufsize(dev);
4124 if (nv_init_ring(dev)) {
4125 if (!np->in_shutdown)
4126 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4127 }
4128 /* reinit nic view of the rx queue */
4129 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4130 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004131 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004132 base + NvRegRingSizes);
4133 pci_push(base);
4134 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4135 pci_push(base);
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08004136 /* clear interrupts */
4137 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4138 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4139 else
4140 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004141
4142 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004143 nv_start_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004144 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004145 netif_addr_unlock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004146 netif_tx_unlock_bh(dev);
4147 }
4148 }
4149
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004150 writel(mask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004151 pci_push(base);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004152
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004153 if (!using_multi_irqs(dev)) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08004154 np->nic_poll_irq = 0;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004155 if (nv_optimized(np))
Ayaz Abdullafcc5f262007-03-23 05:49:37 -05004156 nv_nic_irq_optimized(0, dev);
4157 else
4158 nv_nic_irq(0, dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004159 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004160 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004161 else
Manfred Spraula7475902007-10-17 21:52:33 +02004162 enable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004163 } else {
4164 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08004165 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
David Howells7d12e782006-10-05 14:55:46 +01004166 nv_nic_irq_rx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004167 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004168 }
4169 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08004170 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
David Howells7d12e782006-10-05 14:55:46 +01004171 nv_nic_irq_tx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004172 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004173 }
4174 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08004175 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
David Howells7d12e782006-10-05 14:55:46 +01004176 nv_nic_irq_other(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004177 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004178 }
4179 }
Yinghai Lu79d30a52009-02-06 01:30:01 -08004180
Linus Torvalds1da177e2005-04-16 15:20:36 -07004181}
4182
Michal Schmidt2918c352005-05-12 19:42:06 -04004183#ifdef CONFIG_NET_POLL_CONTROLLER
4184static void nv_poll_controller(struct net_device *dev)
4185{
4186 nv_do_nic_poll((unsigned long) dev);
4187}
4188#endif
4189
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004190static void nv_do_stats_poll(unsigned long data)
david decotignyf5d827a2011-11-16 12:15:13 +00004191 __acquires(&netdev_priv(dev)->hwstats_lock)
4192 __releases(&netdev_priv(dev)->hwstats_lock)
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004193{
4194 struct net_device *dev = (struct net_device *) data;
4195 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004196
david decotignyf5d827a2011-11-16 12:15:13 +00004197 /* If lock is currently taken, the stats are being refreshed
4198 * and hence fresh enough */
4199 if (spin_trylock(&np->hwstats_lock)) {
4200 nv_update_stats(dev);
4201 spin_unlock(&np->hwstats_lock);
4202 }
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004203
4204 if (!np->in_shutdown)
Daniel Drakebfebbb82008-03-18 11:07:18 +00004205 mod_timer(&np->stats_poll,
4206 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004207}
4208
Linus Torvalds1da177e2005-04-16 15:20:36 -07004209static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4210{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004211 struct fe_priv *np = netdev_priv(dev);
Rick Jones68aad782011-11-07 13:29:27 +00004212 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
4213 strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4214 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004215}
4216
4217static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4218{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004219 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004220 wolinfo->supported = WAKE_MAGIC;
4221
4222 spin_lock_irq(&np->lock);
4223 if (np->wolenabled)
4224 wolinfo->wolopts = WAKE_MAGIC;
4225 spin_unlock_irq(&np->lock);
4226}
4227
4228static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4229{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004230 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004231 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004232 u32 flags = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004233
Linus Torvalds1da177e2005-04-16 15:20:36 -07004234 if (wolinfo->wolopts == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004235 np->wolenabled = 0;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004236 } else if (wolinfo->wolopts & WAKE_MAGIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004237 np->wolenabled = 1;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004238 flags = NVREG_WAKEUPFLAGS_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004239 }
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004240 if (netif_running(dev)) {
4241 spin_lock_irq(&np->lock);
4242 writel(flags, base + NvRegWakeUpFlags);
4243 spin_unlock_irq(&np->lock);
4244 }
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00004245 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004246 return 0;
4247}
4248
4249static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4250{
4251 struct fe_priv *np = netdev_priv(dev);
David Decotigny70739492011-04-27 18:32:40 +00004252 u32 speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004253 int adv;
4254
4255 spin_lock_irq(&np->lock);
4256 ecmd->port = PORT_MII;
4257 if (!netif_running(dev)) {
4258 /* We do not track link speed / duplex setting if the
4259 * interface is disabled. Force a link check */
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004260 if (nv_update_linkspeed(dev)) {
4261 if (!netif_carrier_ok(dev))
4262 netif_carrier_on(dev);
4263 } else {
4264 if (netif_carrier_ok(dev))
4265 netif_carrier_off(dev);
4266 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004267 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004268
4269 if (netif_carrier_ok(dev)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004270 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004271 case NVREG_LINKSPEED_10:
David Decotigny70739492011-04-27 18:32:40 +00004272 speed = SPEED_10;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004273 break;
4274 case NVREG_LINKSPEED_100:
David Decotigny70739492011-04-27 18:32:40 +00004275 speed = SPEED_100;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004276 break;
4277 case NVREG_LINKSPEED_1000:
David Decotigny70739492011-04-27 18:32:40 +00004278 speed = SPEED_1000;
4279 break;
4280 default:
4281 speed = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004282 break;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004283 }
4284 ecmd->duplex = DUPLEX_HALF;
4285 if (np->duplex)
4286 ecmd->duplex = DUPLEX_FULL;
4287 } else {
Jiri Pirko537fae02014-06-06 14:17:00 +02004288 speed = SPEED_UNKNOWN;
4289 ecmd->duplex = DUPLEX_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004290 }
David Decotigny70739492011-04-27 18:32:40 +00004291 ethtool_cmd_speed_set(ecmd, speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004292 ecmd->autoneg = np->autoneg;
4293
4294 ecmd->advertising = ADVERTISED_MII;
4295 if (np->autoneg) {
4296 ecmd->advertising |= ADVERTISED_Autoneg;
4297 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004298 if (adv & ADVERTISE_10HALF)
4299 ecmd->advertising |= ADVERTISED_10baseT_Half;
4300 if (adv & ADVERTISE_10FULL)
4301 ecmd->advertising |= ADVERTISED_10baseT_Full;
4302 if (adv & ADVERTISE_100HALF)
4303 ecmd->advertising |= ADVERTISED_100baseT_Half;
4304 if (adv & ADVERTISE_100FULL)
4305 ecmd->advertising |= ADVERTISED_100baseT_Full;
4306 if (np->gigabit == PHY_GIGABIT) {
4307 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4308 if (adv & ADVERTISE_1000FULL)
4309 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4310 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004311 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004312 ecmd->supported = (SUPPORTED_Autoneg |
4313 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4314 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4315 SUPPORTED_MII);
4316 if (np->gigabit == PHY_GIGABIT)
4317 ecmd->supported |= SUPPORTED_1000baseT_Full;
4318
4319 ecmd->phy_address = np->phyaddr;
4320 ecmd->transceiver = XCVR_EXTERNAL;
4321
4322 /* ignore maxtxpkt, maxrxpkt for now */
4323 spin_unlock_irq(&np->lock);
4324 return 0;
4325}
4326
4327static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4328{
4329 struct fe_priv *np = netdev_priv(dev);
David Decotigny25db0332011-04-27 18:32:39 +00004330 u32 speed = ethtool_cmd_speed(ecmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004331
4332 if (ecmd->port != PORT_MII)
4333 return -EINVAL;
4334 if (ecmd->transceiver != XCVR_EXTERNAL)
4335 return -EINVAL;
4336 if (ecmd->phy_address != np->phyaddr) {
4337 /* TODO: support switching between multiple phys. Should be
4338 * trivial, but not enabled due to lack of test hardware. */
4339 return -EINVAL;
4340 }
4341 if (ecmd->autoneg == AUTONEG_ENABLE) {
4342 u32 mask;
4343
4344 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4345 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4346 if (np->gigabit == PHY_GIGABIT)
4347 mask |= ADVERTISED_1000baseT_Full;
4348
4349 if ((ecmd->advertising & mask) == 0)
4350 return -EINVAL;
4351
4352 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4353 /* Note: autonegotiation disable, speed 1000 intentionally
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004354 * forbidden - no one should need that. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07004355
David Decotigny25db0332011-04-27 18:32:39 +00004356 if (speed != SPEED_10 && speed != SPEED_100)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004357 return -EINVAL;
4358 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4359 return -EINVAL;
4360 } else {
4361 return -EINVAL;
4362 }
4363
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004364 netif_carrier_off(dev);
4365 if (netif_running(dev)) {
Tobias Diedrich97bff092008-07-03 23:54:56 -07004366 unsigned long flags;
4367
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004368 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004369 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004370 netif_addr_lock(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004371 /* with plain spinlock lockdep complains */
4372 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004373 /* stop engines */
Tobias Diedrich97bff092008-07-03 23:54:56 -07004374 /* FIXME:
4375 * this can take some time, and interrupts are disabled
4376 * due to spin_lock_irqsave, but let's hope no daemon
4377 * is going to change the settings very often...
4378 * Worst case:
4379 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4380 * + some minor delays, which is up to a second approximately
4381 */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004382 nv_stop_rxtx(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004383 spin_unlock_irqrestore(&np->lock, flags);
David S. Millere308a5d2008-07-15 00:13:44 -07004384 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004385 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004386 }
4387
Linus Torvalds1da177e2005-04-16 15:20:36 -07004388 if (ecmd->autoneg == AUTONEG_ENABLE) {
4389 int adv, bmcr;
4390
4391 np->autoneg = 1;
4392
4393 /* advertise only what has been requested */
4394 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004395 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004396 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4397 adv |= ADVERTISE_10HALF;
4398 if (ecmd->advertising & ADVERTISED_10baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004399 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004400 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4401 adv |= ADVERTISE_100HALF;
4402 if (ecmd->advertising & ADVERTISED_100baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004403 adv |= ADVERTISE_100FULL;
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004404 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004405 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4406 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4407 adv |= ADVERTISE_PAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004408 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4409
4410 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004411 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004412 adv &= ~ADVERTISE_1000FULL;
4413 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4414 adv |= ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004415 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004416 }
4417
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004418 if (netif_running(dev))
Joe Perches1d397f32010-11-29 07:41:57 +00004419 netdev_info(dev, "link down\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07004420 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004421 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4422 bmcr |= BMCR_ANENABLE;
4423 /* reset the phy in order for settings to stick,
4424 * and cause autoneg to start */
4425 if (phy_reset(dev, bmcr)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004426 netdev_info(dev, "phy reset failed\n");
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004427 return -EINVAL;
4428 }
4429 } else {
4430 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4431 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4432 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004433 } else {
4434 int adv, bmcr;
4435
4436 np->autoneg = 0;
4437
4438 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004439 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
David Decotigny25db0332011-04-27 18:32:39 +00004440 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004441 adv |= ADVERTISE_10HALF;
David Decotigny25db0332011-04-27 18:32:39 +00004442 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004443 adv |= ADVERTISE_10FULL;
David Decotigny25db0332011-04-27 18:32:39 +00004444 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004445 adv |= ADVERTISE_100HALF;
David Decotigny25db0332011-04-27 18:32:39 +00004446 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004447 adv |= ADVERTISE_100FULL;
4448 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004449 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004450 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4451 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4452 }
4453 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4454 adv |= ADVERTISE_PAUSE_ASYM;
4455 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4456 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004457 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4458 np->fixed_mode = adv;
4459
4460 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004461 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004462 adv &= ~ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004463 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004464 }
4465
4466 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004467 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4468 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004469 bmcr |= BMCR_FULLDPLX;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004470 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004471 bmcr |= BMCR_SPEED100;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004472 if (np->phy_oui == PHY_OUI_MARVELL) {
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004473 /* reset the phy in order for forced mode settings to stick */
4474 if (phy_reset(dev, bmcr)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004475 netdev_info(dev, "phy reset failed\n");
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004476 return -EINVAL;
4477 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004478 } else {
4479 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4480 if (netif_running(dev)) {
4481 /* Wait a bit and then reconfigure the nic. */
4482 udelay(10);
4483 nv_linkchange(dev);
4484 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004485 }
4486 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004487
4488 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004489 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004490 nv_enable_irq(dev);
4491 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004492
4493 return 0;
4494}
4495
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004496#define FORCEDETH_REGS_VER 1
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004497
4498static int nv_get_regs_len(struct net_device *dev)
4499{
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004500 struct fe_priv *np = netdev_priv(dev);
4501 return np->register_size;
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004502}
4503
4504static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4505{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004506 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004507 u8 __iomem *base = get_hwbase(dev);
4508 u32 *rbuf = buf;
4509 int i;
4510
4511 regs->version = FORCEDETH_REGS_VER;
4512 spin_lock_irq(&np->lock);
david decotignyba9aa132012-08-24 17:22:51 +00004513 for (i = 0; i < np->register_size/sizeof(u32); i++)
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004514 rbuf[i] = readl(base + i*sizeof(u32));
4515 spin_unlock_irq(&np->lock);
4516}
4517
4518static int nv_nway_reset(struct net_device *dev)
4519{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004520 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004521 int ret;
4522
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004523 if (np->autoneg) {
4524 int bmcr;
4525
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004526 netif_carrier_off(dev);
4527 if (netif_running(dev)) {
4528 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004529 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004530 netif_addr_lock(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004531 spin_lock(&np->lock);
4532 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004533 nv_stop_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004534 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004535 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004536 netif_tx_unlock_bh(dev);
Joe Perches1d397f32010-11-29 07:41:57 +00004537 netdev_info(dev, "link down\n");
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004538 }
4539
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004540 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004541 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4542 bmcr |= BMCR_ANENABLE;
4543 /* reset the phy in order for settings to stick*/
4544 if (phy_reset(dev, bmcr)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004545 netdev_info(dev, "phy reset failed\n");
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004546 return -EINVAL;
4547 }
4548 } else {
4549 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4550 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4551 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004552
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004553 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004554 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004555 nv_enable_irq(dev);
4556 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004557 ret = 0;
4558 } else {
4559 ret = -EINVAL;
4560 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004561
4562 return ret;
4563}
4564
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004565static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4566{
4567 struct fe_priv *np = netdev_priv(dev);
4568
4569 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004570 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4571
4572 ring->rx_pending = np->rx_ring_size;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004573 ring->tx_pending = np->tx_ring_size;
4574}
4575
4576static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4577{
4578 struct fe_priv *np = netdev_priv(dev);
4579 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004580 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004581 dma_addr_t ring_addr;
4582
4583 if (ring->rx_pending < RX_RING_MIN ||
4584 ring->tx_pending < TX_RING_MIN ||
4585 ring->rx_mini_pending != 0 ||
4586 ring->rx_jumbo_pending != 0 ||
4587 (np->desc_ver == DESC_VER_1 &&
4588 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4589 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4590 (np->desc_ver != DESC_VER_1 &&
4591 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4592 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4593 return -EINVAL;
4594 }
4595
4596 /* allocate new rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004597 if (!nv_optimized(np)) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004598 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4599 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4600 &ring_addr);
4601 } else {
4602 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4603 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4604 &ring_addr);
4605 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004606 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4607 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4608 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004609 /* fall back to old rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004610 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004611 if (rxtx_ring)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004612 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4613 rxtx_ring, ring_addr);
4614 } else {
4615 if (rxtx_ring)
4616 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4617 rxtx_ring, ring_addr);
4618 }
Szymon Janc9b03b062010-11-27 08:39:44 +00004619
4620 kfree(rx_skbuff);
4621 kfree(tx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004622 goto exit;
4623 }
4624
4625 if (netif_running(dev)) {
4626 nv_disable_irq(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004627 nv_napi_disable(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004628 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004629 netif_addr_lock(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004630 spin_lock(&np->lock);
4631 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004632 nv_stop_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004633 nv_txrx_reset(dev);
4634 /* drain queues */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004635 nv_drain_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004636 /* delete queues */
4637 free_rings(dev);
4638 }
4639
4640 /* set new values */
4641 np->rx_ring_size = ring->rx_pending;
4642 np->tx_ring_size = ring->tx_pending;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004643
4644 if (!nv_optimized(np)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004645 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004646 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4647 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004648 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004649 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4650 }
Szymon Janc78aea4f2010-11-27 08:39:43 +00004651 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4652 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004653 np->ring_addr = ring_addr;
4654
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004655 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4656 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004657
4658 if (netif_running(dev)) {
4659 /* reinit driver view of the queues */
4660 set_bufsize(dev);
4661 if (nv_init_ring(dev)) {
4662 if (!np->in_shutdown)
4663 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4664 }
4665
4666 /* reinit nic view of the queues */
4667 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4668 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004669 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004670 base + NvRegRingSizes);
4671 pci_push(base);
4672 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4673 pci_push(base);
4674
4675 /* restart engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004676 nv_start_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004677 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004678 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004679 netif_tx_unlock_bh(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004680 nv_napi_enable(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004681 nv_enable_irq(dev);
4682 }
4683 return 0;
4684exit:
4685 return -ENOMEM;
4686}
4687
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004688static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4689{
4690 struct fe_priv *np = netdev_priv(dev);
4691
4692 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4693 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4694 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4695}
4696
4697static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4698{
4699 struct fe_priv *np = netdev_priv(dev);
4700 int adv, bmcr;
4701
4702 if ((!np->autoneg && np->duplex == 0) ||
4703 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004704 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004705 return -EINVAL;
4706 }
4707 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004708 netdev_info(dev, "hardware does not support tx pause frames\n");
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004709 return -EINVAL;
4710 }
4711
4712 netif_carrier_off(dev);
4713 if (netif_running(dev)) {
4714 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004715 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004716 netif_addr_lock(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004717 spin_lock(&np->lock);
4718 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004719 nv_stop_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004720 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004721 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004722 netif_tx_unlock_bh(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004723 }
4724
4725 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4726 if (pause->rx_pause)
4727 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4728 if (pause->tx_pause)
4729 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4730
4731 if (np->autoneg && pause->autoneg) {
4732 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4733
4734 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4735 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004736 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004737 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4738 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4739 adv |= ADVERTISE_PAUSE_ASYM;
4740 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4741
4742 if (netif_running(dev))
Joe Perches1d397f32010-11-29 07:41:57 +00004743 netdev_info(dev, "link down\n");
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004744 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4745 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4746 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4747 } else {
4748 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4749 if (pause->rx_pause)
4750 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4751 if (pause->tx_pause)
4752 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4753
4754 if (!netif_running(dev))
4755 nv_update_linkspeed(dev);
4756 else
4757 nv_update_pause(dev, np->pause_flags);
4758 }
4759
4760 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004761 nv_start_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004762 nv_enable_irq(dev);
4763 }
4764 return 0;
4765}
4766
Michał Mirosławc8f44af2011-11-15 15:29:55 +00004767static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
Sanjay Hortikare19df762011-11-11 16:11:21 +00004768{
4769 struct fe_priv *np = netdev_priv(dev);
4770 unsigned long flags;
4771 u32 miicontrol;
4772 int err, retval = 0;
4773
4774 spin_lock_irqsave(&np->lock, flags);
4775 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4776 if (features & NETIF_F_LOOPBACK) {
4777 if (miicontrol & BMCR_LOOPBACK) {
4778 spin_unlock_irqrestore(&np->lock, flags);
4779 netdev_info(dev, "Loopback already enabled\n");
4780 return 0;
4781 }
4782 nv_disable_irq(dev);
4783 /* Turn on loopback mode */
4784 miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4785 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4786 if (err) {
4787 retval = PHY_ERROR;
4788 spin_unlock_irqrestore(&np->lock, flags);
4789 phy_init(dev);
4790 } else {
4791 if (netif_running(dev)) {
4792 /* Force 1000 Mbps full-duplex */
4793 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4794 1);
4795 /* Force link up */
4796 netif_carrier_on(dev);
4797 }
4798 spin_unlock_irqrestore(&np->lock, flags);
4799 netdev_info(dev,
4800 "Internal PHY loopback mode enabled.\n");
4801 }
4802 } else {
4803 if (!(miicontrol & BMCR_LOOPBACK)) {
4804 spin_unlock_irqrestore(&np->lock, flags);
4805 netdev_info(dev, "Loopback already disabled\n");
4806 return 0;
4807 }
4808 nv_disable_irq(dev);
4809 /* Turn off loopback */
4810 spin_unlock_irqrestore(&np->lock, flags);
4811 netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4812 phy_init(dev);
4813 }
4814 msleep(500);
4815 spin_lock_irqsave(&np->lock, flags);
4816 nv_enable_irq(dev);
4817 spin_unlock_irqrestore(&np->lock, flags);
4818
4819 return retval;
4820}
4821
Michał Mirosławc8f44af2011-11-15 15:29:55 +00004822static netdev_features_t nv_fix_features(struct net_device *dev,
4823 netdev_features_t features)
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004824{
Michał Mirosław569e1462011-04-15 04:50:49 +00004825 /* vlan is dependent on rx checksum offload */
Patrick McHardyf6469682013-04-19 02:04:27 +00004826 if (features & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
Michał Mirosław569e1462011-04-15 04:50:49 +00004827 features |= NETIF_F_RXCSUM;
4828
4829 return features;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004830}
4831
Michał Mirosławc8f44af2011-11-15 15:29:55 +00004832static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
Jiri Pirko3326c782011-07-20 04:54:38 +00004833{
4834 struct fe_priv *np = get_nvpriv(dev);
4835
4836 spin_lock_irq(&np->lock);
4837
Patrick McHardyf6469682013-04-19 02:04:27 +00004838 if (features & NETIF_F_HW_VLAN_CTAG_RX)
Jiri Pirko3326c782011-07-20 04:54:38 +00004839 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4840 else
4841 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4842
Patrick McHardyf6469682013-04-19 02:04:27 +00004843 if (features & NETIF_F_HW_VLAN_CTAG_TX)
Jiri Pirko3326c782011-07-20 04:54:38 +00004844 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4845 else
4846 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4847
4848 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4849
4850 spin_unlock_irq(&np->lock);
4851}
4852
Michał Mirosławc8f44af2011-11-15 15:29:55 +00004853static int nv_set_features(struct net_device *dev, netdev_features_t features)
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004854{
4855 struct fe_priv *np = netdev_priv(dev);
4856 u8 __iomem *base = get_hwbase(dev);
Michał Mirosławc8f44af2011-11-15 15:29:55 +00004857 netdev_features_t changed = dev->features ^ features;
Sanjay Hortikare19df762011-11-11 16:11:21 +00004858 int retval;
4859
4860 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4861 retval = nv_set_loopback(dev, features);
4862 if (retval != 0)
4863 return retval;
4864 }
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004865
Michał Mirosław569e1462011-04-15 04:50:49 +00004866 if (changed & NETIF_F_RXCSUM) {
4867 spin_lock_irq(&np->lock);
4868
4869 if (features & NETIF_F_RXCSUM)
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004870 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Michał Mirosław569e1462011-04-15 04:50:49 +00004871 else
4872 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4873
4874 if (netif_running(dev))
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004875 writel(np->txrxctl_bits, base + NvRegTxRxControl);
Michał Mirosław569e1462011-04-15 04:50:49 +00004876
4877 spin_unlock_irq(&np->lock);
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004878 }
4879
Patrick McHardyf6469682013-04-19 02:04:27 +00004880 if (changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX))
Jiri Pirko3326c782011-07-20 04:54:38 +00004881 nv_vlan_mode(dev, features);
4882
Michał Mirosław569e1462011-04-15 04:50:49 +00004883 return 0;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004884}
4885
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004886static int nv_get_sset_count(struct net_device *dev, int sset)
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004887{
4888 struct fe_priv *np = netdev_priv(dev);
4889
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004890 switch (sset) {
4891 case ETH_SS_TEST:
4892 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4893 return NV_TEST_COUNT_EXTENDED;
4894 else
4895 return NV_TEST_COUNT_BASE;
4896 case ETH_SS_STATS:
Ayaz Abdulla8ed14542009-03-05 08:01:49 +00004897 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4898 return NV_DEV_STATISTICS_V3_COUNT;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004899 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4900 return NV_DEV_STATISTICS_V2_COUNT;
Ayaz Abdulla8ed14542009-03-05 08:01:49 +00004901 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4902 return NV_DEV_STATISTICS_V1_COUNT;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004903 else
4904 return 0;
4905 default:
4906 return -EOPNOTSUPP;
4907 }
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004908}
4909
david decotignyf5d827a2011-11-16 12:15:13 +00004910static void nv_get_ethtool_stats(struct net_device *dev,
4911 struct ethtool_stats *estats, u64 *buffer)
4912 __acquires(&netdev_priv(dev)->hwstats_lock)
4913 __releases(&netdev_priv(dev)->hwstats_lock)
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004914{
4915 struct fe_priv *np = netdev_priv(dev);
4916
david decotignyf5d827a2011-11-16 12:15:13 +00004917 spin_lock_bh(&np->hwstats_lock);
4918 nv_update_stats(dev);
4919 memcpy(buffer, &np->estats,
4920 nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4921 spin_unlock_bh(&np->hwstats_lock);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004922}
4923
4924static int nv_link_test(struct net_device *dev)
4925{
4926 struct fe_priv *np = netdev_priv(dev);
4927 int mii_status;
4928
4929 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4930 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4931
4932 /* check phy link status */
4933 if (!(mii_status & BMSR_LSTATUS))
4934 return 0;
4935 else
4936 return 1;
4937}
4938
4939static int nv_register_test(struct net_device *dev)
4940{
4941 u8 __iomem *base = get_hwbase(dev);
4942 int i = 0;
4943 u32 orig_read, new_read;
4944
4945 do {
4946 orig_read = readl(base + nv_registers_test[i].reg);
4947
4948 /* xor with mask to toggle bits */
4949 orig_read ^= nv_registers_test[i].mask;
4950
4951 writel(orig_read, base + nv_registers_test[i].reg);
4952
4953 new_read = readl(base + nv_registers_test[i].reg);
4954
4955 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4956 return 0;
4957
4958 /* restore original value */
4959 orig_read ^= nv_registers_test[i].mask;
4960 writel(orig_read, base + nv_registers_test[i].reg);
4961
4962 } while (nv_registers_test[++i].reg != 0);
4963
4964 return 1;
4965}
4966
4967static int nv_interrupt_test(struct net_device *dev)
4968{
4969 struct fe_priv *np = netdev_priv(dev);
4970 u8 __iomem *base = get_hwbase(dev);
4971 int ret = 1;
4972 int testcnt;
4973 u32 save_msi_flags, save_poll_interval = 0;
4974
4975 if (netif_running(dev)) {
4976 /* free current irq */
4977 nv_free_irq(dev);
4978 save_poll_interval = readl(base+NvRegPollingInterval);
4979 }
4980
4981 /* flag to test interrupt handler */
4982 np->intr_test = 0;
4983
4984 /* setup test irq */
4985 save_msi_flags = np->msi_flags;
4986 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4987 np->msi_flags |= 0x001; /* setup 1 vector */
4988 if (nv_request_irq(dev, 1))
4989 return 0;
4990
4991 /* setup timer interrupt */
4992 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4993 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4994
4995 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4996
4997 /* wait for at least one interrupt */
4998 msleep(100);
4999
5000 spin_lock_irq(&np->lock);
5001
5002 /* flag should be set within ISR */
5003 testcnt = np->intr_test;
5004 if (!testcnt)
5005 ret = 2;
5006
5007 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
5008 if (!(np->msi_flags & NV_MSI_X_ENABLED))
5009 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5010 else
5011 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5012
5013 spin_unlock_irq(&np->lock);
5014
5015 nv_free_irq(dev);
5016
5017 np->msi_flags = save_msi_flags;
5018
5019 if (netif_running(dev)) {
5020 writel(save_poll_interval, base + NvRegPollingInterval);
5021 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5022 /* restore original irq */
5023 if (nv_request_irq(dev, 0))
5024 return 0;
5025 }
5026
5027 return ret;
5028}
5029
5030static int nv_loopback_test(struct net_device *dev)
5031{
5032 struct fe_priv *np = netdev_priv(dev);
5033 u8 __iomem *base = get_hwbase(dev);
5034 struct sk_buff *tx_skb, *rx_skb;
5035 dma_addr_t test_dma_addr;
5036 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005037 u32 flags;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005038 int len, i, pkt_len;
5039 u8 *pkt_data;
5040 u32 filter_flags = 0;
5041 u32 misc1_flags = 0;
5042 int ret = 1;
5043
5044 if (netif_running(dev)) {
5045 nv_disable_irq(dev);
5046 filter_flags = readl(base + NvRegPacketFilterFlags);
5047 misc1_flags = readl(base + NvRegMisc1);
5048 } else {
5049 nv_txrx_reset(dev);
5050 }
5051
5052 /* reinit driver view of the rx queue */
5053 set_bufsize(dev);
5054 nv_init_ring(dev);
5055
5056 /* setup hardware for loopback */
5057 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5058 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5059
5060 /* reinit nic view of the rx queue */
5061 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5062 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005063 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005064 base + NvRegRingSizes);
5065 pci_push(base);
5066
5067 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005068 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005069
5070 /* setup packet for tx */
5071 pkt_len = ETH_DATA_LEN;
Pradeep A. Dalvidae2e9f2012-02-06 11:16:13 +00005072 tx_skb = netdev_alloc_skb(dev, pkt_len);
Jesper Juhl46798c82006-09-25 16:39:24 -07005073 if (!tx_skb) {
Jesper Juhl46798c82006-09-25 16:39:24 -07005074 ret = 0;
5075 goto out;
5076 }
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03005077 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5078 skb_tailroom(tx_skb),
5079 PCI_DMA_FROMDEVICE);
Larry Finger612a7c42012-12-27 17:25:41 +00005080 if (pci_dma_mapping_error(np->pci_dev,
5081 test_dma_addr)) {
5082 dev_kfree_skb_any(tx_skb);
5083 goto out;
5084 }
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005085 pkt_data = skb_put(tx_skb, pkt_len);
5086 for (i = 0; i < pkt_len; i++)
5087 pkt_data[i] = (u8)(i & 0xff);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005088
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005089 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005090 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5091 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005092 } else {
Al Viro5bb7ea22007-12-09 16:06:41 +00005093 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5094 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005095 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005096 }
5097 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5098 pci_push(get_hwbase(dev));
5099
5100 msleep(500);
5101
5102 /* check for rx of the packet */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005103 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005104 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005105 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5106
5107 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005108 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005109 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5110 }
5111
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005112 if (flags & NV_RX_AVAIL) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005113 ret = 0;
5114 } else if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005115 if (flags & NV_RX_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005116 ret = 0;
5117 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00005118 if (flags & NV_RX2_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005119 ret = 0;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005120 }
5121
5122 if (ret) {
5123 if (len != pkt_len) {
5124 ret = 0;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005125 } else {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05005126 rx_skb = np->rx_skb[0].skb;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005127 for (i = 0; i < pkt_len; i++) {
5128 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5129 ret = 0;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005130 break;
5131 }
5132 }
5133 }
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005134 }
5135
Eric Dumazet73a37072009-06-17 21:17:59 +00005136 pci_unmap_single(np->pci_dev, test_dma_addr,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07005137 (skb_end_pointer(tx_skb) - tx_skb->data),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005138 PCI_DMA_TODEVICE);
5139 dev_kfree_skb_any(tx_skb);
Jesper Juhl46798c82006-09-25 16:39:24 -07005140 out:
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005141 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005142 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005143 nv_txrx_reset(dev);
5144 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005145 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005146
5147 if (netif_running(dev)) {
5148 writel(misc1_flags, base + NvRegMisc1);
5149 writel(filter_flags, base + NvRegPacketFilterFlags);
5150 nv_enable_irq(dev);
5151 }
5152
5153 return ret;
5154}
5155
5156static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5157{
5158 struct fe_priv *np = netdev_priv(dev);
5159 u8 __iomem *base = get_hwbase(dev);
Ivan Vecera86d9be22013-12-04 18:06:51 +01005160 int result, count;
5161
5162 count = nv_get_sset_count(dev, ETH_SS_TEST);
5163 memset(buffer, 0, count * sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005164
5165 if (!nv_link_test(dev)) {
5166 test->flags |= ETH_TEST_FL_FAILED;
5167 buffer[0] = 1;
5168 }
5169
5170 if (test->flags & ETH_TEST_FL_OFFLINE) {
5171 if (netif_running(dev)) {
5172 netif_stop_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005173 nv_napi_disable(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10005174 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07005175 netif_addr_lock(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005176 spin_lock_irq(&np->lock);
5177 nv_disable_hw_interrupts(dev, np->irqmask);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005178 if (!(np->msi_flags & NV_MSI_X_ENABLED))
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005179 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005180 else
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005181 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005182 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005183 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005184 nv_txrx_reset(dev);
5185 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005186 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005187 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07005188 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10005189 netif_tx_unlock_bh(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005190 }
5191
5192 if (!nv_register_test(dev)) {
5193 test->flags |= ETH_TEST_FL_FAILED;
5194 buffer[1] = 1;
5195 }
5196
5197 result = nv_interrupt_test(dev);
5198 if (result != 1) {
5199 test->flags |= ETH_TEST_FL_FAILED;
5200 buffer[2] = 1;
5201 }
5202 if (result == 0) {
5203 /* bail out */
5204 return;
5205 }
5206
Ivan Vecera86d9be22013-12-04 18:06:51 +01005207 if (count > NV_TEST_COUNT_BASE && !nv_loopback_test(dev)) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005208 test->flags |= ETH_TEST_FL_FAILED;
5209 buffer[3] = 1;
5210 }
5211
5212 if (netif_running(dev)) {
5213 /* reinit driver view of the rx queue */
5214 set_bufsize(dev);
5215 if (nv_init_ring(dev)) {
5216 if (!np->in_shutdown)
5217 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5218 }
5219 /* reinit nic view of the rx queue */
5220 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5221 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005222 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005223 base + NvRegRingSizes);
5224 pci_push(base);
5225 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5226 pci_push(base);
5227 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005228 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005229 netif_start_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005230 nv_napi_enable(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005231 nv_enable_hw_interrupts(dev, np->irqmask);
5232 }
5233 }
5234}
5235
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005236static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5237{
5238 switch (stringset) {
5239 case ETH_SS_STATS:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005240 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005241 break;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005242 case ETH_SS_TEST:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005243 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005244 break;
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005245 }
5246}
5247
Jeff Garzik7282d492006-09-13 14:30:00 -04005248static const struct ethtool_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005249 .get_drvinfo = nv_get_drvinfo,
5250 .get_link = ethtool_op_get_link,
5251 .get_wol = nv_get_wol,
5252 .set_wol = nv_set_wol,
5253 .get_settings = nv_get_settings,
5254 .set_settings = nv_set_settings,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005255 .get_regs_len = nv_get_regs_len,
5256 .get_regs = nv_get_regs,
5257 .nway_reset = nv_nway_reset,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005258 .get_ringparam = nv_get_ringparam,
5259 .set_ringparam = nv_set_ringparam,
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005260 .get_pauseparam = nv_get_pauseparam,
5261 .set_pauseparam = nv_set_pauseparam,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005262 .get_strings = nv_get_strings,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005263 .get_ethtool_stats = nv_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005264 .get_sset_count = nv_get_sset_count,
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005265 .self_test = nv_self_test,
Richard Cochran74913022012-07-22 07:15:42 +00005266 .get_ts_info = ethtool_op_get_ts_info,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005267};
5268
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005269/* The mgmt unit and driver use a semaphore to access the phy during init */
5270static int nv_mgmt_acquire_sema(struct net_device *dev)
5271{
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005272 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005273 u8 __iomem *base = get_hwbase(dev);
5274 int i;
5275 u32 tx_ctrl, mgmt_sema;
5276
5277 for (i = 0; i < 10; i++) {
5278 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5279 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5280 break;
5281 msleep(500);
5282 }
5283
5284 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5285 return 0;
5286
5287 for (i = 0; i < 2; i++) {
5288 tx_ctrl = readl(base + NvRegTransmitterControl);
5289 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5290 writel(tx_ctrl, base + NvRegTransmitterControl);
5291
5292 /* verify that semaphore was acquired */
5293 tx_ctrl = readl(base + NvRegTransmitterControl);
5294 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005295 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5296 np->mgmt_sema = 1;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005297 return 1;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005298 } else
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005299 udelay(50);
5300 }
5301
5302 return 0;
5303}
5304
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005305static void nv_mgmt_release_sema(struct net_device *dev)
5306{
5307 struct fe_priv *np = netdev_priv(dev);
5308 u8 __iomem *base = get_hwbase(dev);
5309 u32 tx_ctrl;
5310
5311 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5312 if (np->mgmt_sema) {
5313 tx_ctrl = readl(base + NvRegTransmitterControl);
5314 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5315 writel(tx_ctrl, base + NvRegTransmitterControl);
5316 }
5317 }
5318}
5319
5320
5321static int nv_mgmt_get_version(struct net_device *dev)
5322{
5323 struct fe_priv *np = netdev_priv(dev);
5324 u8 __iomem *base = get_hwbase(dev);
5325 u32 data_ready = readl(base + NvRegTransmitterControl);
5326 u32 data_ready2 = 0;
5327 unsigned long start;
5328 int ready = 0;
5329
5330 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5331 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5332 start = jiffies;
5333 while (time_before(jiffies, start + 5*HZ)) {
5334 data_ready2 = readl(base + NvRegTransmitterControl);
5335 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5336 ready = 1;
5337 break;
5338 }
5339 schedule_timeout_uninterruptible(1);
5340 }
5341
5342 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5343 return 0;
5344
5345 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5346
5347 return 1;
5348}
5349
Linus Torvalds1da177e2005-04-16 15:20:36 -07005350static int nv_open(struct net_device *dev)
5351{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005352 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005353 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005354 int ret = 1;
5355 int oom, i;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005356 u32 low;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005357
Ed Swierkcb52deb2008-12-01 12:24:43 +00005358 /* power up phy */
5359 mii_rw(dev, np->phyaddr, MII_BMCR,
5360 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5361
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005362 nv_txrx_gate(dev, false);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005363 /* erase previous misconfiguration */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005364 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5365 nv_mac_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005366 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5367 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005368 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5369 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005370 writel(0, base + NvRegPacketFilterFlags);
5371
5372 writel(0, base + NvRegTransmitterControl);
5373 writel(0, base + NvRegReceiverControl);
5374
5375 writel(0, base + NvRegAdapterControl);
5376
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005377 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5378 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5379
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005380 /* initialize descriptor rings */
Manfred Sprauld81c0982005-07-31 18:20:30 +02005381 set_bufsize(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005382 oom = nv_init_ring(dev);
5383
5384 writel(0, base + NvRegLinkSpeed);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005385 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005386 nv_txrx_reset(dev);
5387 writel(0, base + NvRegUnknownSetupReg6);
5388
5389 np->in_shutdown = 0;
5390
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005391 /* give hw rings */
Ayaz Abdulla0832b252006-02-04 13:13:26 -05005392 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005393 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Linus Torvalds1da177e2005-04-16 15:20:36 -07005394 base + NvRegRingSizes);
5395
Linus Torvalds1da177e2005-04-16 15:20:36 -07005396 writel(np->linkspeed, base + NvRegLinkSpeed);
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04005397 if (np->desc_ver == DESC_VER_1)
5398 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5399 else
5400 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005401 writel(np->txrxctl_bits, base + NvRegTxRxControl);
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005402 writel(np->vlanctl_bits, base + NvRegVlanControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005403 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005404 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00005405 if (reg_delay(dev, NvRegUnknownSetupReg5,
5406 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5407 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
Joe Perches1d397f32010-11-29 07:41:57 +00005408 netdev_info(dev,
5409 "%s: SetupReg5, Bit 31 remained off\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005410
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005411 writel(0, base + NvRegMIIMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005412 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005413 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005414
Linus Torvalds1da177e2005-04-16 15:20:36 -07005415 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5416 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5417 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
Manfred Sprauld81c0982005-07-31 18:20:30 +02005418 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005419
5420 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005421
5422 get_random_bytes(&low, sizeof(low));
5423 low &= NVREG_SLOTTIME_MASK;
5424 if (np->desc_ver == DESC_VER_1) {
5425 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5426 } else {
5427 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5428 /* setup legacy backoff */
5429 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5430 } else {
5431 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5432 nv_gear_backoff_reseed(dev);
5433 }
5434 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04005435 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5436 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005437 if (poll_interval == -1) {
5438 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5439 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5440 else
5441 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005442 } else
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005443 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005444 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5445 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5446 base + NvRegAdapterControl);
5447 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005448 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04005449 if (np->wolenabled)
5450 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005451
5452 i = readl(base + NvRegPowerState);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005453 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005454 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5455
5456 pci_push(base);
5457 udelay(10);
5458 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5459
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005460 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005461 pci_push(base);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005462 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005463 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5464 pci_push(base);
5465
Szymon Janc78aea4f2010-11-27 08:39:43 +00005466 if (nv_request_irq(dev, 0))
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005467 goto out_drain;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005468
5469 /* ask for interrupts */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005470 nv_enable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005471
5472 spin_lock_irq(&np->lock);
5473 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5474 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005475 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5476 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005477 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5478 /* One manual link speed update: Interrupts are enabled, future link
5479 * speed changes cause interrupts and are handled by nv_link_irq().
5480 */
5481 {
5482 u32 miistat;
5483 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005484 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005485 }
Manfred Spraul1b1b3c92005-08-06 23:47:55 +02005486 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5487 * to init hw */
5488 np->linkspeed = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005489 ret = nv_update_linkspeed(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005490 nv_start_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005491 netif_start_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005492 nv_napi_enable(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005493
Linus Torvalds1da177e2005-04-16 15:20:36 -07005494 if (ret) {
5495 netif_carrier_on(dev);
5496 } else {
Joe Perches1d397f32010-11-29 07:41:57 +00005497 netdev_info(dev, "no link during initialization\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005498 netif_carrier_off(dev);
5499 }
5500 if (oom)
5501 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005502
5503 /* start statistics timer */
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005504 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Daniel Drakebfebbb82008-03-18 11:07:18 +00005505 mod_timer(&np->stats_poll,
5506 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005507
Linus Torvalds1da177e2005-04-16 15:20:36 -07005508 spin_unlock_irq(&np->lock);
5509
Sanjay Hortikare19df762011-11-11 16:11:21 +00005510 /* If the loopback feature was set while the device was down, make sure
5511 * that it's set correctly now.
5512 */
5513 if (dev->features & NETIF_F_LOOPBACK)
5514 nv_set_loopback(dev, dev->features);
5515
Linus Torvalds1da177e2005-04-16 15:20:36 -07005516 return 0;
5517out_drain:
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005518 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005519 return ret;
5520}
5521
5522static int nv_close(struct net_device *dev)
5523{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005524 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005525 u8 __iomem *base;
5526
5527 spin_lock_irq(&np->lock);
5528 np->in_shutdown = 1;
5529 spin_unlock_irq(&np->lock);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005530 nv_napi_disable(dev);
Manfred Spraula7475902007-10-17 21:52:33 +02005531 synchronize_irq(np->pci_dev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005532
5533 del_timer_sync(&np->oom_kick);
5534 del_timer_sync(&np->nic_poll);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005535 del_timer_sync(&np->stats_poll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005536
5537 netif_stop_queue(dev);
5538 spin_lock_irq(&np->lock);
david decotigny1ff39eb2012-08-24 17:22:52 +00005539 nv_update_pause(dev, 0); /* otherwise stop_tx bricks NIC */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005540 nv_stop_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005541 nv_txrx_reset(dev);
5542
5543 /* disable interrupts on the nic or we will lock up */
5544 base = get_hwbase(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005545 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005546 pci_push(base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005547
5548 spin_unlock_irq(&np->lock);
5549
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005550 nv_free_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005551
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005552 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005553
Ed Swierk5a9a8e32009-06-02 00:19:52 -07005554 if (np->wolenabled || !phy_power_down) {
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005555 nv_txrx_gate(dev, false);
Tim Mann2cc49a52007-06-14 13:16:38 -07005556 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005557 nv_start_rx(dev);
Ed Swierkcb52deb2008-12-01 12:24:43 +00005558 } else {
5559 /* power down phy */
5560 mii_rw(dev, np->phyaddr, MII_BMCR,
5561 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005562 nv_txrx_gate(dev, true);
Tim Mann2cc49a52007-06-14 13:16:38 -07005563 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005564
5565 /* FIXME: power down nic */
5566
5567 return 0;
5568}
5569
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005570static const struct net_device_ops nv_netdev_ops = {
5571 .ndo_open = nv_open,
5572 .ndo_stop = nv_close,
david decotignyf5d827a2011-11-16 12:15:13 +00005573 .ndo_get_stats64 = nv_get_stats64,
Stephen Hemminger00829822008-11-20 20:14:53 -08005574 .ndo_start_xmit = nv_start_xmit,
5575 .ndo_tx_timeout = nv_tx_timeout,
5576 .ndo_change_mtu = nv_change_mtu,
Michał Mirosław569e1462011-04-15 04:50:49 +00005577 .ndo_fix_features = nv_fix_features,
5578 .ndo_set_features = nv_set_features,
Stephen Hemminger00829822008-11-20 20:14:53 -08005579 .ndo_validate_addr = eth_validate_addr,
5580 .ndo_set_mac_address = nv_set_mac_address,
Jiri Pirkoafc4b132011-08-16 06:29:01 +00005581 .ndo_set_rx_mode = nv_set_multicast,
Stephen Hemminger00829822008-11-20 20:14:53 -08005582#ifdef CONFIG_NET_POLL_CONTROLLER
5583 .ndo_poll_controller = nv_poll_controller,
5584#endif
5585};
5586
5587static const struct net_device_ops nv_netdev_ops_optimized = {
5588 .ndo_open = nv_open,
5589 .ndo_stop = nv_close,
david decotignyf5d827a2011-11-16 12:15:13 +00005590 .ndo_get_stats64 = nv_get_stats64,
Stephen Hemminger00829822008-11-20 20:14:53 -08005591 .ndo_start_xmit = nv_start_xmit_optimized,
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005592 .ndo_tx_timeout = nv_tx_timeout,
5593 .ndo_change_mtu = nv_change_mtu,
Michał Mirosław569e1462011-04-15 04:50:49 +00005594 .ndo_fix_features = nv_fix_features,
5595 .ndo_set_features = nv_set_features,
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005596 .ndo_validate_addr = eth_validate_addr,
5597 .ndo_set_mac_address = nv_set_mac_address,
Jiri Pirkoafc4b132011-08-16 06:29:01 +00005598 .ndo_set_rx_mode = nv_set_multicast,
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005599#ifdef CONFIG_NET_POLL_CONTROLLER
5600 .ndo_poll_controller = nv_poll_controller,
5601#endif
5602};
5603
Bill Pembertond05919a2012-12-03 09:23:20 -05005604static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005605{
5606 struct net_device *dev;
5607 struct fe_priv *np;
5608 unsigned long addr;
5609 u8 __iomem *base;
5610 int err, i;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005611 u32 powerstate, txreg;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005612 u32 phystate_orig = 0, phystate;
5613 int phyinitialized = 0;
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005614 static int printed_version;
5615
5616 if (!printed_version++)
Joe Perches294a5542010-11-29 07:41:56 +00005617 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5618 FORCEDETH_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005619
5620 dev = alloc_etherdev(sizeof(struct fe_priv));
5621 err = -ENOMEM;
5622 if (!dev)
5623 goto out;
5624
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005625 np = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005626 np->dev = dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005627 np->pci_dev = pci_dev;
5628 spin_lock_init(&np->lock);
david decotignyf5d827a2011-11-16 12:15:13 +00005629 spin_lock_init(&np->hwstats_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005630 SET_NETDEV_DEV(dev, &pci_dev->dev);
John Stultz827da442013-10-07 15:51:58 -07005631 u64_stats_init(&np->swstats_rx_syncp);
5632 u64_stats_init(&np->swstats_tx_syncp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005633
5634 init_timer(&np->oom_kick);
5635 np->oom_kick.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005636 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005637 init_timer(&np->nic_poll);
5638 np->nic_poll.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005639 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
david decotigny8f5f6982011-11-16 12:15:15 +00005640 init_timer_deferrable(&np->stats_poll);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005641 np->stats_poll.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005642 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005643
5644 err = pci_enable_device(pci_dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005645 if (err)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005646 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005647
5648 pci_set_master(pci_dev);
5649
5650 err = pci_request_regions(pci_dev, DRV_NAME);
5651 if (err < 0)
5652 goto out_disable;
5653
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005654 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005655 np->register_size = NV_PCI_REGSZ_VER3;
5656 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005657 np->register_size = NV_PCI_REGSZ_VER2;
5658 else
5659 np->register_size = NV_PCI_REGSZ_VER1;
5660
Linus Torvalds1da177e2005-04-16 15:20:36 -07005661 err = -EINVAL;
5662 addr = 0;
5663 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005664 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005665 pci_resource_len(pci_dev, i) >= np->register_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005666 addr = pci_resource_start(pci_dev, i);
5667 break;
5668 }
5669 }
5670 if (i == DEVICE_COUNT_RESOURCE) {
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005671 dev_info(&pci_dev->dev, "Couldn't find register window\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005672 goto out_relreg;
5673 }
5674
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005675 /* copy of driver data */
5676 np->driver_data = id->driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005677 /* copy of device id */
5678 np->device_id = id->device;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005679
Linus Torvalds1da177e2005-04-16 15:20:36 -07005680 /* handle different descriptor versions */
Manfred Spraulee733622005-07-31 18:32:26 +02005681 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5682 /* packet format 3: supports 40-bit addressing */
5683 np->desc_ver = DESC_VER_3;
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005684 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005685 if (dma_64bit) {
Yang Hongyang6afd1422009-04-06 19:01:15 -07005686 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005687 dev_info(&pci_dev->dev,
5688 "64-bit DMA failed, using 32-bit addressing\n");
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005689 else
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005690 dev->features |= NETIF_F_HIGHDMA;
Yang Hongyang6afd1422009-04-06 19:01:15 -07005691 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005692 dev_info(&pci_dev->dev,
5693 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005694 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005695 }
Manfred Spraulee733622005-07-31 18:32:26 +02005696 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5697 /* packet format 2: supports jumbo frames */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005698 np->desc_ver = DESC_VER_2;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005699 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
Manfred Spraulee733622005-07-31 18:32:26 +02005700 } else {
5701 /* original packet format */
5702 np->desc_ver = DESC_VER_1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005703 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
Manfred Sprauld81c0982005-07-31 18:20:30 +02005704 }
Manfred Spraulee733622005-07-31 18:32:26 +02005705
5706 np->pkt_limit = NV_PKTLIMIT_1;
5707 if (id->driver_data & DEV_HAS_LARGEDESC)
5708 np->pkt_limit = NV_PKTLIMIT_2;
5709
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005710 if (id->driver_data & DEV_HAS_CHECKSUM) {
5711 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Michał Mirosław569e1462011-04-15 04:50:49 +00005712 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5713 NETIF_F_TSO | NETIF_F_RXCSUM;
Ayaz Abdulla21828162007-01-23 12:27:21 -05005714 }
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005715
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005716 np->vlanctl_bits = 0;
5717 if (id->driver_data & DEV_HAS_VLAN) {
5718 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
Patrick McHardyf6469682013-04-19 02:04:27 +00005719 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX |
5720 NETIF_F_HW_VLAN_CTAG_TX;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005721 }
5722
Jiri Pirko0891b0e2011-07-26 10:19:28 +00005723 dev->features |= dev->hw_features;
5724
Sanjay Hortikare19df762011-11-11 16:11:21 +00005725 /* Add loopback capability to the device. */
5726 dev->hw_features |= NETIF_F_LOOPBACK;
5727
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005728 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005729 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5730 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5731 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005732 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005733 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005734
Linus Torvalds1da177e2005-04-16 15:20:36 -07005735 err = -ENOMEM;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005736 np->base = ioremap(addr, np->register_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005737 if (!np->base)
5738 goto out_relreg;
Manfred Spraulee733622005-07-31 18:32:26 +02005739
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005740 np->rx_ring_size = RX_RING_DEFAULT;
5741 np->tx_ring_size = TX_RING_DEFAULT;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005742
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005743 if (!nv_optimized(np)) {
Manfred Spraulee733622005-07-31 18:32:26 +02005744 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005745 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005746 &np->ring_addr);
5747 if (!np->rx_ring.orig)
5748 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005749 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005750 } else {
5751 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005752 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005753 &np->ring_addr);
5754 if (!np->rx_ring.ex)
5755 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005756 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005757 }
Yoann Padioleaudd00cc42007-07-19 01:49:03 -07005758 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5759 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05005760 if (!np->rx_skb || !np->tx_skb)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005761 goto out_freering;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005762
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005763 if (!nv_optimized(np))
Stephen Hemminger00829822008-11-20 20:14:53 -08005764 dev->netdev_ops = &nv_netdev_ops;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05005765 else
Stephen Hemminger00829822008-11-20 20:14:53 -08005766 dev->netdev_ops = &nv_netdev_ops_optimized;
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005767
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005768 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00005769 dev->ethtool_ops = &ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005770 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5771
5772 pci_set_drvdata(pci_dev, dev);
5773
5774 /* read the mac address */
5775 base = get_hwbase(dev);
5776 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5777 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5778
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005779 /* check the workaround bit for correct mac address order */
5780 txreg = readl(base + NvRegTransmitPoll);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005781 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005782 /* mac address is already in correct order */
5783 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5784 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5785 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5786 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5787 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5788 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005789 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5790 /* mac address is already in correct order */
5791 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5792 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5793 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5794 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5795 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5796 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5797 /*
5798 * Set orig mac address back to the reversed version.
5799 * This flag will be cleared during low power transition.
5800 * Therefore, we should always put back the reversed address.
5801 */
5802 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5803 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5804 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005805 } else {
5806 /* need to reverse mac address to correct order */
5807 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5808 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5809 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5810 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5811 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5812 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005813 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Joe Perchesc20ec762010-11-29 07:42:02 +00005814 dev_dbg(&pci_dev->dev,
5815 "%s: set workaround bit for reversed mac addr\n",
5816 __func__);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005817 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005818
Jiri Pirkoaaeb6cd2013-01-08 01:38:26 +00005819 if (!is_valid_ether_addr(dev->dev_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005820 /*
5821 * Bad mac address. At least one bios sets the mac address
5822 * to 01:23:45:67:89:ab
5823 */
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005824 dev_err(&pci_dev->dev,
Joe Perchesc20ec762010-11-29 07:42:02 +00005825 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
Szymon Janc78aea4f2010-11-27 08:39:43 +00005826 dev->dev_addr);
Danny Kukawka7ce5d222012-02-15 06:45:40 +00005827 eth_hw_addr_random(dev);
Joe Perchesc20ec762010-11-29 07:42:02 +00005828 dev_err(&pci_dev->dev,
5829 "Using random MAC address: %pM\n", dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005830 }
5831
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005832 /* set mac address */
5833 nv_copy_mac_to_hw(dev);
5834
Linus Torvalds1da177e2005-04-16 15:20:36 -07005835 /* disable WOL */
5836 writel(0, base + NvRegWakeUpFlags);
5837 np->wolenabled = 0;
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00005838 device_set_wakeup_enable(&pci_dev->dev, false);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005839
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005840 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005841
5842 /* take phy and nic out of low power mode */
5843 powerstate = readl(base + NvRegPowerState2);
5844 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005845 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
Auke Kok44c10132007-06-08 15:46:36 -07005846 pci_dev->revision >= 0xA3)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005847 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5848 writel(powerstate, base + NvRegPowerState2);
5849 }
5850
Szymon Janc78aea4f2010-11-27 08:39:43 +00005851 if (np->desc_ver == DESC_VER_1)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005852 np->tx_flags = NV_TX_VALID;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005853 else
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005854 np->tx_flags = NV_TX2_VALID;
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005855
5856 np->msi_flags = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005857 if ((id->driver_data & DEV_HAS_MSI) && msi)
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005858 np->msi_flags |= NV_MSI_CAPABLE;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005859
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005860 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5861 /* msix has had reported issues when modifying irqmask
5862 as in the case of napi, therefore, disable for now
5863 */
David S. Miller0a127612010-05-03 23:33:05 -07005864#if 0
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005865 np->msi_flags |= NV_MSI_X_CAPABLE;
5866#endif
5867 }
5868
5869 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005870 np->irqmask = NVREG_IRQMASK_CPU;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005871 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5872 np->msi_flags |= 0x0001;
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005873 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5874 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5875 /* start off in throughput mode */
5876 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5877 /* remove support for msix mode */
5878 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5879 } else {
5880 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5881 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5882 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5883 np->msi_flags |= 0x0003;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005884 }
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005885
Linus Torvalds1da177e2005-04-16 15:20:36 -07005886 if (id->driver_data & DEV_NEED_TIMERIRQ)
5887 np->irqmask |= NVREG_IRQ_TIMER;
5888 if (id->driver_data & DEV_NEED_LINKTIMER) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005889 np->need_linktimer = 1;
5890 np->link_timeout = jiffies + LINK_TIMEOUT;
5891 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005892 np->need_linktimer = 0;
5893 }
5894
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005895 /* Limit the number of tx's outstanding for hw bug */
5896 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5897 np->tx_limit = 1;
Ayaz Abdulla5c659322010-04-13 18:49:51 -07005898 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005899 pci_dev->revision >= 0xA2)
5900 np->tx_limit = 0;
5901 }
5902
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005903 /* clear phy state and temporarily halt phy interrupts */
5904 writel(0, base + NvRegMIIMask);
5905 phystate = readl(base + NvRegAdapterControl);
5906 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5907 phystate_orig = 1;
5908 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5909 writel(phystate, base + NvRegAdapterControl);
5910 }
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005911 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005912
5913 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005914 /* management unit running on the mac? */
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005915 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5916 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5917 nv_mgmt_acquire_sema(dev) &&
5918 nv_mgmt_get_version(dev)) {
5919 np->mac_in_use = 1;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005920 if (np->mgmt_version > 0)
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005921 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005922 /* management unit setup the phy already? */
5923 if (np->mac_in_use &&
5924 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5925 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5926 /* phy is inited by mgmt unit */
5927 phyinitialized = 1;
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005928 } else {
5929 /* we need to init the phy */
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005930 }
5931 }
5932 }
5933
Linus Torvalds1da177e2005-04-16 15:20:36 -07005934 /* find a suitable phy */
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005935 for (i = 1; i <= 32; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005936 int id1, id2;
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005937 int phyaddr = i & 0x1F;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005938
5939 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005940 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005941 spin_unlock_irq(&np->lock);
5942 if (id1 < 0 || id1 == 0xffff)
5943 continue;
5944 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005945 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005946 spin_unlock_irq(&np->lock);
5947 if (id2 < 0 || id2 == 0xffff)
5948 continue;
5949
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04005950 np->phy_model = id2 & PHYID2_MODEL_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005951 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5952 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005953 np->phyaddr = phyaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005954 np->phy_oui = id1 | id2;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005955
5956 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5957 if (np->phy_oui == PHY_OUI_REALTEK2)
5958 np->phy_oui = PHY_OUI_REALTEK;
5959 /* Setup phy revision for Realtek */
5960 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5961 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5962
Linus Torvalds1da177e2005-04-16 15:20:36 -07005963 break;
5964 }
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005965 if (i == 33) {
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005966 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005967 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005968 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005969
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005970 if (!phyinitialized) {
5971 /* reset it */
5972 phy_init(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005973 } else {
5974 /* see if it is a gigabit phy */
5975 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005976 if (mii_status & PHY_GIGABIT)
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005977 np->gigabit = PHY_GIGABIT;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005978 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005979
5980 /* set default link speed settings */
5981 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5982 np->duplex = 0;
5983 np->autoneg = 1;
5984
5985 err = register_netdev(dev);
5986 if (err) {
Joe Perchesb2ba08e2010-11-29 07:42:00 +00005987 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005988 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005989 }
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005990
david decotigny3f0a1b52012-08-24 17:22:53 +00005991 netif_carrier_off(dev);
5992
5993 /* Some NICs freeze when TX pause is enabled while NIC is
5994 * down, and this stays across warm reboots. The sequence
5995 * below should be enough to recover from that state.
5996 */
5997 nv_update_pause(dev, 0);
5998 nv_start_tx(dev);
5999 nv_stop_tx(dev);
6000
David S. Miller823dcd22011-08-20 10:39:12 -07006001 if (id->driver_data & DEV_HAS_VLAN)
6002 nv_vlan_mode(dev, dev->features);
Jiri Pirko0891b0e2011-07-26 10:19:28 +00006003
Joe Perchesb2ba08e2010-11-29 07:42:00 +00006004 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
6005 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04006006
Sanjay Hortikare19df762011-11-11 16:11:21 +00006007 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
Joe Perchesb2ba08e2010-11-29 07:42:00 +00006008 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
6009 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
Szymon Janc78aea4f2010-11-27 08:39:43 +00006010 "csum " : "",
Patrick McHardyf6469682013-04-19 02:04:27 +00006011 dev->features & (NETIF_F_HW_VLAN_CTAG_RX |
6012 NETIF_F_HW_VLAN_CTAG_TX) ?
Szymon Janc78aea4f2010-11-27 08:39:43 +00006013 "vlan " : "",
Sanjay Hortikare19df762011-11-11 16:11:21 +00006014 dev->features & (NETIF_F_LOOPBACK) ?
6015 "loopback " : "",
Joe Perchesb2ba08e2010-11-29 07:42:00 +00006016 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6017 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6018 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6019 np->gigabit == PHY_GIGABIT ? "gbit " : "",
6020 np->need_linktimer ? "lnktim " : "",
6021 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6022 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6023 np->desc_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006024
6025 return 0;
6026
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04006027out_error:
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05006028 if (phystate_orig)
6029 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04006030out_freering:
6031 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006032out_unmap:
6033 iounmap(get_hwbase(dev));
6034out_relreg:
6035 pci_release_regions(pci_dev);
6036out_disable:
6037 pci_disable_device(pci_dev);
6038out_free:
6039 free_netdev(dev);
6040out:
6041 return err;
6042}
6043
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04006044static void nv_restore_phy(struct net_device *dev)
6045{
6046 struct fe_priv *np = netdev_priv(dev);
6047 u16 phy_reserved, mii_control;
6048
6049 if (np->phy_oui == PHY_OUI_REALTEK &&
6050 np->phy_model == PHY_MODEL_REALTEK_8201 &&
6051 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6052 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6053 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6054 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6055 phy_reserved |= PHY_REALTEK_INIT8;
6056 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6057 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6058
6059 /* restart auto negotiation */
6060 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6061 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6062 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6063 }
6064}
6065
Yinghai Luf55c21f2008-09-13 13:10:31 -07006066static void nv_restore_mac_addr(struct pci_dev *pci_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006067{
6068 struct net_device *dev = pci_get_drvdata(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04006069 struct fe_priv *np = netdev_priv(dev);
6070 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006071
Ayaz Abdullaf1489652006-07-31 12:04:45 -04006072 /* special op: write back the misordered MAC address - otherwise
6073 * the next nv_probe would see a wrong address.
6074 */
6075 writel(np->orig_mac[0], base + NvRegMacAddrA);
6076 writel(np->orig_mac[1], base + NvRegMacAddrB);
Björn Steinbrink2e3884b2008-01-07 23:22:53 -08006077 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6078 base + NvRegTransmitPoll);
Yinghai Luf55c21f2008-09-13 13:10:31 -07006079}
6080
Bill Pembertond05919a2012-12-03 09:23:20 -05006081static void nv_remove(struct pci_dev *pci_dev)
Yinghai Luf55c21f2008-09-13 13:10:31 -07006082{
6083 struct net_device *dev = pci_get_drvdata(pci_dev);
6084
6085 unregister_netdev(dev);
6086
6087 nv_restore_mac_addr(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04006088
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04006089 /* restore any phy related changes */
6090 nv_restore_phy(dev);
6091
Ayaz Abdullacac1c522009-02-07 00:23:57 -08006092 nv_mgmt_release_sema(dev);
6093
Linus Torvalds1da177e2005-04-16 15:20:36 -07006094 /* free all structures */
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04006095 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006096 iounmap(get_hwbase(dev));
6097 pci_release_regions(pci_dev);
6098 pci_disable_device(pci_dev);
6099 free_netdev(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006100}
6101
Michel Lespinasse94252762011-03-06 16:14:50 +00006102#ifdef CONFIG_PM_SLEEP
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00006103static int nv_suspend(struct device *device)
Francois Romieua1893172006-10-10 14:33:27 -07006104{
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00006105 struct pci_dev *pdev = to_pci_dev(device);
Francois Romieua1893172006-10-10 14:33:27 -07006106 struct net_device *dev = pci_get_drvdata(pdev);
6107 struct fe_priv *np = netdev_priv(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006108 u8 __iomem *base = get_hwbase(dev);
6109 int i;
Francois Romieua1893172006-10-10 14:33:27 -07006110
Tobias Diedrich25d90812008-05-18 15:04:29 +02006111 if (netif_running(dev)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00006112 /* Gross. */
Tobias Diedrich25d90812008-05-18 15:04:29 +02006113 nv_close(dev);
6114 }
Francois Romieua1893172006-10-10 14:33:27 -07006115 netif_device_detach(dev);
6116
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006117 /* save non-pci configuration space */
Szymon Janc78aea4f2010-11-27 08:39:43 +00006118 for (i = 0; i <= np->register_size/sizeof(u32); i++)
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006119 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6120
Francois Romieua1893172006-10-10 14:33:27 -07006121 return 0;
6122}
6123
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00006124static int nv_resume(struct device *device)
Francois Romieua1893172006-10-10 14:33:27 -07006125{
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00006126 struct pci_dev *pdev = to_pci_dev(device);
Francois Romieua1893172006-10-10 14:33:27 -07006127 struct net_device *dev = pci_get_drvdata(pdev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006128 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07006129 u8 __iomem *base = get_hwbase(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006130 int i, rc = 0;
Francois Romieua1893172006-10-10 14:33:27 -07006131
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006132 /* restore non-pci configuration space */
Szymon Janc78aea4f2010-11-27 08:39:43 +00006133 for (i = 0; i <= np->register_size/sizeof(u32); i++)
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006134 writel(np->saved_config_space[i], base+i*sizeof(u32));
Ayaz Abdullaa376e792008-04-10 21:30:35 -07006135
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006136 if (np->driver_data & DEV_NEED_MSI_FIX)
6137 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
Ayaz Abdullab6e44052009-02-07 00:24:15 -08006138
Ed Swierk35a74332009-04-06 17:49:12 -07006139 /* restore phy state, including autoneg */
6140 phy_init(dev);
6141
Tobias Diedrich25d90812008-05-18 15:04:29 +02006142 netif_device_attach(dev);
6143 if (netif_running(dev)) {
6144 rc = nv_open(dev);
6145 nv_set_multicast(dev);
6146 }
Francois Romieua1893172006-10-10 14:33:27 -07006147 return rc;
6148}
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006149
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00006150static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
6151#define NV_PM_OPS (&nv_pm_ops)
6152
Michel Lespinasse94252762011-03-06 16:14:50 +00006153#else
6154#define NV_PM_OPS NULL
6155#endif /* CONFIG_PM_SLEEP */
6156
6157#ifdef CONFIG_PM
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006158static void nv_shutdown(struct pci_dev *pdev)
6159{
6160 struct net_device *dev = pci_get_drvdata(pdev);
6161 struct fe_priv *np = netdev_priv(dev);
6162
6163 if (netif_running(dev))
6164 nv_close(dev);
6165
Tobias Diedrich34edaa82009-02-16 00:13:20 -08006166 /*
6167 * Restore the MAC so a kernel started by kexec won't get confused.
6168 * If we really go for poweroff, we must not restore the MAC,
6169 * otherwise the MAC for WOL will be reversed at least on some boards.
6170 */
Szymon Janc78aea4f2010-11-27 08:39:43 +00006171 if (system_state != SYSTEM_POWER_OFF)
Tobias Diedrich34edaa82009-02-16 00:13:20 -08006172 nv_restore_mac_addr(pdev);
Yinghai Luf55c21f2008-09-13 13:10:31 -07006173
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006174 pci_disable_device(pdev);
Tobias Diedrich34edaa82009-02-16 00:13:20 -08006175 /*
6176 * Apparently it is not possible to reinitialise from D3 hot,
6177 * only put the device into D3 if we really go for poweroff.
6178 */
Rafael J. Wysocki3cb55992008-09-05 14:00:19 -07006179 if (system_state == SYSTEM_POWER_OFF) {
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00006180 pci_wake_from_d3(pdev, np->wolenabled);
Rafael J. Wysocki3cb55992008-09-05 14:00:19 -07006181 pci_set_power_state(pdev, PCI_D3hot);
6182 }
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006183}
Francois Romieua1893172006-10-10 14:33:27 -07006184#else
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006185#define nv_shutdown NULL
Francois Romieua1893172006-10-10 14:33:27 -07006186#endif /* CONFIG_PM */
6187
Benoit Taine9baa3c32014-08-08 15:56:03 +02006188static const struct pci_device_id pci_tbl[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07006189 { /* nForce Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006190 PCI_DEVICE(0x10DE, 0x01C3),
Manfred Spraulc2dba062005-07-31 18:29:47 +02006191 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006192 },
6193 { /* nForce2 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006194 PCI_DEVICE(0x10DE, 0x0066),
Manfred Spraulc2dba062005-07-31 18:29:47 +02006195 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006196 },
6197 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006198 PCI_DEVICE(0x10DE, 0x00D6),
Manfred Spraulc2dba062005-07-31 18:29:47 +02006199 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006200 },
6201 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006202 PCI_DEVICE(0x10DE, 0x0086),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006203 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006204 },
6205 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006206 PCI_DEVICE(0x10DE, 0x008C),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006207 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006208 },
6209 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006210 PCI_DEVICE(0x10DE, 0x00E6),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006211 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006212 },
6213 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006214 PCI_DEVICE(0x10DE, 0x00DF),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006215 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006216 },
6217 { /* CK804 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006218 PCI_DEVICE(0x10DE, 0x0056),
Yinghai Lu033e97b2009-02-06 01:30:56 -08006219 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006220 },
6221 { /* CK804 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006222 PCI_DEVICE(0x10DE, 0x0057),
Yinghai Lu033e97b2009-02-06 01:30:56 -08006223 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006224 },
6225 { /* MCP04 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006226 PCI_DEVICE(0x10DE, 0x0037),
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006227 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006228 },
6229 { /* MCP04 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006230 PCI_DEVICE(0x10DE, 0x0038),
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006231 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006232 },
6233 { /* MCP51 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006234 PCI_DEVICE(0x10DE, 0x0268),
6235 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006236 },
Manfred Spraul9992d4a2005-06-05 17:36:11 +02006237 { /* MCP51 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006238 PCI_DEVICE(0x10DE, 0x0269),
6239 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
Manfred Spraul9992d4a2005-06-05 17:36:11 +02006240 },
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006241 { /* MCP55 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006242 PCI_DEVICE(0x10DE, 0x0372),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006243 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006244 },
6245 { /* MCP55 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006246 PCI_DEVICE(0x10DE, 0x0373),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006247 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006248 },
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006249 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006250 PCI_DEVICE(0x10DE, 0x03E5),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006251 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006252 },
6253 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006254 PCI_DEVICE(0x10DE, 0x03E6),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006255 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006256 },
6257 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006258 PCI_DEVICE(0x10DE, 0x03EE),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006259 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006260 },
6261 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006262 PCI_DEVICE(0x10DE, 0x03EF),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006263 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006264 },
6265 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006266 PCI_DEVICE(0x10DE, 0x0450),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006267 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006268 },
6269 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006270 PCI_DEVICE(0x10DE, 0x0451),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006271 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006272 },
6273 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006274 PCI_DEVICE(0x10DE, 0x0452),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006275 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006276 },
6277 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006278 PCI_DEVICE(0x10DE, 0x0453),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006279 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006280 },
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006281 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006282 PCI_DEVICE(0x10DE, 0x054C),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006283 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006284 },
6285 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006286 PCI_DEVICE(0x10DE, 0x054D),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006287 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006288 },
6289 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006290 PCI_DEVICE(0x10DE, 0x054E),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006291 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006292 },
6293 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006294 PCI_DEVICE(0x10DE, 0x054F),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006295 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006296 },
Ayaz Abdulla13986612007-07-22 20:43:26 -04006297 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006298 PCI_DEVICE(0x10DE, 0x07DC),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006299 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006300 },
6301 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006302 PCI_DEVICE(0x10DE, 0x07DD),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006303 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006304 },
6305 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006306 PCI_DEVICE(0x10DE, 0x07DE),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006307 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006308 },
6309 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006310 PCI_DEVICE(0x10DE, 0x07DF),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006311 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006312 },
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006313 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006314 PCI_DEVICE(0x10DE, 0x0760),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006315 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006316 },
6317 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006318 PCI_DEVICE(0x10DE, 0x0761),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006319 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006320 },
6321 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006322 PCI_DEVICE(0x10DE, 0x0762),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006323 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006324 },
6325 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006326 PCI_DEVICE(0x10DE, 0x0763),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006327 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006328 },
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006329 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006330 PCI_DEVICE(0x10DE, 0x0AB0),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006331 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006332 },
6333 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006334 PCI_DEVICE(0x10DE, 0x0AB1),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006335 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006336 },
6337 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006338 PCI_DEVICE(0x10DE, 0x0AB2),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006339 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006340 },
6341 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006342 PCI_DEVICE(0x10DE, 0x0AB3),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006343 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006344 },
Ayaz Abdulla3df81c42009-06-03 15:05:35 +00006345 { /* MCP89 Ethernet Controller */
6346 PCI_DEVICE(0x10DE, 0x0D7D),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006347 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
Ayaz Abdulla3df81c42009-06-03 15:05:35 +00006348 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07006349 {0,},
6350};
6351
Peter Hüwe4f45c402013-05-21 13:42:56 +00006352static struct pci_driver forcedeth_pci_driver = {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04006353 .name = DRV_NAME,
6354 .id_table = pci_tbl,
6355 .probe = nv_probe,
Bill Pembertond05919a2012-12-03 09:23:20 -05006356 .remove = nv_remove,
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006357 .shutdown = nv_shutdown,
Rafael J. Wysockidba5a682011-01-07 11:12:05 +00006358 .driver.pm = NV_PM_OPS,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006359};
6360
Linus Torvalds1da177e2005-04-16 15:20:36 -07006361module_param(max_interrupt_work, int, 0);
6362MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05006363module_param(optimization_mode, int, 0);
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006364MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05006365module_param(poll_interval, int, 0);
6366MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04006367module_param(msi, int, 0);
6368MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6369module_param(msix, int, 0);
6370MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6371module_param(dma_64bit, int, 0);
6372MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04006373module_param(phy_cross, int, 0);
6374MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
Ed Swierk5a9a8e32009-06-02 00:19:52 -07006375module_param(phy_power_down, int, 0);
6376MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
Sameer Nanda1ec4f2d2011-11-16 12:15:12 +00006377module_param(debug_tx_timeout, bool, 0);
6378MODULE_PARM_DESC(debug_tx_timeout,
6379 "Dump tx related registers and ring when tx_timeout happens");
Linus Torvalds1da177e2005-04-16 15:20:36 -07006380
Peter Hüwe4f45c402013-05-21 13:42:56 +00006381module_pci_driver(forcedeth_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006382MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6383MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6384MODULE_LICENSE("GPL");
Linus Torvalds1da177e2005-04-16 15:20:36 -07006385MODULE_DEVICE_TABLE(pci, pci_tbl);