AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for AM33XX SoC |
| 3 | * |
| 4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. |
| 9 | */ |
| 10 | |
Florian Vaussard | e94233c | 2013-06-03 16:12:23 +0200 | [diff] [blame] | 11 | #include <dt-bindings/gpio/gpio.h> |
Florian Vaussard | 6a8a6b6 | 2013-06-03 16:12:25 +0200 | [diff] [blame] | 12 | #include <dt-bindings/pinctrl/am33xx.h> |
Florian Vaussard | e94233c | 2013-06-03 16:12:23 +0200 | [diff] [blame] | 13 | |
Florian Vaussard | eb33ef66 | 2013-06-03 16:12:22 +0200 | [diff] [blame] | 14 | #include "skeleton.dtsi" |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 15 | |
| 16 | / { |
| 17 | compatible = "ti,am33xx"; |
Benoit Cousson | 4c94ac2 | 2012-10-24 10:47:52 +0200 | [diff] [blame] | 18 | interrupt-parent = <&intc>; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 19 | |
| 20 | aliases { |
Nishanth Menon | 6a96867 | 2013-10-16 15:21:04 -0500 | [diff] [blame] | 21 | i2c0 = &i2c0; |
| 22 | i2c1 = &i2c1; |
| 23 | i2c2 = &i2c2; |
Vaibhav Hiremath | dde3b0d | 2013-03-28 11:36:05 +0530 | [diff] [blame] | 24 | serial0 = &uart0; |
| 25 | serial1 = &uart1; |
| 26 | serial2 = &uart2; |
| 27 | serial3 = &uart3; |
| 28 | serial4 = &uart4; |
| 29 | serial5 = &uart5; |
AnilKumar Ch | 7a57ee8 | 2012-11-14 23:38:24 +0530 | [diff] [blame] | 30 | d_can0 = &dcan0; |
| 31 | d_can1 = &dcan1; |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 32 | usb0 = &usb0; |
| 33 | usb1 = &usb1; |
| 34 | phy0 = &usb0_phy; |
| 35 | phy1 = &usb1_phy; |
Dan Murphy | 8170056 | 2013-10-02 12:58:33 -0500 | [diff] [blame] | 36 | ethernet0 = &cpsw_emac0; |
| 37 | ethernet1 = &cpsw_emac1; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 38 | }; |
| 39 | |
| 40 | cpus { |
Lorenzo Pieralisi | 2e0d513 | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 41 | #address-cells = <1>; |
| 42 | #size-cells = <0>; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 43 | cpu@0 { |
| 44 | compatible = "arm,cortex-a8"; |
Lorenzo Pieralisi | 2e0d513 | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 45 | device_type = "cpu"; |
| 46 | reg = <0>; |
AnilKumar Ch | efeedcf2 | 2012-08-31 15:07:20 +0530 | [diff] [blame] | 47 | |
| 48 | /* |
| 49 | * To consider voltage drop between PMIC and SoC, |
| 50 | * tolerance value is reduced to 2% from 4% and |
| 51 | * voltage value is increased as a precaution. |
| 52 | */ |
| 53 | operating-points = < |
| 54 | /* kHz uV */ |
| 55 | 720000 1285000 |
| 56 | 600000 1225000 |
| 57 | 500000 1125000 |
| 58 | 275000 1125000 |
| 59 | >; |
| 60 | voltage-tolerance = <2>; /* 2 percentage */ |
| 61 | clock-latency = <300000>; /* From omap-cpufreq driver */ |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 62 | }; |
| 63 | }; |
| 64 | |
Alexandre Belloni | 6797cdb | 2013-08-03 20:00:54 +0200 | [diff] [blame] | 65 | pmu { |
| 66 | compatible = "arm,cortex-a8-pmu"; |
| 67 | interrupts = <3>; |
| 68 | }; |
| 69 | |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 70 | /* |
| 71 | * The soc node represents the soc top level view. It is uses for IPs |
| 72 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 73 | */ |
| 74 | soc { |
| 75 | compatible = "ti,omap-infra"; |
| 76 | mpu { |
| 77 | compatible = "ti,omap3-mpu"; |
| 78 | ti,hwmods = "mpu"; |
| 79 | }; |
| 80 | }; |
| 81 | |
AnilKumar Ch | b552dfc | 2012-09-20 02:49:26 +0530 | [diff] [blame] | 82 | am33xx_pinmux: pinmux@44e10800 { |
| 83 | compatible = "pinctrl-single"; |
| 84 | reg = <0x44e10800 0x0238>; |
| 85 | #address-cells = <1>; |
| 86 | #size-cells = <0>; |
| 87 | pinctrl-single,register-width = <32>; |
| 88 | pinctrl-single,function-mask = <0x7f>; |
| 89 | }; |
| 90 | |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 91 | /* |
| 92 | * XXX: Use a flat representation of the AM33XX interconnect. |
| 93 | * The real AM33XX interconnect network is quite complex.Since |
| 94 | * that will not bring real advantage to represent that in DT |
| 95 | * for the moment, just use a fake OCP bus entry to represent |
| 96 | * the whole bus hierarchy. |
| 97 | */ |
| 98 | ocp { |
| 99 | compatible = "simple-bus"; |
| 100 | #address-cells = <1>; |
| 101 | #size-cells = <1>; |
| 102 | ranges; |
| 103 | ti,hwmods = "l3_main"; |
| 104 | |
| 105 | intc: interrupt-controller@48200000 { |
| 106 | compatible = "ti,omap2-intc"; |
| 107 | interrupt-controller; |
| 108 | #interrupt-cells = <1>; |
| 109 | ti,intc-size = <128>; |
| 110 | reg = <0x48200000 0x1000>; |
| 111 | }; |
| 112 | |
Matt Porter | 505975d | 2013-09-10 14:24:37 -0500 | [diff] [blame] | 113 | edma: edma@49000000 { |
| 114 | compatible = "ti,edma3"; |
| 115 | ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; |
| 116 | reg = <0x49000000 0x10000>, |
| 117 | <0x44e10f90 0x10>; |
| 118 | interrupts = <12 13 14>; |
| 119 | #dma-cells = <1>; |
| 120 | dma-channels = <64>; |
| 121 | ti,edma-regions = <4>; |
| 122 | ti,edma-slots = <256>; |
| 123 | }; |
| 124 | |
AnilKumar Ch | b918e2c | 2012-11-21 17:22:17 +0530 | [diff] [blame] | 125 | gpio0: gpio@44e07000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 126 | compatible = "ti,omap4-gpio"; |
| 127 | ti,hwmods = "gpio1"; |
| 128 | gpio-controller; |
| 129 | #gpio-cells = <2>; |
| 130 | interrupt-controller; |
Lars Poeschel | 5eac0eb | 2013-08-07 13:06:32 +0200 | [diff] [blame] | 131 | #interrupt-cells = <2>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 132 | reg = <0x44e07000 0x1000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 133 | interrupts = <96>; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 134 | }; |
| 135 | |
AnilKumar Ch | b918e2c | 2012-11-21 17:22:17 +0530 | [diff] [blame] | 136 | gpio1: gpio@4804c000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 137 | compatible = "ti,omap4-gpio"; |
| 138 | ti,hwmods = "gpio2"; |
| 139 | gpio-controller; |
| 140 | #gpio-cells = <2>; |
| 141 | interrupt-controller; |
Lars Poeschel | 5eac0eb | 2013-08-07 13:06:32 +0200 | [diff] [blame] | 142 | #interrupt-cells = <2>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 143 | reg = <0x4804c000 0x1000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 144 | interrupts = <98>; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 145 | }; |
| 146 | |
AnilKumar Ch | b918e2c | 2012-11-21 17:22:17 +0530 | [diff] [blame] | 147 | gpio2: gpio@481ac000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 148 | compatible = "ti,omap4-gpio"; |
| 149 | ti,hwmods = "gpio3"; |
| 150 | gpio-controller; |
| 151 | #gpio-cells = <2>; |
| 152 | interrupt-controller; |
Lars Poeschel | 5eac0eb | 2013-08-07 13:06:32 +0200 | [diff] [blame] | 153 | #interrupt-cells = <2>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 154 | reg = <0x481ac000 0x1000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 155 | interrupts = <32>; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 156 | }; |
| 157 | |
AnilKumar Ch | b918e2c | 2012-11-21 17:22:17 +0530 | [diff] [blame] | 158 | gpio3: gpio@481ae000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 159 | compatible = "ti,omap4-gpio"; |
| 160 | ti,hwmods = "gpio4"; |
| 161 | gpio-controller; |
| 162 | #gpio-cells = <2>; |
| 163 | interrupt-controller; |
Lars Poeschel | 5eac0eb | 2013-08-07 13:06:32 +0200 | [diff] [blame] | 164 | #interrupt-cells = <2>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 165 | reg = <0x481ae000 0x1000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 166 | interrupts = <62>; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 167 | }; |
| 168 | |
Vaibhav Hiremath | dde3b0d | 2013-03-28 11:36:05 +0530 | [diff] [blame] | 169 | uart0: serial@44e09000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 170 | compatible = "ti,omap3-uart"; |
| 171 | ti,hwmods = "uart1"; |
| 172 | clock-frequency = <48000000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 173 | reg = <0x44e09000 0x2000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 174 | interrupts = <72>; |
Vaibhav Hiremath | 53d9103 | 2012-08-15 16:53:25 +0530 | [diff] [blame] | 175 | status = "disabled"; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 176 | }; |
| 177 | |
Vaibhav Hiremath | dde3b0d | 2013-03-28 11:36:05 +0530 | [diff] [blame] | 178 | uart1: serial@48022000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 179 | compatible = "ti,omap3-uart"; |
| 180 | ti,hwmods = "uart2"; |
| 181 | clock-frequency = <48000000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 182 | reg = <0x48022000 0x2000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 183 | interrupts = <73>; |
Vaibhav Hiremath | 53d9103 | 2012-08-15 16:53:25 +0530 | [diff] [blame] | 184 | status = "disabled"; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 185 | }; |
| 186 | |
Vaibhav Hiremath | dde3b0d | 2013-03-28 11:36:05 +0530 | [diff] [blame] | 187 | uart2: serial@48024000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 188 | compatible = "ti,omap3-uart"; |
| 189 | ti,hwmods = "uart3"; |
| 190 | clock-frequency = <48000000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 191 | reg = <0x48024000 0x2000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 192 | interrupts = <74>; |
Vaibhav Hiremath | 53d9103 | 2012-08-15 16:53:25 +0530 | [diff] [blame] | 193 | status = "disabled"; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 194 | }; |
| 195 | |
Vaibhav Hiremath | dde3b0d | 2013-03-28 11:36:05 +0530 | [diff] [blame] | 196 | uart3: serial@481a6000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 197 | compatible = "ti,omap3-uart"; |
| 198 | ti,hwmods = "uart4"; |
| 199 | clock-frequency = <48000000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 200 | reg = <0x481a6000 0x2000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 201 | interrupts = <44>; |
Vaibhav Hiremath | 53d9103 | 2012-08-15 16:53:25 +0530 | [diff] [blame] | 202 | status = "disabled"; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 203 | }; |
| 204 | |
Vaibhav Hiremath | dde3b0d | 2013-03-28 11:36:05 +0530 | [diff] [blame] | 205 | uart4: serial@481a8000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 206 | compatible = "ti,omap3-uart"; |
| 207 | ti,hwmods = "uart5"; |
| 208 | clock-frequency = <48000000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 209 | reg = <0x481a8000 0x2000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 210 | interrupts = <45>; |
Vaibhav Hiremath | 53d9103 | 2012-08-15 16:53:25 +0530 | [diff] [blame] | 211 | status = "disabled"; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 212 | }; |
| 213 | |
Vaibhav Hiremath | dde3b0d | 2013-03-28 11:36:05 +0530 | [diff] [blame] | 214 | uart5: serial@481aa000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 215 | compatible = "ti,omap3-uart"; |
| 216 | ti,hwmods = "uart6"; |
| 217 | clock-frequency = <48000000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 218 | reg = <0x481aa000 0x2000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 219 | interrupts = <46>; |
Vaibhav Hiremath | 53d9103 | 2012-08-15 16:53:25 +0530 | [diff] [blame] | 220 | status = "disabled"; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 221 | }; |
| 222 | |
AnilKumar Ch | b918e2c | 2012-11-21 17:22:17 +0530 | [diff] [blame] | 223 | i2c0: i2c@44e0b000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 224 | compatible = "ti,omap4-i2c"; |
| 225 | #address-cells = <1>; |
| 226 | #size-cells = <0>; |
| 227 | ti,hwmods = "i2c1"; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 228 | reg = <0x44e0b000 0x1000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 229 | interrupts = <70>; |
Vaibhav Hiremath | 53d9103 | 2012-08-15 16:53:25 +0530 | [diff] [blame] | 230 | status = "disabled"; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 231 | }; |
| 232 | |
AnilKumar Ch | b918e2c | 2012-11-21 17:22:17 +0530 | [diff] [blame] | 233 | i2c1: i2c@4802a000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 234 | compatible = "ti,omap4-i2c"; |
| 235 | #address-cells = <1>; |
| 236 | #size-cells = <0>; |
| 237 | ti,hwmods = "i2c2"; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 238 | reg = <0x4802a000 0x1000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 239 | interrupts = <71>; |
Vaibhav Hiremath | 53d9103 | 2012-08-15 16:53:25 +0530 | [diff] [blame] | 240 | status = "disabled"; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 241 | }; |
| 242 | |
AnilKumar Ch | b918e2c | 2012-11-21 17:22:17 +0530 | [diff] [blame] | 243 | i2c2: i2c@4819c000 { |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 244 | compatible = "ti,omap4-i2c"; |
| 245 | #address-cells = <1>; |
| 246 | #size-cells = <0>; |
| 247 | ti,hwmods = "i2c3"; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 248 | reg = <0x4819c000 0x1000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 249 | interrupts = <30>; |
Vaibhav Hiremath | 53d9103 | 2012-08-15 16:53:25 +0530 | [diff] [blame] | 250 | status = "disabled"; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 251 | }; |
Afzal Mohammed | 5f789eb | 2012-07-04 18:00:37 +0530 | [diff] [blame] | 252 | |
Matt Porter | 55b4452 | 2013-09-10 14:24:39 -0500 | [diff] [blame] | 253 | mmc1: mmc@48060000 { |
| 254 | compatible = "ti,omap4-hsmmc"; |
| 255 | ti,hwmods = "mmc1"; |
| 256 | ti,dual-volt; |
| 257 | ti,needs-special-reset; |
| 258 | ti,needs-special-hs-handling; |
| 259 | dmas = <&edma 24 |
| 260 | &edma 25>; |
| 261 | dma-names = "tx", "rx"; |
| 262 | interrupts = <64>; |
| 263 | interrupt-parent = <&intc>; |
| 264 | reg = <0x48060000 0x1000>; |
| 265 | status = "disabled"; |
| 266 | }; |
| 267 | |
| 268 | mmc2: mmc@481d8000 { |
| 269 | compatible = "ti,omap4-hsmmc"; |
| 270 | ti,hwmods = "mmc2"; |
| 271 | ti,needs-special-reset; |
| 272 | dmas = <&edma 2 |
| 273 | &edma 3>; |
| 274 | dma-names = "tx", "rx"; |
| 275 | interrupts = <28>; |
| 276 | interrupt-parent = <&intc>; |
| 277 | reg = <0x481d8000 0x1000>; |
| 278 | status = "disabled"; |
| 279 | }; |
| 280 | |
| 281 | mmc3: mmc@47810000 { |
| 282 | compatible = "ti,omap4-hsmmc"; |
| 283 | ti,hwmods = "mmc3"; |
| 284 | ti,needs-special-reset; |
| 285 | interrupts = <29>; |
| 286 | interrupt-parent = <&intc>; |
| 287 | reg = <0x47810000 0x1000>; |
| 288 | status = "disabled"; |
| 289 | }; |
| 290 | |
Suman Anna | d4cbe80 | 2013-10-10 16:15:35 -0500 | [diff] [blame^] | 291 | hwspinlock: spinlock@480ca000 { |
| 292 | compatible = "ti,omap4-hwspinlock"; |
| 293 | reg = <0x480ca000 0x1000>; |
| 294 | ti,hwmods = "spinlock"; |
| 295 | }; |
| 296 | |
Afzal Mohammed | 5f789eb | 2012-07-04 18:00:37 +0530 | [diff] [blame] | 297 | wdt2: wdt@44e35000 { |
| 298 | compatible = "ti,omap3-wdt"; |
| 299 | ti,hwmods = "wd_timer2"; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 300 | reg = <0x44e35000 0x1000>; |
Vaibhav Hiremath | 4462b31 | 2012-08-27 17:21:01 +0530 | [diff] [blame] | 301 | interrupts = <91>; |
Afzal Mohammed | 5f789eb | 2012-07-04 18:00:37 +0530 | [diff] [blame] | 302 | }; |
AnilKumar Ch | 059b185 | 2012-09-20 02:49:27 +0530 | [diff] [blame] | 303 | |
| 304 | dcan0: d_can@481cc000 { |
| 305 | compatible = "bosch,d_can"; |
| 306 | ti,hwmods = "d_can0"; |
AnilKumar Ch | f178c01 | 2012-11-14 23:38:25 +0530 | [diff] [blame] | 307 | reg = <0x481cc000 0x2000 |
| 308 | 0x44e10644 0x4>; |
AnilKumar Ch | 059b185 | 2012-09-20 02:49:27 +0530 | [diff] [blame] | 309 | interrupts = <52>; |
AnilKumar Ch | 059b185 | 2012-09-20 02:49:27 +0530 | [diff] [blame] | 310 | status = "disabled"; |
| 311 | }; |
| 312 | |
| 313 | dcan1: d_can@481d0000 { |
| 314 | compatible = "bosch,d_can"; |
| 315 | ti,hwmods = "d_can1"; |
AnilKumar Ch | f178c01 | 2012-11-14 23:38:25 +0530 | [diff] [blame] | 316 | reg = <0x481d0000 0x2000 |
| 317 | 0x44e10644 0x4>; |
AnilKumar Ch | 059b185 | 2012-09-20 02:49:27 +0530 | [diff] [blame] | 318 | interrupts = <55>; |
AnilKumar Ch | 059b185 | 2012-09-20 02:49:27 +0530 | [diff] [blame] | 319 | status = "disabled"; |
| 320 | }; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 321 | |
| 322 | timer1: timer@44e31000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 323 | compatible = "ti,am335x-timer-1ms"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 324 | reg = <0x44e31000 0x400>; |
| 325 | interrupts = <67>; |
| 326 | ti,hwmods = "timer1"; |
| 327 | ti,timer-alwon; |
| 328 | }; |
| 329 | |
| 330 | timer2: timer@48040000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 331 | compatible = "ti,am335x-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 332 | reg = <0x48040000 0x400>; |
| 333 | interrupts = <68>; |
| 334 | ti,hwmods = "timer2"; |
| 335 | }; |
| 336 | |
| 337 | timer3: timer@48042000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 338 | compatible = "ti,am335x-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 339 | reg = <0x48042000 0x400>; |
| 340 | interrupts = <69>; |
| 341 | ti,hwmods = "timer3"; |
| 342 | }; |
| 343 | |
| 344 | timer4: timer@48044000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 345 | compatible = "ti,am335x-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 346 | reg = <0x48044000 0x400>; |
| 347 | interrupts = <92>; |
| 348 | ti,hwmods = "timer4"; |
| 349 | ti,timer-pwm; |
| 350 | }; |
| 351 | |
| 352 | timer5: timer@48046000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 353 | compatible = "ti,am335x-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 354 | reg = <0x48046000 0x400>; |
| 355 | interrupts = <93>; |
| 356 | ti,hwmods = "timer5"; |
| 357 | ti,timer-pwm; |
| 358 | }; |
| 359 | |
| 360 | timer6: timer@48048000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 361 | compatible = "ti,am335x-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 362 | reg = <0x48048000 0x400>; |
| 363 | interrupts = <94>; |
| 364 | ti,hwmods = "timer6"; |
| 365 | ti,timer-pwm; |
| 366 | }; |
| 367 | |
| 368 | timer7: timer@4804a000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 369 | compatible = "ti,am335x-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 370 | reg = <0x4804a000 0x400>; |
| 371 | interrupts = <95>; |
| 372 | ti,hwmods = "timer7"; |
| 373 | ti,timer-pwm; |
| 374 | }; |
Afzal Mohammed | 0d935c1 | 2012-10-30 15:04:01 +0530 | [diff] [blame] | 375 | |
| 376 | rtc@44e3e000 { |
| 377 | compatible = "ti,da830-rtc"; |
| 378 | reg = <0x44e3e000 0x1000>; |
| 379 | interrupts = <75 |
| 380 | 76>; |
| 381 | ti,hwmods = "rtc"; |
| 382 | }; |
Philip, Avinash | 9fd3c74 | 2012-10-31 16:21:09 +0530 | [diff] [blame] | 383 | |
| 384 | spi0: spi@48030000 { |
| 385 | compatible = "ti,omap4-mcspi"; |
| 386 | #address-cells = <1>; |
| 387 | #size-cells = <0>; |
| 388 | reg = <0x48030000 0x400>; |
Philip Avinash | 7b3754c | 2013-02-01 11:07:27 +0530 | [diff] [blame] | 389 | interrupts = <65>; |
Philip, Avinash | 9fd3c74 | 2012-10-31 16:21:09 +0530 | [diff] [blame] | 390 | ti,spi-num-cs = <2>; |
| 391 | ti,hwmods = "spi0"; |
Matt Porter | f5e2f80 | 2013-09-10 14:24:38 -0500 | [diff] [blame] | 392 | dmas = <&edma 16 |
| 393 | &edma 17 |
| 394 | &edma 18 |
| 395 | &edma 19>; |
| 396 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
Philip, Avinash | 9fd3c74 | 2012-10-31 16:21:09 +0530 | [diff] [blame] | 397 | status = "disabled"; |
| 398 | }; |
| 399 | |
| 400 | spi1: spi@481a0000 { |
| 401 | compatible = "ti,omap4-mcspi"; |
| 402 | #address-cells = <1>; |
| 403 | #size-cells = <0>; |
| 404 | reg = <0x481a0000 0x400>; |
Philip Avinash | 7b3754c | 2013-02-01 11:07:27 +0530 | [diff] [blame] | 405 | interrupts = <125>; |
Philip, Avinash | 9fd3c74 | 2012-10-31 16:21:09 +0530 | [diff] [blame] | 406 | ti,spi-num-cs = <2>; |
| 407 | ti,hwmods = "spi1"; |
Matt Porter | f5e2f80 | 2013-09-10 14:24:38 -0500 | [diff] [blame] | 408 | dmas = <&edma 42 |
| 409 | &edma 43 |
| 410 | &edma 44 |
| 411 | &edma 45>; |
| 412 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
Philip, Avinash | 9fd3c74 | 2012-10-31 16:21:09 +0530 | [diff] [blame] | 413 | status = "disabled"; |
| 414 | }; |
Ajay Kumar Gupta | 35b47fb | 2012-11-06 19:59:38 +0530 | [diff] [blame] | 415 | |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 416 | usb: usb@47400000 { |
| 417 | compatible = "ti,am33xx-usb"; |
| 418 | reg = <0x47400000 0x1000>; |
| 419 | ranges; |
| 420 | #address-cells = <1>; |
| 421 | #size-cells = <1>; |
Ajay Kumar Gupta | 35b47fb | 2012-11-06 19:59:38 +0530 | [diff] [blame] | 422 | ti,hwmods = "usb_otg_hs"; |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 423 | status = "disabled"; |
| 424 | |
Markus Pargmann | e7243b7 | 2013-10-14 14:49:21 +0200 | [diff] [blame] | 425 | usb_ctrl_mod: control@44e10000 { |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 426 | compatible = "ti,am335x-usb-ctrl-module"; |
| 427 | reg = <0x44e10620 0x10 |
| 428 | 0x44e10648 0x4>; |
| 429 | reg-names = "phy_ctrl", "wakeup"; |
| 430 | status = "disabled"; |
| 431 | }; |
| 432 | |
Sebastian Andrzej Siewior | c031a7d | 2013-08-20 18:35:47 +0200 | [diff] [blame] | 433 | usb0_phy: usb-phy@47401300 { |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 434 | compatible = "ti,am335x-usb-phy"; |
| 435 | reg = <0x47401300 0x100>; |
| 436 | reg-names = "phy"; |
| 437 | status = "disabled"; |
Markus Pargmann | e7243b7 | 2013-10-14 14:49:21 +0200 | [diff] [blame] | 438 | ti,ctrl_mod = <&usb_ctrl_mod>; |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 439 | }; |
| 440 | |
| 441 | usb0: usb@47401000 { |
| 442 | compatible = "ti,musb-am33xx"; |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 443 | status = "disabled"; |
Sebastian Andrzej Siewior | c031a7d | 2013-08-20 18:35:47 +0200 | [diff] [blame] | 444 | reg = <0x47401400 0x400 |
| 445 | 0x47401000 0x200>; |
| 446 | reg-names = "mc", "control"; |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 447 | |
Sebastian Andrzej Siewior | c031a7d | 2013-08-20 18:35:47 +0200 | [diff] [blame] | 448 | interrupts = <18>; |
| 449 | interrupt-names = "mc"; |
| 450 | dr_mode = "otg"; |
| 451 | mentor,multipoint = <1>; |
| 452 | mentor,num-eps = <16>; |
| 453 | mentor,ram-bits = <12>; |
| 454 | mentor,power = <500>; |
| 455 | phys = <&usb0_phy>; |
Sebastian Andrzej Siewior | 9b3452d | 2013-06-20 12:13:04 +0200 | [diff] [blame] | 456 | |
| 457 | dmas = <&cppi41dma 0 0 &cppi41dma 1 0 |
| 458 | &cppi41dma 2 0 &cppi41dma 3 0 |
| 459 | &cppi41dma 4 0 &cppi41dma 5 0 |
| 460 | &cppi41dma 6 0 &cppi41dma 7 0 |
| 461 | &cppi41dma 8 0 &cppi41dma 9 0 |
| 462 | &cppi41dma 10 0 &cppi41dma 11 0 |
| 463 | &cppi41dma 12 0 &cppi41dma 13 0 |
| 464 | &cppi41dma 14 0 &cppi41dma 0 1 |
| 465 | &cppi41dma 1 1 &cppi41dma 2 1 |
| 466 | &cppi41dma 3 1 &cppi41dma 4 1 |
| 467 | &cppi41dma 5 1 &cppi41dma 6 1 |
| 468 | &cppi41dma 7 1 &cppi41dma 8 1 |
| 469 | &cppi41dma 9 1 &cppi41dma 10 1 |
| 470 | &cppi41dma 11 1 &cppi41dma 12 1 |
| 471 | &cppi41dma 13 1 &cppi41dma 14 1>; |
| 472 | dma-names = |
| 473 | "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", |
| 474 | "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", |
| 475 | "rx14", "rx15", |
| 476 | "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", |
| 477 | "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", |
| 478 | "tx14", "tx15"; |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 479 | }; |
| 480 | |
Sebastian Andrzej Siewior | c031a7d | 2013-08-20 18:35:47 +0200 | [diff] [blame] | 481 | usb1_phy: usb-phy@47401b00 { |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 482 | compatible = "ti,am335x-usb-phy"; |
| 483 | reg = <0x47401b00 0x100>; |
| 484 | reg-names = "phy"; |
| 485 | status = "disabled"; |
Markus Pargmann | e7243b7 | 2013-10-14 14:49:21 +0200 | [diff] [blame] | 486 | ti,ctrl_mod = <&usb_ctrl_mod>; |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 487 | }; |
| 488 | |
| 489 | usb1: usb@47401800 { |
| 490 | compatible = "ti,musb-am33xx"; |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 491 | status = "disabled"; |
Sebastian Andrzej Siewior | c031a7d | 2013-08-20 18:35:47 +0200 | [diff] [blame] | 492 | reg = <0x47401c00 0x400 |
| 493 | 0x47401800 0x200>; |
| 494 | reg-names = "mc", "control"; |
| 495 | interrupts = <19>; |
| 496 | interrupt-names = "mc"; |
| 497 | dr_mode = "otg"; |
| 498 | mentor,multipoint = <1>; |
| 499 | mentor,num-eps = <16>; |
| 500 | mentor,ram-bits = <12>; |
| 501 | mentor,power = <500>; |
| 502 | phys = <&usb1_phy>; |
Sebastian Andrzej Siewior | 9b3452d | 2013-06-20 12:13:04 +0200 | [diff] [blame] | 503 | |
| 504 | dmas = <&cppi41dma 15 0 &cppi41dma 16 0 |
| 505 | &cppi41dma 17 0 &cppi41dma 18 0 |
| 506 | &cppi41dma 19 0 &cppi41dma 20 0 |
| 507 | &cppi41dma 21 0 &cppi41dma 22 0 |
| 508 | &cppi41dma 23 0 &cppi41dma 24 0 |
| 509 | &cppi41dma 25 0 &cppi41dma 26 0 |
| 510 | &cppi41dma 27 0 &cppi41dma 28 0 |
| 511 | &cppi41dma 29 0 &cppi41dma 15 1 |
| 512 | &cppi41dma 16 1 &cppi41dma 17 1 |
| 513 | &cppi41dma 18 1 &cppi41dma 19 1 |
| 514 | &cppi41dma 20 1 &cppi41dma 21 1 |
| 515 | &cppi41dma 22 1 &cppi41dma 23 1 |
| 516 | &cppi41dma 24 1 &cppi41dma 25 1 |
| 517 | &cppi41dma 26 1 &cppi41dma 27 1 |
| 518 | &cppi41dma 28 1 &cppi41dma 29 1>; |
| 519 | dma-names = |
| 520 | "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", |
| 521 | "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", |
| 522 | "rx14", "rx15", |
| 523 | "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", |
| 524 | "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", |
| 525 | "tx14", "tx15"; |
Sebastian Andrzej Siewior | 97238b3 | 2013-07-05 14:51:33 +0200 | [diff] [blame] | 526 | }; |
Sebastian Andrzej Siewior | 9b3452d | 2013-06-20 12:13:04 +0200 | [diff] [blame] | 527 | |
Sebastian Andrzej Siewior | c031a7d | 2013-08-20 18:35:47 +0200 | [diff] [blame] | 528 | cppi41dma: dma-controller@07402000 { |
Sebastian Andrzej Siewior | 9b3452d | 2013-06-20 12:13:04 +0200 | [diff] [blame] | 529 | compatible = "ti,am3359-cppi41"; |
| 530 | reg = <0x47400000 0x1000 |
| 531 | 0x47402000 0x1000 |
| 532 | 0x47403000 0x1000 |
| 533 | 0x47404000 0x4000>; |
Sebastian Andrzej Siewior | 3b6394b | 2013-08-20 18:35:45 +0200 | [diff] [blame] | 534 | reg-names = "glue", "controller", "scheduler", "queuemgr"; |
Sebastian Andrzej Siewior | 9b3452d | 2013-06-20 12:13:04 +0200 | [diff] [blame] | 535 | interrupts = <17>; |
| 536 | interrupt-names = "glue"; |
| 537 | #dma-cells = <2>; |
| 538 | #dma-channels = <30>; |
| 539 | #dma-requests = <256>; |
| 540 | status = "disabled"; |
| 541 | }; |
Ajay Kumar Gupta | 35b47fb | 2012-11-06 19:59:38 +0530 | [diff] [blame] | 542 | }; |
Linus Torvalds | 6be35c7 | 2012-12-12 18:07:07 -0800 | [diff] [blame] | 543 | |
Philip Avinash | 0a7486c | 2013-06-06 15:52:37 +0200 | [diff] [blame] | 544 | epwmss0: epwmss@48300000 { |
| 545 | compatible = "ti,am33xx-pwmss"; |
| 546 | reg = <0x48300000 0x10>; |
| 547 | ti,hwmods = "epwmss0"; |
| 548 | #address-cells = <1>; |
| 549 | #size-cells = <1>; |
| 550 | status = "disabled"; |
| 551 | ranges = <0x48300100 0x48300100 0x80 /* ECAP */ |
| 552 | 0x48300180 0x48300180 0x80 /* EQEP */ |
| 553 | 0x48300200 0x48300200 0x80>; /* EHRPWM */ |
| 554 | |
| 555 | ecap0: ecap@48300100 { |
| 556 | compatible = "ti,am33xx-ecap"; |
| 557 | #pwm-cells = <3>; |
| 558 | reg = <0x48300100 0x80>; |
| 559 | ti,hwmods = "ecap0"; |
| 560 | status = "disabled"; |
| 561 | }; |
| 562 | |
| 563 | ehrpwm0: ehrpwm@48300200 { |
| 564 | compatible = "ti,am33xx-ehrpwm"; |
| 565 | #pwm-cells = <3>; |
| 566 | reg = <0x48300200 0x80>; |
| 567 | ti,hwmods = "ehrpwm0"; |
| 568 | status = "disabled"; |
| 569 | }; |
| 570 | }; |
| 571 | |
| 572 | epwmss1: epwmss@48302000 { |
| 573 | compatible = "ti,am33xx-pwmss"; |
| 574 | reg = <0x48302000 0x10>; |
| 575 | ti,hwmods = "epwmss1"; |
| 576 | #address-cells = <1>; |
| 577 | #size-cells = <1>; |
| 578 | status = "disabled"; |
| 579 | ranges = <0x48302100 0x48302100 0x80 /* ECAP */ |
| 580 | 0x48302180 0x48302180 0x80 /* EQEP */ |
| 581 | 0x48302200 0x48302200 0x80>; /* EHRPWM */ |
| 582 | |
| 583 | ecap1: ecap@48302100 { |
| 584 | compatible = "ti,am33xx-ecap"; |
| 585 | #pwm-cells = <3>; |
| 586 | reg = <0x48302100 0x80>; |
| 587 | ti,hwmods = "ecap1"; |
| 588 | status = "disabled"; |
| 589 | }; |
| 590 | |
| 591 | ehrpwm1: ehrpwm@48302200 { |
| 592 | compatible = "ti,am33xx-ehrpwm"; |
| 593 | #pwm-cells = <3>; |
| 594 | reg = <0x48302200 0x80>; |
| 595 | ti,hwmods = "ehrpwm1"; |
| 596 | status = "disabled"; |
| 597 | }; |
| 598 | }; |
| 599 | |
| 600 | epwmss2: epwmss@48304000 { |
| 601 | compatible = "ti,am33xx-pwmss"; |
| 602 | reg = <0x48304000 0x10>; |
| 603 | ti,hwmods = "epwmss2"; |
| 604 | #address-cells = <1>; |
| 605 | #size-cells = <1>; |
| 606 | status = "disabled"; |
| 607 | ranges = <0x48304100 0x48304100 0x80 /* ECAP */ |
| 608 | 0x48304180 0x48304180 0x80 /* EQEP */ |
| 609 | 0x48304200 0x48304200 0x80>; /* EHRPWM */ |
| 610 | |
| 611 | ecap2: ecap@48304100 { |
| 612 | compatible = "ti,am33xx-ecap"; |
| 613 | #pwm-cells = <3>; |
| 614 | reg = <0x48304100 0x80>; |
| 615 | ti,hwmods = "ecap2"; |
| 616 | status = "disabled"; |
| 617 | }; |
| 618 | |
| 619 | ehrpwm2: ehrpwm@48304200 { |
| 620 | compatible = "ti,am33xx-ehrpwm"; |
| 621 | #pwm-cells = <3>; |
| 622 | reg = <0x48304200 0x80>; |
| 623 | ti,hwmods = "ehrpwm2"; |
| 624 | status = "disabled"; |
| 625 | }; |
| 626 | }; |
| 627 | |
Mugunthan V N | 1a39a65 | 2012-11-14 09:08:00 +0000 | [diff] [blame] | 628 | mac: ethernet@4a100000 { |
| 629 | compatible = "ti,cpsw"; |
| 630 | ti,hwmods = "cpgmac0"; |
| 631 | cpdma_channels = <8>; |
| 632 | ale_entries = <1024>; |
| 633 | bd_ram_size = <0x2000>; |
| 634 | no_bd_ram = <0>; |
| 635 | rx_descs = <64>; |
| 636 | mac_control = <0x20>; |
| 637 | slaves = <2>; |
Mugunthan V N | e86ac13 | 2013-03-11 23:16:35 +0000 | [diff] [blame] | 638 | active_slave = <0>; |
Mugunthan V N | 1a39a65 | 2012-11-14 09:08:00 +0000 | [diff] [blame] | 639 | cpts_clock_mult = <0x80000000>; |
| 640 | cpts_clock_shift = <29>; |
| 641 | reg = <0x4a100000 0x800 |
| 642 | 0x4a101200 0x100>; |
| 643 | #address-cells = <1>; |
| 644 | #size-cells = <1>; |
| 645 | interrupt-parent = <&intc>; |
| 646 | /* |
| 647 | * c0_rx_thresh_pend |
| 648 | * c0_rx_pend |
| 649 | * c0_tx_pend |
| 650 | * c0_misc_pend |
| 651 | */ |
| 652 | interrupts = <40 41 42 43>; |
| 653 | ranges; |
| 654 | |
| 655 | davinci_mdio: mdio@4a101000 { |
| 656 | compatible = "ti,davinci_mdio"; |
| 657 | #address-cells = <1>; |
| 658 | #size-cells = <0>; |
| 659 | ti,hwmods = "davinci_mdio"; |
| 660 | bus_freq = <1000000>; |
| 661 | reg = <0x4a101000 0x100>; |
| 662 | }; |
| 663 | |
| 664 | cpsw_emac0: slave@4a100200 { |
| 665 | /* Filled in by U-Boot */ |
| 666 | mac-address = [ 00 00 00 00 00 00 ]; |
| 667 | }; |
| 668 | |
| 669 | cpsw_emac1: slave@4a100300 { |
| 670 | /* Filled in by U-Boot */ |
| 671 | mac-address = [ 00 00 00 00 00 00 ]; |
| 672 | }; |
Mugunthan V N | 1a39a65 | 2012-11-14 09:08:00 +0000 | [diff] [blame] | 673 | }; |
Vaibhav Bedia | f6575c9 | 2013-01-29 16:45:07 +0530 | [diff] [blame] | 674 | |
| 675 | ocmcram: ocmcram@40300000 { |
| 676 | compatible = "ti,am3352-ocmcram"; |
| 677 | reg = <0x40300000 0x10000>; |
| 678 | ti,hwmods = "ocmcram"; |
Vaibhav Bedia | f6575c9 | 2013-01-29 16:45:07 +0530 | [diff] [blame] | 679 | }; |
| 680 | |
| 681 | wkup_m3: wkup_m3@44d00000 { |
| 682 | compatible = "ti,am3353-wkup-m3"; |
| 683 | reg = <0x44d00000 0x4000 /* M3 UMEM */ |
| 684 | 0x44d80000 0x2000>; /* M3 DMEM */ |
| 685 | ti,hwmods = "wkup_m3"; |
Rajendra Nayak | f12ecbe | 2013-10-15 12:37:50 +0530 | [diff] [blame] | 686 | ti,no-reset-on-init; |
Vaibhav Bedia | f6575c9 | 2013-01-29 16:45:07 +0530 | [diff] [blame] | 687 | }; |
Philip Avinash | e45879e | 2013-05-02 15:14:03 +0530 | [diff] [blame] | 688 | |
Philip, Avinash | 15e8246 | 2013-05-31 13:19:03 +0530 | [diff] [blame] | 689 | elm: elm@48080000 { |
| 690 | compatible = "ti,am3352-elm"; |
| 691 | reg = <0x48080000 0x2000>; |
| 692 | interrupts = <4>; |
| 693 | ti,hwmods = "elm"; |
| 694 | status = "disabled"; |
| 695 | }; |
| 696 | |
Benoit Parrot | d6cfc1e | 2013-08-08 18:28:14 -0500 | [diff] [blame] | 697 | lcdc: lcdc@4830e000 { |
| 698 | compatible = "ti,am33xx-tilcdc"; |
| 699 | reg = <0x4830e000 0x1000>; |
| 700 | interrupt-parent = <&intc>; |
| 701 | interrupts = <36>; |
| 702 | ti,hwmods = "lcdc"; |
| 703 | status = "disabled"; |
| 704 | }; |
| 705 | |
Patil, Rachna | a82279d | 2013-01-24 03:45:12 +0000 | [diff] [blame] | 706 | tscadc: tscadc@44e0d000 { |
| 707 | compatible = "ti,am3359-tscadc"; |
| 708 | reg = <0x44e0d000 0x1000>; |
| 709 | interrupt-parent = <&intc>; |
| 710 | interrupts = <16>; |
| 711 | ti,hwmods = "adc_tsc"; |
| 712 | status = "disabled"; |
| 713 | |
| 714 | tsc { |
| 715 | compatible = "ti,am3359-tsc"; |
| 716 | }; |
| 717 | am335x_adc: adc { |
| 718 | #io-channel-cells = <1>; |
| 719 | compatible = "ti,am3359-adc"; |
| 720 | }; |
Patil, Rachna | a82279d | 2013-01-24 03:45:12 +0000 | [diff] [blame] | 721 | }; |
| 722 | |
Philip Avinash | e45879e | 2013-05-02 15:14:03 +0530 | [diff] [blame] | 723 | gpmc: gpmc@50000000 { |
| 724 | compatible = "ti,am3352-gpmc"; |
| 725 | ti,hwmods = "gpmc"; |
Rajendra Nayak | f12ecbe | 2013-10-15 12:37:50 +0530 | [diff] [blame] | 726 | ti,no-idle-on-init; |
Philip Avinash | e45879e | 2013-05-02 15:14:03 +0530 | [diff] [blame] | 727 | reg = <0x50000000 0x2000>; |
| 728 | interrupts = <100>; |
Lars Poeschel | 00dddca | 2013-05-28 10:24:57 +0200 | [diff] [blame] | 729 | gpmc,num-cs = <7>; |
| 730 | gpmc,num-waitpins = <2>; |
Philip Avinash | e45879e | 2013-05-02 15:14:03 +0530 | [diff] [blame] | 731 | #address-cells = <2>; |
| 732 | #size-cells = <1>; |
| 733 | status = "disabled"; |
| 734 | }; |
Mark A. Greer | f8302e1 | 2013-08-23 14:12:35 -0700 | [diff] [blame] | 735 | |
| 736 | sham: sham@53100000 { |
| 737 | compatible = "ti,omap4-sham"; |
| 738 | ti,hwmods = "sham"; |
| 739 | reg = <0x53100000 0x200>; |
| 740 | interrupts = <109>; |
| 741 | dmas = <&edma 36>; |
| 742 | dma-names = "rx"; |
| 743 | }; |
Mark A. Greer | 99919e5e | 2013-08-23 14:12:36 -0700 | [diff] [blame] | 744 | |
| 745 | aes: aes@53500000 { |
| 746 | compatible = "ti,omap4-aes"; |
| 747 | ti,hwmods = "aes"; |
| 748 | reg = <0x53500000 0xa0>; |
Joel Fernandes | 7af8884 | 2013-07-17 19:07:52 -0500 | [diff] [blame] | 749 | interrupts = <103>; |
Mark A. Greer | 99919e5e | 2013-08-23 14:12:36 -0700 | [diff] [blame] | 750 | dmas = <&edma 6>, |
| 751 | <&edma 5>; |
| 752 | dma-names = "tx", "rx"; |
| 753 | }; |
Pantelis Antoniou | 3f72f87 | 2013-10-20 20:04:08 +0300 | [diff] [blame] | 754 | |
| 755 | mcasp0: mcasp@48038000 { |
| 756 | compatible = "ti,am33xx-mcasp-audio"; |
| 757 | ti,hwmods = "mcasp0"; |
Jyri Sarha | 0bee55a | 2013-10-20 20:04:09 +0300 | [diff] [blame] | 758 | reg = <0x48038000 0x2000>, |
| 759 | <0x46000000 0x400000>; |
| 760 | reg-names = "mpu", "dat"; |
Pantelis Antoniou | 3f72f87 | 2013-10-20 20:04:08 +0300 | [diff] [blame] | 761 | interrupts = <80>, <81>; |
| 762 | interrupts-names = "tx", "rx"; |
| 763 | status = "disabled"; |
| 764 | dmas = <&edma 8>, |
| 765 | <&edma 9>; |
| 766 | dma-names = "tx", "rx"; |
| 767 | }; |
| 768 | |
| 769 | mcasp1: mcasp@4803C000 { |
| 770 | compatible = "ti,am33xx-mcasp-audio"; |
| 771 | ti,hwmods = "mcasp1"; |
Jyri Sarha | 0bee55a | 2013-10-20 20:04:09 +0300 | [diff] [blame] | 772 | reg = <0x4803C000 0x2000>, |
| 773 | <0x46400000 0x400000>; |
| 774 | reg-names = "mpu", "dat"; |
Pantelis Antoniou | 3f72f87 | 2013-10-20 20:04:08 +0300 | [diff] [blame] | 775 | interrupts = <82>, <83>; |
| 776 | interrupts-names = "tx", "rx"; |
| 777 | status = "disabled"; |
| 778 | dmas = <&edma 10>, |
| 779 | <&edma 11>; |
| 780 | dma-names = "tx", "rx"; |
| 781 | }; |
AnilKumar Ch | 5fc0b42 | 2012-06-22 15:10:48 +0530 | [diff] [blame] | 782 | }; |
| 783 | }; |