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gerrit-public.fairphone.software / kernel / msm-4.9 / 1d8b368ab4aacfc3f864655baad4d31a3028ec1a / . / arch / arm / boot / dts / imx6qdl.dtsi
blob: 9e8296e4c3434afdf61004e62e2af83c9bbc8490 [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]31 intc: interrupt-controller@00a01000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 reg = <0x00a01000 0x1000>,
38 <0x00a00100 0x100>;
39 };
40
41 clocks {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 ckil {
46 compatible = "fsl,imx-ckil", "fixed-clock";
47 clock-frequency = <32768>;
48 };
49
50 ckih1 {
51 compatible = "fsl,imx-ckih1", "fixed-clock";
52 clock-frequency = <0>;
53 };
54
55 osc {
56 compatible = "fsl,imx-osc", "fixed-clock";
57 clock-frequency = <24000000>;
58 };
59 };
60
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
66 ranges;
67
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]68 dma_apbh: dma-apbh@00110000 {
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]71 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
72 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
73 #dma-cells = <1>;
74 dma-channels = <4>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]75 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]76 };
77
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]78 gpmi: gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]79 compatible = "fsl,imx6q-gpmi-nand";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
83 reg-names = "gpmi-nand", "bch";
84 interrupts = <0 13 0x04>, <0 15 0x04>;
85 interrupt-names = "gpmi-dma", "bch";
86 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
87 <&clks 150>, <&clks 149>;
88 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
89 "gpmi_bch_apb", "per1_bch";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]90 dmas = <&dma_apbh 0>;
91 dma-names = "rx-tx";
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]92 fsl,gpmi-dma-channel = <0>;
93 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]94 };
95
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]96 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]97 compatible = "arm,cortex-a9-twd-timer";
98 reg = <0x00a00600 0x20>;
99 interrupts = <1 13 0xf01>;
Shawn Guo2bb4b702013-04-03 23:50:09 +0800[diff] [blame]100 clocks = <&clks 15>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]101 };
102
103 L2: l2-cache@00a02000 {
104 compatible = "arm,pl310-cache";
105 reg = <0x00a02000 0x1000>;
106 interrupts = <0 92 0x04>;
107 cache-unified;
108 cache-level = <2>;
109 };
110
Dirk Behme218abe62013-02-15 15:10:01 +0100[diff] [blame]111 pmu {
112 compatible = "arm,cortex-a9-pmu";
113 interrupts = <0 94 0x04>;
114 };
115
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]116 aips-bus@02000000 { /* AIPS1 */
117 compatible = "fsl,aips-bus", "simple-bus";
118 #address-cells = <1>;
119 #size-cells = <1>;
120 reg = <0x02000000 0x100000>;
121 ranges;
122
123 spba-bus@02000000 {
124 compatible = "fsl,spba-bus", "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 reg = <0x02000000 0x40000>;
128 ranges;
129
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]130 spdif: spdif@02004000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]131 reg = <0x02004000 0x4000>;
132 interrupts = <0 52 0x04>;
133 };
134
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]135 ecspi1: ecspi@02008000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]136 #address-cells = <1>;
137 #size-cells = <0>;
138 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
139 reg = <0x02008000 0x4000>;
140 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]141 clocks = <&clks 112>, <&clks 112>;
142 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]143 status = "disabled";
144 };
145
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]146 ecspi2: ecspi@0200c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
150 reg = <0x0200c000 0x4000>;
151 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]152 clocks = <&clks 113>, <&clks 113>;
153 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]154 status = "disabled";
155 };
156
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]157 ecspi3: ecspi@02010000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
161 reg = <0x02010000 0x4000>;
162 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]163 clocks = <&clks 114>, <&clks 114>;
164 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]165 status = "disabled";
166 };
167
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]168 ecspi4: ecspi@02014000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]169 #address-cells = <1>;
170 #size-cells = <0>;
171 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
172 reg = <0x02014000 0x4000>;
173 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]174 clocks = <&clks 115>, <&clks 115>;
175 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]176 status = "disabled";
177 };
178
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]179 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]180 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
181 reg = <0x02020000 0x4000>;
182 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]183 clocks = <&clks 160>, <&clks 161>;
184 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]185 status = "disabled";
186 };
187
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]188 esai: esai@02024000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]189 reg = <0x02024000 0x4000>;
190 interrupts = <0 51 0x04>;
191 };
192
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]193 ssi1: ssi@02028000 {
194 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]195 reg = <0x02028000 0x4000>;
196 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]197 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]198 fsl,fifo-depth = <15>;
199 fsl,ssi-dma-events = <38 37>;
200 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]201 };
202
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]203 ssi2: ssi@0202c000 {
204 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]205 reg = <0x0202c000 0x4000>;
206 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]207 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]208 fsl,fifo-depth = <15>;
209 fsl,ssi-dma-events = <42 41>;
210 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]211 };
212
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]213 ssi3: ssi@02030000 {
214 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]215 reg = <0x02030000 0x4000>;
216 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]217 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]218 fsl,fifo-depth = <15>;
219 fsl,ssi-dma-events = <46 45>;
220 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]221 };
222
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]223 asrc: asrc@02034000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]224 reg = <0x02034000 0x4000>;
225 interrupts = <0 50 0x04>;
226 };
227
228 spba@0203c000 {
229 reg = <0x0203c000 0x4000>;
230 };
231 };
232
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]233 vpu: vpu@02040000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]234 reg = <0x02040000 0x3c000>;
235 interrupts = <0 3 0x04 0 12 0x04>;
236 };
237
238 aipstz@0207c000 { /* AIPSTZ1 */
239 reg = <0x0207c000 0x4000>;
240 };
241
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]242 pwm1: pwm@02080000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]243 #pwm-cells = <2>;
244 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]245 reg = <0x02080000 0x4000>;
246 interrupts = <0 83 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]247 clocks = <&clks 62>, <&clks 145>;
248 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]249 };
250
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]251 pwm2: pwm@02084000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]252 #pwm-cells = <2>;
253 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]254 reg = <0x02084000 0x4000>;
255 interrupts = <0 84 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]256 clocks = <&clks 62>, <&clks 146>;
257 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]258 };
259
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]260 pwm3: pwm@02088000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]261 #pwm-cells = <2>;
262 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]263 reg = <0x02088000 0x4000>;
264 interrupts = <0 85 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]265 clocks = <&clks 62>, <&clks 147>;
266 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]267 };
268
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]269 pwm4: pwm@0208c000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]270 #pwm-cells = <2>;
271 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]272 reg = <0x0208c000 0x4000>;
273 interrupts = <0 86 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]274 clocks = <&clks 62>, <&clks 148>;
275 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]276 };
277
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]278 can1: flexcan@02090000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]279 reg = <0x02090000 0x4000>;
280 interrupts = <0 110 0x04>;
281 };
282
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]283 can2: flexcan@02094000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]284 reg = <0x02094000 0x4000>;
285 interrupts = <0 111 0x04>;
286 };
287
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]288 gpt: gpt@02098000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]289 compatible = "fsl,imx6q-gpt";
290 reg = <0x02098000 0x4000>;
291 interrupts = <0 55 0x04>;
Sascha Hauer4efccad2013-03-14 13:09:01 +0100[diff] [blame]292 clocks = <&clks 119>, <&clks 120>;
293 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]294 };
295
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]296 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]297 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]298 reg = <0x0209c000 0x4000>;
299 interrupts = <0 66 0x04 0 67 0x04>;
300 gpio-controller;
301 #gpio-cells = <2>;
302 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]303 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]304 };
305
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]306 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]307 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]308 reg = <0x020a0000 0x4000>;
309 interrupts = <0 68 0x04 0 69 0x04>;
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]313 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]314 };
315
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]316 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]317 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]318 reg = <0x020a4000 0x4000>;
319 interrupts = <0 70 0x04 0 71 0x04>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]323 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]324 };
325
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]326 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]327 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]328 reg = <0x020a8000 0x4000>;
329 interrupts = <0 72 0x04 0 73 0x04>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]333 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]334 };
335
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]336 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]337 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]338 reg = <0x020ac000 0x4000>;
339 interrupts = <0 74 0x04 0 75 0x04>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]343 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]344 };
345
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]346 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]347 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]348 reg = <0x020b0000 0x4000>;
349 interrupts = <0 76 0x04 0 77 0x04>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]353 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]354 };
355
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]356 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]357 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]358 reg = <0x020b4000 0x4000>;
359 interrupts = <0 78 0x04 0 79 0x04>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]363 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]364 };
365
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]366 kpp: kpp@020b8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]367 reg = <0x020b8000 0x4000>;
368 interrupts = <0 82 0x04>;
369 };
370
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]371 wdog1: wdog@020bc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]372 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
373 reg = <0x020bc000 0x4000>;
374 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]375 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]376 };
377
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]378 wdog2: wdog@020c0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]379 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
380 reg = <0x020c0000 0x4000>;
381 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]382 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]383 status = "disabled";
384 };
385
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]386 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]387 compatible = "fsl,imx6q-ccm";
388 reg = <0x020c4000 0x4000>;
389 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]390 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]391 };
392
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]393 anatop: anatop@020c8000 {
394 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]395 reg = <0x020c8000 0x1000>;
396 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]397
398 regulator-1p1@110 {
399 compatible = "fsl,anatop-regulator";
400 regulator-name = "vdd1p1";
401 regulator-min-microvolt = <800000>;
402 regulator-max-microvolt = <1375000>;
403 regulator-always-on;
404 anatop-reg-offset = <0x110>;
405 anatop-vol-bit-shift = <8>;
406 anatop-vol-bit-width = <5>;
407 anatop-min-bit-val = <4>;
408 anatop-min-voltage = <800000>;
409 anatop-max-voltage = <1375000>;
410 };
411
412 regulator-3p0@120 {
413 compatible = "fsl,anatop-regulator";
414 regulator-name = "vdd3p0";
415 regulator-min-microvolt = <2800000>;
416 regulator-max-microvolt = <3150000>;
417 regulator-always-on;
418 anatop-reg-offset = <0x120>;
419 anatop-vol-bit-shift = <8>;
420 anatop-vol-bit-width = <5>;
421 anatop-min-bit-val = <0>;
422 anatop-min-voltage = <2625000>;
423 anatop-max-voltage = <3400000>;
424 };
425
426 regulator-2p5@130 {
427 compatible = "fsl,anatop-regulator";
428 regulator-name = "vdd2p5";
429 regulator-min-microvolt = <2000000>;
430 regulator-max-microvolt = <2750000>;
431 regulator-always-on;
432 anatop-reg-offset = <0x130>;
433 anatop-vol-bit-shift = <8>;
434 anatop-vol-bit-width = <5>;
435 anatop-min-bit-val = <0>;
436 anatop-min-voltage = <2000000>;
437 anatop-max-voltage = <2750000>;
438 };
439
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]440 reg_arm: regulator-vddcore@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]441 compatible = "fsl,anatop-regulator";
442 regulator-name = "cpu";
443 regulator-min-microvolt = <725000>;
444 regulator-max-microvolt = <1450000>;
445 regulator-always-on;
446 anatop-reg-offset = <0x140>;
447 anatop-vol-bit-shift = <0>;
448 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]449 anatop-delay-reg-offset = <0x170>;
450 anatop-delay-bit-shift = <24>;
451 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]452 anatop-min-bit-val = <1>;
453 anatop-min-voltage = <725000>;
454 anatop-max-voltage = <1450000>;
455 };
456
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]457 reg_pu: regulator-vddpu@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]458 compatible = "fsl,anatop-regulator";
459 regulator-name = "vddpu";
460 regulator-min-microvolt = <725000>;
461 regulator-max-microvolt = <1450000>;
462 regulator-always-on;
463 anatop-reg-offset = <0x140>;
464 anatop-vol-bit-shift = <9>;
465 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]466 anatop-delay-reg-offset = <0x170>;
467 anatop-delay-bit-shift = <26>;
468 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]469 anatop-min-bit-val = <1>;
470 anatop-min-voltage = <725000>;
471 anatop-max-voltage = <1450000>;
472 };
473
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]474 reg_soc: regulator-vddsoc@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]475 compatible = "fsl,anatop-regulator";
476 regulator-name = "vddsoc";
477 regulator-min-microvolt = <725000>;
478 regulator-max-microvolt = <1450000>;
479 regulator-always-on;
480 anatop-reg-offset = <0x140>;
481 anatop-vol-bit-shift = <18>;
482 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]483 anatop-delay-reg-offset = <0x170>;
484 anatop-delay-bit-shift = <28>;
485 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]486 anatop-min-bit-val = <1>;
487 anatop-min-voltage = <725000>;
488 anatop-max-voltage = <1450000>;
489 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]490 };
491
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]492 usbphy1: usbphy@020c9000 {
493 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]494 reg = <0x020c9000 0x1000>;
495 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]496 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]497 };
498
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]499 usbphy2: usbphy@020ca000 {
500 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]501 reg = <0x020ca000 0x1000>;
502 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]503 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]504 };
505
506 snvs@020cc000 {
Shawn Guoc9250382012-07-02 20:13:03 +0800[diff] [blame]507 compatible = "fsl,sec-v4.0-mon", "simple-bus";
508 #address-cells = <1>;
509 #size-cells = <1>;
510 ranges = <0 0x020cc000 0x4000>;
511
512 snvs-rtc-lp@34 {
513 compatible = "fsl,sec-v4.0-mon-rtc-lp";
514 reg = <0x34 0x58>;
515 interrupts = <0 19 0x04 0 20 0x04>;
516 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]517 };
518
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]519 epit1: epit@020d0000 { /* EPIT1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]520 reg = <0x020d0000 0x4000>;
521 interrupts = <0 56 0x04>;
522 };
523
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]524 epit2: epit@020d4000 { /* EPIT2 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]525 reg = <0x020d4000 0x4000>;
526 interrupts = <0 57 0x04>;
527 };
528
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]529 src: src@020d8000 {
Philipp Zabelbd3d9242013-03-28 17:35:22 +0100[diff] [blame]530 compatible = "fsl,imx6q-src", "fsl,imx51-src";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]531 reg = <0x020d8000 0x4000>;
532 interrupts = <0 91 0x04 0 96 0x04>;
Philipp Zabel09ebf362013-03-28 17:35:20 +0100[diff] [blame]533 #reset-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]534 };
535
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]536 gpc: gpc@020dc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]537 compatible = "fsl,imx6q-gpc";
538 reg = <0x020dc000 0x4000>;
539 interrupts = <0 89 0x04 0 90 0x04>;
540 };
541
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]542 gpr: iomuxc-gpr@020e0000 {
543 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
544 reg = <0x020e0000 0x38>;
545 };
546
Steffen Trumtrar41c04342013-03-28 16:23:35 +0100[diff] [blame]547 ldb: ldb@020e0008 {
548 #address-cells = <1>;
549 #size-cells = <0>;
550 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
551 gpr = <&gpr>;
552 status = "disabled";
553
554 lvds-channel@0 {
555 reg = <0>;
556 crtcs = <&ipu1 0>;
557 status = "disabled";
558 };
559
560 lvds-channel@1 {
561 reg = <1>;
562 crtcs = <&ipu1 1>;
563 status = "disabled";
564 };
565 };
566
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]567 dcic1: dcic@020e4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]568 reg = <0x020e4000 0x4000>;
569 interrupts = <0 124 0x04>;
570 };
571
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]572 dcic2: dcic@020e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]573 reg = <0x020e8000 0x4000>;
574 interrupts = <0 125 0x04>;
575 };
576
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]577 sdma: sdma@020ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]578 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
579 reg = <0x020ec000 0x4000>;
580 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]581 clocks = <&clks 155>, <&clks 155>;
582 clock-names = "ipg", "ahb";
Fabio Estevamd6b9c592013-01-17 12:13:25 -0200[diff] [blame]583 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]584 };
585 };
586
587 aips-bus@02100000 { /* AIPS2 */
588 compatible = "fsl,aips-bus", "simple-bus";
589 #address-cells = <1>;
590 #size-cells = <1>;
591 reg = <0x02100000 0x100000>;
592 ranges;
593
594 caam@02100000 {
595 reg = <0x02100000 0x40000>;
596 interrupts = <0 105 0x04 0 106 0x04>;
597 };
598
599 aipstz@0217c000 { /* AIPSTZ2 */
600 reg = <0x0217c000 0x4000>;
601 };
602
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]603 usbotg: usb@02184000 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]604 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
605 reg = <0x02184000 0x200>;
606 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]607 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]608 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]609 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]610 status = "disabled";
611 };
612
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]613 usbh1: usb@02184200 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]614 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
615 reg = <0x02184200 0x200>;
616 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]617 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]618 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]619 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]620 status = "disabled";
621 };
622
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]623 usbh2: usb@02184400 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]624 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
625 reg = <0x02184400 0x200>;
626 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]627 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]628 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]629 status = "disabled";
630 };
631
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]632 usbh3: usb@02184600 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]633 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
634 reg = <0x02184600 0x200>;
635 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]636 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]637 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]638 status = "disabled";
639 };
640
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]641 usbmisc: usbmisc: usbmisc@02184800 {
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]642 #index-cells = <1>;
643 compatible = "fsl,imx6q-usbmisc";
644 reg = <0x02184800 0x200>;
645 clocks = <&clks 162>;
646 };
647
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]648 fec: ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]649 compatible = "fsl,imx6q-fec";
650 reg = <0x02188000 0x4000>;
651 interrupts = <0 118 0x04 0 119 0x04>;
Frank Li8dd5c662013-02-05 14:21:06 +0800[diff] [blame]652 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame]653 clock-names = "ipg", "ahb", "ptp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]654 status = "disabled";
655 };
656
657 mlb@0218c000 {
658 reg = <0x0218c000 0x4000>;
659 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
660 };
661
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]662 usdhc1: usdhc@02190000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]663 compatible = "fsl,imx6q-usdhc";
664 reg = <0x02190000 0x4000>;
665 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]666 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
667 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]668 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]669 status = "disabled";
670 };
671
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]672 usdhc2: usdhc@02194000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]673 compatible = "fsl,imx6q-usdhc";
674 reg = <0x02194000 0x4000>;
675 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]676 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
677 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]678 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]679 status = "disabled";
680 };
681
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]682 usdhc3: usdhc@02198000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]683 compatible = "fsl,imx6q-usdhc";
684 reg = <0x02198000 0x4000>;
685 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]686 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
687 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]688 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]689 status = "disabled";
690 };
691
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]692 usdhc4: usdhc@0219c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]693 compatible = "fsl,imx6q-usdhc";
694 reg = <0x0219c000 0x4000>;
695 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]696 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
697 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]698 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]699 status = "disabled";
700 };
701
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]702 i2c1: i2c@021a0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]703 #address-cells = <1>;
704 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]705 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]706 reg = <0x021a0000 0x4000>;
707 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]708 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]709 status = "disabled";
710 };
711
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]712 i2c2: i2c@021a4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]713 #address-cells = <1>;
714 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]715 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]716 reg = <0x021a4000 0x4000>;
717 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]718 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]719 status = "disabled";
720 };
721
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]722 i2c3: i2c@021a8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]723 #address-cells = <1>;
724 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]725 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]726 reg = <0x021a8000 0x4000>;
727 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]728 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]729 status = "disabled";
730 };
731
732 romcp@021ac000 {
733 reg = <0x021ac000 0x4000>;
734 };
735
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]736 mmdc0: mmdc@021b0000 { /* MMDC0 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]737 compatible = "fsl,imx6q-mmdc";
738 reg = <0x021b0000 0x4000>;
739 };
740
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]741 mmdc1: mmdc@021b4000 { /* MMDC1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]742 reg = <0x021b4000 0x4000>;
743 };
744
745 weim@021b8000 {
746 reg = <0x021b8000 0x4000>;
747 interrupts = <0 14 0x04>;
748 };
749
750 ocotp@021bc000 {
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]751 compatible = "fsl,imx6q-ocotp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]752 reg = <0x021bc000 0x4000>;
753 };
754
755 ocotp@021c0000 {
756 reg = <0x021c0000 0x4000>;
757 interrupts = <0 21 0x04>;
758 };
759
760 tzasc@021d0000 { /* TZASC1 */
761 reg = <0x021d0000 0x4000>;
762 interrupts = <0 108 0x04>;
763 };
764
765 tzasc@021d4000 { /* TZASC2 */
766 reg = <0x021d4000 0x4000>;
767 interrupts = <0 109 0x04>;
768 };
769
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]770 audmux: audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]771 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]772 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]773 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]774 };
775
776 mipi@021dc000 { /* MIPI-CSI */
777 reg = <0x021dc000 0x4000>;
778 };
779
780 mipi@021e0000 { /* MIPI-DSI */
781 reg = <0x021e0000 0x4000>;
782 };
783
784 vdoa@021e4000 {
785 reg = <0x021e4000 0x4000>;
786 interrupts = <0 18 0x04>;
787 };
788
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]789 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]790 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
791 reg = <0x021e8000 0x4000>;
792 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]793 clocks = <&clks 160>, <&clks 161>;
794 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]795 status = "disabled";
796 };
797
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]798 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]799 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
800 reg = <0x021ec000 0x4000>;
801 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]802 clocks = <&clks 160>, <&clks 161>;
803 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]804 status = "disabled";
805 };
806
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]807 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]808 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
809 reg = <0x021f0000 0x4000>;
810 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]811 clocks = <&clks 160>, <&clks 161>;
812 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]813 status = "disabled";
814 };
815
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]816 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]817 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
818 reg = <0x021f4000 0x4000>;
819 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]820 clocks = <&clks 160>, <&clks 161>;
821 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]822 status = "disabled";
823 };
824 };
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]825
826 ipu1: ipu@02400000 {
827 #crtc-cells = <1>;
828 compatible = "fsl,imx6q-ipu";
829 reg = <0x02400000 0x400000>;
830 interrupts = <0 6 0x4 0 5 0x4>;
831 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
832 clock-names = "bus", "di0", "di1";
Philipp Zabel09ebf362013-03-28 17:35:20 +0100[diff] [blame]833 resets = <&src 2>;
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]834 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]835 };
836};