blob: 75a29a3822089da48ecb37e179ce7b4050853ce1 [file] [log] [blame]
Daniel Vetter76aaf222010-11-05 22:23:30 +01001/*
2 * Copyright © 2010 Daniel Vetter
Ben Widawskyc4ac5242014-02-19 22:05:47 -08003 * Copyright © 2011-2014 Intel Corporation
Daniel Vetter76aaf222010-11-05 22:23:30 +01004 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
Daniel Vetter0e46ce22014-01-08 16:10:27 +010026#include <linux/seq_file.h>
David Howells760285e2012-10-02 18:01:07 +010027#include <drm/drmP.h>
28#include <drm/i915_drm.h>
Daniel Vetter76aaf222010-11-05 22:23:30 +010029#include "i915_drv.h"
30#include "i915_trace.h"
31#include "intel_drv.h"
32
Tvrtko Ursulin45f8f692014-12-10 17:27:59 +000033/**
34 * DOC: Global GTT views
35 *
36 * Background and previous state
37 *
38 * Historically objects could exists (be bound) in global GTT space only as
39 * singular instances with a view representing all of the object's backing pages
40 * in a linear fashion. This view will be called a normal view.
41 *
42 * To support multiple views of the same object, where the number of mapped
43 * pages is not equal to the backing store, or where the layout of the pages
44 * is not linear, concept of a GGTT view was added.
45 *
46 * One example of an alternative view is a stereo display driven by a single
47 * image. In this case we would have a framebuffer looking like this
48 * (2x2 pages):
49 *
50 * 12
51 * 34
52 *
53 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
54 * rendering. In contrast, fed to the display engine would be an alternative
55 * view which could look something like this:
56 *
57 * 1212
58 * 3434
59 *
60 * In this example both the size and layout of pages in the alternative view is
61 * different from the normal view.
62 *
63 * Implementation and usage
64 *
65 * GGTT views are implemented using VMAs and are distinguished via enum
66 * i915_ggtt_view_type and struct i915_ggtt_view.
67 *
68 * A new flavour of core GEM functions which work with GGTT bound objects were
69 * added with the _view suffix. They take the struct i915_ggtt_view parameter
70 * encapsulating all metadata required to implement a view.
71 *
72 * As a helper for callers which are only interested in the normal view,
73 * globally const i915_ggtt_view_normal singleton instance exists. All old core
74 * GEM API functions, the ones not taking the view parameter, are operating on,
75 * or with the normal GGTT view.
76 *
77 * Code wanting to add or use a new GGTT view needs to:
78 *
79 * 1. Add a new enum with a suitable name.
80 * 2. Extend the metadata in the i915_ggtt_view structure if required.
81 * 3. Add support to i915_get_vma_pages().
82 *
83 * New views are required to build a scatter-gather table from within the
84 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
85 * exists for the lifetime of an VMA.
86 *
87 * Core API is designed to have copy semantics which means that passed in
88 * struct i915_ggtt_view does not need to be persistent (left around after
89 * calling the core API functions).
90 *
91 */
92
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +000093const struct i915_ggtt_view i915_ggtt_view_normal;
94
Ville Syrjäläee0ce472014-04-09 13:28:01 +030095static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
96static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
Ben Widawskya2319c02014-03-18 16:09:37 -070097
Daniel Vettercfa7c862014-04-29 11:53:58 +020098static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
99{
Chris Wilson1893a712014-09-19 11:56:27 +0100100 bool has_aliasing_ppgtt;
101 bool has_full_ppgtt;
102
103 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
104 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
Chris Wilson1893a712014-09-19 11:56:27 +0100105
Damien Lespiau70ee45e2014-11-14 15:05:59 +0000106 /*
107 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
108 * execlists, the sole mechanism available to submit work.
109 */
110 if (INTEL_INFO(dev)->gen < 9 &&
111 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
Daniel Vettercfa7c862014-04-29 11:53:58 +0200112 return 0;
113
114 if (enable_ppgtt == 1)
115 return 1;
116
Chris Wilson1893a712014-09-19 11:56:27 +0100117 if (enable_ppgtt == 2 && has_full_ppgtt)
Daniel Vettercfa7c862014-04-29 11:53:58 +0200118 return 2;
119
Daniel Vetter93a25a92014-03-06 09:40:43 +0100120#ifdef CONFIG_INTEL_IOMMU
121 /* Disable ppgtt on SNB if VT-d is on. */
122 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
123 DRM_INFO("Disabling PPGTT because VT-d is on\n");
Daniel Vettercfa7c862014-04-29 11:53:58 +0200124 return 0;
Daniel Vetter93a25a92014-03-06 09:40:43 +0100125 }
126#endif
127
Jesse Barnes62942ed2014-06-13 09:28:33 -0700128 /* Early VLV doesn't have this */
Ville Syrjäläca2aed6c2014-06-28 02:03:56 +0300129 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
130 dev->pdev->revision < 0xb) {
Jesse Barnes62942ed2014-06-13 09:28:33 -0700131 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
132 return 0;
133 }
134
Michel Thierry2f82bbd2014-12-15 14:58:00 +0000135 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
136 return 2;
137 else
138 return has_aliasing_ppgtt ? 1 : 0;
Daniel Vetter93a25a92014-03-06 09:40:43 +0100139}
140
Ben Widawskyfbe5d362013-11-04 19:56:49 -0800141
Ben Widawsky6f65e292013-12-06 14:10:56 -0800142static void ppgtt_bind_vma(struct i915_vma *vma,
143 enum i915_cache_level cache_level,
144 u32 flags);
145static void ppgtt_unbind_vma(struct i915_vma *vma);
146
Ben Widawsky94ec8f62013-11-02 21:07:18 -0700147static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
148 enum i915_cache_level level,
149 bool valid)
150{
151 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
152 pte |= addr;
Ben Widawsky63c42e52014-04-18 18:04:27 -0300153
154 switch (level) {
155 case I915_CACHE_NONE:
Ben Widawskyfbe5d362013-11-04 19:56:49 -0800156 pte |= PPAT_UNCACHED_INDEX;
Ben Widawsky63c42e52014-04-18 18:04:27 -0300157 break;
158 case I915_CACHE_WT:
159 pte |= PPAT_DISPLAY_ELLC_INDEX;
160 break;
161 default:
162 pte |= PPAT_CACHED_INDEX;
163 break;
164 }
165
Ben Widawsky94ec8f62013-11-02 21:07:18 -0700166 return pte;
167}
168
Ben Widawskyb1fe6672013-11-04 21:20:14 -0800169static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
170 dma_addr_t addr,
171 enum i915_cache_level level)
172{
173 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
174 pde |= addr;
175 if (level != I915_CACHE_NONE)
176 pde |= PPAT_CACHED_PDE_INDEX;
177 else
178 pde |= PPAT_UNCACHED_INDEX;
179 return pde;
180}
181
Chris Wilson350ec882013-08-06 13:17:02 +0100182static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
Ben Widawskyb35b3802013-10-16 09:18:21 -0700183 enum i915_cache_level level,
Akash Goel24f3a8c2014-06-17 10:59:42 +0530184 bool valid, u32 unused)
Ben Widawsky54d12522012-09-24 16:44:32 -0700185{
Ben Widawskyb35b3802013-10-16 09:18:21 -0700186 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Ben Widawsky54d12522012-09-24 16:44:32 -0700187 pte |= GEN6_PTE_ADDR_ENCODE(addr);
Ben Widawskye7210c32012-10-19 09:33:22 -0700188
189 switch (level) {
Chris Wilson350ec882013-08-06 13:17:02 +0100190 case I915_CACHE_L3_LLC:
191 case I915_CACHE_LLC:
192 pte |= GEN6_PTE_CACHE_LLC;
193 break;
194 case I915_CACHE_NONE:
195 pte |= GEN6_PTE_UNCACHED;
196 break;
197 default:
Daniel Vetter5f77eeb2014-12-08 16:40:10 +0100198 MISSING_CASE(level);
Chris Wilson350ec882013-08-06 13:17:02 +0100199 }
200
201 return pte;
202}
203
204static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
Ben Widawskyb35b3802013-10-16 09:18:21 -0700205 enum i915_cache_level level,
Akash Goel24f3a8c2014-06-17 10:59:42 +0530206 bool valid, u32 unused)
Chris Wilson350ec882013-08-06 13:17:02 +0100207{
Ben Widawskyb35b3802013-10-16 09:18:21 -0700208 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Chris Wilson350ec882013-08-06 13:17:02 +0100209 pte |= GEN6_PTE_ADDR_ENCODE(addr);
210
211 switch (level) {
212 case I915_CACHE_L3_LLC:
213 pte |= GEN7_PTE_CACHE_L3_LLC;
Ben Widawskye7210c32012-10-19 09:33:22 -0700214 break;
215 case I915_CACHE_LLC:
216 pte |= GEN6_PTE_CACHE_LLC;
217 break;
218 case I915_CACHE_NONE:
Kenneth Graunke91197082013-04-22 00:53:51 -0700219 pte |= GEN6_PTE_UNCACHED;
Ben Widawskye7210c32012-10-19 09:33:22 -0700220 break;
221 default:
Daniel Vetter5f77eeb2014-12-08 16:40:10 +0100222 MISSING_CASE(level);
Ben Widawskye7210c32012-10-19 09:33:22 -0700223 }
224
Ben Widawsky54d12522012-09-24 16:44:32 -0700225 return pte;
226}
227
Ben Widawsky80a74f72013-06-27 16:30:19 -0700228static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
Ben Widawskyb35b3802013-10-16 09:18:21 -0700229 enum i915_cache_level level,
Akash Goel24f3a8c2014-06-17 10:59:42 +0530230 bool valid, u32 flags)
Kenneth Graunke93c34e72013-04-22 00:53:50 -0700231{
Ben Widawskyb35b3802013-10-16 09:18:21 -0700232 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Kenneth Graunke93c34e72013-04-22 00:53:50 -0700233 pte |= GEN6_PTE_ADDR_ENCODE(addr);
234
Akash Goel24f3a8c2014-06-17 10:59:42 +0530235 if (!(flags & PTE_READ_ONLY))
236 pte |= BYT_PTE_WRITEABLE;
Kenneth Graunke93c34e72013-04-22 00:53:50 -0700237
238 if (level != I915_CACHE_NONE)
239 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
240
241 return pte;
242}
243
Ben Widawsky80a74f72013-06-27 16:30:19 -0700244static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
Ben Widawskyb35b3802013-10-16 09:18:21 -0700245 enum i915_cache_level level,
Akash Goel24f3a8c2014-06-17 10:59:42 +0530246 bool valid, u32 unused)
Kenneth Graunke91197082013-04-22 00:53:51 -0700247{
Ben Widawskyb35b3802013-10-16 09:18:21 -0700248 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Ben Widawsky0d8ff152013-07-04 11:02:03 -0700249 pte |= HSW_PTE_ADDR_ENCODE(addr);
Kenneth Graunke91197082013-04-22 00:53:51 -0700250
251 if (level != I915_CACHE_NONE)
Ben Widawsky87a6b682013-08-04 23:47:29 -0700252 pte |= HSW_WB_LLC_AGE3;
Kenneth Graunke91197082013-04-22 00:53:51 -0700253
254 return pte;
255}
256
Ben Widawsky4d15c142013-07-04 11:02:06 -0700257static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
Ben Widawskyb35b3802013-10-16 09:18:21 -0700258 enum i915_cache_level level,
Akash Goel24f3a8c2014-06-17 10:59:42 +0530259 bool valid, u32 unused)
Ben Widawsky4d15c142013-07-04 11:02:06 -0700260{
Ben Widawskyb35b3802013-10-16 09:18:21 -0700261 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Ben Widawsky4d15c142013-07-04 11:02:06 -0700262 pte |= HSW_PTE_ADDR_ENCODE(addr);
263
Chris Wilson651d7942013-08-08 14:41:10 +0100264 switch (level) {
265 case I915_CACHE_NONE:
266 break;
267 case I915_CACHE_WT:
Chris Wilsonc51e9702013-11-22 10:37:53 +0000268 pte |= HSW_WT_ELLC_LLC_AGE3;
Chris Wilson651d7942013-08-08 14:41:10 +0100269 break;
270 default:
Chris Wilsonc51e9702013-11-22 10:37:53 +0000271 pte |= HSW_WB_ELLC_LLC_AGE3;
Chris Wilson651d7942013-08-08 14:41:10 +0100272 break;
273 }
Ben Widawsky4d15c142013-07-04 11:02:06 -0700274
275 return pte;
276}
277
Ben Widawsky94e409c2013-11-04 22:29:36 -0800278/* Broadwell Page Directory Pointer Descriptors */
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100279static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
McAulay, Alistair6689c162014-08-15 18:51:35 +0100280 uint64_t val)
Ben Widawsky94e409c2013-11-04 22:29:36 -0800281{
282 int ret;
283
284 BUG_ON(entry >= 4);
285
286 ret = intel_ring_begin(ring, 6);
287 if (ret)
288 return ret;
289
290 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
291 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
292 intel_ring_emit(ring, (u32)(val >> 32));
293 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
294 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
295 intel_ring_emit(ring, (u32)(val));
296 intel_ring_advance(ring);
297
298 return 0;
299}
300
Ben Widawskyeeb94882013-12-06 14:11:10 -0800301static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
McAulay, Alistair6689c162014-08-15 18:51:35 +0100302 struct intel_engine_cs *ring)
Ben Widawsky94e409c2013-11-04 22:29:36 -0800303{
Ben Widawskyeeb94882013-12-06 14:11:10 -0800304 int i, ret;
Ben Widawsky94e409c2013-11-04 22:29:36 -0800305
306 /* bit of a hack to find the actual last used pd */
307 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
308
Ben Widawsky94e409c2013-11-04 22:29:36 -0800309 for (i = used_pd - 1; i >= 0; i--) {
310 dma_addr_t addr = ppgtt->pd_dma_addr[i];
McAulay, Alistair6689c162014-08-15 18:51:35 +0100311 ret = gen8_write_pdp(ring, i, addr);
Ben Widawskyeeb94882013-12-06 14:11:10 -0800312 if (ret)
313 return ret;
Ben Widawsky94e409c2013-11-04 22:29:36 -0800314 }
Ben Widawskyd595bd42013-11-25 09:54:32 -0800315
Ben Widawskyeeb94882013-12-06 14:11:10 -0800316 return 0;
Ben Widawsky94e409c2013-11-04 22:29:36 -0800317}
318
Ben Widawsky459108b2013-11-02 21:07:23 -0700319static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -0800320 uint64_t start,
321 uint64_t length,
Ben Widawsky459108b2013-11-02 21:07:23 -0700322 bool use_scratch)
323{
324 struct i915_hw_ppgtt *ppgtt =
325 container_of(vm, struct i915_hw_ppgtt, base);
326 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800327 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
328 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
329 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
Ben Widawsky782f1492014-02-20 11:50:33 -0800330 unsigned num_entries = length >> PAGE_SHIFT;
Ben Widawsky459108b2013-11-02 21:07:23 -0700331 unsigned last_pte, i;
332
333 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
334 I915_CACHE_LLC, use_scratch);
335
336 while (num_entries) {
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800337 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
Ben Widawsky459108b2013-11-02 21:07:23 -0700338
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800339 last_pte = pte + num_entries;
Ben Widawsky459108b2013-11-02 21:07:23 -0700340 if (last_pte > GEN8_PTES_PER_PAGE)
341 last_pte = GEN8_PTES_PER_PAGE;
342
343 pt_vaddr = kmap_atomic(page_table);
344
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800345 for (i = pte; i < last_pte; i++) {
Ben Widawsky459108b2013-11-02 21:07:23 -0700346 pt_vaddr[i] = scratch_pte;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800347 num_entries--;
348 }
Ben Widawsky459108b2013-11-02 21:07:23 -0700349
Rafael Barbalhofd1ab8f2014-04-09 13:28:02 +0300350 if (!HAS_LLC(ppgtt->base.dev))
351 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
Ben Widawsky459108b2013-11-02 21:07:23 -0700352 kunmap_atomic(pt_vaddr);
353
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800354 pte = 0;
355 if (++pde == GEN8_PDES_PER_PAGE) {
356 pdpe++;
357 pde = 0;
358 }
Ben Widawsky459108b2013-11-02 21:07:23 -0700359 }
360}
361
Ben Widawsky9df15b42013-11-02 21:07:24 -0700362static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
363 struct sg_table *pages,
Ben Widawsky782f1492014-02-20 11:50:33 -0800364 uint64_t start,
Akash Goel24f3a8c2014-06-17 10:59:42 +0530365 enum i915_cache_level cache_level, u32 unused)
Ben Widawsky9df15b42013-11-02 21:07:24 -0700366{
367 struct i915_hw_ppgtt *ppgtt =
368 container_of(vm, struct i915_hw_ppgtt, base);
369 gen8_gtt_pte_t *pt_vaddr;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800370 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
371 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
372 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
Ben Widawsky9df15b42013-11-02 21:07:24 -0700373 struct sg_page_iter sg_iter;
374
Chris Wilson6f1cc992013-12-31 15:50:31 +0000375 pt_vaddr = NULL;
Ben Widawsky9df15b42013-11-02 21:07:24 -0700376
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800377 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
378 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
379 break;
380
381 if (pt_vaddr == NULL)
382 pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
383
384 pt_vaddr[pte] =
Chris Wilson6f1cc992013-12-31 15:50:31 +0000385 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
386 cache_level, true);
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800387 if (++pte == GEN8_PTES_PER_PAGE) {
Rafael Barbalhofd1ab8f2014-04-09 13:28:02 +0300388 if (!HAS_LLC(ppgtt->base.dev))
389 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
Ben Widawsky9df15b42013-11-02 21:07:24 -0700390 kunmap_atomic(pt_vaddr);
Chris Wilson6f1cc992013-12-31 15:50:31 +0000391 pt_vaddr = NULL;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800392 if (++pde == GEN8_PDES_PER_PAGE) {
393 pdpe++;
394 pde = 0;
395 }
396 pte = 0;
Ben Widawsky9df15b42013-11-02 21:07:24 -0700397 }
398 }
Rafael Barbalhofd1ab8f2014-04-09 13:28:02 +0300399 if (pt_vaddr) {
400 if (!HAS_LLC(ppgtt->base.dev))
401 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
Chris Wilson6f1cc992013-12-31 15:50:31 +0000402 kunmap_atomic(pt_vaddr);
Rafael Barbalhofd1ab8f2014-04-09 13:28:02 +0300403 }
Ben Widawsky9df15b42013-11-02 21:07:24 -0700404}
405
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800406static void gen8_free_page_tables(struct page **pt_pages)
Ben Widawskyb45a6712014-02-12 14:28:44 -0800407{
408 int i;
409
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800410 if (pt_pages == NULL)
411 return;
Ben Widawskyb45a6712014-02-12 14:28:44 -0800412
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800413 for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
414 if (pt_pages[i])
415 __free_pages(pt_pages[i], 0);
416}
417
418static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
419{
420 int i;
421
422 for (i = 0; i < ppgtt->num_pd_pages; i++) {
423 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
424 kfree(ppgtt->gen8_pt_pages[i]);
425 kfree(ppgtt->gen8_pt_dma_addr[i]);
426 }
427
Ben Widawskyb45a6712014-02-12 14:28:44 -0800428 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
429}
430
431static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
432{
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800433 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
Ben Widawskyb45a6712014-02-12 14:28:44 -0800434 int i, j;
435
436 for (i = 0; i < ppgtt->num_pd_pages; i++) {
437 /* TODO: In the future we'll support sparse mappings, so this
438 * will have to change. */
439 if (!ppgtt->pd_dma_addr[i])
440 continue;
441
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800442 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
443 PCI_DMA_BIDIRECTIONAL);
Ben Widawskyb45a6712014-02-12 14:28:44 -0800444
445 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
446 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
447 if (addr)
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800448 pci_unmap_page(hwdev, addr, PAGE_SIZE,
449 PCI_DMA_BIDIRECTIONAL);
Ben Widawskyb45a6712014-02-12 14:28:44 -0800450 }
451 }
452}
453
Ben Widawsky37aca442013-11-04 20:47:32 -0800454static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
455{
456 struct i915_hw_ppgtt *ppgtt =
457 container_of(vm, struct i915_hw_ppgtt, base);
Ben Widawsky37aca442013-11-04 20:47:32 -0800458
Ben Widawskyb45a6712014-02-12 14:28:44 -0800459 gen8_ppgtt_unmap_pages(ppgtt);
460 gen8_ppgtt_free(ppgtt);
Ben Widawsky37aca442013-11-04 20:47:32 -0800461}
462
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800463static struct page **__gen8_alloc_page_tables(void)
464{
465 struct page **pt_pages;
466 int i;
467
468 pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
469 if (!pt_pages)
470 return ERR_PTR(-ENOMEM);
471
472 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
473 pt_pages[i] = alloc_page(GFP_KERNEL);
474 if (!pt_pages[i])
475 goto bail;
476 }
477
478 return pt_pages;
479
480bail:
481 gen8_free_page_tables(pt_pages);
482 kfree(pt_pages);
483 return ERR_PTR(-ENOMEM);
484}
485
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800486static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
487 const int max_pdp)
488{
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800489 struct page **pt_pages[GEN8_LEGACY_PDPS];
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800490 int i, ret;
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800491
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800492 for (i = 0; i < max_pdp; i++) {
493 pt_pages[i] = __gen8_alloc_page_tables();
494 if (IS_ERR(pt_pages[i])) {
495 ret = PTR_ERR(pt_pages[i]);
496 goto unwind_out;
497 }
498 }
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800499
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800500 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
501 * "atomic" - for cleanup purposes.
502 */
503 for (i = 0; i < max_pdp; i++)
504 ppgtt->gen8_pt_pages[i] = pt_pages[i];
505
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800506 return 0;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800507
508unwind_out:
509 while (i--) {
510 gen8_free_page_tables(pt_pages[i]);
511 kfree(pt_pages[i]);
512 }
513
514 return ret;
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800515}
516
517static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
518{
519 int i;
520
521 for (i = 0; i < ppgtt->num_pd_pages; i++) {
522 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
523 sizeof(dma_addr_t),
524 GFP_KERNEL);
525 if (!ppgtt->gen8_pt_dma_addr[i])
526 return -ENOMEM;
527 }
528
529 return 0;
530}
531
532static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
533 const int max_pdp)
534{
535 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
536 if (!ppgtt->pd_pages)
537 return -ENOMEM;
538
539 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
540 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
541
542 return 0;
543}
544
545static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
546 const int max_pdp)
547{
548 int ret;
549
550 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
551 if (ret)
552 return ret;
553
554 ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
555 if (ret) {
556 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
557 return ret;
558 }
559
560 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
561
562 ret = gen8_ppgtt_allocate_dma(ppgtt);
563 if (ret)
564 gen8_ppgtt_free(ppgtt);
565
566 return ret;
567}
568
569static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
570 const int pd)
571{
572 dma_addr_t pd_addr;
573 int ret;
574
575 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
576 &ppgtt->pd_pages[pd], 0,
577 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
578
579 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
580 if (ret)
581 return ret;
582
583 ppgtt->pd_dma_addr[pd] = pd_addr;
584
585 return 0;
586}
587
588static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
589 const int pd,
590 const int pt)
591{
592 dma_addr_t pt_addr;
593 struct page *p;
594 int ret;
595
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800596 p = ppgtt->gen8_pt_pages[pd][pt];
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800597 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
598 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
599 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
600 if (ret)
601 return ret;
602
603 ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
604
605 return 0;
606}
607
Ben Widawsky37aca442013-11-04 20:47:32 -0800608/**
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800609 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
610 * with a net effect resembling a 2-level page table in normal x86 terms. Each
611 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
612 * space.
Ben Widawsky37aca442013-11-04 20:47:32 -0800613 *
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800614 * FIXME: split allocation into smaller pieces. For now we only ever do this
615 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
Ben Widawsky37aca442013-11-04 20:47:32 -0800616 * TODO: Do something with the size parameter
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800617 */
Ben Widawsky37aca442013-11-04 20:47:32 -0800618static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
619{
Ben Widawsky37aca442013-11-04 20:47:32 -0800620 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800621 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800622 int i, j, ret;
Ben Widawsky37aca442013-11-04 20:47:32 -0800623
624 if (size % (1<<30))
625 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
626
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800627 /* 1. Do all our allocations for page directories and page tables. */
628 ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
629 if (ret)
630 return ret;
Ben Widawsky37aca442013-11-04 20:47:32 -0800631
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800632 /*
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800633 * 2. Create DMA mappings for the page directories and page tables.
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800634 */
635 for (i = 0; i < max_pdp; i++) {
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800636 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800637 if (ret)
638 goto bail;
639
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800640 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800641 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800642 if (ret)
643 goto bail;
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800644 }
645 }
646
647 /*
648 * 3. Map all the page directory entires to point to the page tables
649 * we've allocated.
650 *
651 * For now, the PPGTT helper functions all require that the PDEs are
Ben Widawskyb1fe6672013-11-04 21:20:14 -0800652 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800653 * will never need to touch the PDEs again.
654 */
Ben Widawskyb1fe6672013-11-04 21:20:14 -0800655 for (i = 0; i < max_pdp; i++) {
656 gen8_ppgtt_pde_t *pd_vaddr;
657 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
658 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
659 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
660 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
661 I915_CACHE_LLC);
662 }
Rafael Barbalhofd1ab8f2014-04-09 13:28:02 +0300663 if (!HAS_LLC(ppgtt->base.dev))
664 drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
Ben Widawskyb1fe6672013-11-04 21:20:14 -0800665 kunmap_atomic(pd_vaddr);
666 }
667
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800668 ppgtt->switch_mm = gen8_mm_switch;
669 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
670 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
671 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
672 ppgtt->base.start = 0;
Ben Widawsky5abbcca2014-02-21 13:06:34 -0800673 ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800674
Ben Widawsky5abbcca2014-02-21 13:06:34 -0800675 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
Ben Widawsky459108b2013-11-02 21:07:23 -0700676
Ben Widawsky37aca442013-11-04 20:47:32 -0800677 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
678 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
679 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
Ben Widawsky5abbcca2014-02-21 13:06:34 -0800680 ppgtt->num_pd_entries,
681 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
Ben Widawsky28cf5412013-11-02 21:07:26 -0700682 return 0;
Ben Widawsky37aca442013-11-04 20:47:32 -0800683
Ben Widawskyf3a964b2014-02-19 22:05:42 -0800684bail:
685 gen8_ppgtt_unmap_pages(ppgtt);
686 gen8_ppgtt_free(ppgtt);
Ben Widawsky37aca442013-11-04 20:47:32 -0800687 return ret;
688}
689
Ben Widawsky87d60b62013-12-06 14:11:29 -0800690static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
691{
692 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
693 struct i915_address_space *vm = &ppgtt->base;
694 gen6_gtt_pte_t __iomem *pd_addr;
695 gen6_gtt_pte_t scratch_pte;
696 uint32_t pd_entry;
697 int pte, pde;
698
Akash Goel24f3a8c2014-06-17 10:59:42 +0530699 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
Ben Widawsky87d60b62013-12-06 14:11:29 -0800700
701 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
702 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
703
704 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
705 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
706 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
707 u32 expected;
708 gen6_gtt_pte_t *pt_vaddr;
709 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
710 pd_entry = readl(pd_addr + pde);
711 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
712
713 if (pd_entry != expected)
714 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
715 pde,
716 pd_entry,
717 expected);
718 seq_printf(m, "\tPDE: %x\n", pd_entry);
719
720 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
721 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
722 unsigned long va =
723 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
724 (pte * PAGE_SIZE);
725 int i;
726 bool found = false;
727 for (i = 0; i < 4; i++)
728 if (pt_vaddr[pte + i] != scratch_pte)
729 found = true;
730 if (!found)
731 continue;
732
733 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
734 for (i = 0; i < 4; i++) {
735 if (pt_vaddr[pte + i] != scratch_pte)
736 seq_printf(m, " %08x", pt_vaddr[pte + i]);
737 else
738 seq_puts(m, " SCRATCH ");
739 }
740 seq_puts(m, "\n");
741 }
742 kunmap_atomic(pt_vaddr);
743 }
744}
745
Ben Widawsky3e302542013-04-23 23:15:32 -0700746static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
Ben Widawsky61973492013-04-08 18:43:54 -0700747{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700748 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
Ben Widawsky61973492013-04-08 18:43:54 -0700749 gen6_gtt_pte_t __iomem *pd_addr;
750 uint32_t pd_entry;
751 int i;
752
Ben Widawsky0a732872013-04-23 23:15:30 -0700753 WARN_ON(ppgtt->pd_offset & 0x3f);
Ben Widawsky61973492013-04-08 18:43:54 -0700754 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
755 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
756 for (i = 0; i < ppgtt->num_pd_entries; i++) {
757 dma_addr_t pt_addr;
758
759 pt_addr = ppgtt->pt_dma_addr[i];
760 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
761 pd_entry |= GEN6_PDE_VALID;
762
763 writel(pd_entry, pd_addr + i);
764 }
765 readl(pd_addr);
Ben Widawsky3e302542013-04-23 23:15:32 -0700766}
767
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800768static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
Ben Widawsky3e302542013-04-23 23:15:32 -0700769{
Ben Widawsky3e302542013-04-23 23:15:32 -0700770 BUG_ON(ppgtt->pd_offset & 0x3f);
771
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800772 return (ppgtt->pd_offset / 64) << 16;
773}
Ben Widawsky61973492013-04-08 18:43:54 -0700774
Ben Widawsky90252e52013-12-06 14:11:12 -0800775static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
McAulay, Alistair6689c162014-08-15 18:51:35 +0100776 struct intel_engine_cs *ring)
Ben Widawsky90252e52013-12-06 14:11:12 -0800777{
Ben Widawsky90252e52013-12-06 14:11:12 -0800778 int ret;
Ben Widawsky61973492013-04-08 18:43:54 -0700779
Ben Widawsky90252e52013-12-06 14:11:12 -0800780 /* NB: TLBs must be flushed and invalidated before a switch */
781 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
782 if (ret)
783 return ret;
784
785 ret = intel_ring_begin(ring, 6);
786 if (ret)
787 return ret;
788
789 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
790 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
791 intel_ring_emit(ring, PP_DIR_DCLV_2G);
792 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
793 intel_ring_emit(ring, get_pd_offset(ppgtt));
794 intel_ring_emit(ring, MI_NOOP);
795 intel_ring_advance(ring);
796
797 return 0;
798}
799
Ben Widawsky48a10382013-12-06 14:11:11 -0800800static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
McAulay, Alistair6689c162014-08-15 18:51:35 +0100801 struct intel_engine_cs *ring)
Ben Widawsky48a10382013-12-06 14:11:11 -0800802{
Ben Widawsky48a10382013-12-06 14:11:11 -0800803 int ret;
804
Ben Widawsky48a10382013-12-06 14:11:11 -0800805 /* NB: TLBs must be flushed and invalidated before a switch */
806 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
807 if (ret)
808 return ret;
809
810 ret = intel_ring_begin(ring, 6);
811 if (ret)
812 return ret;
813
814 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
815 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
816 intel_ring_emit(ring, PP_DIR_DCLV_2G);
817 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
818 intel_ring_emit(ring, get_pd_offset(ppgtt));
819 intel_ring_emit(ring, MI_NOOP);
820 intel_ring_advance(ring);
821
Ben Widawsky90252e52013-12-06 14:11:12 -0800822 /* XXX: RCS is the only one to auto invalidate the TLBs? */
823 if (ring->id != RCS) {
824 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
825 if (ret)
826 return ret;
827 }
828
Ben Widawsky48a10382013-12-06 14:11:11 -0800829 return 0;
830}
831
Ben Widawskyeeb94882013-12-06 14:11:10 -0800832static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
McAulay, Alistair6689c162014-08-15 18:51:35 +0100833 struct intel_engine_cs *ring)
Ben Widawskyeeb94882013-12-06 14:11:10 -0800834{
835 struct drm_device *dev = ppgtt->base.dev;
836 struct drm_i915_private *dev_priv = dev->dev_private;
837
Ben Widawsky48a10382013-12-06 14:11:11 -0800838
Ben Widawskyeeb94882013-12-06 14:11:10 -0800839 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
840 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
841
842 POSTING_READ(RING_PP_DIR_DCLV(ring));
843
844 return 0;
845}
846
Daniel Vetter82460d92014-08-06 20:19:53 +0200847static void gen8_ppgtt_enable(struct drm_device *dev)
Ben Widawskyeeb94882013-12-06 14:11:10 -0800848{
Ben Widawskyeeb94882013-12-06 14:11:10 -0800849 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100850 struct intel_engine_cs *ring;
Daniel Vetter82460d92014-08-06 20:19:53 +0200851 int j;
Ben Widawskyeeb94882013-12-06 14:11:10 -0800852
853 for_each_ring(ring, dev_priv, j) {
854 I915_WRITE(RING_MODE_GEN7(ring),
855 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
Ben Widawskyeeb94882013-12-06 14:11:10 -0800856 }
Ben Widawskyeeb94882013-12-06 14:11:10 -0800857}
858
Daniel Vetter82460d92014-08-06 20:19:53 +0200859static void gen7_ppgtt_enable(struct drm_device *dev)
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800860{
Jani Nikula50227e12014-03-31 14:27:21 +0300861 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100862 struct intel_engine_cs *ring;
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800863 uint32_t ecochk, ecobits;
864 int i;
865
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800866 ecobits = I915_READ(GAC_ECO_BITS);
867 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
868
869 ecochk = I915_READ(GAM_ECOCHK);
870 if (IS_HASWELL(dev)) {
871 ecochk |= ECOCHK_PPGTT_WB_HSW;
872 } else {
873 ecochk |= ECOCHK_PPGTT_LLC_IVB;
874 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
875 }
876 I915_WRITE(GAM_ECOCHK, ecochk);
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800877
Ben Widawsky61973492013-04-08 18:43:54 -0700878 for_each_ring(ring, dev_priv, i) {
Ben Widawskyeeb94882013-12-06 14:11:10 -0800879 /* GFX_MODE is per-ring on gen7+ */
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800880 I915_WRITE(RING_MODE_GEN7(ring),
881 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
Ben Widawsky61973492013-04-08 18:43:54 -0700882 }
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800883}
884
Daniel Vetter82460d92014-08-06 20:19:53 +0200885static void gen6_ppgtt_enable(struct drm_device *dev)
Ben Widawsky61973492013-04-08 18:43:54 -0700886{
Jani Nikula50227e12014-03-31 14:27:21 +0300887 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800888 uint32_t ecochk, gab_ctl, ecobits;
Ben Widawsky61973492013-04-08 18:43:54 -0700889
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800890 ecobits = I915_READ(GAC_ECO_BITS);
891 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
892 ECOBITS_PPGTT_CACHE64B);
Ben Widawsky61973492013-04-08 18:43:54 -0700893
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800894 gab_ctl = I915_READ(GAB_CTL);
895 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
Ben Widawsky61973492013-04-08 18:43:54 -0700896
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800897 ecochk = I915_READ(GAM_ECOCHK);
898 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
Ben Widawsky61973492013-04-08 18:43:54 -0700899
Ben Widawskyb4a74e32013-12-06 14:11:09 -0800900 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
Ben Widawsky61973492013-04-08 18:43:54 -0700901}
902
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100903/* PPGTT support for Sandybdrige/Gen6 and later */
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700904static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -0800905 uint64_t start,
906 uint64_t length,
Ben Widawsky828c7902013-10-16 09:21:30 -0700907 bool use_scratch)
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100908{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700909 struct i915_hw_ppgtt *ppgtt =
910 container_of(vm, struct i915_hw_ppgtt, base);
Ben Widawskye7c2b582013-04-08 18:43:48 -0700911 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
Ben Widawsky782f1492014-02-20 11:50:33 -0800912 unsigned first_entry = start >> PAGE_SHIFT;
913 unsigned num_entries = length >> PAGE_SHIFT;
Daniel Vettera15326a2013-03-19 23:48:39 +0100914 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
Daniel Vetter7bddb012012-02-09 17:15:47 +0100915 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
916 unsigned last_pte, i;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100917
Akash Goel24f3a8c2014-06-17 10:59:42 +0530918 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100919
Daniel Vetter7bddb012012-02-09 17:15:47 +0100920 while (num_entries) {
921 last_pte = first_pte + num_entries;
922 if (last_pte > I915_PPGTT_PT_ENTRIES)
923 last_pte = I915_PPGTT_PT_ENTRIES;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100924
Daniel Vettera15326a2013-03-19 23:48:39 +0100925 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
Daniel Vetter7bddb012012-02-09 17:15:47 +0100926
927 for (i = first_pte; i < last_pte; i++)
928 pt_vaddr[i] = scratch_pte;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100929
930 kunmap_atomic(pt_vaddr);
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100931
Daniel Vetter7bddb012012-02-09 17:15:47 +0100932 num_entries -= last_pte - first_pte;
933 first_pte = 0;
Daniel Vettera15326a2013-03-19 23:48:39 +0100934 act_pt++;
Daniel Vetter7bddb012012-02-09 17:15:47 +0100935 }
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100936}
937
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700938static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
Daniel Vetterdef886c2013-01-24 14:44:56 -0800939 struct sg_table *pages,
Ben Widawsky782f1492014-02-20 11:50:33 -0800940 uint64_t start,
Akash Goel24f3a8c2014-06-17 10:59:42 +0530941 enum i915_cache_level cache_level, u32 flags)
Daniel Vetterdef886c2013-01-24 14:44:56 -0800942{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700943 struct i915_hw_ppgtt *ppgtt =
944 container_of(vm, struct i915_hw_ppgtt, base);
Ben Widawskye7c2b582013-04-08 18:43:48 -0700945 gen6_gtt_pte_t *pt_vaddr;
Ben Widawsky782f1492014-02-20 11:50:33 -0800946 unsigned first_entry = start >> PAGE_SHIFT;
Daniel Vettera15326a2013-03-19 23:48:39 +0100947 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
Imre Deak6e995e22013-02-18 19:28:04 +0200948 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
949 struct sg_page_iter sg_iter;
Daniel Vetterdef886c2013-01-24 14:44:56 -0800950
Chris Wilsoncc797142013-12-31 15:50:30 +0000951 pt_vaddr = NULL;
Imre Deak6e995e22013-02-18 19:28:04 +0200952 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
Chris Wilsoncc797142013-12-31 15:50:30 +0000953 if (pt_vaddr == NULL)
954 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
Daniel Vetterdef886c2013-01-24 14:44:56 -0800955
Chris Wilsoncc797142013-12-31 15:50:30 +0000956 pt_vaddr[act_pte] =
957 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
Akash Goel24f3a8c2014-06-17 10:59:42 +0530958 cache_level, true, flags);
959
Imre Deak6e995e22013-02-18 19:28:04 +0200960 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
961 kunmap_atomic(pt_vaddr);
Chris Wilsoncc797142013-12-31 15:50:30 +0000962 pt_vaddr = NULL;
Daniel Vettera15326a2013-03-19 23:48:39 +0100963 act_pt++;
Imre Deak6e995e22013-02-18 19:28:04 +0200964 act_pte = 0;
Daniel Vetterdef886c2013-01-24 14:44:56 -0800965 }
Daniel Vetterdef886c2013-01-24 14:44:56 -0800966 }
Chris Wilsoncc797142013-12-31 15:50:30 +0000967 if (pt_vaddr)
968 kunmap_atomic(pt_vaddr);
Daniel Vetterdef886c2013-01-24 14:44:56 -0800969}
970
Ben Widawskya00d8252014-02-19 22:05:48 -0800971static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100972{
Daniel Vetter3440d262013-01-24 13:49:56 -0800973 int i;
974
975 if (ppgtt->pt_dma_addr) {
976 for (i = 0; i < ppgtt->num_pd_entries; i++)
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700977 pci_unmap_page(ppgtt->base.dev->pdev,
Daniel Vetter3440d262013-01-24 13:49:56 -0800978 ppgtt->pt_dma_addr[i],
979 4096, PCI_DMA_BIDIRECTIONAL);
980 }
Ben Widawskya00d8252014-02-19 22:05:48 -0800981}
982
983static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
984{
985 int i;
Daniel Vetter3440d262013-01-24 13:49:56 -0800986
987 kfree(ppgtt->pt_dma_addr);
988 for (i = 0; i < ppgtt->num_pd_entries; i++)
989 __free_page(ppgtt->pt_pages[i]);
990 kfree(ppgtt->pt_pages);
Daniel Vetter3440d262013-01-24 13:49:56 -0800991}
992
Ben Widawskya00d8252014-02-19 22:05:48 -0800993static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
994{
995 struct i915_hw_ppgtt *ppgtt =
996 container_of(vm, struct i915_hw_ppgtt, base);
997
Ben Widawskya00d8252014-02-19 22:05:48 -0800998 drm_mm_remove_node(&ppgtt->node);
999
1000 gen6_ppgtt_unmap_pages(ppgtt);
1001 gen6_ppgtt_free(ppgtt);
1002}
1003
Ben Widawskyb1465202014-02-19 22:05:49 -08001004static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
Daniel Vetter3440d262013-01-24 13:49:56 -08001005{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001006 struct drm_device *dev = ppgtt->base.dev;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001007 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskye3cc1992013-12-06 14:11:08 -08001008 bool retried = false;
Ben Widawskyb1465202014-02-19 22:05:49 -08001009 int ret;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001010
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001011 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1012 * allocator works in address space sizes, so it's multiplied by page
1013 * size. We allocate at the top of the GTT to avoid fragmentation.
1014 */
1015 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
Ben Widawskye3cc1992013-12-06 14:11:08 -08001016alloc:
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001017 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1018 &ppgtt->node, GEN6_PD_SIZE,
1019 GEN6_PD_ALIGN, 0,
1020 0, dev_priv->gtt.base.total,
Ben Widawsky3e8b5ae2014-05-06 22:21:30 -07001021 DRM_MM_TOPDOWN);
Ben Widawskye3cc1992013-12-06 14:11:08 -08001022 if (ret == -ENOSPC && !retried) {
1023 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1024 GEN6_PD_SIZE, GEN6_PD_ALIGN,
Chris Wilsond23db882014-05-23 08:48:08 +02001025 I915_CACHE_NONE,
1026 0, dev_priv->gtt.base.total,
1027 0);
Ben Widawskye3cc1992013-12-06 14:11:08 -08001028 if (ret)
1029 return ret;
1030
1031 retried = true;
1032 goto alloc;
1033 }
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001034
1035 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1036 DRM_DEBUG("Forced to use aperture for PDEs\n");
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001037
Ben Widawsky6670a5a2013-06-27 16:30:04 -07001038 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
Ben Widawskyb1465202014-02-19 22:05:49 -08001039 return ret;
1040}
1041
1042static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
1043{
1044 int i;
1045
1046 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
1047 GFP_KERNEL);
1048
1049 if (!ppgtt->pt_pages)
1050 return -ENOMEM;
1051
1052 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1053 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
1054 if (!ppgtt->pt_pages[i]) {
1055 gen6_ppgtt_free(ppgtt);
1056 return -ENOMEM;
1057 }
1058 }
1059
1060 return 0;
1061}
1062
1063static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1064{
1065 int ret;
1066
1067 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1068 if (ret)
1069 return ret;
1070
1071 ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1072 if (ret) {
1073 drm_mm_remove_node(&ppgtt->node);
1074 return ret;
1075 }
1076
1077 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1078 GFP_KERNEL);
1079 if (!ppgtt->pt_dma_addr) {
1080 drm_mm_remove_node(&ppgtt->node);
1081 gen6_ppgtt_free(ppgtt);
1082 return -ENOMEM;
1083 }
1084
1085 return 0;
1086}
1087
1088static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1089{
1090 struct drm_device *dev = ppgtt->base.dev;
1091 int i;
1092
1093 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1094 dma_addr_t pt_addr;
1095
1096 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1097 PCI_DMA_BIDIRECTIONAL);
1098
1099 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1100 gen6_ppgtt_unmap_pages(ppgtt);
1101 return -EIO;
1102 }
1103
1104 ppgtt->pt_dma_addr[i] = pt_addr;
1105 }
1106
1107 return 0;
1108}
1109
1110static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1111{
1112 struct drm_device *dev = ppgtt->base.dev;
1113 struct drm_i915_private *dev_priv = dev->dev_private;
1114 int ret;
1115
1116 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
Ben Widawsky48a10382013-12-06 14:11:11 -08001117 if (IS_GEN6(dev)) {
Ben Widawsky48a10382013-12-06 14:11:11 -08001118 ppgtt->switch_mm = gen6_mm_switch;
Ben Widawsky90252e52013-12-06 14:11:12 -08001119 } else if (IS_HASWELL(dev)) {
Ben Widawsky90252e52013-12-06 14:11:12 -08001120 ppgtt->switch_mm = hsw_mm_switch;
Ben Widawsky48a10382013-12-06 14:11:11 -08001121 } else if (IS_GEN7(dev)) {
Ben Widawsky48a10382013-12-06 14:11:11 -08001122 ppgtt->switch_mm = gen7_mm_switch;
1123 } else
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001124 BUG();
Ben Widawskyb1465202014-02-19 22:05:49 -08001125
1126 ret = gen6_ppgtt_alloc(ppgtt);
1127 if (ret)
1128 return ret;
1129
1130 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1131 if (ret) {
1132 gen6_ppgtt_free(ppgtt);
1133 return ret;
1134 }
1135
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001136 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1137 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1138 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
Ben Widawsky686e1f62013-11-25 09:54:34 -08001139 ppgtt->base.start = 0;
Ben Widawsky5a6c93f2014-03-08 11:58:17 -08001140 ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
Ben Widawskyb1465202014-02-19 22:05:49 -08001141 ppgtt->debug_dump = gen6_dump_ppgtt;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001142
Ben Widawskyb1465202014-02-19 22:05:49 -08001143 ppgtt->pd_offset =
1144 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001145
Ben Widawsky782f1492014-02-20 11:50:33 -08001146 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001147
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001148 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1149 ppgtt->node.size >> 20,
1150 ppgtt->node.start / PAGE_SIZE);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001151
Daniel Vetterfa76da32014-08-06 20:19:54 +02001152 gen6_write_pdes(ppgtt);
1153 DRM_DEBUG("Adding PPGTT at offset %x\n",
1154 ppgtt->pd_offset << 10);
1155
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001156 return 0;
Daniel Vetter3440d262013-01-24 13:49:56 -08001157}
1158
Daniel Vetterfa76da32014-08-06 20:19:54 +02001159static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
Daniel Vetter3440d262013-01-24 13:49:56 -08001160{
1161 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter3440d262013-01-24 13:49:56 -08001162
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001163 ppgtt->base.dev = dev;
Ben Widawsky8407bb92014-03-08 11:58:16 -08001164 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
Daniel Vetter3440d262013-01-24 13:49:56 -08001165
Ben Widawsky3ed124b2013-04-08 18:43:53 -07001166 if (INTEL_INFO(dev)->gen < 8)
Daniel Vetterfa76da32014-08-06 20:19:54 +02001167 return gen6_ppgtt_init(ppgtt);
Damien Lespiau3fdcf802014-01-23 13:59:49 +00001168 else if (IS_GEN8(dev) || IS_GEN9(dev))
Daniel Vetterfa76da32014-08-06 20:19:54 +02001169 return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
Ben Widawsky3ed124b2013-04-08 18:43:53 -07001170 else
1171 BUG();
Daniel Vetterfa76da32014-08-06 20:19:54 +02001172}
1173int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1174{
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176 int ret = 0;
Ben Widawsky3ed124b2013-04-08 18:43:53 -07001177
Daniel Vetterfa76da32014-08-06 20:19:54 +02001178 ret = __hw_ppgtt_init(dev, ppgtt);
1179 if (ret == 0) {
Ben Widawskyc7c48df2013-12-06 14:11:15 -08001180 kref_init(&ppgtt->ref);
Ben Widawsky93bd8642013-07-16 16:50:06 -07001181 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1182 ppgtt->base.total);
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08001183 i915_init_vm(dev_priv, &ppgtt->base);
Ben Widawsky93bd8642013-07-16 16:50:06 -07001184 }
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001185
1186 return ret;
1187}
1188
Daniel Vetter82460d92014-08-06 20:19:53 +02001189int i915_ppgtt_init_hw(struct drm_device *dev)
1190{
1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 struct intel_engine_cs *ring;
1193 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1194 int i, ret = 0;
1195
Thomas Daniel671b50132014-08-20 16:24:50 +01001196 /* In the case of execlists, PPGTT is enabled by the context descriptor
1197 * and the PDPs are contained within the context itself. We don't
1198 * need to do anything here. */
1199 if (i915.enable_execlists)
1200 return 0;
1201
Daniel Vetter82460d92014-08-06 20:19:53 +02001202 if (!USES_PPGTT(dev))
1203 return 0;
1204
1205 if (IS_GEN6(dev))
1206 gen6_ppgtt_enable(dev);
1207 else if (IS_GEN7(dev))
1208 gen7_ppgtt_enable(dev);
1209 else if (INTEL_INFO(dev)->gen >= 8)
1210 gen8_ppgtt_enable(dev);
1211 else
Daniel Vetter5f77eeb2014-12-08 16:40:10 +01001212 MISSING_CASE(INTEL_INFO(dev)->gen);
Daniel Vetter82460d92014-08-06 20:19:53 +02001213
1214 if (ppgtt) {
1215 for_each_ring(ring, dev_priv, i) {
McAulay, Alistair6689c162014-08-15 18:51:35 +01001216 ret = ppgtt->switch_mm(ppgtt, ring);
Daniel Vetter82460d92014-08-06 20:19:53 +02001217 if (ret != 0)
1218 return ret;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001219 }
1220 }
1221
1222 return ret;
1223}
Daniel Vetter4d884702014-08-06 15:04:47 +02001224struct i915_hw_ppgtt *
1225i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1226{
1227 struct i915_hw_ppgtt *ppgtt;
1228 int ret;
1229
1230 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1231 if (!ppgtt)
1232 return ERR_PTR(-ENOMEM);
1233
1234 ret = i915_ppgtt_init(dev, ppgtt);
1235 if (ret) {
1236 kfree(ppgtt);
1237 return ERR_PTR(ret);
1238 }
1239
1240 ppgtt->file_priv = fpriv;
1241
Daniele Ceraolo Spurio198c9742014-11-10 13:44:31 +00001242 trace_i915_ppgtt_create(&ppgtt->base);
1243
Daniel Vetter4d884702014-08-06 15:04:47 +02001244 return ppgtt;
1245}
1246
Daniel Vetteree960be2014-08-06 15:04:45 +02001247void i915_ppgtt_release(struct kref *kref)
1248{
1249 struct i915_hw_ppgtt *ppgtt =
1250 container_of(kref, struct i915_hw_ppgtt, ref);
1251
Daniele Ceraolo Spurio198c9742014-11-10 13:44:31 +00001252 trace_i915_ppgtt_release(&ppgtt->base);
1253
Daniel Vetteree960be2014-08-06 15:04:45 +02001254 /* vmas should already be unbound */
1255 WARN_ON(!list_empty(&ppgtt->base.active_list));
1256 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1257
Daniel Vetter19dd1202014-08-06 15:04:55 +02001258 list_del(&ppgtt->base.global_link);
1259 drm_mm_takedown(&ppgtt->base.mm);
1260
Daniel Vetteree960be2014-08-06 15:04:45 +02001261 ppgtt->base.cleanup(&ppgtt->base);
1262 kfree(ppgtt);
1263}
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001264
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08001265static void
Ben Widawsky6f65e292013-12-06 14:10:56 -08001266ppgtt_bind_vma(struct i915_vma *vma,
1267 enum i915_cache_level cache_level,
1268 u32 flags)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001269{
Akash Goel24f3a8c2014-06-17 10:59:42 +05301270 /* Currently applicable only to VLV */
1271 if (vma->obj->gt_ro)
1272 flags |= PTE_READ_ONLY;
1273
Ben Widawsky782f1492014-02-20 11:50:33 -08001274 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
Akash Goel24f3a8c2014-06-17 10:59:42 +05301275 cache_level, flags);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001276}
1277
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08001278static void ppgtt_unbind_vma(struct i915_vma *vma)
Daniel Vetter7bddb012012-02-09 17:15:47 +01001279{
Ben Widawsky6f65e292013-12-06 14:10:56 -08001280 vma->vm->clear_range(vma->vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08001281 vma->node.start,
1282 vma->obj->base.size,
Ben Widawsky6f65e292013-12-06 14:10:56 -08001283 true);
Daniel Vetter7bddb012012-02-09 17:15:47 +01001284}
1285
Ben Widawskya81cc002013-01-18 12:30:31 -08001286extern int intel_iommu_gfx_mapped;
1287/* Certain Gen5 chipsets require require idling the GPU before
1288 * unmapping anything from the GTT when VT-d is enabled.
1289 */
1290static inline bool needs_idle_maps(struct drm_device *dev)
1291{
1292#ifdef CONFIG_INTEL_IOMMU
1293 /* Query intel_iommu to see if we need the workaround. Presumably that
1294 * was loaded first.
1295 */
1296 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1297 return true;
1298#endif
1299 return false;
1300}
1301
Ben Widawsky5c042282011-10-17 15:51:55 -07001302static bool do_idling(struct drm_i915_private *dev_priv)
1303{
1304 bool ret = dev_priv->mm.interruptible;
1305
Ben Widawskya81cc002013-01-18 12:30:31 -08001306 if (unlikely(dev_priv->gtt.do_idle_maps)) {
Ben Widawsky5c042282011-10-17 15:51:55 -07001307 dev_priv->mm.interruptible = false;
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07001308 if (i915_gpu_idle(dev_priv->dev)) {
Ben Widawsky5c042282011-10-17 15:51:55 -07001309 DRM_ERROR("Couldn't idle GPU\n");
1310 /* Wait a bit, in hopes it avoids the hang */
1311 udelay(10);
1312 }
1313 }
1314
1315 return ret;
1316}
1317
1318static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1319{
Ben Widawskya81cc002013-01-18 12:30:31 -08001320 if (unlikely(dev_priv->gtt.do_idle_maps))
Ben Widawsky5c042282011-10-17 15:51:55 -07001321 dev_priv->mm.interruptible = interruptible;
1322}
1323
Ben Widawsky828c7902013-10-16 09:21:30 -07001324void i915_check_and_clear_faults(struct drm_device *dev)
1325{
1326 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001327 struct intel_engine_cs *ring;
Ben Widawsky828c7902013-10-16 09:21:30 -07001328 int i;
1329
1330 if (INTEL_INFO(dev)->gen < 6)
1331 return;
1332
1333 for_each_ring(ring, dev_priv, i) {
1334 u32 fault_reg;
1335 fault_reg = I915_READ(RING_FAULT_REG(ring));
1336 if (fault_reg & RING_FAULT_VALID) {
1337 DRM_DEBUG_DRIVER("Unexpected fault\n"
Paulo Zanoni59a5d292014-10-30 15:52:45 -02001338 "\tAddr: 0x%08lx\n"
Ben Widawsky828c7902013-10-16 09:21:30 -07001339 "\tAddress space: %s\n"
1340 "\tSource ID: %d\n"
1341 "\tType: %d\n",
1342 fault_reg & PAGE_MASK,
1343 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1344 RING_FAULT_SRCID(fault_reg),
1345 RING_FAULT_FAULT_TYPE(fault_reg));
1346 I915_WRITE(RING_FAULT_REG(ring),
1347 fault_reg & ~RING_FAULT_VALID);
1348 }
1349 }
1350 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1351}
1352
Chris Wilson91e56492014-09-25 10:13:12 +01001353static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1354{
1355 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1356 intel_gtt_chipset_flush();
1357 } else {
1358 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1359 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1360 }
1361}
1362
Ben Widawsky828c7902013-10-16 09:21:30 -07001363void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1364{
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367 /* Don't bother messing with faults pre GEN6 as we have little
1368 * documentation supporting that it's a good idea.
1369 */
1370 if (INTEL_INFO(dev)->gen < 6)
1371 return;
1372
1373 i915_check_and_clear_faults(dev);
1374
1375 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
Ben Widawsky782f1492014-02-20 11:50:33 -08001376 dev_priv->gtt.base.start,
1377 dev_priv->gtt.base.total,
Daniel Vettere568af12014-03-26 20:08:20 +01001378 true);
Chris Wilson91e56492014-09-25 10:13:12 +01001379
1380 i915_ggtt_flush(dev_priv);
Ben Widawsky828c7902013-10-16 09:21:30 -07001381}
1382
Daniel Vetter76aaf222010-11-05 22:23:30 +01001383void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1384{
1385 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson05394f32010-11-08 19:18:58 +00001386 struct drm_i915_gem_object *obj;
Ben Widawsky80da2162013-12-06 14:11:17 -08001387 struct i915_address_space *vm;
Daniel Vetter76aaf222010-11-05 22:23:30 +01001388
Ben Widawsky828c7902013-10-16 09:21:30 -07001389 i915_check_and_clear_faults(dev);
1390
Chris Wilsonbee4a182011-01-21 10:54:32 +00001391 /* First fill our portion of the GTT with scratch pages */
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001392 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
Ben Widawsky782f1492014-02-20 11:50:33 -08001393 dev_priv->gtt.base.start,
1394 dev_priv->gtt.base.total,
Ben Widawsky828c7902013-10-16 09:21:30 -07001395 true);
Chris Wilsonbee4a182011-01-21 10:54:32 +00001396
Ben Widawsky35c20a62013-05-31 11:28:48 -07001397 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Ben Widawsky6f65e292013-12-06 14:10:56 -08001398 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1399 &dev_priv->gtt.base);
1400 if (!vma)
1401 continue;
1402
Chris Wilson2c225692013-08-09 12:26:45 +01001403 i915_gem_clflush_object(obj, obj->pin_display);
Ben Widawsky6f65e292013-12-06 14:10:56 -08001404 /* The bind_vma code tries to be smart about tracking mappings.
1405 * Unfortunately above, we've just wiped out the mappings
1406 * without telling our object about it. So we need to fake it.
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00001407 *
1408 * Bind is not expected to fail since this is only called on
1409 * resume and assumption is all requirements exist already.
Ben Widawsky6f65e292013-12-06 14:10:56 -08001410 */
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001411 vma->bound &= ~GLOBAL_BIND;
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00001412 WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND));
Daniel Vetter76aaf222010-11-05 22:23:30 +01001413 }
1414
Ben Widawsky80da2162013-12-06 14:11:17 -08001415
Ben Widawskya2319c02014-03-18 16:09:37 -07001416 if (INTEL_INFO(dev)->gen >= 8) {
Ville Syrjäläee0ce472014-04-09 13:28:01 +03001417 if (IS_CHERRYVIEW(dev))
1418 chv_setup_private_ppat(dev_priv);
1419 else
1420 bdw_setup_private_ppat(dev_priv);
1421
Ben Widawsky80da2162013-12-06 14:11:17 -08001422 return;
Ben Widawskya2319c02014-03-18 16:09:37 -07001423 }
Ben Widawsky80da2162013-12-06 14:11:17 -08001424
1425 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1426 /* TODO: Perhaps it shouldn't be gen6 specific */
1427 if (i915_is_ggtt(vm)) {
1428 if (dev_priv->mm.aliasing_ppgtt)
1429 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1430 continue;
1431 }
1432
1433 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
Daniel Vetter76aaf222010-11-05 22:23:30 +01001434 }
1435
Chris Wilson91e56492014-09-25 10:13:12 +01001436 i915_ggtt_flush(dev_priv);
Daniel Vetter76aaf222010-11-05 22:23:30 +01001437}
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01001438
Daniel Vetter74163902012-02-15 23:50:21 +01001439int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01001440{
Chris Wilson9da3da62012-06-01 15:20:22 +01001441 if (obj->has_dma_mapping)
Daniel Vetter74163902012-02-15 23:50:21 +01001442 return 0;
Chris Wilson9da3da62012-06-01 15:20:22 +01001443
1444 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1445 obj->pages->sgl, obj->pages->nents,
1446 PCI_DMA_BIDIRECTIONAL))
1447 return -ENOSPC;
1448
1449 return 0;
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01001450}
1451
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001452static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1453{
1454#ifdef writeq
1455 writeq(pte, addr);
1456#else
1457 iowrite32((u32)pte, addr);
1458 iowrite32(pte >> 32, addr + 4);
1459#endif
1460}
1461
1462static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1463 struct sg_table *st,
Ben Widawsky782f1492014-02-20 11:50:33 -08001464 uint64_t start,
Akash Goel24f3a8c2014-06-17 10:59:42 +05301465 enum i915_cache_level level, u32 unused)
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001466{
1467 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08001468 unsigned first_entry = start >> PAGE_SHIFT;
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001469 gen8_gtt_pte_t __iomem *gtt_entries =
1470 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1471 int i = 0;
1472 struct sg_page_iter sg_iter;
Pavel Machek57007df2014-07-28 13:20:58 +02001473 dma_addr_t addr = 0; /* shut up gcc */
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001474
1475 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1476 addr = sg_dma_address(sg_iter.sg) +
1477 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1478 gen8_set_pte(&gtt_entries[i],
1479 gen8_pte_encode(addr, level, true));
1480 i++;
1481 }
1482
1483 /*
1484 * XXX: This serves as a posting read to make sure that the PTE has
1485 * actually been updated. There is some concern that even though
1486 * registers and PTEs are within the same BAR that they are potentially
1487 * of NUMA access patterns. Therefore, even with the way we assume
1488 * hardware should work, we must keep this posting read for paranoia.
1489 */
1490 if (i != 0)
1491 WARN_ON(readq(&gtt_entries[i-1])
1492 != gen8_pte_encode(addr, level, true));
1493
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001494 /* This next bit makes the above posting read even more important. We
1495 * want to flush the TLBs only after we're certain all the PTE updates
1496 * have finished.
1497 */
1498 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1499 POSTING_READ(GFX_FLSH_CNTL_GEN6);
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001500}
1501
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001502/*
1503 * Binds an object into the global gtt with the specified cache level. The object
1504 * will be accessible to the GPU via commands whose operands reference offsets
1505 * within the global GTT as well as accessible by the GPU through the GMADR
1506 * mapped BAR (dev_priv->mm.gtt->gtt).
1507 */
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001508static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001509 struct sg_table *st,
Ben Widawsky782f1492014-02-20 11:50:33 -08001510 uint64_t start,
Akash Goel24f3a8c2014-06-17 10:59:42 +05301511 enum i915_cache_level level, u32 flags)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001512{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001513 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08001514 unsigned first_entry = start >> PAGE_SHIFT;
Ben Widawskye7c2b582013-04-08 18:43:48 -07001515 gen6_gtt_pte_t __iomem *gtt_entries =
1516 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
Imre Deak6e995e22013-02-18 19:28:04 +02001517 int i = 0;
1518 struct sg_page_iter sg_iter;
Pavel Machek57007df2014-07-28 13:20:58 +02001519 dma_addr_t addr = 0;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001520
Imre Deak6e995e22013-02-18 19:28:04 +02001521 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
Imre Deak2db76d72013-03-26 15:14:18 +02001522 addr = sg_page_iter_dma_address(&sg_iter);
Akash Goel24f3a8c2014-06-17 10:59:42 +05301523 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
Imre Deak6e995e22013-02-18 19:28:04 +02001524 i++;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001525 }
1526
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001527 /* XXX: This serves as a posting read to make sure that the PTE has
1528 * actually been updated. There is some concern that even though
1529 * registers and PTEs are within the same BAR that they are potentially
1530 * of NUMA access patterns. Therefore, even with the way we assume
1531 * hardware should work, we must keep this posting read for paranoia.
1532 */
Pavel Machek57007df2014-07-28 13:20:58 +02001533 if (i != 0) {
1534 unsigned long gtt = readl(&gtt_entries[i-1]);
1535 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1536 }
Ben Widawsky0f9b91c2012-11-04 09:21:30 -08001537
1538 /* This next bit makes the above posting read even more important. We
1539 * want to flush the TLBs only after we're certain all the PTE updates
1540 * have finished.
1541 */
1542 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1543 POSTING_READ(GFX_FLSH_CNTL_GEN6);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001544}
1545
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001546static void gen8_ggtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08001547 uint64_t start,
1548 uint64_t length,
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001549 bool use_scratch)
1550{
1551 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08001552 unsigned first_entry = start >> PAGE_SHIFT;
1553 unsigned num_entries = length >> PAGE_SHIFT;
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001554 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1555 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1556 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1557 int i;
1558
1559 if (WARN(num_entries > max_entries,
1560 "First entry = %d; Num entries = %d (max=%d)\n",
1561 first_entry, num_entries, max_entries))
1562 num_entries = max_entries;
1563
1564 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1565 I915_CACHE_LLC,
1566 use_scratch);
1567 for (i = 0; i < num_entries; i++)
1568 gen8_set_pte(&gtt_base[i], scratch_pte);
1569 readl(gtt_base);
1570}
1571
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001572static void gen6_ggtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08001573 uint64_t start,
1574 uint64_t length,
Ben Widawsky828c7902013-10-16 09:21:30 -07001575 bool use_scratch)
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001576{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001577 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08001578 unsigned first_entry = start >> PAGE_SHIFT;
1579 unsigned num_entries = length >> PAGE_SHIFT;
Ben Widawskye7c2b582013-04-08 18:43:48 -07001580 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1581 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
Ben Widawskya54c0c22013-01-24 14:45:00 -08001582 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001583 int i;
1584
1585 if (WARN(num_entries > max_entries,
1586 "First entry = %d; Num entries = %d (max=%d)\n",
1587 first_entry, num_entries, max_entries))
1588 num_entries = max_entries;
1589
Akash Goel24f3a8c2014-06-17 10:59:42 +05301590 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
Ben Widawsky828c7902013-10-16 09:21:30 -07001591
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001592 for (i = 0; i < num_entries; i++)
1593 iowrite32(scratch_pte, &gtt_base[i]);
1594 readl(gtt_base);
1595}
1596
Ben Widawsky6f65e292013-12-06 14:10:56 -08001597
1598static void i915_ggtt_bind_vma(struct i915_vma *vma,
1599 enum i915_cache_level cache_level,
1600 u32 unused)
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001601{
Ben Widawsky6f65e292013-12-06 14:10:56 -08001602 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001603 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1604 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1605
Ben Widawsky6f65e292013-12-06 14:10:56 -08001606 BUG_ON(!i915_is_ggtt(vma->vm));
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00001607 intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags);
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001608 vma->bound = GLOBAL_BIND;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001609}
1610
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001611static void i915_ggtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08001612 uint64_t start,
1613 uint64_t length,
Ben Widawsky828c7902013-10-16 09:21:30 -07001614 bool unused)
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001615{
Ben Widawsky782f1492014-02-20 11:50:33 -08001616 unsigned first_entry = start >> PAGE_SHIFT;
1617 unsigned num_entries = length >> PAGE_SHIFT;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001618 intel_gtt_clear_range(first_entry, num_entries);
1619}
1620
Ben Widawsky6f65e292013-12-06 14:10:56 -08001621static void i915_ggtt_unbind_vma(struct i915_vma *vma)
Chris Wilsond5bd1442011-04-14 06:48:26 +01001622{
Ben Widawsky6f65e292013-12-06 14:10:56 -08001623 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1624 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001625
Ben Widawsky6f65e292013-12-06 14:10:56 -08001626 BUG_ON(!i915_is_ggtt(vma->vm));
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001627 vma->bound = 0;
Ben Widawsky6f65e292013-12-06 14:10:56 -08001628 intel_gtt_clear_range(first, size);
Chris Wilsond5bd1442011-04-14 06:48:26 +01001629}
1630
Ben Widawsky6f65e292013-12-06 14:10:56 -08001631static void ggtt_bind_vma(struct i915_vma *vma,
1632 enum i915_cache_level cache_level,
1633 u32 flags)
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01001634{
Ben Widawsky6f65e292013-12-06 14:10:56 -08001635 struct drm_device *dev = vma->vm->dev;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001636 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky6f65e292013-12-06 14:10:56 -08001637 struct drm_i915_gem_object *obj = vma->obj;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001638
Akash Goel24f3a8c2014-06-17 10:59:42 +05301639 /* Currently applicable only to VLV */
1640 if (obj->gt_ro)
1641 flags |= PTE_READ_ONLY;
1642
Ben Widawsky6f65e292013-12-06 14:10:56 -08001643 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1644 * or we have a global mapping already but the cacheability flags have
1645 * changed, set the global PTEs.
1646 *
1647 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1648 * instead if none of the above hold true.
1649 *
1650 * NB: A global mapping should only be needed for special regions like
1651 * "gtt mappable", SNB errata, or if specified via special execbuf
1652 * flags. At all other times, the GPU will use the aliasing PPGTT.
1653 */
1654 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001655 if (!(vma->bound & GLOBAL_BIND) ||
Ben Widawsky6f65e292013-12-06 14:10:56 -08001656 (cache_level != obj->cache_level)) {
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00001657 vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
Ben Widawsky782f1492014-02-20 11:50:33 -08001658 vma->node.start,
Akash Goel24f3a8c2014-06-17 10:59:42 +05301659 cache_level, flags);
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001660 vma->bound |= GLOBAL_BIND;
Ben Widawsky6f65e292013-12-06 14:10:56 -08001661 }
1662 }
Daniel Vetter74898d72012-02-15 23:50:22 +01001663
Ben Widawsky6f65e292013-12-06 14:10:56 -08001664 if (dev_priv->mm.aliasing_ppgtt &&
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001665 (!(vma->bound & LOCAL_BIND) ||
Ben Widawsky6f65e292013-12-06 14:10:56 -08001666 (cache_level != obj->cache_level))) {
1667 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1668 appgtt->base.insert_entries(&appgtt->base,
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00001669 vma->ggtt_view.pages,
Ben Widawsky782f1492014-02-20 11:50:33 -08001670 vma->node.start,
Akash Goel24f3a8c2014-06-17 10:59:42 +05301671 cache_level, flags);
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001672 vma->bound |= LOCAL_BIND;
Ben Widawsky6f65e292013-12-06 14:10:56 -08001673 }
1674}
1675
1676static void ggtt_unbind_vma(struct i915_vma *vma)
1677{
1678 struct drm_device *dev = vma->vm->dev;
1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 struct drm_i915_gem_object *obj = vma->obj;
Ben Widawsky6f65e292013-12-06 14:10:56 -08001681
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001682 if (vma->bound & GLOBAL_BIND) {
Ben Widawsky782f1492014-02-20 11:50:33 -08001683 vma->vm->clear_range(vma->vm,
1684 vma->node.start,
1685 obj->base.size,
Ben Widawsky6f65e292013-12-06 14:10:56 -08001686 true);
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001687 vma->bound &= ~GLOBAL_BIND;
Ben Widawsky6f65e292013-12-06 14:10:56 -08001688 }
1689
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001690 if (vma->bound & LOCAL_BIND) {
Ben Widawsky6f65e292013-12-06 14:10:56 -08001691 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1692 appgtt->base.clear_range(&appgtt->base,
Ben Widawsky782f1492014-02-20 11:50:33 -08001693 vma->node.start,
1694 obj->base.size,
Ben Widawsky6f65e292013-12-06 14:10:56 -08001695 true);
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001696 vma->bound &= ~LOCAL_BIND;
Ben Widawsky6f65e292013-12-06 14:10:56 -08001697 }
Daniel Vetter74163902012-02-15 23:50:21 +01001698}
1699
1700void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1701{
Ben Widawsky5c042282011-10-17 15:51:55 -07001702 struct drm_device *dev = obj->base.dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704 bool interruptible;
1705
1706 interruptible = do_idling(dev_priv);
1707
Chris Wilson9da3da62012-06-01 15:20:22 +01001708 if (!obj->has_dma_mapping)
1709 dma_unmap_sg(&dev->pdev->dev,
1710 obj->pages->sgl, obj->pages->nents,
1711 PCI_DMA_BIDIRECTIONAL);
Ben Widawsky5c042282011-10-17 15:51:55 -07001712
1713 undo_idling(dev_priv, interruptible);
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01001714}
Daniel Vetter644ec022012-03-26 09:45:40 +02001715
Chris Wilson42d6ab42012-07-26 11:49:32 +01001716static void i915_gtt_color_adjust(struct drm_mm_node *node,
1717 unsigned long color,
1718 unsigned long *start,
1719 unsigned long *end)
1720{
1721 if (node->color != color)
1722 *start += 4096;
1723
1724 if (!list_empty(&node->node_list)) {
1725 node = list_entry(node->node_list.next,
1726 struct drm_mm_node,
1727 node_list);
1728 if (node->allocated && node->color != color)
1729 *end -= 4096;
1730 }
1731}
Ben Widawskyfbe5d362013-11-04 19:56:49 -08001732
Daniel Vetterf548c0e2014-11-19 21:40:13 +01001733static int i915_gem_setup_global_gtt(struct drm_device *dev,
1734 unsigned long start,
1735 unsigned long mappable_end,
1736 unsigned long end)
Daniel Vetter644ec022012-03-26 09:45:40 +02001737{
Ben Widawskye78891c2013-01-25 16:41:04 -08001738 /* Let GEM Manage all of the aperture.
1739 *
1740 * However, leave one page at the end still bound to the scratch page.
1741 * There are a number of places where the hardware apparently prefetches
1742 * past the end of the object, and we've seen multiple hangs with the
1743 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1744 * aperture. One page should be enough to keep any prefetching inside
1745 * of the aperture.
1746 */
Ben Widawsky40d749802013-07-31 16:59:59 -07001747 struct drm_i915_private *dev_priv = dev->dev_private;
1748 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
Chris Wilsoned2f3452012-11-15 11:32:19 +00001749 struct drm_mm_node *entry;
1750 struct drm_i915_gem_object *obj;
1751 unsigned long hole_start, hole_end;
Daniel Vetterfa76da32014-08-06 20:19:54 +02001752 int ret;
Daniel Vetter644ec022012-03-26 09:45:40 +02001753
Ben Widawsky35451cb2013-01-17 12:45:13 -08001754 BUG_ON(mappable_end > end);
1755
Chris Wilsoned2f3452012-11-15 11:32:19 +00001756 /* Subtract the guard page ... */
Ben Widawsky40d749802013-07-31 16:59:59 -07001757 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
Chris Wilson42d6ab42012-07-26 11:49:32 +01001758 if (!HAS_LLC(dev))
Ben Widawsky93bd8642013-07-16 16:50:06 -07001759 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
Daniel Vetter644ec022012-03-26 09:45:40 +02001760
Chris Wilsoned2f3452012-11-15 11:32:19 +00001761 /* Mark any preallocated objects as occupied */
Ben Widawsky35c20a62013-05-31 11:28:48 -07001762 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Ben Widawsky40d749802013-07-31 16:59:59 -07001763 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
Daniel Vetterfa76da32014-08-06 20:19:54 +02001764
Ben Widawskyedd41a82013-07-05 14:41:05 -07001765 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
Ben Widawskyc6cfb322013-07-05 14:41:06 -07001766 i915_gem_obj_ggtt_offset(obj), obj->base.size);
Chris Wilsoned2f3452012-11-15 11:32:19 +00001767
Ben Widawskyc6cfb322013-07-05 14:41:06 -07001768 WARN_ON(i915_gem_obj_ggtt_bound(obj));
Ben Widawsky40d749802013-07-31 16:59:59 -07001769 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
Daniel Vetter6c5566a2014-08-06 15:04:50 +02001770 if (ret) {
1771 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
1772 return ret;
1773 }
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01001774 vma->bound |= GLOBAL_BIND;
Chris Wilsoned2f3452012-11-15 11:32:19 +00001775 }
1776
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001777 dev_priv->gtt.base.start = start;
1778 dev_priv->gtt.base.total = end - start;
Daniel Vetter644ec022012-03-26 09:45:40 +02001779
Chris Wilsoned2f3452012-11-15 11:32:19 +00001780 /* Clear any non-preallocated blocks */
Ben Widawsky40d749802013-07-31 16:59:59 -07001781 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
Chris Wilsoned2f3452012-11-15 11:32:19 +00001782 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1783 hole_start, hole_end);
Ben Widawsky782f1492014-02-20 11:50:33 -08001784 ggtt_vm->clear_range(ggtt_vm, hole_start,
1785 hole_end - hole_start, true);
Chris Wilsoned2f3452012-11-15 11:32:19 +00001786 }
1787
1788 /* And finally clear the reserved guard page */
Ben Widawsky782f1492014-02-20 11:50:33 -08001789 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
Daniel Vetter6c5566a2014-08-06 15:04:50 +02001790
Daniel Vetterfa76da32014-08-06 20:19:54 +02001791 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
1792 struct i915_hw_ppgtt *ppgtt;
1793
1794 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1795 if (!ppgtt)
1796 return -ENOMEM;
1797
1798 ret = __hw_ppgtt_init(dev, ppgtt);
1799 if (ret != 0)
1800 return ret;
1801
1802 dev_priv->mm.aliasing_ppgtt = ppgtt;
1803 }
1804
Daniel Vetter6c5566a2014-08-06 15:04:50 +02001805 return 0;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001806}
1807
Ben Widawskyd7e50082012-12-18 10:31:25 -08001808void i915_gem_init_global_gtt(struct drm_device *dev)
1809{
1810 struct drm_i915_private *dev_priv = dev->dev_private;
1811 unsigned long gtt_size, mappable_size;
Ben Widawskyd7e50082012-12-18 10:31:25 -08001812
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001813 gtt_size = dev_priv->gtt.base.total;
Ben Widawsky93d18792013-01-17 12:45:17 -08001814 mappable_size = dev_priv->gtt.mappable_end;
Ben Widawskyd7e50082012-12-18 10:31:25 -08001815
Ben Widawskye78891c2013-01-25 16:41:04 -08001816 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001817}
1818
Daniel Vetter90d0a0e2014-08-06 15:04:56 +02001819void i915_global_gtt_cleanup(struct drm_device *dev)
1820{
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 struct i915_address_space *vm = &dev_priv->gtt.base;
1823
Daniel Vetter70e32542014-08-06 15:04:57 +02001824 if (dev_priv->mm.aliasing_ppgtt) {
1825 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1826
1827 ppgtt->base.cleanup(&ppgtt->base);
1828 }
1829
Daniel Vetter90d0a0e2014-08-06 15:04:56 +02001830 if (drm_mm_initialized(&vm->mm)) {
1831 drm_mm_takedown(&vm->mm);
1832 list_del(&vm->global_link);
1833 }
1834
1835 vm->cleanup(vm);
1836}
Daniel Vetter70e32542014-08-06 15:04:57 +02001837
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001838static int setup_scratch_page(struct drm_device *dev)
1839{
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 struct page *page;
1842 dma_addr_t dma_addr;
1843
1844 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1845 if (page == NULL)
1846 return -ENOMEM;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001847 set_pages_uc(page, 1);
1848
1849#ifdef CONFIG_INTEL_IOMMU
1850 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1851 PCI_DMA_BIDIRECTIONAL);
1852 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1853 return -EINVAL;
1854#else
1855 dma_addr = page_to_phys(page);
1856#endif
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001857 dev_priv->gtt.base.scratch.page = page;
1858 dev_priv->gtt.base.scratch.addr = dma_addr;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001859
1860 return 0;
1861}
1862
1863static void teardown_scratch_page(struct drm_device *dev)
1864{
1865 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001866 struct page *page = dev_priv->gtt.base.scratch.page;
1867
1868 set_pages_wb(page, 1);
1869 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001870 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001871 __free_page(page);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001872}
1873
1874static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1875{
1876 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1877 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1878 return snb_gmch_ctl << 20;
1879}
1880
Ben Widawsky9459d252013-11-03 16:53:55 -08001881static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1882{
1883 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1884 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1885 if (bdw_gmch_ctl)
1886 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
Ben Widawsky562d55d2014-05-27 16:53:08 -07001887
1888#ifdef CONFIG_X86_32
1889 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1890 if (bdw_gmch_ctl > 4)
1891 bdw_gmch_ctl = 4;
1892#endif
1893
Ben Widawsky9459d252013-11-03 16:53:55 -08001894 return bdw_gmch_ctl << 20;
1895}
1896
Damien Lespiaud7f25f22014-05-08 22:19:40 +03001897static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
1898{
1899 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
1900 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
1901
1902 if (gmch_ctrl)
1903 return 1 << (20 + gmch_ctrl);
1904
1905 return 0;
1906}
1907
Ben Widawskybaa09f52013-01-24 13:49:57 -08001908static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001909{
1910 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1911 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1912 return snb_gmch_ctl << 25; /* 32 MB units */
1913}
1914
Ben Widawsky9459d252013-11-03 16:53:55 -08001915static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1916{
1917 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1918 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1919 return bdw_gmch_ctl << 25; /* 32 MB units */
1920}
1921
Damien Lespiaud7f25f22014-05-08 22:19:40 +03001922static size_t chv_get_stolen_size(u16 gmch_ctrl)
1923{
1924 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
1925 gmch_ctrl &= SNB_GMCH_GMS_MASK;
1926
1927 /*
1928 * 0x0 to 0x10: 32MB increments starting at 0MB
1929 * 0x11 to 0x16: 4MB increments starting at 8MB
1930 * 0x17 to 0x1d: 4MB increments start at 36MB
1931 */
1932 if (gmch_ctrl < 0x11)
1933 return gmch_ctrl << 25;
1934 else if (gmch_ctrl < 0x17)
1935 return (gmch_ctrl - 0x11 + 2) << 22;
1936 else
1937 return (gmch_ctrl - 0x17 + 9) << 22;
1938}
1939
Damien Lespiau66375012014-01-09 18:02:46 +00001940static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
1941{
1942 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1943 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
1944
1945 if (gen9_gmch_ctl < 0xf0)
1946 return gen9_gmch_ctl << 25; /* 32 MB units */
1947 else
1948 /* 4MB increments starting at 0xf0 for 4MB */
1949 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
1950}
1951
Ben Widawsky63340132013-11-04 19:32:22 -08001952static int ggtt_probe_common(struct drm_device *dev,
1953 size_t gtt_size)
1954{
1955 struct drm_i915_private *dev_priv = dev->dev_private;
Bjorn Helgaas21c34602013-12-21 10:52:52 -07001956 phys_addr_t gtt_phys_addr;
Ben Widawsky63340132013-11-04 19:32:22 -08001957 int ret;
1958
1959 /* For Modern GENs the PTEs and register space are split in the BAR */
Bjorn Helgaas21c34602013-12-21 10:52:52 -07001960 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
Ben Widawsky63340132013-11-04 19:32:22 -08001961 (pci_resource_len(dev->pdev, 0) / 2);
1962
Bjorn Helgaas21c34602013-12-21 10:52:52 -07001963 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
Ben Widawsky63340132013-11-04 19:32:22 -08001964 if (!dev_priv->gtt.gsm) {
1965 DRM_ERROR("Failed to map the gtt page table\n");
1966 return -ENOMEM;
1967 }
1968
1969 ret = setup_scratch_page(dev);
1970 if (ret) {
1971 DRM_ERROR("Scratch setup failed\n");
1972 /* iounmap will also get called at remove, but meh */
1973 iounmap(dev_priv->gtt.gsm);
1974 }
1975
1976 return ret;
1977}
1978
Ben Widawskyfbe5d362013-11-04 19:56:49 -08001979/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1980 * bits. When using advanced contexts each context stores its own PAT, but
1981 * writing this data shouldn't be harmful even in those cases. */
Ville Syrjäläee0ce472014-04-09 13:28:01 +03001982static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
Ben Widawskyfbe5d362013-11-04 19:56:49 -08001983{
Ben Widawskyfbe5d362013-11-04 19:56:49 -08001984 uint64_t pat;
1985
1986 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1987 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1988 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1989 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1990 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1991 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1992 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1993 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1994
Rodrigo Vivid6a8b722014-11-05 16:56:36 -08001995 if (!USES_PPGTT(dev_priv->dev))
1996 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
1997 * so RTL will always use the value corresponding to
1998 * pat_sel = 000".
1999 * So let's disable cache for GGTT to avoid screen corruptions.
2000 * MOCS still can be used though.
2001 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2002 * before this patch, i.e. the same uncached + snooping access
2003 * like on gen6/7 seems to be in effect.
2004 * - So this just fixes blitter/render access. Again it looks
2005 * like it's not just uncached access, but uncached + snooping.
2006 * So we can still hold onto all our assumptions wrt cpu
2007 * clflushing on LLC machines.
2008 */
2009 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2010
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002011 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2012 * write would work. */
2013 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2014 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2015}
2016
Ville Syrjäläee0ce472014-04-09 13:28:01 +03002017static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2018{
2019 uint64_t pat;
2020
2021 /*
2022 * Map WB on BDW to snooped on CHV.
2023 *
2024 * Only the snoop bit has meaning for CHV, the rest is
2025 * ignored.
2026 *
Ville Syrjäläcf3d2622014-11-14 21:02:44 +02002027 * The hardware will never snoop for certain types of accesses:
2028 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2029 * - PPGTT page tables
2030 * - some other special cycles
2031 *
2032 * As with BDW, we also need to consider the following for GT accesses:
2033 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2034 * so RTL will always use the value corresponding to
2035 * pat_sel = 000".
2036 * Which means we must set the snoop bit in PAT entry 0
2037 * in order to keep the global status page working.
Ville Syrjäläee0ce472014-04-09 13:28:01 +03002038 */
2039 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2040 GEN8_PPAT(1, 0) |
2041 GEN8_PPAT(2, 0) |
2042 GEN8_PPAT(3, 0) |
2043 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2044 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2045 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2046 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2047
2048 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2049 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2050}
2051
Ben Widawsky63340132013-11-04 19:32:22 -08002052static int gen8_gmch_probe(struct drm_device *dev,
2053 size_t *gtt_total,
2054 size_t *stolen,
2055 phys_addr_t *mappable_base,
2056 unsigned long *mappable_end)
2057{
2058 struct drm_i915_private *dev_priv = dev->dev_private;
2059 unsigned int gtt_size;
2060 u16 snb_gmch_ctl;
2061 int ret;
2062
2063 /* TODO: We're not aware of mappable constraints on gen8 yet */
2064 *mappable_base = pci_resource_start(dev->pdev, 2);
2065 *mappable_end = pci_resource_len(dev->pdev, 2);
2066
2067 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2068 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2069
2070 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2071
Damien Lespiau66375012014-01-09 18:02:46 +00002072 if (INTEL_INFO(dev)->gen >= 9) {
2073 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2074 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2075 } else if (IS_CHERRYVIEW(dev)) {
Damien Lespiaud7f25f22014-05-08 22:19:40 +03002076 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2077 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2078 } else {
2079 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2080 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2081 }
Ben Widawsky63340132013-11-04 19:32:22 -08002082
Ben Widawskyd31eb102013-11-02 21:07:17 -07002083 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
Ben Widawsky63340132013-11-04 19:32:22 -08002084
Ville Syrjäläee0ce472014-04-09 13:28:01 +03002085 if (IS_CHERRYVIEW(dev))
2086 chv_setup_private_ppat(dev_priv);
2087 else
2088 bdw_setup_private_ppat(dev_priv);
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002089
Ben Widawsky63340132013-11-04 19:32:22 -08002090 ret = ggtt_probe_common(dev, gtt_size);
2091
Ben Widawsky94ec8f62013-11-02 21:07:18 -07002092 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2093 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
Ben Widawsky63340132013-11-04 19:32:22 -08002094
2095 return ret;
2096}
2097
Ben Widawskybaa09f52013-01-24 13:49:57 -08002098static int gen6_gmch_probe(struct drm_device *dev,
2099 size_t *gtt_total,
Ben Widawsky41907dd2013-02-08 11:32:47 -08002100 size_t *stolen,
2101 phys_addr_t *mappable_base,
2102 unsigned long *mappable_end)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002103{
2104 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002105 unsigned int gtt_size;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002106 u16 snb_gmch_ctl;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002107 int ret;
2108
Ben Widawsky41907dd2013-02-08 11:32:47 -08002109 *mappable_base = pci_resource_start(dev->pdev, 2);
2110 *mappable_end = pci_resource_len(dev->pdev, 2);
2111
Ben Widawskybaa09f52013-01-24 13:49:57 -08002112 /* 64/512MB is the current min/max we actually know of, but this is just
2113 * a coarse sanity check.
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002114 */
Ben Widawsky41907dd2013-02-08 11:32:47 -08002115 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
Ben Widawskybaa09f52013-01-24 13:49:57 -08002116 DRM_ERROR("Unknown GMADR size (%lx)\n",
2117 dev_priv->gtt.mappable_end);
2118 return -ENXIO;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002119 }
2120
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002121 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2122 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
Ben Widawskybaa09f52013-01-24 13:49:57 -08002123 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002124
Ben Widawskyc4ae25e2013-05-01 11:00:34 -07002125 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002126
Ben Widawsky63340132013-11-04 19:32:22 -08002127 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002128 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
2129
Ben Widawsky63340132013-11-04 19:32:22 -08002130 ret = ggtt_probe_common(dev, gtt_size);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002131
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002132 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2133 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002134
2135 return ret;
2136}
2137
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002138static void gen6_gmch_remove(struct i915_address_space *vm)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002139{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002140
2141 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
Ben Widawsky5ed16782013-11-25 09:54:43 -08002142
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002143 iounmap(gtt->gsm);
2144 teardown_scratch_page(vm->dev);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002145}
2146
2147static int i915_gmch_probe(struct drm_device *dev,
2148 size_t *gtt_total,
Ben Widawsky41907dd2013-02-08 11:32:47 -08002149 size_t *stolen,
2150 phys_addr_t *mappable_base,
2151 unsigned long *mappable_end)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002152{
2153 struct drm_i915_private *dev_priv = dev->dev_private;
2154 int ret;
2155
Ben Widawskybaa09f52013-01-24 13:49:57 -08002156 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2157 if (!ret) {
2158 DRM_ERROR("failed to set up gmch\n");
2159 return -EIO;
2160 }
2161
Ben Widawsky41907dd2013-02-08 11:32:47 -08002162 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002163
2164 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002165 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002166
Chris Wilsonc0a7f812013-12-30 12:16:15 +00002167 if (unlikely(dev_priv->gtt.do_idle_maps))
2168 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2169
Ben Widawskybaa09f52013-01-24 13:49:57 -08002170 return 0;
2171}
2172
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002173static void i915_gmch_remove(struct i915_address_space *vm)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002174{
2175 intel_gmch_remove();
2176}
2177
2178int i915_gem_gtt_init(struct drm_device *dev)
2179{
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 struct i915_gtt *gtt = &dev_priv->gtt;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002182 int ret;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002183
Ben Widawskybaa09f52013-01-24 13:49:57 -08002184 if (INTEL_INFO(dev)->gen <= 5) {
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002185 gtt->gtt_probe = i915_gmch_probe;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002186 gtt->base.cleanup = i915_gmch_remove;
Ben Widawsky63340132013-11-04 19:32:22 -08002187 } else if (INTEL_INFO(dev)->gen < 8) {
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002188 gtt->gtt_probe = gen6_gmch_probe;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002189 gtt->base.cleanup = gen6_gmch_remove;
Ben Widawsky4d15c142013-07-04 11:02:06 -07002190 if (IS_HASWELL(dev) && dev_priv->ellc_size)
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002191 gtt->base.pte_encode = iris_pte_encode;
Ben Widawsky4d15c142013-07-04 11:02:06 -07002192 else if (IS_HASWELL(dev))
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002193 gtt->base.pte_encode = hsw_pte_encode;
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002194 else if (IS_VALLEYVIEW(dev))
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002195 gtt->base.pte_encode = byt_pte_encode;
Chris Wilson350ec882013-08-06 13:17:02 +01002196 else if (INTEL_INFO(dev)->gen >= 7)
2197 gtt->base.pte_encode = ivb_pte_encode;
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002198 else
Chris Wilson350ec882013-08-06 13:17:02 +01002199 gtt->base.pte_encode = snb_pte_encode;
Ben Widawsky63340132013-11-04 19:32:22 -08002200 } else {
2201 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2202 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002203 }
2204
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002205 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002206 &gtt->mappable_base, &gtt->mappable_end);
Ben Widawskya54c0c22013-01-24 14:45:00 -08002207 if (ret)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002208 return ret;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002209
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002210 gtt->base.dev = dev;
2211
Ben Widawskybaa09f52013-01-24 13:49:57 -08002212 /* GMADR is the PCI mmio aperture into the global GTT. */
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002213 DRM_INFO("Memory usable by graphics device = %zdM\n",
2214 gtt->base.total >> 20);
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002215 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2216 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
Daniel Vetter5db6c732014-03-31 16:23:04 +02002217#ifdef CONFIG_INTEL_IOMMU
2218 if (intel_iommu_gfx_mapped)
2219 DRM_INFO("VT-d active for gfx access\n");
2220#endif
Daniel Vettercfa7c862014-04-29 11:53:58 +02002221 /*
2222 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2223 * user's requested state against the hardware/driver capabilities. We
2224 * do this now so that we can print out any log messages once rather
2225 * than every time we check intel_enable_ppgtt().
2226 */
2227 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2228 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002229
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002230 return 0;
Daniel Vetter644ec022012-03-26 09:45:40 +02002231}
Ben Widawsky6f65e292013-12-06 14:10:56 -08002232
2233static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002234 struct i915_address_space *vm,
2235 const struct i915_ggtt_view *view)
Ben Widawsky6f65e292013-12-06 14:10:56 -08002236{
2237 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2238 if (vma == NULL)
2239 return ERR_PTR(-ENOMEM);
2240
2241 INIT_LIST_HEAD(&vma->vma_link);
2242 INIT_LIST_HEAD(&vma->mm_list);
2243 INIT_LIST_HEAD(&vma->exec_list);
2244 vma->vm = vm;
2245 vma->obj = obj;
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002246 vma->ggtt_view = *view;
Ben Widawsky6f65e292013-12-06 14:10:56 -08002247
2248 switch (INTEL_INFO(vm->dev)->gen) {
Damien Lespiaufb8aad42014-01-16 16:42:32 +00002249 case 9:
Ben Widawsky6f65e292013-12-06 14:10:56 -08002250 case 8:
2251 case 7:
2252 case 6:
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08002253 if (i915_is_ggtt(vm)) {
2254 vma->unbind_vma = ggtt_unbind_vma;
2255 vma->bind_vma = ggtt_bind_vma;
2256 } else {
2257 vma->unbind_vma = ppgtt_unbind_vma;
2258 vma->bind_vma = ppgtt_bind_vma;
2259 }
Ben Widawsky6f65e292013-12-06 14:10:56 -08002260 break;
2261 case 5:
2262 case 4:
2263 case 3:
2264 case 2:
2265 BUG_ON(!i915_is_ggtt(vm));
2266 vma->unbind_vma = i915_ggtt_unbind_vma;
2267 vma->bind_vma = i915_ggtt_bind_vma;
2268 break;
2269 default:
2270 BUG();
2271 }
2272
Tvrtko Ursulinf7635662014-12-03 14:59:24 +00002273 list_add_tail(&vma->vma_link, &obj->vma_list);
2274 if (!i915_is_ggtt(vm))
Michel Thierrye07f0552014-08-19 15:49:41 +01002275 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
Ben Widawsky6f65e292013-12-06 14:10:56 -08002276
2277 return vma;
2278}
2279
2280struct i915_vma *
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002281i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj,
2282 struct i915_address_space *vm,
2283 const struct i915_ggtt_view *view)
Ben Widawsky6f65e292013-12-06 14:10:56 -08002284{
2285 struct i915_vma *vma;
2286
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002287 vma = i915_gem_obj_to_vma_view(obj, vm, view);
Ben Widawsky6f65e292013-12-06 14:10:56 -08002288 if (!vma)
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002289 vma = __i915_gem_vma_create(obj, vm, view);
Ben Widawsky6f65e292013-12-06 14:10:56 -08002290
2291 return vma;
2292}
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002293
2294static inline
2295int i915_get_vma_pages(struct i915_vma *vma)
2296{
2297 if (vma->ggtt_view.pages)
2298 return 0;
2299
2300 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2301 vma->ggtt_view.pages = vma->obj->pages;
2302 else
2303 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2304 vma->ggtt_view.type);
2305
2306 if (!vma->ggtt_view.pages) {
2307 DRM_ERROR("Failed to get pages for VMA view type %u!\n",
2308 vma->ggtt_view.type);
2309 return -EINVAL;
2310 }
2311
2312 return 0;
2313}
2314
2315/**
2316 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2317 * @vma: VMA to map
2318 * @cache_level: mapping cache level
2319 * @flags: flags like global or local mapping
2320 *
2321 * DMA addresses are taken from the scatter-gather table of this object (or of
2322 * this VMA in case of non-default GGTT views) and PTE entries set up.
2323 * Note that DMA addresses are also the only part of the SG table we care about.
2324 */
2325int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2326 u32 flags)
2327{
2328 int ret = i915_get_vma_pages(vma);
2329
2330 if (ret)
2331 return ret;
2332
2333 vma->bind_vma(vma, cache_level, flags);
2334
2335 return 0;
2336}