Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 29 | #include <linux/sysrq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
| 32 | #include "i915_drm.h" |
| 33 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 34 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 35 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | #define MAX_NOPID ((u32)~0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 39 | /** |
| 40 | * Interrupts that are always left unmasked. |
| 41 | * |
| 42 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, |
| 43 | * we leave them always unmasked in IMR and then control enabling them through |
| 44 | * PIPESTAT alone. |
| 45 | */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 46 | #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ |
| 47 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
| 48 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ |
| 49 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 50 | |
| 51 | /** Interrupts that we mask and unmask at runtime. */ |
| 52 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) |
| 53 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 54 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
| 55 | PIPE_VBLANK_INTERRUPT_STATUS) |
| 56 | |
| 57 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ |
| 58 | PIPE_VBLANK_INTERRUPT_ENABLE) |
| 59 | |
| 60 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ |
| 61 | DRM_I915_VBLANK_PIPE_B) |
| 62 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 63 | void |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 64 | igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 65 | { |
| 66 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { |
| 67 | dev_priv->gt_irq_mask_reg &= ~mask; |
| 68 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 69 | (void) I915_READ(GTIMR); |
| 70 | } |
| 71 | } |
| 72 | |
| 73 | static inline void |
| 74 | igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 75 | { |
| 76 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { |
| 77 | dev_priv->gt_irq_mask_reg |= mask; |
| 78 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 79 | (void) I915_READ(GTIMR); |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | /* For display hotplug interrupt */ |
| 84 | void |
| 85 | igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 86 | { |
| 87 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
| 88 | dev_priv->irq_mask_reg &= ~mask; |
| 89 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 90 | (void) I915_READ(DEIMR); |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | static inline void |
| 95 | igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 96 | { |
| 97 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
| 98 | dev_priv->irq_mask_reg |= mask; |
| 99 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 100 | (void) I915_READ(DEIMR); |
| 101 | } |
| 102 | } |
| 103 | |
| 104 | void |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 105 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 106 | { |
| 107 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
| 108 | dev_priv->irq_mask_reg &= ~mask; |
| 109 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 110 | (void) I915_READ(IMR); |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | static inline void |
| 115 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 116 | { |
| 117 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
| 118 | dev_priv->irq_mask_reg |= mask; |
| 119 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 120 | (void) I915_READ(IMR); |
| 121 | } |
| 122 | } |
| 123 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 124 | static inline u32 |
| 125 | i915_pipestat(int pipe) |
| 126 | { |
| 127 | if (pipe == 0) |
| 128 | return PIPEASTAT; |
| 129 | if (pipe == 1) |
| 130 | return PIPEBSTAT; |
Andrew Morton | 9c84ba4 | 2008-12-01 13:14:08 -0800 | [diff] [blame] | 131 | BUG(); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | void |
| 135 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 136 | { |
| 137 | if ((dev_priv->pipestat[pipe] & mask) != mask) { |
| 138 | u32 reg = i915_pipestat(pipe); |
| 139 | |
| 140 | dev_priv->pipestat[pipe] |= mask; |
| 141 | /* Enable the interrupt, clear any pending status */ |
| 142 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); |
| 143 | (void) I915_READ(reg); |
| 144 | } |
| 145 | } |
| 146 | |
| 147 | void |
| 148 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 149 | { |
| 150 | if ((dev_priv->pipestat[pipe] & mask) != 0) { |
| 151 | u32 reg = i915_pipestat(pipe); |
| 152 | |
| 153 | dev_priv->pipestat[pipe] &= ~mask; |
| 154 | I915_WRITE(reg, dev_priv->pipestat[pipe]); |
| 155 | (void) I915_READ(reg); |
| 156 | } |
| 157 | } |
| 158 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 159 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 160 | * i915_pipe_enabled - check if a pipe is enabled |
| 161 | * @dev: DRM device |
| 162 | * @pipe: pipe to check |
| 163 | * |
| 164 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 165 | * Use this routine to make sure the PLL is running and the pipe is active |
| 166 | * before reading such registers if unsure. |
| 167 | */ |
| 168 | static int |
| 169 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 170 | { |
| 171 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 172 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; |
| 173 | |
| 174 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) |
| 175 | return 1; |
| 176 | |
| 177 | return 0; |
| 178 | } |
| 179 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 180 | /* Called from drm generic code, passed a 'crtc', which |
| 181 | * we use as a pipe index |
| 182 | */ |
| 183 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 184 | { |
| 185 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 186 | unsigned long high_frame; |
| 187 | unsigned long low_frame; |
| 188 | u32 high1, high2, low, count; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 189 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 190 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
| 191 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; |
| 192 | |
| 193 | if (!i915_pipe_enabled(dev, pipe)) { |
Frans Pop | 6cb504c | 2009-08-09 12:25:29 +1000 | [diff] [blame] | 194 | DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 195 | return 0; |
| 196 | } |
| 197 | |
| 198 | /* |
| 199 | * High & low register fields aren't synchronized, so make sure |
| 200 | * we get a low value that's stable across two reads of the high |
| 201 | * register. |
| 202 | */ |
| 203 | do { |
| 204 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> |
| 205 | PIPE_FRAME_HIGH_SHIFT); |
| 206 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> |
| 207 | PIPE_FRAME_LOW_SHIFT); |
| 208 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> |
| 209 | PIPE_FRAME_HIGH_SHIFT); |
| 210 | } while (high1 != high2); |
| 211 | |
| 212 | count = (high1 << 8) | low; |
| 213 | |
| 214 | return count; |
| 215 | } |
| 216 | |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 217 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
| 218 | { |
| 219 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 220 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; |
| 221 | |
| 222 | if (!i915_pipe_enabled(dev, pipe)) { |
Frans Pop | 6cb504c | 2009-08-09 12:25:29 +1000 | [diff] [blame] | 223 | DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 224 | return 0; |
| 225 | } |
| 226 | |
| 227 | return I915_READ(reg); |
| 228 | } |
| 229 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 230 | /* |
| 231 | * Handle hotplug events outside the interrupt handler proper. |
| 232 | */ |
| 233 | static void i915_hotplug_work_func(struct work_struct *work) |
| 234 | { |
| 235 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 236 | hotplug_work); |
| 237 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 238 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 239 | struct drm_connector *connector; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 240 | |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 241 | if (mode_config->num_connector) { |
| 242 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 243 | struct intel_output *intel_output = to_intel_output(connector); |
| 244 | |
| 245 | if (intel_output->hot_plug) |
| 246 | (*intel_output->hot_plug) (intel_output); |
| 247 | } |
| 248 | } |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 249 | /* Just fire off a uevent and let userspace tell us what to do */ |
| 250 | drm_sysfs_hotplug_event(dev); |
| 251 | } |
| 252 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 253 | irqreturn_t igdng_irq_handler(struct drm_device *dev) |
| 254 | { |
| 255 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 256 | int ret = IRQ_NONE; |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame^] | 257 | u32 de_iir, gt_iir, de_ier; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 258 | u32 new_de_iir, new_gt_iir; |
| 259 | struct drm_i915_master_private *master_priv; |
| 260 | |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame^] | 261 | /* disable master interrupt before clearing iir */ |
| 262 | de_ier = I915_READ(DEIER); |
| 263 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
| 264 | (void)I915_READ(DEIER); |
| 265 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 266 | de_iir = I915_READ(DEIIR); |
| 267 | gt_iir = I915_READ(GTIIR); |
| 268 | |
| 269 | for (;;) { |
| 270 | if (de_iir == 0 && gt_iir == 0) |
| 271 | break; |
| 272 | |
| 273 | ret = IRQ_HANDLED; |
| 274 | |
| 275 | I915_WRITE(DEIIR, de_iir); |
| 276 | new_de_iir = I915_READ(DEIIR); |
| 277 | I915_WRITE(GTIIR, gt_iir); |
| 278 | new_gt_iir = I915_READ(GTIIR); |
| 279 | |
| 280 | if (dev->primary->master) { |
| 281 | master_priv = dev->primary->master->driver_priv; |
| 282 | if (master_priv->sarea_priv) |
| 283 | master_priv->sarea_priv->last_dispatch = |
| 284 | READ_BREADCRUMB(dev_priv); |
| 285 | } |
| 286 | |
| 287 | if (gt_iir & GT_USER_INTERRUPT) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 288 | u32 seqno = i915_get_gem_seqno(dev); |
| 289 | dev_priv->mm.irq_gem_seqno = seqno; |
| 290 | trace_i915_gem_request_complete(dev, seqno); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 291 | DRM_WAKEUP(&dev_priv->irq_queue); |
| 292 | } |
| 293 | |
| 294 | de_iir = new_de_iir; |
| 295 | gt_iir = new_gt_iir; |
| 296 | } |
| 297 | |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame^] | 298 | I915_WRITE(DEIER, de_ier); |
| 299 | (void)I915_READ(DEIER); |
| 300 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 301 | return ret; |
| 302 | } |
| 303 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 304 | /** |
| 305 | * i915_error_work_func - do process context error handling work |
| 306 | * @work: work struct |
| 307 | * |
| 308 | * Fire an error uevent so userspace can see that a hang or error |
| 309 | * was detected. |
| 310 | */ |
| 311 | static void i915_error_work_func(struct work_struct *work) |
| 312 | { |
| 313 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 314 | error_work); |
| 315 | struct drm_device *dev = dev_priv->dev; |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 316 | char *error_event[] = { "ERROR=1", NULL }; |
| 317 | char *reset_event[] = { "RESET=1", NULL }; |
| 318 | char *reset_done_event[] = { "ERROR=0", NULL }; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 319 | |
| 320 | DRM_DEBUG("generating error event\n"); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 321 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 322 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 323 | if (atomic_read(&dev_priv->mm.wedged)) { |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 324 | if (IS_I965G(dev)) { |
| 325 | DRM_DEBUG("resetting chip\n"); |
| 326 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
| 327 | if (!i965_reset(dev, GDRST_RENDER)) { |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 328 | atomic_set(&dev_priv->mm.wedged, 0); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 329 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
| 330 | } |
| 331 | } else { |
| 332 | printk("reboot required\n"); |
| 333 | } |
| 334 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | /** |
| 338 | * i915_capture_error_state - capture an error record for later analysis |
| 339 | * @dev: drm device |
| 340 | * |
| 341 | * Should be called when an error is detected (either a hang or an error |
| 342 | * interrupt) to capture error state from the time of the error. Fills |
| 343 | * out a structure which becomes available in debugfs for user level tools |
| 344 | * to pick up. |
| 345 | */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 346 | static void i915_capture_error_state(struct drm_device *dev) |
| 347 | { |
| 348 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 349 | struct drm_i915_error_state *error; |
| 350 | unsigned long flags; |
| 351 | |
| 352 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
| 353 | if (dev_priv->first_error) |
| 354 | goto out; |
| 355 | |
| 356 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
| 357 | if (!error) { |
| 358 | DRM_DEBUG("out ot memory, not capturing error state\n"); |
| 359 | goto out; |
| 360 | } |
| 361 | |
| 362 | error->eir = I915_READ(EIR); |
| 363 | error->pgtbl_er = I915_READ(PGTBL_ER); |
| 364 | error->pipeastat = I915_READ(PIPEASTAT); |
| 365 | error->pipebstat = I915_READ(PIPEBSTAT); |
| 366 | error->instpm = I915_READ(INSTPM); |
| 367 | if (!IS_I965G(dev)) { |
| 368 | error->ipeir = I915_READ(IPEIR); |
| 369 | error->ipehr = I915_READ(IPEHR); |
| 370 | error->instdone = I915_READ(INSTDONE); |
| 371 | error->acthd = I915_READ(ACTHD); |
| 372 | } else { |
| 373 | error->ipeir = I915_READ(IPEIR_I965); |
| 374 | error->ipehr = I915_READ(IPEHR_I965); |
| 375 | error->instdone = I915_READ(INSTDONE_I965); |
| 376 | error->instps = I915_READ(INSTPS); |
| 377 | error->instdone1 = I915_READ(INSTDONE1); |
| 378 | error->acthd = I915_READ(ACTHD_I965); |
| 379 | } |
| 380 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 381 | do_gettimeofday(&error->time); |
| 382 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 383 | dev_priv->first_error = error; |
| 384 | |
| 385 | out: |
| 386 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
| 387 | } |
| 388 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 389 | /** |
| 390 | * i915_handle_error - handle an error interrupt |
| 391 | * @dev: drm device |
| 392 | * |
| 393 | * Do some basic checking of regsiter state at error interrupt time and |
| 394 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 395 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 396 | * so userspace knows something bad happened (should trigger collection |
| 397 | * of a ring dump etc.). |
| 398 | */ |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 399 | static void i915_handle_error(struct drm_device *dev, bool wedged) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 400 | { |
| 401 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 402 | u32 eir = I915_READ(EIR); |
| 403 | u32 pipea_stats = I915_READ(PIPEASTAT); |
| 404 | u32 pipeb_stats = I915_READ(PIPEBSTAT); |
| 405 | |
| 406 | i915_capture_error_state(dev); |
| 407 | |
| 408 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", |
| 409 | eir); |
| 410 | |
| 411 | if (IS_G4X(dev)) { |
| 412 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 413 | u32 ipeir = I915_READ(IPEIR_I965); |
| 414 | |
| 415 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 416 | I915_READ(IPEIR_I965)); |
| 417 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 418 | I915_READ(IPEHR_I965)); |
| 419 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 420 | I915_READ(INSTDONE_I965)); |
| 421 | printk(KERN_ERR " INSTPS: 0x%08x\n", |
| 422 | I915_READ(INSTPS)); |
| 423 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", |
| 424 | I915_READ(INSTDONE1)); |
| 425 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 426 | I915_READ(ACTHD_I965)); |
| 427 | I915_WRITE(IPEIR_I965, ipeir); |
| 428 | (void)I915_READ(IPEIR_I965); |
| 429 | } |
| 430 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 431 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
| 432 | printk(KERN_ERR "page table error\n"); |
| 433 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", |
| 434 | pgtbl_err); |
| 435 | I915_WRITE(PGTBL_ER, pgtbl_err); |
| 436 | (void)I915_READ(PGTBL_ER); |
| 437 | } |
| 438 | } |
| 439 | |
| 440 | if (IS_I9XX(dev)) { |
| 441 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 442 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
| 443 | printk(KERN_ERR "page table error\n"); |
| 444 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", |
| 445 | pgtbl_err); |
| 446 | I915_WRITE(PGTBL_ER, pgtbl_err); |
| 447 | (void)I915_READ(PGTBL_ER); |
| 448 | } |
| 449 | } |
| 450 | |
| 451 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
| 452 | printk(KERN_ERR "memory refresh error\n"); |
| 453 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", |
| 454 | pipea_stats); |
| 455 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", |
| 456 | pipeb_stats); |
| 457 | /* pipestat has already been acked */ |
| 458 | } |
| 459 | if (eir & I915_ERROR_INSTRUCTION) { |
| 460 | printk(KERN_ERR "instruction error\n"); |
| 461 | printk(KERN_ERR " INSTPM: 0x%08x\n", |
| 462 | I915_READ(INSTPM)); |
| 463 | if (!IS_I965G(dev)) { |
| 464 | u32 ipeir = I915_READ(IPEIR); |
| 465 | |
| 466 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 467 | I915_READ(IPEIR)); |
| 468 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 469 | I915_READ(IPEHR)); |
| 470 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 471 | I915_READ(INSTDONE)); |
| 472 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 473 | I915_READ(ACTHD)); |
| 474 | I915_WRITE(IPEIR, ipeir); |
| 475 | (void)I915_READ(IPEIR); |
| 476 | } else { |
| 477 | u32 ipeir = I915_READ(IPEIR_I965); |
| 478 | |
| 479 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 480 | I915_READ(IPEIR_I965)); |
| 481 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 482 | I915_READ(IPEHR_I965)); |
| 483 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 484 | I915_READ(INSTDONE_I965)); |
| 485 | printk(KERN_ERR " INSTPS: 0x%08x\n", |
| 486 | I915_READ(INSTPS)); |
| 487 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", |
| 488 | I915_READ(INSTDONE1)); |
| 489 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 490 | I915_READ(ACTHD_I965)); |
| 491 | I915_WRITE(IPEIR_I965, ipeir); |
| 492 | (void)I915_READ(IPEIR_I965); |
| 493 | } |
| 494 | } |
| 495 | |
| 496 | I915_WRITE(EIR, eir); |
| 497 | (void)I915_READ(EIR); |
| 498 | eir = I915_READ(EIR); |
| 499 | if (eir) { |
| 500 | /* |
| 501 | * some errors might have become stuck, |
| 502 | * mask them. |
| 503 | */ |
| 504 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 505 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 506 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 507 | } |
| 508 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 509 | if (wedged) { |
| 510 | atomic_set(&dev_priv->mm.wedged, 1); |
| 511 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 512 | /* |
| 513 | * Wakeup waiting processes so they don't hang |
| 514 | */ |
| 515 | printk("i915: Waking up sleeping processes\n"); |
| 516 | DRM_WAKEUP(&dev_priv->irq_queue); |
| 517 | } |
| 518 | |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 519 | queue_work(dev_priv->wq, &dev_priv->error_work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 520 | } |
| 521 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 522 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
| 523 | { |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 524 | struct drm_device *dev = (struct drm_device *) arg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 525 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 526 | struct drm_i915_master_private *master_priv; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 527 | u32 iir, new_iir; |
| 528 | u32 pipea_stats, pipeb_stats; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 529 | u32 vblank_status; |
| 530 | u32 vblank_enable; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 531 | int vblank = 0; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 532 | unsigned long irqflags; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 533 | int irq_received; |
| 534 | int ret = IRQ_NONE; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 535 | |
Eric Anholt | 630681d | 2008-10-06 15:14:12 -0700 | [diff] [blame] | 536 | atomic_inc(&dev_priv->irq_received); |
| 537 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 538 | if (IS_IGDNG(dev)) |
| 539 | return igdng_irq_handler(dev); |
| 540 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 541 | iir = I915_READ(IIR); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 542 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 543 | if (IS_I965G(dev)) { |
| 544 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; |
| 545 | vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; |
| 546 | } else { |
| 547 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; |
| 548 | vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; |
| 549 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 550 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 551 | for (;;) { |
| 552 | irq_received = iir != 0; |
| 553 | |
| 554 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 555 | * have been cleared after the pipestat interrupt was received. |
| 556 | * It doesn't set the bit in iir again, but it still produces |
| 557 | * interrupts (for non-MSI). |
| 558 | */ |
| 559 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
| 560 | pipea_stats = I915_READ(PIPEASTAT); |
| 561 | pipeb_stats = I915_READ(PIPEBSTAT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 562 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 563 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 564 | i915_handle_error(dev, false); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 565 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 566 | /* |
| 567 | * Clear the PIPE(A|B)STAT regs before the IIR |
| 568 | */ |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 569 | if (pipea_stats & 0x8000ffff) { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 570 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
| 571 | DRM_DEBUG("pipe a underrun\n"); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 572 | I915_WRITE(PIPEASTAT, pipea_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 573 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 574 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 575 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 576 | if (pipeb_stats & 0x8000ffff) { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 577 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
| 578 | DRM_DEBUG("pipe b underrun\n"); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 579 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 580 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 581 | } |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 582 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
| 583 | |
| 584 | if (!irq_received) |
| 585 | break; |
| 586 | |
| 587 | ret = IRQ_HANDLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 588 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 589 | /* Consume port. Then clear IIR or we'll miss events */ |
| 590 | if ((I915_HAS_HOTPLUG(dev)) && |
| 591 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 592 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 593 | |
| 594 | DRM_DEBUG("hotplug event received, stat 0x%08x\n", |
| 595 | hotplug_status); |
| 596 | if (hotplug_status & dev_priv->hotplug_supported_mask) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 597 | queue_work(dev_priv->wq, |
| 598 | &dev_priv->hotplug_work); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 599 | |
| 600 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 601 | I915_READ(PORT_HOTPLUG_STAT); |
Shaohua Li | 0430296 | 2009-08-24 10:25:23 +0800 | [diff] [blame] | 602 | |
| 603 | /* EOS interrupts occurs */ |
| 604 | if (IS_IGD(dev) && |
| 605 | (hotplug_status & CRT_EOS_INT_STATUS)) { |
| 606 | u32 temp; |
| 607 | |
| 608 | DRM_DEBUG("EOS interrupt occurs\n"); |
| 609 | /* status is already cleared */ |
| 610 | temp = I915_READ(ADPA); |
| 611 | temp &= ~ADPA_DAC_ENABLE; |
| 612 | I915_WRITE(ADPA, temp); |
| 613 | |
| 614 | temp = I915_READ(PORT_HOTPLUG_EN); |
| 615 | temp &= ~CRT_EOS_INT_EN; |
| 616 | I915_WRITE(PORT_HOTPLUG_EN, temp); |
| 617 | |
| 618 | temp = I915_READ(PORT_HOTPLUG_STAT); |
| 619 | if (temp & CRT_EOS_INT_STATUS) |
| 620 | I915_WRITE(PORT_HOTPLUG_STAT, |
| 621 | CRT_EOS_INT_STATUS); |
| 622 | } |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 623 | } |
| 624 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 625 | I915_WRITE(IIR, iir); |
| 626 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 627 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 628 | if (dev->primary->master) { |
| 629 | master_priv = dev->primary->master->driver_priv; |
| 630 | if (master_priv->sarea_priv) |
| 631 | master_priv->sarea_priv->last_dispatch = |
| 632 | READ_BREADCRUMB(dev_priv); |
| 633 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 634 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 635 | if (iir & I915_USER_INTERRUPT) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 636 | u32 seqno = i915_get_gem_seqno(dev); |
| 637 | dev_priv->mm.irq_gem_seqno = seqno; |
| 638 | trace_i915_gem_request_complete(dev, seqno); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 639 | DRM_WAKEUP(&dev_priv->irq_queue); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 640 | dev_priv->hangcheck_count = 0; |
| 641 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 642 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 643 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 644 | if (pipea_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 645 | vblank++; |
| 646 | drm_handle_vblank(dev, 0); |
| 647 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 648 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 649 | if (pipeb_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 650 | vblank++; |
| 651 | drm_handle_vblank(dev, 1); |
| 652 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 653 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 654 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
| 655 | (iir & I915_ASLE_INTERRUPT)) |
| 656 | opregion_asle_intr(dev); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 657 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 658 | /* With MSI, interrupts are only generated when iir |
| 659 | * transitions from zero to nonzero. If another bit got |
| 660 | * set while we were handling the existing iir bits, then |
| 661 | * we would never get another interrupt. |
| 662 | * |
| 663 | * This is fine on non-MSI as well, as if we hit this path |
| 664 | * we avoid exiting the interrupt handler only to generate |
| 665 | * another one. |
| 666 | * |
| 667 | * Note that for MSI this could cause a stray interrupt report |
| 668 | * if an interrupt landed in the time between writing IIR and |
| 669 | * the posting read. This should be rare enough to never |
| 670 | * trigger the 99% of 100,000 interrupts test for disabling |
| 671 | * stray interrupts. |
| 672 | */ |
| 673 | iir = new_iir; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 674 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 675 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 676 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 677 | } |
| 678 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 679 | static int i915_emit_irq(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 680 | { |
| 681 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 682 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 683 | RING_LOCALS; |
| 684 | |
| 685 | i915_kernel_lost_context(dev); |
| 686 | |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 687 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 688 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 689 | dev_priv->counter++; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 690 | if (dev_priv->counter > 0x7FFFFFFFUL) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 691 | dev_priv->counter = 1; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 692 | if (master_priv->sarea_priv) |
| 693 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 694 | |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 695 | BEGIN_LP_RING(4); |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 696 | OUT_RING(MI_STORE_DWORD_INDEX); |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 697 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 698 | OUT_RING(dev_priv->counter); |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 699 | OUT_RING(MI_USER_INTERRUPT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 700 | ADVANCE_LP_RING(); |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 701 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 702 | return dev_priv->counter; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 703 | } |
| 704 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 705 | void i915_user_irq_get(struct drm_device *dev) |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 706 | { |
| 707 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 708 | unsigned long irqflags; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 709 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 710 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 711 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { |
| 712 | if (IS_IGDNG(dev)) |
| 713 | igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
| 714 | else |
| 715 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
| 716 | } |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 717 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 718 | } |
| 719 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 720 | void i915_user_irq_put(struct drm_device *dev) |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 721 | { |
| 722 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 723 | unsigned long irqflags; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 724 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 725 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 726 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 727 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { |
| 728 | if (IS_IGDNG(dev)) |
| 729 | igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
| 730 | else |
| 731 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
| 732 | } |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 733 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 734 | } |
| 735 | |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 736 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
| 737 | { |
| 738 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 739 | |
| 740 | if (dev_priv->trace_irq_seqno == 0) |
| 741 | i915_user_irq_get(dev); |
| 742 | |
| 743 | dev_priv->trace_irq_seqno = seqno; |
| 744 | } |
| 745 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 746 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | { |
| 748 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 749 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 750 | int ret = 0; |
| 751 | |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 752 | DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 753 | READ_BREADCRUMB(dev_priv)); |
| 754 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 755 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 756 | if (master_priv->sarea_priv) |
| 757 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 758 | return 0; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 759 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 760 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 761 | if (master_priv->sarea_priv) |
| 762 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 763 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 764 | i915_user_irq_get(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 765 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
| 766 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 767 | i915_user_irq_put(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 768 | |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 769 | if (ret == -EBUSY) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 770 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 771 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
| 772 | } |
| 773 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 774 | return ret; |
| 775 | } |
| 776 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 777 | /* Needs the lock as it touches the ring. |
| 778 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 779 | int i915_irq_emit(struct drm_device *dev, void *data, |
| 780 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 781 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 783 | drm_i915_irq_emit_t *emit = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 784 | int result; |
| 785 | |
Eric Anholt | 07f4f8b | 2009-04-16 13:46:12 -0700 | [diff] [blame] | 786 | if (!dev_priv || !dev_priv->ring.virtual_start) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 787 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 788 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 789 | } |
Eric Anholt | 299eb93 | 2009-02-24 22:14:12 -0800 | [diff] [blame] | 790 | |
| 791 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 792 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 793 | mutex_lock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 794 | result = i915_emit_irq(dev); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 795 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 796 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 797 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 798 | DRM_ERROR("copy_to_user\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 799 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 800 | } |
| 801 | |
| 802 | return 0; |
| 803 | } |
| 804 | |
| 805 | /* Doesn't need the hardware lock. |
| 806 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 807 | int i915_irq_wait(struct drm_device *dev, void *data, |
| 808 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 809 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 810 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 811 | drm_i915_irq_wait_t *irqwait = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 812 | |
| 813 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 814 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 815 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 816 | } |
| 817 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 818 | return i915_wait_irq(dev, irqwait->irq_seq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 819 | } |
| 820 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 821 | /* Called from drm generic code, passed 'crtc' which |
| 822 | * we use as a pipe index |
| 823 | */ |
| 824 | int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 825 | { |
| 826 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 827 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 828 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 829 | u32 pipeconf; |
| 830 | |
| 831 | pipeconf = I915_READ(pipeconf_reg); |
| 832 | if (!(pipeconf & PIPEACONF_ENABLE)) |
| 833 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 834 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 835 | if (IS_IGDNG(dev)) |
| 836 | return 0; |
| 837 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 838 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 839 | if (IS_I965G(dev)) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 840 | i915_enable_pipestat(dev_priv, pipe, |
| 841 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 842 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 843 | i915_enable_pipestat(dev_priv, pipe, |
| 844 | PIPE_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 845 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 846 | return 0; |
| 847 | } |
| 848 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 849 | /* Called from drm generic code, passed 'crtc' which |
| 850 | * we use as a pipe index |
| 851 | */ |
| 852 | void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 853 | { |
| 854 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 855 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 856 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 857 | if (IS_IGDNG(dev)) |
| 858 | return; |
| 859 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 860 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 861 | i915_disable_pipestat(dev_priv, pipe, |
| 862 | PIPE_VBLANK_INTERRUPT_ENABLE | |
| 863 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 864 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 865 | } |
| 866 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 867 | void i915_enable_interrupt (struct drm_device *dev) |
| 868 | { |
| 869 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | e170b03 | 2009-06-05 15:38:40 +0800 | [diff] [blame] | 870 | |
| 871 | if (!IS_IGDNG(dev)) |
| 872 | opregion_enable_asle(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 873 | dev_priv->irq_enabled = 1; |
| 874 | } |
| 875 | |
| 876 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 877 | /* Set the vblank monitor pipe |
| 878 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 879 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| 880 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 881 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 882 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 883 | |
| 884 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 885 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 886 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 887 | } |
| 888 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | 5b51694 | 2006-10-25 00:08:23 +1000 | [diff] [blame] | 889 | return 0; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 890 | } |
| 891 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 892 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 893 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 894 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 895 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 896 | drm_i915_vblank_pipe_t *pipe = data; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 897 | |
| 898 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 899 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 900 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 901 | } |
| 902 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 903 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 904 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 905 | return 0; |
| 906 | } |
| 907 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 908 | /** |
| 909 | * Schedule buffer swap at given vertical blank. |
| 910 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 911 | int i915_vblank_swap(struct drm_device *dev, void *data, |
| 912 | struct drm_file *file_priv) |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 913 | { |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 914 | /* The delayed swap mechanism was fundamentally racy, and has been |
| 915 | * removed. The model was that the client requested a delayed flip/swap |
| 916 | * from the kernel, then waited for vblank before continuing to perform |
| 917 | * rendering. The problem was that the kernel might wake the client |
| 918 | * up before it dispatched the vblank swap (since the lock has to be |
| 919 | * held while touching the ringbuffer), in which case the client would |
| 920 | * clear and start the next frame before the swap occurred, and |
| 921 | * flicker would occur in addition to likely missing the vblank. |
| 922 | * |
| 923 | * In the absence of this ioctl, userland falls back to a correct path |
| 924 | * of waiting for a vblank, then dispatching the swap on its own. |
| 925 | * Context switching to userland and back is plenty fast enough for |
| 926 | * meeting the requirements of vblank swapping. |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 927 | */ |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 928 | return -EINVAL; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 929 | } |
| 930 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 931 | struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) { |
| 932 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 933 | return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list); |
| 934 | } |
| 935 | |
| 936 | /** |
| 937 | * This is called when the chip hasn't reported back with completed |
| 938 | * batchbuffers in a long time. The first time this is called we simply record |
| 939 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses |
| 940 | * again, we assume the chip is wedged and try to fix it. |
| 941 | */ |
| 942 | void i915_hangcheck_elapsed(unsigned long data) |
| 943 | { |
| 944 | struct drm_device *dev = (struct drm_device *)data; |
| 945 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 946 | uint32_t acthd; |
| 947 | |
| 948 | if (!IS_I965G(dev)) |
| 949 | acthd = I915_READ(ACTHD); |
| 950 | else |
| 951 | acthd = I915_READ(ACTHD_I965); |
| 952 | |
| 953 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
| 954 | if (list_empty(&dev_priv->mm.request_list) || |
| 955 | i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) { |
| 956 | dev_priv->hangcheck_count = 0; |
| 957 | return; |
| 958 | } |
| 959 | |
| 960 | if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) { |
| 961 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 962 | i915_handle_error(dev, true); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 963 | return; |
| 964 | } |
| 965 | |
| 966 | /* Reset timer case chip hangs without another request being added */ |
| 967 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
| 968 | |
| 969 | if (acthd != dev_priv->last_acthd) |
| 970 | dev_priv->hangcheck_count = 0; |
| 971 | else |
| 972 | dev_priv->hangcheck_count++; |
| 973 | |
| 974 | dev_priv->last_acthd = acthd; |
| 975 | } |
| 976 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 977 | /* drm_dma.h hooks |
| 978 | */ |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 979 | static void igdng_irq_preinstall(struct drm_device *dev) |
| 980 | { |
| 981 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 982 | |
| 983 | I915_WRITE(HWSTAM, 0xeffe); |
| 984 | |
| 985 | /* XXX hotplug from PCH */ |
| 986 | |
| 987 | I915_WRITE(DEIMR, 0xffffffff); |
| 988 | I915_WRITE(DEIER, 0x0); |
| 989 | (void) I915_READ(DEIER); |
| 990 | |
| 991 | /* and GT */ |
| 992 | I915_WRITE(GTIMR, 0xffffffff); |
| 993 | I915_WRITE(GTIER, 0x0); |
| 994 | (void) I915_READ(GTIER); |
| 995 | } |
| 996 | |
| 997 | static int igdng_irq_postinstall(struct drm_device *dev) |
| 998 | { |
| 999 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1000 | /* enable kind of interrupts always enabled */ |
| 1001 | u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */; |
| 1002 | u32 render_mask = GT_USER_INTERRUPT; |
| 1003 | |
| 1004 | dev_priv->irq_mask_reg = ~display_mask; |
| 1005 | dev_priv->de_irq_enable_reg = display_mask; |
| 1006 | |
| 1007 | /* should always can generate irq */ |
| 1008 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 1009 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 1010 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); |
| 1011 | (void) I915_READ(DEIER); |
| 1012 | |
| 1013 | /* user interrupt should be enabled, but masked initial */ |
| 1014 | dev_priv->gt_irq_mask_reg = 0xffffffff; |
| 1015 | dev_priv->gt_irq_enable_reg = render_mask; |
| 1016 | |
| 1017 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1018 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 1019 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
| 1020 | (void) I915_READ(GTIER); |
| 1021 | |
| 1022 | return 0; |
| 1023 | } |
| 1024 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1025 | void i915_driver_irq_preinstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1026 | { |
| 1027 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1028 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1029 | atomic_set(&dev_priv->irq_received, 0); |
| 1030 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1031 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1032 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1033 | |
| 1034 | if (IS_IGDNG(dev)) { |
| 1035 | igdng_irq_preinstall(dev); |
| 1036 | return; |
| 1037 | } |
| 1038 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1039 | if (I915_HAS_HOTPLUG(dev)) { |
| 1040 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1041 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1042 | } |
| 1043 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1044 | I915_WRITE(HWSTAM, 0xeffe); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1045 | I915_WRITE(PIPEASTAT, 0); |
| 1046 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1047 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1048 | I915_WRITE(IER, 0x0); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1049 | (void) I915_READ(IER); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1050 | } |
| 1051 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1052 | int i915_driver_irq_postinstall(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1053 | { |
| 1054 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1055 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1056 | u32 error_mask; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1057 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1058 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
| 1059 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1060 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1061 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1062 | if (IS_IGDNG(dev)) |
| 1063 | return igdng_irq_postinstall(dev); |
| 1064 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1065 | /* Unmask the interrupts that we always want on. */ |
| 1066 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1067 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1068 | dev_priv->pipestat[0] = 0; |
| 1069 | dev_priv->pipestat[1] = 0; |
| 1070 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1071 | if (I915_HAS_HOTPLUG(dev)) { |
| 1072 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 1073 | |
| 1074 | /* Leave other bits alone */ |
| 1075 | hotplug_en |= HOTPLUG_EN_MASK; |
| 1076 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 1077 | |
| 1078 | dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS | |
| 1079 | TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS | |
| 1080 | SDVOB_HOTPLUG_INT_STATUS; |
| 1081 | if (IS_G4X(dev)) { |
| 1082 | dev_priv->hotplug_supported_mask |= |
| 1083 | HDMIB_HOTPLUG_INT_STATUS | |
| 1084 | HDMIC_HOTPLUG_INT_STATUS | |
| 1085 | HDMID_HOTPLUG_INT_STATUS; |
| 1086 | } |
| 1087 | /* Enable in IER... */ |
| 1088 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 1089 | /* and unmask in IMR */ |
| 1090 | i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); |
| 1091 | } |
| 1092 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1093 | /* |
| 1094 | * Enable some error detection, note the instruction error mask |
| 1095 | * bit is reserved, so we leave it masked. |
| 1096 | */ |
| 1097 | if (IS_G4X(dev)) { |
| 1098 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 1099 | GM45_ERROR_MEM_PRIV | |
| 1100 | GM45_ERROR_CP_PRIV | |
| 1101 | I915_ERROR_MEMORY_REFRESH); |
| 1102 | } else { |
| 1103 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 1104 | I915_ERROR_MEMORY_REFRESH); |
| 1105 | } |
| 1106 | I915_WRITE(EMR, error_mask); |
| 1107 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1108 | /* Disable pipe interrupt enables, clear pending pipe status */ |
| 1109 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
| 1110 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); |
| 1111 | /* Clear pending interrupt status */ |
| 1112 | I915_WRITE(IIR, I915_READ(IIR)); |
| 1113 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1114 | I915_WRITE(IER, enable_mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1115 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1116 | (void) I915_READ(IER); |
| 1117 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1118 | opregion_enable_asle(dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1119 | |
| 1120 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1121 | } |
| 1122 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1123 | static void igdng_irq_uninstall(struct drm_device *dev) |
| 1124 | { |
| 1125 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1126 | I915_WRITE(HWSTAM, 0xffffffff); |
| 1127 | |
| 1128 | I915_WRITE(DEIMR, 0xffffffff); |
| 1129 | I915_WRITE(DEIER, 0x0); |
| 1130 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 1131 | |
| 1132 | I915_WRITE(GTIMR, 0xffffffff); |
| 1133 | I915_WRITE(GTIER, 0x0); |
| 1134 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1135 | } |
| 1136 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1137 | void i915_driver_irq_uninstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1138 | { |
| 1139 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 1140 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1141 | if (!dev_priv) |
| 1142 | return; |
| 1143 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1144 | dev_priv->vblank_pipe = 0; |
| 1145 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1146 | if (IS_IGDNG(dev)) { |
| 1147 | igdng_irq_uninstall(dev); |
| 1148 | return; |
| 1149 | } |
| 1150 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1151 | if (I915_HAS_HOTPLUG(dev)) { |
| 1152 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1153 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1154 | } |
| 1155 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1156 | I915_WRITE(HWSTAM, 0xffffffff); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1157 | I915_WRITE(PIPEASTAT, 0); |
| 1158 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1159 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1160 | I915_WRITE(IER, 0x0); |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 1161 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1162 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
| 1163 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); |
| 1164 | I915_WRITE(IIR, I915_READ(IIR)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1165 | } |