blob: 06952aadfd7b5d4dccfff9f9689cd804031ab0eb [file] [log] [blame]
Ron Rindjunsky1053d352008-05-05 10:22:43 +08001/******************************************************************************
2 *
Emmanuel Grumbach51368bf2013-12-30 13:15:54 +02003 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
Johannes Berg8b4139d2014-07-24 14:05:26 +02004 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
Ron Rindjunsky1053d352008-05-05 10:22:43 +08005 *
6 * Portions of this file are derived from the ipw3945 project, as well
7 * as portions of the ieee80211 subsystem header files.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 *
22 * The full GNU General Public License is included in this distribution in the
23 * file called LICENSE.
24 *
25 * Contact Information:
Winkler, Tomas759ef892008-12-09 11:28:58 -080026 * Intel Linux Wireless <ilw@linux.intel.com>
Ron Rindjunsky1053d352008-05-05 10:22:43 +080027 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 *****************************************************************************/
Tomas Winklerfd4abac2008-05-15 13:54:07 +080030#include <linux/etherdevice.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Emmanuel Grumbach253a6342011-07-11 07:39:46 -070032#include <linux/sched.h>
Emmanuel Grumbach253a6342011-07-11 07:39:46 -070033
Emmanuel Grumbach522376d2011-09-06 09:31:19 -070034#include "iwl-debug.h"
35#include "iwl-csr.h"
36#include "iwl-prph.h"
Ron Rindjunsky1053d352008-05-05 10:22:43 +080037#include "iwl-io.h"
Avri Altman680073b2014-07-14 09:40:27 +030038#include "iwl-scd.h"
Emmanuel Grumbached277c92012-02-09 16:08:15 +020039#include "iwl-op-mode.h"
Johannes Berg6468a012012-05-16 19:13:54 +020040#include "internal.h"
Johannes Berg6238b002012-04-02 15:04:33 +020041/* FIXME: need to abstract out TX command (once we know what it looks like) */
Johannes Berg1023fdc2012-05-15 12:16:34 +020042#include "dvm/commands.h"
Ron Rindjunsky1053d352008-05-05 10:22:43 +080043
Emmanuel Grumbach522376d2011-09-06 09:31:19 -070044#define IWL_TX_CRC_SIZE 4
45#define IWL_TX_DELIMITER_SIZE 4
46
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +020047/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
48 * DMA services
49 *
50 * Theory of operation
51 *
52 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
53 * of buffer descriptors, each of which points to one or more data buffers for
54 * the device to read from or fill. Driver and device exchange status of each
55 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
56 * entries in each circular buffer, to protect against confusing empty and full
57 * queue states.
58 *
59 * The device reads or writes the data in the queues via the device's several
60 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
61 *
62 * For Tx queue, there are low mark and high mark limits. If, after queuing
63 * the packet for Tx, free space become < low mark, Tx queue stopped. When
64 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
65 * Tx queue resumed.
66 *
67 ***************************************************/
68static int iwl_queue_space(const struct iwl_queue *q)
69{
Ido Yariva9b29242013-07-15 11:51:48 -040070 unsigned int max;
71 unsigned int used;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +020072
Ido Yariva9b29242013-07-15 11:51:48 -040073 /*
74 * To avoid ambiguity between empty and completely full queues, there
Johannes Berg83f32a42014-04-24 09:57:40 +020075 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
76 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
77 * to reserve any queue entries for this purpose.
Ido Yariva9b29242013-07-15 11:51:48 -040078 */
Johannes Berg83f32a42014-04-24 09:57:40 +020079 if (q->n_window < TFD_QUEUE_SIZE_MAX)
Ido Yariva9b29242013-07-15 11:51:48 -040080 max = q->n_window;
81 else
Johannes Berg83f32a42014-04-24 09:57:40 +020082 max = TFD_QUEUE_SIZE_MAX - 1;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +020083
Ido Yariva9b29242013-07-15 11:51:48 -040084 /*
Johannes Berg83f32a42014-04-24 09:57:40 +020085 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
86 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
Ido Yariva9b29242013-07-15 11:51:48 -040087 */
Johannes Berg83f32a42014-04-24 09:57:40 +020088 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
Ido Yariva9b29242013-07-15 11:51:48 -040089
90 if (WARN_ON(used > max))
91 return 0;
92
93 return max - used;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +020094}
95
96/*
97 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
98 */
Johannes Berg83f32a42014-04-24 09:57:40 +020099static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200100{
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200101 q->n_window = slots_num;
102 q->id = id;
103
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200104 /* slots_num must be power-of-two size, otherwise
105 * get_cmd_index is broken. */
106 if (WARN_ON(!is_power_of_2(slots_num)))
107 return -EINVAL;
108
109 q->low_mark = q->n_window / 4;
110 if (q->low_mark < 4)
111 q->low_mark = 4;
112
113 q->high_mark = q->n_window / 8;
114 if (q->high_mark < 2)
115 q->high_mark = 2;
116
117 q->write_ptr = 0;
118 q->read_ptr = 0;
119
120 return 0;
121}
122
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200123static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
124 struct iwl_dma_ptr *ptr, size_t size)
125{
126 if (WARN_ON(ptr->addr))
127 return -EINVAL;
128
129 ptr->addr = dma_alloc_coherent(trans->dev, size,
130 &ptr->dma, GFP_KERNEL);
131 if (!ptr->addr)
132 return -ENOMEM;
133 ptr->size = size;
134 return 0;
135}
136
137static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
138 struct iwl_dma_ptr *ptr)
139{
140 if (unlikely(!ptr->addr))
141 return;
142
143 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
144 memset(ptr, 0, sizeof(*ptr));
145}
146
147static void iwl_pcie_txq_stuck_timer(unsigned long data)
148{
149 struct iwl_txq *txq = (void *)data;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200150 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
151 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
152 u32 scd_sram_addr = trans_pcie->scd_base_addr +
153 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
154 u8 buf[16];
155 int i;
156
157 spin_lock(&txq->lock);
158 /* check if triggered erroneously */
159 if (txq->q.read_ptr == txq->q.write_ptr) {
160 spin_unlock(&txq->lock);
161 return;
162 }
163 spin_unlock(&txq->lock);
164
165 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +0200166 jiffies_to_msecs(txq->wd_timeout));
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200167 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
168 txq->q.read_ptr, txq->q.write_ptr);
169
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +0200170 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200171
172 iwl_print_hex_error(trans, buf, sizeof(buf));
173
174 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
175 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
176 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
177
178 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
179 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
180 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
181 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
182 u32 tbl_dw =
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +0200183 iwl_trans_read_mem32(trans,
184 trans_pcie->scd_base_addr +
185 SCD_TRANS_TBL_OFFSET_QUEUE(i));
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200186
187 if (i & 0x1)
188 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
189 else
190 tbl_dw = tbl_dw & 0x0000FFFF;
191
192 IWL_ERR(trans,
193 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
194 i, active ? "" : "in", fifo, tbl_dw,
Johannes Berg83f32a42014-04-24 09:57:40 +0200195 iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
196 (TFD_QUEUE_SIZE_MAX - 1),
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200197 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
198 }
199
Liad Kaufman4c9706d2014-04-27 16:46:09 +0300200 iwl_force_nmi(trans);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200201}
202
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200203/*
204 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300205 */
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200206static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
207 struct iwl_txq *txq, u16 byte_cnt)
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300208{
Emmanuel Grumbach105183b2011-08-25 23:11:02 -0700209 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
Johannes Berg20d3b642012-05-16 22:54:29 +0200210 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300211 int write_ptr = txq->q.write_ptr;
212 int txq_id = txq->q.id;
213 u8 sec_ctl = 0;
214 u8 sta_id = 0;
215 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
216 __le16 bc_ent;
Emmanuel Grumbach132f98c2011-09-20 15:37:24 -0700217 struct iwl_tx_cmd *tx_cmd =
Johannes Bergbf8440e2012-03-19 17:12:06 +0100218 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300219
Emmanuel Grumbach105183b2011-08-25 23:11:02 -0700220 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
221
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300222 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
223
Emmanuel Grumbach132f98c2011-09-20 15:37:24 -0700224 sta_id = tx_cmd->sta_id;
225 sec_ctl = tx_cmd->sec_ctl;
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300226
227 switch (sec_ctl & TX_CMD_SEC_MSK) {
228 case TX_CMD_SEC_CCM:
Johannes Berg4325f6c2013-05-08 13:09:08 +0200229 len += IEEE80211_CCMP_MIC_LEN;
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300230 break;
231 case TX_CMD_SEC_TKIP:
Johannes Berg4325f6c2013-05-08 13:09:08 +0200232 len += IEEE80211_TKIP_ICV_LEN;
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300233 break;
234 case TX_CMD_SEC_WEP:
Johannes Berg4325f6c2013-05-08 13:09:08 +0200235 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300236 break;
237 }
238
Emmanuel Grumbach046db342012-12-05 15:07:54 +0200239 if (trans_pcie->bc_table_dword)
240 len = DIV_ROUND_UP(len, 4);
241
242 bc_ent = cpu_to_le16(len | (sta_id << 12));
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300243
244 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
245
246 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
247 scd_bc_tbl[txq_id].
248 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
249}
250
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200251static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
252 struct iwl_txq *txq)
253{
254 struct iwl_trans_pcie *trans_pcie =
255 IWL_TRANS_GET_PCIE_TRANS(trans);
256 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
257 int txq_id = txq->q.id;
258 int read_ptr = txq->q.read_ptr;
259 u8 sta_id = 0;
260 __le16 bc_ent;
261 struct iwl_tx_cmd *tx_cmd =
262 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
263
264 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
265
266 if (txq_id != trans_pcie->cmd_queue)
267 sta_id = tx_cmd->sta_id;
268
269 bc_ent = cpu_to_le16(1 | (sta_id << 12));
270 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
271
272 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
273 scd_bc_tbl[txq_id].
274 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
275}
276
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200277/*
278 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800279 */
Johannes Bergea68f462014-02-27 14:36:55 +0100280static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
281 struct iwl_txq *txq)
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800282{
Emmanuel Grumbach23e76d12014-01-20 09:50:29 +0200283 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800284 u32 reg = 0;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800285 int txq_id = txq->q.id;
286
Johannes Bergea68f462014-02-27 14:36:55 +0100287 lockdep_assert_held(&txq->lock);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800288
Eliad Peller50453882014-02-05 19:12:24 +0200289 /*
290 * explicitly wake up the NIC if:
291 * 1. shadow registers aren't enabled
292 * 2. NIC is woken up for CMD regardless of shadow outside this function
293 * 3. there is a chance that the NIC is asleep
294 */
295 if (!trans->cfg->base_params->shadow_reg_enable &&
296 txq_id != trans_pcie->cmd_queue &&
297 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
Wey-Yi Guyf81c1f42010-11-10 09:56:50 -0800298 /*
Eliad Peller50453882014-02-05 19:12:24 +0200299 * wake up nic if it's powered down ...
300 * uCode will wake up, and interrupt us again, so next
301 * time we'll skip this part.
Wey-Yi Guyf81c1f42010-11-10 09:56:50 -0800302 */
Eliad Peller50453882014-02-05 19:12:24 +0200303 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
304
305 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
306 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
307 txq_id, reg);
308 iwl_set_bit(trans, CSR_GP_CNTRL,
309 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
Johannes Bergea68f462014-02-27 14:36:55 +0100310 txq->need_update = true;
Eliad Peller50453882014-02-05 19:12:24 +0200311 return;
312 }
Wey-Yi Guyf81c1f42010-11-10 09:56:50 -0800313 }
Eliad Peller50453882014-02-05 19:12:24 +0200314
315 /*
316 * if not in power-save mode, uCode will never sleep when we're
317 * trying to tx (during RFKILL, we're not trying to tx).
318 */
319 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
320 iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
Johannes Bergea68f462014-02-27 14:36:55 +0100321}
Eliad Peller50453882014-02-05 19:12:24 +0200322
Johannes Bergea68f462014-02-27 14:36:55 +0100323void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
324{
325 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326 int i;
327
328 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
329 struct iwl_txq *txq = &trans_pcie->txq[i];
330
Emmanuel Grumbachd090f872014-05-13 08:10:51 +0300331 spin_lock_bh(&txq->lock);
Johannes Bergea68f462014-02-27 14:36:55 +0100332 if (trans_pcie->txq[i].need_update) {
333 iwl_pcie_txq_inc_wr_ptr(trans, txq);
334 trans_pcie->txq[i].need_update = false;
335 }
Emmanuel Grumbachd090f872014-05-13 08:10:51 +0300336 spin_unlock_bh(&txq->lock);
Johannes Bergea68f462014-02-27 14:36:55 +0100337 }
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800338}
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800339
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200340static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
Johannes Berg214d14d2011-05-04 07:50:44 -0700341{
342 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
343
344 dma_addr_t addr = get_unaligned_le32(&tb->lo);
345 if (sizeof(dma_addr_t) > sizeof(u32))
346 addr |=
347 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
348
349 return addr;
350}
351
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200352static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
353 dma_addr_t addr, u16 len)
Johannes Berg214d14d2011-05-04 07:50:44 -0700354{
355 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
356 u16 hi_n_len = len << 4;
357
358 put_unaligned_le32(addr, &tb->lo);
359 if (sizeof(dma_addr_t) > sizeof(u32))
360 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
361
362 tb->hi_n_len = cpu_to_le16(hi_n_len);
363
364 tfd->num_tbs = idx + 1;
365}
366
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200367static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
Johannes Berg214d14d2011-05-04 07:50:44 -0700368{
369 return tfd->num_tbs & 0x1f;
370}
371
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200372static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
Johannes Berg98891752013-02-26 11:28:19 +0100373 struct iwl_cmd_meta *meta,
374 struct iwl_tfd *tfd)
Johannes Berg214d14d2011-05-04 07:50:44 -0700375{
Johannes Berg214d14d2011-05-04 07:50:44 -0700376 int i;
377 int num_tbs;
378
Johannes Berg214d14d2011-05-04 07:50:44 -0700379 /* Sanity check on number of chunks */
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200380 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
Johannes Berg214d14d2011-05-04 07:50:44 -0700381
382 if (num_tbs >= IWL_NUM_OF_TBS) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700383 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
Johannes Berg214d14d2011-05-04 07:50:44 -0700384 /* @todo issue fatal error, it is quite serious situation */
385 return;
386 }
387
Johannes Berg38c0f3342013-02-27 13:18:50 +0100388 /* first TB is never freed - it's the scratchbuf data */
Johannes Berg214d14d2011-05-04 07:50:44 -0700389
Johannes Berg214d14d2011-05-04 07:50:44 -0700390 for (i = 1; i < num_tbs; i++)
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200391 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
Johannes Berg98891752013-02-26 11:28:19 +0100392 iwl_pcie_tfd_tb_get_len(tfd, i),
393 DMA_TO_DEVICE);
Emmanuel Grumbachebed6332012-05-16 22:35:58 +0200394
395 tfd->num_tbs = 0;
Johannes Berg4ce7cc22011-05-13 11:57:40 -0700396}
397
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200398/*
399 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700400 * @trans - transport private data
Johannes Berg4ce7cc22011-05-13 11:57:40 -0700401 * @txq - tx queue
Emmanuel Grumbachebed6332012-05-16 22:35:58 +0200402 * @dma_dir - the direction of the DMA mapping
Johannes Berg4ce7cc22011-05-13 11:57:40 -0700403 *
404 * Does NOT advance any TFD circular buffer read/write indexes
405 * Does NOT free the TFD itself (which is within circular buffer)
406 */
Johannes Berg98891752013-02-26 11:28:19 +0100407static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
Johannes Berg4ce7cc22011-05-13 11:57:40 -0700408{
409 struct iwl_tfd *tfd_tmp = txq->tfds;
Johannes Berg4ce7cc22011-05-13 11:57:40 -0700410
Johannes Berg83f32a42014-04-24 09:57:40 +0200411 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
412 * idx is bounded by n_window
413 */
Emmanuel Grumbachebed6332012-05-16 22:35:58 +0200414 int rd_ptr = txq->q.read_ptr;
415 int idx = get_cmd_index(&txq->q, rd_ptr);
416
Johannes Berg015c15e2012-03-05 11:24:24 -0800417 lockdep_assert_held(&txq->lock);
418
Johannes Berg83f32a42014-04-24 09:57:40 +0200419 /* We have only q->n_window txq->entries, but we use
420 * TFD_QUEUE_SIZE_MAX tfds
421 */
Johannes Berg98891752013-02-26 11:28:19 +0100422 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
Johannes Berg214d14d2011-05-04 07:50:44 -0700423
424 /* free SKB */
Johannes Bergbf8440e2012-03-19 17:12:06 +0100425 if (txq->entries) {
Johannes Berg214d14d2011-05-04 07:50:44 -0700426 struct sk_buff *skb;
427
Emmanuel Grumbachebed6332012-05-16 22:35:58 +0200428 skb = txq->entries[idx].skb;
Johannes Berg214d14d2011-05-04 07:50:44 -0700429
Emmanuel Grumbach909e9b22011-09-15 11:46:30 -0700430 /* Can be called from irqs-disabled context
431 * If skb is not NULL, it means that the whole queue is being
432 * freed and that the queue is not empty - free the skb
433 */
Johannes Berg214d14d2011-05-04 07:50:44 -0700434 if (skb) {
Emmanuel Grumbached277c92012-02-09 16:08:15 +0200435 iwl_op_mode_free_skb(trans->op_mode, skb);
Emmanuel Grumbachebed6332012-05-16 22:35:58 +0200436 txq->entries[idx].skb = NULL;
Johannes Berg214d14d2011-05-04 07:50:44 -0700437 }
438 }
439}
440
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200441static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
Johannes Berg6d6e68f2014-04-23 19:00:56 +0200442 dma_addr_t addr, u16 len, bool reset)
Johannes Berg214d14d2011-05-04 07:50:44 -0700443{
444 struct iwl_queue *q;
445 struct iwl_tfd *tfd, *tfd_tmp;
446 u32 num_tbs;
447
448 q = &txq->q;
Johannes Berg4ce7cc22011-05-13 11:57:40 -0700449 tfd_tmp = txq->tfds;
Johannes Berg214d14d2011-05-04 07:50:44 -0700450 tfd = &tfd_tmp[q->write_ptr];
451
452 if (reset)
453 memset(tfd, 0, sizeof(*tfd));
454
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200455 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
Johannes Berg214d14d2011-05-04 07:50:44 -0700456
457 /* Each TFD can point to a maximum 20 Tx buffers */
458 if (num_tbs >= IWL_NUM_OF_TBS) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700459 IWL_ERR(trans, "Error can not send more than %d chunks\n",
Johannes Berg20d3b642012-05-16 22:54:29 +0200460 IWL_NUM_OF_TBS);
Johannes Berg214d14d2011-05-04 07:50:44 -0700461 return -EINVAL;
462 }
463
Eliad Peller1092b9b2013-07-16 17:53:43 +0300464 if (WARN(addr & ~IWL_TX_DMA_MASK,
465 "Unaligned address = %llx\n", (unsigned long long)addr))
Johannes Berg214d14d2011-05-04 07:50:44 -0700466 return -EINVAL;
467
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200468 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
Johannes Berg214d14d2011-05-04 07:50:44 -0700469
470 return 0;
471}
472
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200473static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
474 struct iwl_txq *txq, int slots_num,
475 u32 txq_id)
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800476{
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200477 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
478 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
Johannes Berg38c0f3342013-02-27 13:18:50 +0100479 size_t scratchbuf_sz;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200480 int i;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800481
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200482 if (WARN_ON(txq->entries || txq->tfds))
483 return -EINVAL;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800484
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200485 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
486 (unsigned long)txq);
487 txq->trans_pcie = trans_pcie;
488
489 txq->q.n_window = slots_num;
490
491 txq->entries = kcalloc(slots_num,
492 sizeof(struct iwl_pcie_txq_entry),
493 GFP_KERNEL);
494
495 if (!txq->entries)
496 goto error;
497
498 if (txq_id == trans_pcie->cmd_queue)
499 for (i = 0; i < slots_num; i++) {
500 txq->entries[i].cmd =
501 kmalloc(sizeof(struct iwl_device_cmd),
502 GFP_KERNEL);
503 if (!txq->entries[i].cmd)
504 goto error;
505 }
506
507 /* Circular buffer of transmit frame descriptors (TFDs),
508 * shared with device */
509 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
510 &txq->q.dma_addr, GFP_KERNEL);
Joe Perchesd0320f72013-03-14 13:07:21 +0000511 if (!txq->tfds)
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200512 goto error;
Johannes Berg38c0f3342013-02-27 13:18:50 +0100513
514 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
515 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
516 sizeof(struct iwl_cmd_header) +
517 offsetof(struct iwl_tx_cmd, scratch));
518
519 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
520
521 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
522 &txq->scratchbufs_dma,
523 GFP_KERNEL);
524 if (!txq->scratchbufs)
525 goto err_free_tfds;
526
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200527 txq->q.id = txq_id;
528
529 return 0;
Johannes Berg38c0f3342013-02-27 13:18:50 +0100530err_free_tfds:
531 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200532error:
533 if (txq->entries && txq_id == trans_pcie->cmd_queue)
534 for (i = 0; i < slots_num; i++)
535 kfree(txq->entries[i].cmd);
536 kfree(txq->entries);
537 txq->entries = NULL;
538
539 return -ENOMEM;
540
541}
542
543static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
544 int slots_num, u32 txq_id)
545{
546 int ret;
547
Johannes Berg43aa6162014-02-27 14:24:36 +0100548 txq->need_update = false;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200549
550 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
551 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
552 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
553
554 /* Initialize queue's high/low-water marks, and head/tail indexes */
Johannes Berg83f32a42014-04-24 09:57:40 +0200555 ret = iwl_queue_init(&txq->q, slots_num, txq_id);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200556 if (ret)
557 return ret;
558
559 spin_lock_init(&txq->lock);
560
561 /*
562 * Tell nic where to find circular buffer of Tx Frame Descriptors for
563 * given Tx queue, and enable the DMA channel used for that queue.
564 * Circular buffer (TFD queue in DRAM) physical base address */
565 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
566 txq->q.dma_addr >> 8);
567
568 return 0;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800569}
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800570
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200571/*
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200572 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800573 */
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200574static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800575{
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200576 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
577 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
578 struct iwl_queue *q = &txq->q;
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800579
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200580 spin_lock_bh(&txq->lock);
581 while (q->write_ptr != q->read_ptr) {
Emmanuel Grumbachb9676132013-06-13 11:45:59 +0300582 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
583 txq_id, q->read_ptr);
Johannes Berg98891752013-02-26 11:28:19 +0100584 iwl_pcie_txq_free_tfd(trans, txq);
Johannes Berg83f32a42014-04-24 09:57:40 +0200585 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200586 }
Emmanuel Grumbachb9676132013-06-13 11:45:59 +0300587 txq->active = false;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200588 spin_unlock_bh(&txq->lock);
Emmanuel Grumbach8a487b12013-06-13 13:10:00 +0300589
590 /* just in case - this queue may have been stopped */
591 iwl_wake_queue(trans, txq);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200592}
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800593
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200594/*
595 * iwl_pcie_txq_free - Deallocate DMA queue.
596 * @txq: Transmit queue to deallocate.
597 *
598 * Empty queue by removing and destroying all BD's.
599 * Free all buffers.
600 * 0-fill, but do not free "txq" descriptor structure.
601 */
602static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
603{
604 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
605 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
606 struct device *dev = trans->dev;
607 int i;
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800608
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200609 if (WARN_ON(!txq))
610 return;
611
612 iwl_pcie_txq_unmap(trans, txq_id);
613
614 /* De-alloc array of command/tx buffers */
615 if (txq_id == trans_pcie->cmd_queue)
616 for (i = 0; i < txq->q.n_window; i++) {
Johannes Berg5d4185a2014-09-09 21:16:06 +0200617 kzfree(txq->entries[i].cmd);
618 kzfree(txq->entries[i].free_buf);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200619 }
620
621 /* De-alloc circular buffer of TFDs */
Johannes Berg83f32a42014-04-24 09:57:40 +0200622 if (txq->tfds) {
623 dma_free_coherent(dev,
624 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
625 txq->tfds, txq->q.dma_addr);
Johannes Bergd21fa2d2013-01-08 00:25:21 +0100626 txq->q.dma_addr = 0;
Johannes Berg83f32a42014-04-24 09:57:40 +0200627 txq->tfds = NULL;
Johannes Berg38c0f3342013-02-27 13:18:50 +0100628
629 dma_free_coherent(dev,
630 sizeof(*txq->scratchbufs) * txq->q.n_window,
631 txq->scratchbufs, txq->scratchbufs_dma);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200632 }
633
634 kfree(txq->entries);
635 txq->entries = NULL;
636
637 del_timer_sync(&txq->stuck_timer);
638
639 /* 0-fill queue descriptor structure */
640 memset(txq, 0, sizeof(*txq));
641}
642
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200643void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
644{
645 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Johannes Berg22dc3c92013-01-09 00:47:07 +0100646 int nq = trans->cfg->base_params->num_of_queues;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200647 int chan;
648 u32 reg_val;
Johannes Berg22dc3c92013-01-09 00:47:07 +0100649 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
650 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200651
652 /* make sure all queue are not stopped/used */
653 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
654 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
655
656 trans_pcie->scd_base_addr =
657 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
658
659 WARN_ON(scd_base_addr != 0 &&
660 scd_base_addr != trans_pcie->scd_base_addr);
661
Johannes Berg22dc3c92013-01-09 00:47:07 +0100662 /* reset context data, TX status and translation data */
663 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
664 SCD_CONTEXT_MEM_LOWER_BOUND,
665 NULL, clear_dwords);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200666
667 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
668 trans_pcie->scd_bc_tbls.dma >> 10);
669
670 /* The chain extension of the SCD doesn't work well. This feature is
671 * enabled by default by the HW, so we need to disable it manually.
672 */
Emmanuel Grumbache03bbb62014-04-13 10:49:16 +0300673 if (trans->cfg->base_params->scd_chain_ext_wa)
674 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200675
676 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +0200677 trans_pcie->cmd_fifo,
678 trans_pcie->cmd_q_wdg_timeout);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200679
680 /* Activate all Tx DMA/FIFO channels */
Avri Altman680073b2014-07-14 09:40:27 +0300681 iwl_scd_activate_fifos(trans);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200682
683 /* Enable DMA channel */
684 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
685 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
686 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
687 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
688
689 /* Update FH chicken bits */
690 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
691 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
692 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
693
694 /* Enable L1-Active */
Eran Harary3073d8c2013-12-29 14:09:59 +0200695 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
696 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
697 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200698}
699
Johannes Bergddaf5a52013-01-08 11:25:44 +0100700void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
701{
702 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
703 int txq_id;
704
705 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
706 txq_id++) {
707 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
708
709 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
710 txq->q.dma_addr >> 8);
711 iwl_pcie_txq_unmap(trans, txq_id);
712 txq->q.read_ptr = 0;
713 txq->q.write_ptr = 0;
714 }
715
716 /* Tell NIC where to find the "keep warm" buffer */
717 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
718 trans_pcie->kw.dma >> 4);
719
Emmanuel Grumbachcd8f4382015-01-29 21:34:00 +0200720 /*
721 * Send 0 as the scd_base_addr since the device may have be reset
722 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
723 * contain garbage.
724 */
725 iwl_pcie_tx_start(trans, 0);
Johannes Bergddaf5a52013-01-08 11:25:44 +0100726}
727
Emmanuel Grumbach36277232015-02-25 15:49:39 +0200728static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
729{
730 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
731 unsigned long flags;
732 int ch, ret;
733 u32 mask = 0;
734
735 spin_lock(&trans_pcie->irq_lock);
736
737 if (!iwl_trans_grab_nic_access(trans, false, &flags))
738 goto out;
739
740 /* Stop each Tx DMA channel */
741 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
742 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
743 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
744 }
745
746 /* Wait for DMA channels to be idle */
747 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
748 if (ret < 0)
749 IWL_ERR(trans,
750 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
751 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
752
753 iwl_trans_release_nic_access(trans, &flags);
754
755out:
756 spin_unlock(&trans_pcie->irq_lock);
757}
758
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200759/*
760 * iwl_pcie_tx_stop - Stop all Tx DMA channels
761 */
762int iwl_pcie_tx_stop(struct iwl_trans *trans)
763{
764 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach36277232015-02-25 15:49:39 +0200765 int txq_id;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200766
767 /* Turn off all Tx DMA fifos */
Avri Altman680073b2014-07-14 09:40:27 +0300768 iwl_scd_deactivate_fifos(trans);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200769
Emmanuel Grumbach36277232015-02-25 15:49:39 +0200770 /* Turn off all Tx DMA channels */
771 iwl_pcie_tx_stop_fh(trans);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200772
Emmanuel Grumbachfba1c622013-12-19 22:19:17 +0200773 /*
774 * This function can be called before the op_mode disabled the
775 * queues. This happens when we have an rfkill interrupt.
776 * Since we stop Tx altogether - mark the queues as stopped.
777 */
778 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
779 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
780
781 /* This can happen: start_hw, stop_device */
782 if (!trans_pcie->txq)
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200783 return 0;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200784
785 /* Unmap DMA from host system and free skb's */
786 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
787 txq_id++)
788 iwl_pcie_txq_unmap(trans, txq_id);
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800789
790 return 0;
791}
792
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200793/*
794 * iwl_trans_tx_free - Free TXQ Context
795 *
796 * Destroy all TX DMA queues and structures
797 */
798void iwl_pcie_tx_free(struct iwl_trans *trans)
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300799{
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200800 int txq_id;
801 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300802
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200803 /* Tx queues */
804 if (trans_pcie->txq) {
805 for (txq_id = 0;
806 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
807 iwl_pcie_txq_free(trans, txq_id);
808 }
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300809
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200810 kfree(trans_pcie->txq);
811 trans_pcie->txq = NULL;
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300812
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200813 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300814
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200815 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +0300816}
817
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200818/*
819 * iwl_pcie_tx_alloc - allocate TX context
820 * Allocate all Tx DMA structures and initialize them
821 */
822static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
823{
824 int ret;
825 int txq_id, slots_num;
826 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
827
828 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
829 sizeof(struct iwlagn_scd_bc_tbl);
830
831 /*It is not allowed to alloc twice, so warn when this happens.
832 * We cannot rely on the previous allocation, so free and fail */
833 if (WARN_ON(trans_pcie->txq)) {
834 ret = -EINVAL;
835 goto error;
836 }
837
838 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
839 scd_bc_tbls_size);
840 if (ret) {
841 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
842 goto error;
843 }
844
845 /* Alloc keep-warm buffer */
846 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
847 if (ret) {
848 IWL_ERR(trans, "Keep Warm allocation failed\n");
849 goto error;
850 }
851
852 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
853 sizeof(struct iwl_txq), GFP_KERNEL);
854 if (!trans_pcie->txq) {
855 IWL_ERR(trans, "Not enough memory for txq\n");
Dan Carpenter2ab9ba02013-08-11 02:03:21 +0300856 ret = -ENOMEM;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200857 goto error;
858 }
859
860 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
861 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
862 txq_id++) {
863 slots_num = (txq_id == trans_pcie->cmd_queue) ?
864 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
865 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
866 slots_num, txq_id);
867 if (ret) {
868 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
869 goto error;
870 }
871 }
872
873 return 0;
874
875error:
876 iwl_pcie_tx_free(trans);
877
878 return ret;
879}
880int iwl_pcie_tx_init(struct iwl_trans *trans)
881{
882 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
883 int ret;
884 int txq_id, slots_num;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200885 bool alloc = false;
886
887 if (!trans_pcie->txq) {
888 ret = iwl_pcie_tx_alloc(trans);
889 if (ret)
890 goto error;
891 alloc = true;
892 }
893
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +0200894 spin_lock(&trans_pcie->irq_lock);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200895
896 /* Turn off all Tx DMA fifos */
Avri Altman680073b2014-07-14 09:40:27 +0300897 iwl_scd_deactivate_fifos(trans);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200898
899 /* Tell NIC where to find the "keep warm" buffer */
900 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
901 trans_pcie->kw.dma >> 4);
902
Emmanuel Grumbach7b70bd62013-12-11 10:22:28 +0200903 spin_unlock(&trans_pcie->irq_lock);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200904
905 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
906 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
907 txq_id++) {
908 slots_num = (txq_id == trans_pcie->cmd_queue) ?
909 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
910 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
911 slots_num, txq_id);
912 if (ret) {
913 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
914 goto error;
915 }
916 }
917
Emmanuel Grumbachcb6bb122015-01-25 10:36:31 +0200918 if (trans->cfg->base_params->num_of_queues > 20)
919 iwl_set_bits_prph(trans, SCD_GP_CTRL,
920 SCD_GP_CTRL_ENABLE_31_QUEUES);
921
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200922 return 0;
923error:
924 /*Upon error, free only if we allocated something */
925 if (alloc)
926 iwl_pcie_tx_free(trans);
927 return ret;
928}
929
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +0200930static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200931{
Emmanuel Grumbache0b8d4052015-01-20 17:02:40 +0200932 lockdep_assert_held(&txq->lock);
933
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +0200934 if (!txq->wd_timeout)
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200935 return;
936
937 /*
Emmanuel Grumbache0b8d4052015-01-20 17:02:40 +0200938 * station is asleep and we send data - that must
939 * be uAPSD or PS-Poll. Don't rearm the timer.
940 */
941 if (txq->frozen)
942 return;
943
944 /*
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200945 * if empty delete timer, otherwise move timer forward
946 * since we're making progress on this queue
947 */
948 if (txq->q.read_ptr == txq->q.write_ptr)
949 del_timer(&txq->stuck_timer);
950 else
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +0200951 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200952}
953
954/* Frees buffers until index _not_ inclusive */
Emmanuel Grumbachf6d497c2012-11-14 23:32:57 +0200955void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
956 struct sk_buff_head *skbs)
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200957{
958 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
959 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
Johannes Berg83f32a42014-04-24 09:57:40 +0200960 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200961 struct iwl_queue *q = &txq->q;
962 int last_to_free;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200963
964 /* This function is not meant to release cmd queue*/
965 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
Emmanuel Grumbachf6d497c2012-11-14 23:32:57 +0200966 return;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200967
Johannes Berg2bfb5092012-12-27 21:43:48 +0100968 spin_lock_bh(&txq->lock);
Emmanuel Grumbachf6d497c2012-11-14 23:32:57 +0200969
Emmanuel Grumbachb9676132013-06-13 11:45:59 +0300970 if (!txq->active) {
971 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
972 txq_id, ssn);
973 goto out;
974 }
975
Emmanuel Grumbachf6d497c2012-11-14 23:32:57 +0200976 if (txq->q.read_ptr == tfd_num)
977 goto out;
978
979 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
980 txq_id, txq->q.read_ptr, tfd_num, ssn);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200981
982 /*Since we free until index _not_ inclusive, the one before index is
983 * the last we will free. This one must be used */
Johannes Berg83f32a42014-04-24 09:57:40 +0200984 last_to_free = iwl_queue_dec_wrap(tfd_num);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200985
Emmanuel Grumbach6ca6ebc2012-11-14 23:38:08 +0200986 if (!iwl_queue_used(q, last_to_free)) {
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200987 IWL_ERR(trans,
988 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
Johannes Berg83f32a42014-04-24 09:57:40 +0200989 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200990 q->write_ptr, q->read_ptr);
Emmanuel Grumbachf6d497c2012-11-14 23:32:57 +0200991 goto out;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200992 }
993
994 if (WARN_ON(!skb_queue_empty(skbs)))
Emmanuel Grumbachf6d497c2012-11-14 23:32:57 +0200995 goto out;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200996
997 for (;
Emmanuel Grumbachf6d497c2012-11-14 23:32:57 +0200998 q->read_ptr != tfd_num;
Johannes Berg83f32a42014-04-24 09:57:40 +0200999 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001000
1001 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
1002 continue;
1003
1004 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
1005
1006 txq->entries[txq->q.read_ptr].skb = NULL;
1007
1008 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1009
Johannes Berg98891752013-02-26 11:28:19 +01001010 iwl_pcie_txq_free_tfd(trans, txq);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001011 }
1012
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001013 iwl_pcie_txq_progress(txq);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001014
Emmanuel Grumbachf6d497c2012-11-14 23:32:57 +02001015 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1016 iwl_wake_queue(trans, txq);
Eliad Peller7616f332014-11-20 17:33:43 +02001017
1018 if (q->read_ptr == q->write_ptr) {
1019 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id);
1020 iwl_trans_pcie_unref(trans);
1021 }
1022
Emmanuel Grumbachf6d497c2012-11-14 23:32:57 +02001023out:
Johannes Berg2bfb5092012-12-27 21:43:48 +01001024 spin_unlock_bh(&txq->lock);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001025}
1026
Eliad Peller7616f332014-11-20 17:33:43 +02001027static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1028 const struct iwl_host_cmd *cmd)
Eliad Peller804d4c52014-11-20 14:36:26 +02001029{
1030 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1031 int ret;
1032
1033 lockdep_assert_held(&trans_pcie->reg_lock);
1034
Eliad Peller7616f332014-11-20 17:33:43 +02001035 if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1036 !trans_pcie->ref_cmd_in_flight) {
1037 trans_pcie->ref_cmd_in_flight = true;
1038 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1039 iwl_trans_pcie_ref(trans);
1040 }
1041
Eliad Peller804d4c52014-11-20 14:36:26 +02001042 if (trans_pcie->cmd_in_flight)
1043 return 0;
1044
1045 trans_pcie->cmd_in_flight = true;
1046
1047 /*
1048 * wake up the NIC to make sure that the firmware will see the host
1049 * command - we will let the NIC sleep once all the host commands
1050 * returned. This needs to be done only on NICs that have
1051 * apmg_wake_up_wa set.
1052 */
1053 if (trans->cfg->base_params->apmg_wake_up_wa) {
1054 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1055 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1056 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1057 udelay(2);
1058
1059 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1060 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1061 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1062 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1063 15000);
1064 if (ret < 0) {
1065 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1066 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1067 trans_pcie->cmd_in_flight = false;
1068 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1069 return -EIO;
1070 }
1071 }
1072
1073 return 0;
1074}
1075
1076static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
1077{
1078 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1079
1080 lockdep_assert_held(&trans_pcie->reg_lock);
1081
Eliad Peller7616f332014-11-20 17:33:43 +02001082 if (trans_pcie->ref_cmd_in_flight) {
1083 trans_pcie->ref_cmd_in_flight = false;
1084 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
1085 iwl_trans_pcie_unref(trans);
1086 }
1087
Eliad Peller804d4c52014-11-20 14:36:26 +02001088 if (WARN_ON(!trans_pcie->cmd_in_flight))
1089 return 0;
1090
1091 trans_pcie->cmd_in_flight = false;
1092
1093 if (trans->cfg->base_params->apmg_wake_up_wa)
1094 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1095 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1096
1097 return 0;
1098}
1099
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001100/*
1101 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1102 *
1103 * When FW advances 'R' index, all entries between old and new 'R' index
1104 * need to be reclaimed. As result, some free space forms. If there is
1105 * enough free space (> low mark), wake the stack that feeds us.
1106 */
1107static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1108{
1109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1110 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1111 struct iwl_queue *q = &txq->q;
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001112 unsigned long flags;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001113 int nfreed = 0;
1114
1115 lockdep_assert_held(&txq->lock);
1116
Johannes Berg83f32a42014-04-24 09:57:40 +02001117 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001118 IWL_ERR(trans,
1119 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
Johannes Berg83f32a42014-04-24 09:57:40 +02001120 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001121 q->write_ptr, q->read_ptr);
1122 return;
1123 }
1124
Johannes Berg83f32a42014-04-24 09:57:40 +02001125 for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1126 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001127
1128 if (nfreed++ > 0) {
1129 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1130 idx, q->write_ptr, q->read_ptr);
Liad Kaufman4c9706d2014-04-27 16:46:09 +03001131 iwl_force_nmi(trans);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001132 }
1133 }
1134
Eliad Peller804d4c52014-11-20 14:36:26 +02001135 if (q->read_ptr == q->write_ptr) {
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001136 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
Eliad Peller804d4c52014-11-20 14:36:26 +02001137 iwl_pcie_clear_cmd_in_flight(trans);
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001138 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1139 }
1140
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001141 iwl_pcie_txq_progress(txq);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001142}
1143
1144static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
Emmanuel Grumbach1ce86582012-06-04 16:48:17 +03001145 u16 txq_id)
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001146{
Johannes Berg20d3b642012-05-16 22:54:29 +02001147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001148 u32 tbl_dw_addr;
1149 u32 tbl_dw;
1150 u16 scd_q2ratid;
1151
1152 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1153
Emmanuel Grumbach105183b2011-08-25 23:11:02 -07001154 tbl_dw_addr = trans_pcie->scd_base_addr +
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001155 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1156
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001157 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001158
1159 if (txq_id & 0x1)
1160 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1161 else
1162 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1163
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001164 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001165
1166 return 0;
1167}
1168
Emmanuel Grumbachbd5f6a32013-04-28 14:05:22 +03001169/* Receiver address (actually, Rx station's index into station table),
1170 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1171#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1172
Johannes Bergfea77952014-08-01 11:58:47 +02001173void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001174 const struct iwl_trans_txq_scd_cfg *cfg,
1175 unsigned int wdg_timeout)
Johannes Berg70a18c52012-03-05 11:24:44 -08001176{
Johannes Berg9eae88f2012-03-15 13:26:52 -07001177 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001178 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
Johannes Bergd4578ea2014-08-01 12:17:40 +02001179 int fifo = -1;
Emmanuel Grumbach4beaf6c2012-05-29 11:29:10 +03001180
Johannes Berg9eae88f2012-03-15 13:26:52 -07001181 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1182 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001183
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001184 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1185
Johannes Bergd4578ea2014-08-01 12:17:40 +02001186 if (cfg) {
1187 fifo = cfg->fifo;
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001188
Avri Altman002a9e22014-07-24 19:25:10 +03001189 /* Disable the scheduler prior configuring the cmd queue */
Emmanuel Grumbach3a736bc2014-09-10 11:16:41 +03001190 if (txq_id == trans_pcie->cmd_queue &&
1191 trans_pcie->scd_set_active)
Avri Altman002a9e22014-07-24 19:25:10 +03001192 iwl_scd_enable_set_active(trans, 0);
1193
Johannes Bergd4578ea2014-08-01 12:17:40 +02001194 /* Stop this Tx queue before configuring it */
1195 iwl_scd_txq_set_inactive(trans, txq_id);
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001196
Johannes Bergd4578ea2014-08-01 12:17:40 +02001197 /* Set this queue as a chain-building queue unless it is CMD */
1198 if (txq_id != trans_pcie->cmd_queue)
1199 iwl_scd_txq_set_chain(trans, txq_id);
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001200
Johannes Berg64ba8932014-08-01 13:33:46 +02001201 if (cfg->aggregate) {
Johannes Bergd4578ea2014-08-01 12:17:40 +02001202 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
Emmanuel Grumbach4beaf6c2012-05-29 11:29:10 +03001203
Johannes Bergd4578ea2014-08-01 12:17:40 +02001204 /* Map receiver-address / traffic-ID to this queue */
1205 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
Emmanuel Grumbachf4772522013-07-24 14:15:21 +03001206
Johannes Bergd4578ea2014-08-01 12:17:40 +02001207 /* enable aggregations for the queue */
1208 iwl_scd_txq_enable_agg(trans, txq_id);
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001209 txq->ampdu = true;
Johannes Bergd4578ea2014-08-01 12:17:40 +02001210 } else {
1211 /*
1212 * disable aggregations for the queue, this will also
1213 * make the ra_tid mapping configuration irrelevant
1214 * since it is now a non-AGG queue.
1215 */
1216 iwl_scd_txq_disable_agg(trans, txq_id);
1217
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001218 ssn = txq->q.read_ptr;
Johannes Bergd4578ea2014-08-01 12:17:40 +02001219 }
Emmanuel Grumbach4beaf6c2012-05-29 11:29:10 +03001220 }
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001221
1222 /* Place first TFD at index corresponding to start sequence number.
1223 * Assumes that ssn_idx is valid (!= 0xFFF) */
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001224 txq->q.read_ptr = (ssn & 0xff);
1225 txq->q.write_ptr = (ssn & 0xff);
Emmanuel Grumbach0294d9e2015-01-05 16:52:55 +02001226 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1227 (ssn & 0xff) | (txq_id << 8));
Emmanuel Grumbach1ce86582012-06-04 16:48:17 +03001228
Johannes Bergd4578ea2014-08-01 12:17:40 +02001229 if (cfg) {
1230 u8 frame_limit = cfg->frame_limit;
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001231
Johannes Bergd4578ea2014-08-01 12:17:40 +02001232 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1233
1234 /* Set up Tx window size and frame limit for this queue */
1235 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1236 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1237 iwl_trans_write_mem32(trans,
1238 trans_pcie->scd_base_addr +
Johannes Berg9eae88f2012-03-15 13:26:52 -07001239 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1240 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
Johannes Bergd4578ea2014-08-01 12:17:40 +02001241 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
Johannes Berg9eae88f2012-03-15 13:26:52 -07001242 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
Johannes Bergd4578ea2014-08-01 12:17:40 +02001243 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001244
Johannes Bergd4578ea2014-08-01 12:17:40 +02001245 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1246 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1247 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1248 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1249 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1250 SCD_QUEUE_STTS_REG_MSK);
Avri Altman002a9e22014-07-24 19:25:10 +03001251
1252 /* enable the scheduler for this queue (only) */
Emmanuel Grumbach3a736bc2014-09-10 11:16:41 +03001253 if (txq_id == trans_pcie->cmd_queue &&
1254 trans_pcie->scd_set_active)
Avri Altman002a9e22014-07-24 19:25:10 +03001255 iwl_scd_enable_set_active(trans, BIT(txq_id));
Emmanuel Grumbach0294d9e2015-01-05 16:52:55 +02001256
1257 IWL_DEBUG_TX_QUEUES(trans,
1258 "Activate queue %d on FIFO %d WrPtr: %d\n",
1259 txq_id, fifo, ssn & 0xff);
1260 } else {
1261 IWL_DEBUG_TX_QUEUES(trans,
1262 "Activate queue %d WrPtr: %d\n",
1263 txq_id, ssn & 0xff);
Johannes Bergd4578ea2014-08-01 12:17:40 +02001264 }
1265
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001266 txq->active = true;
Emmanuel Grumbach4beaf6c2012-05-29 11:29:10 +03001267}
1268
Johannes Bergd4578ea2014-08-01 12:17:40 +02001269void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1270 bool configure_scd)
Emmanuel Grumbach288712a2011-08-25 23:11:25 -07001271{
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001272 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach986ea6c2012-09-30 16:25:43 +02001273 u32 stts_addr = trans_pcie->scd_base_addr +
1274 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1275 static const u32 zero_val[4] = {};
Emmanuel Grumbach288712a2011-08-25 23:11:25 -07001276
Emmanuel Grumbache0b8d4052015-01-20 17:02:40 +02001277 trans_pcie->txq[txq_id].frozen_expiry_remainder = 0;
1278 trans_pcie->txq[txq_id].frozen = false;
1279
Emmanuel Grumbachfba1c622013-12-19 22:19:17 +02001280 /*
1281 * Upon HW Rfkill - we stop the device, and then stop the queues
1282 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1283 * allow the op_mode to call txq_disable after it already called
1284 * stop_device.
1285 */
Johannes Berg9eae88f2012-03-15 13:26:52 -07001286 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
Emmanuel Grumbachfba1c622013-12-19 22:19:17 +02001287 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1288 "queue %d not used", txq_id);
Johannes Berg9eae88f2012-03-15 13:26:52 -07001289 return;
Emmanuel Grumbachbc237732011-11-21 13:25:31 +02001290 }
1291
Johannes Bergd4578ea2014-08-01 12:17:40 +02001292 if (configure_scd) {
1293 iwl_scd_txq_set_inactive(trans, txq_id);
Emmanuel Grumbachac928f82012-10-14 16:36:36 +02001294
Johannes Bergd4578ea2014-08-01 12:17:40 +02001295 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1296 ARRAY_SIZE(zero_val));
1297 }
Emmanuel Grumbach986ea6c2012-09-30 16:25:43 +02001298
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001299 iwl_pcie_txq_unmap(trans, txq_id);
Johannes Berg68972c42013-06-11 19:05:27 +02001300 trans_pcie->txq[txq_id].ampdu = false;
Emmanuel Grumbach6c3fd3f2012-10-18 12:38:37 +02001301
Emmanuel Grumbach1ce86582012-06-04 16:48:17 +03001302 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
Emmanuel Grumbach48d42c42011-07-10 10:47:01 +03001303}
1304
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001305/*************** HOST COMMAND QUEUE FUNCTIONS *****/
1306
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001307/*
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001308 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001309 * @priv: device private data point
Eliad Pellere89044d2013-07-16 17:33:26 +03001310 * @cmd: a pointer to the ucode command structure
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001311 *
Eliad Pellere89044d2013-07-16 17:33:26 +03001312 * The function returns < 0 values to indicate the operation
1313 * failed. On success, it returns the index (>= 0) of command in the
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001314 * command queue.
1315 */
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001316static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1317 struct iwl_host_cmd *cmd)
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001318{
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001319 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001320 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001321 struct iwl_queue *q = &txq->q;
Johannes Bergc2acea82009-07-24 11:13:05 -07001322 struct iwl_device_cmd *out_cmd;
1323 struct iwl_cmd_meta *out_meta;
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001324 unsigned long flags;
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001325 void *dup_buf = NULL;
Tomas Winklerf3674222008-08-04 16:00:44 +08001326 dma_addr_t phys_addr;
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001327 int idx;
Johannes Berg38c0f3342013-02-27 13:18:50 +01001328 u16 copy_size, cmd_size, scratch_size;
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001329 bool had_nocopy = false;
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001330 int i, ret;
Emmanuel Grumbach96791422012-07-24 01:58:32 +03001331 u32 cmd_pos;
Johannes Berg1afbfb62013-02-26 11:32:26 +01001332 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1333 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001334
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001335 copy_size = sizeof(out_cmd->hdr);
1336 cmd_size = sizeof(out_cmd->hdr);
1337
1338 /* need one for the header if the first is NOCOPY */
Johannes Berg1afbfb62013-02-26 11:32:26 +01001339 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001340
Johannes Berg1afbfb62013-02-26 11:32:26 +01001341 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
Johannes Berg8a964f42013-02-25 16:01:34 +01001342 cmddata[i] = cmd->data[i];
1343 cmdlen[i] = cmd->len[i];
1344
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001345 if (!cmd->len[i])
1346 continue;
Johannes Berg8a964f42013-02-25 16:01:34 +01001347
Johannes Berg38c0f3342013-02-27 13:18:50 +01001348 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1349 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1350 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
Johannes Berg8a964f42013-02-25 16:01:34 +01001351
1352 if (copy > cmdlen[i])
1353 copy = cmdlen[i];
1354 cmdlen[i] -= copy;
1355 cmddata[i] += copy;
1356 copy_size += copy;
1357 }
1358
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001359 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1360 had_nocopy = true;
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001361 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1362 idx = -EINVAL;
1363 goto free_dup_buf;
1364 }
1365 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1366 /*
1367 * This is also a chunk that isn't copied
1368 * to the static buffer so set had_nocopy.
1369 */
1370 had_nocopy = true;
1371
1372 /* only allowed once */
1373 if (WARN_ON(dup_buf)) {
1374 idx = -EINVAL;
1375 goto free_dup_buf;
1376 }
1377
Johannes Berg8a964f42013-02-25 16:01:34 +01001378 dup_buf = kmemdup(cmddata[i], cmdlen[i],
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001379 GFP_ATOMIC);
1380 if (!dup_buf)
1381 return -ENOMEM;
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001382 } else {
1383 /* NOCOPY must not be followed by normal! */
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001384 if (WARN_ON(had_nocopy)) {
1385 idx = -EINVAL;
1386 goto free_dup_buf;
1387 }
Johannes Berg8a964f42013-02-25 16:01:34 +01001388 copy_size += cmdlen[i];
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001389 }
1390 cmd_size += cmd->len[i];
1391 }
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001392
Johannes Berg3e41ace2011-04-18 09:12:37 -07001393 /*
1394 * If any of the command structures end up being larger than
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001395 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1396 * allocated into separate TFDs, then we will need to
1397 * increase the size of the buffers.
Johannes Berg3e41ace2011-04-18 09:12:37 -07001398 */
Johannes Berg2a79e452012-09-26 13:32:13 +02001399 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1400 "Command %s (%#x) is too large (%d bytes)\n",
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001401 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001402 idx = -EINVAL;
1403 goto free_dup_buf;
1404 }
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001405
Johannes Berg015c15e2012-03-05 11:24:24 -08001406 spin_lock_bh(&txq->lock);
Stanislaw Gruszka3598e172011-03-31 17:36:26 +02001407
Johannes Bergc2acea82009-07-24 11:13:05 -07001408 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
Johannes Berg015c15e2012-03-05 11:24:24 -08001409 spin_unlock_bh(&txq->lock);
Stanislaw Gruszka3598e172011-03-31 17:36:26 +02001410
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001411 IWL_ERR(trans, "No space in command queue\n");
Johannes Berg0e781842012-03-06 13:30:49 -08001412 iwl_op_mode_cmd_queue_full(trans->op_mode);
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001413 idx = -ENOSPC;
1414 goto free_dup_buf;
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001415 }
1416
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001417 idx = get_cmd_index(q, q->write_ptr);
Johannes Bergbf8440e2012-03-19 17:12:06 +01001418 out_cmd = txq->entries[idx].cmd;
1419 out_meta = &txq->entries[idx].meta;
Johannes Bergc2acea82009-07-24 11:13:05 -07001420
Daniel C Halperin8ce73f32009-07-31 14:28:06 -07001421 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
Johannes Bergc2acea82009-07-24 11:13:05 -07001422 if (cmd->flags & CMD_WANT_SKB)
1423 out_meta->source = cmd;
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001424
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001425 /* set up the header */
1426
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001427 out_cmd->hdr.cmd = cmd->id;
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001428 out_cmd->hdr.flags = 0;
Emmanuel Grumbachcefeaa52011-08-25 23:10:40 -07001429 out_cmd->hdr.sequence =
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08001430 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
Emmanuel Grumbachcefeaa52011-08-25 23:10:40 -07001431 INDEX_TO_SEQ(q->write_ptr));
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001432
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001433 /* and copy the data that needs to be copied */
Emmanuel Grumbach96791422012-07-24 01:58:32 +03001434 cmd_pos = offsetof(struct iwl_device_cmd, payload);
Johannes Berg8a964f42013-02-25 16:01:34 +01001435 copy_size = sizeof(out_cmd->hdr);
Johannes Berg1afbfb62013-02-26 11:32:26 +01001436 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
Johannes Berg4d075002014-04-24 10:41:31 +02001437 int copy;
Johannes Berg8a964f42013-02-25 16:01:34 +01001438
Emmanuel Grumbachcc904c72013-03-14 08:35:06 +02001439 if (!cmd->len[i])
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001440 continue;
Johannes Berg8a964f42013-02-25 16:01:34 +01001441
Johannes Berg4d075002014-04-24 10:41:31 +02001442 /* copy everything if not nocopy/dup */
1443 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1444 IWL_HCMD_DFL_DUP))) {
1445 copy = cmd->len[i];
1446
1447 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1448 cmd_pos += copy;
1449 copy_size += copy;
1450 continue;
1451 }
1452
1453 /*
1454 * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1455 * in total (for the scratchbuf handling), but copy up to what
1456 * we can fit into the payload for debug dump purposes.
1457 */
1458 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1459
1460 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1461 cmd_pos += copy;
1462
1463 /* However, treat copy_size the proper way, we need it below */
Johannes Berg38c0f3342013-02-27 13:18:50 +01001464 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1465 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
Johannes Berg8a964f42013-02-25 16:01:34 +01001466
1467 if (copy > cmd->len[i])
1468 copy = cmd->len[i];
Johannes Berg8a964f42013-02-25 16:01:34 +01001469 copy_size += copy;
1470 }
Emmanuel Grumbach96791422012-07-24 01:58:32 +03001471 }
1472
Johannes Bergd9fb6462012-03-26 08:23:39 -07001473 IWL_DEBUG_HC(trans,
Johannes Berg20d3b642012-05-16 22:54:29 +02001474 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001475 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
Johannes Berg20d3b642012-05-16 22:54:29 +02001476 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1477 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001478
Johannes Berg38c0f3342013-02-27 13:18:50 +01001479 /* start the TFD with the scratchbuf */
1480 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1481 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1482 iwl_pcie_txq_build_tfd(trans, txq,
1483 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
Johannes Berg6d6e68f2014-04-23 19:00:56 +02001484 scratch_size, true);
Johannes Berg8a964f42013-02-25 16:01:34 +01001485
Johannes Berg38c0f3342013-02-27 13:18:50 +01001486 /* map first command fragment, if any remains */
1487 if (copy_size > scratch_size) {
1488 phys_addr = dma_map_single(trans->dev,
1489 ((u8 *)&out_cmd->hdr) + scratch_size,
1490 copy_size - scratch_size,
1491 DMA_TO_DEVICE);
1492 if (dma_mapping_error(trans->dev, phys_addr)) {
1493 iwl_pcie_tfd_unmap(trans, out_meta,
1494 &txq->tfds[q->write_ptr]);
1495 idx = -ENOMEM;
1496 goto out;
1497 }
1498
1499 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
Johannes Berg6d6e68f2014-04-23 19:00:56 +02001500 copy_size - scratch_size, false);
Johannes Berg2c46f722011-04-28 07:27:10 -07001501 }
1502
Johannes Berg8a964f42013-02-25 16:01:34 +01001503 /* map the remaining (adjusted) nocopy/dup fragments */
Johannes Berg1afbfb62013-02-26 11:32:26 +01001504 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
Johannes Berg8a964f42013-02-25 16:01:34 +01001505 const void *data = cmddata[i];
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001506
Johannes Berg8a964f42013-02-25 16:01:34 +01001507 if (!cmdlen[i])
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001508 continue;
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001509 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1510 IWL_HCMD_DFL_DUP)))
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001511 continue;
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001512 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1513 data = dup_buf;
1514 phys_addr = dma_map_single(trans->dev, (void *)data,
Johannes Berg98891752013-02-26 11:28:19 +01001515 cmdlen[i], DMA_TO_DEVICE);
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001516 if (dma_mapping_error(trans->dev, phys_addr)) {
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001517 iwl_pcie_tfd_unmap(trans, out_meta,
Johannes Berg98891752013-02-26 11:28:19 +01001518 &txq->tfds[q->write_ptr]);
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001519 idx = -ENOMEM;
1520 goto out;
1521 }
1522
Johannes Berg6d6e68f2014-04-23 19:00:56 +02001523 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001524 }
Reinette Chatredf833b12009-04-21 10:55:48 -07001525
Emmanuel Grumbachafaf6b52011-07-08 08:46:09 -07001526 out_meta->flags = cmd->flags;
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001527 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
Johannes Berg5d4185a2014-09-09 21:16:06 +02001528 kzfree(txq->entries[idx].free_buf);
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001529 txq->entries[idx].free_buf = dup_buf;
Johannes Berg2c46f722011-04-28 07:27:10 -07001530
Johannes Berg8a964f42013-02-25 16:01:34 +01001531 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
Reinette Chatredf833b12009-04-21 10:55:48 -07001532
Johannes Berg7c5ba4a2012-04-09 17:46:54 -07001533 /* start timer if queue currently empty */
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001534 if (q->read_ptr == q->write_ptr && txq->wd_timeout)
1535 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
Johannes Berg7c5ba4a2012-04-09 17:46:54 -07001536
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001537 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
Eliad Peller7616f332014-11-20 17:33:43 +02001538 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
Eliad Peller804d4c52014-11-20 14:36:26 +02001539 if (ret < 0) {
1540 idx = ret;
1541 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1542 goto out;
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001543 }
1544
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001545 /* Increment and update queue's write index */
Johannes Berg83f32a42014-04-24 09:57:40 +02001546 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001547 iwl_pcie_txq_inc_wr_ptr(trans, txq);
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001548
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001549 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1550
Johannes Berg2c46f722011-04-28 07:27:10 -07001551 out:
Johannes Berg015c15e2012-03-05 11:24:24 -08001552 spin_unlock_bh(&txq->lock);
Johannes Bergf4feb8a2012-10-19 14:24:43 +02001553 free_dup_buf:
1554 if (idx < 0)
1555 kfree(dup_buf);
Abhijeet Kolekar7bfedc52010-02-03 13:47:56 -08001556 return idx;
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001557}
1558
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001559/*
1560 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
Tomas Winkler17b88922008-05-29 16:35:12 +08001561 * @rxb: Rx buffer to reclaim
Emmanuel Grumbach247c61d2011-09-20 15:37:23 -07001562 * @handler_status: return value of the handler of the command
1563 * (put in setup_rx_handlers)
Tomas Winkler17b88922008-05-29 16:35:12 +08001564 *
1565 * If an Rx buffer has an async callback associated with it the callback
1566 * will be executed. The attached skb (if present) will only be freed
1567 * if the callback returns 1
1568 */
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001569void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1570 struct iwl_rx_cmd_buffer *rxb, int handler_status)
Tomas Winkler17b88922008-05-29 16:35:12 +08001571{
Zhu Yi2f301222009-10-09 17:19:45 +08001572 struct iwl_rx_packet *pkt = rxb_addr(rxb);
Tomas Winkler17b88922008-05-29 16:35:12 +08001573 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1574 int txq_id = SEQ_TO_QUEUE(sequence);
1575 int index = SEQ_TO_INDEX(sequence);
Tomas Winkler17b88922008-05-29 16:35:12 +08001576 int cmd_index;
Johannes Bergc2acea82009-07-24 11:13:05 -07001577 struct iwl_device_cmd *cmd;
1578 struct iwl_cmd_meta *meta;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001579 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001580 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
Tomas Winkler17b88922008-05-29 16:35:12 +08001581
1582 /* If a Tx command is being handled and it isn't in the actual
1583 * command queue then there a command routing bug has been introduced
1584 * in the queue management code. */
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08001585 if (WARN(txq_id != trans_pcie->cmd_queue,
Johannes Berg13bb9482010-08-23 10:46:33 +02001586 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
Johannes Berg20d3b642012-05-16 22:54:29 +02001587 txq_id, trans_pcie->cmd_queue, sequence,
1588 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1589 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
Emmanuel Grumbach3e10cae2011-09-06 09:31:18 -07001590 iwl_print_hex_error(trans, pkt, 32);
Johannes Berg55d6a3c2008-09-23 19:18:43 +02001591 return;
Winkler, Tomas01ef93232008-11-07 09:58:45 -08001592 }
Tomas Winkler17b88922008-05-29 16:35:12 +08001593
Johannes Berg2bfb5092012-12-27 21:43:48 +01001594 spin_lock_bh(&txq->lock);
Johannes Berg015c15e2012-03-05 11:24:24 -08001595
Johannes Berg4ce7cc22011-05-13 11:57:40 -07001596 cmd_index = get_cmd_index(&txq->q, index);
Johannes Bergbf8440e2012-03-19 17:12:06 +01001597 cmd = txq->entries[cmd_index].cmd;
1598 meta = &txq->entries[cmd_index].meta;
Tomas Winkler17b88922008-05-29 16:35:12 +08001599
Johannes Berg98891752013-02-26 11:28:19 +01001600 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
Reinette Chatrec33de622009-10-30 14:36:10 -07001601
Tomas Winkler17b88922008-05-29 16:35:12 +08001602 /* Input error checking is done when commands are added to queue. */
Johannes Bergc2acea82009-07-24 11:13:05 -07001603 if (meta->flags & CMD_WANT_SKB) {
Johannes Berg48a2d662012-03-05 11:24:39 -08001604 struct page *p = rxb_steal_page(rxb);
Stanislaw Gruszka2624e962011-04-20 16:02:58 +02001605
Johannes Berg65b94a42012-03-05 11:24:38 -08001606 meta->source->resp_pkt = pkt;
1607 meta->source->_rx_page_addr = (unsigned long)page_address(p);
Johannes Bergb2cf4102012-04-09 17:46:51 -07001608 meta->source->_rx_page_order = trans_pcie->rx_page_order;
Johannes Berg65b94a42012-03-05 11:24:38 -08001609 meta->source->handler_status = handler_status;
Stanislaw Gruszka2624e962011-04-20 16:02:58 +02001610 }
Tomas Winkler17b88922008-05-29 16:35:12 +08001611
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001612 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
Tomas Winkler17b88922008-05-29 16:35:12 +08001613
Johannes Bergc2acea82009-07-24 11:13:05 -07001614 if (!(meta->flags & CMD_ASYNC)) {
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001615 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
Wey-Yi Guy05c89b92011-10-10 07:26:48 -07001616 IWL_WARN(trans,
1617 "HCMD_ACTIVE already clear for command %s\n",
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001618 get_cmd_string(trans_pcie, cmd->hdr.cmd));
Wey-Yi Guy05c89b92011-10-10 07:26:48 -07001619 }
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001620 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001621 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001622 get_cmd_string(trans_pcie, cmd->hdr.cmd));
Emmanuel Grumbachf946b522012-10-25 17:25:52 +02001623 wake_up(&trans_pcie->wait_command_queue);
Tomas Winkler17b88922008-05-29 16:35:12 +08001624 }
Stanislaw Gruszka3598e172011-03-31 17:36:26 +02001625
Zhu Yidd487442010-03-22 02:28:41 -07001626 meta->flags = 0;
Stanislaw Gruszka3598e172011-03-31 17:36:26 +02001627
Johannes Berg2bfb5092012-12-27 21:43:48 +01001628 spin_unlock_bh(&txq->lock);
Tomas Winkler17b88922008-05-29 16:35:12 +08001629}
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001630
Johannes Berg9439eac2013-10-09 09:59:25 +02001631#define HOST_COMPLETE_TIMEOUT (2 * HZ)
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001632
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001633static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1634 struct iwl_host_cmd *cmd)
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001635{
Johannes Bergd9fb6462012-03-26 08:23:39 -07001636 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001637 int ret;
1638
1639 /* An asynchronous command can not expect an SKB to be set. */
1640 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1641 return -EINVAL;
1642
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001643 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001644 if (ret < 0) {
Johannes Berg721c32f2012-03-06 13:30:40 -08001645 IWL_ERR(trans,
Todd Previteb36b1102011-11-10 06:55:02 -08001646 "Error sending %s: enqueue_hcmd failed: %d\n",
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001647 get_cmd_string(trans_pcie, cmd->id), ret);
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001648 return ret;
1649 }
1650 return 0;
1651}
1652
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001653static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1654 struct iwl_host_cmd *cmd)
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001655{
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001656 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001657 int cmd_idx;
1658 int ret;
1659
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001660 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001661 get_cmd_string(trans_pcie, cmd->id));
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001662
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001663 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1664 &trans->status),
Johannes Bergbcbb8c92013-10-28 15:50:55 +01001665 "Command %s: a command is already active!\n",
1666 get_cmd_string(trans_pcie, cmd->id)))
Johannes Berg2cc39c92012-03-06 13:30:41 -08001667 return -EIO;
Johannes Berg2cc39c92012-03-06 13:30:41 -08001668
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001669 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001670 get_cmd_string(trans_pcie, cmd->id));
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001671
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001672 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001673 if (cmd_idx < 0) {
1674 ret = cmd_idx;
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001675 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
Johannes Berg721c32f2012-03-06 13:30:40 -08001676 IWL_ERR(trans,
Todd Previteb36b1102011-11-10 06:55:02 -08001677 "Error sending %s: enqueue_hcmd failed: %d\n",
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001678 get_cmd_string(trans_pcie, cmd->id), ret);
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001679 return ret;
1680 }
1681
Emmanuel Grumbachb9439492013-12-22 15:09:40 +02001682 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1683 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1684 &trans->status),
1685 HOST_COMPLETE_TIMEOUT);
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001686 if (!ret) {
Johannes Berg6dde8c42013-10-31 18:30:38 +01001687 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1688 struct iwl_queue *q = &txq->q;
Wey-Yi Guyd10630a2011-10-10 07:26:46 -07001689
Johannes Berg6dde8c42013-10-31 18:30:38 +01001690 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1691 get_cmd_string(trans_pcie, cmd->id),
1692 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001693
Johannes Berg6dde8c42013-10-31 18:30:38 +01001694 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1695 q->read_ptr, q->write_ptr);
Wey-Yi Guyd10630a2011-10-10 07:26:46 -07001696
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001697 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
Johannes Berg6dde8c42013-10-31 18:30:38 +01001698 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1699 get_cmd_string(trans_pcie, cmd->id));
1700 ret = -ETIMEDOUT;
Emmanuel Grumbach42550a52013-09-11 14:16:20 +03001701
Liad Kaufman4c9706d2014-04-27 16:46:09 +03001702 iwl_force_nmi(trans);
Arik Nemtsov2a988e92013-12-01 13:50:40 +02001703 iwl_trans_fw_error(trans);
Emmanuel Grumbach42550a52013-09-11 14:16:20 +03001704
Johannes Berg6dde8c42013-10-31 18:30:38 +01001705 goto cancel;
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001706 }
1707
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001708 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
Johannes Bergd18aa872012-11-06 16:36:21 +01001709 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001710 get_cmd_string(trans_pcie, cmd->id));
Johannes Bergb656fa32013-05-03 11:56:17 +02001711 dump_stack();
Johannes Bergd18aa872012-11-06 16:36:21 +01001712 ret = -EIO;
1713 goto cancel;
1714 }
1715
Eran Harary1094fa22013-06-02 12:40:34 +03001716 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001717 test_bit(STATUS_RFKILL, &trans->status)) {
Emmanuel Grumbachf946b522012-10-25 17:25:52 +02001718 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1719 ret = -ERFKILL;
1720 goto cancel;
1721 }
1722
Johannes Berg65b94a42012-03-05 11:24:38 -08001723 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -07001724 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001725 get_cmd_string(trans_pcie, cmd->id));
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001726 ret = -EIO;
1727 goto cancel;
1728 }
1729
1730 return 0;
1731
1732cancel:
1733 if (cmd->flags & CMD_WANT_SKB) {
1734 /*
1735 * Cancel the CMD_WANT_SKB flag for the cmd in the
1736 * TX cmd queue. Otherwise in case the cmd comes
1737 * in later, it will possibly set an invalid
1738 * address (cmd->meta.source).
1739 */
Johannes Bergbf8440e2012-03-19 17:12:06 +01001740 trans_pcie->txq[trans_pcie->cmd_queue].
1741 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001742 }
Emmanuel Grumbach9cac4942011-11-10 06:55:20 -08001743
Johannes Berg65b94a42012-03-05 11:24:38 -08001744 if (cmd->resp_pkt) {
1745 iwl_free_resp(cmd);
1746 cmd->resp_pkt = NULL;
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001747 }
1748
1749 return ret;
1750}
1751
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001752int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001753{
Eran Harary4f593342013-05-13 07:53:26 +03001754 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
Arik Nemtsoveb7ff772013-12-01 12:30:38 +02001755 test_bit(STATUS_RFKILL, &trans->status)) {
Emmanuel Grumbach754d7d92013-03-13 22:16:20 +02001756 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1757 cmd->id);
Emmanuel Grumbachf946b522012-10-25 17:25:52 +02001758 return -ERFKILL;
Emmanuel Grumbach754d7d92013-03-13 22:16:20 +02001759 }
Emmanuel Grumbachf946b522012-10-25 17:25:52 +02001760
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001761 if (cmd->flags & CMD_ASYNC)
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001762 return iwl_pcie_send_hcmd_async(trans, cmd);
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001763
Emmanuel Grumbachf946b522012-10-25 17:25:52 +02001764 /* We still can fail on RFKILL that can be asserted while we wait */
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001765 return iwl_pcie_send_hcmd_sync(trans, cmd);
Emmanuel Grumbach253a6342011-07-11 07:39:46 -07001766}
1767
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001768int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1769 struct iwl_device_cmd *dev_cmd, int txq_id)
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001770{
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001771 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001772 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1773 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1774 struct iwl_cmd_meta *out_meta;
1775 struct iwl_txq *txq;
1776 struct iwl_queue *q;
Johannes Berg38c0f3342013-02-27 13:18:50 +01001777 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1778 void *tb1_addr;
1779 u16 len, tb1_len, tb2_len;
Johannes Bergea68f462014-02-27 14:36:55 +01001780 bool wait_write_ptr;
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001781 __le16 fc = hdr->frame_control;
1782 u8 hdr_len = ieee80211_hdrlen(fc);
Johannes Berg68972c42013-06-11 19:05:27 +02001783 u16 wifi_seq;
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001784
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001785 txq = &trans_pcie->txq[txq_id];
1786 q = &txq->q;
Emmanuel Grumbach39644e92011-09-15 11:46:29 -07001787
Johannes Berg961de6a2013-07-04 18:00:08 +02001788 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1789 "TX on unused queue %d\n", txq_id))
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001790 return -EINVAL;
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001791
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001792 spin_lock(&txq->lock);
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001793
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001794 /* In AGG mode, the index in the ring must correspond to the WiFi
1795 * sequence number. This is a HW requirements to help the SCD to parse
1796 * the BA.
1797 * Check here that the packets are in the right place on the ring.
1798 */
Johannes Berg9a886582013-02-15 19:25:00 +01001799 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
Eliad Peller1092b9b2013-07-16 17:53:43 +03001800 WARN_ONCE(txq->ampdu &&
Johannes Berg68972c42013-06-11 19:05:27 +02001801 (wifi_seq & 0xff) != q->write_ptr,
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001802 "Q: %d WiFi Seq %d tfdNum %d",
1803 txq_id, wifi_seq, q->write_ptr);
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001804
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001805 /* Set up driver data for this TFD */
1806 txq->entries[q->write_ptr].skb = skb;
1807 txq->entries[q->write_ptr].cmd = dev_cmd;
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001808
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001809 dev_cmd->hdr.sequence =
1810 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1811 INDEX_TO_SEQ(q->write_ptr)));
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001812
Johannes Berg38c0f3342013-02-27 13:18:50 +01001813 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1814 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1815 offsetof(struct iwl_tx_cmd, scratch);
1816
1817 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1818 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1819
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001820 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1821 out_meta = &txq->entries[q->write_ptr].meta;
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001822
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001823 /*
Johannes Berg38c0f3342013-02-27 13:18:50 +01001824 * The second TB (tb1) points to the remainder of the TX command
1825 * and the 802.11 header - dword aligned size
1826 * (This calculation modifies the TX command, so do it before the
1827 * setup of the first TB)
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001828 */
Johannes Berg38c0f3342013-02-27 13:18:50 +01001829 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1830 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
Eliad Peller1092b9b2013-07-16 17:53:43 +03001831 tb1_len = ALIGN(len, 4);
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001832
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001833 /* Tell NIC about any 2-byte padding after MAC header */
Johannes Berg38c0f3342013-02-27 13:18:50 +01001834 if (tb1_len != len)
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001835 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1836
Johannes Berg38c0f3342013-02-27 13:18:50 +01001837 /* The first TB points to the scratchbuf data - min_copy bytes */
1838 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1839 IWL_HCMD_SCRATCHBUF_SIZE);
1840 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
Johannes Berg6d6e68f2014-04-23 19:00:56 +02001841 IWL_HCMD_SCRATCHBUF_SIZE, true);
Johannes Berg38c0f3342013-02-27 13:18:50 +01001842
1843 /* there must be data left over for TB1 or this code must be changed */
1844 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1845
1846 /* map the data for TB1 */
1847 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1848 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1849 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001850 goto out_err;
Johannes Berg6d6e68f2014-04-23 19:00:56 +02001851 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
Johannes Berg38c0f3342013-02-27 13:18:50 +01001852
1853 /*
1854 * Set up TFD's third entry to point directly to remainder
1855 * of skb, if any (802.11 null frames have no payload).
1856 */
1857 tb2_len = skb->len - hdr_len;
1858 if (tb2_len > 0) {
1859 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1860 skb->data + hdr_len,
1861 tb2_len, DMA_TO_DEVICE);
1862 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1863 iwl_pcie_tfd_unmap(trans, out_meta,
1864 &txq->tfds[q->write_ptr]);
1865 goto out_err;
1866 }
Johannes Berg6d6e68f2014-04-23 19:00:56 +02001867 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
Johannes Berg38c0f3342013-02-27 13:18:50 +01001868 }
1869
1870 /* Set up entry for this TFD in Tx byte-count array */
1871 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1872
1873 trace_iwlwifi_dev_tx(trans->dev, skb,
1874 &txq->tfds[txq->q.write_ptr],
1875 sizeof(struct iwl_tfd),
1876 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1877 skb->data + hdr_len, tb2_len);
1878 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1879 skb->data + hdr_len, tb2_len);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001880
Johannes Bergea68f462014-02-27 14:36:55 +01001881 wait_write_ptr = ieee80211_has_morefrags(fc);
Johannes Berg7c5ba4a2012-04-09 17:46:54 -07001882
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001883 /* start timer if queue currently empty */
Eliad Peller7616f332014-11-20 17:33:43 +02001884 if (q->read_ptr == q->write_ptr) {
Emmanuel Grumbach4cf677f2015-01-12 14:38:29 +02001885 if (txq->wd_timeout)
1886 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
Eliad Peller7616f332014-11-20 17:33:43 +02001887 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
1888 iwl_trans_pcie_ref(trans);
1889 }
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001890
1891 /* Tell device the write index *just past* this latest filled TFD */
Johannes Berg83f32a42014-04-24 09:57:40 +02001892 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
Johannes Bergea68f462014-02-27 14:36:55 +01001893 if (!wait_write_ptr)
1894 iwl_pcie_txq_inc_wr_ptr(trans, txq);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001895
1896 /*
1897 * At this point the frame is "transmitted" successfully
Johannes Berg43aa6162014-02-27 14:24:36 +01001898 * and we will get a TX status notification eventually.
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001899 */
1900 if (iwl_queue_space(q) < q->high_mark) {
Johannes Bergea68f462014-02-27 14:36:55 +01001901 if (wait_write_ptr)
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001902 iwl_pcie_txq_inc_wr_ptr(trans, txq);
Johannes Bergea68f462014-02-27 14:36:55 +01001903 else
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001904 iwl_stop_queue(trans, txq);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001905 }
1906 spin_unlock(&txq->lock);
1907 return 0;
1908out_err:
1909 spin_unlock(&txq->lock);
1910 return -1;
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001911}