Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Intel IO-APIC support for multi-Pentium hosts. |
| 3 | * |
Ingo Molnar | 8f47e16 | 2009-01-31 02:03:42 +0100 | [diff] [blame] | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * Many thanks to Stig Venaas for trying out countless experimental |
| 7 | * patches and reporting/debugging problems patiently! |
| 8 | * |
| 9 | * (c) 1999, Multiple IO-APIC support, developed by |
| 10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and |
| 11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, |
| 12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> |
| 13 | * and Ingo Molnar <mingo@redhat.com> |
| 14 | * |
| 15 | * Fixes |
| 16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
| 17 | * thanks to Eric Gilmore |
| 18 | * and Rolf G. Tews |
| 19 | * for testing these extensively |
| 20 | * Paul Diefenbaugh : Added full ACPI support |
Thomas Gleixner | 1f93464 | 2015-04-14 10:29:58 +0800 | [diff] [blame] | 21 | * |
| 22 | * Historical information which is worth to be preserved: |
| 23 | * |
| 24 | * - SiS APIC rmw bug: |
| 25 | * |
| 26 | * We used to have a workaround for a bug in SiS chips which |
| 27 | * required to rewrite the index register for a read-modify-write |
| 28 | * operation as the chip lost the index information which was |
| 29 | * setup for the read already. We cache the data now, so that |
| 30 | * workaround has been removed. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | */ |
| 32 | |
| 33 | #include <linux/mm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #include <linux/interrupt.h> |
| 35 | #include <linux/init.h> |
| 36 | #include <linux/delay.h> |
| 37 | #include <linux/sched.h> |
Yinghai Lu | d4057bd | 2008-08-19 20:50:38 -0700 | [diff] [blame] | 38 | #include <linux/pci.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | #include <linux/mc146818rtc.h> |
| 40 | #include <linux/compiler.h> |
| 41 | #include <linux/acpi.h> |
Paul Gortmaker | 186f436 | 2016-07-13 20:18:56 -0400 | [diff] [blame] | 42 | #include <linux/export.h> |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 43 | #include <linux/syscore_ops.h> |
Nigel Cunningham | 7dfb710 | 2006-12-06 20:34:23 -0800 | [diff] [blame] | 44 | #include <linux/freezer.h> |
Eric W. Biederman | f26d6a2 | 2007-05-02 19:27:19 +0200 | [diff] [blame] | 45 | #include <linux/kthread.h> |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 46 | #include <linux/jiffies.h> /* time_after() */ |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 47 | #include <linux/slab.h> |
Yinghai Lu | d4057bd | 2008-08-19 20:50:38 -0700 | [diff] [blame] | 48 | #include <linux/bootmem.h> |
Ashok Raj | 54d5d42 | 2005-09-06 15:16:15 -0700 | [diff] [blame] | 49 | |
Thomas Gleixner | f7a0c78 | 2015-04-14 10:30:08 +0800 | [diff] [blame] | 50 | #include <asm/irqdomain.h> |
Yinghai Lu | d4057bd | 2008-08-19 20:50:38 -0700 | [diff] [blame] | 51 | #include <asm/idle.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | #include <asm/io.h> |
| 53 | #include <asm/smp.h> |
Jaswinder Singh Rajput | 6d652ea | 2009-01-07 21:38:59 +0530 | [diff] [blame] | 54 | #include <asm/cpu.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | #include <asm/desc.h> |
Yinghai Lu | d4057bd | 2008-08-19 20:50:38 -0700 | [diff] [blame] | 56 | #include <asm/proto.h> |
| 57 | #include <asm/acpi.h> |
| 58 | #include <asm/dma.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | #include <asm/timer.h> |
Ingo Molnar | 306e440 | 2005-06-30 02:58:55 -0700 | [diff] [blame] | 60 | #include <asm/i8259.h> |
Yinghai Lu | a4dbc34 | 2008-07-25 02:14:28 -0700 | [diff] [blame] | 61 | #include <asm/setup.h> |
Suresh Siddha | 8a8f422 | 2012-03-30 11:47:08 -0700 | [diff] [blame] | 62 | #include <asm/irq_remapping.h> |
Jaswinder Singh Rajput | 2c1b284 | 2009-04-11 00:03:10 +0530 | [diff] [blame] | 63 | #include <asm/hw_irq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | |
Ingo Molnar | 7b6aa33 | 2009-02-17 13:58:15 +0100 | [diff] [blame] | 65 | #include <asm/apic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 67 | #define for_each_ioapic(idx) \ |
| 68 | for ((idx) = 0; (idx) < nr_ioapics; (idx)++) |
| 69 | #define for_each_ioapic_reverse(idx) \ |
| 70 | for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--) |
| 71 | #define for_each_pin(idx, pin) \ |
| 72 | for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++) |
| 73 | #define for_each_ioapic_pin(idx, pin) \ |
| 74 | for_each_ioapic((idx)) \ |
| 75 | for_each_pin((idx), (pin)) |
Cyrill Gorcunov | 2977fb3 | 2009-08-01 11:47:59 +0400 | [diff] [blame] | 76 | #define for_each_irq_pin(entry, head) \ |
Yinghai Lu | a178b87 | 2014-10-27 16:11:55 +0800 | [diff] [blame] | 77 | list_for_each_entry(entry, &head, list) |
Maciej W. Rozycki | 32f71af | 2008-07-21 00:52:49 +0100 | [diff] [blame] | 78 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 79 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 80 | static DEFINE_MUTEX(ioapic_mutex); |
Jiang Liu | 44767bf | 2014-06-09 16:19:53 +0800 | [diff] [blame] | 81 | static unsigned int ioapic_dynirq_base; |
Jiang Liu | b81975e | 2014-06-09 16:20:11 +0800 | [diff] [blame] | 82 | static int ioapic_initialized; |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 83 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 84 | struct irq_pin_list { |
| 85 | struct list_head list; |
| 86 | int apic, pin; |
| 87 | }; |
| 88 | |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 89 | struct mp_chip_data { |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 90 | struct list_head irq_2_pin; |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 91 | struct IO_APIC_route_entry entry; |
| 92 | int trigger; |
| 93 | int polarity; |
Jiang Liu | 96ed44b | 2015-04-13 14:11:58 +0800 | [diff] [blame] | 94 | u32 count; |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 95 | bool isa_irq; |
| 96 | }; |
| 97 | |
Jiang Liu | 154d9e5 | 2015-04-14 10:29:56 +0800 | [diff] [blame] | 98 | struct mp_ioapic_gsi { |
| 99 | u32 gsi_base; |
| 100 | u32 gsi_end; |
| 101 | }; |
| 102 | |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 103 | static struct ioapic { |
| 104 | /* |
| 105 | * # of IRQ routing registers |
| 106 | */ |
| 107 | int nr_registers; |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 108 | /* |
| 109 | * Saved state during suspend/resume, or while enabling intr-remap. |
| 110 | */ |
| 111 | struct IO_APIC_route_entry *saved_registers; |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 112 | /* I/O APIC config */ |
| 113 | struct mpc_ioapic mp_config; |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 114 | /* IO APIC gsi routing info */ |
| 115 | struct mp_ioapic_gsi gsi_config; |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 116 | struct ioapic_domain_cfg irqdomain_cfg; |
| 117 | struct irq_domain *irqdomain; |
Jiang Liu | 15516a3 | 2014-10-27 13:21:46 +0800 | [diff] [blame] | 118 | struct resource *iomem_res; |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 119 | } ioapics[MAX_IO_APICS]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 121 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 122 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 123 | int mpc_ioapic_id(int ioapic_idx) |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 124 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 125 | return ioapics[ioapic_idx].mp_config.apicid; |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 126 | } |
| 127 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 128 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 129 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 130 | return ioapics[ioapic_idx].mp_config.apicaddr; |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 131 | } |
| 132 | |
Jiang Liu | 154d9e5 | 2015-04-14 10:29:56 +0800 | [diff] [blame] | 133 | static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 134 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 135 | return &ioapics[ioapic_idx].gsi_config; |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 136 | } |
Alexey Starikovskiy | 9f640cc | 2008-04-04 23:41:13 +0400 | [diff] [blame] | 137 | |
Jiang Liu | 18e4855 | 2014-06-09 16:19:45 +0800 | [diff] [blame] | 138 | static inline int mp_ioapic_pin_count(int ioapic) |
| 139 | { |
| 140 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); |
| 141 | |
| 142 | return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; |
| 143 | } |
| 144 | |
Jiang Liu | 154d9e5 | 2015-04-14 10:29:56 +0800 | [diff] [blame] | 145 | static inline u32 mp_pin_to_gsi(int ioapic, int pin) |
Jiang Liu | 18e4855 | 2014-06-09 16:19:45 +0800 | [diff] [blame] | 146 | { |
| 147 | return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; |
| 148 | } |
| 149 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 150 | static inline bool mp_is_legacy_irq(int irq) |
| 151 | { |
| 152 | return irq >= 0 && irq < nr_legacy_irqs(); |
| 153 | } |
| 154 | |
Jiang Liu | 95d76ac | 2014-06-09 16:19:48 +0800 | [diff] [blame] | 155 | /* |
| 156 | * Initialize all legacy IRQs and all pins on the first IOAPIC |
| 157 | * if we have legacy interrupt controller. Kernel boot option "pirq=" |
| 158 | * may rely on non-legacy pins on the first IOAPIC. |
| 159 | */ |
Jiang Liu | 18e4855 | 2014-06-09 16:19:45 +0800 | [diff] [blame] | 160 | static inline int mp_init_irq_at_boot(int ioapic, int irq) |
| 161 | { |
Jiang Liu | 95d76ac | 2014-06-09 16:19:48 +0800 | [diff] [blame] | 162 | if (!nr_legacy_irqs()) |
| 163 | return 0; |
| 164 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 165 | return ioapic == 0 || mp_is_legacy_irq(irq); |
Jiang Liu | 18e4855 | 2014-06-09 16:19:45 +0800 | [diff] [blame] | 166 | } |
| 167 | |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 168 | static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic) |
| 169 | { |
| 170 | return ioapics[ioapic].irqdomain; |
| 171 | } |
| 172 | |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 173 | int nr_ioapics; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 174 | |
Eric W. Biederman | a4384df | 2010-06-08 11:44:32 -0700 | [diff] [blame] | 175 | /* The one past the highest gsi number used */ |
| 176 | u32 gsi_top; |
Eric W. Biederman | 5777372 | 2010-03-30 01:07:10 -0700 | [diff] [blame] | 177 | |
Alexey Starikovskiy | 584f734 | 2008-04-04 23:41:32 +0400 | [diff] [blame] | 178 | /* MP IRQ source entries */ |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 179 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
Alexey Starikovskiy | 584f734 | 2008-04-04 23:41:32 +0400 | [diff] [blame] | 180 | |
| 181 | /* # of MP IRQ source entries */ |
| 182 | int mp_irq_entries; |
| 183 | |
Paul Gortmaker | bb8187d | 2012-05-17 19:06:13 -0400 | [diff] [blame] | 184 | #ifdef CONFIG_EISA |
Alexey Starikovskiy | 8732fc4 | 2008-05-19 19:47:16 +0400 | [diff] [blame] | 185 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
| 186 | #endif |
| 187 | |
| 188 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
| 189 | |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 190 | int skip_ioapic_setup; |
| 191 | |
Henrik Kretzschmar | 7167d08 | 2011-02-22 15:38:05 +0100 | [diff] [blame] | 192 | /** |
| 193 | * disable_ioapic_support() - disables ioapic support at runtime |
| 194 | */ |
| 195 | void disable_ioapic_support(void) |
Ingo Molnar | 65a4e57 | 2009-01-31 03:36:17 +0100 | [diff] [blame] | 196 | { |
| 197 | #ifdef CONFIG_PCI |
| 198 | noioapicquirk = 1; |
| 199 | noioapicreroute = -1; |
| 200 | #endif |
| 201 | skip_ioapic_setup = 1; |
| 202 | } |
| 203 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 204 | static int __init parse_noapic(char *str) |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 205 | { |
| 206 | /* disable IO-APIC */ |
Henrik Kretzschmar | 7167d08 | 2011-02-22 15:38:05 +0100 | [diff] [blame] | 207 | disable_ioapic_support(); |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 208 | return 0; |
| 209 | } |
| 210 | early_param("noapic", parse_noapic); |
Chuck Ebbert | 66759a0 | 2005-09-12 18:49:25 +0200 | [diff] [blame] | 211 | |
Feng Tang | 2d8009b | 2010-11-19 11:33:35 +0800 | [diff] [blame] | 212 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
| 213 | void mp_save_irq(struct mpc_intsrc *m) |
| 214 | { |
| 215 | int i; |
| 216 | |
| 217 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," |
| 218 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", |
| 219 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, |
| 220 | m->srcbusirq, m->dstapic, m->dstirq); |
| 221 | |
| 222 | for (i = 0; i < mp_irq_entries; i++) { |
Feng Tang | 0e3fa13 | 2010-12-08 15:18:57 +0800 | [diff] [blame] | 223 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
Feng Tang | 2d8009b | 2010-11-19 11:33:35 +0800 | [diff] [blame] | 224 | return; |
| 225 | } |
| 226 | |
Feng Tang | 0e3fa13 | 2010-12-08 15:18:57 +0800 | [diff] [blame] | 227 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
Feng Tang | 2d8009b | 2010-11-19 11:33:35 +0800 | [diff] [blame] | 228 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
| 229 | panic("Max # of irq sources exceeded!!\n"); |
| 230 | } |
| 231 | |
Yinghai Lu | 7e89941 | 2014-10-27 13:21:39 +0800 | [diff] [blame] | 232 | static void alloc_ioapic_saved_registers(int idx) |
| 233 | { |
| 234 | size_t size; |
| 235 | |
| 236 | if (ioapics[idx].saved_registers) |
| 237 | return; |
| 238 | |
| 239 | size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers; |
| 240 | ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL); |
| 241 | if (!ioapics[idx].saved_registers) |
| 242 | pr_err("IOAPIC %d: suspend/resume impossible!\n", idx); |
| 243 | } |
| 244 | |
Jiang Liu | 15516a3 | 2014-10-27 13:21:46 +0800 | [diff] [blame] | 245 | static void free_ioapic_saved_registers(int idx) |
| 246 | { |
| 247 | kfree(ioapics[idx].saved_registers); |
| 248 | ioapics[idx].saved_registers = NULL; |
| 249 | } |
| 250 | |
Jiang Liu | 11d686e | 2014-10-27 16:12:05 +0800 | [diff] [blame] | 251 | int __init arch_early_ioapic_init(void) |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 252 | { |
Jiang Liu | 1331532 | 2015-04-13 14:11:56 +0800 | [diff] [blame] | 253 | int i; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 254 | |
Jiang Liu | 95d76ac | 2014-06-09 16:19:48 +0800 | [diff] [blame] | 255 | if (!nr_legacy_irqs()) |
Jacob Pan | 1f91233 | 2010-02-05 04:06:56 -0800 | [diff] [blame] | 256 | io_apic_irqs = ~0UL; |
Jacob Pan | 1f91233 | 2010-02-05 04:06:56 -0800 | [diff] [blame] | 257 | |
Yinghai Lu | 7e89941 | 2014-10-27 13:21:39 +0800 | [diff] [blame] | 258 | for_each_ioapic(i) |
| 259 | alloc_ioapic_saved_registers(i); |
Suresh Siddha | 4c79185 | 2011-05-18 16:31:32 -0700 | [diff] [blame] | 260 | |
Yinghai Lu | 13a0c3c | 2008-12-26 02:05:47 -0800 | [diff] [blame] | 261 | return 0; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 262 | } |
| 263 | |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 264 | struct io_apic { |
| 265 | unsigned int index; |
| 266 | unsigned int unused[3]; |
| 267 | unsigned int data; |
Suresh Siddha | 0280f7c | 2009-03-16 17:05:01 -0700 | [diff] [blame] | 268 | unsigned int unused2[11]; |
| 269 | unsigned int eoi; |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 270 | }; |
| 271 | |
| 272 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) |
| 273 | { |
| 274 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 275 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 276 | } |
| 277 | |
Jiang Liu | ad66e1e | 2015-04-14 10:29:43 +0800 | [diff] [blame] | 278 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
Suresh Siddha | 0280f7c | 2009-03-16 17:05:01 -0700 | [diff] [blame] | 279 | { |
| 280 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
| 281 | writel(vector, &io_apic->eoi); |
| 282 | } |
| 283 | |
Konrad Rzeszutek Wilk | 4a8e2a3 | 2012-03-28 12:37:36 -0400 | [diff] [blame] | 284 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 285 | { |
| 286 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
| 287 | writel(reg, &io_apic->index); |
| 288 | return readl(&io_apic->data); |
| 289 | } |
| 290 | |
Jiang Liu | 9a93d47 | 2015-04-14 10:29:55 +0800 | [diff] [blame] | 291 | static void io_apic_write(unsigned int apic, unsigned int reg, |
| 292 | unsigned int value) |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 293 | { |
| 294 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 295 | |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 296 | writel(reg, &io_apic->index); |
| 297 | writel(value, &io_apic->data); |
| 298 | } |
| 299 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 300 | union entry_union { |
| 301 | struct { u32 w1, w2; }; |
| 302 | struct IO_APIC_route_entry entry; |
| 303 | }; |
| 304 | |
Suresh Siddha | e57253a | 2011-08-25 12:01:12 -0700 | [diff] [blame] | 305 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
| 306 | { |
| 307 | union entry_union eu; |
| 308 | |
| 309 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
| 310 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 311 | |
Suresh Siddha | e57253a | 2011-08-25 12:01:12 -0700 | [diff] [blame] | 312 | return eu.entry; |
| 313 | } |
| 314 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 315 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
| 316 | { |
| 317 | union entry_union eu; |
| 318 | unsigned long flags; |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 319 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 320 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Suresh Siddha | e57253a | 2011-08-25 12:01:12 -0700 | [diff] [blame] | 321 | eu.entry = __ioapic_read_entry(apic, pin); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 322 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 323 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 324 | return eu.entry; |
| 325 | } |
| 326 | |
Linus Torvalds | f9dadfa | 2006-11-01 10:05:35 -0800 | [diff] [blame] | 327 | /* |
| 328 | * When we write a new IO APIC routing entry, we need to write the high |
| 329 | * word first! If the mask bit in the low word is clear, we will enable |
| 330 | * the interrupt, and we need to make sure the entry is fully populated |
| 331 | * before that happens. |
| 332 | */ |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 333 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
Andi Kleen | d15512f | 2006-12-07 02:14:07 +0100 | [diff] [blame] | 334 | { |
Figo.zhang | 50a8d4d | 2009-06-17 22:25:20 +0800 | [diff] [blame] | 335 | union entry_union eu = {{0, 0}}; |
| 336 | |
Andi Kleen | d15512f | 2006-12-07 02:14:07 +0100 | [diff] [blame] | 337 | eu.entry = e; |
| 338 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
| 339 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
| 340 | } |
| 341 | |
Thomas Gleixner | 1a8ce7f | 2010-10-04 21:08:56 +0200 | [diff] [blame] | 342 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 343 | { |
| 344 | unsigned long flags; |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 345 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 346 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Andi Kleen | d15512f | 2006-12-07 02:14:07 +0100 | [diff] [blame] | 347 | __ioapic_write_entry(apic, pin, e); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 348 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | f9dadfa | 2006-11-01 10:05:35 -0800 | [diff] [blame] | 349 | } |
| 350 | |
| 351 | /* |
| 352 | * When we mask an IO APIC routing entry, we need to write the low |
| 353 | * word first, in order to set the mask bit before we change the |
| 354 | * high bits! |
| 355 | */ |
| 356 | static void ioapic_mask_entry(int apic, int pin) |
| 357 | { |
| 358 | unsigned long flags; |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 359 | union entry_union eu = { .entry.mask = IOAPIC_MASKED }; |
Linus Torvalds | f9dadfa | 2006-11-01 10:05:35 -0800 | [diff] [blame] | 360 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 361 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 362 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
| 363 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 364 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 365 | } |
| 366 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | /* |
| 368 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are |
| 369 | * shared ISA-space IRQs, so we have to support them. We are super |
| 370 | * fast in the common case, and fast for shared ISA-space IRQs. |
| 371 | */ |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 372 | static int __add_pin_to_irq_node(struct mp_chip_data *data, |
| 373 | int node, int apic, int pin) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | { |
Yinghai Lu | a178b87 | 2014-10-27 16:11:55 +0800 | [diff] [blame] | 375 | struct irq_pin_list *entry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 376 | |
Cyrill Gorcunov | 2977fb3 | 2009-08-01 11:47:59 +0400 | [diff] [blame] | 377 | /* don't allow duplicates */ |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 378 | for_each_irq_pin(entry, data->irq_2_pin) |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 379 | if (entry->apic == apic && entry->pin == pin) |
Cyrill Gorcunov | f3d1915 | 2009-08-06 00:09:31 +0400 | [diff] [blame] | 380 | return 0; |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 381 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 382 | entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node); |
Cyrill Gorcunov | a7428cd | 2009-08-01 11:48:00 +0400 | [diff] [blame] | 383 | if (!entry) { |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 384 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
| 385 | node, apic, pin); |
Cyrill Gorcunov | f3d1915 | 2009-08-06 00:09:31 +0400 | [diff] [blame] | 386 | return -ENOMEM; |
Cyrill Gorcunov | a7428cd | 2009-08-01 11:48:00 +0400 | [diff] [blame] | 387 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | entry->apic = apic; |
| 389 | entry->pin = pin; |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 390 | list_add_tail(&entry->list, &data->irq_2_pin); |
Jeremy Fitzhardinge | 875e68e | 2009-06-08 03:24:11 -0700 | [diff] [blame] | 391 | |
Cyrill Gorcunov | f3d1915 | 2009-08-06 00:09:31 +0400 | [diff] [blame] | 392 | return 0; |
| 393 | } |
| 394 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 395 | static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin) |
Jiang Liu | df334be | 2014-06-09 16:20:06 +0800 | [diff] [blame] | 396 | { |
Yinghai Lu | a178b87 | 2014-10-27 16:11:55 +0800 | [diff] [blame] | 397 | struct irq_pin_list *tmp, *entry; |
Jiang Liu | df334be | 2014-06-09 16:20:06 +0800 | [diff] [blame] | 398 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 399 | list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) |
Jiang Liu | df334be | 2014-06-09 16:20:06 +0800 | [diff] [blame] | 400 | if (entry->apic == apic && entry->pin == pin) { |
Yinghai Lu | a178b87 | 2014-10-27 16:11:55 +0800 | [diff] [blame] | 401 | list_del(&entry->list); |
Jiang Liu | df334be | 2014-06-09 16:20:06 +0800 | [diff] [blame] | 402 | kfree(entry); |
| 403 | return; |
Jiang Liu | df334be | 2014-06-09 16:20:06 +0800 | [diff] [blame] | 404 | } |
| 405 | } |
| 406 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 407 | static void add_pin_to_irq_node(struct mp_chip_data *data, |
| 408 | int node, int apic, int pin) |
Cyrill Gorcunov | f3d1915 | 2009-08-06 00:09:31 +0400 | [diff] [blame] | 409 | { |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 410 | if (__add_pin_to_irq_node(data, node, apic, pin)) |
Cyrill Gorcunov | f3d1915 | 2009-08-06 00:09:31 +0400 | [diff] [blame] | 411 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 412 | } |
| 413 | |
| 414 | /* |
| 415 | * Reroute an IRQ to a different pin. |
| 416 | */ |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 417 | static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node, |
Jeremy Fitzhardinge | 4eea6ff | 2009-06-08 03:32:15 -0700 | [diff] [blame] | 418 | int oldapic, int oldpin, |
| 419 | int newapic, int newpin) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 420 | { |
Jeremy Fitzhardinge | 535b642 | 2009-06-08 03:29:26 -0700 | [diff] [blame] | 421 | struct irq_pin_list *entry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 422 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 423 | for_each_irq_pin(entry, data->irq_2_pin) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 424 | if (entry->apic == oldapic && entry->pin == oldpin) { |
| 425 | entry->apic = newapic; |
| 426 | entry->pin = newpin; |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 427 | /* every one is different, right? */ |
Jeremy Fitzhardinge | 4eea6ff | 2009-06-08 03:32:15 -0700 | [diff] [blame] | 428 | return; |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 429 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 430 | } |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 431 | |
Jeremy Fitzhardinge | 4eea6ff | 2009-06-08 03:32:15 -0700 | [diff] [blame] | 432 | /* old apic/pin didn't exist, so just add new ones */ |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 433 | add_pin_to_irq_node(data, node, newapic, newpin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 434 | } |
| 435 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 436 | static void io_apic_modify_irq(struct mp_chip_data *data, |
Jeremy Fitzhardinge | 2f210de | 2009-06-08 02:55:22 -0700 | [diff] [blame] | 437 | int mask_and, int mask_or, |
| 438 | void (*final)(struct irq_pin_list *entry)) |
Cyrill Gorcunov | 87783be | 2008-09-10 22:19:50 +0400 | [diff] [blame] | 439 | { |
Jiang Liu | 0be275e | 2015-04-14 10:29:57 +0800 | [diff] [blame] | 440 | union entry_union eu; |
Cyrill Gorcunov | 87783be | 2008-09-10 22:19:50 +0400 | [diff] [blame] | 441 | struct irq_pin_list *entry; |
| 442 | |
Jiang Liu | 0be275e | 2015-04-14 10:29:57 +0800 | [diff] [blame] | 443 | eu.entry = data->entry; |
| 444 | eu.w1 &= mask_and; |
| 445 | eu.w1 |= mask_or; |
| 446 | data->entry = eu.entry; |
| 447 | |
| 448 | for_each_irq_pin(entry, data->irq_2_pin) { |
| 449 | io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1); |
| 450 | if (final) |
| 451 | final(entry); |
| 452 | } |
Suresh Siddha | c29d9db | 2009-12-01 15:31:16 -0800 | [diff] [blame] | 453 | } |
| 454 | |
Jaswinder Singh Rajput | 7f3e632 | 2008-12-29 20:34:35 +0530 | [diff] [blame] | 455 | static void io_apic_sync(struct irq_pin_list *entry) |
Yinghai Lu | 4e738e2 | 2008-08-19 20:50:47 -0700 | [diff] [blame] | 456 | { |
Cyrill Gorcunov | 87783be | 2008-09-10 22:19:50 +0400 | [diff] [blame] | 457 | /* |
| 458 | * Synchronize the IO-APIC and the CPU by doing |
| 459 | * a dummy read from the IO-APIC |
| 460 | */ |
| 461 | struct io_apic __iomem *io_apic; |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 462 | |
Cyrill Gorcunov | 87783be | 2008-09-10 22:19:50 +0400 | [diff] [blame] | 463 | io_apic = io_apic_base(entry->apic); |
Yinghai Lu | 4e738e2 | 2008-08-19 20:50:47 -0700 | [diff] [blame] | 464 | readl(&io_apic->data); |
| 465 | } |
| 466 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 467 | static void mask_ioapic_irq(struct irq_data *irq_data) |
Cyrill Gorcunov | 87783be | 2008-09-10 22:19:50 +0400 | [diff] [blame] | 468 | { |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 469 | struct mp_chip_data *data = irq_data->chip_data; |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 470 | unsigned long flags; |
| 471 | |
| 472 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 473 | io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 474 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 475 | } |
| 476 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 477 | static void __unmask_ioapic(struct mp_chip_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 478 | { |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 479 | io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL); |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 480 | } |
| 481 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 482 | static void unmask_ioapic_irq(struct irq_data *irq_data) |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 483 | { |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 484 | struct mp_chip_data *data = irq_data->chip_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 485 | unsigned long flags; |
| 486 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 487 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 488 | __unmask_ioapic(data); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 489 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 490 | } |
| 491 | |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 492 | /* |
| 493 | * IO-APIC versions below 0x20 don't support EOI register. |
| 494 | * For the record, here is the information about various versions: |
| 495 | * 0Xh 82489DX |
| 496 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant |
| 497 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant |
| 498 | * 30h-FFh Reserved |
| 499 | * |
| 500 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic |
| 501 | * version as 0x2. This is an error with documentation and these ICH chips |
| 502 | * use io-apic's of version 0x20. |
| 503 | * |
| 504 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. |
| 505 | * Otherwise, we simulate the EOI message manually by changing the trigger |
| 506 | * mode to edge and then back to level, with RTE being masked during this. |
| 507 | */ |
Jiang Liu | ad66e1e | 2015-04-14 10:29:43 +0800 | [diff] [blame] | 508 | static void __eoi_ioapic_pin(int apic, int pin, int vector) |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 509 | { |
| 510 | if (mpc_ioapic_ver(apic) >= 0x20) { |
Joerg Roedel | da16532 | 2012-09-26 12:44:50 +0200 | [diff] [blame] | 511 | io_apic_eoi(apic, vector); |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 512 | } else { |
| 513 | struct IO_APIC_route_entry entry, entry1; |
| 514 | |
| 515 | entry = entry1 = __ioapic_read_entry(apic, pin); |
| 516 | |
| 517 | /* |
| 518 | * Mask the entry and change the trigger mode to edge. |
| 519 | */ |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 520 | entry1.mask = IOAPIC_MASKED; |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 521 | entry1.trigger = IOAPIC_EDGE; |
| 522 | |
| 523 | __ioapic_write_entry(apic, pin, entry1); |
| 524 | |
| 525 | /* |
| 526 | * Restore the previous level triggered entry. |
| 527 | */ |
| 528 | __ioapic_write_entry(apic, pin, entry); |
| 529 | } |
| 530 | } |
| 531 | |
Andy Shevchenko | 4faefda | 2015-10-09 17:24:45 +0300 | [diff] [blame] | 532 | static void eoi_ioapic_pin(int vector, struct mp_chip_data *data) |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 533 | { |
| 534 | unsigned long flags; |
| 535 | struct irq_pin_list *entry; |
| 536 | |
| 537 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 538 | for_each_irq_pin(entry, data->irq_2_pin) |
Jiang Liu | ad66e1e | 2015-04-14 10:29:43 +0800 | [diff] [blame] | 539 | __eoi_ioapic_pin(entry->apic, entry->pin, vector); |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 540 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 541 | } |
| 542 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 543 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
| 544 | { |
| 545 | struct IO_APIC_route_entry entry; |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 546 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 547 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 548 | entry = ioapic_read_entry(apic, pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 549 | if (entry.delivery_mode == dest_SMI) |
| 550 | return; |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 551 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 552 | /* |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 553 | * Make sure the entry is masked and re-read the contents to check |
| 554 | * if it is a level triggered pin and if the remote-IRR is set. |
| 555 | */ |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 556 | if (entry.mask == IOAPIC_UNMASKED) { |
| 557 | entry.mask = IOAPIC_MASKED; |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 558 | ioapic_write_entry(apic, pin, entry); |
| 559 | entry = ioapic_read_entry(apic, pin); |
| 560 | } |
| 561 | |
| 562 | if (entry.irr) { |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 563 | unsigned long flags; |
| 564 | |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 565 | /* |
| 566 | * Make sure the trigger mode is set to level. Explicit EOI |
| 567 | * doesn't clear the remote-IRR if the trigger mode is not |
| 568 | * set to level. |
| 569 | */ |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 570 | if (entry.trigger == IOAPIC_EDGE) { |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 571 | entry.trigger = IOAPIC_LEVEL; |
| 572 | ioapic_write_entry(apic, pin, entry); |
| 573 | } |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 574 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Jiang Liu | ad66e1e | 2015-04-14 10:29:43 +0800 | [diff] [blame] | 575 | __eoi_ioapic_pin(apic, pin, entry.vector); |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 576 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 577 | } |
| 578 | |
| 579 | /* |
| 580 | * Clear the rest of the bits in the IO-APIC RTE except for the mask |
| 581 | * bit. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 582 | */ |
Linus Torvalds | f9dadfa | 2006-11-01 10:05:35 -0800 | [diff] [blame] | 583 | ioapic_mask_entry(apic, pin); |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 584 | entry = ioapic_read_entry(apic, pin); |
| 585 | if (entry.irr) |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 586 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 587 | mpc_ioapic_id(apic), pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 588 | } |
| 589 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 590 | static void clear_IO_APIC (void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | { |
| 592 | int apic, pin; |
| 593 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 594 | for_each_ioapic_pin(apic, pin) |
| 595 | clear_IO_APIC_pin(apic, pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 596 | } |
| 597 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 598 | #ifdef CONFIG_X86_32 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | /* |
| 600 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to |
| 601 | * specific CPU-side IRQs. |
| 602 | */ |
| 603 | |
| 604 | #define MAX_PIRQS 8 |
Yinghai Lu | 3bd25d0 | 2009-02-15 02:54:03 -0800 | [diff] [blame] | 605 | static int pirq_entries[MAX_PIRQS] = { |
| 606 | [0 ... MAX_PIRQS - 1] = -1 |
| 607 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 608 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 609 | static int __init ioapic_pirq_setup(char *str) |
| 610 | { |
| 611 | int i, max; |
| 612 | int ints[MAX_PIRQS+1]; |
| 613 | |
| 614 | get_options(str, ARRAY_SIZE(ints), ints); |
| 615 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 616 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 617 | "PIRQ redirection, working around broken MP-BIOS.\n"); |
| 618 | max = MAX_PIRQS; |
| 619 | if (ints[0] < MAX_PIRQS) |
| 620 | max = ints[0]; |
| 621 | |
| 622 | for (i = 0; i < max; i++) { |
| 623 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
| 624 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); |
| 625 | /* |
| 626 | * PIRQs are mapped upside down, usually. |
| 627 | */ |
| 628 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; |
| 629 | } |
| 630 | return 1; |
| 631 | } |
| 632 | |
| 633 | __setup("pirq=", ioapic_pirq_setup); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 634 | #endif /* CONFIG_X86_32 */ |
| 635 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 636 | /* |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 637 | * Saves all the IO-APIC RTE's |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 638 | */ |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 639 | int save_ioapic_entries(void) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 640 | { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 641 | int apic, pin; |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 642 | int err = 0; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 643 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 644 | for_each_ioapic(apic) { |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 645 | if (!ioapics[apic].saved_registers) { |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 646 | err = -ENOMEM; |
| 647 | continue; |
| 648 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 649 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 650 | for_each_pin(apic, pin) |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 651 | ioapics[apic].saved_registers[pin] = |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 652 | ioapic_read_entry(apic, pin); |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 653 | } |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 654 | |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 655 | return err; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 656 | } |
| 657 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 658 | /* |
| 659 | * Mask all IO APIC entries. |
| 660 | */ |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 661 | void mask_ioapic_entries(void) |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 662 | { |
| 663 | int apic, pin; |
| 664 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 665 | for_each_ioapic(apic) { |
Suresh Siddha | 2f344d2 | 2011-05-24 10:45:31 -0700 | [diff] [blame] | 666 | if (!ioapics[apic].saved_registers) |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 667 | continue; |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 668 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 669 | for_each_pin(apic, pin) { |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 670 | struct IO_APIC_route_entry entry; |
| 671 | |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 672 | entry = ioapics[apic].saved_registers[pin]; |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 673 | if (entry.mask == IOAPIC_UNMASKED) { |
| 674 | entry.mask = IOAPIC_MASKED; |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 675 | ioapic_write_entry(apic, pin, entry); |
| 676 | } |
| 677 | } |
| 678 | } |
| 679 | } |
| 680 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 681 | /* |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 682 | * Restore IO APIC entries which was saved in the ioapic structure. |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 683 | */ |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 684 | int restore_ioapic_entries(void) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 685 | { |
| 686 | int apic, pin; |
| 687 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 688 | for_each_ioapic(apic) { |
Suresh Siddha | 2f344d2 | 2011-05-24 10:45:31 -0700 | [diff] [blame] | 689 | if (!ioapics[apic].saved_registers) |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 690 | continue; |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 691 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 692 | for_each_pin(apic, pin) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 693 | ioapic_write_entry(apic, pin, |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 694 | ioapics[apic].saved_registers[pin]); |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 695 | } |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 696 | return 0; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 697 | } |
| 698 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 699 | /* |
| 700 | * Find the IRQ entry number of a certain pin. |
| 701 | */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 702 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 703 | { |
| 704 | int i; |
| 705 | |
| 706 | for (i = 0; i < mp_irq_entries; i++) |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 707 | if (mp_irqs[i].irqtype == type && |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 708 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 709 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
| 710 | mp_irqs[i].dstirq == pin) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 711 | return i; |
| 712 | |
| 713 | return -1; |
| 714 | } |
| 715 | |
| 716 | /* |
| 717 | * Find the pin to which IRQ[irq] (ISA) is connected |
| 718 | */ |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 719 | static int __init find_isa_irq_pin(int irq, int type) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 720 | { |
| 721 | int i; |
| 722 | |
| 723 | for (i = 0; i < mp_irq_entries; i++) { |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 724 | int lbus = mp_irqs[i].srcbus; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 725 | |
Alexey Starikovskiy | d27e2b8 | 2008-03-20 14:54:18 +0300 | [diff] [blame] | 726 | if (test_bit(lbus, mp_bus_not_pci) && |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 727 | (mp_irqs[i].irqtype == type) && |
| 728 | (mp_irqs[i].srcbusirq == irq)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 729 | |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 730 | return mp_irqs[i].dstirq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 731 | } |
| 732 | return -1; |
| 733 | } |
| 734 | |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 735 | static int __init find_isa_irq_apic(int irq, int type) |
| 736 | { |
| 737 | int i; |
| 738 | |
| 739 | for (i = 0; i < mp_irq_entries; i++) { |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 740 | int lbus = mp_irqs[i].srcbus; |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 741 | |
Alexey Starikovskiy | 73b2961 | 2008-03-20 14:54:24 +0300 | [diff] [blame] | 742 | if (test_bit(lbus, mp_bus_not_pci) && |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 743 | (mp_irqs[i].irqtype == type) && |
| 744 | (mp_irqs[i].srcbusirq == irq)) |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 745 | break; |
| 746 | } |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 747 | |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 748 | if (i < mp_irq_entries) { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 749 | int ioapic_idx; |
| 750 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 751 | for_each_ioapic(ioapic_idx) |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 752 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) |
| 753 | return ioapic_idx; |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 754 | } |
| 755 | |
| 756 | return -1; |
| 757 | } |
| 758 | |
Paul Gortmaker | bb8187d | 2012-05-17 19:06:13 -0400 | [diff] [blame] | 759 | #ifdef CONFIG_EISA |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 760 | /* |
| 761 | * EISA Edge/Level control register, ELCR |
| 762 | */ |
| 763 | static int EISA_ELCR(unsigned int irq) |
| 764 | { |
Jiang Liu | 95d76ac | 2014-06-09 16:19:48 +0800 | [diff] [blame] | 765 | if (irq < nr_legacy_irqs()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 766 | unsigned int port = 0x4d0 + (irq >> 3); |
| 767 | return (inb(port) >> (irq & 7)) & 1; |
| 768 | } |
| 769 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 770 | "Broken MPtable reports ISA irq %d\n", irq); |
| 771 | return 0; |
| 772 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 773 | |
Alexey Starikovskiy | c0a282c | 2008-03-20 14:55:02 +0300 | [diff] [blame] | 774 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 776 | /* ISA interrupts are always active high edge triggered, |
Alexey Starikovskiy | 6728801 | 2008-03-20 14:54:36 +0300 | [diff] [blame] | 777 | * when listed as conforming in the MP table. */ |
| 778 | |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 779 | #define default_ISA_trigger(idx) (IOAPIC_EDGE) |
| 780 | #define default_ISA_polarity(idx) (IOAPIC_POL_HIGH) |
Alexey Starikovskiy | 6728801 | 2008-03-20 14:54:36 +0300 | [diff] [blame] | 781 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | /* EISA interrupts are always polarity zero and can be edge or level |
| 783 | * trigger depending on the ELCR value. If an interrupt is listed as |
| 784 | * EISA conforming in the MP table, that means its trigger type must |
| 785 | * be read in from the ELCR */ |
| 786 | |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 787 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
Alexey Starikovskiy | 6728801 | 2008-03-20 14:54:36 +0300 | [diff] [blame] | 788 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 789 | |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 790 | /* PCI interrupts are always active low level triggered, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 791 | * when listed as conforming in the MP table. */ |
| 792 | |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 793 | #define default_PCI_trigger(idx) (IOAPIC_LEVEL) |
| 794 | #define default_PCI_polarity(idx) (IOAPIC_POL_LOW) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 795 | |
Thomas Gleixner | b77cf6a | 2011-02-23 17:33:53 +0100 | [diff] [blame] | 796 | static int irq_polarity(int idx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 797 | { |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 798 | int bus = mp_irqs[idx].srcbus; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 799 | |
| 800 | /* |
| 801 | * Determine IRQ line polarity (high active or low active): |
| 802 | */ |
Thomas Gleixner | ab76085 | 2015-04-14 10:30:07 +0800 | [diff] [blame] | 803 | switch (mp_irqs[idx].irqflag & 0x03) { |
| 804 | case 0: |
| 805 | /* conforms to spec, ie. bus-type dependent polarity */ |
| 806 | if (test_bit(bus, mp_bus_not_pci)) |
| 807 | return default_ISA_polarity(idx); |
| 808 | else |
| 809 | return default_PCI_polarity(idx); |
| 810 | case 1: |
| 811 | return IOAPIC_POL_HIGH; |
| 812 | case 2: |
| 813 | pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n"); |
| 814 | case 3: |
| 815 | default: /* Pointless default required due to do gcc stupidity */ |
| 816 | return IOAPIC_POL_LOW; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 817 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 818 | } |
| 819 | |
Thomas Gleixner | ab76085 | 2015-04-14 10:30:07 +0800 | [diff] [blame] | 820 | #ifdef CONFIG_EISA |
| 821 | static int eisa_irq_trigger(int idx, int bus, int trigger) |
| 822 | { |
| 823 | switch (mp_bus_id_to_type[bus]) { |
| 824 | case MP_BUS_PCI: |
| 825 | case MP_BUS_ISA: |
| 826 | return trigger; |
| 827 | case MP_BUS_EISA: |
| 828 | return default_EISA_trigger(idx); |
| 829 | } |
| 830 | pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus); |
| 831 | return IOAPIC_LEVEL; |
| 832 | } |
| 833 | #else |
| 834 | static inline int eisa_irq_trigger(int idx, int bus, int trigger) |
| 835 | { |
| 836 | return trigger; |
| 837 | } |
| 838 | #endif |
| 839 | |
Thomas Gleixner | b77cf6a | 2011-02-23 17:33:53 +0100 | [diff] [blame] | 840 | static int irq_trigger(int idx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 841 | { |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 842 | int bus = mp_irqs[idx].srcbus; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 843 | int trigger; |
| 844 | |
| 845 | /* |
| 846 | * Determine IRQ trigger mode (edge or level sensitive): |
| 847 | */ |
Thomas Gleixner | ab76085 | 2015-04-14 10:30:07 +0800 | [diff] [blame] | 848 | switch ((mp_irqs[idx].irqflag >> 2) & 0x03) { |
| 849 | case 0: |
| 850 | /* conforms to spec, ie. bus-type dependent trigger mode */ |
| 851 | if (test_bit(bus, mp_bus_not_pci)) |
| 852 | trigger = default_ISA_trigger(idx); |
| 853 | else |
| 854 | trigger = default_PCI_trigger(idx); |
| 855 | /* Take EISA into account */ |
| 856 | return eisa_irq_trigger(idx, bus, trigger); |
| 857 | case 1: |
| 858 | return IOAPIC_EDGE; |
| 859 | case 2: |
| 860 | pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n"); |
| 861 | case 3: |
| 862 | default: /* Pointless default required due to do gcc stupidity */ |
| 863 | return IOAPIC_LEVEL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 864 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 865 | } |
| 866 | |
Jiang Liu | c4d05a2 | 2015-04-13 14:11:54 +0800 | [diff] [blame] | 867 | void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node, |
| 868 | int trigger, int polarity) |
| 869 | { |
| 870 | init_irq_alloc_info(info, NULL); |
| 871 | info->type = X86_IRQ_ALLOC_TYPE_IOAPIC; |
| 872 | info->ioapic_node = node; |
| 873 | info->ioapic_trigger = trigger; |
| 874 | info->ioapic_polarity = polarity; |
| 875 | info->ioapic_valid = 1; |
| 876 | } |
| 877 | |
Jiang Liu | 96ed44b | 2015-04-13 14:11:58 +0800 | [diff] [blame] | 878 | #ifndef CONFIG_ACPI |
| 879 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity); |
| 880 | #endif |
| 881 | |
| 882 | static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst, |
| 883 | struct irq_alloc_info *src, |
| 884 | u32 gsi, int ioapic_idx, int pin) |
| 885 | { |
| 886 | int trigger, polarity; |
| 887 | |
| 888 | copy_irq_alloc_info(dst, src); |
| 889 | dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC; |
| 890 | dst->ioapic_id = mpc_ioapic_id(ioapic_idx); |
| 891 | dst->ioapic_pin = pin; |
| 892 | dst->ioapic_valid = 1; |
| 893 | if (src && src->ioapic_valid) { |
| 894 | dst->ioapic_node = src->ioapic_node; |
| 895 | dst->ioapic_trigger = src->ioapic_trigger; |
| 896 | dst->ioapic_polarity = src->ioapic_polarity; |
| 897 | } else { |
| 898 | dst->ioapic_node = NUMA_NO_NODE; |
| 899 | if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) { |
| 900 | dst->ioapic_trigger = trigger; |
| 901 | dst->ioapic_polarity = polarity; |
| 902 | } else { |
| 903 | /* |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 904 | * PCI interrupts are always active low level |
Jiang Liu | 96ed44b | 2015-04-13 14:11:58 +0800 | [diff] [blame] | 905 | * triggered. |
| 906 | */ |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 907 | dst->ioapic_trigger = IOAPIC_LEVEL; |
| 908 | dst->ioapic_polarity = IOAPIC_POL_LOW; |
Jiang Liu | 96ed44b | 2015-04-13 14:11:58 +0800 | [diff] [blame] | 909 | } |
| 910 | } |
| 911 | } |
| 912 | |
| 913 | static int ioapic_alloc_attr_node(struct irq_alloc_info *info) |
| 914 | { |
| 915 | return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE; |
| 916 | } |
| 917 | |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 918 | static void mp_register_handler(unsigned int irq, unsigned long trigger) |
| 919 | { |
| 920 | irq_flow_handler_t hdl; |
| 921 | bool fasteoi; |
| 922 | |
| 923 | if (trigger) { |
| 924 | irq_set_status_flags(irq, IRQ_LEVEL); |
| 925 | fasteoi = true; |
| 926 | } else { |
| 927 | irq_clear_status_flags(irq, IRQ_LEVEL); |
| 928 | fasteoi = false; |
| 929 | } |
| 930 | |
| 931 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
| 932 | __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge"); |
| 933 | } |
| 934 | |
Jiang Liu | 96ed44b | 2015-04-13 14:11:58 +0800 | [diff] [blame] | 935 | static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info) |
| 936 | { |
| 937 | struct mp_chip_data *data = irq_get_chip_data(irq); |
| 938 | |
| 939 | /* |
| 940 | * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger |
| 941 | * and polarity attirbutes. So allow the first user to reprogram the |
| 942 | * pin with real trigger and polarity attributes. |
| 943 | */ |
| 944 | if (irq < nr_legacy_irqs() && data->count == 1) { |
| 945 | if (info->ioapic_trigger != data->trigger) |
Jiang Liu | 646c4b7 | 2015-07-30 15:51:32 +0800 | [diff] [blame] | 946 | mp_register_handler(irq, info->ioapic_trigger); |
Jiang Liu | 96ed44b | 2015-04-13 14:11:58 +0800 | [diff] [blame] | 947 | data->entry.trigger = data->trigger = info->ioapic_trigger; |
| 948 | data->entry.polarity = data->polarity = info->ioapic_polarity; |
| 949 | } |
| 950 | |
| 951 | return data->trigger == info->ioapic_trigger && |
| 952 | data->polarity == info->ioapic_polarity; |
| 953 | } |
| 954 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 955 | static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi, |
Jiang Liu | c4d05a2 | 2015-04-13 14:11:54 +0800 | [diff] [blame] | 956 | struct irq_alloc_info *info) |
Jiang Liu | 6b9fb70 | 2014-06-10 14:13:25 +0800 | [diff] [blame] | 957 | { |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 958 | bool legacy = false; |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 959 | int irq = -1; |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 960 | int type = ioapics[ioapic].irqdomain_cfg.type; |
| 961 | |
| 962 | switch (type) { |
| 963 | case IOAPIC_DOMAIN_LEGACY: |
| 964 | /* |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 965 | * Dynamically allocate IRQ number for non-ISA IRQs in the first |
| 966 | * 16 GSIs on some weird platforms. |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 967 | */ |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 968 | if (!ioapic_initialized || gsi >= nr_legacy_irqs()) |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 969 | irq = gsi; |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 970 | legacy = mp_is_legacy_irq(irq); |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 971 | break; |
| 972 | case IOAPIC_DOMAIN_STRICT: |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 973 | irq = gsi; |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 974 | break; |
| 975 | case IOAPIC_DOMAIN_DYNAMIC: |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 976 | break; |
| 977 | default: |
| 978 | WARN(1, "ioapic: unknown irqdomain type %d\n", type); |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 979 | return -1; |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 980 | } |
| 981 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 982 | return __irq_domain_alloc_irqs(domain, irq, 1, |
| 983 | ioapic_alloc_attr_node(info), |
Thomas Gleixner | 06ee6d5 | 2016-07-04 17:39:24 +0900 | [diff] [blame] | 984 | info, legacy, NULL); |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 985 | } |
| 986 | |
| 987 | /* |
| 988 | * Need special handling for ISA IRQs because there may be multiple IOAPIC pins |
| 989 | * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping |
| 990 | * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are |
| 991 | * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H). |
| 992 | * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and |
| 993 | * some BIOSes may use MP Interrupt Source records to override IRQ numbers for |
| 994 | * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be |
| 995 | * multiple pins sharing the same legacy IRQ number when ACPI is disabled. |
| 996 | */ |
| 997 | static int alloc_isa_irq_from_domain(struct irq_domain *domain, |
| 998 | int irq, int ioapic, int pin, |
| 999 | struct irq_alloc_info *info) |
| 1000 | { |
| 1001 | struct mp_chip_data *data; |
| 1002 | struct irq_data *irq_data = irq_get_irq_data(irq); |
| 1003 | int node = ioapic_alloc_attr_node(info); |
| 1004 | |
| 1005 | /* |
| 1006 | * Legacy ISA IRQ has already been allocated, just add pin to |
| 1007 | * the pin list assoicated with this IRQ and program the IOAPIC |
| 1008 | * entry. The IOAPIC entry |
| 1009 | */ |
| 1010 | if (irq_data && irq_data->parent_data) { |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1011 | if (!mp_check_pin_attr(irq, info)) |
| 1012 | return -EBUSY; |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1013 | if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic, |
| 1014 | info->ioapic_pin)) |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1015 | return -ENOMEM; |
| 1016 | } else { |
Thomas Gleixner | 06ee6d5 | 2016-07-04 17:39:24 +0900 | [diff] [blame] | 1017 | irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true, |
| 1018 | NULL); |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1019 | if (irq >= 0) { |
| 1020 | irq_data = irq_domain_get_irq_data(domain, irq); |
| 1021 | data = irq_data->chip_data; |
| 1022 | data->isa_irq = true; |
| 1023 | } |
| 1024 | } |
| 1025 | |
| 1026 | return irq; |
Jiang Liu | 6b9fb70 | 2014-06-10 14:13:25 +0800 | [diff] [blame] | 1027 | } |
| 1028 | |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1029 | static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, |
Jiang Liu | c4d05a2 | 2015-04-13 14:11:54 +0800 | [diff] [blame] | 1030 | unsigned int flags, struct irq_alloc_info *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1031 | { |
Eric W. Biederman | d464207 | 2010-03-30 01:07:13 -0700 | [diff] [blame] | 1032 | int irq; |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1033 | bool legacy = false; |
| 1034 | struct irq_alloc_info tmp; |
| 1035 | struct mp_chip_data *data; |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1036 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); |
| 1037 | |
Jiang Liu | b81975e | 2014-06-09 16:20:11 +0800 | [diff] [blame] | 1038 | if (!domain) |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1039 | return -ENOSYS; |
Jiang Liu | 16ee7b3 | 2014-06-09 16:20:04 +0800 | [diff] [blame] | 1040 | |
Jiang Liu | 16ee7b3 | 2014-06-09 16:20:04 +0800 | [diff] [blame] | 1041 | if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) { |
| 1042 | irq = mp_irqs[idx].srcbusirq; |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1043 | legacy = mp_is_legacy_irq(irq); |
| 1044 | } |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1045 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1046 | mutex_lock(&ioapic_mutex); |
| 1047 | if (!(flags & IOAPIC_MAP_ALLOC)) { |
| 1048 | if (!legacy) { |
| 1049 | irq = irq_find_mapping(domain, pin); |
Jiang Liu | 16ee7b3 | 2014-06-09 16:20:04 +0800 | [diff] [blame] | 1050 | if (irq == 0) |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1051 | irq = -ENOENT; |
Jiang Liu | 16ee7b3 | 2014-06-09 16:20:04 +0800 | [diff] [blame] | 1052 | } |
| 1053 | } else { |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1054 | ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin); |
| 1055 | if (legacy) |
| 1056 | irq = alloc_isa_irq_from_domain(domain, irq, |
| 1057 | ioapic, pin, &tmp); |
| 1058 | else if ((irq = irq_find_mapping(domain, pin)) == 0) |
| 1059 | irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp); |
| 1060 | else if (!mp_check_pin_attr(irq, &tmp)) |
| 1061 | irq = -EBUSY; |
| 1062 | if (irq >= 0) { |
| 1063 | data = irq_get_chip_data(irq); |
| 1064 | data->count++; |
| 1065 | } |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1066 | } |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1067 | mutex_unlock(&ioapic_mutex); |
| 1068 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1069 | return irq; |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1070 | } |
| 1071 | |
| 1072 | static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) |
| 1073 | { |
| 1074 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1075 | |
| 1076 | /* |
| 1077 | * Debugging check, we are in big trouble if this message pops up! |
| 1078 | */ |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 1079 | if (mp_irqs[idx].dstirq != pin) |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 1080 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1081 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1082 | #ifdef CONFIG_X86_32 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1083 | /* |
| 1084 | * PCI IRQ command line redirection. Yes, limits are hardcoded. |
| 1085 | */ |
| 1086 | if ((pin >= 16) && (pin <= 23)) { |
| 1087 | if (pirq_entries[pin-16] != -1) { |
| 1088 | if (!pirq_entries[pin-16]) { |
| 1089 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
| 1090 | "disabling PIRQ%d\n", pin-16); |
| 1091 | } else { |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1092 | int irq = pirq_entries[pin-16]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1093 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
| 1094 | "using PIRQ%d -> IRQ %d\n", |
| 1095 | pin-16, irq); |
Jiang Liu | 6b9fb70 | 2014-06-10 14:13:25 +0800 | [diff] [blame] | 1096 | return irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1097 | } |
| 1098 | } |
| 1099 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1100 | #endif |
| 1101 | |
Jiang Liu | c4d05a2 | 2015-04-13 14:11:54 +0800 | [diff] [blame] | 1102 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL); |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1103 | } |
Jiang Liu | 6b9fb70 | 2014-06-10 14:13:25 +0800 | [diff] [blame] | 1104 | |
Jiang Liu | 154d9e5 | 2015-04-14 10:29:56 +0800 | [diff] [blame] | 1105 | int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info) |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1106 | { |
| 1107 | int ioapic, pin, idx; |
| 1108 | |
| 1109 | ioapic = mp_find_ioapic(gsi); |
| 1110 | if (ioapic < 0) |
| 1111 | return -1; |
| 1112 | |
| 1113 | pin = mp_find_ioapic_pin(ioapic, gsi); |
| 1114 | idx = find_irq_entry(ioapic, pin, mp_INT); |
| 1115 | if ((flags & IOAPIC_MAP_CHECK) && idx < 0) |
| 1116 | return -1; |
| 1117 | |
Jiang Liu | c4d05a2 | 2015-04-13 14:11:54 +0800 | [diff] [blame] | 1118 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1119 | } |
| 1120 | |
Jiang Liu | df334be | 2014-06-09 16:20:06 +0800 | [diff] [blame] | 1121 | void mp_unmap_irq(int irq) |
| 1122 | { |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1123 | struct irq_data *irq_data = irq_get_irq_data(irq); |
| 1124 | struct mp_chip_data *data; |
Jiang Liu | df334be | 2014-06-09 16:20:06 +0800 | [diff] [blame] | 1125 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1126 | if (!irq_data || !irq_data->domain) |
Jiang Liu | df334be | 2014-06-09 16:20:06 +0800 | [diff] [blame] | 1127 | return; |
| 1128 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1129 | data = irq_data->chip_data; |
| 1130 | if (!data || data->isa_irq) |
| 1131 | return; |
Jiang Liu | df334be | 2014-06-09 16:20:06 +0800 | [diff] [blame] | 1132 | |
| 1133 | mutex_lock(&ioapic_mutex); |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1134 | if (--data->count == 0) |
| 1135 | irq_domain_free_irqs(irq, 1); |
Jiang Liu | df334be | 2014-06-09 16:20:06 +0800 | [diff] [blame] | 1136 | mutex_unlock(&ioapic_mutex); |
| 1137 | } |
| 1138 | |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1139 | /* |
| 1140 | * Find a specific PCI IRQ entry. |
| 1141 | * Not an __init, possibly needed by modules |
| 1142 | */ |
Jiang Liu | 25d0d35 | 2014-10-27 16:11:54 +0800 | [diff] [blame] | 1143 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1144 | { |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1145 | int irq, i, best_ioapic = -1, best_idx = -1; |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1146 | |
| 1147 | apic_printk(APIC_DEBUG, |
| 1148 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
| 1149 | bus, slot, pin); |
| 1150 | if (test_bit(bus, mp_bus_not_pci)) { |
| 1151 | apic_printk(APIC_VERBOSE, |
| 1152 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
| 1153 | return -1; |
| 1154 | } |
Jiang Liu | 7959850 | 2014-06-09 16:19:44 +0800 | [diff] [blame] | 1155 | |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1156 | for (i = 0; i < mp_irq_entries; i++) { |
| 1157 | int lbus = mp_irqs[i].srcbus; |
Jiang Liu | 7959850 | 2014-06-09 16:19:44 +0800 | [diff] [blame] | 1158 | int ioapic_idx, found = 0; |
| 1159 | |
| 1160 | if (bus != lbus || mp_irqs[i].irqtype != mp_INT || |
| 1161 | slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f)) |
| 1162 | continue; |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1163 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 1164 | for_each_ioapic(ioapic_idx) |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1165 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || |
Jiang Liu | 7959850 | 2014-06-09 16:19:44 +0800 | [diff] [blame] | 1166 | mp_irqs[i].dstapic == MP_APIC_ALL) { |
| 1167 | found = 1; |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1168 | break; |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1169 | } |
Jiang Liu | 7959850 | 2014-06-09 16:19:44 +0800 | [diff] [blame] | 1170 | if (!found) |
| 1171 | continue; |
| 1172 | |
| 1173 | /* Skip ISA IRQs */ |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1174 | irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0); |
| 1175 | if (irq > 0 && !IO_APIC_IRQ(irq)) |
Jiang Liu | 7959850 | 2014-06-09 16:19:44 +0800 | [diff] [blame] | 1176 | continue; |
| 1177 | |
| 1178 | if (pin == (mp_irqs[i].srcbusirq & 3)) { |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1179 | best_idx = i; |
| 1180 | best_ioapic = ioapic_idx; |
| 1181 | goto out; |
Jiang Liu | 7959850 | 2014-06-09 16:19:44 +0800 | [diff] [blame] | 1182 | } |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1183 | |
Jiang Liu | 7959850 | 2014-06-09 16:19:44 +0800 | [diff] [blame] | 1184 | /* |
| 1185 | * Use the first all-but-pin matching entry as a |
| 1186 | * best-guess fuzzy result for broken mptables. |
| 1187 | */ |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1188 | if (best_idx < 0) { |
| 1189 | best_idx = i; |
| 1190 | best_ioapic = ioapic_idx; |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1191 | } |
| 1192 | } |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1193 | if (best_idx < 0) |
| 1194 | return -1; |
| 1195 | |
| 1196 | out: |
Jiang Liu | 25d0d35 | 2014-10-27 16:11:54 +0800 | [diff] [blame] | 1197 | return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, |
| 1198 | IOAPIC_MAP_ALLOC); |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1199 | } |
| 1200 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
| 1201 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1202 | static struct irq_chip ioapic_chip, ioapic_ir_chip; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1203 | |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1204 | #ifdef CONFIG_X86_32 |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 1205 | static inline int IO_APIC_irq_trigger(int irq) |
| 1206 | { |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 1207 | int apic, idx, pin; |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 1208 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 1209 | for_each_ioapic_pin(apic, pin) { |
| 1210 | idx = find_irq_entry(apic, pin, mp_INT); |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 1211 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0))) |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 1212 | return irq_trigger(idx); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 1213 | } |
| 1214 | /* |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1215 | * nonexistent IRQs are edge default |
| 1216 | */ |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 1217 | return 0; |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 1218 | } |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1219 | #else |
| 1220 | static inline int IO_APIC_irq_trigger(int irq) |
| 1221 | { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1222 | return 1; |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1223 | } |
| 1224 | #endif |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 1225 | |
Thomas Gleixner | ed972cc | 2011-02-23 14:31:36 +0100 | [diff] [blame] | 1226 | static void __init setup_IO_APIC_irqs(void) |
| 1227 | { |
Jiang Liu | 16ee7b3 | 2014-06-09 16:20:04 +0800 | [diff] [blame] | 1228 | unsigned int ioapic, pin; |
| 1229 | int idx; |
Thomas Gleixner | ed972cc | 2011-02-23 14:31:36 +0100 | [diff] [blame] | 1230 | |
| 1231 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); |
| 1232 | |
Jiang Liu | 16ee7b3 | 2014-06-09 16:20:04 +0800 | [diff] [blame] | 1233 | for_each_ioapic_pin(ioapic, pin) { |
| 1234 | idx = find_irq_entry(ioapic, pin, mp_INT); |
| 1235 | if (idx < 0) |
| 1236 | apic_printk(APIC_VERBOSE, |
| 1237 | KERN_DEBUG " apic %d pin %d not connected\n", |
| 1238 | mpc_ioapic_id(ioapic), pin); |
| 1239 | else |
| 1240 | pin_2_irq(idx, ioapic, pin, |
| 1241 | ioapic ? 0 : IOAPIC_MAP_ALLOC); |
| 1242 | } |
Thomas Gleixner | ed972cc | 2011-02-23 14:31:36 +0100 | [diff] [blame] | 1243 | } |
| 1244 | |
Yoshihiro YUNOMAE | 1740545 | 2013-08-20 16:01:07 +0900 | [diff] [blame] | 1245 | void ioapic_zap_locks(void) |
| 1246 | { |
| 1247 | raw_spin_lock_init(&ioapic_lock); |
| 1248 | } |
| 1249 | |
Jiang Liu | a44174e | 2015-04-13 14:11:57 +0800 | [diff] [blame] | 1250 | static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
| 1251 | { |
| 1252 | int i; |
| 1253 | char buf[256]; |
| 1254 | struct IO_APIC_route_entry entry; |
| 1255 | struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry; |
| 1256 | |
| 1257 | printk(KERN_DEBUG "IOAPIC %d:\n", apic); |
| 1258 | for (i = 0; i <= nr_entries; i++) { |
| 1259 | entry = ioapic_read_entry(apic, i); |
| 1260 | snprintf(buf, sizeof(buf), |
| 1261 | " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 1262 | i, |
| 1263 | entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ", |
| 1264 | entry.trigger == IOAPIC_LEVEL ? "level" : "edge ", |
| 1265 | entry.polarity == IOAPIC_POL_LOW ? "low " : "high", |
Jiang Liu | a44174e | 2015-04-13 14:11:57 +0800 | [diff] [blame] | 1266 | entry.vector, entry.irr, entry.delivery_status); |
| 1267 | if (ir_entry->format) |
| 1268 | printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n", |
| 1269 | buf, (ir_entry->index << 15) | ir_entry->index, |
| 1270 | ir_entry->zero); |
| 1271 | else |
| 1272 | printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n", |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 1273 | buf, |
| 1274 | entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ? |
| 1275 | "logical " : "physical", |
Jiang Liu | a44174e | 2015-04-13 14:11:57 +0800 | [diff] [blame] | 1276 | entry.dest, entry.delivery_mode); |
| 1277 | } |
| 1278 | } |
| 1279 | |
Jiang Liu | 74afab7 | 2014-10-27 16:12:00 +0800 | [diff] [blame] | 1280 | static void __init print_IO_APIC(int ioapic_idx) |
Joerg Roedel | afcc8a4 | 2012-09-26 12:44:36 +0200 | [diff] [blame] | 1281 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1282 | union IO_APIC_reg_00 reg_00; |
| 1283 | union IO_APIC_reg_01 reg_01; |
| 1284 | union IO_APIC_reg_02 reg_02; |
| 1285 | union IO_APIC_reg_03 reg_03; |
| 1286 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1287 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1288 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1289 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
| 1290 | reg_01.raw = io_apic_read(ioapic_idx, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1291 | if (reg_01.bits.version >= 0x10) |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1292 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 1293 | if (reg_01.bits.version >= 0x20) |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1294 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1295 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1296 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1297 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1298 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
| 1299 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); |
| 1300 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); |
| 1301 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1302 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1303 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
Naga Chumbalkar | bd6a46e | 2011-07-08 18:46:36 +0000 | [diff] [blame] | 1304 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
| 1305 | reg_01.bits.entries); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1306 | |
| 1307 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); |
Naga Chumbalkar | bd6a46e | 2011-07-08 18:46:36 +0000 | [diff] [blame] | 1308 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
| 1309 | reg_01.bits.version); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1310 | |
| 1311 | /* |
| 1312 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, |
| 1313 | * but the value of reg_02 is read as the previous read register |
| 1314 | * value, so ignore it if reg_02 == reg_01. |
| 1315 | */ |
| 1316 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { |
| 1317 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); |
| 1318 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1319 | } |
| 1320 | |
| 1321 | /* |
| 1322 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 |
| 1323 | * or reg_03, but the value of reg_0[23] is read as the previous read |
| 1324 | * register value, so ignore it if reg_03 == reg_0[12]. |
| 1325 | */ |
| 1326 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && |
| 1327 | reg_03.raw != reg_01.raw) { |
| 1328 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); |
| 1329 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1330 | } |
| 1331 | |
| 1332 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); |
Jiang Liu | a44174e | 2015-04-13 14:11:57 +0800 | [diff] [blame] | 1333 | io_apic_print_entries(ioapic_idx, reg_01.bits.entries); |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1334 | } |
| 1335 | |
Jiang Liu | 74afab7 | 2014-10-27 16:12:00 +0800 | [diff] [blame] | 1336 | void __init print_IO_APICs(void) |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1337 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1338 | int ioapic_idx; |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1339 | unsigned int irq; |
| 1340 | |
| 1341 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 1342 | for_each_ioapic(ioapic_idx) |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1343 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1344 | mpc_ioapic_id(ioapic_idx), |
| 1345 | ioapics[ioapic_idx].nr_registers); |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1346 | |
| 1347 | /* |
| 1348 | * We are a bit conservative about what we expect. We have to |
| 1349 | * know about every hardware change ASAP. |
| 1350 | */ |
| 1351 | printk(KERN_INFO "testing the IO APIC.......................\n"); |
| 1352 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 1353 | for_each_ioapic(ioapic_idx) |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1354 | print_IO_APIC(ioapic_idx); |
Naga Chumbalkar | 42f0efc | 2011-07-12 21:17:35 +0000 | [diff] [blame] | 1355 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1356 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
Thomas Gleixner | ad9f433 | 2010-09-30 11:26:43 +0200 | [diff] [blame] | 1357 | for_each_active_irq(irq) { |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 1358 | struct irq_pin_list *entry; |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1359 | struct irq_chip *chip; |
| 1360 | struct mp_chip_data *data; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 1361 | |
Mathias Nyman | 6fd36ba | 2011-11-10 13:45:24 +0000 | [diff] [blame] | 1362 | chip = irq_get_chip(irq); |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1363 | if (chip != &ioapic_chip && chip != &ioapic_ir_chip) |
Mathias Nyman | 6fd36ba | 2011-11-10 13:45:24 +0000 | [diff] [blame] | 1364 | continue; |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1365 | data = irq_get_chip_data(irq); |
| 1366 | if (!data) |
| 1367 | continue; |
| 1368 | if (list_empty(&data->irq_2_pin)) |
| 1369 | continue; |
Mathias Nyman | 6fd36ba | 2011-11-10 13:45:24 +0000 | [diff] [blame] | 1370 | |
Yinghai Lu | 8f09cd2 | 2008-08-19 20:50:51 -0700 | [diff] [blame] | 1371 | printk(KERN_DEBUG "IRQ%d ", irq); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1372 | for_each_irq_pin(entry, data->irq_2_pin) |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 1373 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
| 1374 | pr_cont("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1375 | } |
| 1376 | |
| 1377 | printk(KERN_INFO ".................................... done.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1378 | } |
| 1379 | |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 1380 | /* Where if anywhere is the i8259 connect in external int mode */ |
| 1381 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; |
| 1382 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1383 | void __init enable_IO_APIC(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1384 | { |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1385 | int i8259_apic, i8259_pin; |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 1386 | int apic, pin; |
Thomas Gleixner | bc07844 | 2009-08-29 18:09:57 +0200 | [diff] [blame] | 1387 | |
Thomas Gleixner | a46f5c8 | 2015-01-15 21:22:32 +0000 | [diff] [blame] | 1388 | if (skip_ioapic_setup) |
| 1389 | nr_ioapics = 0; |
| 1390 | |
| 1391 | if (!nr_legacy_irqs() || !nr_ioapics) |
Thomas Gleixner | bc07844 | 2009-08-29 18:09:57 +0200 | [diff] [blame] | 1392 | return; |
| 1393 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 1394 | for_each_ioapic_pin(apic, pin) { |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1395 | /* See if any of the pins is in ExtINT mode */ |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 1396 | struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1397 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 1398 | /* If the interrupt line is enabled and in ExtInt mode |
| 1399 | * I have found the pin where the i8259 is connected. |
| 1400 | */ |
| 1401 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { |
| 1402 | ioapic_i8259.apic = apic; |
| 1403 | ioapic_i8259.pin = pin; |
| 1404 | goto found_i8259; |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1405 | } |
| 1406 | } |
| 1407 | found_i8259: |
| 1408 | /* Look to see what if the MP table has reported the ExtINT */ |
| 1409 | /* If we could not find the appropriate pin by looking at the ioapic |
| 1410 | * the i8259 probably is not connected the ioapic but give the |
| 1411 | * mptable a chance anyway. |
| 1412 | */ |
| 1413 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); |
| 1414 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); |
| 1415 | /* Trust the MP table if nothing is setup in the hardware */ |
| 1416 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { |
| 1417 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); |
| 1418 | ioapic_i8259.pin = i8259_pin; |
| 1419 | ioapic_i8259.apic = i8259_apic; |
| 1420 | } |
| 1421 | /* Complain if the MP table and the hardware disagree */ |
| 1422 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && |
| 1423 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) |
| 1424 | { |
| 1425 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1426 | } |
| 1427 | |
| 1428 | /* |
| 1429 | * Do not trust the IO-APIC being empty at bootup |
| 1430 | */ |
| 1431 | clear_IO_APIC(); |
| 1432 | } |
| 1433 | |
Joerg Roedel | 1c4248c | 2012-09-26 12:44:35 +0200 | [diff] [blame] | 1434 | void native_disable_io_apic(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1435 | { |
| 1436 | /* |
Karsten Wiese | 0b968d2 | 2005-09-09 12:59:04 +0200 | [diff] [blame] | 1437 | * If the i8259 is routed through an IOAPIC |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1438 | * Put that IOAPIC in virtual wire mode |
Karsten Wiese | 0b968d2 | 2005-09-09 12:59:04 +0200 | [diff] [blame] | 1439 | * so legacy interrupts can be delivered. |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1440 | */ |
Joerg Roedel | 1c4248c | 2012-09-26 12:44:35 +0200 | [diff] [blame] | 1441 | if (ioapic_i8259.pin != -1) { |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1442 | struct IO_APIC_route_entry entry; |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1443 | |
| 1444 | memset(&entry, 0, sizeof(entry)); |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 1445 | entry.mask = IOAPIC_UNMASKED; |
| 1446 | entry.trigger = IOAPIC_EDGE; |
| 1447 | entry.polarity = IOAPIC_POL_HIGH; |
| 1448 | entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL; |
| 1449 | entry.delivery_mode = dest_ExtINT; |
| 1450 | entry.dest = read_apic_id(); |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1451 | |
| 1452 | /* |
| 1453 | * Add it to the IO-APIC irq-routing table: |
| 1454 | */ |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 1455 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1456 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1457 | |
Borislav Petkov | 93984fb | 2016-04-04 22:25:00 +0200 | [diff] [blame] | 1458 | if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config()) |
Joerg Roedel | 1c4248c | 2012-09-26 12:44:35 +0200 | [diff] [blame] | 1459 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
Joerg Roedel | 1c4248c | 2012-09-26 12:44:35 +0200 | [diff] [blame] | 1460 | } |
| 1461 | |
| 1462 | /* |
| 1463 | * Not an __init, needed by the reboot code |
| 1464 | */ |
| 1465 | void disable_IO_APIC(void) |
| 1466 | { |
| 1467 | /* |
| 1468 | * Clear the IO-APIC before rebooting: |
| 1469 | */ |
| 1470 | clear_IO_APIC(); |
| 1471 | |
Jiang Liu | 95d76ac | 2014-06-09 16:19:48 +0800 | [diff] [blame] | 1472 | if (!nr_legacy_irqs()) |
Joerg Roedel | 1c4248c | 2012-09-26 12:44:35 +0200 | [diff] [blame] | 1473 | return; |
| 1474 | |
| 1475 | x86_io_apic_ops.disable(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1476 | } |
| 1477 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1478 | #ifdef CONFIG_X86_32 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1479 | /* |
| 1480 | * function to set the IO-APIC physical IDs based on the |
| 1481 | * values stored in the MPC table. |
| 1482 | * |
| 1483 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 |
| 1484 | */ |
Sebastian Andrzej Siewior | a38c538 | 2010-11-26 17:50:20 +0100 | [diff] [blame] | 1485 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1486 | { |
| 1487 | union IO_APIC_reg_00 reg_00; |
| 1488 | physid_mask_t phys_id_present_map; |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1489 | int ioapic_idx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1490 | int i; |
| 1491 | unsigned char old_id; |
| 1492 | unsigned long flags; |
| 1493 | |
Natalie Protasevich | ca05fea | 2005-06-23 00:08:22 -0700 | [diff] [blame] | 1494 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1495 | * This is broken; anything with a real cpu count has to |
| 1496 | * circumvent this idiocy regardless. |
| 1497 | */ |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 1498 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1499 | |
| 1500 | /* |
| 1501 | * Set the IOAPIC ID to the value stored in the MPC table. |
| 1502 | */ |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 1503 | for_each_ioapic(ioapic_idx) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1504 | /* Read the register 0 value */ |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1505 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1506 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1507 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 1508 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1509 | old_id = mpc_ioapic_id(ioapic_idx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1510 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1511 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1512 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1513 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1514 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
| 1515 | reg_00.bits.ID); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1516 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1517 | } |
| 1518 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1519 | /* |
| 1520 | * Sanity check, is the ID really free? Every APIC in a |
| 1521 | * system must have a unique ID or we get lots of nice |
| 1522 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
| 1523 | */ |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 1524 | if (apic->check_apicid_used(&phys_id_present_map, |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1525 | mpc_ioapic_id(ioapic_idx))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1526 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1527 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1528 | for (i = 0; i < get_physical_broadcast(); i++) |
| 1529 | if (!physid_isset(i, phys_id_present_map)) |
| 1530 | break; |
| 1531 | if (i >= get_physical_broadcast()) |
| 1532 | panic("Max APIC ID exceeded!\n"); |
| 1533 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
| 1534 | i); |
| 1535 | physid_set(i, phys_id_present_map); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1536 | ioapics[ioapic_idx].mp_config.apicid = i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1537 | } else { |
| 1538 | physid_mask_t tmp; |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1539 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 1540 | &tmp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1541 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
| 1542 | "phys_id_present_map\n", |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1543 | mpc_ioapic_id(ioapic_idx)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1544 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
| 1545 | } |
| 1546 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1547 | /* |
| 1548 | * We need to adjust the IRQ routing table |
| 1549 | * if the ID changed. |
| 1550 | */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1551 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1552 | for (i = 0; i < mp_irq_entries; i++) |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 1553 | if (mp_irqs[i].dstapic == old_id) |
| 1554 | mp_irqs[i].dstapic |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1555 | = mpc_ioapic_id(ioapic_idx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1556 | |
| 1557 | /* |
Yinghai Lu | 60d79fd | 2010-12-07 00:59:49 -0800 | [diff] [blame] | 1558 | * Update the ID register according to the right value |
| 1559 | * from the MPC table if they are different. |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 1560 | */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1561 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
Yinghai Lu | 60d79fd | 2010-12-07 00:59:49 -0800 | [diff] [blame] | 1562 | continue; |
| 1563 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1564 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 1565 | "...changing IO-APIC physical APIC ID to %d ...", |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1566 | mpc_ioapic_id(ioapic_idx)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1567 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1568 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1569 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1570 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1571 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1572 | |
| 1573 | /* |
| 1574 | * Sanity check |
| 1575 | */ |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1576 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1577 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1578 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1579 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 1580 | pr_cont("could not set ID!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1581 | else |
| 1582 | apic_printk(APIC_VERBOSE, " ok.\n"); |
| 1583 | } |
| 1584 | } |
Sebastian Andrzej Siewior | a38c538 | 2010-11-26 17:50:20 +0100 | [diff] [blame] | 1585 | |
| 1586 | void __init setup_ioapic_ids_from_mpc(void) |
| 1587 | { |
| 1588 | |
| 1589 | if (acpi_ioapic) |
| 1590 | return; |
| 1591 | /* |
| 1592 | * Don't check I/O APIC IDs for xAPIC systems. They have |
| 1593 | * no meaning without the serial APIC bus. |
| 1594 | */ |
| 1595 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
Denys Vlasenko | cff9ab2 | 2016-09-13 20:12:32 +0200 | [diff] [blame] | 1596 | || APIC_XAPIC(boot_cpu_apic_version)) |
Sebastian Andrzej Siewior | a38c538 | 2010-11-26 17:50:20 +0100 | [diff] [blame] | 1597 | return; |
| 1598 | setup_ioapic_ids_from_mpc_nocheck(); |
| 1599 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1600 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1601 | |
Zachary Amsden | 7ce0bcf | 2007-02-13 13:26:21 +0100 | [diff] [blame] | 1602 | int no_timer_check __initdata; |
Zachary Amsden | 8542b20 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 1603 | |
| 1604 | static int __init notimercheck(char *s) |
| 1605 | { |
| 1606 | no_timer_check = 1; |
| 1607 | return 1; |
| 1608 | } |
| 1609 | __setup("no_timer_check", notimercheck); |
| 1610 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1611 | /* |
| 1612 | * There is a nasty bug in some older SMP boards, their mptable lies |
| 1613 | * about the timer IRQ. We do the following to work around the situation: |
| 1614 | * |
| 1615 | * - timer IRQ defaults to IO-APIC IRQ |
| 1616 | * - if this function detects that timer IRQs are defunct, then we fall |
| 1617 | * back to ISA timer IRQs |
| 1618 | */ |
Adrian Bunk | f0a7a5c | 2007-07-21 17:10:29 +0200 | [diff] [blame] | 1619 | static int __init timer_irq_works(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1620 | { |
| 1621 | unsigned long t1 = jiffies; |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 1622 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1623 | |
Zachary Amsden | 8542b20 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 1624 | if (no_timer_check) |
| 1625 | return 1; |
| 1626 | |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 1627 | local_save_flags(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1628 | local_irq_enable(); |
| 1629 | /* Let ten ticks pass... */ |
| 1630 | mdelay((10 * 1000) / HZ); |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 1631 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1632 | |
| 1633 | /* |
| 1634 | * Expect a few ticks at least, to be sure some possible |
| 1635 | * glue logic does not lock up after one or two first |
| 1636 | * ticks in a non-ExtINT mode. Also the local APIC |
| 1637 | * might have cached one ExtINT interrupt. Finally, at |
| 1638 | * least one tick may be lost due to delays. |
| 1639 | */ |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1640 | |
| 1641 | /* jiffies wrap? */ |
Julia Lawall | 1d16b53 | 2008-01-30 13:32:19 +0100 | [diff] [blame] | 1642 | if (time_after(jiffies, t1 + 4)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1643 | return 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1644 | return 0; |
| 1645 | } |
| 1646 | |
| 1647 | /* |
| 1648 | * In the SMP+IOAPIC case it might happen that there are an unspecified |
| 1649 | * number of pending IRQ events unhandled. These cases are very rare, |
| 1650 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much |
| 1651 | * better to do it this way as thus we do not have to be aware of |
| 1652 | * 'pending' interrupts in the IRQ path, except at this point. |
| 1653 | */ |
| 1654 | /* |
| 1655 | * Edge triggered needs to resend any interrupt |
| 1656 | * that was delayed but this is now handled in the device |
| 1657 | * independent code. |
| 1658 | */ |
| 1659 | |
| 1660 | /* |
| 1661 | * Starting up a edge-triggered IO-APIC interrupt is |
| 1662 | * nasty - we need to make sure that we get the edge. |
| 1663 | * If it is already asserted for some reason, we need |
| 1664 | * return 1 to indicate that is was pending. |
| 1665 | * |
| 1666 | * This is not complete - we should be able to fake |
| 1667 | * an edge even if it isn't on the 8259A... |
| 1668 | */ |
Thomas Gleixner | 61a38ce | 2010-09-28 16:00:34 +0200 | [diff] [blame] | 1669 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1670 | { |
Thomas Gleixner | 61a38ce | 2010-09-28 16:00:34 +0200 | [diff] [blame] | 1671 | int was_pending = 0, irq = data->irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1672 | unsigned long flags; |
| 1673 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1674 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Jiang Liu | 95d76ac | 2014-06-09 16:19:48 +0800 | [diff] [blame] | 1675 | if (irq < nr_legacy_irqs()) { |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 1676 | legacy_pic->mask(irq); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 1677 | if (legacy_pic->irq_pending(irq)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1678 | was_pending = 1; |
| 1679 | } |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1680 | __unmask_ioapic(data->chip_data); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1681 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1682 | |
| 1683 | return was_pending; |
| 1684 | } |
| 1685 | |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 1686 | atomic_t irq_mis_count; |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 1687 | |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 1688 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1689 | static bool io_apic_level_ack_pending(struct mp_chip_data *data) |
Márton Németh | d1ecad6 | 2012-05-08 00:24:20 -0700 | [diff] [blame] | 1690 | { |
| 1691 | struct irq_pin_list *entry; |
| 1692 | unsigned long flags; |
| 1693 | |
| 1694 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1695 | for_each_irq_pin(entry, data->irq_2_pin) { |
Márton Németh | d1ecad6 | 2012-05-08 00:24:20 -0700 | [diff] [blame] | 1696 | unsigned int reg; |
| 1697 | int pin; |
| 1698 | |
| 1699 | pin = entry->pin; |
| 1700 | reg = io_apic_read(entry->apic, 0x10 + pin*2); |
| 1701 | /* Is the remote IRR bit set? */ |
| 1702 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { |
| 1703 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1704 | return true; |
| 1705 | } |
| 1706 | } |
| 1707 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1708 | |
| 1709 | return false; |
| 1710 | } |
| 1711 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1712 | static inline bool ioapic_irqd_mask(struct irq_data *data) |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 1713 | { |
| 1714 | /* If we are moving the irq we need to mask it */ |
| 1715 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1716 | mask_ioapic_irq(data); |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 1717 | return true; |
| 1718 | } |
| 1719 | return false; |
| 1720 | } |
| 1721 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1722 | static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked) |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 1723 | { |
| 1724 | if (unlikely(masked)) { |
| 1725 | /* Only migrate the irq if the ack has been received. |
| 1726 | * |
| 1727 | * On rare occasions the broadcast level triggered ack gets |
| 1728 | * delayed going to ioapics, and if we reprogram the |
| 1729 | * vector while Remote IRR is still set the irq will never |
| 1730 | * fire again. |
| 1731 | * |
| 1732 | * To prevent this scenario we read the Remote IRR bit |
| 1733 | * of the ioapic. This has two effects. |
| 1734 | * - On any sane system the read of the ioapic will |
| 1735 | * flush writes (and acks) going to the ioapic from |
| 1736 | * this cpu. |
| 1737 | * - We get to see if the ACK has actually been delivered. |
| 1738 | * |
| 1739 | * Based on failed experiments of reprogramming the |
| 1740 | * ioapic entry from outside of irq context starting |
| 1741 | * with masking the ioapic entry and then polling until |
| 1742 | * Remote IRR was clear before reprogramming the |
| 1743 | * ioapic I don't trust the Remote IRR bit to be |
| 1744 | * completey accurate. |
| 1745 | * |
| 1746 | * However there appears to be no other way to plug |
| 1747 | * this race, so if the Remote IRR bit is not |
| 1748 | * accurate and is causing problems then it is a hardware bug |
| 1749 | * and you can go talk to the chipset vendor about it. |
| 1750 | */ |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1751 | if (!io_apic_level_ack_pending(data->chip_data)) |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 1752 | irq_move_masked_irq(data); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1753 | unmask_ioapic_irq(data); |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 1754 | } |
| 1755 | } |
| 1756 | #else |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1757 | static inline bool ioapic_irqd_mask(struct irq_data *data) |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 1758 | { |
| 1759 | return false; |
| 1760 | } |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1761 | static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked) |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 1762 | { |
| 1763 | } |
| 1764 | #endif |
| 1765 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1766 | static void ioapic_ack_level(struct irq_data *irq_data) |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1767 | { |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1768 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 1769 | unsigned long v; |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 1770 | bool masked; |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1771 | int i; |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1772 | |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 1773 | irq_complete_move(cfg); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1774 | masked = ioapic_irqd_mask(irq_data); |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1775 | |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 1776 | /* |
Jeremy Fitzhardinge | 916a0fe | 2009-06-08 03:00:22 -0700 | [diff] [blame] | 1777 | * It appears there is an erratum which affects at least version 0x11 |
| 1778 | * of I/O APIC (that's the 82093AA and cores integrated into various |
| 1779 | * chipsets). Under certain conditions a level-triggered interrupt is |
| 1780 | * erroneously delivered as edge-triggered one but the respective IRR |
| 1781 | * bit gets set nevertheless. As a result the I/O unit expects an EOI |
| 1782 | * message but it will never arrive and further interrupts are blocked |
| 1783 | * from the source. The exact reason is so far unknown, but the |
| 1784 | * phenomenon was observed when two consecutive interrupt requests |
| 1785 | * from a given source get delivered to the same CPU and the source is |
| 1786 | * temporarily disabled in between. |
| 1787 | * |
| 1788 | * A workaround is to simulate an EOI message manually. We achieve it |
| 1789 | * by setting the trigger mode to edge and then to level when the edge |
| 1790 | * trigger mode gets detected in the TMR of a local APIC for a |
| 1791 | * level-triggered interrupt. We mask the source for the time of the |
| 1792 | * operation to prevent an edge-triggered interrupt escaping meanwhile. |
| 1793 | * The idea is from Manfred Spraul. --macro |
Suresh Siddha | 1c83995 | 2009-12-01 15:31:17 -0800 | [diff] [blame] | 1794 | * |
| 1795 | * Also in the case when cpu goes offline, fixup_irqs() will forward |
| 1796 | * any unhandled interrupt on the offlined cpu to the new cpu |
| 1797 | * destination that is handling the corresponding interrupt. This |
| 1798 | * interrupt forwarding is done via IPI's. Hence, in this case also |
| 1799 | * level-triggered io-apic interrupt will be seen as an edge |
| 1800 | * interrupt in the IRR. And we can't rely on the cpu's EOI |
| 1801 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR |
| 1802 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's |
| 1803 | * supporting EOI register, we do an explicit EOI to clear the |
| 1804 | * remote IRR and on IO-APIC's which don't have an EOI register, |
| 1805 | * we use the above logic (mask+edge followed by unmask+level) from |
| 1806 | * Manfred Spraul to clear the remote IRR. |
Jeremy Fitzhardinge | 916a0fe | 2009-06-08 03:00:22 -0700 | [diff] [blame] | 1807 | */ |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 1808 | i = cfg->vector; |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 1809 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 1810 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1811 | /* |
| 1812 | * We must acknowledge the irq before we move it or the acknowledge will |
| 1813 | * not propagate properly. |
| 1814 | */ |
| 1815 | ack_APIC_irq(); |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1816 | |
Suresh Siddha | 1c83995 | 2009-12-01 15:31:17 -0800 | [diff] [blame] | 1817 | /* |
| 1818 | * Tail end of clearing remote IRR bit (either by delivering the EOI |
| 1819 | * message via io-apic EOI register write or simulating it using |
| 1820 | * mask+edge followed by unnask+level logic) manually when the |
| 1821 | * level triggered interrupt is seen as the edge triggered interrupt |
| 1822 | * at the cpu. |
| 1823 | */ |
Maciej W. Rozycki | ca64c47 | 2009-12-01 15:31:15 -0800 | [diff] [blame] | 1824 | if (!(v & (1 << (i & 0x1f)))) { |
| 1825 | atomic_inc(&irq_mis_count); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1826 | eoi_ioapic_pin(cfg->vector, irq_data->chip_data); |
Maciej W. Rozycki | ca64c47 | 2009-12-01 15:31:15 -0800 | [diff] [blame] | 1827 | } |
| 1828 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1829 | ioapic_irqd_unmask(irq_data, masked); |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 1830 | } |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 1831 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1832 | static void ioapic_ir_ack_level(struct irq_data *irq_data) |
| 1833 | { |
| 1834 | struct mp_chip_data *data = irq_data->chip_data; |
| 1835 | |
| 1836 | /* |
| 1837 | * Intr-remapping uses pin number as the virtual vector |
| 1838 | * in the RTE. Actual vector is programmed in |
| 1839 | * intr-remapping table entry. Hence for the io-apic |
| 1840 | * EOI we use the pin number. |
| 1841 | */ |
| 1842 | ack_APIC_irq(); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 1843 | eoi_ioapic_pin(data->entry.vector, data); |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1844 | } |
| 1845 | |
| 1846 | static int ioapic_set_affinity(struct irq_data *irq_data, |
| 1847 | const struct cpumask *mask, bool force) |
| 1848 | { |
| 1849 | struct irq_data *parent = irq_data->parent_data; |
| 1850 | struct mp_chip_data *data = irq_data->chip_data; |
Jiang Liu | 0be275e | 2015-04-14 10:29:57 +0800 | [diff] [blame] | 1851 | struct irq_pin_list *entry; |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1852 | struct irq_cfg *cfg; |
| 1853 | unsigned long flags; |
| 1854 | int ret; |
| 1855 | |
| 1856 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
| 1857 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
| 1858 | if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) { |
| 1859 | cfg = irqd_cfg(irq_data); |
| 1860 | data->entry.dest = cfg->dest_apicid; |
| 1861 | data->entry.vector = cfg->vector; |
Jiang Liu | 0be275e | 2015-04-14 10:29:57 +0800 | [diff] [blame] | 1862 | for_each_irq_pin(entry, data->irq_2_pin) |
| 1863 | __ioapic_write_entry(entry->apic, entry->pin, |
| 1864 | data->entry); |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1865 | } |
| 1866 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1867 | |
| 1868 | return ret; |
| 1869 | } |
| 1870 | |
Ingo Molnar | f5b9ed7 | 2006-10-04 02:16:26 -0700 | [diff] [blame] | 1871 | static struct irq_chip ioapic_chip __read_mostly = { |
Thomas Gleixner | f7e909e | 2010-10-08 21:40:23 +0200 | [diff] [blame] | 1872 | .name = "IO-APIC", |
| 1873 | .irq_startup = startup_ioapic_irq, |
| 1874 | .irq_mask = mask_ioapic_irq, |
| 1875 | .irq_unmask = unmask_ioapic_irq, |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 1876 | .irq_ack = irq_chip_ack_parent, |
| 1877 | .irq_eoi = ioapic_ack_level, |
| 1878 | .irq_set_affinity = ioapic_set_affinity, |
| 1879 | .flags = IRQCHIP_SKIP_SET_WAKE, |
| 1880 | }; |
| 1881 | |
| 1882 | static struct irq_chip ioapic_ir_chip __read_mostly = { |
| 1883 | .name = "IR-IO-APIC", |
| 1884 | .irq_startup = startup_ioapic_irq, |
| 1885 | .irq_mask = mask_ioapic_irq, |
| 1886 | .irq_unmask = unmask_ioapic_irq, |
| 1887 | .irq_ack = irq_chip_ack_parent, |
| 1888 | .irq_eoi = ioapic_ir_ack_level, |
| 1889 | .irq_set_affinity = ioapic_set_affinity, |
Rafael J. Wysocki | 5613570 | 2014-09-01 13:49:07 +0200 | [diff] [blame] | 1890 | .flags = IRQCHIP_SKIP_SET_WAKE, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1891 | }; |
| 1892 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1893 | static inline void init_IO_APIC_traps(void) |
| 1894 | { |
Yinghai Lu | da51a82 | 2008-08-19 20:50:25 -0700 | [diff] [blame] | 1895 | struct irq_cfg *cfg; |
Thomas Gleixner | ad9f433 | 2010-09-30 11:26:43 +0200 | [diff] [blame] | 1896 | unsigned int irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1897 | |
Thomas Gleixner | ad9f433 | 2010-09-30 11:26:43 +0200 | [diff] [blame] | 1898 | for_each_active_irq(irq) { |
Jiang Liu | 32f5ef5 | 2014-06-09 16:19:43 +0800 | [diff] [blame] | 1899 | cfg = irq_cfg(irq); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 1900 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1901 | /* |
| 1902 | * Hmm.. We don't have an entry for this, |
| 1903 | * so default to an old-fashioned 8259 |
| 1904 | * interrupt if we can.. |
| 1905 | */ |
Jiang Liu | 95d76ac | 2014-06-09 16:19:48 +0800 | [diff] [blame] | 1906 | if (irq < nr_legacy_irqs()) |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 1907 | legacy_pic->make_irq(irq); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 1908 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1909 | /* Strange. Oh, well.. */ |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 1910 | irq_set_chip(irq, &no_irq_chip); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1911 | } |
| 1912 | } |
| 1913 | } |
| 1914 | |
Ingo Molnar | f5b9ed7 | 2006-10-04 02:16:26 -0700 | [diff] [blame] | 1915 | /* |
| 1916 | * The local APIC irq-chip implementation: |
| 1917 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1918 | |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 1919 | static void mask_lapic_irq(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1920 | { |
| 1921 | unsigned long v; |
| 1922 | |
| 1923 | v = apic_read(APIC_LVT0); |
Maciej W. Rozycki | 593f4a7 | 2008-07-16 19:15:30 +0100 | [diff] [blame] | 1924 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1925 | } |
| 1926 | |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 1927 | static void unmask_lapic_irq(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1928 | { |
Ingo Molnar | f5b9ed7 | 2006-10-04 02:16:26 -0700 | [diff] [blame] | 1929 | unsigned long v; |
| 1930 | |
| 1931 | v = apic_read(APIC_LVT0); |
Maciej W. Rozycki | 593f4a7 | 2008-07-16 19:15:30 +0100 | [diff] [blame] | 1932 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1933 | } |
| 1934 | |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 1935 | static void ack_lapic_irq(struct irq_data *data) |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 1936 | { |
| 1937 | ack_APIC_irq(); |
| 1938 | } |
| 1939 | |
Ingo Molnar | f5b9ed7 | 2006-10-04 02:16:26 -0700 | [diff] [blame] | 1940 | static struct irq_chip lapic_chip __read_mostly = { |
Maciej W. Rozycki | 9a1c619 | 2008-05-27 21:19:09 +0100 | [diff] [blame] | 1941 | .name = "local-APIC", |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 1942 | .irq_mask = mask_lapic_irq, |
| 1943 | .irq_unmask = unmask_lapic_irq, |
| 1944 | .irq_ack = ack_lapic_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1945 | }; |
| 1946 | |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 1947 | static void lapic_register_intr(int irq) |
Maciej W. Rozycki | c88ac1d | 2008-07-11 19:35:17 +0100 | [diff] [blame] | 1948 | { |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 1949 | irq_clear_status_flags(irq, IRQ_LEVEL); |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 1950 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
Maciej W. Rozycki | c88ac1d | 2008-07-11 19:35:17 +0100 | [diff] [blame] | 1951 | "edge"); |
Maciej W. Rozycki | c88ac1d | 2008-07-11 19:35:17 +0100 | [diff] [blame] | 1952 | } |
| 1953 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1954 | /* |
| 1955 | * This looks a bit hackish but it's about the only one way of sending |
| 1956 | * a few INTA cycles to 8259As and any associated glue logic. ICR does |
| 1957 | * not support the ExtINT mode, unfortunately. We need to send these |
| 1958 | * cycles as some i82489DX-based boards have glue logic that keeps the |
| 1959 | * 8259A interrupt line asserted until INTA. --macro |
| 1960 | */ |
Jacek Luczak | 28acf28 | 2008-04-12 17:41:12 +0200 | [diff] [blame] | 1961 | static inline void __init unlock_ExtINT_logic(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1962 | { |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1963 | int apic, pin, i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1964 | struct IO_APIC_route_entry entry0, entry1; |
| 1965 | unsigned char save_control, save_freq_select; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1966 | |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1967 | pin = find_isa_irq_pin(8, mp_INT); |
Adrian Bunk | 956fb53 | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 1968 | if (pin == -1) { |
| 1969 | WARN_ON_ONCE(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1970 | return; |
Adrian Bunk | 956fb53 | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 1971 | } |
| 1972 | apic = find_isa_irq_apic(8, mp_INT); |
| 1973 | if (apic == -1) { |
| 1974 | WARN_ON_ONCE(1); |
| 1975 | return; |
| 1976 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1977 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 1978 | entry0 = ioapic_read_entry(apic, pin); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1979 | clear_IO_APIC_pin(apic, pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1980 | |
| 1981 | memset(&entry1, 0, sizeof(entry1)); |
| 1982 | |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 1983 | entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL; |
| 1984 | entry1.mask = IOAPIC_UNMASKED; |
Yinghai Lu | d83e94a | 2008-08-19 20:50:33 -0700 | [diff] [blame] | 1985 | entry1.dest = hard_smp_processor_id(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1986 | entry1.delivery_mode = dest_ExtINT; |
| 1987 | entry1.polarity = entry0.polarity; |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 1988 | entry1.trigger = IOAPIC_EDGE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1989 | entry1.vector = 0; |
| 1990 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 1991 | ioapic_write_entry(apic, pin, entry1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1992 | |
| 1993 | save_control = CMOS_READ(RTC_CONTROL); |
| 1994 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); |
| 1995 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, |
| 1996 | RTC_FREQ_SELECT); |
| 1997 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); |
| 1998 | |
| 1999 | i = 100; |
| 2000 | while (i-- > 0) { |
| 2001 | mdelay(10); |
| 2002 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) |
| 2003 | i -= 10; |
| 2004 | } |
| 2005 | |
| 2006 | CMOS_WRITE(save_control, RTC_CONTROL); |
| 2007 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2008 | clear_IO_APIC_pin(apic, pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2009 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 2010 | ioapic_write_entry(apic, pin, entry0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2011 | } |
| 2012 | |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 2013 | static int disable_timer_pin_1 __initdata; |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 2014 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2015 | static int __init disable_timer_pin_setup(char *arg) |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 2016 | { |
| 2017 | disable_timer_pin_1 = 1; |
| 2018 | return 0; |
| 2019 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2020 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 2021 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 2022 | static int mp_alloc_timer_irq(int ioapic, int pin) |
| 2023 | { |
| 2024 | int irq = -1; |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 2025 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); |
| 2026 | |
| 2027 | if (domain) { |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 2028 | struct irq_alloc_info info; |
| 2029 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 2030 | ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0); |
| 2031 | info.ioapic_id = mpc_ioapic_id(ioapic); |
| 2032 | info.ioapic_pin = pin; |
| 2033 | mutex_lock(&ioapic_mutex); |
| 2034 | irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); |
| 2035 | mutex_unlock(&ioapic_mutex); |
| 2036 | } |
| 2037 | |
| 2038 | return irq; |
| 2039 | } |
| 2040 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2041 | /* |
| 2042 | * This code may look a bit paranoid, but it's supposed to cooperate with |
| 2043 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ |
| 2044 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast |
| 2045 | * fanatically on his truly buggy board. |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2046 | * |
| 2047 | * FIXME: really need to revamp this for all platforms. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2048 | */ |
Zachary Amsden | 8542b20 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 2049 | static inline void __init check_timer(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2050 | { |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 2051 | struct irq_data *irq_data = irq_get_irq_data(0); |
| 2052 | struct mp_chip_data *data = irq_data->chip_data; |
| 2053 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
Robert Richter | f6e9456c | 2010-07-21 19:03:58 +0200 | [diff] [blame] | 2054 | int node = cpu_to_node(0); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2055 | int apic1, pin1, apic2, pin2; |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2056 | unsigned long flags; |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 2057 | int no_pin1 = 0; |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2058 | |
| 2059 | local_irq_save(flags); |
Maciej W. Rozycki | d4d25de | 2007-11-26 20:42:19 +0100 | [diff] [blame] | 2060 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2061 | /* |
| 2062 | * get/set the timer IRQ vector: |
| 2063 | */ |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 2064 | legacy_pic->mask(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2065 | |
| 2066 | /* |
Maciej W. Rozycki | d11d579 | 2008-05-21 22:09:11 +0100 | [diff] [blame] | 2067 | * As IRQ0 is to be enabled in the 8259A, the virtual |
| 2068 | * wire has to be disabled in the local APIC. Also |
| 2069 | * timer interrupts need to be acknowledged manually in |
| 2070 | * the 8259A for the i82489DX when using the NMI |
| 2071 | * watchdog as that APIC treats NMIs as level-triggered. |
| 2072 | * The AEOI mode will finish them in the 8259A |
| 2073 | * automatically. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2074 | */ |
Maciej W. Rozycki | 593f4a7 | 2008-07-16 19:15:30 +0100 | [diff] [blame] | 2075 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 2076 | legacy_pic->init(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2077 | |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2078 | pin1 = find_isa_irq_pin(0, mp_INT); |
| 2079 | apic1 = find_isa_irq_apic(0, mp_INT); |
| 2080 | pin2 = ioapic_i8259.pin; |
| 2081 | apic2 = ioapic_i8259.apic; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2082 | |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2083 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
| 2084 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2085 | cfg->vector, apic1, pin1, apic2, pin2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2086 | |
Maciej W. Rozycki | 691874f | 2008-05-27 21:19:51 +0100 | [diff] [blame] | 2087 | /* |
| 2088 | * Some BIOS writers are clueless and report the ExtINTA |
| 2089 | * I/O APIC input from the cascaded 8259A as the timer |
| 2090 | * interrupt input. So just in case, if only one pin |
| 2091 | * was found above, try it both directly and through the |
| 2092 | * 8259A. |
| 2093 | */ |
| 2094 | if (pin1 == -1) { |
Joerg Roedel | 6a9f5de | 2012-09-26 12:44:41 +0200 | [diff] [blame] | 2095 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
Maciej W. Rozycki | 691874f | 2008-05-27 21:19:51 +0100 | [diff] [blame] | 2096 | pin1 = pin2; |
| 2097 | apic1 = apic2; |
| 2098 | no_pin1 = 1; |
| 2099 | } else if (pin2 == -1) { |
| 2100 | pin2 = pin1; |
| 2101 | apic2 = apic1; |
| 2102 | } |
| 2103 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2104 | if (pin1 != -1) { |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 2105 | /* Ok, does IRQ0 through the IOAPIC work? */ |
Maciej W. Rozycki | 691874f | 2008-05-27 21:19:51 +0100 | [diff] [blame] | 2106 | if (no_pin1) { |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 2107 | mp_alloc_timer_irq(apic1, pin1); |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2108 | } else { |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 2109 | /* |
| 2110 | * for edge trigger, it's already unmasked, |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2111 | * so only need to unmask if it is level-trigger |
| 2112 | * do we really have level trigger timer? |
| 2113 | */ |
| 2114 | int idx; |
| 2115 | idx = find_irq_entry(apic1, pin1, mp_INT); |
| 2116 | if (idx != -1 && irq_trigger(idx)) |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 2117 | unmask_ioapic_irq(irq_get_chip_data(0)); |
Maciej W. Rozycki | 691874f | 2008-05-27 21:19:51 +0100 | [diff] [blame] | 2118 | } |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 2119 | irq_domain_activate_irq(irq_data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2120 | if (timer_irq_works()) { |
Chuck Ebbert | 66759a0 | 2005-09-12 18:49:25 +0200 | [diff] [blame] | 2121 | if (disable_timer_pin_1 > 0) |
| 2122 | clear_IO_APIC_pin(0, pin1); |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2123 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2124 | } |
Joerg Roedel | 6a9f5de | 2012-09-26 12:44:41 +0200 | [diff] [blame] | 2125 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2126 | local_irq_disable(); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2127 | clear_IO_APIC_pin(apic1, pin1); |
Maciej W. Rozycki | 691874f | 2008-05-27 21:19:51 +0100 | [diff] [blame] | 2128 | if (!no_pin1) |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2129 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
| 2130 | "8254 timer not connected to IO-APIC\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2131 | |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2132 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
| 2133 | "(IRQ0) through the 8259A ...\n"); |
| 2134 | apic_printk(APIC_QUIET, KERN_INFO |
| 2135 | "..... (found apic %d pin %d) ...\n", apic2, pin2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2136 | /* |
| 2137 | * legacy devices should be connected to IO APIC #0 |
| 2138 | */ |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 2139 | replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2); |
| 2140 | irq_domain_activate_irq(irq_data); |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 2141 | legacy_pic->unmask(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2142 | if (timer_irq_works()) { |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2143 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2144 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2145 | } |
| 2146 | /* |
| 2147 | * Cleanup, just in case ... |
| 2148 | */ |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2149 | local_irq_disable(); |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 2150 | legacy_pic->mask(0); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2151 | clear_IO_APIC_pin(apic2, pin2); |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2152 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2153 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2154 | |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2155 | apic_printk(APIC_QUIET, KERN_INFO |
| 2156 | "...trying to set up timer as Virtual Wire IRQ...\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2157 | |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 2158 | lapic_register_intr(0); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2159 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 2160 | legacy_pic->unmask(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2161 | |
| 2162 | if (timer_irq_works()) { |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2163 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2164 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2165 | } |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2166 | local_irq_disable(); |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 2167 | legacy_pic->mask(0); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2168 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2169 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2170 | |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2171 | apic_printk(APIC_QUIET, KERN_INFO |
| 2172 | "...trying to set up timer as ExtINT IRQ...\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2173 | |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 2174 | legacy_pic->init(0); |
| 2175 | legacy_pic->make_irq(0); |
Maciej W. Rozycki | 593f4a7 | 2008-07-16 19:15:30 +0100 | [diff] [blame] | 2176 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2177 | |
| 2178 | unlock_ExtINT_logic(); |
| 2179 | |
| 2180 | if (timer_irq_works()) { |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2181 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2182 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2183 | } |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2184 | local_irq_disable(); |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2185 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
Thomas Gleixner | 2ca5b40 | 2015-01-15 21:22:14 +0000 | [diff] [blame] | 2186 | if (apic_is_x2apic_enabled()) |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 2187 | apic_printk(APIC_QUIET, KERN_INFO |
| 2188 | "Perhaps problem with the pre-enabled x2apic mode\n" |
| 2189 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2190 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2191 | "report. Then try booting with the 'noapic' option.\n"); |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2192 | out: |
| 2193 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2194 | } |
| 2195 | |
| 2196 | /* |
Maciej W. Rozycki | af17478 | 2008-07-11 19:35:23 +0100 | [diff] [blame] | 2197 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
| 2198 | * to devices. However there may be an I/O APIC pin available for |
| 2199 | * this interrupt regardless. The pin may be left unconnected, but |
| 2200 | * typically it will be reused as an ExtINT cascade interrupt for |
| 2201 | * the master 8259A. In the MPS case such a pin will normally be |
| 2202 | * reported as an ExtINT interrupt in the MP table. With ACPI |
| 2203 | * there is no provision for ExtINT interrupts, and in the absence |
| 2204 | * of an override it would be treated as an ordinary ISA I/O APIC |
| 2205 | * interrupt, that is edge-triggered and unmasked by default. We |
| 2206 | * used to do this, but it caused problems on some systems because |
| 2207 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using |
| 2208 | * the same ExtINT cascade interrupt to drive the local APIC of the |
| 2209 | * bootstrap processor. Therefore we refrain from routing IRQ2 to |
| 2210 | * the I/O APIC in all cases now. No actual device should request |
| 2211 | * it anyway. --macro |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2212 | */ |
Thomas Gleixner | bc07844 | 2009-08-29 18:09:57 +0200 | [diff] [blame] | 2213 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2214 | |
Jiang Liu | 44767bf | 2014-06-09 16:19:53 +0800 | [diff] [blame] | 2215 | static int mp_irqdomain_create(int ioapic) |
| 2216 | { |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 2217 | struct irq_alloc_info info; |
| 2218 | struct irq_domain *parent; |
Jiang Liu | 44767bf | 2014-06-09 16:19:53 +0800 | [diff] [blame] | 2219 | int hwirqs = mp_ioapic_pin_count(ioapic); |
| 2220 | struct ioapic *ip = &ioapics[ioapic]; |
| 2221 | struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; |
| 2222 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); |
| 2223 | |
| 2224 | if (cfg->type == IOAPIC_DOMAIN_INVALID) |
| 2225 | return 0; |
| 2226 | |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 2227 | init_irq_alloc_info(&info, NULL); |
| 2228 | info.type = X86_IRQ_ALLOC_TYPE_IOAPIC; |
| 2229 | info.ioapic_id = mpc_ioapic_id(ioapic); |
| 2230 | parent = irq_remapping_get_ir_irq_domain(&info); |
| 2231 | if (!parent) |
| 2232 | parent = x86_vector_domain; |
| 2233 | |
Jiang Liu | 44767bf | 2014-06-09 16:19:53 +0800 | [diff] [blame] | 2234 | ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops, |
| 2235 | (void *)(long)ioapic); |
Jiang Liu | b75e818 | 2015-04-14 10:29:39 +0800 | [diff] [blame] | 2236 | if (!ip->irqdomain) |
Jiang Liu | 44767bf | 2014-06-09 16:19:53 +0800 | [diff] [blame] | 2237 | return -ENOMEM; |
Jiang Liu | b75e818 | 2015-04-14 10:29:39 +0800 | [diff] [blame] | 2238 | |
| 2239 | ip->irqdomain->parent = parent; |
Jiang Liu | 44767bf | 2014-06-09 16:19:53 +0800 | [diff] [blame] | 2240 | |
| 2241 | if (cfg->type == IOAPIC_DOMAIN_LEGACY || |
| 2242 | cfg->type == IOAPIC_DOMAIN_STRICT) |
| 2243 | ioapic_dynirq_base = max(ioapic_dynirq_base, |
| 2244 | gsi_cfg->gsi_end + 1); |
| 2245 | |
Jiang Liu | 44767bf | 2014-06-09 16:19:53 +0800 | [diff] [blame] | 2246 | return 0; |
| 2247 | } |
| 2248 | |
Jiang Liu | 15516a3 | 2014-10-27 13:21:46 +0800 | [diff] [blame] | 2249 | static void ioapic_destroy_irqdomain(int idx) |
| 2250 | { |
| 2251 | if (ioapics[idx].irqdomain) { |
| 2252 | irq_domain_remove(ioapics[idx].irqdomain); |
| 2253 | ioapics[idx].irqdomain = NULL; |
| 2254 | } |
Jiang Liu | 15516a3 | 2014-10-27 13:21:46 +0800 | [diff] [blame] | 2255 | } |
| 2256 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2257 | void __init setup_IO_APIC(void) |
| 2258 | { |
Jiang Liu | 44767bf | 2014-06-09 16:19:53 +0800 | [diff] [blame] | 2259 | int ioapic; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2260 | |
Thomas Gleixner | a46f5c8 | 2015-01-15 21:22:32 +0000 | [diff] [blame] | 2261 | if (skip_ioapic_setup || !nr_ioapics) |
| 2262 | return; |
| 2263 | |
Jiang Liu | 95d76ac | 2014-06-09 16:19:48 +0800 | [diff] [blame] | 2264 | io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2265 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2266 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
Jiang Liu | 44767bf | 2014-06-09 16:19:53 +0800 | [diff] [blame] | 2267 | for_each_ioapic(ioapic) |
| 2268 | BUG_ON(mp_irqdomain_create(ioapic)); |
| 2269 | |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 2270 | /* |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2271 | * Set up IO-APIC IRQ routing. |
| 2272 | */ |
Thomas Gleixner | de93410 | 2009-08-20 09:27:29 +0200 | [diff] [blame] | 2273 | x86_init.mpparse.setup_ioapic_ids(); |
| 2274 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2275 | sync_Arb_IDs(); |
| 2276 | setup_IO_APIC_irqs(); |
| 2277 | init_IO_APIC_traps(); |
Jiang Liu | 95d76ac | 2014-06-09 16:19:48 +0800 | [diff] [blame] | 2278 | if (nr_legacy_irqs()) |
Thomas Gleixner | bc07844 | 2009-08-29 18:09:57 +0200 | [diff] [blame] | 2279 | check_timer(); |
Jiang Liu | b81975e | 2014-06-09 16:20:11 +0800 | [diff] [blame] | 2280 | |
| 2281 | ioapic_initialized = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2282 | } |
| 2283 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2284 | static void resume_ioapic_id(int ioapic_idx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2285 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2286 | unsigned long flags; |
| 2287 | union IO_APIC_reg_00 reg_00; |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 2288 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2289 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2290 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
| 2291 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { |
| 2292 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
| 2293 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2294 | } |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2295 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2296 | } |
| 2297 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2298 | static void ioapic_resume(void) |
| 2299 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2300 | int ioapic_idx; |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2301 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 2302 | for_each_ioapic_reverse(ioapic_idx) |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2303 | resume_ioapic_id(ioapic_idx); |
Suresh Siddha | 15bac20 | 2011-05-18 16:31:34 -0700 | [diff] [blame] | 2304 | |
| 2305 | restore_ioapic_entries(); |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2306 | } |
| 2307 | |
| 2308 | static struct syscore_ops ioapic_syscore_ops = { |
Suresh Siddha | 15bac20 | 2011-05-18 16:31:34 -0700 | [diff] [blame] | 2309 | .suspend = save_ioapic_entries, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2310 | .resume = ioapic_resume, |
| 2311 | }; |
| 2312 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2313 | static int __init ioapic_init_ops(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2314 | { |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2315 | register_syscore_ops(&ioapic_syscore_ops); |
| 2316 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2317 | return 0; |
| 2318 | } |
| 2319 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2320 | device_initcall(ioapic_init_ops); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2321 | |
Jiang Liu | 67dc5e7 | 2014-10-27 13:21:41 +0800 | [diff] [blame] | 2322 | static int io_apic_get_redir_entries(int ioapic) |
Yinghai Lu | 9d6a4d0 | 2008-08-19 20:50:52 -0700 | [diff] [blame] | 2323 | { |
| 2324 | union IO_APIC_reg_01 reg_01; |
| 2325 | unsigned long flags; |
| 2326 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2327 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 9d6a4d0 | 2008-08-19 20:50:52 -0700 | [diff] [blame] | 2328 | reg_01.raw = io_apic_read(ioapic, 1); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2329 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Yinghai Lu | 9d6a4d0 | 2008-08-19 20:50:52 -0700 | [diff] [blame] | 2330 | |
Eric W. Biederman | 4b6b19a | 2010-03-30 01:07:08 -0700 | [diff] [blame] | 2331 | /* The register returns the maximum index redir index |
| 2332 | * supported, which is one less than the total number of redir |
| 2333 | * entries. |
| 2334 | */ |
| 2335 | return reg_01.bits.entries + 1; |
Yinghai Lu | 9d6a4d0 | 2008-08-19 20:50:52 -0700 | [diff] [blame] | 2336 | } |
| 2337 | |
Thomas Gleixner | 62a08ae | 2014-04-24 09:50:53 +0200 | [diff] [blame] | 2338 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
| 2339 | { |
Jiang Liu | b81975e | 2014-06-09 16:20:11 +0800 | [diff] [blame] | 2340 | /* |
| 2341 | * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use |
| 2342 | * gsi_top if ioapic_dynirq_base hasn't been initialized yet. |
| 2343 | */ |
| 2344 | return ioapic_initialized ? ioapic_dynirq_base : gsi_top; |
Thomas Gleixner | 62a08ae | 2014-04-24 09:50:53 +0200 | [diff] [blame] | 2345 | } |
| 2346 | |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2347 | #ifdef CONFIG_X86_32 |
Jiang Liu | 67dc5e7 | 2014-10-27 13:21:41 +0800 | [diff] [blame] | 2348 | static int io_apic_get_unique_id(int ioapic, int apic_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2349 | { |
| 2350 | union IO_APIC_reg_00 reg_00; |
| 2351 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; |
| 2352 | physid_mask_t tmp; |
| 2353 | unsigned long flags; |
| 2354 | int i = 0; |
| 2355 | |
| 2356 | /* |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 2357 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
| 2358 | * buses (one for LAPICs, one for IOAPICs), where predecessors only |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2359 | * supports up to 16 on one shared APIC bus. |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 2360 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2361 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
| 2362 | * advantage of new APIC bus architecture. |
| 2363 | */ |
| 2364 | |
| 2365 | if (physids_empty(apic_id_map)) |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 2366 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2367 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2368 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2369 | reg_00.raw = io_apic_read(ioapic, 0); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2370 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2371 | |
| 2372 | if (apic_id >= get_physical_broadcast()) { |
| 2373 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " |
| 2374 | "%d\n", ioapic, apic_id, reg_00.bits.ID); |
| 2375 | apic_id = reg_00.bits.ID; |
| 2376 | } |
| 2377 | |
| 2378 | /* |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 2379 | * Every APIC in a system must have a unique ID or we get lots of nice |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2380 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
| 2381 | */ |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 2382 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2383 | |
| 2384 | for (i = 0; i < get_physical_broadcast(); i++) { |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 2385 | if (!apic->check_apicid_used(&apic_id_map, i)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2386 | break; |
| 2387 | } |
| 2388 | |
| 2389 | if (i == get_physical_broadcast()) |
| 2390 | panic("Max apic_id exceeded!\n"); |
| 2391 | |
| 2392 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " |
| 2393 | "trying %d\n", ioapic, apic_id, i); |
| 2394 | |
| 2395 | apic_id = i; |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 2396 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2397 | |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 2398 | apic->apicid_to_cpu_present(apic_id, &tmp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2399 | physids_or(apic_id_map, apic_id_map, tmp); |
| 2400 | |
| 2401 | if (reg_00.bits.ID != apic_id) { |
| 2402 | reg_00.bits.ID = apic_id; |
| 2403 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2404 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2405 | io_apic_write(ioapic, 0, reg_00.raw); |
| 2406 | reg_00.raw = io_apic_read(ioapic, 0); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2407 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2408 | |
| 2409 | /* Sanity check */ |
Andreas Deresch | 6070f9e | 2006-02-26 04:18:34 +0100 | [diff] [blame] | 2410 | if (reg_00.bits.ID != apic_id) { |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 2411 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
| 2412 | ioapic); |
Andreas Deresch | 6070f9e | 2006-02-26 04:18:34 +0100 | [diff] [blame] | 2413 | return -1; |
| 2414 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2415 | } |
| 2416 | |
| 2417 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 2418 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); |
| 2419 | |
| 2420 | return apic_id; |
| 2421 | } |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 2422 | |
Jiang Liu | 67dc5e7 | 2014-10-27 13:21:41 +0800 | [diff] [blame] | 2423 | static u8 io_apic_unique_id(int idx, u8 id) |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 2424 | { |
| 2425 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && |
Denys Vlasenko | cff9ab2 | 2016-09-13 20:12:32 +0200 | [diff] [blame] | 2426 | !APIC_XAPIC(boot_cpu_apic_version)) |
Yinghai Lu | 5411dc4 | 2014-10-27 13:21:40 +0800 | [diff] [blame] | 2427 | return io_apic_get_unique_id(idx, id); |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 2428 | else |
| 2429 | return id; |
| 2430 | } |
| 2431 | #else |
Jiang Liu | 67dc5e7 | 2014-10-27 13:21:41 +0800 | [diff] [blame] | 2432 | static u8 io_apic_unique_id(int idx, u8 id) |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 2433 | { |
Yinghai Lu | 5411dc4 | 2014-10-27 13:21:40 +0800 | [diff] [blame] | 2434 | union IO_APIC_reg_00 reg_00; |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 2435 | DECLARE_BITMAP(used, 256); |
Yinghai Lu | 5411dc4 | 2014-10-27 13:21:40 +0800 | [diff] [blame] | 2436 | unsigned long flags; |
| 2437 | u8 new_id; |
| 2438 | int i; |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 2439 | |
| 2440 | bitmap_zero(used, 256); |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 2441 | for_each_ioapic(i) |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 2442 | __set_bit(mpc_ioapic_id(i), used); |
Yinghai Lu | 5411dc4 | 2014-10-27 13:21:40 +0800 | [diff] [blame] | 2443 | |
| 2444 | /* Hand out the requested id if available */ |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 2445 | if (!test_bit(id, used)) |
| 2446 | return id; |
Yinghai Lu | 5411dc4 | 2014-10-27 13:21:40 +0800 | [diff] [blame] | 2447 | |
| 2448 | /* |
| 2449 | * Read the current id from the ioapic and keep it if |
| 2450 | * available. |
| 2451 | */ |
| 2452 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
| 2453 | reg_00.raw = io_apic_read(idx, 0); |
| 2454 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2455 | new_id = reg_00.bits.ID; |
| 2456 | if (!test_bit(new_id, used)) { |
| 2457 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 2458 | "IOAPIC[%d]: Using reg apic_id %d instead of %d\n", |
| 2459 | idx, new_id, id); |
| 2460 | return new_id; |
| 2461 | } |
| 2462 | |
| 2463 | /* |
| 2464 | * Get the next free id and write it to the ioapic. |
| 2465 | */ |
| 2466 | new_id = find_first_zero_bit(used, 256); |
| 2467 | reg_00.bits.ID = new_id; |
| 2468 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
| 2469 | io_apic_write(idx, 0, reg_00.raw); |
| 2470 | reg_00.raw = io_apic_read(idx, 0); |
| 2471 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2472 | /* Sanity check */ |
| 2473 | BUG_ON(reg_00.bits.ID != new_id); |
| 2474 | |
| 2475 | return new_id; |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 2476 | } |
Naga Chumbalkar | 58f892e | 2009-05-26 21:48:07 +0000 | [diff] [blame] | 2477 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2478 | |
Jiang Liu | 67dc5e7 | 2014-10-27 13:21:41 +0800 | [diff] [blame] | 2479 | static int io_apic_get_version(int ioapic) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2480 | { |
| 2481 | union IO_APIC_reg_01 reg_01; |
| 2482 | unsigned long flags; |
| 2483 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2484 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2485 | reg_01.raw = io_apic_read(ioapic, 1); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2486 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2487 | |
| 2488 | return reg_01.bits.version; |
| 2489 | } |
| 2490 | |
Eric W. Biederman | 9a0a91b | 2010-03-30 01:07:03 -0700 | [diff] [blame] | 2491 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
Shaohua Li | 61fd47e | 2007-11-17 01:05:28 -0500 | [diff] [blame] | 2492 | { |
Eric W. Biederman | 9a0a91b | 2010-03-30 01:07:03 -0700 | [diff] [blame] | 2493 | int ioapic, pin, idx; |
Shaohua Li | 61fd47e | 2007-11-17 01:05:28 -0500 | [diff] [blame] | 2494 | |
| 2495 | if (skip_ioapic_setup) |
| 2496 | return -1; |
| 2497 | |
Eric W. Biederman | 9a0a91b | 2010-03-30 01:07:03 -0700 | [diff] [blame] | 2498 | ioapic = mp_find_ioapic(gsi); |
| 2499 | if (ioapic < 0) |
Shaohua Li | 61fd47e | 2007-11-17 01:05:28 -0500 | [diff] [blame] | 2500 | return -1; |
| 2501 | |
Eric W. Biederman | 9a0a91b | 2010-03-30 01:07:03 -0700 | [diff] [blame] | 2502 | pin = mp_find_ioapic_pin(ioapic, gsi); |
| 2503 | if (pin < 0) |
| 2504 | return -1; |
| 2505 | |
| 2506 | idx = find_irq_entry(ioapic, pin, mp_INT); |
| 2507 | if (idx < 0) |
| 2508 | return -1; |
| 2509 | |
| 2510 | *trigger = irq_trigger(idx); |
| 2511 | *polarity = irq_polarity(idx); |
Shaohua Li | 61fd47e | 2007-11-17 01:05:28 -0500 | [diff] [blame] | 2512 | return 0; |
| 2513 | } |
| 2514 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2515 | /* |
| 2516 | * This function currently is only a helper for the i386 smp boot process where |
| 2517 | * we need to reprogram the ioredtbls to cater for the cpus which have come online |
Ingo Molnar | fe402e1 | 2009-01-28 04:32:51 +0100 | [diff] [blame] | 2518 | * so mask in all cases should simply be apic->target_cpus() |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2519 | */ |
| 2520 | #ifdef CONFIG_SMP |
| 2521 | void __init setup_ioapic_dest(void) |
| 2522 | { |
Eric W. Biederman | fad5399 | 2010-02-28 01:06:34 -0800 | [diff] [blame] | 2523 | int pin, ioapic, irq, irq_entry; |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 2524 | const struct cpumask *mask; |
Thomas Gleixner | e23b257 | 2016-01-14 08:43:38 +0100 | [diff] [blame] | 2525 | struct irq_desc *desc; |
Thomas Gleixner | 5451ddc | 2011-02-05 15:35:51 +0100 | [diff] [blame] | 2526 | struct irq_data *idata; |
Thomas Gleixner | 4857c91 | 2015-09-14 12:00:55 +0200 | [diff] [blame] | 2527 | struct irq_chip *chip; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2528 | |
| 2529 | if (skip_ioapic_setup == 1) |
| 2530 | return; |
| 2531 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 2532 | for_each_ioapic_pin(ioapic, pin) { |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 2533 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
| 2534 | if (irq_entry == -1) |
| 2535 | continue; |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 2536 | |
Jiang Liu | d7f3d47 | 2014-06-09 16:19:52 +0800 | [diff] [blame] | 2537 | irq = pin_2_irq(irq_entry, ioapic, pin, 0); |
| 2538 | if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq)) |
Eric W. Biederman | fad5399 | 2010-02-28 01:06:34 -0800 | [diff] [blame] | 2539 | continue; |
| 2540 | |
Thomas Gleixner | e23b257 | 2016-01-14 08:43:38 +0100 | [diff] [blame] | 2541 | desc = irq_to_desc(irq); |
| 2542 | raw_spin_lock_irq(&desc->lock); |
| 2543 | idata = irq_desc_get_irq_data(desc); |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 2544 | |
| 2545 | /* |
| 2546 | * Honour affinities which have been set in early boot |
| 2547 | */ |
Thomas Gleixner | 5451ddc | 2011-02-05 15:35:51 +0100 | [diff] [blame] | 2548 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
Jiang Liu | c149e4c | 2015-06-03 11:46:22 +0800 | [diff] [blame] | 2549 | mask = irq_data_get_affinity_mask(idata); |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 2550 | else |
| 2551 | mask = apic->target_cpus(); |
| 2552 | |
Thomas Gleixner | 4857c91 | 2015-09-14 12:00:55 +0200 | [diff] [blame] | 2553 | chip = irq_data_get_irq_chip(idata); |
Werner Pawlitschko | ababae4 | 2015-10-27 09:08:04 +0900 | [diff] [blame] | 2554 | /* Might be lapic_chip for irq 0 */ |
| 2555 | if (chip->irq_set_affinity) |
| 2556 | chip->irq_set_affinity(idata, mask, false); |
Thomas Gleixner | e23b257 | 2016-01-14 08:43:38 +0100 | [diff] [blame] | 2557 | raw_spin_unlock_irq(&desc->lock); |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 2558 | } |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2559 | } |
| 2560 | #endif |
| 2561 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2562 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
| 2563 | |
| 2564 | static struct resource *ioapic_resources; |
| 2565 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 2566 | static struct resource * __init ioapic_setup_resources(void) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2567 | { |
| 2568 | unsigned long n; |
| 2569 | struct resource *res; |
| 2570 | char *mem; |
Rui Wang | 4855531 | 2016-06-08 14:59:53 +0800 | [diff] [blame] | 2571 | int i; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2572 | |
Rui Wang | 4855531 | 2016-06-08 14:59:53 +0800 | [diff] [blame] | 2573 | if (nr_ioapics == 0) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2574 | return NULL; |
| 2575 | |
| 2576 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); |
Rui Wang | 4855531 | 2016-06-08 14:59:53 +0800 | [diff] [blame] | 2577 | n *= nr_ioapics; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2578 | |
| 2579 | mem = alloc_bootmem(n); |
| 2580 | res = (void *)mem; |
| 2581 | |
Rui Wang | 4855531 | 2016-06-08 14:59:53 +0800 | [diff] [blame] | 2582 | mem += sizeof(struct resource) * nr_ioapics; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2583 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 2584 | for_each_ioapic(i) { |
Rui Wang | 4855531 | 2016-06-08 14:59:53 +0800 | [diff] [blame] | 2585 | res[i].name = mem; |
| 2586 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; |
Cyrill Gorcunov | 4343fe1 | 2009-11-08 18:54:31 +0300 | [diff] [blame] | 2587 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
Cyrill Gorcunov | ffc4383 | 2009-08-24 21:53:39 +0400 | [diff] [blame] | 2588 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
Rui Wang | 4855531 | 2016-06-08 14:59:53 +0800 | [diff] [blame] | 2589 | ioapics[i].iomem_res = &res[i]; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2590 | } |
| 2591 | |
| 2592 | ioapic_resources = res; |
| 2593 | |
| 2594 | return res; |
| 2595 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2596 | |
Thomas Gleixner | ca1b886 | 2015-04-24 13:57:48 +0200 | [diff] [blame] | 2597 | void __init io_apic_init_mappings(void) |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 2598 | { |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 2599 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2600 | struct resource *ioapic_res; |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 2601 | int i; |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 2602 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 2603 | ioapic_res = ioapic_setup_resources(); |
| 2604 | for_each_ioapic(i) { |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 2605 | if (smp_found_config) { |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 2606 | ioapic_phys = mpc_ioapic_addr(i); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2607 | #ifdef CONFIG_X86_32 |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 2608 | if (!ioapic_phys) { |
| 2609 | printk(KERN_ERR |
| 2610 | "WARNING: bogus zero IO-APIC " |
| 2611 | "address found in MPTABLE, " |
| 2612 | "disabling IO/APIC support!\n"); |
| 2613 | smp_found_config = 0; |
| 2614 | skip_ioapic_setup = 1; |
| 2615 | goto fake_ioapic_page; |
| 2616 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2617 | #endif |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 2618 | } else { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2619 | #ifdef CONFIG_X86_32 |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 2620 | fake_ioapic_page: |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2621 | #endif |
Cyrill Gorcunov | e79c65a | 2009-11-16 18:14:26 +0300 | [diff] [blame] | 2622 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 2623 | ioapic_phys = __pa(ioapic_phys); |
| 2624 | } |
| 2625 | set_fixmap_nocache(idx, ioapic_phys); |
Cyrill Gorcunov | e79c65a | 2009-11-16 18:14:26 +0300 | [diff] [blame] | 2626 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
| 2627 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), |
| 2628 | ioapic_phys); |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 2629 | idx++; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2630 | |
Cyrill Gorcunov | ffc4383 | 2009-08-24 21:53:39 +0400 | [diff] [blame] | 2631 | ioapic_res->start = ioapic_phys; |
Cyrill Gorcunov | e79c65a | 2009-11-16 18:14:26 +0300 | [diff] [blame] | 2632 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
Cyrill Gorcunov | ffc4383 | 2009-08-24 21:53:39 +0400 | [diff] [blame] | 2633 | ioapic_res++; |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 2634 | } |
| 2635 | } |
| 2636 | |
Yinghai Lu | 857fdc5 | 2009-07-10 09:36:20 -0700 | [diff] [blame] | 2637 | void __init ioapic_insert_resources(void) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2638 | { |
| 2639 | int i; |
| 2640 | struct resource *r = ioapic_resources; |
| 2641 | |
| 2642 | if (!r) { |
Yinghai Lu | 857fdc5 | 2009-07-10 09:36:20 -0700 | [diff] [blame] | 2643 | if (nr_ioapics > 0) |
Bartlomiej Zolnierkiewicz | 04c93ce | 2009-03-20 21:02:55 +0100 | [diff] [blame] | 2644 | printk(KERN_ERR |
| 2645 | "IO APIC resources couldn't be allocated.\n"); |
Yinghai Lu | 857fdc5 | 2009-07-10 09:36:20 -0700 | [diff] [blame] | 2646 | return; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2647 | } |
| 2648 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 2649 | for_each_ioapic(i) { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2650 | insert_resource(&iomem_resource, r); |
| 2651 | r++; |
| 2652 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2653 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2654 | |
Eric W. Biederman | eddb0c5 | 2010-03-30 01:07:09 -0700 | [diff] [blame] | 2655 | int mp_find_ioapic(u32 gsi) |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2656 | { |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 2657 | int i; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2658 | |
Paul Bolle | 678301e | 2011-02-14 22:52:38 +0100 | [diff] [blame] | 2659 | if (nr_ioapics == 0) |
| 2660 | return -1; |
| 2661 | |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2662 | /* Find the IOAPIC that manages this GSI. */ |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 2663 | for_each_ioapic(i) { |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 2664 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 2665 | if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2666 | return i; |
| 2667 | } |
| 2668 | |
| 2669 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
| 2670 | return -1; |
| 2671 | } |
| 2672 | |
Eric W. Biederman | eddb0c5 | 2010-03-30 01:07:09 -0700 | [diff] [blame] | 2673 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2674 | { |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 2675 | struct mp_ioapic_gsi *gsi_cfg; |
| 2676 | |
Jiang Liu | f44d169 | 2014-06-09 16:19:42 +0800 | [diff] [blame] | 2677 | if (WARN_ON(ioapic < 0)) |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2678 | return -1; |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 2679 | |
| 2680 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); |
| 2681 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2682 | return -1; |
| 2683 | |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 2684 | return gsi - gsi_cfg->gsi_base; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2685 | } |
| 2686 | |
Jiang Liu | 67dc5e7 | 2014-10-27 13:21:41 +0800 | [diff] [blame] | 2687 | static int bad_ioapic_register(int idx) |
Suresh Siddha | 73d63d0 | 2012-03-12 11:36:33 -0700 | [diff] [blame] | 2688 | { |
| 2689 | union IO_APIC_reg_00 reg_00; |
| 2690 | union IO_APIC_reg_01 reg_01; |
| 2691 | union IO_APIC_reg_02 reg_02; |
| 2692 | |
| 2693 | reg_00.raw = io_apic_read(idx, 0); |
| 2694 | reg_01.raw = io_apic_read(idx, 1); |
| 2695 | reg_02.raw = io_apic_read(idx, 2); |
| 2696 | |
| 2697 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { |
| 2698 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", |
| 2699 | mpc_ioapic_addr(idx)); |
| 2700 | return 1; |
| 2701 | } |
| 2702 | |
| 2703 | return 0; |
| 2704 | } |
| 2705 | |
Jiang Liu | 35ef9c9 | 2014-10-27 13:21:43 +0800 | [diff] [blame] | 2706 | static int find_free_ioapic_entry(void) |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2707 | { |
Jiang Liu | 7db298c | 2014-10-27 13:21:45 +0800 | [diff] [blame] | 2708 | int idx; |
| 2709 | |
| 2710 | for (idx = 0; idx < MAX_IO_APICS; idx++) |
| 2711 | if (ioapics[idx].nr_registers == 0) |
| 2712 | return idx; |
| 2713 | |
| 2714 | return MAX_IO_APICS; |
Jiang Liu | 35ef9c9 | 2014-10-27 13:21:43 +0800 | [diff] [blame] | 2715 | } |
| 2716 | |
| 2717 | /** |
| 2718 | * mp_register_ioapic - Register an IOAPIC device |
| 2719 | * @id: hardware IOAPIC ID |
| 2720 | * @address: physical address of IOAPIC register area |
| 2721 | * @gsi_base: base of GSI associated with the IOAPIC |
| 2722 | * @cfg: configuration information for the IOAPIC |
| 2723 | */ |
| 2724 | int mp_register_ioapic(int id, u32 address, u32 gsi_base, |
| 2725 | struct ioapic_domain_cfg *cfg) |
| 2726 | { |
Jiang Liu | 7db298c | 2014-10-27 13:21:45 +0800 | [diff] [blame] | 2727 | bool hotplug = !!ioapic_initialized; |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 2728 | struct mp_ioapic_gsi *gsi_cfg; |
Jiang Liu | 35ef9c9 | 2014-10-27 13:21:43 +0800 | [diff] [blame] | 2729 | int idx, ioapic, entries; |
| 2730 | u32 gsi_end; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2731 | |
Jiang Liu | 35ef9c9 | 2014-10-27 13:21:43 +0800 | [diff] [blame] | 2732 | if (!address) { |
| 2733 | pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); |
| 2734 | return -EINVAL; |
| 2735 | } |
| 2736 | for_each_ioapic(ioapic) |
| 2737 | if (ioapics[ioapic].mp_config.apicaddr == address) { |
| 2738 | pr_warn("address 0x%x conflicts with IOAPIC%d\n", |
| 2739 | address, ioapic); |
| 2740 | return -EEXIST; |
| 2741 | } |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2742 | |
Jiang Liu | 35ef9c9 | 2014-10-27 13:21:43 +0800 | [diff] [blame] | 2743 | idx = find_free_ioapic_entry(); |
| 2744 | if (idx >= MAX_IO_APICS) { |
| 2745 | pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n", |
| 2746 | MAX_IO_APICS, idx); |
| 2747 | return -ENOSPC; |
| 2748 | } |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2749 | |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 2750 | ioapics[idx].mp_config.type = MP_IOAPIC; |
| 2751 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; |
| 2752 | ioapics[idx].mp_config.apicaddr = address; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2753 | |
| 2754 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); |
Suresh Siddha | 73d63d0 | 2012-03-12 11:36:33 -0700 | [diff] [blame] | 2755 | if (bad_ioapic_register(idx)) { |
| 2756 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); |
Jiang Liu | 35ef9c9 | 2014-10-27 13:21:43 +0800 | [diff] [blame] | 2757 | return -ENODEV; |
Suresh Siddha | 73d63d0 | 2012-03-12 11:36:33 -0700 | [diff] [blame] | 2758 | } |
| 2759 | |
Yinghai Lu | 5411dc4 | 2014-10-27 13:21:40 +0800 | [diff] [blame] | 2760 | ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id); |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 2761 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2762 | |
| 2763 | /* |
| 2764 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups |
| 2765 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). |
| 2766 | */ |
Eric W. Biederman | 7716a5c | 2010-03-30 01:07:12 -0700 | [diff] [blame] | 2767 | entries = io_apic_get_redir_entries(idx); |
Jiang Liu | 35ef9c9 | 2014-10-27 13:21:43 +0800 | [diff] [blame] | 2768 | gsi_end = gsi_base + entries - 1; |
| 2769 | for_each_ioapic(ioapic) { |
| 2770 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); |
| 2771 | if ((gsi_base >= gsi_cfg->gsi_base && |
| 2772 | gsi_base <= gsi_cfg->gsi_end) || |
| 2773 | (gsi_end >= gsi_cfg->gsi_base && |
| 2774 | gsi_end <= gsi_cfg->gsi_end)) { |
| 2775 | pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", |
| 2776 | gsi_base, gsi_end, |
| 2777 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); |
| 2778 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); |
| 2779 | return -ENOSPC; |
| 2780 | } |
| 2781 | } |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 2782 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
| 2783 | gsi_cfg->gsi_base = gsi_base; |
Jiang Liu | 35ef9c9 | 2014-10-27 13:21:43 +0800 | [diff] [blame] | 2784 | gsi_cfg->gsi_end = gsi_end; |
Eric W. Biederman | 7716a5c | 2010-03-30 01:07:12 -0700 | [diff] [blame] | 2785 | |
Jiang Liu | 35ef9c9 | 2014-10-27 13:21:43 +0800 | [diff] [blame] | 2786 | ioapics[idx].irqdomain = NULL; |
| 2787 | ioapics[idx].irqdomain_cfg = *cfg; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2788 | |
Jiang Liu | 7db298c | 2014-10-27 13:21:45 +0800 | [diff] [blame] | 2789 | /* |
| 2790 | * If mp_register_ioapic() is called during early boot stage when |
| 2791 | * walking ACPI/SFI/DT tables, it's too early to create irqdomain, |
| 2792 | * we are still using bootmem allocator. So delay it to setup_IO_APIC(). |
| 2793 | */ |
| 2794 | if (hotplug) { |
| 2795 | if (mp_irqdomain_create(idx)) { |
| 2796 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); |
| 2797 | return -ENOMEM; |
| 2798 | } |
| 2799 | alloc_ioapic_saved_registers(idx); |
| 2800 | } |
| 2801 | |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 2802 | if (gsi_cfg->gsi_end >= gsi_top) |
| 2803 | gsi_top = gsi_cfg->gsi_end + 1; |
Jiang Liu | 35ef9c9 | 2014-10-27 13:21:43 +0800 | [diff] [blame] | 2804 | if (nr_ioapics <= idx) |
| 2805 | nr_ioapics = idx + 1; |
| 2806 | |
| 2807 | /* Set nr_registers to mark entry present */ |
| 2808 | ioapics[idx].nr_registers = entries; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2809 | |
Suresh Siddha | 73d63d0 | 2012-03-12 11:36:33 -0700 | [diff] [blame] | 2810 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
| 2811 | idx, mpc_ioapic_id(idx), |
| 2812 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), |
| 2813 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2814 | |
Jiang Liu | 35ef9c9 | 2014-10-27 13:21:43 +0800 | [diff] [blame] | 2815 | return 0; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 2816 | } |
Jacob Pan | 05ddafb | 2009-09-23 07:20:23 -0700 | [diff] [blame] | 2817 | |
Jiang Liu | 15516a3 | 2014-10-27 13:21:46 +0800 | [diff] [blame] | 2818 | int mp_unregister_ioapic(u32 gsi_base) |
| 2819 | { |
| 2820 | int ioapic, pin; |
| 2821 | int found = 0; |
Jiang Liu | 15516a3 | 2014-10-27 13:21:46 +0800 | [diff] [blame] | 2822 | |
| 2823 | for_each_ioapic(ioapic) |
| 2824 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) { |
| 2825 | found = 1; |
| 2826 | break; |
| 2827 | } |
| 2828 | if (!found) { |
| 2829 | pr_warn("can't find IOAPIC for GSI %d\n", gsi_base); |
| 2830 | return -ENODEV; |
| 2831 | } |
| 2832 | |
| 2833 | for_each_pin(ioapic, pin) { |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 2834 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
| 2835 | int irq = mp_map_gsi_to_irq(gsi, 0, NULL); |
| 2836 | struct mp_chip_data *data; |
| 2837 | |
| 2838 | if (irq >= 0) { |
| 2839 | data = irq_get_chip_data(irq); |
| 2840 | if (data && data->count) { |
| 2841 | pr_warn("pin%d on IOAPIC%d is still in use.\n", |
| 2842 | pin, ioapic); |
| 2843 | return -EBUSY; |
| 2844 | } |
Jiang Liu | 15516a3 | 2014-10-27 13:21:46 +0800 | [diff] [blame] | 2845 | } |
| 2846 | } |
| 2847 | |
| 2848 | /* Mark entry not present */ |
| 2849 | ioapics[ioapic].nr_registers = 0; |
| 2850 | ioapic_destroy_irqdomain(ioapic); |
| 2851 | free_ioapic_saved_registers(ioapic); |
| 2852 | if (ioapics[ioapic].iomem_res) |
| 2853 | release_resource(ioapics[ioapic].iomem_res); |
| 2854 | clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic); |
| 2855 | memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic])); |
| 2856 | |
| 2857 | return 0; |
| 2858 | } |
| 2859 | |
Jiang Liu | e89900c | 2014-10-27 13:21:47 +0800 | [diff] [blame] | 2860 | int mp_ioapic_registered(u32 gsi_base) |
| 2861 | { |
| 2862 | int ioapic; |
| 2863 | |
| 2864 | for_each_ioapic(ioapic) |
| 2865 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) |
| 2866 | return 1; |
| 2867 | |
| 2868 | return 0; |
| 2869 | } |
| 2870 | |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2871 | static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data, |
Jiang Liu | 5ad274d | 2015-04-14 10:29:38 +0800 | [diff] [blame] | 2872 | struct irq_alloc_info *info) |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2873 | { |
| 2874 | if (info && info->ioapic_valid) { |
| 2875 | data->trigger = info->ioapic_trigger; |
| 2876 | data->polarity = info->ioapic_polarity; |
| 2877 | } else if (acpi_get_override_irq(gsi, &data->trigger, |
| 2878 | &data->polarity) < 0) { |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 2879 | /* PCI interrupts are always active low level triggered. */ |
| 2880 | data->trigger = IOAPIC_LEVEL; |
| 2881 | data->polarity = IOAPIC_POL_LOW; |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2882 | } |
| 2883 | } |
| 2884 | |
| 2885 | static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data, |
| 2886 | struct IO_APIC_route_entry *entry) |
| 2887 | { |
| 2888 | memset(entry, 0, sizeof(*entry)); |
| 2889 | entry->delivery_mode = apic->irq_delivery_mode; |
| 2890 | entry->dest_mode = apic->irq_dest_mode; |
| 2891 | entry->dest = cfg->dest_apicid; |
| 2892 | entry->vector = cfg->vector; |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2893 | entry->trigger = data->trigger; |
| 2894 | entry->polarity = data->polarity; |
| 2895 | /* |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 2896 | * Mask level triggered irqs. Edge triggered irqs are masked |
| 2897 | * by the irq core code in case they fire. |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2898 | */ |
Thomas Gleixner | 335efdf | 2015-04-14 10:30:06 +0800 | [diff] [blame] | 2899 | if (data->trigger == IOAPIC_LEVEL) |
| 2900 | entry->mask = IOAPIC_MASKED; |
| 2901 | else |
| 2902 | entry->mask = IOAPIC_UNMASKED; |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2903 | } |
| 2904 | |
| 2905 | int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, |
| 2906 | unsigned int nr_irqs, void *arg) |
| 2907 | { |
| 2908 | int ret, ioapic, pin; |
| 2909 | struct irq_cfg *cfg; |
| 2910 | struct irq_data *irq_data; |
| 2911 | struct mp_chip_data *data; |
| 2912 | struct irq_alloc_info *info = arg; |
Vitaly Kuznetsov | c0ff971 | 2015-10-15 19:42:23 +0200 | [diff] [blame] | 2913 | unsigned long flags; |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2914 | |
| 2915 | if (!info || nr_irqs > 1) |
| 2916 | return -EINVAL; |
| 2917 | irq_data = irq_domain_get_irq_data(domain, virq); |
| 2918 | if (!irq_data) |
| 2919 | return -EINVAL; |
| 2920 | |
| 2921 | ioapic = mp_irqdomain_ioapic_idx(domain); |
| 2922 | pin = info->ioapic_pin; |
| 2923 | if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0) |
| 2924 | return -EEXIST; |
| 2925 | |
| 2926 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
| 2927 | if (!data) |
| 2928 | return -ENOMEM; |
| 2929 | |
| 2930 | info->ioapic_entry = &data->entry; |
| 2931 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info); |
| 2932 | if (ret < 0) { |
| 2933 | kfree(data); |
| 2934 | return ret; |
| 2935 | } |
| 2936 | |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 2937 | INIT_LIST_HEAD(&data->irq_2_pin); |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2938 | irq_data->hwirq = info->ioapic_pin; |
Jiang Liu | d32932d | 2015-04-13 14:11:59 +0800 | [diff] [blame] | 2939 | irq_data->chip = (domain->parent == x86_vector_domain) ? |
| 2940 | &ioapic_chip : &ioapic_ir_chip; |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2941 | irq_data->chip_data = data; |
| 2942 | mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); |
| 2943 | |
| 2944 | cfg = irqd_cfg(irq_data); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 2945 | add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin); |
Vitaly Kuznetsov | c0ff971 | 2015-10-15 19:42:23 +0200 | [diff] [blame] | 2946 | |
| 2947 | local_irq_save(flags); |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2948 | if (info->ioapic_entry) |
| 2949 | mp_setup_entry(cfg, data, info->ioapic_entry); |
| 2950 | mp_register_handler(virq, data->trigger); |
| 2951 | if (virq < nr_legacy_irqs()) |
| 2952 | legacy_pic->mask(virq); |
Vitaly Kuznetsov | c0ff971 | 2015-10-15 19:42:23 +0200 | [diff] [blame] | 2953 | local_irq_restore(flags); |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2954 | |
| 2955 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
| 2956 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n", |
| 2957 | ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector, |
| 2958 | virq, data->trigger, data->polarity, cfg->dest_apicid); |
| 2959 | |
| 2960 | return 0; |
| 2961 | } |
| 2962 | |
| 2963 | void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq, |
| 2964 | unsigned int nr_irqs) |
| 2965 | { |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2966 | struct irq_data *irq_data; |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 2967 | struct mp_chip_data *data; |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2968 | |
| 2969 | BUG_ON(nr_irqs != 1); |
| 2970 | irq_data = irq_domain_get_irq_data(domain, virq); |
| 2971 | if (irq_data && irq_data->chip_data) { |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 2972 | data = irq_data->chip_data; |
| 2973 | __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2974 | (int)irq_data->hwirq); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 2975 | WARN_ON(!list_empty(&data->irq_2_pin)); |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2976 | kfree(irq_data->chip_data); |
| 2977 | } |
| 2978 | irq_domain_free_irqs_top(domain, virq, nr_irqs); |
| 2979 | } |
| 2980 | |
| 2981 | void mp_irqdomain_activate(struct irq_domain *domain, |
| 2982 | struct irq_data *irq_data) |
| 2983 | { |
| 2984 | unsigned long flags; |
| 2985 | struct irq_pin_list *entry; |
| 2986 | struct mp_chip_data *data = irq_data->chip_data; |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2987 | |
| 2988 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Jiang Liu | 4467715 | 2015-04-14 10:29:53 +0800 | [diff] [blame] | 2989 | for_each_irq_pin(entry, data->irq_2_pin) |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 2990 | __ioapic_write_entry(entry->apic, entry->pin, data->entry); |
| 2991 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2992 | } |
| 2993 | |
| 2994 | void mp_irqdomain_deactivate(struct irq_domain *domain, |
| 2995 | struct irq_data *irq_data) |
| 2996 | { |
| 2997 | /* It won't be called for IRQ with multiple IOAPIC pins associated */ |
| 2998 | ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), |
| 2999 | (int)irq_data->hwirq); |
| 3000 | } |
| 3001 | |
Jiang Liu | 49c7e60 | 2015-04-13 14:11:55 +0800 | [diff] [blame] | 3002 | int mp_irqdomain_ioapic_idx(struct irq_domain *domain) |
| 3003 | { |
| 3004 | return (int)(long)domain->host_data; |
| 3005 | } |
Thomas Gleixner | f7a0c78 | 2015-04-14 10:30:08 +0800 | [diff] [blame] | 3006 | |
| 3007 | const struct irq_domain_ops mp_ioapic_irqdomain_ops = { |
| 3008 | .alloc = mp_irqdomain_alloc, |
| 3009 | .free = mp_irqdomain_free, |
| 3010 | .activate = mp_irqdomain_activate, |
| 3011 | .deactivate = mp_irqdomain_deactivate, |
| 3012 | }; |