Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/omap2/dss/dss.c |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> |
| 6 | * |
| 7 | * Some code and ideas taken from drivers/video/omap/ driver |
| 8 | * by Imre Deak. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License version 2 as published by |
| 12 | * the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 17 | * more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along with |
| 20 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
| 23 | #define DSS_SUBSYS_NAME "DSS" |
| 24 | |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/err.h> |
| 28 | #include <linux/delay.h> |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 29 | #include <linux/seq_file.h> |
| 30 | #include <linux/clk.h> |
Tomi Valkeinen | 24e6289 | 2011-05-23 11:51:18 +0300 | [diff] [blame] | 31 | #include <linux/platform_device.h> |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 32 | #include <linux/pm_runtime.h> |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 33 | |
Tomi Valkeinen | a0b38cc | 2011-05-11 14:05:07 +0300 | [diff] [blame] | 34 | #include <video/omapdss.h> |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 35 | #include <plat/clock.h> |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 36 | #include "dss.h" |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 37 | #include "dss_features.h" |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 38 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 39 | #define DSS_SZ_REGS SZ_512 |
| 40 | |
| 41 | struct dss_reg { |
| 42 | u16 idx; |
| 43 | }; |
| 44 | |
| 45 | #define DSS_REG(idx) ((const struct dss_reg) { idx }) |
| 46 | |
| 47 | #define DSS_REVISION DSS_REG(0x0000) |
| 48 | #define DSS_SYSCONFIG DSS_REG(0x0010) |
| 49 | #define DSS_SYSSTATUS DSS_REG(0x0014) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 50 | #define DSS_CONTROL DSS_REG(0x0040) |
| 51 | #define DSS_SDI_CONTROL DSS_REG(0x0044) |
| 52 | #define DSS_PLL_CONTROL DSS_REG(0x0048) |
| 53 | #define DSS_SDI_STATUS DSS_REG(0x005C) |
| 54 | |
| 55 | #define REG_GET(idx, start, end) \ |
| 56 | FLD_GET(dss_read_reg(idx), start, end) |
| 57 | |
| 58 | #define REG_FLD_MOD(idx, val, start, end) \ |
| 59 | dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) |
| 60 | |
| 61 | static struct { |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 62 | struct platform_device *pdev; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 63 | void __iomem *base; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 64 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 65 | struct clk *dpll4_m4_ck; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 66 | struct clk *dss_clk; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 67 | |
| 68 | unsigned long cache_req_pck; |
| 69 | unsigned long cache_prate; |
| 70 | struct dss_clock_info cache_dss_cinfo; |
| 71 | struct dispc_clock_info cache_dispc_cinfo; |
| 72 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 73 | enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI]; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 74 | enum omap_dss_clk_source dispc_clk_source; |
| 75 | enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 76 | |
Tomi Valkeinen | 69f0605 | 2011-06-01 15:56:39 +0300 | [diff] [blame] | 77 | bool ctx_valid; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 78 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; |
| 79 | } dss; |
| 80 | |
Taneja, Archit | 235e7db | 2011-03-14 23:28:21 -0500 | [diff] [blame] | 81 | static const char * const dss_generic_clk_source_names[] = { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 82 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC", |
| 83 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI", |
| 84 | [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK", |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 85 | }; |
| 86 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 87 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) |
| 88 | { |
| 89 | __raw_writel(val, dss.base + idx.idx); |
| 90 | } |
| 91 | |
| 92 | static inline u32 dss_read_reg(const struct dss_reg idx) |
| 93 | { |
| 94 | return __raw_readl(dss.base + idx.idx); |
| 95 | } |
| 96 | |
| 97 | #define SR(reg) \ |
| 98 | dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) |
| 99 | #define RR(reg) \ |
| 100 | dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) |
| 101 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 102 | static void dss_save_context(void) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 103 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 104 | DSSDBG("dss_save_context\n"); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 105 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 106 | SR(CONTROL); |
| 107 | |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 108 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 109 | OMAP_DISPLAY_TYPE_SDI) { |
| 110 | SR(SDI_CONTROL); |
| 111 | SR(PLL_CONTROL); |
| 112 | } |
Tomi Valkeinen | 69f0605 | 2011-06-01 15:56:39 +0300 | [diff] [blame] | 113 | |
| 114 | dss.ctx_valid = true; |
| 115 | |
| 116 | DSSDBG("context saved\n"); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 117 | } |
| 118 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 119 | static void dss_restore_context(void) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 120 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 121 | DSSDBG("dss_restore_context\n"); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 122 | |
Tomi Valkeinen | 69f0605 | 2011-06-01 15:56:39 +0300 | [diff] [blame] | 123 | if (!dss.ctx_valid) |
| 124 | return; |
| 125 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 126 | RR(CONTROL); |
| 127 | |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 128 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 129 | OMAP_DISPLAY_TYPE_SDI) { |
| 130 | RR(SDI_CONTROL); |
| 131 | RR(PLL_CONTROL); |
| 132 | } |
Tomi Valkeinen | 69f0605 | 2011-06-01 15:56:39 +0300 | [diff] [blame] | 133 | |
| 134 | DSSDBG("context restored\n"); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | #undef SR |
| 138 | #undef RR |
| 139 | |
| 140 | void dss_sdi_init(u8 datapairs) |
| 141 | { |
| 142 | u32 l; |
| 143 | |
| 144 | BUG_ON(datapairs > 3 || datapairs < 1); |
| 145 | |
| 146 | l = dss_read_reg(DSS_SDI_CONTROL); |
| 147 | l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ |
| 148 | l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ |
| 149 | l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ |
| 150 | dss_write_reg(DSS_SDI_CONTROL, l); |
| 151 | |
| 152 | l = dss_read_reg(DSS_PLL_CONTROL); |
| 153 | l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ |
| 154 | l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ |
| 155 | l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ |
| 156 | dss_write_reg(DSS_PLL_CONTROL, l); |
| 157 | } |
| 158 | |
| 159 | int dss_sdi_enable(void) |
| 160 | { |
| 161 | unsigned long timeout; |
| 162 | |
| 163 | dispc_pck_free_enable(1); |
| 164 | |
| 165 | /* Reset SDI PLL */ |
| 166 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ |
| 167 | udelay(1); /* wait 2x PCLK */ |
| 168 | |
| 169 | /* Lock SDI PLL */ |
| 170 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ |
| 171 | |
| 172 | /* Waiting for PLL lock request to complete */ |
| 173 | timeout = jiffies + msecs_to_jiffies(500); |
| 174 | while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { |
| 175 | if (time_after_eq(jiffies, timeout)) { |
| 176 | DSSERR("PLL lock request timed out\n"); |
| 177 | goto err1; |
| 178 | } |
| 179 | } |
| 180 | |
| 181 | /* Clearing PLL_GO bit */ |
| 182 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); |
| 183 | |
| 184 | /* Waiting for PLL to lock */ |
| 185 | timeout = jiffies + msecs_to_jiffies(500); |
| 186 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { |
| 187 | if (time_after_eq(jiffies, timeout)) { |
| 188 | DSSERR("PLL lock timed out\n"); |
| 189 | goto err1; |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | dispc_lcd_enable_signal(1); |
| 194 | |
| 195 | /* Waiting for SDI reset to complete */ |
| 196 | timeout = jiffies + msecs_to_jiffies(500); |
| 197 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { |
| 198 | if (time_after_eq(jiffies, timeout)) { |
| 199 | DSSERR("SDI reset timed out\n"); |
| 200 | goto err2; |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | return 0; |
| 205 | |
| 206 | err2: |
| 207 | dispc_lcd_enable_signal(0); |
| 208 | err1: |
| 209 | /* Reset SDI PLL */ |
| 210 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ |
| 211 | |
| 212 | dispc_pck_free_enable(0); |
| 213 | |
| 214 | return -ETIMEDOUT; |
| 215 | } |
| 216 | |
| 217 | void dss_sdi_disable(void) |
| 218 | { |
| 219 | dispc_lcd_enable_signal(0); |
| 220 | |
| 221 | dispc_pck_free_enable(0); |
| 222 | |
| 223 | /* Reset SDI PLL */ |
| 224 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ |
| 225 | } |
| 226 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 227 | const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src) |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 228 | { |
Taneja, Archit | 235e7db | 2011-03-14 23:28:21 -0500 | [diff] [blame] | 229 | return dss_generic_clk_source_names[clk_src]; |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 230 | } |
| 231 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 232 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 233 | void dss_dump_clocks(struct seq_file *s) |
| 234 | { |
| 235 | unsigned long dpll4_ck_rate; |
| 236 | unsigned long dpll4_m4_ck_rate; |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 237 | const char *fclk_name, *fclk_real_name; |
| 238 | unsigned long fclk_rate; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 239 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 240 | if (dss_runtime_get()) |
| 241 | return; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 242 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 243 | seq_printf(s, "- DSS -\n"); |
| 244 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 245 | fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK); |
| 246 | fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 247 | fclk_rate = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 248 | |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 249 | if (dss.dpll4_m4_ck) { |
| 250 | dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 251 | dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); |
| 252 | |
| 253 | seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); |
| 254 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 255 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 256 | seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", |
| 257 | fclk_name, fclk_real_name, |
| 258 | dpll4_ck_rate, |
| 259 | dpll4_ck_rate / dpll4_m4_ck_rate, |
| 260 | fclk_rate); |
| 261 | else |
| 262 | seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", |
| 263 | fclk_name, fclk_real_name, |
| 264 | dpll4_ck_rate, |
| 265 | dpll4_ck_rate / dpll4_m4_ck_rate, |
| 266 | fclk_rate); |
| 267 | } else { |
| 268 | seq_printf(s, "%s (%s) = %lu\n", |
| 269 | fclk_name, fclk_real_name, |
| 270 | fclk_rate); |
| 271 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 272 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 273 | dss_runtime_put(); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 274 | } |
| 275 | |
| 276 | void dss_dump_regs(struct seq_file *s) |
| 277 | { |
| 278 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) |
| 279 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 280 | if (dss_runtime_get()) |
| 281 | return; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 282 | |
| 283 | DUMPREG(DSS_REVISION); |
| 284 | DUMPREG(DSS_SYSCONFIG); |
| 285 | DUMPREG(DSS_SYSSTATUS); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 286 | DUMPREG(DSS_CONTROL); |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 287 | |
| 288 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 289 | OMAP_DISPLAY_TYPE_SDI) { |
| 290 | DUMPREG(DSS_SDI_CONTROL); |
| 291 | DUMPREG(DSS_PLL_CONTROL); |
| 292 | DUMPREG(DSS_SDI_STATUS); |
| 293 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 294 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 295 | dss_runtime_put(); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 296 | #undef DUMPREG |
| 297 | } |
| 298 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 299 | void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 300 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 301 | struct platform_device *dsidev; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 302 | int b; |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 303 | u8 start, end; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 304 | |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 305 | switch (clk_src) { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 306 | case OMAP_DSS_CLK_SRC_FCK: |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 307 | b = 0; |
| 308 | break; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 309 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 310 | b = 1; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 311 | dsidev = dsi_get_dsidev_from_id(0); |
| 312 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 313 | break; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 314 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
| 315 | b = 2; |
| 316 | dsidev = dsi_get_dsidev_from_id(1); |
| 317 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
| 318 | break; |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 319 | default: |
| 320 | BUG(); |
| 321 | } |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 322 | |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 323 | dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); |
| 324 | |
| 325 | REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 326 | |
| 327 | dss.dispc_clk_source = clk_src; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 328 | } |
| 329 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 330 | void dss_select_dsi_clk_source(int dsi_module, |
| 331 | enum omap_dss_clk_source clk_src) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 332 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 333 | struct platform_device *dsidev; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 334 | int b; |
| 335 | |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 336 | switch (clk_src) { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 337 | case OMAP_DSS_CLK_SRC_FCK: |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 338 | b = 0; |
| 339 | break; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 340 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 341 | BUG_ON(dsi_module != 0); |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 342 | b = 1; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 343 | dsidev = dsi_get_dsidev_from_id(0); |
| 344 | dsi_wait_pll_hsdiv_dsi_active(dsidev); |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 345 | break; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 346 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI: |
| 347 | BUG_ON(dsi_module != 1); |
| 348 | b = 1; |
| 349 | dsidev = dsi_get_dsidev_from_id(1); |
| 350 | dsi_wait_pll_hsdiv_dsi_active(dsidev); |
| 351 | break; |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 352 | default: |
| 353 | BUG(); |
| 354 | } |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 355 | |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 356 | REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ |
| 357 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 358 | dss.dsi_clk_source[dsi_module] = clk_src; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 359 | } |
| 360 | |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 361 | void dss_select_lcd_clk_source(enum omap_channel channel, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 362 | enum omap_dss_clk_source clk_src) |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 363 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 364 | struct platform_device *dsidev; |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 365 | int b, ix, pos; |
| 366 | |
| 367 | if (!dss_has_feature(FEAT_LCD_CLK_SRC)) |
| 368 | return; |
| 369 | |
| 370 | switch (clk_src) { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 371 | case OMAP_DSS_CLK_SRC_FCK: |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 372 | b = 0; |
| 373 | break; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 374 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 375 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); |
| 376 | b = 1; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 377 | dsidev = dsi_get_dsidev_from_id(0); |
| 378 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 379 | break; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 380 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
| 381 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2); |
| 382 | b = 1; |
| 383 | dsidev = dsi_get_dsidev_from_id(1); |
| 384 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
| 385 | break; |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 386 | default: |
| 387 | BUG(); |
| 388 | } |
| 389 | |
| 390 | pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12; |
| 391 | REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ |
| 392 | |
| 393 | ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; |
| 394 | dss.lcd_clk_source[ix] = clk_src; |
| 395 | } |
| 396 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 397 | enum omap_dss_clk_source dss_get_dispc_clk_source(void) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 398 | { |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 399 | return dss.dispc_clk_source; |
| 400 | } |
| 401 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 402 | enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module) |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 403 | { |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 404 | return dss.dsi_clk_source[dsi_module]; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 405 | } |
| 406 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 407 | enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 408 | { |
Archit Taneja | 89976f2 | 2011-03-31 13:23:35 +0530 | [diff] [blame] | 409 | if (dss_has_feature(FEAT_LCD_CLK_SRC)) { |
| 410 | int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; |
| 411 | return dss.lcd_clk_source[ix]; |
| 412 | } else { |
| 413 | /* LCD_CLK source is the same as DISPC_FCLK source for |
| 414 | * OMAP2 and OMAP3 */ |
| 415 | return dss.dispc_clk_source; |
| 416 | } |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 417 | } |
| 418 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 419 | /* calculate clock rates using dividers in cinfo */ |
| 420 | int dss_calc_clock_rates(struct dss_clock_info *cinfo) |
| 421 | { |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 422 | if (dss.dpll4_m4_ck) { |
| 423 | unsigned long prate; |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 424 | u16 fck_div_max = 16; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 425 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 426 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
| 427 | fck_div_max = 32; |
| 428 | |
| 429 | if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0) |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 430 | return -EINVAL; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 431 | |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 432 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 433 | |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 434 | cinfo->fck = prate / cinfo->fck_div; |
| 435 | } else { |
| 436 | if (cinfo->fck_div != 0) |
| 437 | return -EINVAL; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 438 | cinfo->fck = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 439 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 440 | |
| 441 | return 0; |
| 442 | } |
| 443 | |
| 444 | int dss_set_clock_div(struct dss_clock_info *cinfo) |
| 445 | { |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 446 | if (dss.dpll4_m4_ck) { |
| 447 | unsigned long prate; |
| 448 | int r; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 449 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 450 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 451 | DSSDBG("dpll4_m4 = %ld\n", prate); |
| 452 | |
| 453 | r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div); |
| 454 | if (r) |
| 455 | return r; |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 456 | } else { |
| 457 | if (cinfo->fck_div != 0) |
| 458 | return -EINVAL; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 459 | } |
| 460 | |
| 461 | DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); |
| 462 | |
| 463 | return 0; |
| 464 | } |
| 465 | |
| 466 | int dss_get_clock_div(struct dss_clock_info *cinfo) |
| 467 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 468 | cinfo->fck = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 469 | |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 470 | if (dss.dpll4_m4_ck) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 471 | unsigned long prate; |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 472 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 473 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 474 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 475 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
Kishore Y | ac01bb7 | 2010-04-25 16:27:19 +0530 | [diff] [blame] | 476 | cinfo->fck_div = prate / (cinfo->fck); |
| 477 | else |
| 478 | cinfo->fck_div = prate / (cinfo->fck / 2); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 479 | } else { |
| 480 | cinfo->fck_div = 0; |
| 481 | } |
| 482 | |
| 483 | return 0; |
| 484 | } |
| 485 | |
| 486 | unsigned long dss_get_dpll4_rate(void) |
| 487 | { |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 488 | if (dss.dpll4_m4_ck) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 489 | return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 490 | else |
| 491 | return 0; |
| 492 | } |
| 493 | |
| 494 | int dss_calc_clock_div(bool is_tft, unsigned long req_pck, |
| 495 | struct dss_clock_info *dss_cinfo, |
| 496 | struct dispc_clock_info *dispc_cinfo) |
| 497 | { |
| 498 | unsigned long prate; |
| 499 | struct dss_clock_info best_dss; |
| 500 | struct dispc_clock_info best_dispc; |
| 501 | |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 502 | unsigned long fck, max_dss_fck; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 503 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 504 | u16 fck_div, fck_div_max = 16; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 505 | |
| 506 | int match = 0; |
| 507 | int min_fck_per_pck; |
| 508 | |
| 509 | prate = dss_get_dpll4_rate(); |
| 510 | |
Taneja, Archit | 31ef823 | 2011-03-14 23:28:22 -0500 | [diff] [blame] | 511 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 512 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 513 | fck = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 514 | if (req_pck == dss.cache_req_pck && |
| 515 | ((cpu_is_omap34xx() && prate == dss.cache_prate) || |
| 516 | dss.cache_dss_cinfo.fck == fck)) { |
| 517 | DSSDBG("dispc clock info found from cache.\n"); |
| 518 | *dss_cinfo = dss.cache_dss_cinfo; |
| 519 | *dispc_cinfo = dss.cache_dispc_cinfo; |
| 520 | return 0; |
| 521 | } |
| 522 | |
| 523 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; |
| 524 | |
| 525 | if (min_fck_per_pck && |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 526 | req_pck * min_fck_per_pck > max_dss_fck) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 527 | DSSERR("Requested pixel clock not possible with the current " |
| 528 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " |
| 529 | "the constraint off.\n"); |
| 530 | min_fck_per_pck = 0; |
| 531 | } |
| 532 | |
| 533 | retry: |
| 534 | memset(&best_dss, 0, sizeof(best_dss)); |
| 535 | memset(&best_dispc, 0, sizeof(best_dispc)); |
| 536 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 537 | if (dss.dpll4_m4_ck == NULL) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 538 | struct dispc_clock_info cur_dispc; |
| 539 | /* XXX can we change the clock on omap2? */ |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 540 | fck = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 541 | fck_div = 1; |
| 542 | |
| 543 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); |
| 544 | match = 1; |
| 545 | |
| 546 | best_dss.fck = fck; |
| 547 | best_dss.fck_div = fck_div; |
| 548 | |
| 549 | best_dispc = cur_dispc; |
| 550 | |
| 551 | goto found; |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 552 | } else { |
| 553 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
| 554 | fck_div_max = 32; |
| 555 | |
| 556 | for (fck_div = fck_div_max; fck_div > 0; --fck_div) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 557 | struct dispc_clock_info cur_dispc; |
| 558 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 559 | if (fck_div_max == 32) |
Kishore Y | ac01bb7 | 2010-04-25 16:27:19 +0530 | [diff] [blame] | 560 | fck = prate / fck_div; |
| 561 | else |
| 562 | fck = prate / fck_div * 2; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 563 | |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 564 | if (fck > max_dss_fck) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 565 | continue; |
| 566 | |
| 567 | if (min_fck_per_pck && |
| 568 | fck < req_pck * min_fck_per_pck) |
| 569 | continue; |
| 570 | |
| 571 | match = 1; |
| 572 | |
| 573 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); |
| 574 | |
| 575 | if (abs(cur_dispc.pck - req_pck) < |
| 576 | abs(best_dispc.pck - req_pck)) { |
| 577 | |
| 578 | best_dss.fck = fck; |
| 579 | best_dss.fck_div = fck_div; |
| 580 | |
| 581 | best_dispc = cur_dispc; |
| 582 | |
| 583 | if (cur_dispc.pck == req_pck) |
| 584 | goto found; |
| 585 | } |
| 586 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | found: |
| 590 | if (!match) { |
| 591 | if (min_fck_per_pck) { |
| 592 | DSSERR("Could not find suitable clock settings.\n" |
| 593 | "Turning FCK/PCK constraint off and" |
| 594 | "trying again.\n"); |
| 595 | min_fck_per_pck = 0; |
| 596 | goto retry; |
| 597 | } |
| 598 | |
| 599 | DSSERR("Could not find suitable clock settings.\n"); |
| 600 | |
| 601 | return -EINVAL; |
| 602 | } |
| 603 | |
| 604 | if (dss_cinfo) |
| 605 | *dss_cinfo = best_dss; |
| 606 | if (dispc_cinfo) |
| 607 | *dispc_cinfo = best_dispc; |
| 608 | |
| 609 | dss.cache_req_pck = req_pck; |
| 610 | dss.cache_prate = prate; |
| 611 | dss.cache_dss_cinfo = best_dss; |
| 612 | dss.cache_dispc_cinfo = best_dispc; |
| 613 | |
| 614 | return 0; |
| 615 | } |
| 616 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 617 | void dss_set_venc_output(enum omap_dss_venc_type type) |
| 618 | { |
| 619 | int l = 0; |
| 620 | |
| 621 | if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) |
| 622 | l = 0; |
| 623 | else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) |
| 624 | l = 1; |
| 625 | else |
| 626 | BUG(); |
| 627 | |
| 628 | /* venc out selection. 0 = comp, 1 = svideo */ |
| 629 | REG_FLD_MOD(DSS_CONTROL, l, 6, 6); |
| 630 | } |
| 631 | |
| 632 | void dss_set_dac_pwrdn_bgz(bool enable) |
| 633 | { |
| 634 | REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ |
| 635 | } |
| 636 | |
Mythri P K | 7ed024a | 2011-03-09 16:31:38 +0530 | [diff] [blame] | 637 | void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi) |
| 638 | { |
| 639 | REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */ |
| 640 | } |
| 641 | |
Tomi Valkeinen | 4a61e26 | 2011-08-31 14:33:31 +0300 | [diff] [blame^] | 642 | enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void) |
| 643 | { |
| 644 | enum omap_display_type displays; |
| 645 | |
| 646 | displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); |
| 647 | if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0) |
| 648 | return DSS_VENC_TV_CLK; |
| 649 | |
| 650 | return REG_GET(DSS_CONTROL, 15, 15); |
| 651 | } |
| 652 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 653 | static int dss_get_clocks(void) |
| 654 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 655 | struct clk *clk; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 656 | int r; |
| 657 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 658 | clk = clk_get(&dss.pdev->dev, "fck"); |
| 659 | if (IS_ERR(clk)) { |
| 660 | DSSERR("can't get clock fck\n"); |
| 661 | r = PTR_ERR(clk); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 662 | goto err; |
Semwal, Sumit | a1a0dcc | 2011-03-01 02:42:14 -0600 | [diff] [blame] | 663 | } |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 664 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 665 | dss.dss_clk = clk; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 666 | |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 667 | if (cpu_is_omap34xx()) { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 668 | clk = clk_get(NULL, "dpll4_m4_ck"); |
| 669 | if (IS_ERR(clk)) { |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 670 | DSSERR("Failed to get dpll4_m4_ck\n"); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 671 | r = PTR_ERR(clk); |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 672 | goto err; |
| 673 | } |
| 674 | } else if (cpu_is_omap44xx()) { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 675 | clk = clk_get(NULL, "dpll_per_m5x2_ck"); |
| 676 | if (IS_ERR(clk)) { |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 677 | DSSERR("Failed to get dpll_per_m5x2_ck\n"); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 678 | r = PTR_ERR(clk); |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 679 | goto err; |
| 680 | } |
| 681 | } else { /* omap24xx */ |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 682 | clk = NULL; |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 683 | } |
| 684 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 685 | dss.dpll4_m4_ck = clk; |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 686 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 687 | return 0; |
| 688 | |
| 689 | err: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 690 | if (dss.dss_clk) |
| 691 | clk_put(dss.dss_clk); |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 692 | if (dss.dpll4_m4_ck) |
| 693 | clk_put(dss.dpll4_m4_ck); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 694 | |
| 695 | return r; |
| 696 | } |
| 697 | |
| 698 | static void dss_put_clocks(void) |
| 699 | { |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 700 | if (dss.dpll4_m4_ck) |
| 701 | clk_put(dss.dpll4_m4_ck); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 702 | clk_put(dss.dss_clk); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 703 | } |
| 704 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 705 | int dss_runtime_get(void) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 706 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 707 | int r; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 708 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 709 | DSSDBG("dss_runtime_get\n"); |
| 710 | |
| 711 | r = pm_runtime_get_sync(&dss.pdev->dev); |
| 712 | WARN_ON(r < 0); |
| 713 | return r < 0 ? r : 0; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 714 | } |
| 715 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 716 | void dss_runtime_put(void) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 717 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 718 | int r; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 719 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 720 | DSSDBG("dss_runtime_put\n"); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 721 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 722 | r = pm_runtime_put(&dss.pdev->dev); |
| 723 | WARN_ON(r < 0); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 724 | } |
| 725 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 726 | /* DEBUGFS */ |
| 727 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) |
| 728 | void dss_debug_dump_clocks(struct seq_file *s) |
| 729 | { |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 730 | dss_dump_clocks(s); |
| 731 | dispc_dump_clocks(s); |
| 732 | #ifdef CONFIG_OMAP2_DSS_DSI |
| 733 | dsi_dump_clocks(s); |
| 734 | #endif |
| 735 | } |
| 736 | #endif |
| 737 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 738 | /* DSS HW IP initialisation */ |
| 739 | static int omap_dsshw_probe(struct platform_device *pdev) |
| 740 | { |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 741 | struct resource *dss_mem; |
| 742 | u32 rev; |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 743 | int r; |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 744 | |
| 745 | dss.pdev = pdev; |
| 746 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 747 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); |
| 748 | if (!dss_mem) { |
| 749 | DSSERR("can't get IORESOURCE_MEM DSS\n"); |
| 750 | r = -EINVAL; |
| 751 | goto err_ioremap; |
| 752 | } |
| 753 | dss.base = ioremap(dss_mem->start, resource_size(dss_mem)); |
| 754 | if (!dss.base) { |
| 755 | DSSERR("can't ioremap DSS\n"); |
| 756 | r = -ENOMEM; |
| 757 | goto err_ioremap; |
| 758 | } |
| 759 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 760 | r = dss_get_clocks(); |
| 761 | if (r) |
| 762 | goto err_clocks; |
| 763 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 764 | pm_runtime_enable(&pdev->dev); |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 765 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 766 | r = dss_runtime_get(); |
| 767 | if (r) |
| 768 | goto err_runtime_get; |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 769 | |
| 770 | /* Select DPLL */ |
| 771 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); |
| 772 | |
| 773 | #ifdef CONFIG_OMAP2_DSS_VENC |
| 774 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ |
| 775 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ |
| 776 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ |
| 777 | #endif |
| 778 | dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; |
| 779 | dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; |
| 780 | dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; |
| 781 | dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; |
| 782 | dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 783 | |
Tomi Valkeinen | 587b5e8 | 2011-03-02 12:47:54 +0200 | [diff] [blame] | 784 | r = dpi_init(); |
| 785 | if (r) { |
| 786 | DSSERR("Failed to initialize DPI\n"); |
| 787 | goto err_dpi; |
| 788 | } |
| 789 | |
| 790 | r = sdi_init(); |
| 791 | if (r) { |
| 792 | DSSERR("Failed to initialize SDI\n"); |
| 793 | goto err_sdi; |
| 794 | } |
| 795 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 796 | rev = dss_read_reg(DSS_REVISION); |
| 797 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", |
| 798 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
| 799 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 800 | dss_runtime_put(); |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 801 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 802 | return 0; |
Tomi Valkeinen | 587b5e8 | 2011-03-02 12:47:54 +0200 | [diff] [blame] | 803 | err_sdi: |
| 804 | dpi_exit(); |
| 805 | err_dpi: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 806 | dss_runtime_put(); |
| 807 | err_runtime_get: |
| 808 | pm_runtime_disable(&pdev->dev); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 809 | dss_put_clocks(); |
| 810 | err_clocks: |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 811 | iounmap(dss.base); |
| 812 | err_ioremap: |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 813 | return r; |
| 814 | } |
| 815 | |
| 816 | static int omap_dsshw_remove(struct platform_device *pdev) |
| 817 | { |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 818 | dpi_exit(); |
| 819 | sdi_exit(); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 820 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 821 | iounmap(dss.base); |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 822 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 823 | pm_runtime_disable(&pdev->dev); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 824 | |
| 825 | dss_put_clocks(); |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 826 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 827 | return 0; |
| 828 | } |
| 829 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 830 | static int dss_runtime_suspend(struct device *dev) |
| 831 | { |
| 832 | dss_save_context(); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 833 | return 0; |
| 834 | } |
| 835 | |
| 836 | static int dss_runtime_resume(struct device *dev) |
| 837 | { |
Tomi Valkeinen | 3902071 | 2011-05-26 14:54:05 +0300 | [diff] [blame] | 838 | dss_restore_context(); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 839 | return 0; |
| 840 | } |
| 841 | |
| 842 | static const struct dev_pm_ops dss_pm_ops = { |
| 843 | .runtime_suspend = dss_runtime_suspend, |
| 844 | .runtime_resume = dss_runtime_resume, |
| 845 | }; |
| 846 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 847 | static struct platform_driver omap_dsshw_driver = { |
| 848 | .probe = omap_dsshw_probe, |
| 849 | .remove = omap_dsshw_remove, |
| 850 | .driver = { |
| 851 | .name = "omapdss_dss", |
| 852 | .owner = THIS_MODULE, |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 853 | .pm = &dss_pm_ops, |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 854 | }, |
| 855 | }; |
| 856 | |
| 857 | int dss_init_platform_driver(void) |
| 858 | { |
| 859 | return platform_driver_register(&omap_dsshw_driver); |
| 860 | } |
| 861 | |
| 862 | void dss_uninit_platform_driver(void) |
| 863 | { |
| 864 | return platform_driver_unregister(&omap_dsshw_driver); |
| 865 | } |