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gerrit-public.fairphone.software / kernel / msm-4.9 / 553c0a200e2082686fd9b829b77f7df6ebae14e9 / . / arch / arm / boot / dts / tegra30-cardhu.dtsi
blob: dfcc18adcfd7cff94bcee8deec244804a1e63787 [file] [log] [blame]
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]1#include "tegra30.dtsi"
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]2
Laxman Dewangan640a7af2012-08-09 16:30:38 +0530[diff] [blame]3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame^]30 aliases {
31 rtc0 = "/i2c@7000d000/tps6586x@34";
32 rtc1 = "/rtc@7000e000";
33 };
34
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]35 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]36 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]37 };
38
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]39 pcie-controller@00003000 {
Jay Agarwal89e7ada2013-08-09 16:49:27 +0200[diff] [blame]40 status = "okay";
41 pex-clk-supply = <&pex_hvdd_3v3_reg>;
42 vdd-supply = <&ldo1_reg>;
43 avdd-supply = <&ldo2_reg>;
44
45 pci@1,0 {
46 nvidia,num-lanes = <4>;
47 };
48
49 pci@2,0 {
50 nvidia,num-lanes = <1>;
51 };
52
53 pci@3,0 {
54 status = "okay";
55 nvidia,num-lanes = <1>;
56 };
57 };
58
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]59 pinmux@70000868 {
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]60 pinctrl-names = "default";
61 pinctrl-0 = <&state_default>;
62
63 state_default: pinmux {
64 sdmmc1_clk_pz0 {
65 nvidia,pins = "sdmmc1_clk_pz0";
66 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]67 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
68 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]69 };
70 sdmmc1_cmd_pz1 {
71 nvidia,pins = "sdmmc1_cmd_pz1",
72 "sdmmc1_dat0_py7",
73 "sdmmc1_dat1_py6",
74 "sdmmc1_dat2_py5",
75 "sdmmc1_dat3_py4";
76 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]77 nvidia,pull = <TEGRA_PIN_PULL_UP>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]79 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]80 sdmmc3_clk_pa6 {
81 nvidia,pins = "sdmmc3_clk_pa6";
82 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]85 };
86 sdmmc3_cmd_pa7 {
87 nvidia,pins = "sdmmc3_cmd_pa7",
88 "sdmmc3_dat0_pb7",
89 "sdmmc3_dat1_pb6",
90 "sdmmc3_dat2_pb5",
91 "sdmmc3_dat3_pb4";
92 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]93 nvidia,pull = <TEGRA_PIN_PULL_UP>;
94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]95 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]96 sdmmc4_clk_pcc4 {
97 nvidia,pins = "sdmmc4_clk_pcc4",
98 "sdmmc4_rst_n_pcc3";
99 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]102 };
103 sdmmc4_dat0_paa0 {
104 nvidia,pins = "sdmmc4_dat0_paa0",
105 "sdmmc4_dat1_paa1",
106 "sdmmc4_dat2_paa2",
107 "sdmmc4_dat3_paa3",
108 "sdmmc4_dat4_paa4",
109 "sdmmc4_dat5_paa5",
110 "sdmmc4_dat6_paa6",
111 "sdmmc4_dat7_paa7";
112 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]113 nvidia,pull = <TEGRA_PIN_PULL_UP>;
114 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]115 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]116 dap2_fs_pa2 {
117 nvidia,pins = "dap2_fs_pa2",
118 "dap2_sclk_pa3",
119 "dap2_din_pa4",
120 "dap2_dout_pa5";
121 nvidia,function = "i2s1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]122 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
123 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]124 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]125 sdio3 {
126 nvidia,pins = "drive_sdio3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]127 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
128 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]129 nvidia,pull-down-strength = <46>;
130 nvidia,pull-up-strength = <42>;
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]131 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
132 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]133 };
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]134 uart3_txd_pw6 {
135 nvidia,pins = "uart3_txd_pw6",
136 "uart3_cts_n_pa1",
137 "uart3_rts_n_pc0",
138 "uart3_rxd_pw7";
139 nvidia,function = "uartc";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]142 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]143 };
144 };
145
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]146 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]147 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]148 };
149
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]150 serial@70006200 {
151 compatible = "nvidia,tegra30-hsuart";
152 status = "okay";
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]153 };
154
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]155 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]156 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]157 clock-frequency = <100000>;
158 };
159
160 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]161 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]162 clock-frequency = <100000>;
163 };
164
165 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]166 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]167 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]168
169 /* ALS and Proximity sensor */
170 isl29028@44 {
171 compatible = "isil,isl29028";
172 reg = <0x44>;
173 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]174 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]175 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]176 };
177
178 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]179 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]180 clock-frequency = <100000>;
181 };
182
183 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]184 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]185 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]186
187 wm8903: wm8903@1a {
188 compatible = "wlf,wm8903";
189 reg = <0x1a>;
190 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]191 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]192
193 gpio-controller;
194 #gpio-cells = <2>;
195
196 micdet-cfg = <0>;
197 micdet-delay = <100>;
198 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
199 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]200
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]201 pmic: tps65911@2d {
202 compatible = "ti,tps65911";
203 reg = <0x2d>;
204
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]205 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]206 #interrupt-cells = <2>;
207 interrupt-controller;
208
Stephen Warren44b12ef2012-09-11 11:42:26 -0600[diff] [blame]209 ti,system-power-controller;
210
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]211 #gpio-cells = <2>;
212 gpio-controller;
213
214 vcc1-supply = <&vdd_ac_bat_reg>;
215 vcc2-supply = <&vdd_ac_bat_reg>;
216 vcc3-supply = <&vio_reg>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]217 vcc4-supply = <&vdd_5v0_reg>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]218 vcc5-supply = <&vdd_ac_bat_reg>;
219 vcc6-supply = <&vdd2_reg>;
220 vcc7-supply = <&vdd_ac_bat_reg>;
221 vccio-supply = <&vdd_ac_bat_reg>;
222
223 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]224 vdd1_reg: vdd1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]225 regulator-name = "vddio_ddr_1v2";
226 regulator-min-microvolt = <1200000>;
227 regulator-max-microvolt = <1200000>;
228 regulator-always-on;
229 };
230
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]231 vdd2_reg: vdd2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]232 regulator-name = "vdd_1v5_gen";
233 regulator-min-microvolt = <1500000>;
234 regulator-max-microvolt = <1500000>;
235 regulator-always-on;
236 };
237
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]238 vddctrl_reg: vddctrl {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]239 regulator-name = "vdd_cpu,vdd_sys";
240 regulator-min-microvolt = <1000000>;
241 regulator-max-microvolt = <1000000>;
242 regulator-always-on;
243 };
244
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]245 vio_reg: vio {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]246 regulator-name = "vdd_1v8_gen";
247 regulator-min-microvolt = <1800000>;
248 regulator-max-microvolt = <1800000>;
249 regulator-always-on;
250 };
251
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]252 ldo1_reg: ldo1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]253 regulator-name = "vdd_pexa,vdd_pexb";
254 regulator-min-microvolt = <1050000>;
255 regulator-max-microvolt = <1050000>;
256 };
257
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]258 ldo2_reg: ldo2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]259 regulator-name = "vdd_sata,avdd_plle";
260 regulator-min-microvolt = <1050000>;
261 regulator-max-microvolt = <1050000>;
262 };
263
264 /* LDO3 is not connected to anything */
265
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]266 ldo4_reg: ldo4 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]267 regulator-name = "vdd_rtc";
268 regulator-min-microvolt = <1200000>;
269 regulator-max-microvolt = <1200000>;
270 regulator-always-on;
271 };
272
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]273 ldo5_reg: ldo5 {
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]274 regulator-name = "vddio_sdmmc,avdd_vdac";
275 regulator-min-microvolt = <3300000>;
276 regulator-max-microvolt = <3300000>;
277 regulator-always-on;
278 };
279
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]280 ldo6_reg: ldo6 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]281 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
282 regulator-min-microvolt = <1200000>;
283 regulator-max-microvolt = <1200000>;
284 };
285
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]286 ldo7_reg: ldo7 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]287 regulator-name = "vdd_pllm,x,u,a_p_c_s";
288 regulator-min-microvolt = <1200000>;
289 regulator-max-microvolt = <1200000>;
290 regulator-always-on;
291 };
292
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]293 ldo8_reg: ldo8 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]294 regulator-name = "vdd_ddr_hs";
295 regulator-min-microvolt = <1000000>;
296 regulator-max-microvolt = <1000000>;
297 regulator-always-on;
298 };
299 };
300 };
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]301
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]302 temperature-sensor@4c {
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]303 compatible = "onnn,nct1008";
304 reg = <0x4c>;
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]305 vcc-supply = <&sys_3v3_reg>;
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]306 interrupt-parent = <&gpio>;
307 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
308 };
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]309
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]310 tps62361@60 {
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]311 compatible = "ti,tps62361";
312 reg = <0x60>;
313
314 regulator-name = "tps62361-vout";
315 regulator-min-microvolt = <500000>;
316 regulator-max-microvolt = <1500000>;
317 regulator-boot-on;
318 regulator-always-on;
319 ti,vsel0-state-high;
320 ti,vsel1-state-high;
321 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]322 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]323
Laxman Dewanganc42cb1c2012-10-31 14:32:54 +0530[diff] [blame]324 spi@7000da00 {
325 status = "okay";
326 spi-max-frequency = <25000000>;
327 spi-flash@1 {
328 compatible = "winbond,w25q32";
329 reg = <1>;
330 spi-max-frequency = <20000000>;
331 };
332 };
333
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]334 pmc@7000e400 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]335 status = "okay";
336 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800[diff] [blame]337 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800[diff] [blame]338 nvidia,cpu-pwr-good-time = <2000>;
339 nvidia,cpu-pwr-off-time = <200>;
340 nvidia,core-pwr-good-time = <3845 3845>;
341 nvidia,core-pwr-off-time = <0>;
342 nvidia,core-power-req-active-high;
343 nvidia,sys-clock-req-active-high;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]344 };
345
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]346 ahub@70080000 {
347 i2s@70080400 {
348 status = "okay";
349 };
350 };
351
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]352 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]353 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]354 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
355 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
356 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]357 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]358 };
359
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]360 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]361 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]362 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600[diff] [blame]363 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]364 };
365
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300[diff] [blame]366 usb@7d008000 {
367 status = "okay";
368 };
369
370 usb-phy@7d008000 {
371 vbus-supply = <&usb3_vbus_reg>;
372 status = "okay";
373 };
374
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]375 clocks {
376 compatible = "simple-bus";
377 #address-cells = <1>;
378 #size-cells = <0>;
379
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]380 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]381 compatible = "fixed-clock";
382 reg=<0>;
383 #clock-cells = <0>;
384 clock-frequency = <32768>;
385 };
386 };
387
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]388 regulators {
389 compatible = "simple-bus";
390 #address-cells = <1>;
391 #size-cells = <0>;
392
393 vdd_ac_bat_reg: regulator@0 {
394 compatible = "regulator-fixed";
395 reg = <0>;
396 regulator-name = "vdd_ac_bat";
397 regulator-min-microvolt = <5000000>;
398 regulator-max-microvolt = <5000000>;
399 regulator-always-on;
400 };
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]401
402 cam_1v8_reg: regulator@1 {
403 compatible = "regulator-fixed";
404 reg = <1>;
405 regulator-name = "cam_1v8";
406 regulator-min-microvolt = <1800000>;
407 regulator-max-microvolt = <1800000>;
408 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]409 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]410 vin-supply = <&vio_reg>;
411 };
412
413 cp_5v_reg: regulator@2 {
414 compatible = "regulator-fixed";
415 reg = <2>;
416 regulator-name = "cp_5v";
417 regulator-min-microvolt = <5000000>;
418 regulator-max-microvolt = <5000000>;
419 regulator-boot-on;
420 regulator-always-on;
421 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]422 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]423 };
424
425 emmc_3v3_reg: regulator@3 {
426 compatible = "regulator-fixed";
427 reg = <3>;
428 regulator-name = "emmc_3v3";
429 regulator-min-microvolt = <3300000>;
430 regulator-max-microvolt = <3300000>;
431 regulator-always-on;
432 regulator-boot-on;
433 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]434 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]435 vin-supply = <&sys_3v3_reg>;
436 };
437
438 modem_3v3_reg: regulator@4 {
439 compatible = "regulator-fixed";
440 reg = <4>;
441 regulator-name = "modem_3v3";
442 regulator-min-microvolt = <3300000>;
443 regulator-max-microvolt = <3300000>;
444 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]445 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]446 };
447
448 pex_hvdd_3v3_reg: regulator@5 {
449 compatible = "regulator-fixed";
450 reg = <5>;
451 regulator-name = "pex_hvdd_3v3";
452 regulator-min-microvolt = <3300000>;
453 regulator-max-microvolt = <3300000>;
454 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]455 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]456 vin-supply = <&sys_3v3_reg>;
457 };
458
459 vdd_cam1_ldo_reg: regulator@6 {
460 compatible = "regulator-fixed";
461 reg = <6>;
462 regulator-name = "vdd_cam1_ldo";
463 regulator-min-microvolt = <2800000>;
464 regulator-max-microvolt = <2800000>;
465 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]466 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]467 vin-supply = <&sys_3v3_reg>;
468 };
469
470 vdd_cam2_ldo_reg: regulator@7 {
471 compatible = "regulator-fixed";
472 reg = <7>;
473 regulator-name = "vdd_cam2_ldo";
474 regulator-min-microvolt = <2800000>;
475 regulator-max-microvolt = <2800000>;
476 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]477 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]478 vin-supply = <&sys_3v3_reg>;
479 };
480
481 vdd_cam3_ldo_reg: regulator@8 {
482 compatible = "regulator-fixed";
483 reg = <8>;
484 regulator-name = "vdd_cam3_ldo";
485 regulator-min-microvolt = <3300000>;
486 regulator-max-microvolt = <3300000>;
487 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]488 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]489 vin-supply = <&sys_3v3_reg>;
490 };
491
492 vdd_com_reg: regulator@9 {
493 compatible = "regulator-fixed";
494 reg = <9>;
495 regulator-name = "vdd_com";
496 regulator-min-microvolt = <3300000>;
497 regulator-max-microvolt = <3300000>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]498 regulator-always-on;
499 regulator-boot-on;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]500 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]501 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]502 vin-supply = <&sys_3v3_reg>;
503 };
504
505 vdd_fuse_3v3_reg: regulator@10 {
506 compatible = "regulator-fixed";
507 reg = <10>;
508 regulator-name = "vdd_fuse_3v3";
509 regulator-min-microvolt = <3300000>;
510 regulator-max-microvolt = <3300000>;
511 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]512 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]513 vin-supply = <&sys_3v3_reg>;
514 };
515
516 vdd_pnl1_reg: regulator@11 {
517 compatible = "regulator-fixed";
518 reg = <11>;
519 regulator-name = "vdd_pnl1";
520 regulator-min-microvolt = <3300000>;
521 regulator-max-microvolt = <3300000>;
522 regulator-always-on;
523 regulator-boot-on;
524 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]525 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]526 vin-supply = <&sys_3v3_reg>;
527 };
528
529 vdd_vid_reg: regulator@12 {
530 compatible = "regulator-fixed";
531 reg = <12>;
532 regulator-name = "vddio_vid";
533 regulator-min-microvolt = <5000000>;
534 regulator-max-microvolt = <5000000>;
535 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]536 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]537 gpio-open-drain;
538 vin-supply = <&vdd_5v0_reg>;
539 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]540 };
541
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]542 sound {
543 compatible = "nvidia,tegra-audio-wm8903-cardhu",
544 "nvidia,tegra-audio-wm8903";
545 nvidia,model = "NVIDIA Tegra Cardhu";
546
547 nvidia,audio-routing =
548 "Headphone Jack", "HPOUTR",
549 "Headphone Jack", "HPOUTL",
550 "Int Spk", "ROP",
551 "Int Spk", "RON",
552 "Int Spk", "LOP",
553 "Int Spk", "LON",
554 "Mic Jack", "MICBIAS",
555 "IN1L", "Mic Jack";
556
557 nvidia,i2s-controller = <&tegra_i2s1>;
558 nvidia,audio-codec = <&wm8903>;
559
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]560 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
561 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
562 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]563
Hiroshi Doyu05849c92013-05-22 19:45:34 +0300[diff] [blame]564 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
565 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
566 <&tegra_car TEGRA30_CLK_EXTERN1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]567 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]568 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]569};