blob: 04e74f4857146e4700669504de55a6ad632823a0 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080012#include <linux/pci-aspm.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090013#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070014
15#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16#define CARDBUS_RESERVE_BUSNR 3
Linus Torvalds1da177e2005-04-16 15:20:36 -070017
18/* Ugh. Need to stop exporting this to modules. */
19LIST_HEAD(pci_root_buses);
20EXPORT_SYMBOL(pci_root_buses);
21
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080022
23static int find_anything(struct device *dev, void *data)
24{
25 return 1;
26}
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070028/*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080031 * is no device to be found on the pci_bus_type.
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070032 */
33int no_pci_devices(void)
34{
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080035 struct device *dev;
36 int no_devices;
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070037
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080038 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42}
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070043EXPORT_SYMBOL(no_pci_devices);
44
Linus Torvalds1da177e2005-04-16 15:20:36 -070045/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070046 * PCI Bus Class
47 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040048static void release_pcibus_dev(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070049{
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040050 struct pci_bus *pci_bus = to_pci_bus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
52 if (pci_bus->bridge)
53 put_device(pci_bus->bridge);
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -070054 pci_bus_remove_resources(pci_bus);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +100055 pci_release_bus_of_node(pci_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 kfree(pci_bus);
57}
58
59static struct class pcibus_class = {
60 .name = "pci_bus",
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040061 .dev_release = &release_pcibus_dev,
Yinghai Lub9d320f2011-05-12 17:11:39 -070062 .dev_attrs = pcibus_dev_attrs,
Linus Torvalds1da177e2005-04-16 15:20:36 -070063};
64
65static int __init pcibus_class_init(void)
66{
67 return class_register(&pcibus_class);
68}
69postcore_initcall(pcibus_class_init);
70
Matthew Wilcox6ac665c2008-07-28 13:38:59 -040071static u64 pci_size(u64 base, u64 maxbase, u64 mask)
Yinghai Lu07eddf32006-11-29 13:53:10 -080072{
73 u64 size = mask & maxbase; /* Find the significant bits */
74 if (!size)
75 return 0;
76
77 /* Get the lowest of them to find the decode size, and
78 from that the extent. */
79 size = (size & ~(size-1)) - 1;
80
81 /* base == maxbase can be valid only if the BAR has
82 already been programmed with all 1s. */
83 if (base == maxbase && ((base | size) & mask) != mask)
84 return 0;
85
86 return size;
87}
88
Bjorn Helgaas28c68212011-06-14 13:04:35 -060089static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
Yinghai Lu07eddf32006-11-29 13:53:10 -080090{
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -060091 u32 mem_type;
Bjorn Helgaas28c68212011-06-14 13:04:35 -060092 unsigned long flags;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -060093
Matthew Wilcox6ac665c2008-07-28 13:38:59 -040094 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -060095 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
96 flags |= IORESOURCE_IO;
97 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -040098 }
99
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600100 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
101 flags |= IORESOURCE_MEM;
102 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
103 flags |= IORESOURCE_PREFETCH;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400104
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600105 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
106 switch (mem_type) {
107 case PCI_BASE_ADDRESS_MEM_TYPE_32:
108 break;
109 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
110 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
111 break;
112 case PCI_BASE_ADDRESS_MEM_TYPE_64:
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600113 flags |= IORESOURCE_MEM_64;
114 break;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600115 default:
116 dev_warn(&dev->dev,
117 "mem unknown type %x treated as 32-bit BAR\n",
118 mem_type);
119 break;
120 }
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600121 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400122}
123
Yu Zhao0b400c72008-11-22 02:40:40 +0800124/**
125 * pci_read_base - read a PCI BAR
126 * @dev: the PCI device
127 * @type: type of the BAR
128 * @res: resource buffer to be filled in
129 * @pos: BAR position in the config space
130 *
131 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400132 */
Yu Zhao0b400c72008-11-22 02:40:40 +0800133int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400134 struct resource *res, unsigned int pos)
135{
136 u32 l, sz, mask;
Jacob Pan253d2e52010-07-16 10:19:22 -0700137 u16 orig_cmd;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400138
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200139 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400140
Jacob Pan253d2e52010-07-16 10:19:22 -0700141 if (!dev->mmio_always_on) {
142 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
143 pci_write_config_word(dev, PCI_COMMAND,
144 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
145 }
146
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400147 res->name = pci_name(dev);
148
149 pci_read_config_dword(dev, pos, &l);
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200150 pci_write_config_dword(dev, pos, l | mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400151 pci_read_config_dword(dev, pos, &sz);
152 pci_write_config_dword(dev, pos, l);
153
Jacob Pan253d2e52010-07-16 10:19:22 -0700154 if (!dev->mmio_always_on)
155 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
156
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400157 /*
158 * All bits set in sz means the device isn't working properly.
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600159 * If the BAR isn't implemented, all bits must be 0. If it's a
160 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
161 * 1 must be clear.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400162 */
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600163 if (!sz || sz == 0xffffffff)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400164 goto fail;
165
166 /*
167 * I don't know how l can have all bits set. Copied from old code.
168 * Maybe it fixes a bug on some ancient platform.
169 */
170 if (l == 0xffffffff)
171 l = 0;
172
173 if (type == pci_bar_unknown) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600174 res->flags = decode_bar(dev, l);
175 res->flags |= IORESOURCE_SIZEALIGN;
176 if (res->flags & IORESOURCE_IO) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400177 l &= PCI_BASE_ADDRESS_IO_MASK;
David S. Miller5aceca92011-05-23 17:12:22 -0700178 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400179 } else {
180 l &= PCI_BASE_ADDRESS_MEM_MASK;
181 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
182 }
183 } else {
184 res->flags |= (l & IORESOURCE_ROM_ENABLE);
185 l &= PCI_ROM_ADDRESS_MASK;
186 mask = (u32)PCI_ROM_ADDRESS_MASK;
187 }
188
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600189 if (res->flags & IORESOURCE_MEM_64) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400190 u64 l64 = l;
191 u64 sz64 = sz;
192 u64 mask64 = mask | (u64)~0 << 32;
193
194 pci_read_config_dword(dev, pos + 4, &l);
195 pci_write_config_dword(dev, pos + 4, ~0);
196 pci_read_config_dword(dev, pos + 4, &sz);
197 pci_write_config_dword(dev, pos + 4, l);
198
199 l64 |= ((u64)l << 32);
200 sz64 |= ((u64)sz << 32);
201
202 sz64 = pci_size(l64, sz64, mask64);
203
204 if (!sz64)
205 goto fail;
206
Matthew Wilcoxcc5499c2008-07-28 13:39:00 -0400207 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700208 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
209 pos);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400210 goto fail;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600211 }
212
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600213 if ((sizeof(resource_size_t) < 8) && l) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400214 /* Address above 32-bit boundary; disable the BAR */
215 pci_write_config_dword(dev, pos, 0);
216 pci_write_config_dword(dev, pos + 4, 0);
217 res->start = 0;
218 res->end = sz64;
219 } else {
220 res->start = l64;
221 res->end = l64 + sz64;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600222 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
Bjorn Helgaasa369c792009-10-06 15:33:44 -0600223 pos, res);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400224 }
225 } else {
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600226 sz = pci_size(l, sz, mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400227
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600228 if (!sz)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400229 goto fail;
230
231 res->start = l;
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600232 res->end = l + sz;
Vincent Legollf393d9b2008-10-12 12:26:12 +0200233
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600234 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400235 }
236
237 out:
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600238 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400239 fail:
240 res->flags = 0;
241 goto out;
Yinghai Lu07eddf32006-11-29 13:53:10 -0800242}
243
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
245{
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400246 unsigned int pos, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400248 for (pos = 0; pos < howmany; pos++) {
249 struct resource *res = &dev->resource[pos];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400251 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400253
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 if (rom) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400255 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 dev->rom_base_reg = rom;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400257 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
258 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
259 IORESOURCE_SIZEALIGN;
260 __pci_read_base(dev, pci_bar_mem32, res, rom);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 }
262}
263
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700264static void __devinit pci_read_bridge_io(struct pci_bus *child)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265{
266 struct pci_dev *dev = child->self;
267 u8 io_base_lo, io_limit_lo;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 unsigned long base, limit;
269 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 res = child->resource[0];
272 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
273 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
274 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
275 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
276
277 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
278 u16 io_base_hi, io_limit_hi;
279 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
280 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
281 base |= (io_base_hi << 16);
282 limit |= (io_limit_hi << 16);
283 }
284
Yinghai Lucd81e1e2010-01-22 01:02:22 -0800285 if (base && base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
Daniel Yeisley9d265122005-12-05 07:06:43 -0500287 if (!res->start)
288 res->start = base;
289 if (!res->end)
290 res->end = limit + 0xfff;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600291 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700293}
294
295static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
296{
297 struct pci_dev *dev = child->self;
298 u16 mem_base_lo, mem_limit_lo;
299 unsigned long base, limit;
300 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301
302 res = child->resource[1];
303 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
304 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
305 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
306 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
Yinghai Lucd81e1e2010-01-22 01:02:22 -0800307 if (base && base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
309 res->start = base;
310 res->end = limit + 0xfffff;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600311 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700313}
314
315static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
316{
317 struct pci_dev *dev = child->self;
318 u16 mem_base_lo, mem_limit_lo;
319 unsigned long base, limit;
320 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321
322 res = child->resource[2];
323 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
324 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
325 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
326 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
327
328 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
329 u32 mem_base_hi, mem_limit_hi;
330 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
331 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
332
333 /*
334 * Some bridges set the base > limit by default, and some
335 * (broken) BIOSes do not initialize them. If we find
336 * this, just assume they are not being used.
337 */
338 if (mem_base_hi <= mem_limit_hi) {
339#if BITS_PER_LONG == 64
340 base |= ((long) mem_base_hi) << 32;
341 limit |= ((long) mem_limit_hi) << 32;
342#else
343 if (mem_base_hi || mem_limit_hi) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600344 dev_err(&dev->dev, "can't handle 64-bit "
345 "address space for bridge\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346 return;
347 }
348#endif
349 }
350 }
Yinghai Lucd81e1e2010-01-22 01:02:22 -0800351 if (base && base <= limit) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700352 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
353 IORESOURCE_MEM | IORESOURCE_PREFETCH;
354 if (res->flags & PCI_PREF_RANGE_TYPE_64)
355 res->flags |= IORESOURCE_MEM_64;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 res->start = base;
357 res->end = limit + 0xfffff;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600358 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359 }
360}
361
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700362void __devinit pci_read_bridge_bases(struct pci_bus *child)
363{
364 struct pci_dev *dev = child->self;
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700365 struct resource *res;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700366 int i;
367
368 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
369 return;
370
371 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
372 child->secondary, child->subordinate,
373 dev->transparent ? " (subtractive decode)" : "");
374
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700375 pci_bus_remove_resources(child);
376 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
377 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
378
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700379 pci_read_bridge_io(child);
380 pci_read_bridge_mmio(child);
381 pci_read_bridge_mmio_pref(child);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700382
383 if (dev->transparent) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700384 pci_bus_for_each_resource(child->parent, res, i) {
385 if (res) {
386 pci_bus_add_resource(child, res,
387 PCI_SUBTRACTIVE_DECODE);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700388 dev_printk(KERN_DEBUG, &dev->dev,
389 " bridge window %pR (subtractive decode)\n",
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700390 res);
391 }
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700392 }
393 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700394}
395
Sam Ravnborg96bde062007-03-26 21:53:30 -0800396static struct pci_bus * pci_alloc_bus(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397{
398 struct pci_bus *b;
399
Eric Sesterhennf5afe802006-02-28 15:34:49 +0100400 b = kzalloc(sizeof(*b), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401 if (b) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700402 INIT_LIST_HEAD(&b->node);
403 INIT_LIST_HEAD(&b->children);
404 INIT_LIST_HEAD(&b->devices);
Alex Chiangf46753c2008-06-10 15:28:50 -0600405 INIT_LIST_HEAD(&b->slots);
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700406 INIT_LIST_HEAD(&b->resources);
Matthew Wilcox3749c512009-12-13 08:11:32 -0500407 b->max_bus_speed = PCI_SPEED_UNKNOWN;
408 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409 }
410 return b;
411}
412
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500413static unsigned char pcix_bus_speed[] = {
414 PCI_SPEED_UNKNOWN, /* 0 */
415 PCI_SPEED_66MHz_PCIX, /* 1 */
416 PCI_SPEED_100MHz_PCIX, /* 2 */
417 PCI_SPEED_133MHz_PCIX, /* 3 */
418 PCI_SPEED_UNKNOWN, /* 4 */
419 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
420 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
421 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
422 PCI_SPEED_UNKNOWN, /* 8 */
423 PCI_SPEED_66MHz_PCIX_266, /* 9 */
424 PCI_SPEED_100MHz_PCIX_266, /* A */
425 PCI_SPEED_133MHz_PCIX_266, /* B */
426 PCI_SPEED_UNKNOWN, /* C */
427 PCI_SPEED_66MHz_PCIX_533, /* D */
428 PCI_SPEED_100MHz_PCIX_533, /* E */
429 PCI_SPEED_133MHz_PCIX_533 /* F */
430};
431
Matthew Wilcox3749c512009-12-13 08:11:32 -0500432static unsigned char pcie_link_speed[] = {
433 PCI_SPEED_UNKNOWN, /* 0 */
434 PCIE_SPEED_2_5GT, /* 1 */
435 PCIE_SPEED_5_0GT, /* 2 */
Matthew Wilcox9dfd97f2009-12-13 08:11:35 -0500436 PCIE_SPEED_8_0GT, /* 3 */
Matthew Wilcox3749c512009-12-13 08:11:32 -0500437 PCI_SPEED_UNKNOWN, /* 4 */
438 PCI_SPEED_UNKNOWN, /* 5 */
439 PCI_SPEED_UNKNOWN, /* 6 */
440 PCI_SPEED_UNKNOWN, /* 7 */
441 PCI_SPEED_UNKNOWN, /* 8 */
442 PCI_SPEED_UNKNOWN, /* 9 */
443 PCI_SPEED_UNKNOWN, /* A */
444 PCI_SPEED_UNKNOWN, /* B */
445 PCI_SPEED_UNKNOWN, /* C */
446 PCI_SPEED_UNKNOWN, /* D */
447 PCI_SPEED_UNKNOWN, /* E */
448 PCI_SPEED_UNKNOWN /* F */
449};
450
451void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
452{
453 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
454}
455EXPORT_SYMBOL_GPL(pcie_update_link_speed);
456
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500457static unsigned char agp_speeds[] = {
458 AGP_UNKNOWN,
459 AGP_1X,
460 AGP_2X,
461 AGP_4X,
462 AGP_8X
463};
464
465static enum pci_bus_speed agp_speed(int agp3, int agpstat)
466{
467 int index = 0;
468
469 if (agpstat & 4)
470 index = 3;
471 else if (agpstat & 2)
472 index = 2;
473 else if (agpstat & 1)
474 index = 1;
475 else
476 goto out;
477
478 if (agp3) {
479 index += 2;
480 if (index == 5)
481 index = 0;
482 }
483
484 out:
485 return agp_speeds[index];
486}
487
488
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500489static void pci_set_bus_speed(struct pci_bus *bus)
490{
491 struct pci_dev *bridge = bus->self;
492 int pos;
493
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500494 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
495 if (!pos)
496 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
497 if (pos) {
498 u32 agpstat, agpcmd;
499
500 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
501 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
502
503 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
504 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
505 }
506
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500507 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
508 if (pos) {
509 u16 status;
510 enum pci_bus_speed max;
511 pci_read_config_word(bridge, pos + 2, &status);
512
513 if (status & 0x8000) {
514 max = PCI_SPEED_133MHz_PCIX_533;
515 } else if (status & 0x4000) {
516 max = PCI_SPEED_133MHz_PCIX_266;
517 } else if (status & 0x0002) {
518 if (((status >> 12) & 0x3) == 2) {
519 max = PCI_SPEED_133MHz_PCIX_ECC;
520 } else {
521 max = PCI_SPEED_133MHz_PCIX;
522 }
523 } else {
524 max = PCI_SPEED_66MHz_PCIX;
525 }
526
527 bus->max_bus_speed = max;
528 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
529
530 return;
531 }
532
533 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
534 if (pos) {
535 u32 linkcap;
536 u16 linksta;
537
538 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
539 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
540
541 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
542 pcie_update_link_speed(bus, linksta);
543 }
544}
545
546
Adrian Bunkcbd4e052008-04-18 13:53:55 -0700547static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
548 struct pci_dev *bridge, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549{
550 struct pci_bus *child;
551 int i;
552
553 /*
554 * Allocate a new bus, and inherit stuff from the parent..
555 */
556 child = pci_alloc_bus();
557 if (!child)
558 return NULL;
559
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560 child->parent = parent;
561 child->ops = parent->ops;
562 child->sysdata = parent->sysdata;
Michael S. Tsirkin6e325a62006-02-14 18:52:22 +0200563 child->bus_flags = parent->bus_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400565 /* initialize some portions of the bus device, but don't register it
566 * now as the parent is not properly set up yet. This device will get
567 * registered later in pci_bus_add_devices()
568 */
569 child->dev.class = &pcibus_class;
Kay Sievers1a927132008-10-30 02:17:49 +0100570 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571
572 /*
573 * Set up the primary, secondary and subordinate
574 * bus numbers.
575 */
576 child->number = child->secondary = busnr;
577 child->primary = parent->secondary;
578 child->subordinate = 0xff;
579
Yu Zhao3789fa82008-11-22 02:41:07 +0800580 if (!bridge)
581 return child;
582
583 child->self = bridge;
584 child->bridge = get_device(&bridge->dev);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +1000585 pci_set_bus_of_node(child);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500586 pci_set_bus_speed(child);
587
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588 /* Set up default resource pointers and names.. */
Yu Zhaofde09c62008-11-22 02:39:32 +0800589 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
591 child->resource[i]->name = child->name;
592 }
593 bridge->subordinate = child;
594
595 return child;
596}
597
Sam Ravnborg451124a2008-02-02 22:33:43 +0100598struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599{
600 struct pci_bus *child;
601
602 child = pci_alloc_child_bus(parent, dev, busnr);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700603 if (child) {
Zhang Yanmind71374d2006-06-02 12:35:43 +0800604 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605 list_add_tail(&child->node, &parent->children);
Zhang Yanmind71374d2006-06-02 12:35:43 +0800606 up_write(&pci_bus_sem);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700607 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608 return child;
609}
610
Sam Ravnborg96bde062007-03-26 21:53:30 -0800611static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700612{
613 struct pci_bus *parent = child->parent;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700614
615 /* Attempts to fix that up are really dangerous unless
616 we're going to re-assign all bus numbers. */
617 if (!pcibios_assign_all_busses())
618 return;
619
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700620 while (parent->parent && parent->subordinate < max) {
621 parent->subordinate = max;
622 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
623 parent = parent->parent;
624 }
625}
626
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627/*
628 * If it's a bridge, configure it and scan the bus behind it.
629 * For CardBus bridges, we don't scan behind as the devices will
630 * be handled by the bridge driver itself.
631 *
632 * We need to process bridges in two passes -- first we scan those
633 * already configured by the BIOS and after we are done with all of
634 * them, we proceed to assigning numbers to the remaining buses in
635 * order to avoid overlaps between old and new bus numbers.
636 */
Sam Ravnborg0ab2b572008-02-17 10:45:28 +0100637int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638{
639 struct pci_bus *child;
640 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
Dominik Brodowski49887942005-12-08 16:53:12 +0100641 u32 buses, i, j = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700642 u16 bctl;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600643 u8 primary, secondary, subordinate;
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100644 int broken = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645
646 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600647 primary = buses & 0xFF;
648 secondary = (buses >> 8) & 0xFF;
649 subordinate = (buses >> 16) & 0xFF;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600651 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
652 secondary, subordinate, pass);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100654 /* Check if setup is sensible at all */
655 if (!pass &&
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600656 (primary != bus->number || secondary <= bus->number)) {
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100657 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
658 broken = 1;
659 }
660
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661 /* Disable MasterAbortMode during probing to avoid reporting
662 of bus errors (in some architectures) */
663 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
664 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
665 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
666
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600667 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
668 !is_cardbus && !broken) {
669 unsigned int cmax;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670 /*
671 * Bus already configured by firmware, process it in the first
672 * pass and just note the configuration.
673 */
674 if (pass)
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000675 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676
677 /*
678 * If we already got to this bus through a different bridge,
Alex Chiang74710de2009-03-20 14:56:10 -0600679 * don't re-add it. This can happen with the i450NX chipset.
680 *
681 * However, we continue to descend down the hierarchy and
682 * scan remaining child buses.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 */
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600684 child = pci_find_bus(pci_domain_nr(bus), secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600685 if (!child) {
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600686 child = pci_add_new_bus(bus, dev, secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600687 if (!child)
688 goto out;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600689 child->primary = primary;
690 child->subordinate = subordinate;
Alex Chiang74710de2009-03-20 14:56:10 -0600691 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692 }
693
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694 cmax = pci_scan_child_bus(child);
695 if (cmax > max)
696 max = cmax;
697 if (child->subordinate > max)
698 max = child->subordinate;
699 } else {
700 /*
701 * We need to assign a number to this bus which we always
702 * do in the second pass.
703 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700704 if (!pass) {
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100705 if (pcibios_assign_all_busses() || broken)
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700706 /* Temporarily disable forwarding of the
707 configuration cycles on all bridges in
708 this bus segment to avoid possible
709 conflicts in the second pass between two
710 bridges programmed with overlapping
711 bus ranges. */
712 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
713 buses & ~0xffffff);
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000714 goto out;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700715 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716
717 /* Clear errors */
718 pci_write_config_word(dev, PCI_STATUS, 0xffff);
719
Rajesh Shahcc574502005-04-28 00:25:47 -0700720 /* Prevent assigning a bus number that already exists.
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800721 * This can happen when a bridge is hot-plugged, so in
722 * this case we only re-scan this bus. */
723 child = pci_find_bus(pci_domain_nr(bus), max+1);
724 if (!child) {
725 child = pci_add_new_bus(bus, dev, ++max);
726 if (!child)
727 goto out;
728 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729 buses = (buses & 0xff000000)
730 | ((unsigned int)(child->primary) << 0)
731 | ((unsigned int)(child->secondary) << 8)
732 | ((unsigned int)(child->subordinate) << 16);
733
734 /*
735 * yenta.c forces a secondary latency timer of 176.
736 * Copy that behaviour here.
737 */
738 if (is_cardbus) {
739 buses &= ~0xff000000;
740 buses |= CARDBUS_LATENCY_TIMER << 24;
741 }
Jesper Juhl7c867c82011-01-24 21:14:33 +0100742
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743 /*
744 * We need to blast all three values with a single write.
745 */
746 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
747
748 if (!is_cardbus) {
Gary Hade11949252007-10-08 16:24:16 -0700749 child->bridge_ctl = bctl;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700750 /*
751 * Adjust subordinate busnr in parent buses.
752 * We do this before scanning for children because
753 * some devices may not be detected if the bios
754 * was lazy.
755 */
756 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757 /* Now we can scan all subordinate buses... */
758 max = pci_scan_child_bus(child);
Kristen Accardie3ac86d2006-01-17 16:57:01 -0800759 /*
760 * now fix it up again since we have found
761 * the real value of max.
762 */
763 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764 } else {
765 /*
766 * For CardBus bridges, we leave 4 bus numbers
767 * as cards with a PCI-to-PCI bridge can be
768 * inserted later.
769 */
Dominik Brodowski49887942005-12-08 16:53:12 +0100770 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
771 struct pci_bus *parent = bus;
Rajesh Shahcc574502005-04-28 00:25:47 -0700772 if (pci_find_bus(pci_domain_nr(bus),
773 max+i+1))
774 break;
Dominik Brodowski49887942005-12-08 16:53:12 +0100775 while (parent->parent) {
776 if ((!pcibios_assign_all_busses()) &&
777 (parent->subordinate > max) &&
778 (parent->subordinate <= max+i)) {
779 j = 1;
780 }
781 parent = parent->parent;
782 }
783 if (j) {
784 /*
785 * Often, there are two cardbus bridges
786 * -- try to leave one valid bus number
787 * for each one.
788 */
789 i /= 2;
790 break;
791 }
792 }
Rajesh Shahcc574502005-04-28 00:25:47 -0700793 max += i;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700794 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 }
796 /*
797 * Set the subordinate bus number to its real value.
798 */
799 child->subordinate = max;
800 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
801 }
802
Gary Hadecb3576f2008-02-08 14:00:52 -0800803 sprintf(child->name,
804 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
805 pci_domain_nr(bus), child->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200807 /* Has only triggered on CardBus, fixup is in yenta_socket */
Dominik Brodowski49887942005-12-08 16:53:12 +0100808 while (bus->parent) {
809 if ((child->subordinate > bus->subordinate) ||
810 (child->number > bus->subordinate) ||
811 (child->number < bus->number) ||
812 (child->subordinate < bus->number)) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700813 dev_info(&child->dev, "[bus %02x-%02x] %s "
814 "hidden behind%s bridge %s [bus %02x-%02x]\n",
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200815 child->number, child->subordinate,
816 (bus->number > child->subordinate &&
817 bus->subordinate < child->number) ?
Joe Perchesa6f29a92007-11-19 17:48:29 -0800818 "wholly" : "partially",
819 bus->self->transparent ? " transparent" : "",
Bjorn Helgaas865df572009-11-04 10:32:57 -0700820 dev_name(&bus->dev),
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200821 bus->number, bus->subordinate);
Dominik Brodowski49887942005-12-08 16:53:12 +0100822 }
823 bus = bus->parent;
824 }
825
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000826out:
827 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
828
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829 return max;
830}
831
832/*
833 * Read interrupt line and base address registers.
834 * The architecture-dependent code can tweak these, of course.
835 */
836static void pci_read_irq(struct pci_dev *dev)
837{
838 unsigned char irq;
839
840 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
Kristen Accardiffeff782005-11-02 16:24:32 -0800841 dev->pin = irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 if (irq)
843 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
844 dev->irq = irq;
845}
846
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +0000847void set_pcie_port_type(struct pci_dev *pdev)
Yu Zhao480b93b2009-03-20 11:25:14 +0800848{
849 int pos;
850 u16 reg16;
851
852 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
853 if (!pos)
854 return;
855 pdev->is_pcie = 1;
Kenji Kaneshige0efea002009-11-05 12:05:11 +0900856 pdev->pcie_cap = pos;
Yu Zhao480b93b2009-03-20 11:25:14 +0800857 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
858 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
Jon Masonb03e7492011-07-20 15:20:54 -0500859 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
860 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
Yu Zhao480b93b2009-03-20 11:25:14 +0800861}
862
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +0000863void set_pcie_hotplug_bridge(struct pci_dev *pdev)
Eric W. Biederman28760482009-09-09 14:09:24 -0700864{
865 int pos;
866 u16 reg16;
867 u32 reg32;
868
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +0900869 pos = pci_pcie_cap(pdev);
Eric W. Biederman28760482009-09-09 14:09:24 -0700870 if (!pos)
871 return;
872 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
873 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
874 return;
875 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
876 if (reg32 & PCI_EXP_SLTCAP_HPC)
877 pdev->is_hotplug_bridge = 1;
878}
879
Bartlomiej Zolnierkiewicz01abc2a2007-04-23 23:19:36 +0200880#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
Randy Dunlap76e6a1d2006-12-29 16:47:29 -0800881
Linus Torvalds1da177e2005-04-16 15:20:36 -0700882/**
883 * pci_setup_device - fill in class and map information of a device
884 * @dev: the device structure to fill
885 *
886 * Initialize the device structure with information about the device's
887 * vendor,class,memory and IO-space addresses,IRQ lines etc.
888 * Called at initialisation of the PCI subsystem and by CardBus services.
Yu Zhao480b93b2009-03-20 11:25:14 +0800889 * Returns 0 on success and negative if unknown type of device (not normal,
890 * bridge or CardBus).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891 */
Yu Zhao480b93b2009-03-20 11:25:14 +0800892int pci_setup_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700893{
894 u32 class;
Yu Zhao480b93b2009-03-20 11:25:14 +0800895 u8 hdr_type;
896 struct pci_slot *slot;
Gabe Blackbc577d22009-10-06 10:45:19 -0500897 int pos = 0;
Yu Zhao480b93b2009-03-20 11:25:14 +0800898
899 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
900 return -EIO;
901
902 dev->sysdata = dev->bus->sysdata;
903 dev->dev.parent = dev->bus->bridge;
904 dev->dev.bus = &pci_bus_type;
905 dev->hdr_type = hdr_type & 0x7f;
906 dev->multifunction = !!(hdr_type & 0x80);
Yu Zhao480b93b2009-03-20 11:25:14 +0800907 dev->error_state = pci_channel_io_normal;
908 set_pcie_port_type(dev);
909
910 list_for_each_entry(slot, &dev->bus->slots, list)
911 if (PCI_SLOT(dev->devfn) == slot->number)
912 dev->slot = slot;
913
914 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
915 set this higher, assuming the system even supports it. */
916 dev->dma_mask = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700917
Greg Kroah-Hartmaneebfcfb2008-07-02 13:24:49 -0700918 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
919 dev->bus->number, PCI_SLOT(dev->devfn),
920 PCI_FUNC(dev->devfn));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921
922 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
Auke Kokb8a3a522007-06-08 15:46:30 -0700923 dev->revision = class & 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924 class >>= 8; /* upper 3 bytes */
925 dev->class = class;
926 class >>= 8;
927
Bjorn Helgaas2c6413a2010-09-29 12:23:21 -0600928 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n",
929 dev->vendor, dev->device, dev->hdr_type, class);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700930
Yu Zhao853346e2009-03-21 22:05:11 +0800931 /* need to have dev->class ready */
932 dev->cfg_size = pci_cfg_space_size(dev);
933
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934 /* "Unknown power state" */
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700935 dev->current_state = PCI_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936
937 /* Early fixups, before probing the BARs */
938 pci_fixup_device(pci_fixup_early, dev);
Yu Zhaof79b1b12009-05-28 00:25:05 +0800939 /* device class may be changed after fixup */
940 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700941
942 switch (dev->hdr_type) { /* header type */
943 case PCI_HEADER_TYPE_NORMAL: /* standard header */
944 if (class == PCI_CLASS_BRIDGE_PCI)
945 goto bad;
946 pci_read_irq(dev);
947 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
948 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
949 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
Alan Cox368c73d2006-10-04 00:41:26 +0100950
951 /*
952 * Do the ugly legacy mode stuff here rather than broken chip
953 * quirk code. Legacy mode ATA controllers have fixed
954 * addresses. These are not always echoed in BAR0-3, and
955 * BAR0-3 in a few cases contain junk!
956 */
957 if (class == PCI_CLASS_STORAGE_IDE) {
958 u8 progif;
959 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
960 if ((progif & 1) == 0) {
Linus Torvaldsaf1bff42007-12-10 07:40:54 -0800961 dev->resource[0].start = 0x1F0;
962 dev->resource[0].end = 0x1F7;
963 dev->resource[0].flags = LEGACY_IO_RESOURCE;
964 dev->resource[1].start = 0x3F6;
965 dev->resource[1].end = 0x3F6;
966 dev->resource[1].flags = LEGACY_IO_RESOURCE;
Alan Cox368c73d2006-10-04 00:41:26 +0100967 }
968 if ((progif & 4) == 0) {
Linus Torvaldsaf1bff42007-12-10 07:40:54 -0800969 dev->resource[2].start = 0x170;
970 dev->resource[2].end = 0x177;
971 dev->resource[2].flags = LEGACY_IO_RESOURCE;
972 dev->resource[3].start = 0x376;
973 dev->resource[3].end = 0x376;
974 dev->resource[3].flags = LEGACY_IO_RESOURCE;
Alan Cox368c73d2006-10-04 00:41:26 +0100975 }
976 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700977 break;
978
979 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
980 if (class != PCI_CLASS_BRIDGE_PCI)
981 goto bad;
982 /* The PCI-to-PCI bridge spec requires that subtractive
983 decoding (i.e. transparent) bridge must have programming
984 interface code of 0x01. */
Kristen Accardi3efd2732005-11-02 16:55:49 -0800985 pci_read_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986 dev->transparent = ((dev->class & 0xff) == 1);
987 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
Eric W. Biederman28760482009-09-09 14:09:24 -0700988 set_pcie_hotplug_bridge(dev);
Gabe Blackbc577d22009-10-06 10:45:19 -0500989 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
990 if (pos) {
991 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
992 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
993 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700994 break;
995
996 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
997 if (class != PCI_CLASS_BRIDGE_CARDBUS)
998 goto bad;
999 pci_read_irq(dev);
1000 pci_read_bases(dev, 1, 0);
1001 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1002 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1003 break;
1004
1005 default: /* unknown header */
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001006 dev_err(&dev->dev, "unknown header type %02x, "
1007 "ignoring device\n", dev->hdr_type);
Yu Zhao480b93b2009-03-20 11:25:14 +08001008 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009
1010 bad:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001011 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1012 "type %02x)\n", class, dev->hdr_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013 dev->class = PCI_CLASS_NOT_DEFINED;
1014 }
1015
1016 /* We found a fine healthy device, go go go... */
1017 return 0;
1018}
1019
Zhao, Yu201de562008-10-13 19:49:55 +08001020static void pci_release_capabilities(struct pci_dev *dev)
1021{
1022 pci_vpd_release(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001023 pci_iov_release(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001024}
1025
Linus Torvalds1da177e2005-04-16 15:20:36 -07001026/**
1027 * pci_release_dev - free a pci device structure when all users of it are finished.
1028 * @dev: device that's been disconnected
1029 *
1030 * Will be called only by the device core when all users of this pci device are
1031 * done.
1032 */
1033static void pci_release_dev(struct device *dev)
1034{
1035 struct pci_dev *pci_dev;
1036
1037 pci_dev = to_pci_dev(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001038 pci_release_capabilities(pci_dev);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001039 pci_release_of_node(pci_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001040 kfree(pci_dev);
1041}
1042
1043/**
1044 * pci_cfg_space_size - get the configuration space size of the PCI device.
Randy Dunlap8f7020d2005-10-23 11:57:38 -07001045 * @dev: PCI device
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046 *
1047 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1048 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1049 * access it. Maybe we don't have a way to generate extended config space
1050 * accesses, or the device is behind a reverse Express bridge. So we try
1051 * reading the dword at 0x100 which must either be 0 or a valid extended
1052 * capability header.
1053 */
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001054int pci_cfg_space_size_ext(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001055{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056 u32 status;
Zhao, Yu557848c2008-10-13 19:18:07 +08001057 int pos = PCI_CFG_SPACE_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058
Zhao, Yu557848c2008-10-13 19:18:07 +08001059 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060 goto fail;
1061 if (status == 0xffffffff)
1062 goto fail;
1063
1064 return PCI_CFG_SPACE_EXP_SIZE;
1065
1066 fail:
1067 return PCI_CFG_SPACE_SIZE;
1068}
1069
Yinghai Lu57741a72008-02-15 01:32:50 -08001070int pci_cfg_space_size(struct pci_dev *dev)
1071{
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001072 int pos;
1073 u32 status;
Yinghai Ludfadd9ed2009-03-08 21:35:37 -07001074 u16 class;
1075
1076 class = dev->class >> 8;
1077 if (class == PCI_CLASS_BRIDGE_HOST)
1078 return pci_cfg_space_size_ext(dev);
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001079
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +09001080 pos = pci_pcie_cap(dev);
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001081 if (!pos) {
1082 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1083 if (!pos)
1084 goto fail;
1085
1086 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1087 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1088 goto fail;
1089 }
1090
1091 return pci_cfg_space_size_ext(dev);
1092
1093 fail:
1094 return PCI_CFG_SPACE_SIZE;
Yinghai Lu57741a72008-02-15 01:32:50 -08001095}
1096
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097static void pci_release_bus_bridge_dev(struct device *dev)
1098{
1099 kfree(dev);
1100}
1101
Michael Ellerman65891212007-04-05 17:19:08 +10001102struct pci_dev *alloc_pci_dev(void)
1103{
1104 struct pci_dev *dev;
1105
1106 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1107 if (!dev)
1108 return NULL;
1109
Michael Ellerman65891212007-04-05 17:19:08 +10001110 INIT_LIST_HEAD(&dev->bus_list);
1111
1112 return dev;
1113}
1114EXPORT_SYMBOL(alloc_pci_dev);
1115
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116/*
1117 * Read the config data for a PCI device, sanity-check it
1118 * and fill in the dev structure...
1119 */
Adrian Bunk7f7b5de2008-04-18 13:53:55 -07001120static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121{
1122 struct pci_dev *dev;
1123 u32 l;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124 int delay = 1;
1125
1126 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1127 return NULL;
1128
1129 /* some broken boards return 0 or ~0 if a slot is empty: */
1130 if (l == 0xffffffff || l == 0x00000000 ||
1131 l == 0x0000ffff || l == 0xffff0000)
1132 return NULL;
1133
1134 /* Configuration request Retry Status */
1135 while (l == 0xffff0001) {
1136 msleep(delay);
1137 delay *= 2;
1138 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1139 return NULL;
1140 /* Card hasn't responded in 60 seconds? Must be stuck. */
1141 if (delay > 60 * 1000) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001142 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001143 "responding\n", pci_domain_nr(bus),
1144 bus->number, PCI_SLOT(devfn),
1145 PCI_FUNC(devfn));
1146 return NULL;
1147 }
1148 }
1149
Michael Ellermanbab41e92007-04-05 17:19:09 +10001150 dev = alloc_pci_dev();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151 if (!dev)
1152 return NULL;
1153
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154 dev->bus = bus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001155 dev->devfn = devfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156 dev->vendor = l & 0xffff;
1157 dev->device = (l >> 16) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001159 pci_set_of_node(dev);
1160
Yu Zhao480b93b2009-03-20 11:25:14 +08001161 if (pci_setup_device(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001162 kfree(dev);
1163 return NULL;
1164 }
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001165
1166 return dev;
1167}
1168
Zhao, Yu201de562008-10-13 19:49:55 +08001169static void pci_init_capabilities(struct pci_dev *dev)
1170{
1171 /* MSI/MSI-X list */
1172 pci_msi_init_pci_dev(dev);
1173
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001174 /* Buffers for saving PCIe and PCI-X capabilities */
1175 pci_allocate_cap_save_buffers(dev);
1176
Zhao, Yu201de562008-10-13 19:49:55 +08001177 /* Power Management */
1178 pci_pm_init(dev);
Jesse Barneseb9c39d2008-12-17 12:10:05 -08001179 platform_pci_wakeup_init(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001180
1181 /* Vital Product Data */
1182 pci_vpd_pci22_init(dev);
Yu Zhao58c3a722008-10-14 14:02:53 +08001183
1184 /* Alternative Routing-ID Forwarding */
1185 pci_enable_ari(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001186
1187 /* Single Root I/O Virtualization */
1188 pci_iov_init(dev);
Allen Kayae21ee62009-10-07 10:27:17 -07001189
1190 /* Enable ACS P2P upstream forwarding */
Chris Wright5d990b62009-12-04 12:15:21 -08001191 pci_enable_acs(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001192}
1193
Sam Ravnborg96bde062007-03-26 21:53:30 -08001194void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001195{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196 device_initialize(&dev->dev);
1197 dev->dev.release = pci_release_dev;
1198 pci_dev_get(dev);
1199
Linus Torvalds1da177e2005-04-16 15:20:36 -07001200 dev->dev.dma_mask = &dev->dma_mask;
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001201 dev->dev.dma_parms = &dev->dma_parms;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001202 dev->dev.coherent_dma_mask = 0xffffffffull;
1203
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001204 pci_set_dma_max_seg_size(dev, 65536);
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08001205 pci_set_dma_seg_boundary(dev, 0xffffffff);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001206
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207 /* Fix up broken headers */
1208 pci_fixup_device(pci_fixup_header, dev);
1209
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001210 /* Clear the state_saved flag. */
1211 dev->state_saved = false;
1212
Zhao, Yu201de562008-10-13 19:49:55 +08001213 /* Initialize various capabilities */
1214 pci_init_capabilities(dev);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001215
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216 /*
1217 * Add the device to our list of discovered devices
1218 * and the bus list for fixup functions, etc.
1219 */
Zhang Yanmind71374d2006-06-02 12:35:43 +08001220 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221 list_add_tail(&dev->bus_list, &bus->devices);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001222 up_write(&pci_bus_sem);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001223}
1224
Sam Ravnborg451124a2008-02-02 22:33:43 +01001225struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001226{
1227 struct pci_dev *dev;
1228
Trent Piepho90bdb312009-03-20 14:56:00 -06001229 dev = pci_get_slot(bus, devfn);
1230 if (dev) {
1231 pci_dev_put(dev);
1232 return dev;
1233 }
1234
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001235 dev = pci_scan_device(bus, devfn);
1236 if (!dev)
1237 return NULL;
1238
1239 pci_device_add(dev, bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240
1241 return dev;
1242}
Adrian Bunkb73e9682007-11-21 15:07:11 -08001243EXPORT_SYMBOL(pci_scan_single_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001245static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1246{
1247 u16 cap;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001248 unsigned pos, next_fn;
1249
1250 if (!dev)
1251 return 0;
1252
1253 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001254 if (!pos)
1255 return 0;
1256 pci_read_config_word(dev, pos + 4, &cap);
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001257 next_fn = cap >> 8;
1258 if (next_fn <= fn)
1259 return 0;
1260 return next_fn;
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001261}
1262
1263static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1264{
1265 return (fn + 1) % 8;
1266}
1267
1268static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1269{
1270 return 0;
1271}
1272
1273static int only_one_child(struct pci_bus *bus)
1274{
1275 struct pci_dev *parent = bus->self;
1276 if (!parent || !pci_is_pcie(parent))
1277 return 0;
1278 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1279 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1280 return 1;
1281 return 0;
1282}
1283
Linus Torvalds1da177e2005-04-16 15:20:36 -07001284/**
1285 * pci_scan_slot - scan a PCI slot on a bus for devices.
1286 * @bus: PCI bus to scan
1287 * @devfn: slot number to scan (must have zero function.)
1288 *
1289 * Scan a PCI slot on the specified PCI bus for devices, adding
1290 * discovered devices to the @bus->devices list. New devices
Greg Kroah-Hartman8a1bc902008-02-14 14:56:56 -08001291 * will not have is_added set.
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001292 *
1293 * Returns the number of new devices found.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001294 */
Sam Ravnborg96bde062007-03-26 21:53:30 -08001295int pci_scan_slot(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001296{
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001297 unsigned fn, nr = 0;
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001298 struct pci_dev *dev;
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001299 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1300
1301 if (only_one_child(bus) && (devfn > 0))
1302 return 0; /* Already scanned the entire slot */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001303
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001304 dev = pci_scan_single_device(bus, devfn);
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001305 if (!dev)
1306 return 0;
1307 if (!dev->is_added)
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001308 nr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001309
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001310 if (pci_ari_enabled(bus))
1311 next_fn = next_ari_fn;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001312 else if (dev->multifunction)
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001313 next_fn = next_trad_fn;
1314
1315 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1316 dev = pci_scan_single_device(bus, devfn + fn);
1317 if (dev) {
1318 if (!dev->is_added)
1319 nr++;
1320 dev->multifunction = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001321 }
1322 }
Shaohua Li7d715a62008-02-25 09:46:41 +08001323
Shaohua Li149e1632008-07-23 10:32:31 +08001324 /* only one slot has pcie device */
1325 if (bus->self && nr)
Shaohua Li7d715a62008-02-25 09:46:41 +08001326 pcie_aspm_init_link_state(bus->self);
1327
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328 return nr;
1329}
1330
Jon Masonb03e7492011-07-20 15:20:54 -05001331static int pcie_find_smpss(struct pci_dev *dev, void *data)
1332{
1333 u8 *smpss = data;
1334
1335 if (!pci_is_pcie(dev))
1336 return 0;
1337
1338 /* For PCIE hotplug enabled slots not connected directly to a
1339 * PCI-E root port, there can be problems when hotplugging
1340 * devices. This is due to the possibility of hotplugging a
1341 * device into the fabric with a smaller MPS that the devices
1342 * currently running have configured. Modifying the MPS on the
1343 * running devices could cause a fatal bus error due to an
1344 * incoming frame being larger than the newly configured MPS.
1345 * To work around this, the MPS for the entire fabric must be
1346 * set to the minimum size. Any devices hotplugged into this
1347 * fabric will have the minimum MPS set. If the PCI hotplug
1348 * slot is directly connected to the root port and there are not
1349 * other devices on the fabric (which seems to be the most
1350 * common case), then this is not an issue and MPS discovery
1351 * will occur as normal.
1352 */
1353 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
Benjamin Herrenschmidt1a4b1a42011-09-13 15:16:33 -03001354 (dev->bus->self &&
1355 dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
Jon Masonb03e7492011-07-20 15:20:54 -05001356 *smpss = 0;
1357
1358 if (*smpss > dev->pcie_mpss)
1359 *smpss = dev->pcie_mpss;
1360
1361 return 0;
1362}
1363
1364static void pcie_write_mps(struct pci_dev *dev, int mps)
1365{
Jon Mason62f392e2011-10-14 14:56:14 -05001366 int rc;
Jon Masonb03e7492011-07-20 15:20:54 -05001367
1368 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
Jon Mason62f392e2011-10-14 14:56:14 -05001369 mps = 128 << dev->pcie_mpss;
Jon Masonb03e7492011-07-20 15:20:54 -05001370
Jon Mason62f392e2011-10-14 14:56:14 -05001371 if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self)
1372 /* For "Performance", the assumption is made that
Jon Masonb03e7492011-07-20 15:20:54 -05001373 * downstream communication will never be larger than
1374 * the MRRS. So, the MPS only needs to be configured
1375 * for the upstream communication. This being the case,
1376 * walk from the top down and set the MPS of the child
1377 * to that of the parent bus.
Jon Mason62f392e2011-10-14 14:56:14 -05001378 *
1379 * Configure the device MPS with the smaller of the
1380 * device MPSS or the bridge MPS (which is assumed to be
1381 * properly configured at this point to the largest
1382 * allowable MPS based on its parent bus).
Jon Masonb03e7492011-07-20 15:20:54 -05001383 */
Jon Mason62f392e2011-10-14 14:56:14 -05001384 mps = min(mps, pcie_get_mps(dev->bus->self));
Jon Masonb03e7492011-07-20 15:20:54 -05001385 }
1386
1387 rc = pcie_set_mps(dev, mps);
1388 if (rc)
1389 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1390}
1391
Jon Mason62f392e2011-10-14 14:56:14 -05001392static void pcie_write_mrrs(struct pci_dev *dev)
Jon Masonb03e7492011-07-20 15:20:54 -05001393{
Jon Mason62f392e2011-10-14 14:56:14 -05001394 int rc, mrrs;
Jon Masonb03e7492011-07-20 15:20:54 -05001395
Jon Masoned2888e2011-09-08 16:41:18 -05001396 /* In the "safe" case, do not configure the MRRS. There appear to be
1397 * issues with setting MRRS to 0 on a number of devices.
1398 */
Jon Masoned2888e2011-09-08 16:41:18 -05001399 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1400 return;
Jon Masonb03e7492011-07-20 15:20:54 -05001401
Jon Masoned2888e2011-09-08 16:41:18 -05001402 /* For Max performance, the MRRS must be set to the largest supported
1403 * value. However, it cannot be configured larger than the MPS the
Jon Mason62f392e2011-10-14 14:56:14 -05001404 * device or the bus can support. This should already be properly
1405 * configured by a prior call to pcie_write_mps.
Jon Masoned2888e2011-09-08 16:41:18 -05001406 */
Jon Mason62f392e2011-10-14 14:56:14 -05001407 mrrs = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001408
1409 /* MRRS is a R/W register. Invalid values can be written, but a
Jon Masoned2888e2011-09-08 16:41:18 -05001410 * subsequent read will verify if the value is acceptable or not.
Jon Masonb03e7492011-07-20 15:20:54 -05001411 * If the MRRS value provided is not acceptable (e.g., too large),
1412 * shrink the value until it is acceptable to the HW.
1413 */
1414 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1415 rc = pcie_set_readrq(dev, mrrs);
Jon Mason62f392e2011-10-14 14:56:14 -05001416 if (!rc)
1417 break;
Jon Masonb03e7492011-07-20 15:20:54 -05001418
Jon Mason62f392e2011-10-14 14:56:14 -05001419 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001420 mrrs /= 2;
1421 }
Jon Mason62f392e2011-10-14 14:56:14 -05001422
1423 if (mrrs < 128)
1424 dev_err(&dev->dev, "MRRS was unable to be configured with a "
1425 "safe value. If problems are experienced, try running "
1426 "with pci=pcie_bus_safe.\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001427}
1428
1429static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1430{
Jon Masona513a992011-10-14 14:56:16 -05001431 int mps, orig_mps;
Jon Masonb03e7492011-07-20 15:20:54 -05001432
1433 if (!pci_is_pcie(dev))
1434 return 0;
1435
Jon Masona513a992011-10-14 14:56:16 -05001436 mps = 128 << *(u8 *)data;
1437 orig_mps = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001438
1439 pcie_write_mps(dev, mps);
Jon Mason62f392e2011-10-14 14:56:14 -05001440 pcie_write_mrrs(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001441
Jon Masona513a992011-10-14 14:56:16 -05001442 dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
1443 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1444 orig_mps, pcie_get_readrq(dev));
Jon Masonb03e7492011-07-20 15:20:54 -05001445
1446 return 0;
1447}
1448
Jon Masona513a992011-10-14 14:56:16 -05001449/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
Jon Masonb03e7492011-07-20 15:20:54 -05001450 * parents then children fashion. If this changes, then this code will not
1451 * work as designed.
1452 */
1453void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1454{
Jon Mason5f39e672011-10-03 09:50:20 -05001455 u8 smpss;
Jon Masonb03e7492011-07-20 15:20:54 -05001456
Jon Masonb03e7492011-07-20 15:20:54 -05001457 if (!pci_is_pcie(bus->self))
1458 return;
1459
Jon Mason5f39e672011-10-03 09:50:20 -05001460 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1461 return;
1462
1463 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1464 * to be aware to the MPS of the destination. To work around this,
1465 * simply force the MPS of the entire system to the smallest possible.
1466 */
1467 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1468 smpss = 0;
1469
Jon Masonb03e7492011-07-20 15:20:54 -05001470 if (pcie_bus_config == PCIE_BUS_SAFE) {
Jon Mason5f39e672011-10-03 09:50:20 -05001471 smpss = mpss;
1472
Jon Masonb03e7492011-07-20 15:20:54 -05001473 pcie_find_smpss(bus->self, &smpss);
1474 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1475 }
1476
1477 pcie_bus_configure_set(bus->self, &smpss);
1478 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1479}
Jon Masondebc3b72011-08-02 00:01:18 -05001480EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
Jon Masonb03e7492011-07-20 15:20:54 -05001481
Sam Ravnborg0ab2b572008-02-17 10:45:28 +01001482unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001483{
1484 unsigned int devfn, pass, max = bus->secondary;
1485 struct pci_dev *dev;
1486
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001487 dev_dbg(&bus->dev, "scanning bus\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488
1489 /* Go find them, Rover! */
1490 for (devfn = 0; devfn < 0x100; devfn += 8)
1491 pci_scan_slot(bus, devfn);
1492
Yu Zhaoa28724b2009-03-20 11:25:13 +08001493 /* Reserve buses for SR-IOV capability. */
1494 max += pci_iov_bus_range(bus);
1495
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496 /*
1497 * After performing arch-dependent fixup of the bus, look behind
1498 * all PCI-to-PCI bridges on this bus.
1499 */
Alex Chiang74710de2009-03-20 14:56:10 -06001500 if (!bus->is_added) {
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001501 dev_dbg(&bus->dev, "fixups for bus\n");
Alex Chiang74710de2009-03-20 14:56:10 -06001502 pcibios_fixup_bus(bus);
1503 if (pci_is_root_bus(bus))
1504 bus->is_added = 1;
1505 }
1506
Linus Torvalds1da177e2005-04-16 15:20:36 -07001507 for (pass=0; pass < 2; pass++)
1508 list_for_each_entry(dev, &bus->devices, bus_list) {
1509 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1510 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1511 max = pci_scan_bridge(bus, dev, max, pass);
1512 }
1513
1514 /*
1515 * We've scanned the bus and so we know all about what's on
1516 * the other side of any bridges that may be on this bus plus
1517 * any devices.
1518 *
1519 * Return how far we've got finding sub-buses.
1520 */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001521 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001522 return max;
1523}
1524
Sam Ravnborg96bde062007-03-26 21:53:30 -08001525struct pci_bus * pci_create_bus(struct device *parent,
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001526 int bus, struct pci_ops *ops, void *sysdata)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001527{
1528 int error;
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001529 struct pci_bus *b, *b2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530 struct device *dev;
1531
1532 b = pci_alloc_bus();
1533 if (!b)
1534 return NULL;
1535
Geert Uytterhoeven6a3b3e22009-03-15 20:14:37 +01001536 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001537 if (!dev){
1538 kfree(b);
1539 return NULL;
1540 }
1541
1542 b->sysdata = sysdata;
1543 b->ops = ops;
1544
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001545 b2 = pci_find_bus(pci_domain_nr(b), bus);
1546 if (b2) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001547 /* If we already got to this bus through a different bridge, ignore it */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001548 dev_dbg(&b2->dev, "bus already known\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549 goto err_out;
1550 }
Zhang Yanmind71374d2006-06-02 12:35:43 +08001551
1552 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553 list_add_tail(&b->node, &pci_root_buses);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001554 up_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001555
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556 dev->parent = parent;
1557 dev->release = pci_release_bus_bridge_dev;
Kay Sievers1a927132008-10-30 02:17:49 +01001558 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001559 error = device_register(dev);
1560 if (error)
1561 goto dev_reg_err;
1562 b->bridge = get_device(dev);
Rafael J. Wysockia1e4d722010-02-08 19:16:33 +01001563 device_enable_async_suspend(b->bridge);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001564 pci_set_bus_of_node(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001565
Yinghai Lu0d358f22008-02-19 03:20:41 -08001566 if (!parent)
1567 set_dev_node(b->bridge, pcibus_to_node(b));
1568
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001569 b->dev.class = &pcibus_class;
1570 b->dev.parent = b->bridge;
Kay Sievers1a927132008-10-30 02:17:49 +01001571 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001572 error = device_register(&b->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001573 if (error)
1574 goto class_dev_reg_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001575
1576 /* Create legacy_io and legacy_mem files for this bus */
1577 pci_create_legacy_files(b);
1578
Linus Torvalds1da177e2005-04-16 15:20:36 -07001579 b->number = b->secondary = bus;
1580 b->resource[0] = &ioport_resource;
1581 b->resource[1] = &iomem_resource;
1582
Linus Torvalds1da177e2005-04-16 15:20:36 -07001583 return b;
1584
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585class_dev_reg_err:
1586 device_unregister(dev);
1587dev_reg_err:
Zhang Yanmind71374d2006-06-02 12:35:43 +08001588 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001589 list_del(&b->node);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001590 up_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001591err_out:
1592 kfree(dev);
1593 kfree(b);
1594 return NULL;
1595}
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001596
Sam Ravnborg0ab2b572008-02-17 10:45:28 +01001597struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001598 int bus, struct pci_ops *ops, void *sysdata)
1599{
1600 struct pci_bus *b;
1601
1602 b = pci_create_bus(parent, bus, ops, sysdata);
1603 if (b)
1604 b->subordinate = pci_scan_child_bus(b);
1605 return b;
1606}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001607EXPORT_SYMBOL(pci_scan_bus_parented);
1608
1609#ifdef CONFIG_HOTPLUG
Alex Chiang3ed4fd92009-03-20 14:56:25 -06001610/**
1611 * pci_rescan_bus - scan a PCI bus for devices.
1612 * @bus: PCI bus to scan
1613 *
1614 * Scan a PCI bus and child buses for new devices, adds them,
1615 * and enables them.
1616 *
1617 * Returns the max number of subordinate bus discovered.
1618 */
Alex Chiang5446a6b2009-04-01 18:24:12 -06001619unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
Alex Chiang3ed4fd92009-03-20 14:56:25 -06001620{
1621 unsigned int max;
1622 struct pci_dev *dev;
1623
1624 max = pci_scan_child_bus(bus);
1625
Alex Chiang705b1aa2009-03-20 14:56:31 -06001626 down_read(&pci_bus_sem);
Alex Chiang3ed4fd92009-03-20 14:56:25 -06001627 list_for_each_entry(dev, &bus->devices, bus_list)
1628 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1629 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1630 if (dev->subordinate)
1631 pci_bus_size_bridges(dev->subordinate);
Alex Chiang705b1aa2009-03-20 14:56:31 -06001632 up_read(&pci_bus_sem);
Alex Chiang3ed4fd92009-03-20 14:56:25 -06001633
1634 pci_bus_assign_resources(bus);
1635 pci_enable_bridges(bus);
1636 pci_bus_add_devices(bus);
1637
1638 return max;
1639}
1640EXPORT_SYMBOL_GPL(pci_rescan_bus);
1641
Linus Torvalds1da177e2005-04-16 15:20:36 -07001642EXPORT_SYMBOL(pci_add_new_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001643EXPORT_SYMBOL(pci_scan_slot);
1644EXPORT_SYMBOL(pci_scan_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001645EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1646#endif
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001647
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001648static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001649{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001650 const struct pci_dev *a = to_pci_dev(d_a);
1651 const struct pci_dev *b = to_pci_dev(d_b);
1652
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001653 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1654 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1655
1656 if (a->bus->number < b->bus->number) return -1;
1657 else if (a->bus->number > b->bus->number) return 1;
1658
1659 if (a->devfn < b->devfn) return -1;
1660 else if (a->devfn > b->devfn) return 1;
1661
1662 return 0;
1663}
1664
Greg Kroah-Hartman5ff580c2008-02-14 14:56:56 -08001665void __init pci_sort_breadthfirst(void)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001666{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001667 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001668}