blob: 01442fc257de1032314019c70ab88190c7525738 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -06001/dts-v1/;
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -06003#include "tegra20.dtsi"
Grant Likely8e267f32011-07-19 17:26:54 -06004
5/ {
6 model = "NVIDIA Seaboard";
7 compatible = "nvidia,seaboard", "nvidia,tegra20";
8
Grant Likely8e267f32011-07-19 17:26:54 -06009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -060011 };
12
Stephen Warren58ecb232013-11-25 17:53:16 -070013 host1x@50000000 {
14 hdmi@54280000 {
Stephen Warrena75191e2013-01-02 14:53:20 -070015 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070021 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
22 GPIO_ACTIVE_HIGH>;
Stephen Warrena75191e2013-01-02 14:53:20 -070023 };
24 };
25
Stephen Warren58ecb232013-11-25 17:53:16 -070026 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060027 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>;
29
30 state_default: pinmux {
31 ata {
32 nvidia,pins = "ata";
33 nvidia,function = "ide";
34 };
35 atb {
36 nvidia,pins = "atb", "gma", "gme";
37 nvidia,function = "sdio4";
38 };
39 atc {
40 nvidia,pins = "atc";
41 nvidia,function = "nand";
42 };
43 atd {
44 nvidia,pins = "atd", "ate", "gmb", "spia",
45 "spib", "spic";
46 nvidia,function = "gmi";
47 };
48 cdev1 {
49 nvidia,pins = "cdev1";
50 nvidia,function = "plla_out";
51 };
52 cdev2 {
53 nvidia,pins = "cdev2";
54 nvidia,function = "pllp_out4";
55 };
56 crtp {
57 nvidia,pins = "crtp", "lm1";
58 nvidia,function = "crt";
59 };
60 csus {
61 nvidia,pins = "csus";
62 nvidia,function = "vi_sensor_clk";
63 };
64 dap1 {
65 nvidia,pins = "dap1";
66 nvidia,function = "dap1";
67 };
68 dap2 {
69 nvidia,pins = "dap2";
70 nvidia,function = "dap2";
71 };
72 dap3 {
73 nvidia,pins = "dap3";
74 nvidia,function = "dap3";
75 };
76 dap4 {
77 nvidia,pins = "dap4";
78 nvidia,function = "dap4";
79 };
Stephen Warrenecc295b2012-03-15 16:27:36 -060080 dta {
81 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
82 nvidia,function = "vi";
83 };
84 dtf {
85 nvidia,pins = "dtf";
86 nvidia,function = "i2c3";
87 };
88 gmc {
89 nvidia,pins = "gmc";
90 nvidia,function = "uartd";
91 };
92 gmd {
93 nvidia,pins = "gmd";
94 nvidia,function = "sflash";
95 };
96 gpu {
97 nvidia,pins = "gpu";
98 nvidia,function = "pwm";
99 };
100 gpu7 {
101 nvidia,pins = "gpu7";
102 nvidia,function = "rtck";
103 };
104 gpv {
105 nvidia,pins = "gpv", "slxa", "slxk";
106 nvidia,function = "pcie";
107 };
108 hdint {
109 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
Stephen Warren802a8492012-04-26 11:21:54 -0600110 "lsck", "lsda";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600111 nvidia,function = "hdmi";
112 };
113 i2cp {
114 nvidia,pins = "i2cp";
115 nvidia,function = "i2cp";
116 };
117 irrx {
118 nvidia,pins = "irrx", "irtx";
119 nvidia,function = "uartb";
120 };
121 kbca {
122 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
123 "kbce", "kbcf";
124 nvidia,function = "kbc";
125 };
126 lcsn {
127 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
128 "lsdi", "lvp0";
129 nvidia,function = "rsvd4";
130 };
131 ld0 {
132 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
133 "ld5", "ld6", "ld7", "ld8", "ld9",
134 "ld10", "ld11", "ld12", "ld13", "ld14",
135 "ld15", "ld16", "ld17", "ldi", "lhp0",
136 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
137 "lspi", "lvp1", "lvs";
138 nvidia,function = "displaya";
139 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600140 owc {
141 nvidia,pins = "owc", "spdi", "spdo", "uac";
142 nvidia,function = "rsvd2";
143 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600144 pmc {
145 nvidia,pins = "pmc";
146 nvidia,function = "pwr_on";
147 };
148 rm {
149 nvidia,pins = "rm";
150 nvidia,function = "i2c1";
151 };
152 sdb {
153 nvidia,pins = "sdb", "sdc", "sdd";
154 nvidia,function = "sdio3";
155 };
156 sdio1 {
157 nvidia,pins = "sdio1";
158 nvidia,function = "sdio1";
159 };
160 slxc {
161 nvidia,pins = "slxc", "slxd";
162 nvidia,function = "spdif";
163 };
164 spid {
165 nvidia,pins = "spid", "spie", "spif";
166 nvidia,function = "spi1";
167 };
168 spig {
169 nvidia,pins = "spig", "spih";
170 nvidia,function = "spi2_alt";
171 };
172 uaa {
173 nvidia,pins = "uaa", "uab", "uda";
174 nvidia,function = "ulpi";
175 };
176 uad {
177 nvidia,pins = "uad";
178 nvidia,function = "irda";
179 };
180 uca {
181 nvidia,pins = "uca", "ucb";
182 nvidia,function = "uartc";
183 };
184 conf_ata {
185 nvidia,pins = "ata", "atb", "atc", "atd",
186 "cdev1", "cdev2", "dap1", "dap2",
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600187 "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
Stephen Warrenecc295b2012-03-15 16:27:36 -0600188 "gme", "gpu", "gpu7", "i2cp", "irrx",
189 "irtx", "pta", "rm", "sdc", "sdd",
190 "slxd", "slxk", "spdi", "spdo", "uac",
191 "uad", "uca", "ucb", "uda";
192 nvidia,pull = <0>;
193 nvidia,tristate = <0>;
194 };
195 conf_ate {
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600196 nvidia,pins = "ate", "csus", "dap3",
Stephen Warrenecc295b2012-03-15 16:27:36 -0600197 "gpv", "owc", "slxc", "spib", "spid",
198 "spie";
199 nvidia,pull = <0>;
200 nvidia,tristate = <1>;
201 };
202 conf_ck32 {
203 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
204 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
205 nvidia,pull = <0>;
206 };
207 conf_crtp {
208 nvidia,pins = "crtp", "gmb", "slxa", "spia",
209 "spig", "spih";
210 nvidia,pull = <2>;
211 nvidia,tristate = <1>;
212 };
213 conf_dta {
214 nvidia,pins = "dta", "dtb", "dtc", "dtd";
215 nvidia,pull = <1>;
216 nvidia,tristate = <0>;
217 };
218 conf_dte {
219 nvidia,pins = "dte", "spif";
220 nvidia,pull = <1>;
221 nvidia,tristate = <1>;
222 };
223 conf_hdint {
224 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
225 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
226 "lvp0";
227 nvidia,tristate = <1>;
228 };
229 conf_kbca {
230 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
231 "kbce", "kbcf", "sdio1", "spic", "uaa",
232 "uab";
233 nvidia,pull = <2>;
234 nvidia,tristate = <0>;
235 };
236 conf_lc {
237 nvidia,pins = "lc", "ls";
238 nvidia,pull = <2>;
239 };
240 conf_ld0 {
241 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
242 "ld5", "ld6", "ld7", "ld8", "ld9",
243 "ld10", "ld11", "ld12", "ld13", "ld14",
244 "ld15", "ld16", "ld17", "ldi", "lhp0",
245 "lhp1", "lhp2", "lhs", "lm0", "lpp",
246 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
247 "lvs", "pmc", "sdb";
248 nvidia,tristate = <0>;
249 };
250 conf_ld17_0 {
251 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
252 "ld23_22";
253 nvidia,pull = <1>;
254 };
255 drive_sdio1 {
256 nvidia,pins = "drive_sdio1";
257 nvidia,high-speed-mode = <0>;
258 nvidia,schmitt = <0>;
259 nvidia,low-power-mode = <3>;
260 nvidia,pull-down-strength = <31>;
261 nvidia,pull-up-strength = <31>;
262 nvidia,slew-rate-rising = <3>;
263 nvidia,slew-rate-falling = <3>;
264 };
265 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600266
267 state_i2cmux_ddc: pinmux_i2cmux_ddc {
268 ddc {
269 nvidia,pins = "ddc";
270 nvidia,function = "i2c2";
271 };
272 pta {
273 nvidia,pins = "pta";
274 nvidia,function = "rsvd4";
275 };
276 };
277
278 state_i2cmux_pta: pinmux_i2cmux_pta {
279 ddc {
280 nvidia,pins = "ddc";
281 nvidia,function = "rsvd4";
282 };
283 pta {
284 nvidia,pins = "pta";
285 nvidia,function = "i2c2";
286 };
287 };
288
289 state_i2cmux_idle: pinmux_i2cmux_idle {
290 ddc {
291 nvidia,pins = "ddc";
292 nvidia,function = "rsvd4";
293 };
294 pta {
295 nvidia,pins = "pta";
296 nvidia,function = "rsvd4";
297 };
298 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600299 };
300
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600301 i2s@70002800 {
302 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600303 };
304
305 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600306 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600307 };
308
Stephen Warren88950f3b2011-11-21 14:44:09 -0700309 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600310 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700311 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700312
313 wm8903: wm8903@1a {
314 compatible = "wlf,wm8903";
315 reg = <0x1a>;
316 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700317 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren797acf72012-01-11 16:09:57 -0700318
319 gpio-controller;
320 #gpio-cells = <2>;
321
322 micdet-cfg = <0>;
323 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600324 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700325 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530326
327 /* ALS and proximity sensor */
328 isl29018@44 {
329 compatible = "isil,isl29018";
330 reg = <0x44>;
331 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700332 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530333 };
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000334
335 gyrometer@68 {
336 compatible = "invn,mpu3050";
337 reg = <0x68>;
338 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700339 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000340 };
Stephen Warren88950f3b2011-11-21 14:44:09 -0700341 };
342
343 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600344 status = "okay";
Stephen Warren22bd1f72012-04-26 11:19:03 -0600345 clock-frequency = <100000>;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700346 };
347
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600348 i2cmux {
349 compatible = "i2c-mux-pinctrl";
350 #address-cells = <1>;
351 #size-cells = <0>;
352
353 i2c-parent = <&{/i2c@7000c400}>;
354
355 pinctrl-names = "ddc", "pta", "idle";
356 pinctrl-0 = <&state_i2cmux_ddc>;
357 pinctrl-1 = <&state_i2cmux_pta>;
358 pinctrl-2 = <&state_i2cmux_idle>;
359
Stephen Warrena75191e2013-01-02 14:53:20 -0700360 hdmi_ddc: i2c@0 {
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600361 reg = <0>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 };
365
366 i2c@1 {
367 reg = <1>;
368 #address-cells = <1>;
369 #size-cells = <0>;
Stephen Warren0879c5f2012-04-25 16:57:28 -0600370
371 smart-battery@b {
372 compatible = "ti,bq20z75", "smart-battery-1.1";
373 reg = <0xb>;
374 ti,i2c-retry-count = <2>;
375 ti,poll-retry-count = <10>;
376 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600377 };
378 };
379
Stephen Warren88950f3b2011-11-21 14:44:09 -0700380 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600381 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700382 clock-frequency = <400000>;
383 };
384
385 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600386 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700387 clock-frequency = <400000>;
Stephen Warren401c9a52011-12-17 23:29:32 -0700388
Stephen Warren6529e632012-06-20 15:58:34 -0600389 pmic: tps6586x@34 {
390 compatible = "ti,tps6586x";
391 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700392 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600393
Stephen Warren44b12ef2012-09-11 11:42:26 -0600394 ti,system-power-controller;
395
Stephen Warren6529e632012-06-20 15:58:34 -0600396 #gpio-cells = <2>;
397 gpio-controller;
398
399 sys-supply = <&vdd_5v0_reg>;
400 vin-sm0-supply = <&sys_reg>;
401 vin-sm1-supply = <&sys_reg>;
402 vin-sm2-supply = <&sys_reg>;
403 vinldo01-supply = <&sm2_reg>;
404 vinldo23-supply = <&sm2_reg>;
405 vinldo4-supply = <&sm2_reg>;
406 vinldo678-supply = <&sm2_reg>;
407 vinldo9-supply = <&sm2_reg>;
408
409 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600410 sys_reg: sys {
Stephen Warren6529e632012-06-20 15:58:34 -0600411 regulator-name = "vdd_sys";
412 regulator-always-on;
413 };
414
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600415 sm0 {
Stephen Warren6529e632012-06-20 15:58:34 -0600416 regulator-name = "vdd_sm0,vdd_core";
417 regulator-min-microvolt = <1300000>;
418 regulator-max-microvolt = <1300000>;
419 regulator-always-on;
420 };
421
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600422 sm1 {
Stephen Warren6529e632012-06-20 15:58:34 -0600423 regulator-name = "vdd_sm1,vdd_cpu";
424 regulator-min-microvolt = <1125000>;
425 regulator-max-microvolt = <1125000>;
426 regulator-always-on;
427 };
428
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600429 sm2_reg: sm2 {
Stephen Warren6529e632012-06-20 15:58:34 -0600430 regulator-name = "vdd_sm2,vin_ldo*";
431 regulator-min-microvolt = <3700000>;
432 regulator-max-microvolt = <3700000>;
433 regulator-always-on;
434 };
435
436 /* LDO0 is not connected to anything */
437
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600438 ldo1 {
Stephen Warren6529e632012-06-20 15:58:34 -0600439 regulator-name = "vdd_ldo1,avdd_pll*";
440 regulator-min-microvolt = <1100000>;
441 regulator-max-microvolt = <1100000>;
442 regulator-always-on;
443 };
444
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600445 ldo2 {
Stephen Warren6529e632012-06-20 15:58:34 -0600446 regulator-name = "vdd_ldo2,vdd_rtc";
447 regulator-min-microvolt = <1200000>;
448 regulator-max-microvolt = <1200000>;
449 };
450
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600451 ldo3 {
Stephen Warren6529e632012-06-20 15:58:34 -0600452 regulator-name = "vdd_ldo3,avdd_usb*";
453 regulator-min-microvolt = <3300000>;
454 regulator-max-microvolt = <3300000>;
455 regulator-always-on;
456 };
457
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600458 ldo4 {
Stephen Warren6529e632012-06-20 15:58:34 -0600459 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
460 regulator-min-microvolt = <1800000>;
461 regulator-max-microvolt = <1800000>;
462 regulator-always-on;
463 };
464
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600465 ldo5 {
Stephen Warren6529e632012-06-20 15:58:34 -0600466 regulator-name = "vdd_ldo5,vcore_mmc";
467 regulator-min-microvolt = <2850000>;
468 regulator-max-microvolt = <2850000>;
469 regulator-always-on;
470 };
471
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600472 ldo6 {
Stephen Warren6529e632012-06-20 15:58:34 -0600473 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
474 regulator-min-microvolt = <1800000>;
475 regulator-max-microvolt = <1800000>;
476 };
477
Stephen Warrena75191e2013-01-02 14:53:20 -0700478 hdmi_vdd_reg: ldo7 {
Stephen Warren6529e632012-06-20 15:58:34 -0600479 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
480 regulator-min-microvolt = <3300000>;
481 regulator-max-microvolt = <3300000>;
482 };
483
Stephen Warrena75191e2013-01-02 14:53:20 -0700484 hdmi_pll_reg: ldo8 {
Stephen Warren6529e632012-06-20 15:58:34 -0600485 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
486 regulator-min-microvolt = <1800000>;
487 regulator-max-microvolt = <1800000>;
488 };
489
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600490 ldo9 {
Stephen Warren6529e632012-06-20 15:58:34 -0600491 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
492 regulator-min-microvolt = <2850000>;
493 regulator-max-microvolt = <2850000>;
494 regulator-always-on;
495 };
496
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600497 ldo_rtc {
Stephen Warren6529e632012-06-20 15:58:34 -0600498 regulator-name = "vdd_rtc_out,vdd_cell";
499 regulator-min-microvolt = <3300000>;
500 regulator-max-microvolt = <3300000>;
501 regulator-always-on;
502 };
503 };
504 };
505
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000506 temperature-sensor@4c {
Stephen Warren98462102012-11-19 15:34:44 -0700507 compatible = "onnn,nct1008";
Stephen Warren401c9a52011-12-17 23:29:32 -0700508 reg = <0x4c>;
509 };
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000510
511 magnetometer@c {
Stephen Warren98462102012-11-19 15:34:44 -0700512 compatible = "ak,ak8975";
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000513 reg = <0xc>;
514 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700515 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000516 };
Stephen Warren88950f3b2011-11-21 14:44:09 -0700517 };
518
Stephen Warren58ecb232013-11-25 17:53:16 -0700519 pmc@7000e400 {
Stephen Warren6529e632012-06-20 15:58:34 -0600520 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800521 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800522 nvidia,cpu-pwr-good-time = <5000>;
523 nvidia,cpu-pwr-off-time = <5000>;
524 nvidia,core-pwr-good-time = <3845 3845>;
525 nvidia,core-pwr-off-time = <3875>;
526 nvidia,sys-clock-req-active-high;
Stephen Warren6529e632012-06-20 15:58:34 -0600527 };
528
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600529 memory-controller@7000f400 {
Olof Johanssond8017a92011-10-18 11:06:06 -0700530 emc-table@190000 {
Stephen Warren95decf82012-05-11 16:11:38 -0600531 reg = <190000>;
Olof Johanssond8017a92011-10-18 11:06:06 -0700532 compatible = "nvidia,tegra20-emc-table";
Stephen Warren95decf82012-05-11 16:11:38 -0600533 clock-frequency = <190000>;
534 nvidia,emc-registers = <0x0000000c 0x00000026
Olof Johanssond8017a92011-10-18 11:06:06 -0700535 0x00000009 0x00000003 0x00000004 0x00000004
536 0x00000002 0x0000000c 0x00000003 0x00000003
537 0x00000002 0x00000001 0x00000004 0x00000005
538 0x00000004 0x00000009 0x0000000d 0x0000059f
539 0x00000000 0x00000003 0x00000003 0x00000003
540 0x00000003 0x00000001 0x0000000b 0x000000c8
541 0x00000003 0x00000007 0x00000004 0x0000000f
542 0x00000002 0x00000000 0x00000000 0x00000002
543 0x00000000 0x00000000 0x00000083 0xa06204ae
544 0x007dc010 0x00000000 0x00000000 0x00000000
Stephen Warren95decf82012-05-11 16:11:38 -0600545 0x00000000 0x00000000 0x00000000 0x00000000>;
Olof Johanssond8017a92011-10-18 11:06:06 -0700546 };
547
548 emc-table@380000 {
Stephen Warren95decf82012-05-11 16:11:38 -0600549 reg = <380000>;
Olof Johanssond8017a92011-10-18 11:06:06 -0700550 compatible = "nvidia,tegra20-emc-table";
Stephen Warren95decf82012-05-11 16:11:38 -0600551 clock-frequency = <380000>;
552 nvidia,emc-registers = <0x00000017 0x0000004b
Olof Johanssond8017a92011-10-18 11:06:06 -0700553 0x00000012 0x00000006 0x00000004 0x00000005
554 0x00000003 0x0000000c 0x00000006 0x00000006
555 0x00000003 0x00000001 0x00000004 0x00000005
556 0x00000004 0x00000009 0x0000000d 0x00000b5f
557 0x00000000 0x00000003 0x00000003 0x00000006
558 0x00000006 0x00000001 0x00000011 0x000000c8
559 0x00000003 0x0000000e 0x00000007 0x0000000f
560 0x00000002 0x00000000 0x00000000 0x00000002
561 0x00000000 0x00000000 0x00000083 0xe044048b
562 0x007d8010 0x00000000 0x00000000 0x00000000
Stephen Warren95decf82012-05-11 16:11:38 -0600563 0x00000000 0x00000000 0x00000000 0x00000000>;
Olof Johanssond8017a92011-10-18 11:06:06 -0700564 };
565 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600566
Stephen Warrenc04abb32012-05-11 17:03:26 -0600567 usb@c5000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600568 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600569 dr_mode = "otg";
570 };
571
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530572 usb-phy@c5000000 {
573 status = "okay";
574 vbus-supply = <&vbus_reg>;
575 dr_mode = "otg";
576 };
577
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600578 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600579 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700580 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
581 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530582 };
583
584 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530585 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700586 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
587 GPIO_ACTIVE_LOW>;
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600588 };
Stephen Warrenc04abb32012-05-11 17:03:26 -0600589
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600590 usb@c5008000 {
591 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600592 };
593
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530594 usb-phy@c5008000 {
595 status = "okay";
596 };
597
Wei Nida2fc652012-09-21 16:54:57 +0800598 sdhci@c8000000 {
599 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700600 power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
Wei Nida2fc652012-09-21 16:54:57 +0800601 bus-width = <4>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600602 keep-power-in-suspend;
Wei Nida2fc652012-09-21 16:54:57 +0800603 };
604
Stephen Warrenc04abb32012-05-11 17:03:26 -0600605 sdhci@c8000400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600606 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700607 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
608 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
609 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400610 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600611 };
612
613 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600614 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400615 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600616 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600617 };
618
Joseph Lo7021d122013-04-03 19:31:27 +0800619 clocks {
620 compatible = "simple-bus";
621 #address-cells = <1>;
622 #size-cells = <0>;
623
Stephen Warren58ecb232013-11-25 17:53:16 -0700624 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800625 compatible = "fixed-clock";
626 reg=<0>;
627 #clock-cells = <0>;
628 clock-frequency = <32768>;
629 };
630 };
631
Stephen Warrenc04abb32012-05-11 17:03:26 -0600632 gpio-keys {
633 compatible = "gpio-keys";
634
635 power {
636 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700637 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600638 linux,code = <116>; /* KEY_POWER */
639 gpio-key,wakeup;
640 };
641
642 lid {
643 label = "Lid";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700644 gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600645 linux,input-type = <5>; /* EV_SW */
646 linux,code = <0>; /* SW_LID */
647 debounce-interval = <1>;
648 gpio-key,wakeup;
649 };
650 };
651
Stephen Warren58ecb232013-11-25 17:53:16 -0700652 kbc@7000e200 {
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530653 status = "okay";
654 nvidia,debounce-delay-ms = <32>;
655 nvidia,repeat-delay-ms = <160>;
656 nvidia,ghost-filter;
657 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
658 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
659 linux,keymap = <0x00020011 /* KEY_W */
660 0x0003001F /* KEY_S */
661 0x0004001E /* KEY_A */
662 0x0005002C /* KEY_Z */
663 0x000701d0 /* KEY_FN */
664
665 0x0107007D /* KEY_LEFTMETA */
666 0x02060064 /* KEY_RIGHTALT */
667 0x02070038 /* KEY_LEFTALT */
668
669 0x03000006 /* KEY_5 */
670 0x03010005 /* KEY_4 */
671 0x03020013 /* KEY_R */
672 0x03030012 /* KEY_E */
673 0x03040021 /* KEY_F */
674 0x03050020 /* KEY_D */
675 0x0306002D /* KEY_X */
676
677 0x04000008 /* KEY_7 */
678 0x04010007 /* KEY_6 */
679 0x04020014 /* KEY_T */
680 0x04030023 /* KEY_H */
681 0x04040022 /* KEY_G */
682 0x0405002F /* KEY_V */
683 0x0406002E /* KEY_C */
684 0x04070039 /* KEY_SPACE */
685
686 0x0500000A /* KEY_9 */
687 0x05010009 /* KEY_8 */
688 0x05020016 /* KEY_U */
689 0x05030015 /* KEY_Y */
690 0x05040024 /* KEY_J */
691 0x05050031 /* KEY_N */
692 0x05060030 /* KEY_B */
693 0x0507002B /* KEY_BACKSLASH */
694
695 0x0600000C /* KEY_MINUS */
696 0x0601000B /* KEY_0 */
697 0x06020018 /* KEY_O */
698 0x06030017 /* KEY_I */
699 0x06040026 /* KEY_L */
700 0x06050025 /* KEY_K */
701 0x06060033 /* KEY_COMMA */
702 0x06070032 /* KEY_M */
703
704 0x0701000D /* KEY_EQUAL */
705 0x0702001B /* KEY_RIGHTBRACE */
706 0x0703001C /* KEY_ENTER */
707 0x0707008B /* KEY_MENU */
708
709 0x08040036 /* KEY_RIGHTSHIFT */
710 0x0805002A /* KEY_LEFTSHIFT */
711
712 0x09050061 /* KEY_RIGHTCTRL */
713 0x0907001D /* KEY_LEFTCTRL */
714
715 0x0B00001A /* KEY_LEFTBRACE */
716 0x0B010019 /* KEY_P */
717 0x0B020028 /* KEY_APOSTROPHE */
718 0x0B030027 /* KEY_SEMICOLON */
719 0x0B040035 /* KEY_SLASH */
720 0x0B050034 /* KEY_DOT */
721
722 0x0C000044 /* KEY_F10 */
723 0x0C010043 /* KEY_F9 */
724 0x0C02000E /* KEY_BACKSPACE */
725 0x0C030004 /* KEY_3 */
726 0x0C040003 /* KEY_2 */
727 0x0C050067 /* KEY_UP */
728 0x0C0600D2 /* KEY_PRINT */
729 0x0C070077 /* KEY_PAUSE */
730
731 0x0D00006E /* KEY_INSERT */
732 0x0D01006F /* KEY_DELETE */
733 0x0D030068 /* KEY_PAGEUP */
734 0x0D04006D /* KEY_PAGEDOWN */
735 0x0D05006A /* KEY_RIGHT */
736 0x0D06006C /* KEY_DOWN */
737 0x0D070069 /* KEY_LEFT */
738
739 0x0E000057 /* KEY_F11 */
740 0x0E010058 /* KEY_F12 */
741 0x0E020042 /* KEY_F8 */
742 0x0E030010 /* KEY_Q */
743 0x0E04003E /* KEY_F4 */
744 0x0E05003D /* KEY_F3 */
745 0x0E060002 /* KEY_1 */
746 0x0E070041 /* KEY_F7 */
747
748 0x0F000001 /* KEY_ESC */
749 0x0F010029 /* KEY_GRAVE */
750 0x0F02003F /* KEY_F5 */
751 0x0F03000F /* KEY_TAB */
752 0x0F04003B /* KEY_F1 */
753 0x0F05003C /* KEY_F2 */
754 0x0F06003A /* KEY_CAPSLOCK */
755 0x0F070040 /* KEY_F6 */
756
757 /* Software Handled Function Keys */
758 0x14000047 /* KEY_KP7 */
759
760 0x15000049 /* KEY_KP9 */
761 0x15010048 /* KEY_KP8 */
762 0x1502004B /* KEY_KP4 */
763 0x1504004F /* KEY_KP1 */
764
765 0x1601004E /* KEY_KPSLASH */
766 0x1602004D /* KEY_KP6 */
767 0x1603004C /* KEY_KP5 */
768 0x16040051 /* KEY_KP3 */
769 0x16050050 /* KEY_KP2 */
770 0x16070052 /* KEY_KP0 */
771
772 0x1B010037 /* KEY_KPASTERISK */
773 0x1B03004A /* KEY_KPMINUS */
774 0x1B04004E /* KEY_KPPLUS */
775 0x1B050053 /* KEY_KPDOT */
776
777 0x1C050073 /* KEY_VOLUMEUP */
778
779 0x1D030066 /* KEY_HOME */
780 0x1D04006B /* KEY_END */
781 0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
782 0x1D060072 /* KEY_VOLUMEDOWN */
783 0x1D0700E1 /* KEY_BRIGHTNESSUP */
784
785 0x1E000045 /* KEY_NUMLOCK */
786 0x1E010046 /* KEY_SCROLLLOCK */
787 0x1E020071 /* KEY_MUTE */
788
789 0x1F04008A>; /* KEY_HELP */
790 };
Stephen Warren6529e632012-06-20 15:58:34 -0600791 regulators {
792 compatible = "simple-bus";
793 #address-cells = <1>;
794 #size-cells = <0>;
795
796 vdd_5v0_reg: regulator@0 {
797 compatible = "regulator-fixed";
798 reg = <0>;
799 regulator-name = "vdd_5v0";
800 regulator-min-microvolt = <5000000>;
801 regulator-max-microvolt = <5000000>;
802 regulator-always-on;
803 };
804
805 regulator@1 {
806 compatible = "regulator-fixed";
807 reg = <1>;
808 regulator-name = "vdd_1v5";
809 regulator-min-microvolt = <1500000>;
810 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700811 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600812 };
813
814 regulator@2 {
815 compatible = "regulator-fixed";
816 reg = <2>;
817 regulator-name = "vdd_1v2";
818 regulator-min-microvolt = <1200000>;
819 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700820 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600821 enable-active-high;
822 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530823
824 vbus_reg: regulator@3 {
825 compatible = "regulator-fixed";
826 reg = <3>;
827 regulator-name = "vdd_vbus_wup1";
828 regulator-min-microvolt = <5000000>;
829 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600830 enable-active-high;
Stephen Warren23f95ef2013-08-01 12:26:01 -0600831 gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
Stephen Warren30ca2222013-08-20 14:00:13 -0600832 regulator-always-on;
833 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530834 };
Stephen Warren6529e632012-06-20 15:58:34 -0600835 };
836
Stephen Warrenc04abb32012-05-11 17:03:26 -0600837 sound {
838 compatible = "nvidia,tegra-audio-wm8903-seaboard",
839 "nvidia,tegra-audio-wm8903";
840 nvidia,model = "NVIDIA Tegra Seaboard";
841
842 nvidia,audio-routing =
843 "Headphone Jack", "HPOUTR",
844 "Headphone Jack", "HPOUTL",
845 "Int Spk", "ROP",
846 "Int Spk", "RON",
847 "Int Spk", "LOP",
848 "Int Spk", "LON",
849 "Mic Jack", "MICBIAS",
850 "IN1R", "Mic Jack";
851
852 nvidia,i2s-controller = <&tegra_i2s1>;
853 nvidia,audio-codec = <&wm8903>;
854
Stephen Warren3325f1b2013-02-12 17:25:15 -0700855 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
856 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600857
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300858 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
859 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
860 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600861 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600862 };
Grant Likely8e267f32011-07-19 17:26:54 -0600863};