Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 1 | /* |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 2 | * Copyright 2012 Red Hat Inc. |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 25 | #include <core/client.h> |
| 26 | #include <core/handle.h> |
| 27 | #include <core/namedb.h> |
| 28 | #include <core/gpuobj.h> |
| 29 | #include <core/engctx.h> |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 30 | #include <core/event.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 31 | #include <core/class.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 32 | #include <core/enum.h> |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 33 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 34 | #include <subdev/timer.h> |
| 35 | #include <subdev/bar.h> |
Ben Skeggs | 5222555 | 2013-12-23 01:51:16 +1000 | [diff] [blame] | 36 | #include <subdev/fb.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 37 | #include <subdev/vm.h> |
| 38 | |
| 39 | #include <engine/dmaobj.h> |
Ben Skeggs | 02a841d | 2012-07-04 23:44:54 +1000 | [diff] [blame] | 40 | #include <engine/fifo.h> |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 41 | |
| 42 | struct nvc0_fifo_priv { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 43 | struct nouveau_fifo base; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 44 | |
| 45 | struct work_struct fault; |
| 46 | u64 mask; |
| 47 | |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 48 | struct { |
| 49 | struct nouveau_gpuobj *mem[2]; |
| 50 | int active; |
| 51 | wait_queue_head_t wait; |
| 52 | } runlist; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 53 | |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 54 | struct { |
| 55 | struct nouveau_gpuobj *mem; |
| 56 | struct nouveau_vma bar; |
| 57 | } user; |
Ben Skeggs | ec9c088 | 2010-12-31 12:10:49 +1000 | [diff] [blame] | 58 | int spoon_nr; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 59 | }; |
| 60 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 61 | struct nvc0_fifo_base { |
| 62 | struct nouveau_fifo_base base; |
| 63 | struct nouveau_gpuobj *pgd; |
| 64 | struct nouveau_vm *vm; |
| 65 | }; |
| 66 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 67 | struct nvc0_fifo_chan { |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 68 | struct nouveau_fifo_chan base; |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 69 | enum { |
| 70 | STOPPED, |
| 71 | RUNNING, |
| 72 | KILLED |
| 73 | } state; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 74 | }; |
| 75 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 76 | /******************************************************************************* |
| 77 | * FIFO channel objects |
| 78 | ******************************************************************************/ |
| 79 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 80 | static void |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 81 | nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 82 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 83 | struct nouveau_bar *bar = nouveau_bar(priv); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 84 | struct nouveau_gpuobj *cur; |
| 85 | int i, p; |
| 86 | |
Ben Skeggs | fadb171 | 2013-05-13 10:02:11 +1000 | [diff] [blame] | 87 | mutex_lock(&nv_subdev(priv)->mutex); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 88 | cur = priv->runlist.mem[priv->runlist.active]; |
| 89 | priv->runlist.active = !priv->runlist.active; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 90 | |
| 91 | for (i = 0, p = 0; i < 128; i++) { |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 92 | struct nvc0_fifo_chan *chan = (void *)priv->base.channel[i]; |
| 93 | if (chan && chan->state == RUNNING) { |
| 94 | nv_wo32(cur, p + 0, i); |
| 95 | nv_wo32(cur, p + 4, 0x00000004); |
| 96 | p += 8; |
| 97 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 98 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 99 | bar->flush(bar); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 100 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 101 | nv_wr32(priv, 0x002270, cur->addr >> 12); |
| 102 | nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3)); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 103 | |
Ben Skeggs | 3cf6290 | 2014-02-22 01:05:01 +1000 | [diff] [blame] | 104 | if (wait_event_timeout(priv->runlist.wait, |
| 105 | !(nv_rd32(priv, 0x00227c) & 0x00100000), |
| 106 | msecs_to_jiffies(2000)) == 0) |
| 107 | nv_error(priv, "runlist update timeout\n"); |
Ben Skeggs | fadb171 | 2013-05-13 10:02:11 +1000 | [diff] [blame] | 108 | mutex_unlock(&nv_subdev(priv)->mutex); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 109 | } |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 110 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 111 | static int |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 112 | nvc0_fifo_context_attach(struct nouveau_object *parent, |
| 113 | struct nouveau_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 114 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 115 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 116 | struct nvc0_fifo_base *base = (void *)parent->parent; |
| 117 | struct nouveau_engctx *ectx = (void *)object; |
| 118 | u32 addr; |
| 119 | int ret; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 120 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 121 | switch (nv_engidx(object->engine)) { |
| 122 | case NVDEV_ENGINE_SW : return 0; |
| 123 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 124 | case NVDEV_ENGINE_COPY0: addr = 0x0230; break; |
| 125 | case NVDEV_ENGINE_COPY1: addr = 0x0240; break; |
Maarten Lankhorst | 23c14ed | 2012-11-23 11:08:23 +1000 | [diff] [blame] | 126 | case NVDEV_ENGINE_BSP : addr = 0x0270; break; |
| 127 | case NVDEV_ENGINE_VP : addr = 0x0250; break; |
| 128 | case NVDEV_ENGINE_PPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 129 | default: |
| 130 | return -EINVAL; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 131 | } |
| 132 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 133 | if (!ectx->vma.node) { |
| 134 | ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, |
| 135 | NV_MEM_ACCESS_RW, &ectx->vma); |
| 136 | if (ret) |
| 137 | return ret; |
Ben Skeggs | 4c2d422 | 2012-08-10 15:10:34 +1000 | [diff] [blame] | 138 | |
| 139 | nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 140 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 141 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 142 | nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); |
| 143 | nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); |
| 144 | bar->flush(bar); |
| 145 | return 0; |
| 146 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 147 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 148 | static int |
| 149 | nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, |
| 150 | struct nouveau_object *object) |
| 151 | { |
| 152 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 153 | struct nvc0_fifo_priv *priv = (void *)parent->engine; |
| 154 | struct nvc0_fifo_base *base = (void *)parent->parent; |
| 155 | struct nvc0_fifo_chan *chan = (void *)parent; |
| 156 | u32 addr; |
| 157 | |
| 158 | switch (nv_engidx(object->engine)) { |
| 159 | case NVDEV_ENGINE_SW : return 0; |
| 160 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 161 | case NVDEV_ENGINE_COPY0: addr = 0x0230; break; |
| 162 | case NVDEV_ENGINE_COPY1: addr = 0x0240; break; |
Maarten Lankhorst | 23c14ed | 2012-11-23 11:08:23 +1000 | [diff] [blame] | 163 | case NVDEV_ENGINE_BSP : addr = 0x0270; break; |
| 164 | case NVDEV_ENGINE_VP : addr = 0x0250; break; |
| 165 | case NVDEV_ENGINE_PPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 166 | default: |
| 167 | return -EINVAL; |
| 168 | } |
| 169 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 170 | nv_wr32(priv, 0x002634, chan->base.chid); |
| 171 | if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 172 | nv_error(priv, "channel %d [%s] kick timeout\n", |
| 173 | chan->base.chid, nouveau_client_name(chan)); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 174 | if (suspend) |
| 175 | return -EBUSY; |
| 176 | } |
| 177 | |
Ben Skeggs | edc260d | 2012-11-27 11:05:36 +1000 | [diff] [blame] | 178 | nv_wo32(base, addr + 0x00, 0x00000000); |
| 179 | nv_wo32(base, addr + 0x04, 0x00000000); |
| 180 | bar->flush(bar); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 181 | return 0; |
| 182 | } |
| 183 | |
| 184 | static int |
| 185 | nvc0_fifo_chan_ctor(struct nouveau_object *parent, |
| 186 | struct nouveau_object *engine, |
| 187 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 188 | struct nouveau_object **pobject) |
| 189 | { |
| 190 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 191 | struct nvc0_fifo_priv *priv = (void *)engine; |
| 192 | struct nvc0_fifo_base *base = (void *)parent; |
| 193 | struct nvc0_fifo_chan *chan; |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 194 | struct nv50_channel_ind_class *args = data; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 195 | u64 usermem, ioffset, ilength; |
| 196 | int ret, i; |
| 197 | |
| 198 | if (size < sizeof(*args)) |
| 199 | return -EINVAL; |
| 200 | |
| 201 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, |
| 202 | priv->user.bar.offset, 0x1000, |
| 203 | args->pushbuf, |
Martin Peres | 507ceb1 | 2012-11-27 00:30:32 +0100 | [diff] [blame] | 204 | (1ULL << NVDEV_ENGINE_SW) | |
| 205 | (1ULL << NVDEV_ENGINE_GR) | |
| 206 | (1ULL << NVDEV_ENGINE_COPY0) | |
| 207 | (1ULL << NVDEV_ENGINE_COPY1) | |
| 208 | (1ULL << NVDEV_ENGINE_BSP) | |
| 209 | (1ULL << NVDEV_ENGINE_VP) | |
| 210 | (1ULL << NVDEV_ENGINE_PPP), &chan); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 211 | *pobject = nv_object(chan); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 212 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 213 | return ret; |
| 214 | |
| 215 | nv_parent(chan)->context_attach = nvc0_fifo_context_attach; |
| 216 | nv_parent(chan)->context_detach = nvc0_fifo_context_detach; |
| 217 | |
| 218 | usermem = chan->base.chid * 0x1000; |
| 219 | ioffset = args->ioffset; |
Ilia Mirkin | 57be046 | 2013-07-27 00:27:00 -0400 | [diff] [blame] | 220 | ilength = order_base_2(args->ilength / 8); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 221 | |
| 222 | for (i = 0; i < 0x1000; i += 4) |
| 223 | nv_wo32(priv->user.mem, usermem + i, 0x00000000); |
| 224 | |
| 225 | nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem)); |
| 226 | nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem)); |
| 227 | nv_wo32(base, 0x10, 0x0000face); |
| 228 | nv_wo32(base, 0x30, 0xfffff902); |
| 229 | nv_wo32(base, 0x48, lower_32_bits(ioffset)); |
| 230 | nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); |
| 231 | nv_wo32(base, 0x54, 0x00000002); |
| 232 | nv_wo32(base, 0x84, 0x20400000); |
| 233 | nv_wo32(base, 0x94, 0x30000001); |
| 234 | nv_wo32(base, 0x9c, 0x00000100); |
| 235 | nv_wo32(base, 0xa4, 0x1f1f1f1f); |
| 236 | nv_wo32(base, 0xa8, 0x1f1f1f1f); |
| 237 | nv_wo32(base, 0xac, 0x0000001f); |
| 238 | nv_wo32(base, 0xb8, 0xf8000000); |
| 239 | nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */ |
| 240 | nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */ |
| 241 | bar->flush(bar); |
| 242 | return 0; |
| 243 | } |
| 244 | |
| 245 | static int |
| 246 | nvc0_fifo_chan_init(struct nouveau_object *object) |
| 247 | { |
| 248 | struct nouveau_gpuobj *base = nv_gpuobj(object->parent); |
| 249 | struct nvc0_fifo_priv *priv = (void *)object->engine; |
| 250 | struct nvc0_fifo_chan *chan = (void *)object; |
| 251 | u32 chid = chan->base.chid; |
| 252 | int ret; |
| 253 | |
| 254 | ret = nouveau_fifo_channel_init(&chan->base); |
| 255 | if (ret) |
| 256 | return ret; |
| 257 | |
| 258 | nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 259 | |
| 260 | if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { |
| 261 | nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001); |
| 262 | nvc0_fifo_runlist_update(priv); |
| 263 | } |
| 264 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 265 | return 0; |
| 266 | } |
| 267 | |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 268 | static void nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv); |
| 269 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 270 | static int |
| 271 | nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend) |
| 272 | { |
| 273 | struct nvc0_fifo_priv *priv = (void *)object->engine; |
| 274 | struct nvc0_fifo_chan *chan = (void *)object; |
| 275 | u32 chid = chan->base.chid; |
| 276 | |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 277 | if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { |
| 278 | nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000); |
| 279 | nvc0_fifo_runlist_update(priv); |
| 280 | } |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 281 | |
| 282 | nvc0_fifo_intr_engine(priv); |
| 283 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 284 | nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 285 | return nouveau_fifo_channel_fini(&chan->base, suspend); |
| 286 | } |
| 287 | |
| 288 | static struct nouveau_ofuncs |
| 289 | nvc0_fifo_ofuncs = { |
| 290 | .ctor = nvc0_fifo_chan_ctor, |
| 291 | .dtor = _nouveau_fifo_channel_dtor, |
| 292 | .init = nvc0_fifo_chan_init, |
| 293 | .fini = nvc0_fifo_chan_fini, |
| 294 | .rd32 = _nouveau_fifo_channel_rd32, |
| 295 | .wr32 = _nouveau_fifo_channel_wr32, |
| 296 | }; |
| 297 | |
| 298 | static struct nouveau_oclass |
| 299 | nvc0_fifo_sclass[] = { |
Ben Skeggs | c97f8c9 | 2012-08-19 16:03:00 +1000 | [diff] [blame] | 300 | { NVC0_CHANNEL_IND_CLASS, &nvc0_fifo_ofuncs }, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 301 | {} |
| 302 | }; |
| 303 | |
| 304 | /******************************************************************************* |
| 305 | * FIFO context - instmem heap and vm setup |
| 306 | ******************************************************************************/ |
| 307 | |
| 308 | static int |
| 309 | nvc0_fifo_context_ctor(struct nouveau_object *parent, |
| 310 | struct nouveau_object *engine, |
| 311 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 312 | struct nouveau_object **pobject) |
| 313 | { |
| 314 | struct nvc0_fifo_base *base; |
| 315 | int ret; |
| 316 | |
| 317 | ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, |
| 318 | 0x1000, NVOBJ_FLAG_ZERO_ALLOC | |
| 319 | NVOBJ_FLAG_HEAP, &base); |
| 320 | *pobject = nv_object(base); |
| 321 | if (ret) |
| 322 | return ret; |
| 323 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 324 | ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, |
| 325 | &base->pgd); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 326 | if (ret) |
| 327 | return ret; |
| 328 | |
| 329 | nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr)); |
| 330 | nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr)); |
| 331 | nv_wo32(base, 0x0208, 0xffffffff); |
| 332 | nv_wo32(base, 0x020c, 0x000000ff); |
| 333 | |
| 334 | ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); |
| 335 | if (ret) |
| 336 | return ret; |
| 337 | |
| 338 | return 0; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 339 | } |
| 340 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 341 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 342 | nvc0_fifo_context_dtor(struct nouveau_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 343 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 344 | struct nvc0_fifo_base *base = (void *)object; |
| 345 | nouveau_vm_ref(NULL, &base->vm, base->pgd); |
| 346 | nouveau_gpuobj_ref(NULL, &base->pgd); |
| 347 | nouveau_fifo_context_destroy(&base->base); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 348 | } |
| 349 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 350 | static struct nouveau_oclass |
| 351 | nvc0_fifo_cclass = { |
| 352 | .handle = NV_ENGCTX(FIFO, 0xc0), |
| 353 | .ofuncs = &(struct nouveau_ofuncs) { |
| 354 | .ctor = nvc0_fifo_context_ctor, |
| 355 | .dtor = nvc0_fifo_context_dtor, |
| 356 | .init = _nouveau_fifo_context_init, |
| 357 | .fini = _nouveau_fifo_context_fini, |
| 358 | .rd32 = _nouveau_fifo_context_rd32, |
| 359 | .wr32 = _nouveau_fifo_context_wr32, |
| 360 | }, |
| 361 | }; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 362 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 363 | /******************************************************************************* |
| 364 | * PFIFO engine |
| 365 | ******************************************************************************/ |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 366 | |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 367 | static inline int |
| 368 | nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn) |
| 369 | { |
| 370 | switch (engn) { |
| 371 | case NVDEV_ENGINE_GR : engn = 0; break; |
| 372 | case NVDEV_ENGINE_BSP : engn = 1; break; |
| 373 | case NVDEV_ENGINE_PPP : engn = 2; break; |
| 374 | case NVDEV_ENGINE_VP : engn = 3; break; |
| 375 | case NVDEV_ENGINE_COPY0: engn = 4; break; |
| 376 | case NVDEV_ENGINE_COPY1: engn = 5; break; |
| 377 | default: |
| 378 | return -1; |
| 379 | } |
| 380 | |
| 381 | return engn; |
| 382 | } |
| 383 | |
| 384 | static inline struct nouveau_engine * |
| 385 | nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn) |
| 386 | { |
| 387 | switch (engn) { |
| 388 | case 0: engn = NVDEV_ENGINE_GR; break; |
| 389 | case 1: engn = NVDEV_ENGINE_BSP; break; |
| 390 | case 2: engn = NVDEV_ENGINE_PPP; break; |
| 391 | case 3: engn = NVDEV_ENGINE_VP; break; |
| 392 | case 4: engn = NVDEV_ENGINE_COPY0; break; |
| 393 | case 5: engn = NVDEV_ENGINE_COPY1; break; |
| 394 | default: |
| 395 | return NULL; |
| 396 | } |
| 397 | |
| 398 | return nouveau_engine(priv, engn); |
| 399 | } |
| 400 | |
| 401 | static void |
| 402 | nvc0_fifo_recover_work(struct work_struct *work) |
| 403 | { |
| 404 | struct nvc0_fifo_priv *priv = container_of(work, typeof(*priv), fault); |
| 405 | struct nouveau_object *engine; |
| 406 | unsigned long flags; |
| 407 | u32 engn, engm = 0; |
| 408 | u64 mask, todo; |
| 409 | |
| 410 | spin_lock_irqsave(&priv->base.lock, flags); |
| 411 | mask = priv->mask; |
| 412 | priv->mask = 0ULL; |
| 413 | spin_unlock_irqrestore(&priv->base.lock, flags); |
| 414 | |
| 415 | for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) |
| 416 | engm |= 1 << nvc0_fifo_engidx(priv, engn); |
| 417 | nv_mask(priv, 0x002630, engm, engm); |
| 418 | |
| 419 | for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { |
| 420 | if ((engine = (void *)nouveau_engine(priv, engn))) { |
| 421 | nv_ofuncs(engine)->fini(engine, false); |
| 422 | WARN_ON(nv_ofuncs(engine)->init(engine)); |
| 423 | } |
| 424 | } |
| 425 | |
| 426 | nvc0_fifo_runlist_update(priv); |
| 427 | nv_wr32(priv, 0x00262c, engm); |
| 428 | nv_mask(priv, 0x002630, engm, 0x00000000); |
| 429 | } |
| 430 | |
| 431 | static void |
| 432 | nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine, |
| 433 | struct nvc0_fifo_chan *chan) |
| 434 | { |
| 435 | struct nouveau_object *engobj = nv_object(engine); |
| 436 | u32 chid = chan->base.chid; |
| 437 | unsigned long flags; |
| 438 | |
| 439 | nv_error(priv, "%s engine fault on channel %d, recovering...\n", |
| 440 | nv_subdev(engine)->name, chid); |
| 441 | |
| 442 | nv_mask(priv, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); |
| 443 | chan->state = KILLED; |
| 444 | |
| 445 | spin_lock_irqsave(&priv->base.lock, flags); |
| 446 | priv->mask |= 1ULL << nv_engidx(engobj); |
| 447 | spin_unlock_irqrestore(&priv->base.lock, flags); |
| 448 | schedule_work(&priv->fault); |
| 449 | } |
| 450 | |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 451 | static int |
| 452 | nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) |
| 453 | { |
| 454 | struct nvc0_fifo_chan *chan = NULL; |
| 455 | struct nouveau_handle *bind; |
| 456 | unsigned long flags; |
| 457 | int ret = -EINVAL; |
| 458 | |
| 459 | spin_lock_irqsave(&priv->base.lock, flags); |
| 460 | if (likely(chid >= priv->base.min && chid <= priv->base.max)) |
| 461 | chan = (void *)priv->base.channel[chid]; |
| 462 | if (unlikely(!chan)) |
| 463 | goto out; |
| 464 | |
| 465 | bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e); |
| 466 | if (likely(bind)) { |
| 467 | if (!mthd || !nv_call(bind->object, mthd, data)) |
| 468 | ret = 0; |
| 469 | nouveau_namedb_put(bind); |
| 470 | } |
| 471 | |
| 472 | out: |
| 473 | spin_unlock_irqrestore(&priv->base.lock, flags); |
| 474 | return ret; |
| 475 | } |
| 476 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 477 | static const struct nouveau_enum |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 478 | nvc0_fifo_sched_reason[] = { |
| 479 | { 0x0a, "CTXSW_TIMEOUT" }, |
| 480 | {} |
| 481 | }; |
| 482 | |
| 483 | static void |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame^] | 484 | nvc0_fifo_intr_sched_ctxsw(struct nvc0_fifo_priv *priv) |
| 485 | { |
| 486 | struct nouveau_engine *engine; |
| 487 | struct nvc0_fifo_chan *chan; |
| 488 | u32 engn; |
| 489 | |
| 490 | for (engn = 0; engn < 6; engn++) { |
| 491 | u32 stat = nv_rd32(priv, 0x002640 + (engn * 0x04)); |
| 492 | u32 busy = (stat & 0x80000000); |
| 493 | u32 save = (stat & 0x00100000); /* maybe? */ |
| 494 | u32 unk0 = (stat & 0x00040000); |
| 495 | u32 unk1 = (stat & 0x00001000); |
| 496 | u32 chid = (stat & 0x0000007f); |
| 497 | (void)save; |
| 498 | |
| 499 | if (busy && unk0 && unk1) { |
| 500 | if (!(chan = (void *)priv->base.channel[chid])) |
| 501 | continue; |
| 502 | if (!(engine = nvc0_fifo_engine(priv, engn))) |
| 503 | continue; |
| 504 | nvc0_fifo_recover(priv, engine, chan); |
| 505 | } |
| 506 | } |
| 507 | } |
| 508 | |
| 509 | static void |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 510 | nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv) |
| 511 | { |
| 512 | u32 intr = nv_rd32(priv, 0x00254c); |
| 513 | u32 code = intr & 0x000000ff; |
| 514 | const struct nouveau_enum *en; |
| 515 | char enunk[6] = ""; |
| 516 | |
| 517 | en = nouveau_enum_find(nvc0_fifo_sched_reason, code); |
| 518 | if (!en) |
| 519 | snprintf(enunk, sizeof(enunk), "UNK%02x", code); |
| 520 | |
| 521 | nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame^] | 522 | |
| 523 | switch (code) { |
| 524 | case 0x0a: |
| 525 | nvc0_fifo_intr_sched_ctxsw(priv); |
| 526 | break; |
| 527 | default: |
| 528 | break; |
| 529 | } |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 530 | } |
| 531 | |
| 532 | static const struct nouveau_enum |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 533 | nvc0_fifo_fault_engine[] = { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 534 | { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 535 | { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB }, |
| 536 | { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, |
| 537 | { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 538 | { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO }, |
| 539 | { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP }, |
| 540 | { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 541 | { 0x13, "PCOUNTER" }, |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 542 | { 0x14, "PVP", NULL, NVDEV_ENGINE_VP }, |
| 543 | { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 }, |
| 544 | { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 545 | { 0x17, "PDAEMON" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 546 | {} |
| 547 | }; |
| 548 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 549 | static const struct nouveau_enum |
| 550 | nvc0_fifo_fault_reason[] = { |
Ben Skeggs | e296663 | 2011-03-29 08:57:34 +1000 | [diff] [blame] | 551 | { 0x00, "PT_NOT_PRESENT" }, |
| 552 | { 0x01, "PT_TOO_SHORT" }, |
| 553 | { 0x02, "PAGE_NOT_PRESENT" }, |
| 554 | { 0x03, "VM_LIMIT_EXCEEDED" }, |
| 555 | { 0x04, "NO_CHANNEL" }, |
| 556 | { 0x05, "PAGE_SYSTEM_ONLY" }, |
| 557 | { 0x06, "PAGE_READ_ONLY" }, |
| 558 | { 0x0a, "COMPRESSED_SYSRAM" }, |
| 559 | { 0x0c, "INVALID_STORAGE_TYPE" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 560 | {} |
| 561 | }; |
| 562 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 563 | static const struct nouveau_enum |
| 564 | nvc0_fifo_fault_hubclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 565 | { 0x01, "PCOPY0" }, |
| 566 | { 0x02, "PCOPY1" }, |
| 567 | { 0x04, "DISPATCH" }, |
| 568 | { 0x05, "CTXCTL" }, |
| 569 | { 0x06, "PFIFO" }, |
| 570 | { 0x07, "BAR_READ" }, |
| 571 | { 0x08, "BAR_WRITE" }, |
| 572 | { 0x0b, "PVP" }, |
| 573 | { 0x0c, "PPPP" }, |
| 574 | { 0x0d, "PBSP" }, |
| 575 | { 0x11, "PCOUNTER" }, |
| 576 | { 0x12, "PDAEMON" }, |
| 577 | { 0x14, "CCACHE" }, |
| 578 | { 0x15, "CCACHE_POST" }, |
| 579 | {} |
| 580 | }; |
| 581 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 582 | static const struct nouveau_enum |
| 583 | nvc0_fifo_fault_gpcclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 584 | { 0x01, "TEX" }, |
| 585 | { 0x0c, "ESETUP" }, |
| 586 | { 0x0e, "CTXCTL" }, |
| 587 | { 0x0f, "PROP" }, |
| 588 | {} |
| 589 | }; |
| 590 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 591 | static void |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 592 | nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 593 | { |
Ben Skeggs | b3ccd34 | 2012-09-06 20:26:38 -0400 | [diff] [blame] | 594 | u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); |
| 595 | u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); |
| 596 | u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10)); |
| 597 | u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10)); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 598 | u32 gpc = (stat & 0x1f000000) >> 24; |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 599 | u32 client = (stat & 0x00001f00) >> 8; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 600 | u32 write = (stat & 0x00000080); |
| 601 | u32 hub = (stat & 0x00000040); |
| 602 | u32 reason = (stat & 0x0000000f); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 603 | struct nouveau_object *engctx = NULL, *object; |
| 604 | struct nouveau_engine *engine = NULL; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 605 | const struct nouveau_enum *er, *eu, *ec; |
| 606 | char erunk[6] = ""; |
| 607 | char euunk[6] = ""; |
| 608 | char ecunk[6] = ""; |
| 609 | char gpcid[3] = ""; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 610 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 611 | er = nouveau_enum_find(nvc0_fifo_fault_reason, reason); |
| 612 | if (!er) |
| 613 | snprintf(erunk, sizeof(erunk), "UNK%02X", reason); |
| 614 | |
| 615 | eu = nouveau_enum_find(nvc0_fifo_fault_engine, unit); |
| 616 | if (eu) { |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 617 | switch (eu->data2) { |
| 618 | case NVDEV_SUBDEV_BAR: |
| 619 | nv_mask(priv, 0x001704, 0x00000000, 0x00000000); |
| 620 | break; |
| 621 | case NVDEV_SUBDEV_INSTMEM: |
| 622 | nv_mask(priv, 0x001714, 0x00000000, 0x00000000); |
| 623 | break; |
| 624 | case NVDEV_ENGINE_IFB: |
| 625 | nv_mask(priv, 0x001718, 0x00000000, 0x00000000); |
| 626 | break; |
| 627 | default: |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 628 | engine = nouveau_engine(priv, eu->data2); |
| 629 | if (engine) |
| 630 | engctx = nouveau_engctx_get(engine, inst); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 631 | break; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 632 | } |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 633 | } else { |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 634 | snprintf(euunk, sizeof(euunk), "UNK%02x", unit); |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 635 | } |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 636 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 637 | if (hub) { |
| 638 | ec = nouveau_enum_find(nvc0_fifo_fault_hubclient, client); |
| 639 | } else { |
| 640 | ec = nouveau_enum_find(nvc0_fifo_fault_gpcclient, client); |
| 641 | snprintf(gpcid, sizeof(gpcid), "%d", gpc); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 642 | } |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 643 | |
| 644 | if (!ec) |
| 645 | snprintf(ecunk, sizeof(ecunk), "UNK%02x", client); |
| 646 | |
| 647 | nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on " |
| 648 | "channel 0x%010llx [%s]\n", write ? "write" : "read", |
| 649 | (u64)vahi << 32 | valo, er ? er->name : erunk, |
| 650 | eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/", |
| 651 | ec ? ec->name : ecunk, (u64)inst << 12, |
| 652 | nouveau_client_name(engctx)); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 653 | |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 654 | object = engctx; |
| 655 | while (object) { |
| 656 | switch (nv_mclass(object)) { |
| 657 | case NVC0_CHANNEL_IND_CLASS: |
| 658 | nvc0_fifo_recover(priv, engine, (void *)object); |
| 659 | break; |
| 660 | } |
| 661 | object = object->parent; |
| 662 | } |
| 663 | |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 664 | nouveau_engctx_put(engctx); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 665 | } |
| 666 | |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 667 | static const struct nouveau_bitfield |
| 668 | nvc0_fifo_pbdma_intr[] = { |
| 669 | /* { 0x00008000, "" } seen with null ib push */ |
| 670 | { 0x00200000, "ILLEGAL_MTHD" }, |
| 671 | { 0x00800000, "EMPTY_SUBC" }, |
| 672 | {} |
| 673 | }; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 674 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 675 | static void |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 676 | nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 677 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 678 | u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); |
| 679 | u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); |
| 680 | u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000)); |
| 681 | u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f; |
| 682 | u32 subc = (addr & 0x00070000) >> 16; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 683 | u32 mthd = (addr & 0x00003ffc); |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 684 | u32 show = stat; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 685 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 686 | if (stat & 0x00800000) { |
| 687 | if (!nvc0_fifo_swmthd(priv, chid, mthd, data)) |
| 688 | show &= ~0x00800000; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 689 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 690 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 691 | if (show) { |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 692 | nv_error(priv, "PBDMA%d:", unit); |
| 693 | nouveau_bitfield_print(nvc0_fifo_pbdma_intr, show); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 694 | pr_cont("\n"); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 695 | nv_error(priv, |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 696 | "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 697 | unit, chid, |
| 698 | nouveau_client_name_for_fifo_chid(&priv->base, chid), |
| 699 | subc, mthd, data); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 700 | } |
| 701 | |
| 702 | nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); |
| 703 | nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 704 | } |
| 705 | |
| 706 | static void |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 707 | nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv) |
| 708 | { |
| 709 | u32 intr = nv_rd32(priv, 0x002a00); |
| 710 | |
| 711 | if (intr & 0x10000000) { |
| 712 | wake_up(&priv->runlist.wait); |
| 713 | nv_wr32(priv, 0x002a00, 0x10000000); |
| 714 | intr &= ~0x10000000; |
| 715 | } |
| 716 | |
| 717 | if (intr) { |
| 718 | nv_error(priv, "RUNLIST 0x%08x\n", intr); |
| 719 | nv_wr32(priv, 0x002a00, intr); |
| 720 | } |
| 721 | } |
| 722 | |
| 723 | static void |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 724 | nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn) |
| 725 | { |
| 726 | u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04)); |
| 727 | u32 inte = nv_rd32(priv, 0x002628); |
| 728 | u32 unkn; |
| 729 | |
| 730 | for (unkn = 0; unkn < 8; unkn++) { |
| 731 | u32 ints = (intr >> (unkn * 0x04)) & inte; |
| 732 | if (ints & 0x1) { |
| 733 | nouveau_event_trigger(priv->base.uevent, 0); |
| 734 | ints &= ~1; |
| 735 | } |
| 736 | if (ints) { |
| 737 | nv_error(priv, "ENGINE %d %d %01x", engn, unkn, ints); |
| 738 | nv_mask(priv, 0x002628, ints, 0); |
| 739 | } |
| 740 | } |
| 741 | |
| 742 | nv_wr32(priv, 0x0025a8 + (engn * 0x04), intr); |
| 743 | } |
| 744 | |
| 745 | static void |
| 746 | nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv) |
| 747 | { |
| 748 | u32 mask = nv_rd32(priv, 0x0025a4); |
| 749 | while (mask) { |
| 750 | u32 unit = __ffs(mask); |
| 751 | nvc0_fifo_intr_engine_unit(priv, unit); |
| 752 | mask &= ~(1 << unit); |
| 753 | } |
| 754 | } |
| 755 | |
| 756 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 757 | nvc0_fifo_intr(struct nouveau_subdev *subdev) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 758 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 759 | struct nvc0_fifo_priv *priv = (void *)subdev; |
| 760 | u32 mask = nv_rd32(priv, 0x002140); |
| 761 | u32 stat = nv_rd32(priv, 0x002100) & mask; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 762 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 763 | if (stat & 0x00000001) { |
| 764 | u32 intr = nv_rd32(priv, 0x00252c); |
| 765 | nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr); |
| 766 | nv_wr32(priv, 0x002100, 0x00000001); |
| 767 | stat &= ~0x00000001; |
| 768 | } |
| 769 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 770 | if (stat & 0x00000100) { |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 771 | nvc0_fifo_intr_sched(priv); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 772 | nv_wr32(priv, 0x002100, 0x00000100); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 773 | stat &= ~0x00000100; |
| 774 | } |
| 775 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 776 | if (stat & 0x00010000) { |
| 777 | u32 intr = nv_rd32(priv, 0x00256c); |
| 778 | nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr); |
| 779 | nv_wr32(priv, 0x002100, 0x00010000); |
| 780 | stat &= ~0x00010000; |
| 781 | } |
| 782 | |
| 783 | if (stat & 0x01000000) { |
| 784 | u32 intr = nv_rd32(priv, 0x00258c); |
| 785 | nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr); |
| 786 | nv_wr32(priv, 0x002100, 0x01000000); |
| 787 | stat &= ~0x01000000; |
| 788 | } |
| 789 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 790 | if (stat & 0x10000000) { |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 791 | u32 mask = nv_rd32(priv, 0x00259c); |
| 792 | while (mask) { |
| 793 | u32 unit = __ffs(mask); |
| 794 | nvc0_fifo_intr_fault(priv, unit); |
| 795 | nv_wr32(priv, 0x00259c, (1 << unit)); |
| 796 | mask &= ~(1 << unit); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 797 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 798 | stat &= ~0x10000000; |
| 799 | } |
| 800 | |
| 801 | if (stat & 0x20000000) { |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 802 | u32 mask = nv_rd32(priv, 0x0025a0); |
| 803 | while (mask) { |
| 804 | u32 unit = __ffs(mask); |
| 805 | nvc0_fifo_intr_pbdma(priv, unit); |
| 806 | nv_wr32(priv, 0x0025a0, (1 << unit)); |
| 807 | mask &= ~(1 << unit); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 808 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 809 | stat &= ~0x20000000; |
| 810 | } |
| 811 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 812 | if (stat & 0x40000000) { |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 813 | nvc0_fifo_intr_runlist(priv); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 814 | stat &= ~0x40000000; |
| 815 | } |
| 816 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 817 | if (stat & 0x80000000) { |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 818 | nvc0_fifo_intr_engine(priv); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 819 | stat &= ~0x80000000; |
| 820 | } |
| 821 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 822 | if (stat) { |
Ben Skeggs | 22a7a27 | 2014-02-22 00:19:19 +1000 | [diff] [blame] | 823 | nv_error(priv, "INTR 0x%08x\n", stat); |
| 824 | nv_mask(priv, 0x002140, stat, 0x00000000); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 825 | nv_wr32(priv, 0x002100, stat); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 826 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 827 | } |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 828 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 829 | static void |
| 830 | nvc0_fifo_uevent_enable(struct nouveau_event *event, int index) |
| 831 | { |
| 832 | struct nvc0_fifo_priv *priv = event->priv; |
| 833 | nv_mask(priv, 0x002140, 0x80000000, 0x80000000); |
| 834 | } |
| 835 | |
| 836 | static void |
| 837 | nvc0_fifo_uevent_disable(struct nouveau_event *event, int index) |
| 838 | { |
| 839 | struct nvc0_fifo_priv *priv = event->priv; |
| 840 | nv_mask(priv, 0x002140, 0x80000000, 0x00000000); |
| 841 | } |
| 842 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 843 | static int |
| 844 | nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 845 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 846 | struct nouveau_object **pobject) |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 847 | { |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 848 | struct nvc0_fifo_priv *priv; |
| 849 | int ret; |
| 850 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 851 | ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv); |
| 852 | *pobject = nv_object(priv); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 853 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 854 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 855 | |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 856 | INIT_WORK(&priv->fault, nvc0_fifo_recover_work); |
| 857 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 858 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 859 | &priv->runlist.mem[0]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 860 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 861 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 862 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 863 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 864 | &priv->runlist.mem[1]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 865 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 866 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 867 | |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 868 | init_waitqueue_head(&priv->runlist.wait); |
| 869 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 870 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 871 | &priv->user.mem); |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 872 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 873 | return ret; |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 874 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 875 | ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, |
| 876 | &priv->user.bar); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 877 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 878 | return ret; |
| 879 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 880 | priv->base.uevent->enable = nvc0_fifo_uevent_enable; |
| 881 | priv->base.uevent->disable = nvc0_fifo_uevent_disable; |
| 882 | priv->base.uevent->priv = priv; |
| 883 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 884 | nv_subdev(priv)->unit = 0x00000100; |
| 885 | nv_subdev(priv)->intr = nvc0_fifo_intr; |
| 886 | nv_engine(priv)->cclass = &nvc0_fifo_cclass; |
| 887 | nv_engine(priv)->sclass = nvc0_fifo_sclass; |
| 888 | return 0; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 889 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 890 | |
| 891 | static void |
| 892 | nvc0_fifo_dtor(struct nouveau_object *object) |
| 893 | { |
| 894 | struct nvc0_fifo_priv *priv = (void *)object; |
| 895 | |
| 896 | nouveau_gpuobj_unmap(&priv->user.bar); |
| 897 | nouveau_gpuobj_ref(NULL, &priv->user.mem); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 898 | nouveau_gpuobj_ref(NULL, &priv->runlist.mem[0]); |
| 899 | nouveau_gpuobj_ref(NULL, &priv->runlist.mem[1]); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 900 | |
| 901 | nouveau_fifo_destroy(&priv->base); |
| 902 | } |
| 903 | |
| 904 | static int |
| 905 | nvc0_fifo_init(struct nouveau_object *object) |
| 906 | { |
| 907 | struct nvc0_fifo_priv *priv = (void *)object; |
| 908 | int ret, i; |
| 909 | |
| 910 | ret = nouveau_fifo_init(&priv->base); |
| 911 | if (ret) |
| 912 | return ret; |
| 913 | |
| 914 | nv_wr32(priv, 0x000204, 0xffffffff); |
| 915 | nv_wr32(priv, 0x002204, 0xffffffff); |
| 916 | |
| 917 | priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204)); |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 918 | nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 919 | |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 920 | /* assign engines to PBDMAs */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 921 | if (priv->spoon_nr >= 3) { |
| 922 | nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */ |
| 923 | nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */ |
| 924 | nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */ |
| 925 | nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */ |
| 926 | nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */ |
| 927 | nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */ |
| 928 | } |
| 929 | |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 930 | /* PBDMA[n] */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 931 | for (i = 0; i < priv->spoon_nr; i++) { |
| 932 | nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); |
| 933 | nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ |
| 934 | nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ |
| 935 | } |
| 936 | |
| 937 | nv_mask(priv, 0x002200, 0x00000001, 0x00000001); |
| 938 | nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12); |
| 939 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 940 | nv_wr32(priv, 0x002100, 0xffffffff); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 941 | nv_wr32(priv, 0x002140, 0x7fffffff); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 942 | nv_wr32(priv, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 943 | return 0; |
| 944 | } |
| 945 | |
Ben Skeggs | 16c4f22 | 2013-11-05 14:26:58 +1000 | [diff] [blame] | 946 | struct nouveau_oclass * |
| 947 | nvc0_fifo_oclass = &(struct nouveau_oclass) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 948 | .handle = NV_ENGINE(FIFO, 0xc0), |
| 949 | .ofuncs = &(struct nouveau_ofuncs) { |
| 950 | .ctor = nvc0_fifo_ctor, |
| 951 | .dtor = nvc0_fifo_dtor, |
| 952 | .init = nvc0_fifo_init, |
| 953 | .fini = _nouveau_fifo_fini, |
| 954 | }, |
| 955 | }; |