blob: ba8227e92bd19753cf188e69eb2e018c5fd63e21 [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
Shawn Guoce4c6f92012-05-04 14:32:35 +080017 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +080023 saif0 = &saif0;
24 saif1 = &saif1;
Fabio Estevam80d969e2012-06-15 12:35:56 -030025 serial0 = &auart0;
26 serial1 = &auart1;
27 serial2 = &auart2;
28 serial3 = &auart3;
29 serial4 = &auart4;
Shawn Guoce4c6f92012-05-04 14:32:35 +080030 };
31
Dong Aishengbc3a59c2012-03-31 21:26:57 +080032 cpus {
33 cpu@0 {
34 compatible = "arm,arm926ejs";
35 };
36 };
37
38 apb@80000000 {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 reg = <0x80000000 0x80000>;
43 ranges;
44
45 apbh@80000000 {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <0x80000000 0x3c900>;
50 ranges;
51
52 icoll: interrupt-controller@80000000 {
53 compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
54 interrupt-controller;
55 #interrupt-cells = <1>;
56 reg = <0x80000000 0x2000>;
57 };
58
59 hsadc@80002000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -030060 reg = <0x80002000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080061 interrupts = <13 87>;
62 status = "disabled";
63 };
64
65 dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +080066 compatible = "fsl,imx28-dma-apbh";
Fabio Estevam0f06cde2012-07-30 21:29:19 -030067 reg = <0x80004000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080068 };
69
70 perfmon@80006000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -030071 reg = <0x80006000 0x800>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080072 interrupts = <27>;
73 status = "disabled";
74 };
75
Huang Shijie7a8e5142012-05-25 17:25:35 +080076 gpmi-nand@8000c000 {
77 compatible = "fsl,imx28-gpmi-nand";
78 #address-cells = <1>;
79 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -030080 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijie7a8e5142012-05-25 17:25:35 +080081 reg-names = "gpmi-nand", "bch";
82 interrupts = <88>, <41>;
83 interrupt-names = "gpmi-dma", "bch";
84 fsl,gpmi-dma-channel = <4>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080085 status = "disabled";
86 };
87
88 ssp0: ssp@80010000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -030089 reg = <0x80010000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080090 interrupts = <96 82>;
Shawn Guo35d23042012-05-06 16:33:34 +080091 fsl,ssp-dma-channel = <0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080092 status = "disabled";
93 };
94
95 ssp1: ssp@80012000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -030096 reg = <0x80012000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080097 interrupts = <97 83>;
Shawn Guo35d23042012-05-06 16:33:34 +080098 fsl,ssp-dma-channel = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080099 status = "disabled";
100 };
101
102 ssp2: ssp@80014000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300103 reg = <0x80014000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800104 interrupts = <98 84>;
Shawn Guo35d23042012-05-06 16:33:34 +0800105 fsl,ssp-dma-channel = <2>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800106 status = "disabled";
107 };
108
109 ssp3: ssp@80016000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300110 reg = <0x80016000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800111 interrupts = <99 85>;
Shawn Guo35d23042012-05-06 16:33:34 +0800112 fsl,ssp-dma-channel = <3>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800113 status = "disabled";
114 };
115
116 pinctrl@80018000 {
117 #address-cells = <1>;
118 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800119 compatible = "fsl,imx28-pinctrl", "simple-bus";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300120 reg = <0x80018000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800121
Shawn Guoce4c6f92012-05-04 14:32:35 +0800122 gpio0: gpio@0 {
123 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
124 interrupts = <127>;
125 gpio-controller;
126 #gpio-cells = <2>;
127 interrupt-controller;
128 #interrupt-cells = <2>;
129 };
130
131 gpio1: gpio@1 {
132 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
133 interrupts = <126>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
138 };
139
140 gpio2: gpio@2 {
141 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
142 interrupts = <125>;
143 gpio-controller;
144 #gpio-cells = <2>;
145 interrupt-controller;
146 #interrupt-cells = <2>;
147 };
148
149 gpio3: gpio@3 {
150 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
151 interrupts = <124>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 interrupt-controller;
155 #interrupt-cells = <2>;
156 };
157
158 gpio4: gpio@4 {
159 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
160 interrupts = <123>;
161 gpio-controller;
162 #gpio-cells = <2>;
163 interrupt-controller;
164 #interrupt-cells = <2>;
165 };
166
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800167 duart_pins_a: duart@0 {
168 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800169 fsl,pinmux-ids = <
170 0x3102 /* MX28_PAD_PWM0__DUART_RX */
171 0x3112 /* MX28_PAD_PWM1__DUART_TX */
172 >;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800173 fsl,drive-strength = <0>;
174 fsl,voltage = <1>;
175 fsl,pull-up = <0>;
176 };
177
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200178 duart_pins_b: duart@1 {
179 reg = <1>;
Shawn Guof14da762012-06-28 11:44:57 +0800180 fsl,pinmux-ids = <
181 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
182 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
183 >;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200184 fsl,drive-strength = <0>;
185 fsl,voltage = <1>;
186 fsl,pull-up = <0>;
187 };
188
Shawn Guoe1a4d182012-07-09 12:34:35 +0800189 duart_4pins_a: duart-4pins@0 {
190 reg = <0>;
191 fsl,pinmux-ids = <
192 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
193 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
194 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
195 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
196 >;
197 fsl,drive-strength = <0>;
198 fsl,voltage = <1>;
199 fsl,pull-up = <0>;
200 };
201
Huang Shijie7a8e5142012-05-25 17:25:35 +0800202 gpmi_pins_a: gpmi-nand@0 {
203 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800204 fsl,pinmux-ids = <
205 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
206 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
207 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
208 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
209 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
210 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
211 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
212 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
213 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
Shawn Guof14da762012-06-28 11:44:57 +0800214 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
Shawn Guof14da762012-06-28 11:44:57 +0800215 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
216 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
217 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
218 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
219 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
220 >;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800221 fsl,drive-strength = <0>;
222 fsl,voltage = <1>;
223 fsl,pull-up = <0>;
224 };
225
226 gpmi_status_cfg: gpmi-status-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800227 fsl,pinmux-ids = <
228 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
229 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
230 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
231 >;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800232 fsl,drive-strength = <2>;
233 };
234
Fabio Estevam80d969e2012-06-15 12:35:56 -0300235 auart0_pins_a: auart0@0 {
236 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800237 fsl,pinmux-ids = <
238 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
239 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
240 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
241 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
242 >;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300243 fsl,drive-strength = <0>;
244 fsl,voltage = <1>;
245 fsl,pull-up = <0>;
246 };
247
Marek Vasut8fa62e12012-07-07 21:21:38 +0800248 auart0_2pins_a: auart0-2pins@0 {
249 reg = <0>;
250 fsl,pinmux-ids = <
251 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
252 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
253 >;
254 fsl,drive-strength = <0>;
255 fsl,voltage = <1>;
256 fsl,pull-up = <0>;
257 };
258
Shawn Guoe1a4d182012-07-09 12:34:35 +0800259 auart1_pins_a: auart1@0 {
260 reg = <0>;
261 fsl,pinmux-ids = <
262 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
263 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
264 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
265 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
266 >;
267 fsl,drive-strength = <0>;
268 fsl,voltage = <1>;
269 fsl,pull-up = <0>;
270 };
271
Shawn Guo3143bbb2012-07-07 23:12:03 +0800272 auart1_2pins_a: auart1-2pins@0 {
273 reg = <0>;
274 fsl,pinmux-ids = <
275 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
276 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
277 >;
278 fsl,drive-strength = <0>;
279 fsl,voltage = <1>;
280 fsl,pull-up = <0>;
281 };
282
283 auart2_2pins_a: auart2-2pins@0 {
284 reg = <0>;
285 fsl,pinmux-ids = <
286 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
287 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
288 >;
289 fsl,drive-strength = <0>;
290 fsl,voltage = <1>;
291 fsl,pull-up = <0>;
292 };
293
Fabio Estevam80d969e2012-06-15 12:35:56 -0300294 auart3_pins_a: auart3@0 {
295 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800296 fsl,pinmux-ids = <
297 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
298 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
299 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
300 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
301 >;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300302 fsl,drive-strength = <0>;
303 fsl,voltage = <1>;
304 fsl,pull-up = <0>;
305 };
306
Shawn Guo3143bbb2012-07-07 23:12:03 +0800307 auart3_2pins_a: auart3-2pins@0 {
308 reg = <0>;
309 fsl,pinmux-ids = <
310 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
311 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
312 >;
313 fsl,drive-strength = <0>;
314 fsl,voltage = <1>;
315 fsl,pull-up = <0>;
316 };
317
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800318 mac0_pins_a: mac0@0 {
319 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800320 fsl,pinmux-ids = <
321 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
322 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
323 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
324 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
325 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
326 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
327 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
328 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
329 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
330 >;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800331 fsl,drive-strength = <1>;
332 fsl,voltage = <1>;
333 fsl,pull-up = <1>;
334 };
335
336 mac1_pins_a: mac1@0 {
337 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800338 fsl,pinmux-ids = <
339 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
340 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
341 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
342 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
343 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
344 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
345 >;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800346 fsl,drive-strength = <1>;
347 fsl,voltage = <1>;
348 fsl,pull-up = <1>;
349 };
Shawn Guo35d23042012-05-06 16:33:34 +0800350
351 mmc0_8bit_pins_a: mmc0-8bit@0 {
352 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800353 fsl,pinmux-ids = <
354 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
355 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
356 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
357 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
358 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
359 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
360 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
361 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
362 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
363 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
364 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
365 >;
Shawn Guo35d23042012-05-06 16:33:34 +0800366 fsl,drive-strength = <1>;
367 fsl,voltage = <1>;
368 fsl,pull-up = <1>;
369 };
370
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200371 mmc0_4bit_pins_a: mmc0-4bit@0 {
372 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800373 fsl,pinmux-ids = <
374 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
375 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
376 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
377 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
378 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
379 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
380 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
381 >;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200382 fsl,drive-strength = <1>;
383 fsl,voltage = <1>;
384 fsl,pull-up = <1>;
385 };
386
Shawn Guo35d23042012-05-06 16:33:34 +0800387 mmc0_cd_cfg: mmc0-cd-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800388 fsl,pinmux-ids = <
389 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
390 >;
Shawn Guo35d23042012-05-06 16:33:34 +0800391 fsl,pull-up = <0>;
392 };
393
394 mmc0_sck_cfg: mmc0-sck-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800395 fsl,pinmux-ids = <
396 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
397 >;
Shawn Guo35d23042012-05-06 16:33:34 +0800398 fsl,drive-strength = <2>;
399 fsl,pull-up = <0>;
400 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800401
402 i2c0_pins_a: i2c0@0 {
403 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800404 fsl,pinmux-ids = <
405 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
406 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
407 >;
Shawn Guo2a96e392012-05-10 15:02:10 +0800408 fsl,drive-strength = <1>;
409 fsl,voltage = <1>;
410 fsl,pull-up = <1>;
411 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800412
413 saif0_pins_a: saif0@0 {
414 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800415 fsl,pinmux-ids = <
416 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
417 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
418 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
419 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
420 >;
Shawn Guo530f1d42012-05-10 15:03:16 +0800421 fsl,drive-strength = <2>;
422 fsl,voltage = <1>;
423 fsl,pull-up = <1>;
424 };
425
426 saif1_pins_a: saif1@0 {
427 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800428 fsl,pinmux-ids = <
429 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
430 >;
Shawn Guo530f1d42012-05-10 15:03:16 +0800431 fsl,drive-strength = <2>;
432 fsl,voltage = <1>;
433 fsl,pull-up = <1>;
434 };
Shawn Guo52f71762012-06-28 11:45:06 +0800435
Shawn Guoe1a4d182012-07-09 12:34:35 +0800436 pwm0_pins_a: pwm0@0 {
437 reg = <0>;
438 fsl,pinmux-ids = <
439 0x3100 /* MX28_PAD_PWM0__PWM_0 */
440 >;
441 fsl,drive-strength = <0>;
442 fsl,voltage = <1>;
443 fsl,pull-up = <0>;
444 };
445
Shawn Guo52f71762012-06-28 11:45:06 +0800446 pwm2_pins_a: pwm2@0 {
447 reg = <0>;
448 fsl,pinmux-ids = <
449 0x3120 /* MX28_PAD_PWM2__PWM_2 */
450 >;
451 fsl,drive-strength = <0>;
452 fsl,voltage = <1>;
453 fsl,pull-up = <0>;
454 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800455
456 lcdif_24bit_pins_a: lcdif-24bit@0 {
457 reg = <0>;
458 fsl,pinmux-ids = <
459 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
460 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
461 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
462 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
463 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
464 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
465 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
466 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
467 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
468 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
469 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
470 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
471 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
472 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
473 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
474 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
475 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
476 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
477 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
478 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
479 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
480 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
481 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
482 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
Shawn Guoa915ee42012-06-28 11:45:07 +0800483 >;
484 fsl,drive-strength = <0>;
485 fsl,voltage = <1>;
486 fsl,pull-up = <0>;
487 };
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800488
489 can0_pins_a: can0@0 {
490 reg = <0>;
491 fsl,pinmux-ids = <
492 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
493 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
494 >;
495 fsl,drive-strength = <0>;
496 fsl,voltage = <1>;
497 fsl,pull-up = <0>;
498 };
499
500 can1_pins_a: can1@0 {
501 reg = <0>;
502 fsl,pinmux-ids = <
503 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
504 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
505 >;
506 fsl,drive-strength = <0>;
507 fsl,voltage = <1>;
508 fsl,pull-up = <0>;
509 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800510 };
511
512 digctl@8001c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300513 reg = <0x8001c000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800514 interrupts = <89>;
515 status = "disabled";
516 };
517
518 etm@80022000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300519 reg = <0x80022000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800520 status = "disabled";
521 };
522
523 dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800524 compatible = "fsl,imx28-dma-apbx";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300525 reg = <0x80024000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800526 };
527
528 dcp@80028000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300529 reg = <0x80028000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800530 interrupts = <52 53 54>;
531 status = "disabled";
532 };
533
534 pxp@8002a000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300535 reg = <0x8002a000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800536 interrupts = <39>;
537 status = "disabled";
538 };
539
540 ocotp@8002c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300541 reg = <0x8002c000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800542 status = "disabled";
543 };
544
545 axi-ahb@8002e000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300546 reg = <0x8002e000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800547 status = "disabled";
548 };
549
550 lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800551 compatible = "fsl,imx28-lcdif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300552 reg = <0x80030000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800553 interrupts = <38 86>;
554 status = "disabled";
555 };
556
557 can0: can@80032000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800558 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300559 reg = <0x80032000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800560 interrupts = <8>;
561 status = "disabled";
562 };
563
564 can1: can@80034000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800565 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300566 reg = <0x80034000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800567 interrupts = <9>;
568 status = "disabled";
569 };
570
571 simdbg@8003c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300572 reg = <0x8003c000 0x200>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800573 status = "disabled";
574 };
575
576 simgpmisel@8003c200 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300577 reg = <0x8003c200 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800578 status = "disabled";
579 };
580
581 simsspsel@8003c300 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300582 reg = <0x8003c300 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800583 status = "disabled";
584 };
585
586 simmemsel@8003c400 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300587 reg = <0x8003c400 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800588 status = "disabled";
589 };
590
591 gpiomon@8003c500 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300592 reg = <0x8003c500 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800593 status = "disabled";
594 };
595
596 simenet@8003c700 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300597 reg = <0x8003c700 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800598 status = "disabled";
599 };
600
601 armjtag@8003c800 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300602 reg = <0x8003c800 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800603 status = "disabled";
604 };
605 };
606
607 apbx@80040000 {
608 compatible = "simple-bus";
609 #address-cells = <1>;
610 #size-cells = <1>;
611 reg = <0x80040000 0x40000>;
612 ranges;
613
614 clkctl@80040000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300615 reg = <0x80040000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800616 status = "disabled";
617 };
618
619 saif0: saif@80042000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800620 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300621 reg = <0x80042000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800622 interrupts = <59 80>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800623 fsl,saif-dma-channel = <4>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800624 status = "disabled";
625 };
626
627 power@80044000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300628 reg = <0x80044000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800629 status = "disabled";
630 };
631
632 saif1: saif@80046000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800633 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300634 reg = <0x80046000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800635 interrupts = <58 81>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800636 fsl,saif-dma-channel = <5>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800637 status = "disabled";
638 };
639
640 lradc@80050000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300641 reg = <0x80050000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800642 status = "disabled";
643 };
644
645 spdif@80054000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300646 reg = <0x80054000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800647 interrupts = <45 66>;
648 status = "disabled";
649 };
650
651 rtc@80056000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800652 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300653 reg = <0x80056000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800654 interrupts = <29>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800655 };
656
657 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800658 #address-cells = <1>;
659 #size-cells = <0>;
660 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300661 reg = <0x80058000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800662 interrupts = <111 68>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200663 clock-frequency = <100000>;
Marek Vasut62885f52012-08-24 05:44:31 +0200664 fsl,i2c-dma-channel = <6>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800665 status = "disabled";
666 };
667
668 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800669 #address-cells = <1>;
670 #size-cells = <0>;
671 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300672 reg = <0x8005a000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800673 interrupts = <110 69>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200674 clock-frequency = <100000>;
Marek Vasut62885f52012-08-24 05:44:31 +0200675 fsl,i2c-dma-channel = <7>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800676 status = "disabled";
677 };
678
Shawn Guo52f71762012-06-28 11:45:06 +0800679 pwm: pwm@80064000 {
680 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300681 reg = <0x80064000 0x2000>;
Shawn Guo52f71762012-06-28 11:45:06 +0800682 #pwm-cells = <2>;
683 fsl,pwm-number = <8>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800684 status = "disabled";
685 };
686
687 timrot@80068000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300688 reg = <0x80068000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800689 status = "disabled";
690 };
691
692 auart0: serial@8006a000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300693 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800694 reg = <0x8006a000 0x2000>;
695 interrupts = <112 70 71>;
696 status = "disabled";
697 };
698
699 auart1: serial@8006c000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300700 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800701 reg = <0x8006c000 0x2000>;
702 interrupts = <113 72 73>;
703 status = "disabled";
704 };
705
706 auart2: serial@8006e000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300707 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800708 reg = <0x8006e000 0x2000>;
709 interrupts = <114 74 75>;
710 status = "disabled";
711 };
712
713 auart3: serial@80070000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300714 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800715 reg = <0x80070000 0x2000>;
716 interrupts = <115 76 77>;
717 status = "disabled";
718 };
719
720 auart4: serial@80072000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300721 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800722 reg = <0x80072000 0x2000>;
723 interrupts = <116 78 79>;
724 status = "disabled";
725 };
726
727 duart: serial@80074000 {
728 compatible = "arm,pl011", "arm,primecell";
729 reg = <0x80074000 0x1000>;
730 interrupts = <47>;
731 status = "disabled";
732 };
733
734 usbphy0: usbphy@8007c000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800735 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800736 reg = <0x8007c000 0x2000>;
737 status = "disabled";
738 };
739
740 usbphy1: usbphy@8007e000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800741 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800742 reg = <0x8007e000 0x2000>;
743 status = "disabled";
744 };
745 };
746 };
747
748 ahb@80080000 {
749 compatible = "simple-bus";
750 #address-cells = <1>;
751 #size-cells = <1>;
752 reg = <0x80080000 0x80000>;
753 ranges;
754
Richard Zhao5da01272012-07-12 10:25:27 +0800755 usb0: usb@80080000 {
756 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800757 reg = <0x80080000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800758 interrupts = <93>;
759 fsl,usbphy = <&usbphy0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800760 status = "disabled";
761 };
762
Richard Zhao5da01272012-07-12 10:25:27 +0800763 usb1: usb@80090000 {
764 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800765 reg = <0x80090000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800766 interrupts = <92>;
767 fsl,usbphy = <&usbphy1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800768 status = "disabled";
769 };
770
771 dflpt@800c0000 {
772 reg = <0x800c0000 0x10000>;
773 status = "disabled";
774 };
775
776 mac0: ethernet@800f0000 {
777 compatible = "fsl,imx28-fec";
778 reg = <0x800f0000 0x4000>;
779 interrupts = <101>;
780 status = "disabled";
781 };
782
783 mac1: ethernet@800f4000 {
784 compatible = "fsl,imx28-fec";
785 reg = <0x800f4000 0x4000>;
786 interrupts = <102>;
787 status = "disabled";
788 };
789
790 switch@800f8000 {
791 reg = <0x800f8000 0x8000>;
792 status = "disabled";
793 };
794
795 };
796};