Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 29 | #include <linux/sysrq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
| 32 | #include "i915_drm.h" |
| 33 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 34 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 35 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | #define MAX_NOPID ((u32)~0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 39 | /** |
| 40 | * Interrupts that are always left unmasked. |
| 41 | * |
| 42 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, |
| 43 | * we leave them always unmasked in IMR and then control enabling them through |
| 44 | * PIPESTAT alone. |
| 45 | */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame^] | 46 | #define I915_INTERRUPT_ENABLE_FIX \ |
| 47 | (I915_ASLE_INTERRUPT | \ |
| 48 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
| 49 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ |
| 50 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ |
| 51 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ |
| 52 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 53 | |
| 54 | /** Interrupts that we mask and unmask at runtime. */ |
| 55 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) |
| 56 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 57 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
| 58 | PIPE_VBLANK_INTERRUPT_STATUS) |
| 59 | |
| 60 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ |
| 61 | PIPE_VBLANK_INTERRUPT_ENABLE) |
| 62 | |
| 63 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ |
| 64 | DRM_I915_VBLANK_PIPE_B) |
| 65 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 66 | void |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 67 | igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 68 | { |
| 69 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { |
| 70 | dev_priv->gt_irq_mask_reg &= ~mask; |
| 71 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 72 | (void) I915_READ(GTIMR); |
| 73 | } |
| 74 | } |
| 75 | |
| 76 | static inline void |
| 77 | igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 78 | { |
| 79 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { |
| 80 | dev_priv->gt_irq_mask_reg |= mask; |
| 81 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 82 | (void) I915_READ(GTIMR); |
| 83 | } |
| 84 | } |
| 85 | |
| 86 | /* For display hotplug interrupt */ |
| 87 | void |
| 88 | igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 89 | { |
| 90 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
| 91 | dev_priv->irq_mask_reg &= ~mask; |
| 92 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 93 | (void) I915_READ(DEIMR); |
| 94 | } |
| 95 | } |
| 96 | |
| 97 | static inline void |
| 98 | igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 99 | { |
| 100 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
| 101 | dev_priv->irq_mask_reg |= mask; |
| 102 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 103 | (void) I915_READ(DEIMR); |
| 104 | } |
| 105 | } |
| 106 | |
| 107 | void |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 108 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 109 | { |
| 110 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
| 111 | dev_priv->irq_mask_reg &= ~mask; |
| 112 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 113 | (void) I915_READ(IMR); |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | static inline void |
| 118 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 119 | { |
| 120 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
| 121 | dev_priv->irq_mask_reg |= mask; |
| 122 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 123 | (void) I915_READ(IMR); |
| 124 | } |
| 125 | } |
| 126 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 127 | static inline u32 |
| 128 | i915_pipestat(int pipe) |
| 129 | { |
| 130 | if (pipe == 0) |
| 131 | return PIPEASTAT; |
| 132 | if (pipe == 1) |
| 133 | return PIPEBSTAT; |
Andrew Morton | 9c84ba4 | 2008-12-01 13:14:08 -0800 | [diff] [blame] | 134 | BUG(); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | void |
| 138 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 139 | { |
| 140 | if ((dev_priv->pipestat[pipe] & mask) != mask) { |
| 141 | u32 reg = i915_pipestat(pipe); |
| 142 | |
| 143 | dev_priv->pipestat[pipe] |= mask; |
| 144 | /* Enable the interrupt, clear any pending status */ |
| 145 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); |
| 146 | (void) I915_READ(reg); |
| 147 | } |
| 148 | } |
| 149 | |
| 150 | void |
| 151 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 152 | { |
| 153 | if ((dev_priv->pipestat[pipe] & mask) != 0) { |
| 154 | u32 reg = i915_pipestat(pipe); |
| 155 | |
| 156 | dev_priv->pipestat[pipe] &= ~mask; |
| 157 | I915_WRITE(reg, dev_priv->pipestat[pipe]); |
| 158 | (void) I915_READ(reg); |
| 159 | } |
| 160 | } |
| 161 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 162 | /** |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 163 | * intel_enable_asle - enable ASLE interrupt for OpRegion |
| 164 | */ |
| 165 | void intel_enable_asle (struct drm_device *dev) |
| 166 | { |
| 167 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 168 | |
| 169 | if (IS_IGDNG(dev)) |
| 170 | igdng_enable_display_irq(dev_priv, DE_GSE); |
| 171 | else |
| 172 | i915_enable_pipestat(dev_priv, 1, |
| 173 | I915_LEGACY_BLC_EVENT_ENABLE); |
| 174 | } |
| 175 | |
| 176 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 177 | * i915_pipe_enabled - check if a pipe is enabled |
| 178 | * @dev: DRM device |
| 179 | * @pipe: pipe to check |
| 180 | * |
| 181 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 182 | * Use this routine to make sure the PLL is running and the pipe is active |
| 183 | * before reading such registers if unsure. |
| 184 | */ |
| 185 | static int |
| 186 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 187 | { |
| 188 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 189 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; |
| 190 | |
| 191 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) |
| 192 | return 1; |
| 193 | |
| 194 | return 0; |
| 195 | } |
| 196 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 197 | /* Called from drm generic code, passed a 'crtc', which |
| 198 | * we use as a pipe index |
| 199 | */ |
| 200 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 201 | { |
| 202 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 203 | unsigned long high_frame; |
| 204 | unsigned long low_frame; |
| 205 | u32 high1, high2, low, count; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 206 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 207 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
| 208 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; |
| 209 | |
| 210 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 211 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
| 212 | "pipe %d\n", pipe); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 213 | return 0; |
| 214 | } |
| 215 | |
| 216 | /* |
| 217 | * High & low register fields aren't synchronized, so make sure |
| 218 | * we get a low value that's stable across two reads of the high |
| 219 | * register. |
| 220 | */ |
| 221 | do { |
| 222 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> |
| 223 | PIPE_FRAME_HIGH_SHIFT); |
| 224 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> |
| 225 | PIPE_FRAME_LOW_SHIFT); |
| 226 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> |
| 227 | PIPE_FRAME_HIGH_SHIFT); |
| 228 | } while (high1 != high2); |
| 229 | |
| 230 | count = (high1 << 8) | low; |
| 231 | |
| 232 | return count; |
| 233 | } |
| 234 | |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 235 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
| 236 | { |
| 237 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 238 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; |
| 239 | |
| 240 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 241 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
| 242 | "pipe %d\n", pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | return I915_READ(reg); |
| 247 | } |
| 248 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 249 | /* |
| 250 | * Handle hotplug events outside the interrupt handler proper. |
| 251 | */ |
| 252 | static void i915_hotplug_work_func(struct work_struct *work) |
| 253 | { |
| 254 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 255 | hotplug_work); |
| 256 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 257 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 258 | struct drm_connector *connector; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 259 | |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 260 | if (mode_config->num_connector) { |
| 261 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 262 | struct intel_output *intel_output = to_intel_output(connector); |
| 263 | |
| 264 | if (intel_output->hot_plug) |
| 265 | (*intel_output->hot_plug) (intel_output); |
| 266 | } |
| 267 | } |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 268 | /* Just fire off a uevent and let userspace tell us what to do */ |
| 269 | drm_sysfs_hotplug_event(dev); |
| 270 | } |
| 271 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 272 | irqreturn_t igdng_irq_handler(struct drm_device *dev) |
| 273 | { |
| 274 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 275 | int ret = IRQ_NONE; |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 276 | u32 de_iir, gt_iir, pch_iir; |
| 277 | u32 new_de_iir, new_gt_iir, new_pch_iir; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 278 | struct drm_i915_master_private *master_priv; |
| 279 | |
| 280 | de_iir = I915_READ(DEIIR); |
| 281 | gt_iir = I915_READ(GTIIR); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 282 | pch_iir = I915_READ(SDEIIR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 283 | |
| 284 | for (;;) { |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 285 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 286 | break; |
| 287 | |
| 288 | ret = IRQ_HANDLED; |
| 289 | |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 290 | /* should clear PCH hotplug event before clear CPU irq */ |
| 291 | I915_WRITE(SDEIIR, pch_iir); |
| 292 | new_pch_iir = I915_READ(SDEIIR); |
| 293 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 294 | I915_WRITE(DEIIR, de_iir); |
| 295 | new_de_iir = I915_READ(DEIIR); |
| 296 | I915_WRITE(GTIIR, gt_iir); |
| 297 | new_gt_iir = I915_READ(GTIIR); |
| 298 | |
| 299 | if (dev->primary->master) { |
| 300 | master_priv = dev->primary->master->driver_priv; |
| 301 | if (master_priv->sarea_priv) |
| 302 | master_priv->sarea_priv->last_dispatch = |
| 303 | READ_BREADCRUMB(dev_priv); |
| 304 | } |
| 305 | |
| 306 | if (gt_iir & GT_USER_INTERRUPT) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 307 | u32 seqno = i915_get_gem_seqno(dev); |
| 308 | dev_priv->mm.irq_gem_seqno = seqno; |
| 309 | trace_i915_gem_request_complete(dev, seqno); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 310 | DRM_WAKEUP(&dev_priv->irq_queue); |
| 311 | } |
| 312 | |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 313 | if (de_iir & DE_GSE) |
| 314 | ironlake_opregion_gse_intr(dev); |
| 315 | |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 316 | /* check event from PCH */ |
| 317 | if ((de_iir & DE_PCH_EVENT) && |
| 318 | (pch_iir & SDE_HOTPLUG_MASK)) { |
| 319 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
| 320 | } |
| 321 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 322 | de_iir = new_de_iir; |
| 323 | gt_iir = new_gt_iir; |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 324 | pch_iir = new_pch_iir; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 325 | } |
| 326 | |
| 327 | return ret; |
| 328 | } |
| 329 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 330 | /** |
| 331 | * i915_error_work_func - do process context error handling work |
| 332 | * @work: work struct |
| 333 | * |
| 334 | * Fire an error uevent so userspace can see that a hang or error |
| 335 | * was detected. |
| 336 | */ |
| 337 | static void i915_error_work_func(struct work_struct *work) |
| 338 | { |
| 339 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 340 | error_work); |
| 341 | struct drm_device *dev = dev_priv->dev; |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 342 | char *error_event[] = { "ERROR=1", NULL }; |
| 343 | char *reset_event[] = { "RESET=1", NULL }; |
| 344 | char *reset_done_event[] = { "ERROR=0", NULL }; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 345 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 346 | DRM_DEBUG_DRIVER("generating error event\n"); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 347 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 348 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 349 | if (atomic_read(&dev_priv->mm.wedged)) { |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 350 | if (IS_I965G(dev)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 351 | DRM_DEBUG_DRIVER("resetting chip\n"); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 352 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
| 353 | if (!i965_reset(dev, GDRST_RENDER)) { |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 354 | atomic_set(&dev_priv->mm.wedged, 0); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 355 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
| 356 | } |
| 357 | } else { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 358 | DRM_DEBUG_DRIVER("reboot required\n"); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 359 | } |
| 360 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 361 | } |
| 362 | |
| 363 | /** |
| 364 | * i915_capture_error_state - capture an error record for later analysis |
| 365 | * @dev: drm device |
| 366 | * |
| 367 | * Should be called when an error is detected (either a hang or an error |
| 368 | * interrupt) to capture error state from the time of the error. Fills |
| 369 | * out a structure which becomes available in debugfs for user level tools |
| 370 | * to pick up. |
| 371 | */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 372 | static void i915_capture_error_state(struct drm_device *dev) |
| 373 | { |
| 374 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 375 | struct drm_i915_error_state *error; |
| 376 | unsigned long flags; |
| 377 | |
| 378 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
| 379 | if (dev_priv->first_error) |
| 380 | goto out; |
| 381 | |
| 382 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
| 383 | if (!error) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 384 | DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n"); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 385 | goto out; |
| 386 | } |
| 387 | |
| 388 | error->eir = I915_READ(EIR); |
| 389 | error->pgtbl_er = I915_READ(PGTBL_ER); |
| 390 | error->pipeastat = I915_READ(PIPEASTAT); |
| 391 | error->pipebstat = I915_READ(PIPEBSTAT); |
| 392 | error->instpm = I915_READ(INSTPM); |
| 393 | if (!IS_I965G(dev)) { |
| 394 | error->ipeir = I915_READ(IPEIR); |
| 395 | error->ipehr = I915_READ(IPEHR); |
| 396 | error->instdone = I915_READ(INSTDONE); |
| 397 | error->acthd = I915_READ(ACTHD); |
| 398 | } else { |
| 399 | error->ipeir = I915_READ(IPEIR_I965); |
| 400 | error->ipehr = I915_READ(IPEHR_I965); |
| 401 | error->instdone = I915_READ(INSTDONE_I965); |
| 402 | error->instps = I915_READ(INSTPS); |
| 403 | error->instdone1 = I915_READ(INSTDONE1); |
| 404 | error->acthd = I915_READ(ACTHD_I965); |
| 405 | } |
| 406 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 407 | do_gettimeofday(&error->time); |
| 408 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 409 | dev_priv->first_error = error; |
| 410 | |
| 411 | out: |
| 412 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
| 413 | } |
| 414 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 415 | /** |
| 416 | * i915_handle_error - handle an error interrupt |
| 417 | * @dev: drm device |
| 418 | * |
| 419 | * Do some basic checking of regsiter state at error interrupt time and |
| 420 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 421 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 422 | * so userspace knows something bad happened (should trigger collection |
| 423 | * of a ring dump etc.). |
| 424 | */ |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 425 | static void i915_handle_error(struct drm_device *dev, bool wedged) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 426 | { |
| 427 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 428 | u32 eir = I915_READ(EIR); |
| 429 | u32 pipea_stats = I915_READ(PIPEASTAT); |
| 430 | u32 pipeb_stats = I915_READ(PIPEBSTAT); |
| 431 | |
| 432 | i915_capture_error_state(dev); |
| 433 | |
| 434 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", |
| 435 | eir); |
| 436 | |
| 437 | if (IS_G4X(dev)) { |
| 438 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 439 | u32 ipeir = I915_READ(IPEIR_I965); |
| 440 | |
| 441 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 442 | I915_READ(IPEIR_I965)); |
| 443 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 444 | I915_READ(IPEHR_I965)); |
| 445 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 446 | I915_READ(INSTDONE_I965)); |
| 447 | printk(KERN_ERR " INSTPS: 0x%08x\n", |
| 448 | I915_READ(INSTPS)); |
| 449 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", |
| 450 | I915_READ(INSTDONE1)); |
| 451 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 452 | I915_READ(ACTHD_I965)); |
| 453 | I915_WRITE(IPEIR_I965, ipeir); |
| 454 | (void)I915_READ(IPEIR_I965); |
| 455 | } |
| 456 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 457 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
| 458 | printk(KERN_ERR "page table error\n"); |
| 459 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", |
| 460 | pgtbl_err); |
| 461 | I915_WRITE(PGTBL_ER, pgtbl_err); |
| 462 | (void)I915_READ(PGTBL_ER); |
| 463 | } |
| 464 | } |
| 465 | |
| 466 | if (IS_I9XX(dev)) { |
| 467 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 468 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
| 469 | printk(KERN_ERR "page table error\n"); |
| 470 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", |
| 471 | pgtbl_err); |
| 472 | I915_WRITE(PGTBL_ER, pgtbl_err); |
| 473 | (void)I915_READ(PGTBL_ER); |
| 474 | } |
| 475 | } |
| 476 | |
| 477 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
| 478 | printk(KERN_ERR "memory refresh error\n"); |
| 479 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", |
| 480 | pipea_stats); |
| 481 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", |
| 482 | pipeb_stats); |
| 483 | /* pipestat has already been acked */ |
| 484 | } |
| 485 | if (eir & I915_ERROR_INSTRUCTION) { |
| 486 | printk(KERN_ERR "instruction error\n"); |
| 487 | printk(KERN_ERR " INSTPM: 0x%08x\n", |
| 488 | I915_READ(INSTPM)); |
| 489 | if (!IS_I965G(dev)) { |
| 490 | u32 ipeir = I915_READ(IPEIR); |
| 491 | |
| 492 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 493 | I915_READ(IPEIR)); |
| 494 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 495 | I915_READ(IPEHR)); |
| 496 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 497 | I915_READ(INSTDONE)); |
| 498 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 499 | I915_READ(ACTHD)); |
| 500 | I915_WRITE(IPEIR, ipeir); |
| 501 | (void)I915_READ(IPEIR); |
| 502 | } else { |
| 503 | u32 ipeir = I915_READ(IPEIR_I965); |
| 504 | |
| 505 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 506 | I915_READ(IPEIR_I965)); |
| 507 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 508 | I915_READ(IPEHR_I965)); |
| 509 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 510 | I915_READ(INSTDONE_I965)); |
| 511 | printk(KERN_ERR " INSTPS: 0x%08x\n", |
| 512 | I915_READ(INSTPS)); |
| 513 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", |
| 514 | I915_READ(INSTDONE1)); |
| 515 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 516 | I915_READ(ACTHD_I965)); |
| 517 | I915_WRITE(IPEIR_I965, ipeir); |
| 518 | (void)I915_READ(IPEIR_I965); |
| 519 | } |
| 520 | } |
| 521 | |
| 522 | I915_WRITE(EIR, eir); |
| 523 | (void)I915_READ(EIR); |
| 524 | eir = I915_READ(EIR); |
| 525 | if (eir) { |
| 526 | /* |
| 527 | * some errors might have become stuck, |
| 528 | * mask them. |
| 529 | */ |
| 530 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 531 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 532 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 533 | } |
| 534 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 535 | if (wedged) { |
| 536 | atomic_set(&dev_priv->mm.wedged, 1); |
| 537 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 538 | /* |
| 539 | * Wakeup waiting processes so they don't hang |
| 540 | */ |
| 541 | printk("i915: Waking up sleeping processes\n"); |
| 542 | DRM_WAKEUP(&dev_priv->irq_queue); |
| 543 | } |
| 544 | |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 545 | queue_work(dev_priv->wq, &dev_priv->error_work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 546 | } |
| 547 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 548 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
| 549 | { |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 550 | struct drm_device *dev = (struct drm_device *) arg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 551 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 552 | struct drm_i915_master_private *master_priv; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 553 | u32 iir, new_iir; |
| 554 | u32 pipea_stats, pipeb_stats; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 555 | u32 vblank_status; |
| 556 | u32 vblank_enable; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 557 | int vblank = 0; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 558 | unsigned long irqflags; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 559 | int irq_received; |
| 560 | int ret = IRQ_NONE; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 561 | |
Eric Anholt | 630681d | 2008-10-06 15:14:12 -0700 | [diff] [blame] | 562 | atomic_inc(&dev_priv->irq_received); |
| 563 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 564 | if (IS_IGDNG(dev)) |
| 565 | return igdng_irq_handler(dev); |
| 566 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 567 | iir = I915_READ(IIR); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 568 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 569 | if (IS_I965G(dev)) { |
| 570 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; |
| 571 | vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; |
| 572 | } else { |
| 573 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; |
| 574 | vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; |
| 575 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 576 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 577 | for (;;) { |
| 578 | irq_received = iir != 0; |
| 579 | |
| 580 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 581 | * have been cleared after the pipestat interrupt was received. |
| 582 | * It doesn't set the bit in iir again, but it still produces |
| 583 | * interrupts (for non-MSI). |
| 584 | */ |
| 585 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
| 586 | pipea_stats = I915_READ(PIPEASTAT); |
| 587 | pipeb_stats = I915_READ(PIPEBSTAT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 588 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 589 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 590 | i915_handle_error(dev, false); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 591 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 592 | /* |
| 593 | * Clear the PIPE(A|B)STAT regs before the IIR |
| 594 | */ |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 595 | if (pipea_stats & 0x8000ffff) { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 596 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 597 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 598 | I915_WRITE(PIPEASTAT, pipea_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 599 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 600 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 601 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 602 | if (pipeb_stats & 0x8000ffff) { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 603 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 604 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 605 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 606 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 607 | } |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 608 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
| 609 | |
| 610 | if (!irq_received) |
| 611 | break; |
| 612 | |
| 613 | ret = IRQ_HANDLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 615 | /* Consume port. Then clear IIR or we'll miss events */ |
| 616 | if ((I915_HAS_HOTPLUG(dev)) && |
| 617 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 618 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 619 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 620 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 621 | hotplug_status); |
| 622 | if (hotplug_status & dev_priv->hotplug_supported_mask) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 623 | queue_work(dev_priv->wq, |
| 624 | &dev_priv->hotplug_work); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 625 | |
| 626 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 627 | I915_READ(PORT_HOTPLUG_STAT); |
| 628 | } |
| 629 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 630 | I915_WRITE(IIR, iir); |
| 631 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 632 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 633 | if (dev->primary->master) { |
| 634 | master_priv = dev->primary->master->driver_priv; |
| 635 | if (master_priv->sarea_priv) |
| 636 | master_priv->sarea_priv->last_dispatch = |
| 637 | READ_BREADCRUMB(dev_priv); |
| 638 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 639 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 640 | if (iir & I915_USER_INTERRUPT) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 641 | u32 seqno = i915_get_gem_seqno(dev); |
| 642 | dev_priv->mm.irq_gem_seqno = seqno; |
| 643 | trace_i915_gem_request_complete(dev, seqno); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 644 | DRM_WAKEUP(&dev_priv->irq_queue); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 645 | dev_priv->hangcheck_count = 0; |
| 646 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 647 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 648 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame^] | 649 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) |
| 650 | intel_prepare_page_flip(dev, 0); |
| 651 | |
| 652 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) |
| 653 | intel_prepare_page_flip(dev, 1); |
| 654 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 655 | if (pipea_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 656 | vblank++; |
| 657 | drm_handle_vblank(dev, 0); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame^] | 658 | intel_finish_page_flip(dev, 0); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 659 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 660 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 661 | if (pipeb_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 662 | vblank++; |
| 663 | drm_handle_vblank(dev, 1); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame^] | 664 | intel_finish_page_flip(dev, 1); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 665 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 666 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 667 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
| 668 | (iir & I915_ASLE_INTERRUPT)) |
| 669 | opregion_asle_intr(dev); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 670 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 671 | /* With MSI, interrupts are only generated when iir |
| 672 | * transitions from zero to nonzero. If another bit got |
| 673 | * set while we were handling the existing iir bits, then |
| 674 | * we would never get another interrupt. |
| 675 | * |
| 676 | * This is fine on non-MSI as well, as if we hit this path |
| 677 | * we avoid exiting the interrupt handler only to generate |
| 678 | * another one. |
| 679 | * |
| 680 | * Note that for MSI this could cause a stray interrupt report |
| 681 | * if an interrupt landed in the time between writing IIR and |
| 682 | * the posting read. This should be rare enough to never |
| 683 | * trigger the 99% of 100,000 interrupts test for disabling |
| 684 | * stray interrupts. |
| 685 | */ |
| 686 | iir = new_iir; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 687 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 688 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 689 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 690 | } |
| 691 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 692 | static int i915_emit_irq(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 693 | { |
| 694 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 695 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 696 | RING_LOCALS; |
| 697 | |
| 698 | i915_kernel_lost_context(dev); |
| 699 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 700 | DRM_DEBUG_DRIVER("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 701 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 702 | dev_priv->counter++; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 703 | if (dev_priv->counter > 0x7FFFFFFFUL) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 704 | dev_priv->counter = 1; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 705 | if (master_priv->sarea_priv) |
| 706 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 707 | |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 708 | BEGIN_LP_RING(4); |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 709 | OUT_RING(MI_STORE_DWORD_INDEX); |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 710 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 711 | OUT_RING(dev_priv->counter); |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 712 | OUT_RING(MI_USER_INTERRUPT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | ADVANCE_LP_RING(); |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 714 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 715 | return dev_priv->counter; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 716 | } |
| 717 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 718 | void i915_user_irq_get(struct drm_device *dev) |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 719 | { |
| 720 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 721 | unsigned long irqflags; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 722 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 723 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 724 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { |
| 725 | if (IS_IGDNG(dev)) |
| 726 | igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
| 727 | else |
| 728 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
| 729 | } |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 730 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 731 | } |
| 732 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 733 | void i915_user_irq_put(struct drm_device *dev) |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 734 | { |
| 735 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 736 | unsigned long irqflags; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 737 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 738 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 739 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 740 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { |
| 741 | if (IS_IGDNG(dev)) |
| 742 | igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
| 743 | else |
| 744 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
| 745 | } |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 746 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 747 | } |
| 748 | |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 749 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
| 750 | { |
| 751 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 752 | |
| 753 | if (dev_priv->trace_irq_seqno == 0) |
| 754 | i915_user_irq_get(dev); |
| 755 | |
| 756 | dev_priv->trace_irq_seqno = seqno; |
| 757 | } |
| 758 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 759 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 760 | { |
| 761 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 762 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 763 | int ret = 0; |
| 764 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 765 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 766 | READ_BREADCRUMB(dev_priv)); |
| 767 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 768 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 769 | if (master_priv->sarea_priv) |
| 770 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 771 | return 0; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 772 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 773 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 774 | if (master_priv->sarea_priv) |
| 775 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 776 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 777 | i915_user_irq_get(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 778 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
| 779 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 780 | i915_user_irq_put(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 781 | |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 782 | if (ret == -EBUSY) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 783 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 784 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
| 785 | } |
| 786 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 787 | return ret; |
| 788 | } |
| 789 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 790 | /* Needs the lock as it touches the ring. |
| 791 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 792 | int i915_irq_emit(struct drm_device *dev, void *data, |
| 793 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 794 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 795 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 796 | drm_i915_irq_emit_t *emit = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 797 | int result; |
| 798 | |
Eric Anholt | 07f4f8b | 2009-04-16 13:46:12 -0700 | [diff] [blame] | 799 | if (!dev_priv || !dev_priv->ring.virtual_start) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 800 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 801 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 802 | } |
Eric Anholt | 299eb93 | 2009-02-24 22:14:12 -0800 | [diff] [blame] | 803 | |
| 804 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 805 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 806 | mutex_lock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 807 | result = i915_emit_irq(dev); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 808 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 809 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 810 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 811 | DRM_ERROR("copy_to_user\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 812 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 813 | } |
| 814 | |
| 815 | return 0; |
| 816 | } |
| 817 | |
| 818 | /* Doesn't need the hardware lock. |
| 819 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 820 | int i915_irq_wait(struct drm_device *dev, void *data, |
| 821 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 822 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 823 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 824 | drm_i915_irq_wait_t *irqwait = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 825 | |
| 826 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 827 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 828 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 829 | } |
| 830 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 831 | return i915_wait_irq(dev, irqwait->irq_seq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 832 | } |
| 833 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 834 | /* Called from drm generic code, passed 'crtc' which |
| 835 | * we use as a pipe index |
| 836 | */ |
| 837 | int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 838 | { |
| 839 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 840 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 841 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 842 | u32 pipeconf; |
| 843 | |
| 844 | pipeconf = I915_READ(pipeconf_reg); |
| 845 | if (!(pipeconf & PIPEACONF_ENABLE)) |
| 846 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 847 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 848 | if (IS_IGDNG(dev)) |
| 849 | return 0; |
| 850 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 851 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 852 | if (IS_I965G(dev)) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 853 | i915_enable_pipestat(dev_priv, pipe, |
| 854 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 855 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 856 | i915_enable_pipestat(dev_priv, pipe, |
| 857 | PIPE_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 858 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 859 | return 0; |
| 860 | } |
| 861 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 862 | /* Called from drm generic code, passed 'crtc' which |
| 863 | * we use as a pipe index |
| 864 | */ |
| 865 | void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 866 | { |
| 867 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 868 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 869 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 870 | if (IS_IGDNG(dev)) |
| 871 | return; |
| 872 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 873 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 874 | i915_disable_pipestat(dev_priv, pipe, |
| 875 | PIPE_VBLANK_INTERRUPT_ENABLE | |
| 876 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 877 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 878 | } |
| 879 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 880 | void i915_enable_interrupt (struct drm_device *dev) |
| 881 | { |
| 882 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | e170b03 | 2009-06-05 15:38:40 +0800 | [diff] [blame] | 883 | |
| 884 | if (!IS_IGDNG(dev)) |
| 885 | opregion_enable_asle(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 886 | dev_priv->irq_enabled = 1; |
| 887 | } |
| 888 | |
| 889 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 890 | /* Set the vblank monitor pipe |
| 891 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 892 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| 893 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 894 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 895 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 896 | |
| 897 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 898 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 899 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 900 | } |
| 901 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | 5b51694 | 2006-10-25 00:08:23 +1000 | [diff] [blame] | 902 | return 0; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 903 | } |
| 904 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 905 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 906 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 907 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 908 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 909 | drm_i915_vblank_pipe_t *pipe = data; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 910 | |
| 911 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 912 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 913 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 914 | } |
| 915 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 916 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 917 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 918 | return 0; |
| 919 | } |
| 920 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 921 | /** |
| 922 | * Schedule buffer swap at given vertical blank. |
| 923 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 924 | int i915_vblank_swap(struct drm_device *dev, void *data, |
| 925 | struct drm_file *file_priv) |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 926 | { |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 927 | /* The delayed swap mechanism was fundamentally racy, and has been |
| 928 | * removed. The model was that the client requested a delayed flip/swap |
| 929 | * from the kernel, then waited for vblank before continuing to perform |
| 930 | * rendering. The problem was that the kernel might wake the client |
| 931 | * up before it dispatched the vblank swap (since the lock has to be |
| 932 | * held while touching the ringbuffer), in which case the client would |
| 933 | * clear and start the next frame before the swap occurred, and |
| 934 | * flicker would occur in addition to likely missing the vblank. |
| 935 | * |
| 936 | * In the absence of this ioctl, userland falls back to a correct path |
| 937 | * of waiting for a vblank, then dispatching the swap on its own. |
| 938 | * Context switching to userland and back is plenty fast enough for |
| 939 | * meeting the requirements of vblank swapping. |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 940 | */ |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 941 | return -EINVAL; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 942 | } |
| 943 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 944 | struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) { |
| 945 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 946 | return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list); |
| 947 | } |
| 948 | |
| 949 | /** |
| 950 | * This is called when the chip hasn't reported back with completed |
| 951 | * batchbuffers in a long time. The first time this is called we simply record |
| 952 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses |
| 953 | * again, we assume the chip is wedged and try to fix it. |
| 954 | */ |
| 955 | void i915_hangcheck_elapsed(unsigned long data) |
| 956 | { |
| 957 | struct drm_device *dev = (struct drm_device *)data; |
| 958 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 959 | uint32_t acthd; |
| 960 | |
| 961 | if (!IS_I965G(dev)) |
| 962 | acthd = I915_READ(ACTHD); |
| 963 | else |
| 964 | acthd = I915_READ(ACTHD_I965); |
| 965 | |
| 966 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
| 967 | if (list_empty(&dev_priv->mm.request_list) || |
| 968 | i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) { |
| 969 | dev_priv->hangcheck_count = 0; |
| 970 | return; |
| 971 | } |
| 972 | |
| 973 | if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) { |
| 974 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 975 | i915_handle_error(dev, true); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 976 | return; |
| 977 | } |
| 978 | |
| 979 | /* Reset timer case chip hangs without another request being added */ |
| 980 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
| 981 | |
| 982 | if (acthd != dev_priv->last_acthd) |
| 983 | dev_priv->hangcheck_count = 0; |
| 984 | else |
| 985 | dev_priv->hangcheck_count++; |
| 986 | |
| 987 | dev_priv->last_acthd = acthd; |
| 988 | } |
| 989 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 990 | /* drm_dma.h hooks |
| 991 | */ |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 992 | static void igdng_irq_preinstall(struct drm_device *dev) |
| 993 | { |
| 994 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 995 | |
| 996 | I915_WRITE(HWSTAM, 0xeffe); |
| 997 | |
| 998 | /* XXX hotplug from PCH */ |
| 999 | |
| 1000 | I915_WRITE(DEIMR, 0xffffffff); |
| 1001 | I915_WRITE(DEIER, 0x0); |
| 1002 | (void) I915_READ(DEIER); |
| 1003 | |
| 1004 | /* and GT */ |
| 1005 | I915_WRITE(GTIMR, 0xffffffff); |
| 1006 | I915_WRITE(GTIER, 0x0); |
| 1007 | (void) I915_READ(GTIER); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1008 | |
| 1009 | /* south display irq */ |
| 1010 | I915_WRITE(SDEIMR, 0xffffffff); |
| 1011 | I915_WRITE(SDEIER, 0x0); |
| 1012 | (void) I915_READ(SDEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1013 | } |
| 1014 | |
| 1015 | static int igdng_irq_postinstall(struct drm_device *dev) |
| 1016 | { |
| 1017 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1018 | /* enable kind of interrupts always enabled */ |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1019 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1020 | u32 render_mask = GT_USER_INTERRUPT; |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1021 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
| 1022 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1023 | |
| 1024 | dev_priv->irq_mask_reg = ~display_mask; |
| 1025 | dev_priv->de_irq_enable_reg = display_mask; |
| 1026 | |
| 1027 | /* should always can generate irq */ |
| 1028 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 1029 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 1030 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); |
| 1031 | (void) I915_READ(DEIER); |
| 1032 | |
| 1033 | /* user interrupt should be enabled, but masked initial */ |
| 1034 | dev_priv->gt_irq_mask_reg = 0xffffffff; |
| 1035 | dev_priv->gt_irq_enable_reg = render_mask; |
| 1036 | |
| 1037 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1038 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 1039 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
| 1040 | (void) I915_READ(GTIER); |
| 1041 | |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1042 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
| 1043 | dev_priv->pch_irq_enable_reg = hotplug_mask; |
| 1044 | |
| 1045 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
| 1046 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); |
| 1047 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); |
| 1048 | (void) I915_READ(SDEIER); |
| 1049 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1050 | return 0; |
| 1051 | } |
| 1052 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1053 | void i915_driver_irq_preinstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1054 | { |
| 1055 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1056 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1057 | atomic_set(&dev_priv->irq_received, 0); |
| 1058 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1059 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1060 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1061 | |
| 1062 | if (IS_IGDNG(dev)) { |
| 1063 | igdng_irq_preinstall(dev); |
| 1064 | return; |
| 1065 | } |
| 1066 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1067 | if (I915_HAS_HOTPLUG(dev)) { |
| 1068 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1069 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1070 | } |
| 1071 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1072 | I915_WRITE(HWSTAM, 0xeffe); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1073 | I915_WRITE(PIPEASTAT, 0); |
| 1074 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1075 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1076 | I915_WRITE(IER, 0x0); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1077 | (void) I915_READ(IER); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1078 | } |
| 1079 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1080 | int i915_driver_irq_postinstall(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1081 | { |
| 1082 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1083 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1084 | u32 error_mask; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1085 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1086 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
| 1087 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1088 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1089 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1090 | if (IS_IGDNG(dev)) |
| 1091 | return igdng_irq_postinstall(dev); |
| 1092 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1093 | /* Unmask the interrupts that we always want on. */ |
| 1094 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1095 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1096 | dev_priv->pipestat[0] = 0; |
| 1097 | dev_priv->pipestat[1] = 0; |
| 1098 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1099 | if (I915_HAS_HOTPLUG(dev)) { |
| 1100 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 1101 | |
| 1102 | /* Leave other bits alone */ |
| 1103 | hotplug_en |= HOTPLUG_EN_MASK; |
| 1104 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 1105 | |
| 1106 | dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS | |
| 1107 | TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS | |
| 1108 | SDVOB_HOTPLUG_INT_STATUS; |
| 1109 | if (IS_G4X(dev)) { |
| 1110 | dev_priv->hotplug_supported_mask |= |
| 1111 | HDMIB_HOTPLUG_INT_STATUS | |
| 1112 | HDMIC_HOTPLUG_INT_STATUS | |
| 1113 | HDMID_HOTPLUG_INT_STATUS; |
| 1114 | } |
| 1115 | /* Enable in IER... */ |
| 1116 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 1117 | /* and unmask in IMR */ |
| 1118 | i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); |
| 1119 | } |
| 1120 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1121 | /* |
| 1122 | * Enable some error detection, note the instruction error mask |
| 1123 | * bit is reserved, so we leave it masked. |
| 1124 | */ |
| 1125 | if (IS_G4X(dev)) { |
| 1126 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 1127 | GM45_ERROR_MEM_PRIV | |
| 1128 | GM45_ERROR_CP_PRIV | |
| 1129 | I915_ERROR_MEMORY_REFRESH); |
| 1130 | } else { |
| 1131 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 1132 | I915_ERROR_MEMORY_REFRESH); |
| 1133 | } |
| 1134 | I915_WRITE(EMR, error_mask); |
| 1135 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1136 | /* Disable pipe interrupt enables, clear pending pipe status */ |
| 1137 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
| 1138 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); |
| 1139 | /* Clear pending interrupt status */ |
| 1140 | I915_WRITE(IIR, I915_READ(IIR)); |
| 1141 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1142 | I915_WRITE(IER, enable_mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1143 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1144 | (void) I915_READ(IER); |
| 1145 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1146 | opregion_enable_asle(dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1147 | |
| 1148 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1149 | } |
| 1150 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1151 | static void igdng_irq_uninstall(struct drm_device *dev) |
| 1152 | { |
| 1153 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1154 | I915_WRITE(HWSTAM, 0xffffffff); |
| 1155 | |
| 1156 | I915_WRITE(DEIMR, 0xffffffff); |
| 1157 | I915_WRITE(DEIER, 0x0); |
| 1158 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 1159 | |
| 1160 | I915_WRITE(GTIMR, 0xffffffff); |
| 1161 | I915_WRITE(GTIER, 0x0); |
| 1162 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1163 | } |
| 1164 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1165 | void i915_driver_irq_uninstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1166 | { |
| 1167 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 1168 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1169 | if (!dev_priv) |
| 1170 | return; |
| 1171 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1172 | dev_priv->vblank_pipe = 0; |
| 1173 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1174 | if (IS_IGDNG(dev)) { |
| 1175 | igdng_irq_uninstall(dev); |
| 1176 | return; |
| 1177 | } |
| 1178 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1179 | if (I915_HAS_HOTPLUG(dev)) { |
| 1180 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1181 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1182 | } |
| 1183 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1184 | I915_WRITE(HWSTAM, 0xffffffff); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1185 | I915_WRITE(PIPEASTAT, 0); |
| 1186 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1187 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1188 | I915_WRITE(IER, 0x0); |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 1189 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1190 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
| 1191 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); |
| 1192 | I915_WRITE(IIR, I915_READ(IIR)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1193 | } |