Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3 | * |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
Pierre Ossman | 643f720 | 2006-09-30 23:27:52 -0700 | [diff] [blame] | 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or (at |
| 9 | * your option) any later version. |
Pierre Ossman | 84c46a5 | 2007-12-02 19:58:16 +0100 | [diff] [blame] | 10 | * |
| 11 | * Thanks to the following companies for their support: |
| 12 | * |
| 13 | * - JMicron (hardware and technical support) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 14 | */ |
| 15 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 16 | #include <linux/delay.h> |
| 17 | #include <linux/highmem.h> |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 18 | #include <linux/io.h> |
Paul Gortmaker | 88b4767 | 2011-07-03 15:15:51 -0400 | [diff] [blame] | 19 | #include <linux/module.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 20 | #include <linux/dma-mapping.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 21 | #include <linux/slab.h> |
Ralf Baechle | 1176360 | 2007-10-23 20:42:11 +0200 | [diff] [blame] | 22 | #include <linux/scatterlist.h> |
Marek Szyprowski | 9bea3c8 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 23 | #include <linux/regulator/consumer.h> |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 24 | #include <linux/pm_runtime.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 25 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 26 | #include <linux/leds.h> |
| 27 | |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 28 | #include <linux/mmc/mmc.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 29 | #include <linux/mmc/host.h> |
Aaron Lu | 473b095a | 2012-07-03 17:27:49 +0800 | [diff] [blame] | 30 | #include <linux/mmc/card.h> |
Corneliu Doban | 85cc1c3 | 2015-02-09 16:06:29 -0800 | [diff] [blame] | 31 | #include <linux/mmc/sdio.h> |
Guennadi Liakhovetski | bec9d4e | 2012-09-17 16:45:10 +0800 | [diff] [blame] | 32 | #include <linux/mmc/slot-gpio.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 33 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 34 | #include "sdhci.h" |
| 35 | |
| 36 | #define DRIVER_NAME "sdhci" |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 37 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 38 | #define DBG(f, x...) \ |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 39 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 40 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 41 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
| 42 | defined(CONFIG_MMC_SDHCI_MODULE)) |
| 43 | #define SDHCI_USE_LEDS_CLASS |
| 44 | #endif |
| 45 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 46 | #define MAX_TUNING_LOOP 40 |
| 47 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 48 | static unsigned int debug_quirks = 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 49 | static unsigned int debug_quirks2; |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 50 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 51 | static void sdhci_finish_data(struct sdhci_host *); |
| 52 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 53 | static void sdhci_finish_command(struct sdhci_host *); |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 54 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 55 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 56 | static int sdhci_pre_dma_transfer(struct sdhci_host *host, |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 57 | struct mmc_data *data); |
Scott Branden | 04e079c | 2015-03-10 11:35:10 -0700 | [diff] [blame] | 58 | static int sdhci_do_get_cd(struct sdhci_host *host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 59 | |
Rafael J. Wysocki | 162d6f9 | 2014-12-05 03:05:33 +0100 | [diff] [blame] | 60 | #ifdef CONFIG_PM |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 61 | static int sdhci_runtime_pm_get(struct sdhci_host *host); |
| 62 | static int sdhci_runtime_pm_put(struct sdhci_host *host); |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 63 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); |
| 64 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 65 | #else |
| 66 | static inline int sdhci_runtime_pm_get(struct sdhci_host *host) |
| 67 | { |
| 68 | return 0; |
| 69 | } |
| 70 | static inline int sdhci_runtime_pm_put(struct sdhci_host *host) |
| 71 | { |
| 72 | return 0; |
| 73 | } |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 74 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
| 75 | { |
| 76 | } |
| 77 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) |
| 78 | { |
| 79 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 80 | #endif |
| 81 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 82 | static void sdhci_dumpregs(struct sdhci_host *host) |
| 83 | { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 84 | pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
Philip Rakity | 412ab65 | 2010-09-22 15:25:13 -0700 | [diff] [blame] | 85 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 86 | |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 87 | pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 88 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
| 89 | sdhci_readw(host, SDHCI_HOST_VERSION)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 90 | pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 91 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
| 92 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 93 | pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 94 | sdhci_readl(host, SDHCI_ARGUMENT), |
| 95 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 96 | pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 97 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
| 98 | sdhci_readb(host, SDHCI_HOST_CONTROL)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 99 | pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 100 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
| 101 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 102 | pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 103 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
| 104 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 105 | pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 106 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
| 107 | sdhci_readl(host, SDHCI_INT_STATUS)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 108 | pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 109 | sdhci_readl(host, SDHCI_INT_ENABLE), |
| 110 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 111 | pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 112 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
| 113 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 114 | pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 115 | sdhci_readl(host, SDHCI_CAPABILITIES), |
Philip Rakity | e8120ad | 2010-11-30 00:55:23 -0500 | [diff] [blame] | 116 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 117 | pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", |
Philip Rakity | e8120ad | 2010-11-30 00:55:23 -0500 | [diff] [blame] | 118 | sdhci_readw(host, SDHCI_COMMAND), |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 119 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 120 | pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 121 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 122 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 123 | if (host->flags & SDHCI_USE_ADMA) { |
| 124 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 125 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", |
| 126 | readl(host->ioaddr + SDHCI_ADMA_ERROR), |
| 127 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), |
| 128 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); |
| 129 | else |
| 130 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", |
| 131 | readl(host->ioaddr + SDHCI_ADMA_ERROR), |
| 132 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); |
| 133 | } |
Ben Dooks | be3f4ae | 2009-06-08 23:33:52 +0100 | [diff] [blame] | 134 | |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 135 | pr_debug(DRIVER_NAME ": ===========================================\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | /*****************************************************************************\ |
| 139 | * * |
| 140 | * Low level functions * |
| 141 | * * |
| 142 | \*****************************************************************************/ |
| 143 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 144 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) |
| 145 | { |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 146 | u32 present; |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 147 | |
Adrian Hunter | c79396c | 2011-12-27 15:48:42 +0200 | [diff] [blame] | 148 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
Daniel Drake | 87b87a3 | 2012-04-10 00:14:20 +0100 | [diff] [blame] | 149 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 150 | return; |
| 151 | |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 152 | if (enable) { |
| 153 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
| 154 | SDHCI_CARD_PRESENT; |
Shawn Guo | d25928d | 2011-06-21 22:41:48 +0800 | [diff] [blame] | 155 | |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 156 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
| 157 | SDHCI_INT_CARD_INSERT; |
| 158 | } else { |
| 159 | host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); |
| 160 | } |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 161 | |
| 162 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 163 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 164 | } |
| 165 | |
| 166 | static void sdhci_enable_card_detection(struct sdhci_host *host) |
| 167 | { |
| 168 | sdhci_set_card_detection(host, true); |
| 169 | } |
| 170 | |
| 171 | static void sdhci_disable_card_detection(struct sdhci_host *host) |
| 172 | { |
| 173 | sdhci_set_card_detection(host, false); |
| 174 | } |
| 175 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 176 | void sdhci_reset(struct sdhci_host *host, u8 mask) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 177 | { |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 178 | unsigned long timeout; |
Philip Rakity | 393c1a3 | 2011-01-21 11:26:40 -0800 | [diff] [blame] | 179 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 180 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 181 | |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 182 | if (mask & SDHCI_RESET_ALL) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 183 | host->clock = 0; |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 184 | /* Reset-all turns off SD Bus Power */ |
| 185 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 186 | sdhci_runtime_pm_bus_off(host); |
| 187 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 188 | |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 189 | /* Wait max 100 ms */ |
| 190 | timeout = 100; |
| 191 | |
| 192 | /* hw clears the bit when it's done */ |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 193 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 194 | if (timeout == 0) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 195 | pr_err("%s: Reset 0x%x never completed.\n", |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 196 | mmc_hostname(host->mmc), (int)mask); |
| 197 | sdhci_dumpregs(host); |
| 198 | return; |
| 199 | } |
| 200 | timeout--; |
| 201 | mdelay(1); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 202 | } |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 203 | } |
| 204 | EXPORT_SYMBOL_GPL(sdhci_reset); |
Anton Vorontsov | 063a9db | 2009-03-17 00:14:02 +0300 | [diff] [blame] | 205 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 206 | static void sdhci_do_reset(struct sdhci_host *host, u8 mask) |
| 207 | { |
| 208 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
Ivan T. Ivanov | 135b0a2 | 2015-07-06 15:16:21 +0300 | [diff] [blame] | 209 | if (!sdhci_do_get_cd(host)) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 210 | return; |
| 211 | } |
| 212 | |
| 213 | host->ops->reset(host, mask); |
Philip Rakity | 393c1a3 | 2011-01-21 11:26:40 -0800 | [diff] [blame] | 214 | |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 215 | if (mask & SDHCI_RESET_ALL) { |
| 216 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
| 217 | if (host->ops->enable_dma) |
| 218 | host->ops->enable_dma(host); |
| 219 | } |
| 220 | |
| 221 | /* Resetting the controller clears many */ |
| 222 | host->preset_enabled = false; |
Shaohui Xie | 3abc1e80 | 2011-12-29 16:33:00 +0800 | [diff] [blame] | 223 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 224 | } |
| 225 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 226 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
| 227 | |
| 228 | static void sdhci_init(struct sdhci_host *host, int soft) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 229 | { |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 230 | if (soft) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 231 | sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 232 | else |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 233 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 234 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 235 | host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
| 236 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | |
| 237 | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | |
| 238 | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | |
| 239 | SDHCI_INT_RESPONSE; |
| 240 | |
| 241 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 242 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 243 | |
| 244 | if (soft) { |
| 245 | /* force clock reconfiguration */ |
| 246 | host->clock = 0; |
| 247 | sdhci_set_ios(host->mmc, &host->mmc->ios); |
| 248 | } |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 249 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 250 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 251 | static void sdhci_reinit(struct sdhci_host *host) |
| 252 | { |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 253 | sdhci_init(host, 0); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 254 | sdhci_enable_card_detection(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | static void sdhci_activate_led(struct sdhci_host *host) |
| 258 | { |
| 259 | u8 ctrl; |
| 260 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 261 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 262 | ctrl |= SDHCI_CTRL_LED; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 263 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 264 | } |
| 265 | |
| 266 | static void sdhci_deactivate_led(struct sdhci_host *host) |
| 267 | { |
| 268 | u8 ctrl; |
| 269 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 270 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 271 | ctrl &= ~SDHCI_CTRL_LED; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 272 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 273 | } |
| 274 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 275 | #ifdef SDHCI_USE_LEDS_CLASS |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 276 | static void sdhci_led_control(struct led_classdev *led, |
| 277 | enum led_brightness brightness) |
| 278 | { |
| 279 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); |
| 280 | unsigned long flags; |
| 281 | |
| 282 | spin_lock_irqsave(&host->lock, flags); |
| 283 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 284 | if (host->runtime_suspended) |
| 285 | goto out; |
| 286 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 287 | if (brightness == LED_OFF) |
| 288 | sdhci_deactivate_led(host); |
| 289 | else |
| 290 | sdhci_activate_led(host); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 291 | out: |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 292 | spin_unlock_irqrestore(&host->lock, flags); |
| 293 | } |
| 294 | #endif |
| 295 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 296 | /*****************************************************************************\ |
| 297 | * * |
| 298 | * Core functions * |
| 299 | * * |
| 300 | \*****************************************************************************/ |
| 301 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 302 | static void sdhci_read_block_pio(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 303 | { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 304 | unsigned long flags; |
| 305 | size_t blksize, len, chunk; |
Steven Noonan | 7244b85 | 2008-10-01 01:50:25 -0700 | [diff] [blame] | 306 | u32 uninitialized_var(scratch); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 307 | u8 *buf; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 308 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 309 | DBG("PIO reading\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 310 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 311 | blksize = host->data->blksz; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 312 | chunk = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 313 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 314 | local_irq_save(flags); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 315 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 316 | while (blksize) { |
Fabio Estevam | bf3a35a | 2015-05-09 18:44:51 -0300 | [diff] [blame] | 317 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 318 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 319 | len = min(host->sg_miter.length, blksize); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 320 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 321 | blksize -= len; |
| 322 | host->sg_miter.consumed = len; |
Alex Dubov | 14d836e | 2007-04-13 19:04:38 +0200 | [diff] [blame] | 323 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 324 | buf = host->sg_miter.addr; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 325 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 326 | while (len) { |
| 327 | if (chunk == 0) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 328 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 329 | chunk = 4; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 330 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 331 | |
| 332 | *buf = scratch & 0xFF; |
| 333 | |
| 334 | buf++; |
| 335 | scratch >>= 8; |
| 336 | chunk--; |
| 337 | len--; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 338 | } |
| 339 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 340 | |
| 341 | sg_miter_stop(&host->sg_miter); |
| 342 | |
| 343 | local_irq_restore(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 344 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 345 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 346 | static void sdhci_write_block_pio(struct sdhci_host *host) |
| 347 | { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 348 | unsigned long flags; |
| 349 | size_t blksize, len, chunk; |
| 350 | u32 scratch; |
| 351 | u8 *buf; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 352 | |
| 353 | DBG("PIO writing\n"); |
| 354 | |
| 355 | blksize = host->data->blksz; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 356 | chunk = 0; |
| 357 | scratch = 0; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 358 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 359 | local_irq_save(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 360 | |
| 361 | while (blksize) { |
Fabio Estevam | bf3a35a | 2015-05-09 18:44:51 -0300 | [diff] [blame] | 362 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 363 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 364 | len = min(host->sg_miter.length, blksize); |
Alex Dubov | 14d836e | 2007-04-13 19:04:38 +0200 | [diff] [blame] | 365 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 366 | blksize -= len; |
| 367 | host->sg_miter.consumed = len; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 368 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 369 | buf = host->sg_miter.addr; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 370 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 371 | while (len) { |
| 372 | scratch |= (u32)*buf << (chunk * 8); |
| 373 | |
| 374 | buf++; |
| 375 | chunk++; |
| 376 | len--; |
| 377 | |
| 378 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 379 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 380 | chunk = 0; |
| 381 | scratch = 0; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 382 | } |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 383 | } |
| 384 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 385 | |
| 386 | sg_miter_stop(&host->sg_miter); |
| 387 | |
| 388 | local_irq_restore(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 389 | } |
| 390 | |
| 391 | static void sdhci_transfer_pio(struct sdhci_host *host) |
| 392 | { |
| 393 | u32 mask; |
| 394 | |
| 395 | BUG_ON(!host->data); |
| 396 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 397 | if (host->blocks == 0) |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 398 | return; |
| 399 | |
| 400 | if (host->data->flags & MMC_DATA_READ) |
| 401 | mask = SDHCI_DATA_AVAILABLE; |
| 402 | else |
| 403 | mask = SDHCI_SPACE_AVAILABLE; |
| 404 | |
Pierre Ossman | 4a3cba3 | 2008-07-29 00:11:16 +0200 | [diff] [blame] | 405 | /* |
| 406 | * Some controllers (JMicron JMB38x) mess up the buffer bits |
| 407 | * for transfers < 4 bytes. As long as it is just one block, |
| 408 | * we can ignore the bits. |
| 409 | */ |
| 410 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && |
| 411 | (host->data->blocks == 1)) |
| 412 | mask = ~0; |
| 413 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 414 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
Anton Vorontsov | 3e3bf20 | 2009-03-17 00:14:00 +0300 | [diff] [blame] | 415 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
| 416 | udelay(100); |
| 417 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 418 | if (host->data->flags & MMC_DATA_READ) |
| 419 | sdhci_read_block_pio(host); |
| 420 | else |
| 421 | sdhci_write_block_pio(host); |
| 422 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 423 | host->blocks--; |
| 424 | if (host->blocks == 0) |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 425 | break; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 426 | } |
| 427 | |
| 428 | DBG("PIO transfer complete.\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 429 | } |
| 430 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 431 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
| 432 | { |
| 433 | local_irq_save(*flags); |
Cong Wang | 482fce9 | 2011-11-27 13:27:00 +0800 | [diff] [blame] | 434 | return kmap_atomic(sg_page(sg)) + sg->offset; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 435 | } |
| 436 | |
| 437 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) |
| 438 | { |
Cong Wang | 482fce9 | 2011-11-27 13:27:00 +0800 | [diff] [blame] | 439 | kunmap_atomic(buffer); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 440 | local_irq_restore(*flags); |
| 441 | } |
| 442 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 443 | static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, |
| 444 | dma_addr_t addr, int len, unsigned cmd) |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 445 | { |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 446 | struct sdhci_adma2_64_desc *dma_desc = desc; |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 447 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 448 | /* 32-bit and 64-bit descriptors have these members in same position */ |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 449 | dma_desc->cmd = cpu_to_le16(cmd); |
| 450 | dma_desc->len = cpu_to_le16(len); |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 451 | dma_desc->addr_lo = cpu_to_le32((u32)addr); |
| 452 | |
| 453 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 454 | dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 455 | } |
| 456 | |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 457 | static void sdhci_adma_mark_end(void *desc) |
| 458 | { |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 459 | struct sdhci_adma2_64_desc *dma_desc = desc; |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 460 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 461 | /* 32-bit and 64-bit descriptors have 'cmd' in same position */ |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 462 | dma_desc->cmd |= cpu_to_le16(ADMA2_END); |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 463 | } |
| 464 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 465 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 466 | struct mmc_data *data) |
| 467 | { |
Adrian Hunter | 1c3d5f6 | 2014-11-04 12:42:41 +0200 | [diff] [blame] | 468 | void *desc; |
| 469 | void *align; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 470 | dma_addr_t addr; |
| 471 | dma_addr_t align_addr; |
| 472 | int len, offset; |
| 473 | |
| 474 | struct scatterlist *sg; |
| 475 | int i; |
| 476 | char *buffer; |
| 477 | unsigned long flags; |
| 478 | |
| 479 | /* |
| 480 | * The spec does not specify endianness of descriptor table. |
| 481 | * We currently guess that it is LE. |
| 482 | */ |
| 483 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 484 | host->sg_count = sdhci_pre_dma_transfer(host, data); |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 485 | if (host->sg_count < 0) |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 486 | return -EINVAL; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 487 | |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 488 | desc = host->adma_table; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 489 | align = host->align_buffer; |
| 490 | |
| 491 | align_addr = host->align_addr; |
| 492 | |
| 493 | for_each_sg(data->sg, sg, host->sg_count, i) { |
| 494 | addr = sg_dma_address(sg); |
| 495 | len = sg_dma_len(sg); |
| 496 | |
| 497 | /* |
| 498 | * The SDHCI specification states that ADMA |
| 499 | * addresses must be 32-bit aligned. If they |
| 500 | * aren't, then we use a bounce buffer for |
| 501 | * the (up to three) bytes that screw up the |
| 502 | * alignment. |
| 503 | */ |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 504 | offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & |
| 505 | SDHCI_ADMA2_MASK; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 506 | if (offset) { |
| 507 | if (data->flags & MMC_DATA_WRITE) { |
| 508 | buffer = sdhci_kmap_atomic(sg, &flags); |
| 509 | memcpy(align, buffer, offset); |
| 510 | sdhci_kunmap_atomic(buffer, &flags); |
| 511 | } |
| 512 | |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 513 | /* tran, valid */ |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 514 | sdhci_adma_write_desc(host, desc, align_addr, offset, |
Adrian Hunter | 739d46d | 2014-11-04 12:42:44 +0200 | [diff] [blame] | 515 | ADMA2_TRAN_VALID); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 516 | |
| 517 | BUG_ON(offset > 65536); |
| 518 | |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 519 | align += SDHCI_ADMA2_ALIGN; |
| 520 | align_addr += SDHCI_ADMA2_ALIGN; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 521 | |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 522 | desc += host->desc_sz; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 523 | |
| 524 | addr += offset; |
| 525 | len -= offset; |
| 526 | } |
| 527 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 528 | BUG_ON(len > 65536); |
| 529 | |
Adrian Hunter | 347ea32 | 2015-11-26 14:00:48 +0200 | [diff] [blame] | 530 | if (len) { |
| 531 | /* tran, valid */ |
| 532 | sdhci_adma_write_desc(host, desc, addr, len, |
| 533 | ADMA2_TRAN_VALID); |
| 534 | desc += host->desc_sz; |
| 535 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 536 | |
| 537 | /* |
| 538 | * If this triggers then we have a calculation bug |
| 539 | * somewhere. :/ |
| 540 | */ |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 541 | WARN_ON((desc - host->adma_table) >= host->adma_table_sz); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 542 | } |
| 543 | |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 544 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
| 545 | /* |
| 546 | * Mark the last descriptor as the terminating descriptor |
| 547 | */ |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 548 | if (desc != host->adma_table) { |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 549 | desc -= host->desc_sz; |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 550 | sdhci_adma_mark_end(desc); |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 551 | } |
| 552 | } else { |
| 553 | /* |
| 554 | * Add a terminating entry. |
| 555 | */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 556 | |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 557 | /* nop, end, valid */ |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 558 | sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 559 | } |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 560 | return 0; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 561 | } |
| 562 | |
| 563 | static void sdhci_adma_table_post(struct sdhci_host *host, |
| 564 | struct mmc_data *data) |
| 565 | { |
| 566 | int direction; |
| 567 | |
| 568 | struct scatterlist *sg; |
| 569 | int i, size; |
Adrian Hunter | 1c3d5f6 | 2014-11-04 12:42:41 +0200 | [diff] [blame] | 570 | void *align; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 571 | char *buffer; |
| 572 | unsigned long flags; |
Russell King | de0b65a | 2014-04-25 12:58:29 +0100 | [diff] [blame] | 573 | bool has_unaligned; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 574 | |
| 575 | if (data->flags & MMC_DATA_READ) |
| 576 | direction = DMA_FROM_DEVICE; |
| 577 | else |
| 578 | direction = DMA_TO_DEVICE; |
| 579 | |
Russell King | de0b65a | 2014-04-25 12:58:29 +0100 | [diff] [blame] | 580 | /* Do a quick scan of the SG list for any unaligned mappings */ |
| 581 | has_unaligned = false; |
| 582 | for_each_sg(data->sg, sg, host->sg_count, i) |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 583 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { |
Russell King | de0b65a | 2014-04-25 12:58:29 +0100 | [diff] [blame] | 584 | has_unaligned = true; |
| 585 | break; |
| 586 | } |
| 587 | |
| 588 | if (has_unaligned && data->flags & MMC_DATA_READ) { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 589 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, |
| 590 | data->sg_len, direction); |
| 591 | |
| 592 | align = host->align_buffer; |
| 593 | |
| 594 | for_each_sg(data->sg, sg, host->sg_count, i) { |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 595 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { |
| 596 | size = SDHCI_ADMA2_ALIGN - |
| 597 | (sg_dma_address(sg) & SDHCI_ADMA2_MASK); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 598 | |
| 599 | buffer = sdhci_kmap_atomic(sg, &flags); |
| 600 | memcpy(buffer, align, size); |
| 601 | sdhci_kunmap_atomic(buffer, &flags); |
| 602 | |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 603 | align += SDHCI_ADMA2_ALIGN; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 604 | } |
| 605 | } |
| 606 | } |
| 607 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 608 | if (data->host_cookie == COOKIE_MAPPED) { |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 609 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
| 610 | data->sg_len, direction); |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 611 | data->host_cookie = COOKIE_UNMAPPED; |
| 612 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 613 | } |
| 614 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 615 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 616 | { |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 617 | u8 count; |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 618 | struct mmc_data *data = cmd->data; |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 619 | unsigned target_timeout, current_timeout; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 620 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 621 | /* |
| 622 | * If the host controller provides us with an incorrect timeout |
| 623 | * value, just skip the check and use 0xE. The hardware may take |
| 624 | * longer to time out, but that's much better than having a too-short |
| 625 | * timeout value. |
| 626 | */ |
Pierre Ossman | 11a2f1b | 2009-06-21 20:59:33 +0200 | [diff] [blame] | 627 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 628 | return 0xE; |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 629 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 630 | /* Unspecified timeout, assume max */ |
Ulf Hansson | 1d4d774 | 2014-01-08 15:06:08 +0100 | [diff] [blame] | 631 | if (!data && !cmd->busy_timeout) |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 632 | return 0xE; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 633 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 634 | /* timeout in us */ |
| 635 | if (!data) |
Ulf Hansson | 1d4d774 | 2014-01-08 15:06:08 +0100 | [diff] [blame] | 636 | target_timeout = cmd->busy_timeout * 1000; |
Andy Shevchenko | 78a2ca2 | 2011-08-03 18:35:59 +0300 | [diff] [blame] | 637 | else { |
Russell King | fafcfda | 2016-01-26 13:40:58 +0000 | [diff] [blame] | 638 | target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); |
Russell King | 7f05538 | 2016-01-26 13:41:04 +0000 | [diff] [blame^] | 639 | if (host->clock && data->timeout_clks) { |
| 640 | unsigned long long val; |
| 641 | |
| 642 | /* |
| 643 | * data->timeout_clks is in units of clock cycles. |
| 644 | * host->clock is in Hz. target_timeout is in us. |
| 645 | * Hence, us = 1000000 * cycles / Hz. Round up. |
| 646 | */ |
| 647 | val = 1000000 * data->timeout_clks; |
| 648 | if (do_div(val, host->clock)) |
| 649 | target_timeout++; |
| 650 | target_timeout += val; |
| 651 | } |
Andy Shevchenko | 78a2ca2 | 2011-08-03 18:35:59 +0300 | [diff] [blame] | 652 | } |
Anton Vorontsov | 81b3980 | 2009-09-22 16:45:13 -0700 | [diff] [blame] | 653 | |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 654 | /* |
| 655 | * Figure out needed cycles. |
| 656 | * We do this in steps in order to fit inside a 32 bit int. |
| 657 | * The first step is the minimum timeout, which will have a |
| 658 | * minimum resolution of 6 bits: |
| 659 | * (1) 2^13*1000 > 2^22, |
| 660 | * (2) host->timeout_clk < 2^16 |
| 661 | * => |
| 662 | * (1) / (2) > 2^6 |
| 663 | */ |
| 664 | count = 0; |
| 665 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; |
| 666 | while (current_timeout < target_timeout) { |
| 667 | count++; |
| 668 | current_timeout <<= 1; |
| 669 | if (count >= 0xF) |
| 670 | break; |
| 671 | } |
| 672 | |
| 673 | if (count >= 0xF) { |
Chris Ball | 09eeff5 | 2012-06-01 10:39:45 -0400 | [diff] [blame] | 674 | DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", |
| 675 | mmc_hostname(host->mmc), count, cmd->opcode); |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 676 | count = 0xE; |
| 677 | } |
| 678 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 679 | return count; |
| 680 | } |
| 681 | |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 682 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
| 683 | { |
| 684 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; |
| 685 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; |
| 686 | |
| 687 | if (host->flags & SDHCI_REQ_USE_DMA) |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 688 | host->ier = (host->ier & ~pio_irqs) | dma_irqs; |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 689 | else |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 690 | host->ier = (host->ier & ~dma_irqs) | pio_irqs; |
| 691 | |
| 692 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 693 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 694 | } |
| 695 | |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 696 | static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 697 | { |
| 698 | u8 count; |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 699 | |
| 700 | if (host->ops->set_timeout) { |
| 701 | host->ops->set_timeout(host, cmd); |
| 702 | } else { |
| 703 | count = sdhci_calc_timeout(host, cmd); |
| 704 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); |
| 705 | } |
| 706 | } |
| 707 | |
| 708 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) |
| 709 | { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 710 | u8 ctrl; |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 711 | struct mmc_data *data = cmd->data; |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 712 | int ret; |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 713 | |
| 714 | WARN_ON(host->data); |
| 715 | |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 716 | if (data || (cmd->flags & MMC_RSP_BUSY)) |
| 717 | sdhci_set_timeout(host, cmd); |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 718 | |
| 719 | if (!data) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 720 | return; |
| 721 | |
| 722 | /* Sanity checks */ |
| 723 | BUG_ON(data->blksz * data->blocks > 524288); |
| 724 | BUG_ON(data->blksz > host->mmc->max_blk_size); |
| 725 | BUG_ON(data->blocks > 65535); |
| 726 | |
| 727 | host->data = data; |
| 728 | host->data_early = 0; |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 729 | host->data->bytes_xfered = 0; |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 730 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 731 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 732 | host->flags |= SDHCI_REQ_USE_DMA; |
| 733 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 734 | /* |
| 735 | * FIXME: This doesn't account for merging when mapping the |
| 736 | * scatterlist. |
| 737 | */ |
| 738 | if (host->flags & SDHCI_REQ_USE_DMA) { |
| 739 | int broken, i; |
| 740 | struct scatterlist *sg; |
| 741 | |
| 742 | broken = 0; |
| 743 | if (host->flags & SDHCI_USE_ADMA) { |
| 744 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) |
| 745 | broken = 1; |
| 746 | } else { |
| 747 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) |
| 748 | broken = 1; |
| 749 | } |
| 750 | |
| 751 | if (unlikely(broken)) { |
| 752 | for_each_sg(data->sg, sg, data->sg_len, i) { |
| 753 | if (sg->length & 0x3) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 754 | DBG("Reverting to PIO because of transfer size (%d)\n", |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 755 | sg->length); |
| 756 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 757 | break; |
| 758 | } |
| 759 | } |
| 760 | } |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 761 | } |
| 762 | |
| 763 | /* |
| 764 | * The assumption here being that alignment is the same after |
| 765 | * translation to device address space. |
| 766 | */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 767 | if (host->flags & SDHCI_REQ_USE_DMA) { |
| 768 | int broken, i; |
| 769 | struct scatterlist *sg; |
| 770 | |
| 771 | broken = 0; |
| 772 | if (host->flags & SDHCI_USE_ADMA) { |
| 773 | /* |
| 774 | * As we use 3 byte chunks to work around |
| 775 | * alignment problems, we need to check this |
| 776 | * quirk. |
| 777 | */ |
| 778 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) |
| 779 | broken = 1; |
| 780 | } else { |
| 781 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) |
| 782 | broken = 1; |
| 783 | } |
| 784 | |
| 785 | if (unlikely(broken)) { |
| 786 | for_each_sg(data->sg, sg, data->sg_len, i) { |
| 787 | if (sg->offset & 0x3) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 788 | DBG("Reverting to PIO because of bad alignment\n"); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 789 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 790 | break; |
| 791 | } |
| 792 | } |
| 793 | } |
| 794 | } |
| 795 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 796 | if (host->flags & SDHCI_REQ_USE_DMA) { |
| 797 | if (host->flags & SDHCI_USE_ADMA) { |
| 798 | ret = sdhci_adma_table_pre(host, data); |
| 799 | if (ret) { |
| 800 | /* |
| 801 | * This only happens when someone fed |
| 802 | * us an invalid request. |
| 803 | */ |
| 804 | WARN_ON(1); |
Pierre Ossman | ebd6d35 | 2008-07-29 00:45:51 +0200 | [diff] [blame] | 805 | host->flags &= ~SDHCI_REQ_USE_DMA; |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 806 | } else { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 807 | sdhci_writel(host, host->adma_addr, |
| 808 | SDHCI_ADMA_ADDRESS); |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 809 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 810 | sdhci_writel(host, |
| 811 | (u64)host->adma_addr >> 32, |
| 812 | SDHCI_ADMA_ADDRESS_HI); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 813 | } |
| 814 | } else { |
Tomas Winkler | c8b3e02 | 2008-07-05 19:52:04 +0300 | [diff] [blame] | 815 | int sg_cnt; |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 816 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 817 | sg_cnt = sdhci_pre_dma_transfer(host, data); |
Jiri Slaby | 62a7f36 | 2015-06-12 11:45:02 +0200 | [diff] [blame] | 818 | if (sg_cnt <= 0) { |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 819 | /* |
| 820 | * This only happens when someone fed |
| 821 | * us an invalid request. |
| 822 | */ |
| 823 | WARN_ON(1); |
Pierre Ossman | ebd6d35 | 2008-07-29 00:45:51 +0200 | [diff] [blame] | 824 | host->flags &= ~SDHCI_REQ_USE_DMA; |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 825 | } else { |
Pierre Ossman | 719a61b | 2008-07-22 13:23:23 +0200 | [diff] [blame] | 826 | WARN_ON(sg_cnt != 1); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 827 | sdhci_writel(host, sg_dma_address(data->sg), |
| 828 | SDHCI_DMA_ADDRESS); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 829 | } |
| 830 | } |
| 831 | } |
| 832 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 833 | /* |
| 834 | * Always adjust the DMA selection as some controllers |
| 835 | * (e.g. JMicron) can't do PIO properly when the selection |
| 836 | * is ADMA. |
| 837 | */ |
| 838 | if (host->version >= SDHCI_SPEC_200) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 839 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 840 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
| 841 | if ((host->flags & SDHCI_REQ_USE_DMA) && |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 842 | (host->flags & SDHCI_USE_ADMA)) { |
| 843 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 844 | ctrl |= SDHCI_CTRL_ADMA64; |
| 845 | else |
| 846 | ctrl |= SDHCI_CTRL_ADMA32; |
| 847 | } else { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 848 | ctrl |= SDHCI_CTRL_SDMA; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 849 | } |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 850 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 851 | } |
| 852 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 853 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
Sebastian Andrzej Siewior | da60a91 | 2009-06-18 09:33:32 +0200 | [diff] [blame] | 854 | int flags; |
| 855 | |
| 856 | flags = SG_MITER_ATOMIC; |
| 857 | if (host->data->flags & MMC_DATA_READ) |
| 858 | flags |= SG_MITER_TO_SG; |
| 859 | else |
| 860 | flags |= SG_MITER_FROM_SG; |
| 861 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 862 | host->blocks = data->blocks; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 863 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 864 | |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 865 | sdhci_set_transfer_irqs(host); |
| 866 | |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 867 | /* Set the DMA boundary value and block size */ |
| 868 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, |
| 869 | data->blksz), SDHCI_BLOCK_SIZE); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 870 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 871 | } |
| 872 | |
| 873 | static void sdhci_set_transfer_mode(struct sdhci_host *host, |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 874 | struct mmc_command *cmd) |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 875 | { |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 876 | u16 mode = 0; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 877 | struct mmc_data *data = cmd->data; |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 878 | |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 879 | if (data == NULL) { |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 880 | if (host->quirks2 & |
| 881 | SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { |
| 882 | sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); |
| 883 | } else { |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 884 | /* clear Auto CMD settings for no data CMDs */ |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 885 | mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); |
| 886 | sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 887 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 888 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 889 | return; |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 890 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 891 | |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 892 | WARN_ON(!host->data); |
| 893 | |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 894 | if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) |
| 895 | mode = SDHCI_TRNS_BLK_CNT_EN; |
| 896 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 897 | if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 898 | mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 899 | /* |
| 900 | * If we are sending CMD23, CMD12 never gets sent |
| 901 | * on successful completion (so no Auto-CMD12). |
| 902 | */ |
Corneliu Doban | 85cc1c3 | 2015-02-09 16:06:29 -0800 | [diff] [blame] | 903 | if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && |
| 904 | (cmd->opcode != SD_IO_RW_EXTENDED)) |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 905 | mode |= SDHCI_TRNS_AUTO_CMD12; |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 906 | else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { |
| 907 | mode |= SDHCI_TRNS_AUTO_CMD23; |
| 908 | sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); |
| 909 | } |
Jerry Huang | c4512f7 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 910 | } |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 911 | |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 912 | if (data->flags & MMC_DATA_READ) |
| 913 | mode |= SDHCI_TRNS_READ; |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 914 | if (host->flags & SDHCI_REQ_USE_DMA) |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 915 | mode |= SDHCI_TRNS_DMA; |
| 916 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 917 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 918 | } |
| 919 | |
| 920 | static void sdhci_finish_data(struct sdhci_host *host) |
| 921 | { |
| 922 | struct mmc_data *data; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 923 | |
| 924 | BUG_ON(!host->data); |
| 925 | |
| 926 | data = host->data; |
| 927 | host->data = NULL; |
| 928 | |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 929 | if (host->flags & SDHCI_REQ_USE_DMA) { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 930 | if (host->flags & SDHCI_USE_ADMA) |
| 931 | sdhci_adma_table_post(host, data); |
| 932 | else { |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 933 | if (data->host_cookie == COOKIE_MAPPED) { |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 934 | dma_unmap_sg(mmc_dev(host->mmc), |
| 935 | data->sg, data->sg_len, |
| 936 | (data->flags & MMC_DATA_READ) ? |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 937 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 938 | data->host_cookie = COOKIE_UNMAPPED; |
| 939 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 940 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 941 | } |
| 942 | |
| 943 | /* |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 944 | * The specification states that the block count register must |
| 945 | * be updated, but it does not specify at what point in the |
| 946 | * data flow. That makes the register entirely useless to read |
| 947 | * back so we have to assume that nothing made it to the card |
| 948 | * in the event of an error. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 949 | */ |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 950 | if (data->error) |
| 951 | data->bytes_xfered = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 952 | else |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 953 | data->bytes_xfered = data->blksz * data->blocks; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 954 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 955 | /* |
| 956 | * Need to send CMD12 if - |
| 957 | * a) open-ended multiblock transfer (no CMD23) |
| 958 | * b) error in multiblock transfer |
| 959 | */ |
| 960 | if (data->stop && |
| 961 | (data->error || |
| 962 | !host->mrq->sbc)) { |
| 963 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 964 | /* |
| 965 | * The controller needs a reset of internal state machines |
| 966 | * upon error conditions. |
| 967 | */ |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 968 | if (data->error) { |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 969 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 970 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 971 | } |
| 972 | |
| 973 | sdhci_send_command(host, data->stop); |
| 974 | } else |
| 975 | tasklet_schedule(&host->finish_tasklet); |
| 976 | } |
| 977 | |
Dong Aisheng | c0e55129 | 2013-09-13 19:11:31 +0800 | [diff] [blame] | 978 | void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 979 | { |
| 980 | int flags; |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 981 | u32 mask; |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 982 | unsigned long timeout; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 983 | |
| 984 | WARN_ON(host->cmd); |
| 985 | |
Russell King | 9677620 | 2016-01-26 13:39:34 +0000 | [diff] [blame] | 986 | /* Initially, a command has no error */ |
| 987 | cmd->error = 0; |
| 988 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 989 | /* Wait max 10 ms */ |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 990 | timeout = 10; |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 991 | |
| 992 | mask = SDHCI_CMD_INHIBIT; |
| 993 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) |
| 994 | mask |= SDHCI_DATA_INHIBIT; |
| 995 | |
| 996 | /* We shouldn't wait for data inihibit for stop commands, even |
| 997 | though they might use busy signaling */ |
| 998 | if (host->mrq->data && (cmd == host->mrq->data->stop)) |
| 999 | mask &= ~SDHCI_DATA_INHIBIT; |
| 1000 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1001 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1002 | if (timeout == 0) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1003 | pr_err("%s: Controller never released inhibit bit(s).\n", |
| 1004 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1005 | sdhci_dumpregs(host); |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1006 | cmd->error = -EIO; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1007 | tasklet_schedule(&host->finish_tasklet); |
| 1008 | return; |
| 1009 | } |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1010 | timeout--; |
| 1011 | mdelay(1); |
| 1012 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1013 | |
Adrian Hunter | 3e1a689 | 2013-11-14 10:16:20 +0200 | [diff] [blame] | 1014 | timeout = jiffies; |
Ulf Hansson | 1d4d774 | 2014-01-08 15:06:08 +0100 | [diff] [blame] | 1015 | if (!cmd->data && cmd->busy_timeout > 9000) |
| 1016 | timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; |
Adrian Hunter | 3e1a689 | 2013-11-14 10:16:20 +0200 | [diff] [blame] | 1017 | else |
| 1018 | timeout += 10 * HZ; |
| 1019 | mod_timer(&host->timer, timeout); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1020 | |
| 1021 | host->cmd = cmd; |
Chanho Min | e99783a | 2014-08-30 12:40:40 +0900 | [diff] [blame] | 1022 | host->busy_handle = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1023 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 1024 | sdhci_prepare_data(host, cmd); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1025 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1026 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1027 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1028 | sdhci_set_transfer_mode(host, cmd); |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1029 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1030 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 1031 | pr_err("%s: Unsupported response type!\n", |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1032 | mmc_hostname(host->mmc)); |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1033 | cmd->error = -EINVAL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1034 | tasklet_schedule(&host->finish_tasklet); |
| 1035 | return; |
| 1036 | } |
| 1037 | |
| 1038 | if (!(cmd->flags & MMC_RSP_PRESENT)) |
| 1039 | flags = SDHCI_CMD_RESP_NONE; |
| 1040 | else if (cmd->flags & MMC_RSP_136) |
| 1041 | flags = SDHCI_CMD_RESP_LONG; |
| 1042 | else if (cmd->flags & MMC_RSP_BUSY) |
| 1043 | flags = SDHCI_CMD_RESP_SHORT_BUSY; |
| 1044 | else |
| 1045 | flags = SDHCI_CMD_RESP_SHORT; |
| 1046 | |
| 1047 | if (cmd->flags & MMC_RSP_CRC) |
| 1048 | flags |= SDHCI_CMD_CRC; |
| 1049 | if (cmd->flags & MMC_RSP_OPCODE) |
| 1050 | flags |= SDHCI_CMD_INDEX; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1051 | |
| 1052 | /* CMD19 is special in that the Data Present Select should be set */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1053 | if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || |
| 1054 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1055 | flags |= SDHCI_CMD_DATA; |
| 1056 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1057 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1058 | } |
Dong Aisheng | c0e55129 | 2013-09-13 19:11:31 +0800 | [diff] [blame] | 1059 | EXPORT_SYMBOL_GPL(sdhci_send_command); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1060 | |
| 1061 | static void sdhci_finish_command(struct sdhci_host *host) |
| 1062 | { |
| 1063 | int i; |
| 1064 | |
| 1065 | BUG_ON(host->cmd == NULL); |
| 1066 | |
| 1067 | if (host->cmd->flags & MMC_RSP_PRESENT) { |
| 1068 | if (host->cmd->flags & MMC_RSP_136) { |
| 1069 | /* CRC is stripped so we need to do some shifting. */ |
| 1070 | for (i = 0;i < 4;i++) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1071 | host->cmd->resp[i] = sdhci_readl(host, |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1072 | SDHCI_RESPONSE + (3-i)*4) << 8; |
| 1073 | if (i != 3) |
| 1074 | host->cmd->resp[i] |= |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1075 | sdhci_readb(host, |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1076 | SDHCI_RESPONSE + (3-i)*4-1); |
| 1077 | } |
| 1078 | } else { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1079 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1080 | } |
| 1081 | } |
| 1082 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1083 | /* Finished CMD23, now send actual command. */ |
| 1084 | if (host->cmd == host->mrq->sbc) { |
| 1085 | host->cmd = NULL; |
| 1086 | sdhci_send_command(host, host->mrq->cmd); |
| 1087 | } else { |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 1088 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1089 | /* Processed actual command. */ |
| 1090 | if (host->data && host->data_early) |
| 1091 | sdhci_finish_data(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1092 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1093 | if (!host->cmd->data) |
| 1094 | tasklet_schedule(&host->finish_tasklet); |
| 1095 | |
| 1096 | host->cmd = NULL; |
| 1097 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1098 | } |
| 1099 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1100 | static u16 sdhci_get_preset_value(struct sdhci_host *host) |
| 1101 | { |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1102 | u16 preset = 0; |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1103 | |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1104 | switch (host->timing) { |
| 1105 | case MMC_TIMING_UHS_SDR12: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1106 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
| 1107 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1108 | case MMC_TIMING_UHS_SDR25: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1109 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); |
| 1110 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1111 | case MMC_TIMING_UHS_SDR50: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1112 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); |
| 1113 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1114 | case MMC_TIMING_UHS_SDR104: |
| 1115 | case MMC_TIMING_MMC_HS200: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1116 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); |
| 1117 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1118 | case MMC_TIMING_UHS_DDR50: |
Jisheng Zhang | 0dafa60 | 2015-08-18 16:21:39 +0800 | [diff] [blame] | 1119 | case MMC_TIMING_MMC_DDR52: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1120 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); |
| 1121 | break; |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1122 | case MMC_TIMING_MMC_HS400: |
| 1123 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); |
| 1124 | break; |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1125 | default: |
| 1126 | pr_warn("%s: Invalid UHS-I mode selected\n", |
| 1127 | mmc_hostname(host->mmc)); |
| 1128 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
| 1129 | break; |
| 1130 | } |
| 1131 | return preset; |
| 1132 | } |
| 1133 | |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1134 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1135 | { |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1136 | int div = 0; /* Initialized for compiler warning */ |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1137 | int real_div = div, clk_mul = 1; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1138 | u16 clk = 0; |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1139 | unsigned long timeout; |
ludovic.desroches@atmel.com | 5497159 | 2015-07-29 16:22:46 +0200 | [diff] [blame] | 1140 | bool switch_base_clk = false; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1141 | |
Russell King | 1650d0c | 2014-04-25 12:58:50 +0100 | [diff] [blame] | 1142 | host->mmc->actual_clock = 0; |
| 1143 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1144 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
ludovic.desroches@atmel.com | af95176 | 2015-09-17 10:16:19 +0200 | [diff] [blame] | 1145 | if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST) |
| 1146 | mdelay(1); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1147 | |
| 1148 | if (clock == 0) |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 1149 | return; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1150 | |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1151 | if (host->version >= SDHCI_SPEC_300) { |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 1152 | if (host->preset_enabled) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1153 | u16 pre_val; |
| 1154 | |
| 1155 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1156 | pre_val = sdhci_get_preset_value(host); |
| 1157 | div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) |
| 1158 | >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; |
| 1159 | if (host->clk_mul && |
| 1160 | (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { |
| 1161 | clk = SDHCI_PROG_CLOCK_MODE; |
| 1162 | real_div = div + 1; |
| 1163 | clk_mul = host->clk_mul; |
| 1164 | } else { |
| 1165 | real_div = max_t(int, 1, div << 1); |
| 1166 | } |
| 1167 | goto clock_set; |
| 1168 | } |
| 1169 | |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1170 | /* |
| 1171 | * Check if the Host Controller supports Programmable Clock |
| 1172 | * Mode. |
| 1173 | */ |
| 1174 | if (host->clk_mul) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1175 | for (div = 1; div <= 1024; div++) { |
| 1176 | if ((host->max_clk * host->clk_mul / div) |
| 1177 | <= clock) |
| 1178 | break; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1179 | } |
ludovic.desroches@atmel.com | 5497159 | 2015-07-29 16:22:46 +0200 | [diff] [blame] | 1180 | if ((host->max_clk * host->clk_mul / div) <= clock) { |
| 1181 | /* |
| 1182 | * Set Programmable Clock Mode in the Clock |
| 1183 | * Control register. |
| 1184 | */ |
| 1185 | clk = SDHCI_PROG_CLOCK_MODE; |
| 1186 | real_div = div; |
| 1187 | clk_mul = host->clk_mul; |
| 1188 | div--; |
| 1189 | } else { |
| 1190 | /* |
| 1191 | * Divisor can be too small to reach clock |
| 1192 | * speed requirement. Then use the base clock. |
| 1193 | */ |
| 1194 | switch_base_clk = true; |
| 1195 | } |
| 1196 | } |
| 1197 | |
| 1198 | if (!host->clk_mul || switch_base_clk) { |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1199 | /* Version 3.00 divisors must be a multiple of 2. */ |
| 1200 | if (host->max_clk <= clock) |
| 1201 | div = 1; |
| 1202 | else { |
| 1203 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; |
| 1204 | div += 2) { |
| 1205 | if ((host->max_clk / div) <= clock) |
| 1206 | break; |
| 1207 | } |
| 1208 | } |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1209 | real_div = div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1210 | div >>= 1; |
Suneel Garapati | d1955c3 | 2015-06-09 13:01:50 +0530 | [diff] [blame] | 1211 | if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) |
| 1212 | && !div && host->max_clk <= 25000000) |
| 1213 | div = 1; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1214 | } |
| 1215 | } else { |
| 1216 | /* Version 2.00 divisors must be a power of 2. */ |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 1217 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1218 | if ((host->max_clk / div) <= clock) |
| 1219 | break; |
| 1220 | } |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1221 | real_div = div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1222 | div >>= 1; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1223 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1224 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1225 | clock_set: |
Aisheng Dong | 03d6f5f | 2014-08-27 15:26:32 +0800 | [diff] [blame] | 1226 | if (real_div) |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1227 | host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1228 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1229 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
| 1230 | << SDHCI_DIVIDER_HI_SHIFT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1231 | clk |= SDHCI_CLOCK_INT_EN; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1232 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1233 | |
Chris Ball | 27f6cb1 | 2009-09-22 16:45:31 -0700 | [diff] [blame] | 1234 | /* Wait max 20 ms */ |
| 1235 | timeout = 20; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1236 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1237 | & SDHCI_CLOCK_INT_STABLE)) { |
| 1238 | if (timeout == 0) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1239 | pr_err("%s: Internal clock never stabilised.\n", |
| 1240 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1241 | sdhci_dumpregs(host); |
| 1242 | return; |
| 1243 | } |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1244 | timeout--; |
| 1245 | mdelay(1); |
| 1246 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1247 | |
| 1248 | clk |= SDHCI_CLOCK_CARD_EN; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1249 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1250 | } |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1251 | EXPORT_SYMBOL_GPL(sdhci_set_clock); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1252 | |
Russell King | 24fbb3c | 2014-04-25 13:00:06 +0100 | [diff] [blame] | 1253 | static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
| 1254 | unsigned short vdd) |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1255 | { |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1256 | struct mmc_host *mmc = host->mmc; |
Giuseppe Cavallaro | 8364248 | 2010-09-28 10:41:28 +0200 | [diff] [blame] | 1257 | u8 pwr = 0; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1258 | |
Russell King | 24fbb3c | 2014-04-25 13:00:06 +0100 | [diff] [blame] | 1259 | if (mode != MMC_POWER_OFF) { |
| 1260 | switch (1 << vdd) { |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1261 | case MMC_VDD_165_195: |
| 1262 | pwr = SDHCI_POWER_180; |
| 1263 | break; |
| 1264 | case MMC_VDD_29_30: |
| 1265 | case MMC_VDD_30_31: |
| 1266 | pwr = SDHCI_POWER_300; |
| 1267 | break; |
| 1268 | case MMC_VDD_32_33: |
| 1269 | case MMC_VDD_33_34: |
| 1270 | pwr = SDHCI_POWER_330; |
| 1271 | break; |
| 1272 | default: |
Adrian Hunter | 9d5de93 | 2015-11-26 14:00:46 +0200 | [diff] [blame] | 1273 | WARN(1, "%s: Invalid vdd %#x\n", |
| 1274 | mmc_hostname(host->mmc), vdd); |
| 1275 | break; |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1276 | } |
| 1277 | } |
| 1278 | |
| 1279 | if (host->pwr == pwr) |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1280 | return; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1281 | |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1282 | host->pwr = pwr; |
| 1283 | |
| 1284 | if (pwr == 0) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1285 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 1286 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 1287 | sdhci_runtime_pm_bus_off(host); |
Russell King | 24fbb3c | 2014-04-25 13:00:06 +0100 | [diff] [blame] | 1288 | vdd = 0; |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1289 | } else { |
| 1290 | /* |
| 1291 | * Spec says that we should clear the power reg before setting |
| 1292 | * a new value. Some controllers don't seem to like this though. |
| 1293 | */ |
| 1294 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
| 1295 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
Darren Salt | 9e9dc5f | 2007-01-27 15:32:31 +0100 | [diff] [blame] | 1296 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1297 | /* |
| 1298 | * At least the Marvell CaFe chip gets confused if we set the |
| 1299 | * voltage and set turn on power at the same time, so set the |
| 1300 | * voltage first. |
| 1301 | */ |
| 1302 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
| 1303 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1304 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1305 | pwr |= SDHCI_POWER_ON; |
| 1306 | |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1307 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
| 1308 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1309 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 1310 | sdhci_runtime_pm_bus_on(host); |
Andres Salomon | e08c169 | 2008-07-04 10:00:03 -0700 | [diff] [blame] | 1311 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1312 | /* |
| 1313 | * Some controllers need an extra 10ms delay of 10ms before |
| 1314 | * they can apply clock after applying power |
| 1315 | */ |
| 1316 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
| 1317 | mdelay(10); |
| 1318 | } |
Jisheng Zhang | 918f4cb | 2015-12-11 21:36:29 +0800 | [diff] [blame] | 1319 | |
| 1320 | if (!IS_ERR(mmc->supply.vmmc)) { |
| 1321 | spin_unlock_irq(&host->lock); |
| 1322 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); |
| 1323 | spin_lock_irq(&host->lock); |
| 1324 | } |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1325 | } |
| 1326 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1327 | /*****************************************************************************\ |
| 1328 | * * |
| 1329 | * MMC callbacks * |
| 1330 | * * |
| 1331 | \*****************************************************************************/ |
| 1332 | |
| 1333 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 1334 | { |
| 1335 | struct sdhci_host *host; |
Shawn Guo | 505a868 | 2012-12-11 15:23:42 +0800 | [diff] [blame] | 1336 | int present; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1337 | unsigned long flags; |
| 1338 | |
| 1339 | host = mmc_priv(mmc); |
| 1340 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1341 | sdhci_runtime_pm_get(host); |
| 1342 | |
Scott Branden | 04e079c | 2015-03-10 11:35:10 -0700 | [diff] [blame] | 1343 | /* Firstly check card presence */ |
Adrian Hunter | 8d28b7a | 2016-02-09 16:12:36 +0200 | [diff] [blame] | 1344 | present = mmc->ops->get_cd(mmc); |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 1345 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1346 | spin_lock_irqsave(&host->lock, flags); |
| 1347 | |
| 1348 | WARN_ON(host->mrq != NULL); |
| 1349 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 1350 | #ifndef SDHCI_USE_LEDS_CLASS |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1351 | sdhci_activate_led(host); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 1352 | #endif |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1353 | |
| 1354 | /* |
| 1355 | * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED |
| 1356 | * requests if Auto-CMD12 is enabled. |
| 1357 | */ |
| 1358 | if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { |
Jerry Huang | c4512f7 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 1359 | if (mrq->stop) { |
| 1360 | mrq->data->stop = NULL; |
| 1361 | mrq->stop = NULL; |
| 1362 | } |
| 1363 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1364 | |
| 1365 | host->mrq = mrq; |
| 1366 | |
Anton Vorontsov | 68d1fb7 | 2009-03-17 00:13:52 +0300 | [diff] [blame] | 1367 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1368 | host->mrq->cmd->error = -ENOMEDIUM; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1369 | tasklet_schedule(&host->finish_tasklet); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 1370 | } else { |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 1371 | if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1372 | sdhci_send_command(host, mrq->sbc); |
| 1373 | else |
| 1374 | sdhci_send_command(host, mrq->cmd); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 1375 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1376 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 1377 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1378 | spin_unlock_irqrestore(&host->lock, flags); |
| 1379 | } |
| 1380 | |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 1381 | void sdhci_set_bus_width(struct sdhci_host *host, int width) |
| 1382 | { |
| 1383 | u8 ctrl; |
| 1384 | |
| 1385 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
| 1386 | if (width == MMC_BUS_WIDTH_8) { |
| 1387 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 1388 | if (host->version >= SDHCI_SPEC_300) |
| 1389 | ctrl |= SDHCI_CTRL_8BITBUS; |
| 1390 | } else { |
| 1391 | if (host->version >= SDHCI_SPEC_300) |
| 1392 | ctrl &= ~SDHCI_CTRL_8BITBUS; |
| 1393 | if (width == MMC_BUS_WIDTH_4) |
| 1394 | ctrl |= SDHCI_CTRL_4BITBUS; |
| 1395 | else |
| 1396 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 1397 | } |
| 1398 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 1399 | } |
| 1400 | EXPORT_SYMBOL_GPL(sdhci_set_bus_width); |
| 1401 | |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 1402 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
| 1403 | { |
| 1404 | u16 ctrl_2; |
| 1405 | |
| 1406 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1407 | /* Select Bus Speed Mode for host */ |
| 1408 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
| 1409 | if ((timing == MMC_TIMING_MMC_HS200) || |
| 1410 | (timing == MMC_TIMING_UHS_SDR104)) |
| 1411 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 1412 | else if (timing == MMC_TIMING_UHS_SDR12) |
| 1413 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
| 1414 | else if (timing == MMC_TIMING_UHS_SDR25) |
| 1415 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; |
| 1416 | else if (timing == MMC_TIMING_UHS_SDR50) |
| 1417 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; |
| 1418 | else if ((timing == MMC_TIMING_UHS_DDR50) || |
| 1419 | (timing == MMC_TIMING_MMC_DDR52)) |
| 1420 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1421 | else if (timing == MMC_TIMING_MMC_HS400) |
| 1422 | ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 1423 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
| 1424 | } |
| 1425 | EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); |
| 1426 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1427 | static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1428 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1429 | unsigned long flags; |
| 1430 | u8 ctrl; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1431 | struct mmc_host *mmc = host->mmc; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1432 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1433 | spin_lock_irqsave(&host->lock, flags); |
| 1434 | |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1435 | if (host->flags & SDHCI_DEVICE_DEAD) { |
| 1436 | spin_unlock_irqrestore(&host->lock, flags); |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1437 | if (!IS_ERR(mmc->supply.vmmc) && |
| 1438 | ios->power_mode == MMC_POWER_OFF) |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 1439 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1440 | return; |
| 1441 | } |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1442 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1443 | /* |
| 1444 | * Reset the chip on each power off. |
| 1445 | * Should clear out any weird states. |
| 1446 | */ |
| 1447 | if (ios->power_mode == MMC_POWER_OFF) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1448 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 1449 | sdhci_reinit(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1450 | } |
| 1451 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1452 | if (host->version >= SDHCI_SPEC_300 && |
Dong Aisheng | 372c463 | 2013-10-18 19:48:50 +0800 | [diff] [blame] | 1453 | (ios->power_mode == MMC_POWER_UP) && |
| 1454 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1455 | sdhci_enable_preset_value(host, false); |
| 1456 | |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 1457 | if (!ios->clock || ios->clock != host->clock) { |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1458 | host->ops->set_clock(host, ios->clock); |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 1459 | host->clock = ios->clock; |
Aisheng Dong | 03d6f5f | 2014-08-27 15:26:32 +0800 | [diff] [blame] | 1460 | |
| 1461 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && |
| 1462 | host->clock) { |
| 1463 | host->timeout_clk = host->mmc->actual_clock ? |
| 1464 | host->mmc->actual_clock / 1000 : |
| 1465 | host->clock / 1000; |
| 1466 | host->mmc->max_busy_timeout = |
| 1467 | host->ops->get_max_timeout_count ? |
| 1468 | host->ops->get_max_timeout_count(host) : |
| 1469 | 1 << 27; |
| 1470 | host->mmc->max_busy_timeout /= host->timeout_clk; |
| 1471 | } |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 1472 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1473 | |
Russell King | 24fbb3c | 2014-04-25 13:00:06 +0100 | [diff] [blame] | 1474 | sdhci_set_power(host, ios->power_mode, ios->vdd); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1475 | |
Philip Rakity | 643a81f | 2010-09-23 08:24:32 -0700 | [diff] [blame] | 1476 | if (host->ops->platform_send_init_74_clocks) |
| 1477 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); |
| 1478 | |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 1479 | host->ops->set_bus_width(host, ios->bus_width); |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 1480 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1481 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 1482 | |
Philip Rakity | 3ab9c8d | 2010-10-06 11:57:23 -0700 | [diff] [blame] | 1483 | if ((ios->timing == MMC_TIMING_SD_HS || |
| 1484 | ios->timing == MMC_TIMING_MMC_HS) |
| 1485 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 1486 | ctrl |= SDHCI_CTRL_HISPD; |
| 1487 | else |
| 1488 | ctrl &= ~SDHCI_CTRL_HISPD; |
| 1489 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1490 | if (host->version >= SDHCI_SPEC_300) { |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1491 | u16 clk, ctrl_2; |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1492 | |
| 1493 | /* In case of UHS-I modes, set High Speed Enable */ |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1494 | if ((ios->timing == MMC_TIMING_MMC_HS400) || |
| 1495 | (ios->timing == MMC_TIMING_MMC_HS200) || |
Seungwon Jeon | bb8175a | 2014-03-14 21:12:48 +0900 | [diff] [blame] | 1496 | (ios->timing == MMC_TIMING_MMC_DDR52) || |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1497 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1498 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
| 1499 | (ios->timing == MMC_TIMING_UHS_DDR50) || |
Alexander Elbs | dd8df17 | 2012-01-03 23:26:53 -0500 | [diff] [blame] | 1500 | (ios->timing == MMC_TIMING_UHS_SDR25)) |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1501 | ctrl |= SDHCI_CTRL_HISPD; |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1502 | |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 1503 | if (!host->preset_enabled) { |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1504 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1505 | /* |
| 1506 | * We only need to set Driver Strength if the |
| 1507 | * preset value enable is not set. |
| 1508 | */ |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 1509 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1510 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; |
| 1511 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) |
| 1512 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 1513 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) |
| 1514 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1515 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) |
| 1516 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 1517 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) |
| 1518 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; |
| 1519 | else { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1520 | pr_warn("%s: invalid driver type, default to driver type B\n", |
| 1521 | mmc_hostname(mmc)); |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 1522 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; |
| 1523 | } |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1524 | |
| 1525 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1526 | } else { |
| 1527 | /* |
| 1528 | * According to SDHC Spec v3.00, if the Preset Value |
| 1529 | * Enable in the Host Control 2 register is set, we |
| 1530 | * need to reset SD Clock Enable before changing High |
| 1531 | * Speed Enable to avoid generating clock gliches. |
| 1532 | */ |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1533 | |
| 1534 | /* Reset SD Clock Enable */ |
| 1535 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1536 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 1537 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1538 | |
| 1539 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 1540 | |
| 1541 | /* Re-enable SD Clock */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1542 | host->ops->set_clock(host, host->clock); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1543 | } |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1544 | |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1545 | /* Reset SD Clock Enable */ |
| 1546 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1547 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 1548 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1549 | |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 1550 | host->ops->set_uhs_signaling(host, ios->timing); |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1551 | host->timing = ios->timing; |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1552 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1553 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && |
| 1554 | ((ios->timing == MMC_TIMING_UHS_SDR12) || |
| 1555 | (ios->timing == MMC_TIMING_UHS_SDR25) || |
| 1556 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
| 1557 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
Jisheng Zhang | 0dafa60 | 2015-08-18 16:21:39 +0800 | [diff] [blame] | 1558 | (ios->timing == MMC_TIMING_UHS_DDR50) || |
| 1559 | (ios->timing == MMC_TIMING_MMC_DDR52))) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1560 | u16 preset; |
| 1561 | |
| 1562 | sdhci_enable_preset_value(host, true); |
| 1563 | preset = sdhci_get_preset_value(host); |
| 1564 | ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) |
| 1565 | >> SDHCI_PRESET_DRV_SHIFT; |
| 1566 | } |
| 1567 | |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1568 | /* Re-enable SD Clock */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1569 | host->ops->set_clock(host, host->clock); |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1570 | } else |
| 1571 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1572 | |
Leandro Dorileo | b835226 | 2007-07-25 23:47:04 +0200 | [diff] [blame] | 1573 | /* |
| 1574 | * Some (ENE) controllers go apeshit on some ios operation, |
| 1575 | * signalling timeout and CRC errors even on CMD0. Resetting |
| 1576 | * it on each ios seems to solve the problem. |
| 1577 | */ |
Mohammad Jamal | c63705e | 2015-01-13 20:47:24 +0530 | [diff] [blame] | 1578 | if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 1579 | sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
Leandro Dorileo | b835226 | 2007-07-25 23:47:04 +0200 | [diff] [blame] | 1580 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 1581 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1582 | spin_unlock_irqrestore(&host->lock, flags); |
| 1583 | } |
| 1584 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1585 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1586 | { |
| 1587 | struct sdhci_host *host = mmc_priv(mmc); |
| 1588 | |
| 1589 | sdhci_runtime_pm_get(host); |
| 1590 | sdhci_do_set_ios(host, ios); |
| 1591 | sdhci_runtime_pm_put(host); |
| 1592 | } |
| 1593 | |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1594 | static int sdhci_do_get_cd(struct sdhci_host *host) |
| 1595 | { |
| 1596 | int gpio_cd = mmc_gpio_get_cd(host->mmc); |
| 1597 | |
| 1598 | if (host->flags & SDHCI_DEVICE_DEAD) |
| 1599 | return 0; |
| 1600 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 1601 | /* If nonremovable, assume that the card is always present. */ |
| 1602 | if (host->mmc->caps & MMC_CAP_NONREMOVABLE) |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1603 | return 1; |
| 1604 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 1605 | /* |
| 1606 | * Try slot gpio detect, if defined it take precedence |
| 1607 | * over build in controller functionality |
| 1608 | */ |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1609 | if (!IS_ERR_VALUE(gpio_cd)) |
| 1610 | return !!gpio_cd; |
| 1611 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 1612 | /* If polling, assume that the card is always present. */ |
| 1613 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
| 1614 | return 1; |
| 1615 | |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1616 | /* Host native card detect */ |
| 1617 | return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); |
| 1618 | } |
| 1619 | |
| 1620 | static int sdhci_get_cd(struct mmc_host *mmc) |
| 1621 | { |
| 1622 | struct sdhci_host *host = mmc_priv(mmc); |
| 1623 | int ret; |
| 1624 | |
| 1625 | sdhci_runtime_pm_get(host); |
| 1626 | ret = sdhci_do_get_cd(host); |
| 1627 | sdhci_runtime_pm_put(host); |
| 1628 | return ret; |
| 1629 | } |
| 1630 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1631 | static int sdhci_check_ro(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1632 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1633 | unsigned long flags; |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1634 | int is_readonly; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1635 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1636 | spin_lock_irqsave(&host->lock, flags); |
| 1637 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1638 | if (host->flags & SDHCI_DEVICE_DEAD) |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1639 | is_readonly = 0; |
| 1640 | else if (host->ops->get_ro) |
| 1641 | is_readonly = host->ops->get_ro(host); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1642 | else |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1643 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
| 1644 | & SDHCI_WRITE_PROTECT); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1645 | |
| 1646 | spin_unlock_irqrestore(&host->lock, flags); |
| 1647 | |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1648 | /* This quirk needs to be replaced by a callback-function later */ |
| 1649 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? |
| 1650 | !is_readonly : is_readonly; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1651 | } |
| 1652 | |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1653 | #define SAMPLE_COUNT 5 |
| 1654 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1655 | static int sdhci_do_get_ro(struct sdhci_host *host) |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1656 | { |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1657 | int i, ro_count; |
| 1658 | |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1659 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1660 | return sdhci_check_ro(host); |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1661 | |
| 1662 | ro_count = 0; |
| 1663 | for (i = 0; i < SAMPLE_COUNT; i++) { |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1664 | if (sdhci_check_ro(host)) { |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1665 | if (++ro_count > SAMPLE_COUNT / 2) |
| 1666 | return 1; |
| 1667 | } |
| 1668 | msleep(30); |
| 1669 | } |
| 1670 | return 0; |
| 1671 | } |
| 1672 | |
Adrian Hunter | 20758b6 | 2011-08-29 16:42:12 +0300 | [diff] [blame] | 1673 | static void sdhci_hw_reset(struct mmc_host *mmc) |
| 1674 | { |
| 1675 | struct sdhci_host *host = mmc_priv(mmc); |
| 1676 | |
| 1677 | if (host->ops && host->ops->hw_reset) |
| 1678 | host->ops->hw_reset(host); |
| 1679 | } |
| 1680 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1681 | static int sdhci_get_ro(struct mmc_host *mmc) |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1682 | { |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1683 | struct sdhci_host *host = mmc_priv(mmc); |
| 1684 | int ret; |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1685 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1686 | sdhci_runtime_pm_get(host); |
| 1687 | ret = sdhci_do_get_ro(host); |
| 1688 | sdhci_runtime_pm_put(host); |
| 1689 | return ret; |
| 1690 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1691 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1692 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
| 1693 | { |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 1694 | if (!(host->flags & SDHCI_DEVICE_DEAD)) { |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1695 | if (enable) |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 1696 | host->ier |= SDHCI_INT_CARD_INT; |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1697 | else |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 1698 | host->ier &= ~SDHCI_INT_CARD_INT; |
| 1699 | |
| 1700 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 1701 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1702 | mmiowb(); |
| 1703 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1704 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1705 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1706 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
| 1707 | { |
| 1708 | struct sdhci_host *host = mmc_priv(mmc); |
| 1709 | unsigned long flags; |
| 1710 | |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1711 | sdhci_runtime_pm_get(host); |
| 1712 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1713 | spin_lock_irqsave(&host->lock, flags); |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1714 | if (enable) |
| 1715 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; |
| 1716 | else |
| 1717 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; |
| 1718 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1719 | sdhci_enable_sdio_irq_nolock(host, enable); |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1720 | spin_unlock_irqrestore(&host->lock, flags); |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1721 | |
| 1722 | sdhci_runtime_pm_put(host); |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1723 | } |
| 1724 | |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1725 | static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, |
Fabio Estevam | 21f5998 | 2013-02-14 10:35:03 -0200 | [diff] [blame] | 1726 | struct mmc_ios *ios) |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1727 | { |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1728 | struct mmc_host *mmc = host->mmc; |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1729 | u16 ctrl; |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1730 | int ret; |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1731 | |
| 1732 | /* |
| 1733 | * Signal Voltage Switching is only applicable for Host Controllers |
| 1734 | * v3.00 and above. |
| 1735 | */ |
| 1736 | if (host->version < SDHCI_SPEC_300) |
| 1737 | return 0; |
| 1738 | |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1739 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1740 | |
Fabio Estevam | 21f5998 | 2013-02-14 10:35:03 -0200 | [diff] [blame] | 1741 | switch (ios->signal_voltage) { |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1742 | case MMC_SIGNAL_VOLTAGE_330: |
| 1743 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ |
| 1744 | ctrl &= ~SDHCI_CTRL_VDD_180; |
| 1745 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1746 | |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1747 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 1748 | ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, |
| 1749 | 3600000); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1750 | if (ret) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1751 | pr_warn("%s: Switching to 3.3V signalling voltage failed\n", |
| 1752 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1753 | return -EIO; |
| 1754 | } |
| 1755 | } |
| 1756 | /* Wait for 5ms */ |
| 1757 | usleep_range(5000, 5500); |
| 1758 | |
| 1759 | /* 3.3V regulator output should be stable within 5 ms */ |
| 1760 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1761 | if (!(ctrl & SDHCI_CTRL_VDD_180)) |
| 1762 | return 0; |
| 1763 | |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1764 | pr_warn("%s: 3.3V regulator output did not became stable\n", |
| 1765 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1766 | |
| 1767 | return -EAGAIN; |
| 1768 | case MMC_SIGNAL_VOLTAGE_180: |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1769 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 1770 | ret = regulator_set_voltage(mmc->supply.vqmmc, |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1771 | 1700000, 1950000); |
| 1772 | if (ret) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1773 | pr_warn("%s: Switching to 1.8V signalling voltage failed\n", |
| 1774 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1775 | return -EIO; |
| 1776 | } |
| 1777 | } |
| 1778 | |
| 1779 | /* |
| 1780 | * Enable 1.8V Signal Enable in the Host Control2 |
| 1781 | * register |
| 1782 | */ |
| 1783 | ctrl |= SDHCI_CTRL_VDD_180; |
| 1784 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1785 | |
Vincent Yang | 9d967a6 | 2015-01-20 16:05:15 +0800 | [diff] [blame] | 1786 | /* Some controller need to do more when switching */ |
| 1787 | if (host->ops->voltage_switch) |
| 1788 | host->ops->voltage_switch(host); |
| 1789 | |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1790 | /* 1.8V regulator output should be stable within 5 ms */ |
| 1791 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1792 | if (ctrl & SDHCI_CTRL_VDD_180) |
| 1793 | return 0; |
| 1794 | |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1795 | pr_warn("%s: 1.8V regulator output did not became stable\n", |
| 1796 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1797 | |
| 1798 | return -EAGAIN; |
| 1799 | case MMC_SIGNAL_VOLTAGE_120: |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1800 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 1801 | ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, |
| 1802 | 1300000); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1803 | if (ret) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1804 | pr_warn("%s: Switching to 1.2V signalling voltage failed\n", |
| 1805 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1806 | return -EIO; |
| 1807 | } |
| 1808 | } |
| 1809 | return 0; |
| 1810 | default: |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1811 | /* No signal voltage switch required */ |
| 1812 | return 0; |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1813 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1814 | } |
| 1815 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1816 | static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
Fabio Estevam | 21f5998 | 2013-02-14 10:35:03 -0200 | [diff] [blame] | 1817 | struct mmc_ios *ios) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1818 | { |
| 1819 | struct sdhci_host *host = mmc_priv(mmc); |
| 1820 | int err; |
| 1821 | |
| 1822 | if (host->version < SDHCI_SPEC_300) |
| 1823 | return 0; |
| 1824 | sdhci_runtime_pm_get(host); |
Fabio Estevam | 21f5998 | 2013-02-14 10:35:03 -0200 | [diff] [blame] | 1825 | err = sdhci_do_start_signal_voltage_switch(host, ios); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1826 | sdhci_runtime_pm_put(host); |
| 1827 | return err; |
| 1828 | } |
| 1829 | |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1830 | static int sdhci_card_busy(struct mmc_host *mmc) |
| 1831 | { |
| 1832 | struct sdhci_host *host = mmc_priv(mmc); |
| 1833 | u32 present_state; |
| 1834 | |
| 1835 | sdhci_runtime_pm_get(host); |
| 1836 | /* Check whether DAT[3:0] is 0000 */ |
| 1837 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); |
| 1838 | sdhci_runtime_pm_put(host); |
| 1839 | |
| 1840 | return !(present_state & SDHCI_DATA_LVL_MASK); |
| 1841 | } |
| 1842 | |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1843 | static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1844 | { |
| 1845 | struct sdhci_host *host = mmc_priv(mmc); |
| 1846 | unsigned long flags; |
| 1847 | |
| 1848 | spin_lock_irqsave(&host->lock, flags); |
| 1849 | host->flags |= SDHCI_HS400_TUNING; |
| 1850 | spin_unlock_irqrestore(&host->lock, flags); |
| 1851 | |
| 1852 | return 0; |
| 1853 | } |
| 1854 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1855 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1856 | { |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1857 | struct sdhci_host *host = mmc_priv(mmc); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1858 | u16 ctrl; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1859 | int tuning_loop_counter = MAX_TUNING_LOOP; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1860 | int err = 0; |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 1861 | unsigned long flags; |
Adrian Hunter | 38e40bf | 2014-12-05 19:25:30 +0200 | [diff] [blame] | 1862 | unsigned int tuning_count = 0; |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1863 | bool hs400_tuning; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1864 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1865 | sdhci_runtime_pm_get(host); |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 1866 | spin_lock_irqsave(&host->lock, flags); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1867 | |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1868 | hs400_tuning = host->flags & SDHCI_HS400_TUNING; |
| 1869 | host->flags &= ~SDHCI_HS400_TUNING; |
| 1870 | |
Adrian Hunter | 38e40bf | 2014-12-05 19:25:30 +0200 | [diff] [blame] | 1871 | if (host->tuning_mode == SDHCI_TUNING_MODE_1) |
| 1872 | tuning_count = host->tuning_count; |
| 1873 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1874 | /* |
Weijun Yang | 9faac7b | 2015-10-04 12:04:12 +0000 | [diff] [blame] | 1875 | * The Host Controller needs tuning in case of SDR104 and DDR50 |
| 1876 | * mode, and for SDR50 mode when Use Tuning for SDR50 is set in |
| 1877 | * the Capabilities register. |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1878 | * If the Host Controller supports the HS200 mode then the |
| 1879 | * tuning function has to be executed. |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1880 | */ |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1881 | switch (host->timing) { |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1882 | /* HS400 tuning is done in HS200 mode */ |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1883 | case MMC_TIMING_MMC_HS400: |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1884 | err = -EINVAL; |
| 1885 | goto out_unlock; |
| 1886 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1887 | case MMC_TIMING_MMC_HS200: |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1888 | /* |
| 1889 | * Periodic re-tuning for HS400 is not expected to be needed, so |
| 1890 | * disable it here. |
| 1891 | */ |
| 1892 | if (hs400_tuning) |
| 1893 | tuning_count = 0; |
| 1894 | break; |
| 1895 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1896 | case MMC_TIMING_UHS_SDR104: |
Weijun Yang | 9faac7b | 2015-10-04 12:04:12 +0000 | [diff] [blame] | 1897 | case MMC_TIMING_UHS_DDR50: |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1898 | break; |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1899 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1900 | case MMC_TIMING_UHS_SDR50: |
| 1901 | if (host->flags & SDHCI_SDR50_NEEDS_TUNING || |
| 1902 | host->flags & SDHCI_SDR104_NEEDS_TUNING) |
| 1903 | break; |
| 1904 | /* FALLTHROUGH */ |
| 1905 | |
| 1906 | default: |
Adrian Hunter | d519c86 | 2014-12-05 19:25:29 +0200 | [diff] [blame] | 1907 | goto out_unlock; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1908 | } |
| 1909 | |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 1910 | if (host->ops->platform_execute_tuning) { |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 1911 | spin_unlock_irqrestore(&host->lock, flags); |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 1912 | err = host->ops->platform_execute_tuning(host, opcode); |
| 1913 | sdhci_runtime_pm_put(host); |
| 1914 | return err; |
| 1915 | } |
| 1916 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1917 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1918 | ctrl |= SDHCI_CTRL_EXEC_TUNING; |
Vincent Yang | 67d0d04 | 2015-01-20 16:05:16 +0800 | [diff] [blame] | 1919 | if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) |
| 1920 | ctrl |= SDHCI_CTRL_TUNED_CLK; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1921 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1922 | |
| 1923 | /* |
| 1924 | * As per the Host Controller spec v3.00, tuning command |
| 1925 | * generates Buffer Read Ready interrupt, so enable that. |
| 1926 | * |
| 1927 | * Note: The spec clearly says that when tuning sequence |
| 1928 | * is being performed, the controller does not generate |
| 1929 | * interrupts other than Buffer Read Ready interrupt. But |
| 1930 | * to make sure we don't hit a controller bug, we _only_ |
| 1931 | * enable Buffer Read Ready interrupt here. |
| 1932 | */ |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 1933 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
| 1934 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1935 | |
| 1936 | /* |
| 1937 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number |
| 1938 | * of loops reaches 40 times or a timeout of 150ms occurs. |
| 1939 | */ |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1940 | do { |
| 1941 | struct mmc_command cmd = {0}; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1942 | struct mmc_request mrq = {NULL}; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1943 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1944 | cmd.opcode = opcode; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1945 | cmd.arg = 0; |
| 1946 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; |
| 1947 | cmd.retries = 0; |
| 1948 | cmd.data = NULL; |
| 1949 | cmd.error = 0; |
| 1950 | |
Al Cooper | 7ce45e9 | 2014-05-09 11:34:07 -0400 | [diff] [blame] | 1951 | if (tuning_loop_counter-- == 0) |
| 1952 | break; |
| 1953 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1954 | mrq.cmd = &cmd; |
| 1955 | host->mrq = &mrq; |
| 1956 | |
| 1957 | /* |
| 1958 | * In response to CMD19, the card sends 64 bytes of tuning |
| 1959 | * block to the Host Controller. So we set the block size |
| 1960 | * to 64 here. |
| 1961 | */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1962 | if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { |
| 1963 | if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) |
| 1964 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), |
| 1965 | SDHCI_BLOCK_SIZE); |
| 1966 | else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
| 1967 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), |
| 1968 | SDHCI_BLOCK_SIZE); |
| 1969 | } else { |
| 1970 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), |
| 1971 | SDHCI_BLOCK_SIZE); |
| 1972 | } |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1973 | |
| 1974 | /* |
| 1975 | * The tuning block is sent by the card to the host controller. |
| 1976 | * So we set the TRNS_READ bit in the Transfer Mode register. |
| 1977 | * This also takes care of setting DMA Enable and Multi Block |
| 1978 | * Select in the same register to 0. |
| 1979 | */ |
| 1980 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); |
| 1981 | |
| 1982 | sdhci_send_command(host, &cmd); |
| 1983 | |
| 1984 | host->cmd = NULL; |
| 1985 | host->mrq = NULL; |
| 1986 | |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 1987 | spin_unlock_irqrestore(&host->lock, flags); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1988 | /* Wait for Buffer Read Ready interrupt */ |
| 1989 | wait_event_interruptible_timeout(host->buf_ready_int, |
| 1990 | (host->tuning_done == 1), |
| 1991 | msecs_to_jiffies(50)); |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 1992 | spin_lock_irqsave(&host->lock, flags); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1993 | |
| 1994 | if (!host->tuning_done) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1995 | pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n"); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1996 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1997 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
| 1998 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; |
| 1999 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 2000 | |
| 2001 | err = -EIO; |
| 2002 | goto out; |
| 2003 | } |
| 2004 | |
| 2005 | host->tuning_done = 0; |
| 2006 | |
| 2007 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Nick Sanders | 197160d | 2014-05-06 18:52:38 -0700 | [diff] [blame] | 2008 | |
| 2009 | /* eMMC spec does not require a delay between tuning cycles */ |
| 2010 | if (opcode == MMC_SEND_TUNING_BLOCK) |
| 2011 | mdelay(1); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2012 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
| 2013 | |
| 2014 | /* |
| 2015 | * The Host Driver has exhausted the maximum number of loops allowed, |
| 2016 | * so use fixed sampling frequency. |
| 2017 | */ |
Al Cooper | 7ce45e9 | 2014-05-09 11:34:07 -0400 | [diff] [blame] | 2018 | if (tuning_loop_counter < 0) { |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2019 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
| 2020 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
Al Cooper | 7ce45e9 | 2014-05-09 11:34:07 -0400 | [diff] [blame] | 2021 | } |
| 2022 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2023 | pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n"); |
Dong Aisheng | 114f2bf | 2013-10-18 19:48:45 +0800 | [diff] [blame] | 2024 | err = -EIO; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2025 | } |
| 2026 | |
| 2027 | out: |
Adrian Hunter | 38e40bf | 2014-12-05 19:25:30 +0200 | [diff] [blame] | 2028 | if (tuning_count) { |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2029 | /* |
| 2030 | * In case tuning fails, host controllers which support |
| 2031 | * re-tuning can try tuning again at a later time, when the |
| 2032 | * re-tuning timer expires. So for these controllers, we |
| 2033 | * return 0. Since there might be other controllers who do not |
| 2034 | * have this capability, we return error for them. |
| 2035 | */ |
| 2036 | err = 0; |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2037 | } |
| 2038 | |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2039 | host->mmc->retune_period = err ? 0 : tuning_count; |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2040 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2041 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 2042 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Adrian Hunter | d519c86 | 2014-12-05 19:25:29 +0200 | [diff] [blame] | 2043 | out_unlock: |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 2044 | spin_unlock_irqrestore(&host->lock, flags); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2045 | sdhci_runtime_pm_put(host); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2046 | |
| 2047 | return err; |
| 2048 | } |
| 2049 | |
Adrian Hunter | cb84964 | 2015-02-06 14:12:59 +0200 | [diff] [blame] | 2050 | static int sdhci_select_drive_strength(struct mmc_card *card, |
| 2051 | unsigned int max_dtr, int host_drv, |
| 2052 | int card_drv, int *drv_type) |
| 2053 | { |
| 2054 | struct sdhci_host *host = mmc_priv(card->host); |
| 2055 | |
| 2056 | if (!host->ops->select_drive_strength) |
| 2057 | return 0; |
| 2058 | |
| 2059 | return host->ops->select_drive_strength(host, card, max_dtr, host_drv, |
| 2060 | card_drv, drv_type); |
| 2061 | } |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2062 | |
| 2063 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2064 | { |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2065 | /* Host Controller v3.00 defines preset value registers */ |
| 2066 | if (host->version < SDHCI_SPEC_300) |
| 2067 | return; |
| 2068 | |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2069 | /* |
| 2070 | * We only enable or disable Preset Value if they are not already |
| 2071 | * enabled or disabled respectively. Otherwise, we bail out. |
| 2072 | */ |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 2073 | if (host->preset_enabled != enable) { |
| 2074 | u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2075 | |
| 2076 | if (enable) |
| 2077 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 2078 | else |
| 2079 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 2080 | |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2081 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 2082 | |
| 2083 | if (enable) |
| 2084 | host->flags |= SDHCI_PV_ENABLED; |
| 2085 | else |
| 2086 | host->flags &= ~SDHCI_PV_ENABLED; |
| 2087 | |
| 2088 | host->preset_enabled = enable; |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2089 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2090 | } |
| 2091 | |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2092 | static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
| 2093 | int err) |
| 2094 | { |
| 2095 | struct sdhci_host *host = mmc_priv(mmc); |
| 2096 | struct mmc_data *data = mrq->data; |
| 2097 | |
Russell King | 771a3dc | 2016-01-26 13:40:53 +0000 | [diff] [blame] | 2098 | if (data->host_cookie == COOKIE_GIVEN || |
| 2099 | data->host_cookie == COOKIE_MAPPED) |
| 2100 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
| 2101 | data->flags & MMC_DATA_WRITE ? |
| 2102 | DMA_TO_DEVICE : DMA_FROM_DEVICE); |
| 2103 | |
| 2104 | data->host_cookie = COOKIE_UNMAPPED; |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2105 | } |
| 2106 | |
| 2107 | static int sdhci_pre_dma_transfer(struct sdhci_host *host, |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 2108 | struct mmc_data *data) |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2109 | { |
| 2110 | int sg_count; |
| 2111 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 2112 | if (data->host_cookie == COOKIE_MAPPED) { |
| 2113 | data->host_cookie = COOKIE_GIVEN; |
| 2114 | return data->sg_count; |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2115 | } |
| 2116 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 2117 | WARN_ON(data->host_cookie == COOKIE_GIVEN); |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2118 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 2119 | sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
| 2120 | data->flags & MMC_DATA_WRITE ? |
| 2121 | DMA_TO_DEVICE : DMA_FROM_DEVICE); |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2122 | |
| 2123 | if (sg_count == 0) |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 2124 | return -ENOSPC; |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2125 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 2126 | data->sg_count = sg_count; |
| 2127 | data->host_cookie = COOKIE_MAPPED; |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2128 | |
| 2129 | return sg_count; |
| 2130 | } |
| 2131 | |
| 2132 | static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, |
| 2133 | bool is_first_req) |
| 2134 | { |
| 2135 | struct sdhci_host *host = mmc_priv(mmc); |
| 2136 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 2137 | mrq->data->host_cookie = COOKIE_UNMAPPED; |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2138 | |
| 2139 | if (host->flags & SDHCI_REQ_USE_DMA) |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 2140 | sdhci_pre_dma_transfer(host, mrq->data); |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2141 | } |
| 2142 | |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2143 | static void sdhci_card_event(struct mmc_host *mmc) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2144 | { |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2145 | struct sdhci_host *host = mmc_priv(mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2146 | unsigned long flags; |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 2147 | int present; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2148 | |
Christian Daudt | 722e128 | 2013-06-20 14:26:36 -0700 | [diff] [blame] | 2149 | /* First check if client has provided their own card event */ |
| 2150 | if (host->ops->card_event) |
| 2151 | host->ops->card_event(host); |
| 2152 | |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 2153 | present = sdhci_do_get_cd(host); |
| 2154 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2155 | spin_lock_irqsave(&host->lock, flags); |
| 2156 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2157 | /* Check host->mrq first in case we are runtime suspended */ |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 2158 | if (host->mrq && !present) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2159 | pr_err("%s: Card removed during transfer!\n", |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2160 | mmc_hostname(host->mmc)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2161 | pr_err("%s: Resetting controller.\n", |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2162 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2163 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 2164 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 2165 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2166 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2167 | host->mrq->cmd->error = -ENOMEDIUM; |
| 2168 | tasklet_schedule(&host->finish_tasklet); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2169 | } |
| 2170 | |
| 2171 | spin_unlock_irqrestore(&host->lock, flags); |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2172 | } |
| 2173 | |
| 2174 | static const struct mmc_host_ops sdhci_ops = { |
| 2175 | .request = sdhci_request, |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2176 | .post_req = sdhci_post_req, |
| 2177 | .pre_req = sdhci_pre_req, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2178 | .set_ios = sdhci_set_ios, |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 2179 | .get_cd = sdhci_get_cd, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2180 | .get_ro = sdhci_get_ro, |
| 2181 | .hw_reset = sdhci_hw_reset, |
| 2182 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
| 2183 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2184 | .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2185 | .execute_tuning = sdhci_execute_tuning, |
Adrian Hunter | cb84964 | 2015-02-06 14:12:59 +0200 | [diff] [blame] | 2186 | .select_drive_strength = sdhci_select_drive_strength, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2187 | .card_event = sdhci_card_event, |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2188 | .card_busy = sdhci_card_busy, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2189 | }; |
| 2190 | |
| 2191 | /*****************************************************************************\ |
| 2192 | * * |
| 2193 | * Tasklets * |
| 2194 | * * |
| 2195 | \*****************************************************************************/ |
| 2196 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2197 | static void sdhci_tasklet_finish(unsigned long param) |
| 2198 | { |
| 2199 | struct sdhci_host *host; |
| 2200 | unsigned long flags; |
| 2201 | struct mmc_request *mrq; |
| 2202 | |
| 2203 | host = (struct sdhci_host*)param; |
| 2204 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2205 | spin_lock_irqsave(&host->lock, flags); |
| 2206 | |
Chris Ball | 0c9c99a | 2011-04-27 17:35:31 -0400 | [diff] [blame] | 2207 | /* |
| 2208 | * If this tasklet gets rescheduled while running, it will |
| 2209 | * be run again afterwards but without any active request. |
| 2210 | */ |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2211 | if (!host->mrq) { |
| 2212 | spin_unlock_irqrestore(&host->lock, flags); |
Chris Ball | 0c9c99a | 2011-04-27 17:35:31 -0400 | [diff] [blame] | 2213 | return; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2214 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2215 | |
| 2216 | del_timer(&host->timer); |
| 2217 | |
| 2218 | mrq = host->mrq; |
| 2219 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2220 | /* |
Russell King | 054cedf | 2016-01-26 13:40:42 +0000 | [diff] [blame] | 2221 | * Always unmap the data buffers if they were mapped by |
| 2222 | * sdhci_prepare_data() whenever we finish with a request. |
| 2223 | * This avoids leaking DMA mappings on error. |
| 2224 | */ |
| 2225 | if (host->flags & SDHCI_REQ_USE_DMA) { |
| 2226 | struct mmc_data *data = mrq->data; |
| 2227 | |
| 2228 | if (data && data->host_cookie == COOKIE_MAPPED) { |
| 2229 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
| 2230 | (data->flags & MMC_DATA_READ) ? |
| 2231 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 2232 | data->host_cookie = COOKIE_UNMAPPED; |
| 2233 | } |
| 2234 | } |
| 2235 | |
| 2236 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2237 | * The controller needs a reset of internal state machines |
| 2238 | * upon error conditions. |
| 2239 | */ |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 2240 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
Ben Dooks | b7b4d34 | 2011-04-27 14:24:19 +0100 | [diff] [blame] | 2241 | ((mrq->cmd && mrq->cmd->error) || |
Andrew Gabbasov | fce9d33 | 2014-10-01 07:14:08 -0500 | [diff] [blame] | 2242 | (mrq->sbc && mrq->sbc->error) || |
| 2243 | (mrq->data && ((mrq->data->error && !mrq->data->stop) || |
| 2244 | (mrq->data->stop && mrq->data->stop->error))) || |
| 2245 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 2246 | |
| 2247 | /* Some controllers need this kick or reset won't work here */ |
Andy Shevchenko | 8213af3 | 2013-01-07 16:31:08 +0200 | [diff] [blame] | 2248 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 2249 | /* This is to force an update */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 2250 | host->ops->set_clock(host, host->clock); |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 2251 | |
| 2252 | /* Spec says we should do both at the same time, but Ricoh |
| 2253 | controllers do not like that. */ |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 2254 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 2255 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2256 | } |
| 2257 | |
| 2258 | host->mrq = NULL; |
| 2259 | host->cmd = NULL; |
| 2260 | host->data = NULL; |
| 2261 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 2262 | #ifndef SDHCI_USE_LEDS_CLASS |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2263 | sdhci_deactivate_led(host); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 2264 | #endif |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2265 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 2266 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2267 | spin_unlock_irqrestore(&host->lock, flags); |
| 2268 | |
| 2269 | mmc_request_done(host->mmc, mrq); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2270 | sdhci_runtime_pm_put(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2271 | } |
| 2272 | |
| 2273 | static void sdhci_timeout_timer(unsigned long data) |
| 2274 | { |
| 2275 | struct sdhci_host *host; |
| 2276 | unsigned long flags; |
| 2277 | |
| 2278 | host = (struct sdhci_host*)data; |
| 2279 | |
| 2280 | spin_lock_irqsave(&host->lock, flags); |
| 2281 | |
| 2282 | if (host->mrq) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2283 | pr_err("%s: Timeout waiting for hardware interrupt.\n", |
| 2284 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2285 | sdhci_dumpregs(host); |
| 2286 | |
| 2287 | if (host->data) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2288 | host->data->error = -ETIMEDOUT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2289 | sdhci_finish_data(host); |
| 2290 | } else { |
| 2291 | if (host->cmd) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2292 | host->cmd->error = -ETIMEDOUT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2293 | else |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2294 | host->mrq->cmd->error = -ETIMEDOUT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2295 | |
| 2296 | tasklet_schedule(&host->finish_tasklet); |
| 2297 | } |
| 2298 | } |
| 2299 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 2300 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2301 | spin_unlock_irqrestore(&host->lock, flags); |
| 2302 | } |
| 2303 | |
| 2304 | /*****************************************************************************\ |
| 2305 | * * |
| 2306 | * Interrupt handling * |
| 2307 | * * |
| 2308 | \*****************************************************************************/ |
| 2309 | |
Adrian Hunter | 6154139 | 2014-09-24 10:27:27 +0300 | [diff] [blame] | 2310 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2311 | { |
| 2312 | BUG_ON(intmask == 0); |
| 2313 | |
| 2314 | if (!host->cmd) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2315 | pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", |
| 2316 | mmc_hostname(host->mmc), (unsigned)intmask); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2317 | sdhci_dumpregs(host); |
| 2318 | return; |
| 2319 | } |
| 2320 | |
Russell King | ec014cb | 2016-01-26 13:39:39 +0000 | [diff] [blame] | 2321 | if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | |
| 2322 | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { |
| 2323 | if (intmask & SDHCI_INT_TIMEOUT) |
| 2324 | host->cmd->error = -ETIMEDOUT; |
| 2325 | else |
| 2326 | host->cmd->error = -EILSEQ; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2327 | |
Russell King | 71fcbda | 2016-01-26 13:39:45 +0000 | [diff] [blame] | 2328 | /* |
| 2329 | * If this command initiates a data phase and a response |
| 2330 | * CRC error is signalled, the card can start transferring |
| 2331 | * data - the card may have received the command without |
| 2332 | * error. We must not terminate the mmc_request early. |
| 2333 | * |
| 2334 | * If the card did not receive the command or returned an |
| 2335 | * error which prevented it sending data, the data phase |
| 2336 | * will time out. |
| 2337 | */ |
| 2338 | if (host->cmd->data && |
| 2339 | (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == |
| 2340 | SDHCI_INT_CRC) { |
| 2341 | host->cmd = NULL; |
| 2342 | return; |
| 2343 | } |
| 2344 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2345 | tasklet_schedule(&host->finish_tasklet); |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2346 | return; |
| 2347 | } |
| 2348 | |
| 2349 | /* |
| 2350 | * The host can send and interrupt when the busy state has |
| 2351 | * ended, allowing us to wait without wasting CPU cycles. |
| 2352 | * Unfortunately this is overloaded on the "data complete" |
| 2353 | * interrupt, so we need to take some care when handling |
| 2354 | * it. |
| 2355 | * |
| 2356 | * Note: The 1.0 specification is a bit ambiguous about this |
| 2357 | * feature so there might be some problems with older |
| 2358 | * controllers. |
| 2359 | */ |
| 2360 | if (host->cmd->flags & MMC_RSP_BUSY) { |
| 2361 | if (host->cmd->data) |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2362 | DBG("Cannot wait for busy signal when also doing a data transfer"); |
Chanho Min | e99783a | 2014-08-30 12:40:40 +0900 | [diff] [blame] | 2363 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) |
| 2364 | && !host->busy_handle) { |
| 2365 | /* Mark that command complete before busy is ended */ |
| 2366 | host->busy_handle = 1; |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2367 | return; |
Chanho Min | e99783a | 2014-08-30 12:40:40 +0900 | [diff] [blame] | 2368 | } |
Ben Dooks | f945405 | 2009-02-20 20:33:08 +0300 | [diff] [blame] | 2369 | |
| 2370 | /* The controller does not support the end-of-busy IRQ, |
| 2371 | * fall through and take the SDHCI_INT_RESPONSE */ |
Adrian Hunter | 6154139 | 2014-09-24 10:27:27 +0300 | [diff] [blame] | 2372 | } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && |
| 2373 | host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) { |
| 2374 | *mask &= ~SDHCI_INT_DATA_END; |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2375 | } |
| 2376 | |
| 2377 | if (intmask & SDHCI_INT_RESPONSE) |
Pierre Ossman | 43b58b3 | 2007-07-25 23:15:27 +0200 | [diff] [blame] | 2378 | sdhci_finish_command(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2379 | } |
| 2380 | |
George G. Davis | 0957c33 | 2010-02-18 12:32:12 -0500 | [diff] [blame] | 2381 | #ifdef CONFIG_MMC_DEBUG |
Adrian Hunter | 08621b1 | 2014-11-04 12:42:38 +0200 | [diff] [blame] | 2382 | static void sdhci_adma_show_error(struct sdhci_host *host) |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2383 | { |
| 2384 | const char *name = mmc_hostname(host->mmc); |
Adrian Hunter | 1c3d5f6 | 2014-11-04 12:42:41 +0200 | [diff] [blame] | 2385 | void *desc = host->adma_table; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2386 | |
| 2387 | sdhci_dumpregs(host); |
| 2388 | |
| 2389 | while (true) { |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2390 | struct sdhci_adma2_64_desc *dma_desc = desc; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2391 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2392 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 2393 | DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", |
| 2394 | name, desc, le32_to_cpu(dma_desc->addr_hi), |
| 2395 | le32_to_cpu(dma_desc->addr_lo), |
| 2396 | le16_to_cpu(dma_desc->len), |
| 2397 | le16_to_cpu(dma_desc->cmd)); |
| 2398 | else |
| 2399 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", |
| 2400 | name, desc, le32_to_cpu(dma_desc->addr_lo), |
| 2401 | le16_to_cpu(dma_desc->len), |
| 2402 | le16_to_cpu(dma_desc->cmd)); |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2403 | |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 2404 | desc += host->desc_sz; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2405 | |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 2406 | if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2407 | break; |
| 2408 | } |
| 2409 | } |
| 2410 | #else |
Adrian Hunter | 08621b1 | 2014-11-04 12:42:38 +0200 | [diff] [blame] | 2411 | static void sdhci_adma_show_error(struct sdhci_host *host) { } |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2412 | #endif |
| 2413 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2414 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
| 2415 | { |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2416 | u32 command; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2417 | BUG_ON(intmask == 0); |
| 2418 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2419 | /* CMD19 generates _only_ Buffer Read Ready interrupt */ |
| 2420 | if (intmask & SDHCI_INT_DATA_AVAIL) { |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2421 | command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); |
| 2422 | if (command == MMC_SEND_TUNING_BLOCK || |
| 2423 | command == MMC_SEND_TUNING_BLOCK_HS200) { |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2424 | host->tuning_done = 1; |
| 2425 | wake_up(&host->buf_ready_int); |
| 2426 | return; |
| 2427 | } |
| 2428 | } |
| 2429 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2430 | if (!host->data) { |
| 2431 | /* |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2432 | * The "data complete" interrupt is also used to |
| 2433 | * indicate that a busy state has ended. See comment |
| 2434 | * above in sdhci_cmd_irq(). |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2435 | */ |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2436 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
Matthieu CASTET | c5abd5e | 2014-08-14 16:03:17 +0200 | [diff] [blame] | 2437 | if (intmask & SDHCI_INT_DATA_TIMEOUT) { |
| 2438 | host->cmd->error = -ETIMEDOUT; |
| 2439 | tasklet_schedule(&host->finish_tasklet); |
| 2440 | return; |
| 2441 | } |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2442 | if (intmask & SDHCI_INT_DATA_END) { |
Chanho Min | e99783a | 2014-08-30 12:40:40 +0900 | [diff] [blame] | 2443 | /* |
| 2444 | * Some cards handle busy-end interrupt |
| 2445 | * before the command completed, so make |
| 2446 | * sure we do things in the proper order. |
| 2447 | */ |
| 2448 | if (host->busy_handle) |
| 2449 | sdhci_finish_command(host); |
| 2450 | else |
| 2451 | host->busy_handle = 1; |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2452 | return; |
| 2453 | } |
| 2454 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2455 | |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2456 | pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", |
| 2457 | mmc_hostname(host->mmc), (unsigned)intmask); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2458 | sdhci_dumpregs(host); |
| 2459 | |
| 2460 | return; |
| 2461 | } |
| 2462 | |
| 2463 | if (intmask & SDHCI_INT_DATA_TIMEOUT) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2464 | host->data->error = -ETIMEDOUT; |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 2465 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
| 2466 | host->data->error = -EILSEQ; |
| 2467 | else if ((intmask & SDHCI_INT_DATA_CRC) && |
| 2468 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) |
| 2469 | != MMC_BUS_TEST_R) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2470 | host->data->error = -EILSEQ; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2471 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2472 | pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); |
Adrian Hunter | 08621b1 | 2014-11-04 12:42:38 +0200 | [diff] [blame] | 2473 | sdhci_adma_show_error(host); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2474 | host->data->error = -EIO; |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 2475 | if (host->ops->adma_workaround) |
| 2476 | host->ops->adma_workaround(host, intmask); |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2477 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2478 | |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2479 | if (host->data->error) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2480 | sdhci_finish_data(host); |
| 2481 | else { |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 2482 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2483 | sdhci_transfer_pio(host); |
| 2484 | |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2485 | /* |
| 2486 | * We currently don't do anything fancy with DMA |
| 2487 | * boundaries, but as we can't disable the feature |
| 2488 | * we need to at least restart the transfer. |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 2489 | * |
| 2490 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) |
| 2491 | * should return a valid address to continue from, but as |
| 2492 | * some controllers are faulty, don't trust them. |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2493 | */ |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 2494 | if (intmask & SDHCI_INT_DMA_END) { |
| 2495 | u32 dmastart, dmanow; |
| 2496 | dmastart = sg_dma_address(host->data->sg); |
| 2497 | dmanow = dmastart + host->data->bytes_xfered; |
| 2498 | /* |
| 2499 | * Force update to the next DMA block boundary. |
| 2500 | */ |
| 2501 | dmanow = (dmanow & |
| 2502 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + |
| 2503 | SDHCI_DEFAULT_BOUNDARY_SIZE; |
| 2504 | host->data->bytes_xfered = dmanow - dmastart; |
| 2505 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," |
| 2506 | " next 0x%08x\n", |
| 2507 | mmc_hostname(host->mmc), dmastart, |
| 2508 | host->data->bytes_xfered, dmanow); |
| 2509 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); |
| 2510 | } |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2511 | |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 2512 | if (intmask & SDHCI_INT_DATA_END) { |
| 2513 | if (host->cmd) { |
| 2514 | /* |
| 2515 | * Data managed to finish before the |
| 2516 | * command completed. Make sure we do |
| 2517 | * things in the proper order. |
| 2518 | */ |
| 2519 | host->data_early = 1; |
| 2520 | } else { |
| 2521 | sdhci_finish_data(host); |
| 2522 | } |
| 2523 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2524 | } |
| 2525 | } |
| 2526 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 2527 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2528 | { |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2529 | irqreturn_t result = IRQ_NONE; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2530 | struct sdhci_host *host = dev_id; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2531 | u32 intmask, mask, unexpected = 0; |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2532 | int max_loops = 16; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2533 | |
| 2534 | spin_lock(&host->lock); |
| 2535 | |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 2536 | if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2537 | spin_unlock(&host->lock); |
Adrian Hunter | 655bca7 | 2014-03-11 10:09:36 +0200 | [diff] [blame] | 2538 | return IRQ_NONE; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2539 | } |
| 2540 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2541 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
Mark Lord | 62df67a5 | 2007-03-06 13:30:13 +0100 | [diff] [blame] | 2542 | if (!intmask || intmask == 0xffffffff) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2543 | result = IRQ_NONE; |
| 2544 | goto out; |
| 2545 | } |
| 2546 | |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2547 | do { |
| 2548 | /* Clear selected interrupts. */ |
| 2549 | mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | |
| 2550 | SDHCI_INT_BUS_POWER); |
| 2551 | sdhci_writel(host, mask, SDHCI_INT_STATUS); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2552 | |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2553 | DBG("*** %s got interrupt: 0x%08x\n", |
| 2554 | mmc_hostname(host->mmc), intmask); |
| 2555 | |
| 2556 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
| 2557 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
| 2558 | SDHCI_CARD_PRESENT; |
| 2559 | |
| 2560 | /* |
| 2561 | * There is a observation on i.mx esdhc. INSERT |
| 2562 | * bit will be immediately set again when it gets |
| 2563 | * cleared, if a card is inserted. We have to mask |
| 2564 | * the irq to prevent interrupt storm which will |
| 2565 | * freeze the system. And the REMOVE gets the |
| 2566 | * same situation. |
| 2567 | * |
| 2568 | * More testing are needed here to ensure it works |
| 2569 | * for other platforms though. |
| 2570 | */ |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2571 | host->ier &= ~(SDHCI_INT_CARD_INSERT | |
| 2572 | SDHCI_INT_CARD_REMOVE); |
| 2573 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
| 2574 | SDHCI_INT_CARD_INSERT; |
| 2575 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 2576 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2577 | |
| 2578 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
| 2579 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); |
Russell King | 3560db8 | 2014-04-25 12:55:51 +0100 | [diff] [blame] | 2580 | |
| 2581 | host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | |
| 2582 | SDHCI_INT_CARD_REMOVE); |
| 2583 | result = IRQ_WAKE_THREAD; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2584 | } |
| 2585 | |
| 2586 | if (intmask & SDHCI_INT_CMD_MASK) |
Adrian Hunter | 6154139 | 2014-09-24 10:27:27 +0300 | [diff] [blame] | 2587 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, |
| 2588 | &intmask); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2589 | |
| 2590 | if (intmask & SDHCI_INT_DATA_MASK) |
| 2591 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
| 2592 | |
| 2593 | if (intmask & SDHCI_INT_BUS_POWER) |
| 2594 | pr_err("%s: Card is consuming too much power!\n", |
| 2595 | mmc_hostname(host->mmc)); |
| 2596 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2597 | if (intmask & SDHCI_INT_CARD_INT) { |
| 2598 | sdhci_enable_sdio_irq_nolock(host, false); |
| 2599 | host->thread_isr |= SDHCI_INT_CARD_INT; |
| 2600 | result = IRQ_WAKE_THREAD; |
| 2601 | } |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2602 | |
| 2603 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
| 2604 | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | |
| 2605 | SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | |
| 2606 | SDHCI_INT_CARD_INT); |
| 2607 | |
| 2608 | if (intmask) { |
| 2609 | unexpected |= intmask; |
| 2610 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
| 2611 | } |
| 2612 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2613 | if (result == IRQ_NONE) |
| 2614 | result = IRQ_HANDLED; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2615 | |
| 2616 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2617 | } while (intmask && --max_loops); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2618 | out: |
| 2619 | spin_unlock(&host->lock); |
| 2620 | |
Alexander Stein | 6379b23 | 2012-03-14 09:52:10 +0100 | [diff] [blame] | 2621 | if (unexpected) { |
| 2622 | pr_err("%s: Unexpected interrupt 0x%08x.\n", |
| 2623 | mmc_hostname(host->mmc), unexpected); |
| 2624 | sdhci_dumpregs(host); |
| 2625 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 2626 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2627 | return result; |
| 2628 | } |
| 2629 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2630 | static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) |
| 2631 | { |
| 2632 | struct sdhci_host *host = dev_id; |
| 2633 | unsigned long flags; |
| 2634 | u32 isr; |
| 2635 | |
| 2636 | spin_lock_irqsave(&host->lock, flags); |
| 2637 | isr = host->thread_isr; |
| 2638 | host->thread_isr = 0; |
| 2639 | spin_unlock_irqrestore(&host->lock, flags); |
| 2640 | |
Russell King | 3560db8 | 2014-04-25 12:55:51 +0100 | [diff] [blame] | 2641 | if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
| 2642 | sdhci_card_event(host->mmc); |
| 2643 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); |
| 2644 | } |
| 2645 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2646 | if (isr & SDHCI_INT_CARD_INT) { |
| 2647 | sdio_run_irqs(host->mmc); |
| 2648 | |
| 2649 | spin_lock_irqsave(&host->lock, flags); |
| 2650 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
| 2651 | sdhci_enable_sdio_irq_nolock(host, true); |
| 2652 | spin_unlock_irqrestore(&host->lock, flags); |
| 2653 | } |
| 2654 | |
| 2655 | return isr ? IRQ_HANDLED : IRQ_NONE; |
| 2656 | } |
| 2657 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2658 | /*****************************************************************************\ |
| 2659 | * * |
| 2660 | * Suspend/resume * |
| 2661 | * * |
| 2662 | \*****************************************************************************/ |
| 2663 | |
| 2664 | #ifdef CONFIG_PM |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2665 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
| 2666 | { |
| 2667 | u8 val; |
| 2668 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
| 2669 | | SDHCI_WAKE_ON_INT; |
| 2670 | |
| 2671 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); |
| 2672 | val |= mask ; |
| 2673 | /* Avoid fake wake up */ |
| 2674 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
| 2675 | val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); |
| 2676 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); |
| 2677 | } |
| 2678 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); |
| 2679 | |
Fabio Estevam | 0b10f47 | 2014-08-30 14:53:13 -0300 | [diff] [blame] | 2680 | static void sdhci_disable_irq_wakeups(struct sdhci_host *host) |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2681 | { |
| 2682 | u8 val; |
| 2683 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
| 2684 | | SDHCI_WAKE_ON_INT; |
| 2685 | |
| 2686 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); |
| 2687 | val &= ~mask; |
| 2688 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); |
| 2689 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2690 | |
Manuel Lauss | 29495aa | 2011-11-03 11:09:45 +0100 | [diff] [blame] | 2691 | int sdhci_suspend_host(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2692 | { |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 2693 | sdhci_disable_card_detection(host); |
| 2694 | |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2695 | mmc_retune_timer_stop(host->mmc); |
| 2696 | mmc_retune_needed(host->mmc); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2697 | |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2698 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2699 | host->ier = 0; |
| 2700 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 2701 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2702 | free_irq(host->irq, host); |
| 2703 | } else { |
| 2704 | sdhci_enable_irq_wakeups(host); |
| 2705 | enable_irq_wake(host->irq); |
| 2706 | } |
Ulf Hansson | 4ee14ec | 2013-09-25 14:15:24 +0200 | [diff] [blame] | 2707 | return 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2708 | } |
| 2709 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2710 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2711 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2712 | int sdhci_resume_host(struct sdhci_host *host) |
| 2713 | { |
Ulf Hansson | 4ee14ec | 2013-09-25 14:15:24 +0200 | [diff] [blame] | 2714 | int ret = 0; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2715 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2716 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2717 | if (host->ops->enable_dma) |
| 2718 | host->ops->enable_dma(host); |
| 2719 | } |
| 2720 | |
Adrian Hunter | 6308d29 | 2012-02-07 14:48:54 +0200 | [diff] [blame] | 2721 | if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && |
| 2722 | (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { |
| 2723 | /* Card keeps power but host controller does not */ |
| 2724 | sdhci_init(host, 0); |
| 2725 | host->pwr = 0; |
| 2726 | host->clock = 0; |
| 2727 | sdhci_do_set_ios(host, &host->mmc->ios); |
| 2728 | } else { |
| 2729 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); |
| 2730 | mmiowb(); |
| 2731 | } |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2732 | |
Haibo Chen | 14a7b4164 | 2015-09-15 18:32:58 +0800 | [diff] [blame] | 2733 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
| 2734 | ret = request_threaded_irq(host->irq, sdhci_irq, |
| 2735 | sdhci_thread_irq, IRQF_SHARED, |
| 2736 | mmc_hostname(host->mmc), host); |
| 2737 | if (ret) |
| 2738 | return ret; |
| 2739 | } else { |
| 2740 | sdhci_disable_irq_wakeups(host); |
| 2741 | disable_irq_wake(host->irq); |
| 2742 | } |
| 2743 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 2744 | sdhci_enable_card_detection(host); |
| 2745 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 2746 | return ret; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2747 | } |
| 2748 | |
| 2749 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2750 | |
| 2751 | static int sdhci_runtime_pm_get(struct sdhci_host *host) |
| 2752 | { |
| 2753 | return pm_runtime_get_sync(host->mmc->parent); |
| 2754 | } |
| 2755 | |
| 2756 | static int sdhci_runtime_pm_put(struct sdhci_host *host) |
| 2757 | { |
| 2758 | pm_runtime_mark_last_busy(host->mmc->parent); |
| 2759 | return pm_runtime_put_autosuspend(host->mmc->parent); |
| 2760 | } |
| 2761 | |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 2762 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
| 2763 | { |
Adrian Hunter | 5c671c4 | 2015-11-26 14:00:50 +0200 | [diff] [blame] | 2764 | if (host->bus_on) |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 2765 | return; |
| 2766 | host->bus_on = true; |
| 2767 | pm_runtime_get_noresume(host->mmc->parent); |
| 2768 | } |
| 2769 | |
| 2770 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) |
| 2771 | { |
Adrian Hunter | 5c671c4 | 2015-11-26 14:00:50 +0200 | [diff] [blame] | 2772 | if (!host->bus_on) |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 2773 | return; |
| 2774 | host->bus_on = false; |
| 2775 | pm_runtime_put_noidle(host->mmc->parent); |
| 2776 | } |
| 2777 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2778 | int sdhci_runtime_suspend_host(struct sdhci_host *host) |
| 2779 | { |
| 2780 | unsigned long flags; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2781 | |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2782 | mmc_retune_timer_stop(host->mmc); |
| 2783 | mmc_retune_needed(host->mmc); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2784 | |
| 2785 | spin_lock_irqsave(&host->lock, flags); |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2786 | host->ier &= SDHCI_INT_CARD_INT; |
| 2787 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 2788 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2789 | spin_unlock_irqrestore(&host->lock, flags); |
| 2790 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2791 | synchronize_hardirq(host->irq); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2792 | |
| 2793 | spin_lock_irqsave(&host->lock, flags); |
| 2794 | host->runtime_suspended = true; |
| 2795 | spin_unlock_irqrestore(&host->lock, flags); |
| 2796 | |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 2797 | return 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2798 | } |
| 2799 | EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); |
| 2800 | |
| 2801 | int sdhci_runtime_resume_host(struct sdhci_host *host) |
| 2802 | { |
| 2803 | unsigned long flags; |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 2804 | int host_flags = host->flags; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2805 | |
| 2806 | if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
| 2807 | if (host->ops->enable_dma) |
| 2808 | host->ops->enable_dma(host); |
| 2809 | } |
| 2810 | |
| 2811 | sdhci_init(host, 0); |
| 2812 | |
| 2813 | /* Force clock and power re-program */ |
| 2814 | host->pwr = 0; |
| 2815 | host->clock = 0; |
Jisheng Zhang | 3396e73 | 2015-01-29 17:42:12 +0800 | [diff] [blame] | 2816 | sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2817 | sdhci_do_set_ios(host, &host->mmc->ios); |
| 2818 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2819 | if ((host_flags & SDHCI_PV_ENABLED) && |
| 2820 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { |
| 2821 | spin_lock_irqsave(&host->lock, flags); |
| 2822 | sdhci_enable_preset_value(host, true); |
| 2823 | spin_unlock_irqrestore(&host->lock, flags); |
| 2824 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2825 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2826 | spin_lock_irqsave(&host->lock, flags); |
| 2827 | |
| 2828 | host->runtime_suspended = false; |
| 2829 | |
| 2830 | /* Enable SDIO IRQ */ |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 2831 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2832 | sdhci_enable_sdio_irq_nolock(host, true); |
| 2833 | |
| 2834 | /* Enable Card Detection */ |
| 2835 | sdhci_enable_card_detection(host); |
| 2836 | |
| 2837 | spin_unlock_irqrestore(&host->lock, flags); |
| 2838 | |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 2839 | return 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2840 | } |
| 2841 | EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); |
| 2842 | |
Rafael J. Wysocki | 162d6f9 | 2014-12-05 03:05:33 +0100 | [diff] [blame] | 2843 | #endif /* CONFIG_PM */ |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2844 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2845 | /*****************************************************************************\ |
| 2846 | * * |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2847 | * Device allocation/registration * |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2848 | * * |
| 2849 | \*****************************************************************************/ |
| 2850 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2851 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
| 2852 | size_t priv_size) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2853 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2854 | struct mmc_host *mmc; |
| 2855 | struct sdhci_host *host; |
| 2856 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2857 | WARN_ON(dev == NULL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2858 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2859 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2860 | if (!mmc) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2861 | return ERR_PTR(-ENOMEM); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2862 | |
| 2863 | host = mmc_priv(mmc); |
| 2864 | host->mmc = mmc; |
Adrian Hunter | bf60e59 | 2016-02-09 16:12:35 +0200 | [diff] [blame] | 2865 | host->mmc_host_ops = sdhci_ops; |
| 2866 | mmc->ops = &host->mmc_host_ops; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2867 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2868 | return host; |
| 2869 | } |
Pierre Ossman | 8a4da14 | 2006-10-04 02:15:40 -0700 | [diff] [blame] | 2870 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2871 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2872 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2873 | int sdhci_add_host(struct sdhci_host *host) |
| 2874 | { |
| 2875 | struct mmc_host *mmc; |
Philip Rakity | bd6a8c3 | 2012-06-27 21:49:27 -0700 | [diff] [blame] | 2876 | u32 caps[2] = {0, 0}; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2877 | u32 max_current_caps; |
| 2878 | unsigned int ocr_avail; |
Adrian Hunter | f5fa92e | 2014-09-24 10:27:32 +0300 | [diff] [blame] | 2879 | unsigned int override_timeout_clk; |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 2880 | u32 max_clk; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2881 | int ret; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2882 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2883 | WARN_ON(host == NULL); |
| 2884 | if (host == NULL) |
| 2885 | return -EINVAL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2886 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2887 | mmc = host->mmc; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2888 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2889 | if (debug_quirks) |
| 2890 | host->quirks = debug_quirks; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2891 | if (debug_quirks2) |
| 2892 | host->quirks2 = debug_quirks2; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2893 | |
Adrian Hunter | f5fa92e | 2014-09-24 10:27:32 +0300 | [diff] [blame] | 2894 | override_timeout_clk = host->timeout_clk; |
| 2895 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 2896 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Pierre Ossman | d96649e | 2006-06-30 02:22:30 -0700 | [diff] [blame] | 2897 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2898 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2899 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
| 2900 | >> SDHCI_SPEC_VER_SHIFT; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 2901 | if (host->version > SDHCI_SPEC_300) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2902 | pr_err("%s: Unknown controller version (%d). You may experience problems.\n", |
| 2903 | mmc_hostname(mmc), host->version); |
Pierre Ossman | 4a96550 | 2006-06-30 02:22:29 -0700 | [diff] [blame] | 2904 | } |
| 2905 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2906 | caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
Maxim Levitsky | ccc92c2 | 2010-08-10 18:01:42 -0700 | [diff] [blame] | 2907 | sdhci_readl(host, SDHCI_CAPABILITIES); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2908 | |
Philip Rakity | bd6a8c3 | 2012-06-27 21:49:27 -0700 | [diff] [blame] | 2909 | if (host->version >= SDHCI_SPEC_300) |
| 2910 | caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? |
| 2911 | host->caps1 : |
| 2912 | sdhci_readl(host, SDHCI_CAPABILITIES_1); |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2913 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2914 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2915 | host->flags |= SDHCI_USE_SDMA; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2916 | else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2917 | DBG("Controller doesn't have SDMA capability\n"); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 2918 | else |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2919 | host->flags |= SDHCI_USE_SDMA; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2920 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2921 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2922 | (host->flags & SDHCI_USE_SDMA)) { |
Rolf Eike Beer | cee687c | 2007-11-02 15:22:30 +0100 | [diff] [blame] | 2923 | DBG("Disabling DMA as it is marked broken\n"); |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2924 | host->flags &= ~SDHCI_USE_SDMA; |
Feng Tang | 7c168e3 | 2007-09-30 12:44:18 +0200 | [diff] [blame] | 2925 | } |
| 2926 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2927 | if ((host->version >= SDHCI_SPEC_200) && |
| 2928 | (caps[0] & SDHCI_CAN_DO_ADMA2)) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2929 | host->flags |= SDHCI_USE_ADMA; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2930 | |
| 2931 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && |
| 2932 | (host->flags & SDHCI_USE_ADMA)) { |
| 2933 | DBG("Disabling ADMA as it is marked broken\n"); |
| 2934 | host->flags &= ~SDHCI_USE_ADMA; |
| 2935 | } |
| 2936 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2937 | /* |
| 2938 | * It is assumed that a 64-bit capable device has set a 64-bit DMA mask |
| 2939 | * and *must* do 64-bit DMA. A driver has the opportunity to change |
| 2940 | * that during the first call to ->enable_dma(). Similarly |
| 2941 | * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to |
| 2942 | * implement. |
| 2943 | */ |
Al Cooper | 5eaa747 | 2016-02-10 15:25:39 -0500 | [diff] [blame] | 2944 | if (caps[0] & SDHCI_CAN_64BIT) |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2945 | host->flags |= SDHCI_USE_64_BIT_DMA; |
| 2946 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2947 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2948 | if (host->ops->enable_dma) { |
| 2949 | if (host->ops->enable_dma(host)) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 2950 | pr_warn("%s: No suitable DMA available - falling back to PIO\n", |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2951 | mmc_hostname(mmc)); |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2952 | host->flags &= |
| 2953 | ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2954 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2955 | } |
| 2956 | } |
| 2957 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2958 | /* SDMA does not support 64-bit DMA */ |
| 2959 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 2960 | host->flags &= ~SDHCI_USE_SDMA; |
| 2961 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2962 | if (host->flags & SDHCI_USE_ADMA) { |
| 2963 | /* |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 2964 | * The DMA descriptor table size is calculated as the maximum |
| 2965 | * number of segments times 2, to allow for an alignment |
| 2966 | * descriptor for each segment, plus 1 for a nop end descriptor, |
| 2967 | * all multipled by the descriptor size. |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2968 | */ |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2969 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
| 2970 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * |
| 2971 | SDHCI_ADMA2_64_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2972 | host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2973 | } else { |
| 2974 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * |
| 2975 | SDHCI_ADMA2_32_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2976 | host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2977 | } |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 2978 | host->adma_table = dma_alloc_coherent(mmc_dev(mmc), |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 2979 | host->adma_table_sz, |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 2980 | &host->adma_addr, |
| 2981 | GFP_KERNEL); |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 2982 | host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 2983 | host->align_buffer = dma_alloc_coherent(mmc_dev(mmc), |
| 2984 | host->align_buffer_sz, |
| 2985 | &host->align_addr, |
| 2986 | GFP_KERNEL); |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 2987 | if (!host->adma_table || !host->align_buffer) { |
Peng Fan | 7ac0203 | 2015-06-22 11:41:23 +0800 | [diff] [blame] | 2988 | if (host->adma_table) |
| 2989 | dma_free_coherent(mmc_dev(mmc), |
| 2990 | host->adma_table_sz, |
| 2991 | host->adma_table, |
| 2992 | host->adma_addr); |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 2993 | if (host->align_buffer) |
| 2994 | dma_free_coherent(mmc_dev(mmc), |
| 2995 | host->align_buffer_sz, |
| 2996 | host->align_buffer, |
| 2997 | host->align_addr); |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 2998 | pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2999 | mmc_hostname(mmc)); |
| 3000 | host->flags &= ~SDHCI_USE_ADMA; |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 3001 | host->adma_table = NULL; |
Russell King | d1e49f7 | 2014-04-25 12:58:34 +0100 | [diff] [blame] | 3002 | host->align_buffer = NULL; |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 3003 | } else if (host->adma_addr & (SDHCI_ADMA2_DESC_ALIGN - 1)) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 3004 | pr_warn("%s: unable to allocate aligned ADMA descriptor\n", |
| 3005 | mmc_hostname(mmc)); |
Russell King | d1e49f7 | 2014-04-25 12:58:34 +0100 | [diff] [blame] | 3006 | host->flags &= ~SDHCI_USE_ADMA; |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 3007 | dma_free_coherent(mmc_dev(mmc), host->adma_table_sz, |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 3008 | host->adma_table, host->adma_addr); |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 3009 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz, |
| 3010 | host->align_buffer, host->align_addr); |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 3011 | host->adma_table = NULL; |
Russell King | d1e49f7 | 2014-04-25 12:58:34 +0100 | [diff] [blame] | 3012 | host->align_buffer = NULL; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3013 | } |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 3014 | |
| 3015 | /* dma_alloc_coherent returns page aligned and sized buffers */ |
| 3016 | BUG_ON(host->align_addr & SDHCI_ADMA2_MASK); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3017 | } |
| 3018 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 3019 | /* |
| 3020 | * If we use DMA, then it's up to the caller to set the DMA |
| 3021 | * mask, but PIO does not need the hw shim so we set a new |
| 3022 | * mask here in that case. |
| 3023 | */ |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3024 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 3025 | host->dma_mask = DMA_BIT_MASK(64); |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 3026 | mmc_dev(mmc)->dma_mask = &host->dma_mask; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 3027 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3028 | |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 3029 | if (host->version >= SDHCI_SPEC_300) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3030 | host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 3031 | >> SDHCI_CLOCK_BASE_SHIFT; |
| 3032 | else |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3033 | host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 3034 | >> SDHCI_CLOCK_BASE_SHIFT; |
| 3035 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3036 | host->max_clk *= 1000000; |
Anton Vorontsov | f27f47e | 2010-05-26 14:41:53 -0700 | [diff] [blame] | 3037 | if (host->max_clk == 0 || host->quirks & |
| 3038 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 3039 | if (!host->ops->get_max_clock) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 3040 | pr_err("%s: Hardware doesn't specify base clock frequency.\n", |
| 3041 | mmc_hostname(mmc)); |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 3042 | return -ENODEV; |
| 3043 | } |
| 3044 | host->max_clk = host->ops->get_max_clock(host); |
| 3045 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3046 | |
| 3047 | /* |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 3048 | * In case of Host Controller v3.00, find out whether clock |
| 3049 | * multiplier is supported. |
| 3050 | */ |
| 3051 | host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> |
| 3052 | SDHCI_CLOCK_MUL_SHIFT; |
| 3053 | |
| 3054 | /* |
| 3055 | * In case the value in Clock Multiplier is 0, then programmable |
| 3056 | * clock mode is not supported, otherwise the actual clock |
| 3057 | * multiplier is one more than the value of Clock Multiplier |
| 3058 | * in the Capabilities Register. |
| 3059 | */ |
| 3060 | if (host->clk_mul) |
| 3061 | host->clk_mul += 1; |
| 3062 | |
| 3063 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3064 | * Set host parameters. |
| 3065 | */ |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 3066 | max_clk = host->max_clk; |
| 3067 | |
Marek Szyprowski | ce5f036 | 2010-08-10 18:01:56 -0700 | [diff] [blame] | 3068 | if (host->ops->get_min_clock) |
Anton Vorontsov | a9e58f2 | 2009-07-29 15:04:16 -0700 | [diff] [blame] | 3069 | mmc->f_min = host->ops->get_min_clock(host); |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 3070 | else if (host->version >= SDHCI_SPEC_300) { |
| 3071 | if (host->clk_mul) { |
| 3072 | mmc->f_min = (host->max_clk * host->clk_mul) / 1024; |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 3073 | max_clk = host->max_clk * host->clk_mul; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 3074 | } else |
| 3075 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; |
| 3076 | } else |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 3077 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 3078 | |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 3079 | if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk))) |
| 3080 | mmc->f_max = max_clk; |
| 3081 | |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3082 | if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { |
| 3083 | host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> |
| 3084 | SDHCI_TIMEOUT_CLK_SHIFT; |
| 3085 | if (host->timeout_clk == 0) { |
| 3086 | if (host->ops->get_timeout_clock) { |
| 3087 | host->timeout_clk = |
| 3088 | host->ops->get_timeout_clock(host); |
| 3089 | } else { |
| 3090 | pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", |
| 3091 | mmc_hostname(mmc)); |
| 3092 | return -ENODEV; |
| 3093 | } |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 3094 | } |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 3095 | |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3096 | if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) |
| 3097 | host->timeout_clk *= 1000; |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 3098 | |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3099 | mmc->max_busy_timeout = host->ops->get_max_timeout_count ? |
Aisheng Dong | a6ff5ae | 2014-08-27 15:26:27 +0800 | [diff] [blame] | 3100 | host->ops->get_max_timeout_count(host) : 1 << 27; |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3101 | mmc->max_busy_timeout /= host->timeout_clk; |
| 3102 | } |
Adrian Hunter | 58d1246 | 2011-06-28 17:16:03 +0300 | [diff] [blame] | 3103 | |
Adrian Hunter | f5fa92e | 2014-09-24 10:27:32 +0300 | [diff] [blame] | 3104 | if (override_timeout_clk) |
| 3105 | host->timeout_clk = override_timeout_clk; |
| 3106 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 3107 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3108 | mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 3109 | |
| 3110 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) |
| 3111 | host->flags |= SDHCI_AUTO_CMD12; |
Anton Vorontsov | 5fe23c7 | 2009-06-18 00:14:08 +0400 | [diff] [blame] | 3112 | |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 3113 | /* Auto-CMD23 stuff only works in ADMA or PIO. */ |
Andrei Warkentin | 4f3d3e9 | 2011-05-25 10:42:50 -0400 | [diff] [blame] | 3114 | if ((host->version >= SDHCI_SPEC_300) && |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 3115 | ((host->flags & SDHCI_USE_ADMA) || |
Scott Branden | 3bfa6f0 | 2015-02-09 16:06:28 -0800 | [diff] [blame] | 3116 | !(host->flags & SDHCI_USE_SDMA)) && |
| 3117 | !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 3118 | host->flags |= SDHCI_AUTO_CMD23; |
| 3119 | DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); |
| 3120 | } else { |
| 3121 | DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); |
| 3122 | } |
| 3123 | |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 3124 | /* |
| 3125 | * A controller may support 8-bit width, but the board itself |
| 3126 | * might not have the pins brought out. Boards that support |
| 3127 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in |
| 3128 | * their platform code before calling sdhci_add_host(), and we |
| 3129 | * won't assume 8-bit width for hosts without that CAP. |
| 3130 | */ |
Anton Vorontsov | 5fe23c7 | 2009-06-18 00:14:08 +0400 | [diff] [blame] | 3131 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 3132 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3133 | |
Jerry Huang | 63ef5d8 | 2012-10-25 13:47:19 +0800 | [diff] [blame] | 3134 | if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) |
| 3135 | mmc->caps &= ~MMC_CAP_CMD23; |
| 3136 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3137 | if (caps[0] & SDHCI_CAN_DO_HISPD) |
Zhangfei Gao | a29e7e1 | 2010-08-16 21:15:32 -0400 | [diff] [blame] | 3138 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 3139 | |
Jaehoon Chung | 176d1ed | 2010-09-27 09:42:20 +0100 | [diff] [blame] | 3140 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
Ivan T. Ivanov | c31d22e | 2015-07-06 15:16:20 +0300 | [diff] [blame] | 3141 | !(mmc->caps & MMC_CAP_NONREMOVABLE) && |
| 3142 | IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc))) |
Anton Vorontsov | 68d1fb7 | 2009-03-17 00:13:52 +0300 | [diff] [blame] | 3143 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
| 3144 | |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3145 | /* If there are external regulators, get them */ |
| 3146 | if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER) |
| 3147 | return -EPROBE_DEFER; |
| 3148 | |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 3149 | /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3150 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 3151 | ret = regulator_enable(mmc->supply.vqmmc); |
| 3152 | if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, |
| 3153 | 1950000)) |
Kevin Liu | 8363c37 | 2012-11-17 17:55:51 -0500 | [diff] [blame] | 3154 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | |
| 3155 | SDHCI_SUPPORT_SDR50 | |
| 3156 | SDHCI_SUPPORT_DDR50); |
Chris Ball | a3361ab | 2013-03-11 17:51:53 -0400 | [diff] [blame] | 3157 | if (ret) { |
| 3158 | pr_warn("%s: Failed to enable vqmmc regulator: %d\n", |
| 3159 | mmc_hostname(mmc), ret); |
Adrian Hunter | 4bb7431 | 2014-11-06 15:19:04 +0200 | [diff] [blame] | 3160 | mmc->supply.vqmmc = ERR_PTR(-EINVAL); |
Chris Ball | a3361ab | 2013-03-11 17:51:53 -0400 | [diff] [blame] | 3161 | } |
Kevin Liu | 8363c37 | 2012-11-17 17:55:51 -0500 | [diff] [blame] | 3162 | } |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 3163 | |
Daniel Drake | 6a66180 | 2012-11-25 13:01:19 -0500 | [diff] [blame] | 3164 | if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) |
| 3165 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | |
| 3166 | SDHCI_SUPPORT_DDR50); |
| 3167 | |
Al Cooper | 4188bba | 2012-03-16 15:54:17 -0400 | [diff] [blame] | 3168 | /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ |
| 3169 | if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | |
| 3170 | SDHCI_SUPPORT_DDR50)) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3171 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
| 3172 | |
| 3173 | /* SDR104 supports also implies SDR50 support */ |
Giuseppe CAVALLARO | 156e14b | 2013-06-12 08:16:38 +0200 | [diff] [blame] | 3174 | if (caps[1] & SDHCI_SUPPORT_SDR104) { |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3175 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; |
Giuseppe CAVALLARO | 156e14b | 2013-06-12 08:16:38 +0200 | [diff] [blame] | 3176 | /* SD3.0: SDR104 is supported so (for eMMC) the caps2 |
| 3177 | * field can be promoted to support HS200. |
| 3178 | */ |
Adrian Hunter | 549c0b1 | 2014-11-06 15:19:05 +0200 | [diff] [blame] | 3179 | if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) |
David Cohen | 13868bf | 2013-10-29 10:58:26 -0700 | [diff] [blame] | 3180 | mmc->caps2 |= MMC_CAP2_HS200; |
Giuseppe CAVALLARO | 156e14b | 2013-06-12 08:16:38 +0200 | [diff] [blame] | 3181 | } else if (caps[1] & SDHCI_SUPPORT_SDR50) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3182 | mmc->caps |= MMC_CAP_UHS_SDR50; |
| 3183 | |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 3184 | if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && |
| 3185 | (caps[1] & SDHCI_SUPPORT_HS400)) |
| 3186 | mmc->caps2 |= MMC_CAP2_HS400; |
| 3187 | |
Adrian Hunter | 549c0b1 | 2014-11-06 15:19:05 +0200 | [diff] [blame] | 3188 | if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && |
| 3189 | (IS_ERR(mmc->supply.vqmmc) || |
| 3190 | !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, |
| 3191 | 1300000))) |
| 3192 | mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; |
| 3193 | |
Micky Ching | 9107ebb | 2014-02-21 18:40:35 +0800 | [diff] [blame] | 3194 | if ((caps[1] & SDHCI_SUPPORT_DDR50) && |
| 3195 | !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3196 | mmc->caps |= MMC_CAP_UHS_DDR50; |
| 3197 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 3198 | /* Does the host need tuning for SDR50? */ |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 3199 | if (caps[1] & SDHCI_USE_SDR50_TUNING) |
| 3200 | host->flags |= SDHCI_SDR50_NEEDS_TUNING; |
| 3201 | |
Giuseppe CAVALLARO | 156e14b | 2013-06-12 08:16:38 +0200 | [diff] [blame] | 3202 | /* Does the host need tuning for SDR104 / HS200? */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 3203 | if (mmc->caps2 & MMC_CAP2_HS200) |
Giuseppe CAVALLARO | 156e14b | 2013-06-12 08:16:38 +0200 | [diff] [blame] | 3204 | host->flags |= SDHCI_SDR104_NEEDS_TUNING; |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 3205 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 3206 | /* Driver Type(s) (A, C, D) supported by the host */ |
| 3207 | if (caps[1] & SDHCI_DRIVER_TYPE_A) |
| 3208 | mmc->caps |= MMC_CAP_DRIVER_TYPE_A; |
| 3209 | if (caps[1] & SDHCI_DRIVER_TYPE_C) |
| 3210 | mmc->caps |= MMC_CAP_DRIVER_TYPE_C; |
| 3211 | if (caps[1] & SDHCI_DRIVER_TYPE_D) |
| 3212 | mmc->caps |= MMC_CAP_DRIVER_TYPE_D; |
| 3213 | |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 3214 | /* Initial value for re-tuning timer count */ |
| 3215 | host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> |
| 3216 | SDHCI_RETUNING_TIMER_COUNT_SHIFT; |
| 3217 | |
| 3218 | /* |
| 3219 | * In case Re-tuning Timer is not disabled, the actual value of |
| 3220 | * re-tuning timer will be 2 ^ (n - 1). |
| 3221 | */ |
| 3222 | if (host->tuning_count) |
| 3223 | host->tuning_count = 1 << (host->tuning_count - 1); |
| 3224 | |
| 3225 | /* Re-tuning mode supported by the Host Controller */ |
| 3226 | host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> |
| 3227 | SDHCI_RETUNING_MODE_SHIFT; |
| 3228 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3229 | ocr_avail = 0; |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 3230 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3231 | /* |
| 3232 | * According to SD Host Controller spec v3.00, if the Host System |
| 3233 | * can afford more than 150mA, Host Driver should set XPC to 1. Also |
| 3234 | * the value is meaningful only if Voltage Support in the Capabilities |
| 3235 | * register is set. The actual current value is 4 times the register |
| 3236 | * value. |
| 3237 | */ |
| 3238 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3239 | if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { |
Chuanxiao.Dong | ae90603 | 2014-08-01 14:00:13 +0800 | [diff] [blame] | 3240 | int curr = regulator_get_current_limit(mmc->supply.vmmc); |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 3241 | if (curr > 0) { |
| 3242 | |
| 3243 | /* convert to SDHCI_MAX_CURRENT format */ |
| 3244 | curr = curr/1000; /* convert to mA */ |
| 3245 | curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; |
| 3246 | |
| 3247 | curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); |
| 3248 | max_current_caps = |
| 3249 | (curr << SDHCI_MAX_CURRENT_330_SHIFT) | |
| 3250 | (curr << SDHCI_MAX_CURRENT_300_SHIFT) | |
| 3251 | (curr << SDHCI_MAX_CURRENT_180_SHIFT); |
| 3252 | } |
| 3253 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3254 | |
| 3255 | if (caps[0] & SDHCI_CAN_VDD_330) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3256 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3257 | |
Aaron Lu | 55c4665 | 2012-07-04 13:31:48 +0800 | [diff] [blame] | 3258 | mmc->max_current_330 = ((max_current_caps & |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3259 | SDHCI_MAX_CURRENT_330_MASK) >> |
| 3260 | SDHCI_MAX_CURRENT_330_SHIFT) * |
| 3261 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3262 | } |
| 3263 | if (caps[0] & SDHCI_CAN_VDD_300) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3264 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3265 | |
Aaron Lu | 55c4665 | 2012-07-04 13:31:48 +0800 | [diff] [blame] | 3266 | mmc->max_current_300 = ((max_current_caps & |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3267 | SDHCI_MAX_CURRENT_300_MASK) >> |
| 3268 | SDHCI_MAX_CURRENT_300_SHIFT) * |
| 3269 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3270 | } |
| 3271 | if (caps[0] & SDHCI_CAN_VDD_180) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3272 | ocr_avail |= MMC_VDD_165_195; |
| 3273 | |
Aaron Lu | 55c4665 | 2012-07-04 13:31:48 +0800 | [diff] [blame] | 3274 | mmc->max_current_180 = ((max_current_caps & |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3275 | SDHCI_MAX_CURRENT_180_MASK) >> |
| 3276 | SDHCI_MAX_CURRENT_180_SHIFT) * |
| 3277 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3278 | } |
| 3279 | |
Ulf Hansson | 5fd26c7 | 2015-06-05 11:40:08 +0200 | [diff] [blame] | 3280 | /* If OCR set by host, use it instead. */ |
| 3281 | if (host->ocr_mask) |
| 3282 | ocr_avail = host->ocr_mask; |
| 3283 | |
| 3284 | /* If OCR set by external regulators, give it highest prio. */ |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3285 | if (mmc->ocr_avail) |
Tim Kryger | 5222161 | 2014-06-25 00:25:34 -0700 | [diff] [blame] | 3286 | ocr_avail = mmc->ocr_avail; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3287 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3288 | mmc->ocr_avail = ocr_avail; |
| 3289 | mmc->ocr_avail_sdio = ocr_avail; |
| 3290 | if (host->ocr_avail_sdio) |
| 3291 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; |
| 3292 | mmc->ocr_avail_sd = ocr_avail; |
| 3293 | if (host->ocr_avail_sd) |
| 3294 | mmc->ocr_avail_sd &= host->ocr_avail_sd; |
| 3295 | else /* normal SD controllers don't support 1.8V */ |
| 3296 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; |
| 3297 | mmc->ocr_avail_mmc = ocr_avail; |
| 3298 | if (host->ocr_avail_mmc) |
| 3299 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 3300 | |
| 3301 | if (mmc->ocr_avail == 0) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 3302 | pr_err("%s: Hardware doesn't report any support voltages.\n", |
| 3303 | mmc_hostname(mmc)); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3304 | return -ENODEV; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 3305 | } |
| 3306 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3307 | spin_lock_init(&host->lock); |
| 3308 | |
| 3309 | /* |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3310 | * Maximum number of segments. Depends on if the hardware |
| 3311 | * can do scatter/gather or not. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3312 | */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3313 | if (host->flags & SDHCI_USE_ADMA) |
Adrian Hunter | 4fb213f | 2014-11-04 12:42:43 +0200 | [diff] [blame] | 3314 | mmc->max_segs = SDHCI_MAX_SEGS; |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3315 | else if (host->flags & SDHCI_USE_SDMA) |
Martin K. Petersen | a36274e | 2010-09-10 01:33:59 -0400 | [diff] [blame] | 3316 | mmc->max_segs = 1; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3317 | else /* PIO */ |
Adrian Hunter | 4fb213f | 2014-11-04 12:42:43 +0200 | [diff] [blame] | 3318 | mmc->max_segs = SDHCI_MAX_SEGS; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3319 | |
| 3320 | /* |
Adrian Hunter | ac00531 | 2014-12-05 19:25:28 +0200 | [diff] [blame] | 3321 | * Maximum number of sectors in one transfer. Limited by SDMA boundary |
| 3322 | * size (512KiB). Note some tuning modes impose a 4MiB limit, but this |
| 3323 | * is less anyway. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3324 | */ |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 3325 | mmc->max_req_size = 524288; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3326 | |
| 3327 | /* |
| 3328 | * Maximum segment size. Could be one segment with the maximum number |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3329 | * of bytes. When doing hardware scatter/gather, each entry cannot |
| 3330 | * be larger than 64 KiB though. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3331 | */ |
Olof Johansson | 30652aa | 2011-01-01 18:37:32 -0600 | [diff] [blame] | 3332 | if (host->flags & SDHCI_USE_ADMA) { |
| 3333 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) |
| 3334 | mmc->max_seg_size = 65535; |
| 3335 | else |
| 3336 | mmc->max_seg_size = 65536; |
| 3337 | } else { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3338 | mmc->max_seg_size = mmc->max_req_size; |
Olof Johansson | 30652aa | 2011-01-01 18:37:32 -0600 | [diff] [blame] | 3339 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3340 | |
| 3341 | /* |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 3342 | * Maximum block size. This varies from controller to controller and |
| 3343 | * is specified in the capabilities register. |
| 3344 | */ |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 3345 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
| 3346 | mmc->max_blk_size = 2; |
| 3347 | } else { |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3348 | mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 3349 | SDHCI_MAX_BLOCK_SHIFT; |
| 3350 | if (mmc->max_blk_size >= 3) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 3351 | pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", |
| 3352 | mmc_hostname(mmc)); |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 3353 | mmc->max_blk_size = 0; |
| 3354 | } |
| 3355 | } |
| 3356 | |
| 3357 | mmc->max_blk_size = 512 << mmc->max_blk_size; |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 3358 | |
| 3359 | /* |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 3360 | * Maximum block count. |
| 3361 | */ |
Ben Dooks | 1388eef | 2009-06-14 12:40:53 +0100 | [diff] [blame] | 3362 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 3363 | |
| 3364 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3365 | * Init tasklets. |
| 3366 | */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3367 | tasklet_init(&host->finish_tasklet, |
| 3368 | sdhci_tasklet_finish, (unsigned long)host); |
| 3369 | |
Al Viro | e4cad1b | 2006-10-10 22:47:07 +0100 | [diff] [blame] | 3370 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3371 | |
Adrian Hunter | 250fb7b4 | 2014-12-05 19:41:10 +0200 | [diff] [blame] | 3372 | init_waitqueue_head(&host->buf_ready_int); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 3373 | |
Shawn Guo | 2af502c | 2013-07-05 14:38:55 +0800 | [diff] [blame] | 3374 | sdhci_init(host, 0); |
| 3375 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3376 | ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, |
| 3377 | IRQF_SHARED, mmc_hostname(mmc), host); |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3378 | if (ret) { |
| 3379 | pr_err("%s: Failed to request IRQ %d: %d\n", |
| 3380 | mmc_hostname(mmc), host->irq, ret); |
Pierre Ossman | 8ef1a14 | 2006-06-30 02:22:21 -0700 | [diff] [blame] | 3381 | goto untasklet; |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3382 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3383 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3384 | #ifdef CONFIG_MMC_DEBUG |
| 3385 | sdhci_dumpregs(host); |
| 3386 | #endif |
| 3387 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 3388 | #ifdef SDHCI_USE_LEDS_CLASS |
Helmut Schaa | 5dbace0 | 2009-02-14 16:22:39 +0100 | [diff] [blame] | 3389 | snprintf(host->led_name, sizeof(host->led_name), |
| 3390 | "%s::", mmc_hostname(mmc)); |
| 3391 | host->led.name = host->led_name; |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3392 | host->led.brightness = LED_OFF; |
| 3393 | host->led.default_trigger = mmc_hostname(mmc); |
| 3394 | host->led.brightness_set = sdhci_led_control; |
| 3395 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3396 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3397 | if (ret) { |
| 3398 | pr_err("%s: Failed to register LED device: %d\n", |
| 3399 | mmc_hostname(mmc), ret); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3400 | goto reset; |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3401 | } |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3402 | #endif |
| 3403 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 3404 | mmiowb(); |
| 3405 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3406 | mmc_add_host(mmc); |
| 3407 | |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3408 | pr_info("%s: SDHCI controller on %s [%s] using %s\n", |
Kay Sievers | d1b2686 | 2008-11-08 21:37:46 +0100 | [diff] [blame] | 3409 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3410 | (host->flags & SDHCI_USE_ADMA) ? |
| 3411 | (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3412 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3413 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 3414 | sdhci_enable_card_detection(host); |
| 3415 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3416 | return 0; |
| 3417 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 3418 | #ifdef SDHCI_USE_LEDS_CLASS |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3419 | reset: |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 3420 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 3421 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 3422 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3423 | free_irq(host->irq, host); |
| 3424 | #endif |
Pierre Ossman | 8ef1a14 | 2006-06-30 02:22:21 -0700 | [diff] [blame] | 3425 | untasklet: |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3426 | tasklet_kill(&host->finish_tasklet); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3427 | |
| 3428 | return ret; |
| 3429 | } |
| 3430 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3431 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
| 3432 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3433 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3434 | { |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3435 | struct mmc_host *mmc = host->mmc; |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3436 | unsigned long flags; |
| 3437 | |
| 3438 | if (dead) { |
| 3439 | spin_lock_irqsave(&host->lock, flags); |
| 3440 | |
| 3441 | host->flags |= SDHCI_DEVICE_DEAD; |
| 3442 | |
| 3443 | if (host->mrq) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3444 | pr_err("%s: Controller removed during " |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 3445 | " transfer!\n", mmc_hostname(mmc)); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3446 | |
| 3447 | host->mrq->cmd->error = -ENOMEDIUM; |
| 3448 | tasklet_schedule(&host->finish_tasklet); |
| 3449 | } |
| 3450 | |
| 3451 | spin_unlock_irqrestore(&host->lock, flags); |
| 3452 | } |
| 3453 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 3454 | sdhci_disable_card_detection(host); |
| 3455 | |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 3456 | mmc_remove_host(mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3457 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 3458 | #ifdef SDHCI_USE_LEDS_CLASS |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3459 | led_classdev_unregister(&host->led); |
| 3460 | #endif |
| 3461 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3462 | if (!dead) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 3463 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3464 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 3465 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 3466 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3467 | free_irq(host->irq, host); |
| 3468 | |
| 3469 | del_timer_sync(&host->timer); |
| 3470 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3471 | tasklet_kill(&host->finish_tasklet); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3472 | |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3473 | if (!IS_ERR(mmc->supply.vqmmc)) |
| 3474 | regulator_disable(mmc->supply.vqmmc); |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 3475 | |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 3476 | if (host->adma_table) |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 3477 | dma_free_coherent(mmc_dev(mmc), host->adma_table_sz, |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 3478 | host->adma_table, host->adma_addr); |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 3479 | if (host->align_buffer) |
| 3480 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz, |
| 3481 | host->align_buffer, host->align_addr); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3482 | |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 3483 | host->adma_table = NULL; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3484 | host->align_buffer = NULL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3485 | } |
| 3486 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3487 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
| 3488 | |
| 3489 | void sdhci_free_host(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3490 | { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3491 | mmc_free_host(host->mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3492 | } |
| 3493 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3494 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3495 | |
| 3496 | /*****************************************************************************\ |
| 3497 | * * |
| 3498 | * Driver init/exit * |
| 3499 | * * |
| 3500 | \*****************************************************************************/ |
| 3501 | |
| 3502 | static int __init sdhci_drv_init(void) |
| 3503 | { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3504 | pr_info(DRIVER_NAME |
Pierre Ossman | 52fbf9c | 2007-02-09 08:23:41 +0100 | [diff] [blame] | 3505 | ": Secure Digital Host Controller Interface driver\n"); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3506 | pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3507 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3508 | return 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3509 | } |
| 3510 | |
| 3511 | static void __exit sdhci_drv_exit(void) |
| 3512 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3513 | } |
| 3514 | |
| 3515 | module_init(sdhci_drv_init); |
| 3516 | module_exit(sdhci_drv_exit); |
| 3517 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3518 | module_param(debug_quirks, uint, 0444); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3519 | module_param(debug_quirks2, uint, 0444); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3520 | |
Pierre Ossman | 32710e8 | 2009-04-08 20:14:54 +0200 | [diff] [blame] | 3521 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3522 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3523 | MODULE_LICENSE("GPL"); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3524 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3525 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3526 | MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); |