blob: 7faa2f554ab19e51a96c39c15799c899c069bf08 [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -07001#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
Mike Frysinger53f8a252007-11-15 15:48:01 +08006mainmenu "Blackfin Kernel Configuration"
Bryan Wu1394f032007-05-06 14:50:22 -07007
8config MMU
Mike Frysingerbac7d892009-06-07 03:46:06 -04009 def_bool n
Bryan Wu1394f032007-05-06 14:50:22 -070010
11config FPU
Mike Frysingerbac7d892009-06-07 03:46:06 -040012 def_bool n
Bryan Wu1394f032007-05-06 14:50:22 -070013
14config RWSEM_GENERIC_SPINLOCK
Mike Frysingerbac7d892009-06-07 03:46:06 -040015 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070016
17config RWSEM_XCHGADD_ALGORITHM
Mike Frysingerbac7d892009-06-07 03:46:06 -040018 def_bool n
Bryan Wu1394f032007-05-06 14:50:22 -070019
20config BLACKFIN
Mike Frysingerbac7d892009-06-07 03:46:06 -040021 def_bool y
Mike Frysinger1ee76d72009-06-10 04:45:29 -040022 select HAVE_FUNCTION_GRAPH_TRACER
Mike Frysinger1c873be2009-06-09 07:25:09 -040023 select HAVE_FUNCTION_TRACER
Sam Ravnborgec7748b2008-02-09 10:46:40 +010024 select HAVE_IDE
Mike Frysinger538067c2009-06-07 03:47:01 -040025 select HAVE_KERNEL_GZIP
26 select HAVE_KERNEL_BZIP2
27 select HAVE_KERNEL_LZMA
Mathieu Desnoyers42d4b832008-02-02 15:10:34 -050028 select HAVE_OPROFILE
Michael Hennericha4f0b32c2008-11-18 17:48:22 +080029 select ARCH_WANT_OPTIONAL_GPIOLIB
Bryan Wu1394f032007-05-06 14:50:22 -070030
Mike Frysinger70f12562009-06-07 17:18:25 -040031config GENERIC_BUG
32 def_bool y
33 depends on BUG
34
Aubrey Lie3defff2007-05-21 18:09:11 +080035config ZONE_DMA
Mike Frysingerbac7d892009-06-07 03:46:06 -040036 def_bool y
Aubrey Lie3defff2007-05-21 18:09:11 +080037
Bryan Wu1394f032007-05-06 14:50:22 -070038config GENERIC_FIND_NEXT_BIT
Mike Frysingerbac7d892009-06-07 03:46:06 -040039 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070040
41config GENERIC_HWEIGHT
Mike Frysingerbac7d892009-06-07 03:46:06 -040042 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070043
44config GENERIC_HARDIRQS
Mike Frysingerbac7d892009-06-07 03:46:06 -040045 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070046
47config GENERIC_IRQ_PROBE
Mike Frysingerbac7d892009-06-07 03:46:06 -040048 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070049
Michael Hennerichb2d15832007-07-24 15:46:36 +080050config GENERIC_GPIO
Mike Frysingerbac7d892009-06-07 03:46:06 -040051 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070052
53config FORCE_MAX_ZONEORDER
54 int
55 default "14"
56
57config GENERIC_CALIBRATE_DELAY
Mike Frysingerbac7d892009-06-07 03:46:06 -040058 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070059
Mike Frysinger6fa68e72009-06-08 18:45:01 -040060config LOCKDEP_SUPPORT
61 def_bool y
62
Mike Frysingerc7b412f2009-06-08 18:44:45 -040063config STACKTRACE_SUPPORT
64 def_bool y
65
Mike Frysinger8f860012009-06-08 12:49:48 -040066config TRACE_IRQFLAGS_SUPPORT
67 def_bool y
Bryan Wu1394f032007-05-06 14:50:22 -070068
Bryan Wu1394f032007-05-06 14:50:22 -070069source "init/Kconfig"
Matt Helsleydc52ddc2008-10-18 20:27:21 -070070
Bryan Wu1394f032007-05-06 14:50:22 -070071source "kernel/Kconfig.preempt"
72
Matt Helsleydc52ddc2008-10-18 20:27:21 -070073source "kernel/Kconfig.freezer"
74
Bryan Wu1394f032007-05-06 14:50:22 -070075menu "Blackfin Processor Options"
76
77comment "Processor and Board Settings"
78
79choice
80 prompt "CPU"
81 default BF533
82
Bryan Wu2f6f4bc2008-11-18 17:48:21 +080083config BF512
84 bool "BF512"
85 help
86 BF512 Processor Support.
87
88config BF514
89 bool "BF514"
90 help
91 BF514 Processor Support.
92
93config BF516
94 bool "BF516"
95 help
96 BF516 Processor Support.
97
98config BF518
99 bool "BF518"
100 help
101 BF518 Processor Support.
102
Michael Hennerich59003142007-10-21 16:54:27 +0800103config BF522
104 bool "BF522"
105 help
106 BF522 Processor Support.
107
Mike Frysinger1545a112007-12-24 16:54:48 +0800108config BF523
109 bool "BF523"
110 help
111 BF523 Processor Support.
112
113config BF524
114 bool "BF524"
115 help
116 BF524 Processor Support.
117
Michael Hennerich59003142007-10-21 16:54:27 +0800118config BF525
119 bool "BF525"
120 help
121 BF525 Processor Support.
122
Mike Frysinger1545a112007-12-24 16:54:48 +0800123config BF526
124 bool "BF526"
125 help
126 BF526 Processor Support.
127
Michael Hennerich59003142007-10-21 16:54:27 +0800128config BF527
129 bool "BF527"
130 help
131 BF527 Processor Support.
132
Bryan Wu1394f032007-05-06 14:50:22 -0700133config BF531
134 bool "BF531"
135 help
136 BF531 Processor Support.
137
138config BF532
139 bool "BF532"
140 help
141 BF532 Processor Support.
142
143config BF533
144 bool "BF533"
145 help
146 BF533 Processor Support.
147
148config BF534
149 bool "BF534"
150 help
151 BF534 Processor Support.
152
153config BF536
154 bool "BF536"
155 help
156 BF536 Processor Support.
157
158config BF537
159 bool "BF537"
160 help
161 BF537 Processor Support.
162
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800163config BF538
164 bool "BF538"
165 help
166 BF538 Processor Support.
167
168config BF539
169 bool "BF539"
170 help
171 BF539 Processor Support.
172
Roy Huang24a07a12007-07-12 22:41:45 +0800173config BF542
174 bool "BF542"
175 help
176 BF542 Processor Support.
177
Mike Frysinger2f89c062009-02-04 16:49:45 +0800178config BF542M
179 bool "BF542m"
180 help
181 BF542 Processor Support.
182
Roy Huang24a07a12007-07-12 22:41:45 +0800183config BF544
184 bool "BF544"
185 help
186 BF544 Processor Support.
187
Mike Frysinger2f89c062009-02-04 16:49:45 +0800188config BF544M
189 bool "BF544m"
190 help
191 BF544 Processor Support.
192
Mike Frysinger7c7fd172007-11-15 21:10:21 +0800193config BF547
194 bool "BF547"
195 help
196 BF547 Processor Support.
197
Mike Frysinger2f89c062009-02-04 16:49:45 +0800198config BF547M
199 bool "BF547m"
200 help
201 BF547 Processor Support.
202
Roy Huang24a07a12007-07-12 22:41:45 +0800203config BF548
204 bool "BF548"
205 help
206 BF548 Processor Support.
207
Mike Frysinger2f89c062009-02-04 16:49:45 +0800208config BF548M
209 bool "BF548m"
210 help
211 BF548 Processor Support.
212
Roy Huang24a07a12007-07-12 22:41:45 +0800213config BF549
214 bool "BF549"
215 help
216 BF549 Processor Support.
217
Mike Frysinger2f89c062009-02-04 16:49:45 +0800218config BF549M
219 bool "BF549m"
220 help
221 BF549 Processor Support.
222
Bryan Wu1394f032007-05-06 14:50:22 -0700223config BF561
224 bool "BF561"
225 help
Mike Frysingercd88b4d2008-10-09 12:03:22 +0800226 BF561 Processor Support.
Bryan Wu1394f032007-05-06 14:50:22 -0700227
228endchoice
229
Graf Yang46fa5ee2009-01-07 23:14:39 +0800230config SMP
231 depends on BF561
Graf Yang9b9bfde2009-05-27 09:58:35 +0000232 select GENERIC_TIME
Graf Yang46fa5ee2009-01-07 23:14:39 +0800233 bool "Symmetric multi-processing support"
234 ---help---
235 This enables support for systems with more than one CPU,
236 like the dual core BF561. If you have a system with only one
237 CPU, say N. If you have a system with more than one CPU, say Y.
238
239 If you don't know what to do here, say N.
240
241config NR_CPUS
242 int
243 depends on SMP
244 default 2 if BF561
245
246config IRQ_PER_CPU
247 bool
248 depends on SMP
249 default y
250
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800251config BF_REV_MIN
252 int
Mike Frysinger2f89c062009-02-04 16:49:45 +0800253 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800254 default 2 if (BF537 || BF536 || BF534)
Mike Frysinger2f89c062009-02-04 16:49:45 +0800255 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800256 default 4 if (BF538 || BF539)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800257
258config BF_REV_MAX
259 int
Mike Frysinger2f89c062009-02-04 16:49:45 +0800260 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
261 default 3 if (BF537 || BF536 || BF534 || BF54xM)
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800262 default 5 if (BF561 || BF538 || BF539)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800263 default 6 if (BF533 || BF532 || BF531)
264
Bryan Wu1394f032007-05-06 14:50:22 -0700265choice
266 prompt "Silicon Rev"
Mike Frysingerf8b55652009-04-13 21:58:34 +0000267 default BF_REV_0_0 if (BF51x || BF52x)
268 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
Mike Frysinger2f89c062009-02-04 16:49:45 +0800269 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
Roy Huang24a07a12007-07-12 22:41:45 +0800270
271config BF_REV_0_0
272 bool "0.0"
Mike Frysinger2f89c062009-02-04 16:49:45 +0800273 depends on (BF51x || BF52x || (BF54x && !BF54xM))
Michael Hennerich59003142007-10-21 16:54:27 +0800274
275config BF_REV_0_1
Mike Frysingerd07f4382007-11-15 15:49:17 +0800276 bool "0.1"
Mike Frysinger3d15f302009-06-15 16:21:44 +0000277 depends on (BF51x || BF52x || (BF54x && !BF54xM))
Bryan Wu1394f032007-05-06 14:50:22 -0700278
279config BF_REV_0_2
280 bool "0.2"
Mike Frysinger2f89c062009-02-04 16:49:45 +0800281 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
Bryan Wu1394f032007-05-06 14:50:22 -0700282
283config BF_REV_0_3
284 bool "0.3"
Mike Frysinger2f89c062009-02-04 16:49:45 +0800285 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
Bryan Wu1394f032007-05-06 14:50:22 -0700286
287config BF_REV_0_4
288 bool "0.4"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800289 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
Bryan Wu1394f032007-05-06 14:50:22 -0700290
291config BF_REV_0_5
292 bool "0.5"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800293 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
Bryan Wu1394f032007-05-06 14:50:22 -0700294
Mike Frysinger49f72532008-10-09 12:06:27 +0800295config BF_REV_0_6
296 bool "0.6"
297 depends on (BF533 || BF532 || BF531)
298
Jie Zhangde3025f2007-06-25 18:04:12 +0800299config BF_REV_ANY
300 bool "any"
301
302config BF_REV_NONE
303 bool "none"
304
Bryan Wu1394f032007-05-06 14:50:22 -0700305endchoice
306
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800307config BF51x
308 bool
309 depends on (BF512 || BF514 || BF516 || BF518)
310 default y
311
Michael Hennerich59003142007-10-21 16:54:27 +0800312config BF52x
313 bool
Mike Frysinger1545a112007-12-24 16:54:48 +0800314 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
Michael Hennerich59003142007-10-21 16:54:27 +0800315 default y
316
Roy Huang24a07a12007-07-12 22:41:45 +0800317config BF53x
318 bool
319 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
320 default y
321
Mike Frysinger2f89c062009-02-04 16:49:45 +0800322config BF54xM
323 bool
324 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
325 default y
326
Roy Huang24a07a12007-07-12 22:41:45 +0800327config BF54x
328 bool
Mike Frysinger2f89c062009-02-04 16:49:45 +0800329 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
Roy Huang24a07a12007-07-12 22:41:45 +0800330 default y
331
Bryan Wu1394f032007-05-06 14:50:22 -0700332config MEM_GENERIC_BOARD
333 bool
334 depends on GENERIC_BOARD
335 default y
336
337config MEM_MT48LC64M4A2FB_7E
338 bool
339 depends on (BFIN533_STAMP)
340 default y
341
342config MEM_MT48LC16M16A2TG_75
343 bool
344 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
Javier Herreroab472a02007-10-29 16:14:44 +0800345 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
Michael Hennerich9db144f2008-07-19 17:16:07 +0800346 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
Bryan Wu1394f032007-05-06 14:50:22 -0700347 default y
348
349config MEM_MT48LC32M8A2_75
350 bool
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800351 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
Bryan Wu1394f032007-05-06 14:50:22 -0700352 default y
353
354config MEM_MT48LC8M32B2B5_7
355 bool
356 depends on (BFIN561_BLUETECHNIX_CM)
357 default y
358
Michael Hennerich59003142007-10-21 16:54:27 +0800359config MEM_MT48LC32M16A2TG_75
360 bool
Graf Yangee48efb2009-06-18 04:32:04 +0000361 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
Michael Hennerich59003142007-10-21 16:54:27 +0800362 default y
363
Sonic Zhang49345402009-01-07 23:14:38 +0800364config MEM_MT48LC32M8A2_75
365 bool
366 depends on (BFIN518F_EZBRD)
367 default y
368
Graf Yangee48efb2009-06-18 04:32:04 +0000369config MEM_MT48H32M16LFCJ_75
370 bool
371 depends on (BFIN526_EZBRD)
372 default y
373
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800374source "arch/blackfin/mach-bf518/Kconfig"
Michael Hennerich59003142007-10-21 16:54:27 +0800375source "arch/blackfin/mach-bf527/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700376source "arch/blackfin/mach-bf533/Kconfig"
377source "arch/blackfin/mach-bf561/Kconfig"
378source "arch/blackfin/mach-bf537/Kconfig"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800379source "arch/blackfin/mach-bf538/Kconfig"
Roy Huang24a07a12007-07-12 22:41:45 +0800380source "arch/blackfin/mach-bf548/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700381
382menu "Board customizations"
383
384config CMDLINE_BOOL
385 bool "Default bootloader kernel arguments"
386
387config CMDLINE
388 string "Initial kernel command string"
389 depends on CMDLINE_BOOL
390 default "console=ttyBF0,57600"
391 help
392 If you don't have a boot loader capable of passing a command line string
393 to the kernel, you may specify one here. As a minimum, you should specify
394 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
395
Mike Frysinger5f004c22008-04-25 02:11:24 +0800396config BOOT_LOAD
397 hex "Kernel load address for booting"
398 default "0x1000"
399 range 0x1000 0x20000000
400 help
401 This option allows you to set the load address of the kernel.
402 This can be useful if you are on a board which has a small amount
403 of memory or you wish to reserve some memory at the beginning of
404 the address space.
405
406 Note that you need to keep this value above 4k (0x1000) as this
407 memory region is used to capture NULL pointer references as well
408 as some core kernel functions.
409
Michael Hennerich8cc71172008-10-13 14:45:06 +0800410config ROM_BASE
411 hex "Kernel ROM Base"
Mike Frysinger86249912008-11-18 17:48:22 +0800412 depends on ROMKERNEL
Michael Hennerich8cc71172008-10-13 14:45:06 +0800413 default "0x20040000"
414 range 0x20000000 0x20400000 if !(BF54x || BF561)
415 range 0x20000000 0x30000000 if (BF54x || BF561)
416 help
417
Robin Getzf16295e2007-08-03 18:07:17 +0800418comment "Clock/PLL Setup"
Bryan Wu1394f032007-05-06 14:50:22 -0700419
420config CLKIN_HZ
Sonic Zhang2fb6cb42008-04-25 04:39:28 +0800421 int "Frequency of the crystal on the board in Hz"
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800422 default "10000000" if BFIN532_IP0X
Mike Frysingerd0cb9b42009-06-11 21:52:35 +0000423 default "11059200" if BFIN533_STAMP
424 default "24576000" if PNAV10
425 default "25000000" # most people use this
426 default "27000000" if BFIN533_EZKIT
427 default "30000000" if BFIN561_EZKIT
Bryan Wu1394f032007-05-06 14:50:22 -0700428 help
429 The frequency of CLKIN crystal oscillator on the board in Hz.
Sonic Zhang2fb6cb42008-04-25 04:39:28 +0800430 Warning: This value should match the crystal on the board. Otherwise,
431 peripherals won't work properly.
Bryan Wu1394f032007-05-06 14:50:22 -0700432
Robin Getzf16295e2007-08-03 18:07:17 +0800433config BFIN_KERNEL_CLOCK
434 bool "Re-program Clocks while Kernel boots?"
435 default n
436 help
437 This option decides if kernel clocks are re-programed from the
438 bootloader settings. If the clocks are not set, the SDRAM settings
439 are also not changed, and the Bootloader does 100% of the hardware
440 configuration.
441
442config PLL_BYPASS
Mike Frysingere4e9a7a2007-11-15 20:39:34 +0800443 bool "Bypass PLL"
444 depends on BFIN_KERNEL_CLOCK
445 default n
Robin Getzf16295e2007-08-03 18:07:17 +0800446
447config CLKIN_HALF
448 bool "Half Clock In"
449 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
450 default n
451 help
452 If this is set the clock will be divided by 2, before it goes to the PLL.
453
454config VCO_MULT
455 int "VCO Multiplier"
456 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
457 range 1 64
458 default "22" if BFIN533_EZKIT
459 default "45" if BFIN533_STAMP
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800460 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
Robin Getzf16295e2007-08-03 18:07:17 +0800461 default "22" if BFIN533_BLUETECHNIX_CM
Michael Hennerich9db144f2008-07-19 17:16:07 +0800462 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
Robin Getzf16295e2007-08-03 18:07:17 +0800463 default "20" if BFIN561_EZKIT
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800464 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
Robin Getzf16295e2007-08-03 18:07:17 +0800465 help
466 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
467 PLL Frequency = (Crystal Frequency) * (this setting)
468
469choice
470 prompt "Core Clock Divider"
471 depends on BFIN_KERNEL_CLOCK
472 default CCLK_DIV_1
473 help
474 This sets the frequency of the core. It can be 1, 2, 4 or 8
475 Core Frequency = (PLL frequency) / (this setting)
476
477config CCLK_DIV_1
478 bool "1"
479
480config CCLK_DIV_2
481 bool "2"
482
483config CCLK_DIV_4
484 bool "4"
485
486config CCLK_DIV_8
487 bool "8"
488endchoice
489
490config SCLK_DIV
491 int "System Clock Divider"
492 depends on BFIN_KERNEL_CLOCK
493 range 1 15
Mike Frysinger5f004c22008-04-25 02:11:24 +0800494 default 5
Robin Getzf16295e2007-08-03 18:07:17 +0800495 help
496 This sets the frequency of the system clock (including SDRAM or DDR).
497 This can be between 1 and 15
498 System Clock = (PLL frequency) / (this setting)
499
Mike Frysinger5f004c22008-04-25 02:11:24 +0800500choice
501 prompt "DDR SDRAM Chip Type"
502 depends on BFIN_KERNEL_CLOCK
503 depends on BF54x
504 default MEM_MT46V32M16_5B
505
506config MEM_MT46V32M16_6T
507 bool "MT46V32M16_6T"
508
509config MEM_MT46V32M16_5B
510 bool "MT46V32M16_5B"
511endchoice
512
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800513choice
514 prompt "DDR/SDRAM Timing"
515 depends on BFIN_KERNEL_CLOCK
516 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
517 help
518 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
519 The calculated SDRAM timing parameters may not be 100%
520 accurate - This option is therefore marked experimental.
521
522config BFIN_KERNEL_CLOCK_MEMINIT_CALC
523 bool "Calculate Timings (EXPERIMENTAL)"
524 depends on EXPERIMENTAL
525
526config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
527 bool "Provide accurate Timings based on target SCLK"
528 help
529 Please consult the Blackfin Hardware Reference Manuals as well
530 as the memory device datasheet.
531 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
532endchoice
533
534menu "Memory Init Control"
535 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
536
537config MEM_DDRCTL0
538 depends on BF54x
539 hex "DDRCTL0"
540 default 0x0
541
542config MEM_DDRCTL1
543 depends on BF54x
544 hex "DDRCTL1"
545 default 0x0
546
547config MEM_DDRCTL2
548 depends on BF54x
549 hex "DDRCTL2"
550 default 0x0
551
552config MEM_EBIU_DDRQUE
553 depends on BF54x
554 hex "DDRQUE"
555 default 0x0
556
557config MEM_SDRRC
558 depends on !BF54x
559 hex "SDRRC"
560 default 0x0
561
562config MEM_SDGCTL
563 depends on !BF54x
564 hex "SDGCTL"
565 default 0x0
566endmenu
567
Robin Getzf16295e2007-08-03 18:07:17 +0800568#
569# Max & Min Speeds for various Chips
570#
571config MAX_VCO_HZ
572 int
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800573 default 400000000 if BF512
574 default 400000000 if BF514
575 default 400000000 if BF516
576 default 400000000 if BF518
Robin Getzf16295e2007-08-03 18:07:17 +0800577 default 600000000 if BF522
Mike Frysinger1545a112007-12-24 16:54:48 +0800578 default 400000000 if BF523
579 default 400000000 if BF524
Robin Getzf16295e2007-08-03 18:07:17 +0800580 default 600000000 if BF525
Mike Frysinger1545a112007-12-24 16:54:48 +0800581 default 400000000 if BF526
Robin Getzf16295e2007-08-03 18:07:17 +0800582 default 600000000 if BF527
583 default 400000000 if BF531
584 default 400000000 if BF532
585 default 750000000 if BF533
586 default 500000000 if BF534
587 default 400000000 if BF536
588 default 600000000 if BF537
Robin Getzf72eecb2007-11-21 16:29:20 +0800589 default 533333333 if BF538
590 default 533333333 if BF539
Robin Getzf16295e2007-08-03 18:07:17 +0800591 default 600000000 if BF542
Robin Getzf72eecb2007-11-21 16:29:20 +0800592 default 533333333 if BF544
Mike Frysinger1545a112007-12-24 16:54:48 +0800593 default 600000000 if BF547
594 default 600000000 if BF548
Robin Getzf72eecb2007-11-21 16:29:20 +0800595 default 533333333 if BF549
Robin Getzf16295e2007-08-03 18:07:17 +0800596 default 600000000 if BF561
597
598config MIN_VCO_HZ
599 int
600 default 50000000
601
602config MAX_SCLK_HZ
603 int
Robin Getzf72eecb2007-11-21 16:29:20 +0800604 default 133333333
Robin Getzf16295e2007-08-03 18:07:17 +0800605
606config MIN_SCLK_HZ
607 int
608 default 27000000
609
610comment "Kernel Timer/Scheduler"
611
612source kernel/Kconfig.hz
613
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800614config GENERIC_TIME
615 bool "Generic time"
616 default y
617
618config GENERIC_CLOCKEVENTS
619 bool "Generic clock events"
620 depends on GENERIC_TIME
621 default y
622
Graf Yang1fa9be72009-05-15 11:01:59 +0000623choice
624 prompt "Kernel Tick Source"
625 depends on GENERIC_CLOCKEVENTS
626 default TICKSOURCE_CORETMR
627
628config TICKSOURCE_GPTMR0
629 bool "Gptimer0 (SCLK domain)"
630 select BFIN_GPTIMERS
Graf Yang1fa9be72009-05-15 11:01:59 +0000631
632config TICKSOURCE_CORETMR
633 bool "Core timer (CCLK domain)"
634
635endchoice
636
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800637config CYCLES_CLOCKSOURCE
Graf Yang1fa9be72009-05-15 11:01:59 +0000638 bool "Use 'CYCLES' as a clocksource"
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800639 depends on GENERIC_CLOCKEVENTS
640 depends on !BFIN_SCRATCH_REG_CYCLES
Graf Yang1fa9be72009-05-15 11:01:59 +0000641 depends on !SMP
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800642 help
643 If you say Y here, you will enable support for using the 'cycles'
644 registers as a clock source. Doing so means you will be unable to
645 safely write to the 'cycles' register during runtime. You will
646 still be able to read it (such as for performance monitoring), but
647 writing the registers will most likely crash the kernel.
648
Graf Yang1fa9be72009-05-15 11:01:59 +0000649config GPTMR0_CLOCKSOURCE
650 bool "Use GPTimer0 as a clocksource (higher rating)"
Mike Frysinger3aca47c2009-06-18 19:40:47 +0000651 select BFIN_GPTIMERS
Graf Yang1fa9be72009-05-15 11:01:59 +0000652 depends on GENERIC_CLOCKEVENTS
653 depends on !TICKSOURCE_GPTMR0
654
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800655source kernel/time/Kconfig
656
Mike Frysinger5f004c22008-04-25 02:11:24 +0800657comment "Misc"
Sonic Zhang971d5bc2008-01-27 16:32:31 +0800658
Mike Frysingerf0b5d122007-08-05 17:03:59 +0800659choice
660 prompt "Blackfin Exception Scratch Register"
661 default BFIN_SCRATCH_REG_RETN
662 help
663 Select the resource to reserve for the Exception handler:
664 - RETN: Non-Maskable Interrupt (NMI)
665 - RETE: Exception Return (JTAG/ICE)
666 - CYCLES: Performance counter
667
668 If you are unsure, please select "RETN".
669
670config BFIN_SCRATCH_REG_RETN
671 bool "RETN"
672 help
673 Use the RETN register in the Blackfin exception handler
674 as a stack scratch register. This means you cannot
675 safely use NMI on the Blackfin while running Linux, but
676 you can debug the system with a JTAG ICE and use the
677 CYCLES performance registers.
678
679 If you are unsure, please select "RETN".
680
681config BFIN_SCRATCH_REG_RETE
682 bool "RETE"
683 help
684 Use the RETE register in the Blackfin exception handler
685 as a stack scratch register. This means you cannot
686 safely use a JTAG ICE while debugging a Blackfin board,
687 but you can safely use the CYCLES performance registers
688 and the NMI.
689
690 If you are unsure, please select "RETN".
691
692config BFIN_SCRATCH_REG_CYCLES
693 bool "CYCLES"
694 help
695 Use the CYCLES register in the Blackfin exception handler
696 as a stack scratch register. This means you cannot
697 safely use the CYCLES performance registers on a Blackfin
698 board at anytime, but you can debug the system with a JTAG
699 ICE and use the NMI.
700
701 If you are unsure, please select "RETN".
702
703endchoice
704
Bryan Wu1394f032007-05-06 14:50:22 -0700705endmenu
706
707
708menu "Blackfin Kernel Optimizations"
Graf Yang46fa5ee2009-01-07 23:14:39 +0800709 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700710
Bryan Wu1394f032007-05-06 14:50:22 -0700711comment "Memory Optimizations"
712
713config I_ENTRY_L1
714 bool "Locate interrupt entry code in L1 Memory"
715 default y
716 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200717 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
718 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700719
720config EXCPT_IRQ_SYSC_L1
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200721 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
Bryan Wu1394f032007-05-06 14:50:22 -0700722 default y
723 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200724 If enabled, the entire ASM lowlevel exception and interrupt entry code
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800725 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200726 (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700727
728config DO_IRQ_L1
729 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
730 default y
731 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200732 If enabled, the frequently called do_irq dispatcher function is linked
733 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700734
735config CORE_TIMER_IRQ_L1
736 bool "Locate frequently called timer_interrupt() function in L1 Memory"
737 default y
738 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200739 If enabled, the frequently called timer_interrupt() function is linked
740 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700741
742config IDLE_L1
743 bool "Locate frequently idle function in L1 Memory"
744 default y
745 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200746 If enabled, the frequently called idle function is linked
747 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700748
749config SCHEDULE_L1
750 bool "Locate kernel schedule function in L1 Memory"
751 default y
752 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200753 If enabled, the frequently called kernel schedule is linked
754 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700755
756config ARITHMETIC_OPS_L1
757 bool "Locate kernel owned arithmetic functions in L1 Memory"
758 default y
759 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200760 If enabled, arithmetic functions are linked
761 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700762
763config ACCESS_OK_L1
764 bool "Locate access_ok function in L1 Memory"
765 default y
766 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200767 If enabled, the access_ok function is linked
768 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700769
770config MEMSET_L1
771 bool "Locate memset function in L1 Memory"
772 default y
773 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200774 If enabled, the memset function is linked
775 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700776
777config MEMCPY_L1
778 bool "Locate memcpy function in L1 Memory"
779 default y
780 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200781 If enabled, the memcpy function is linked
782 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700783
784config SYS_BFIN_SPINLOCK_L1
785 bool "Locate sys_bfin_spinlock function in L1 Memory"
786 default y
787 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200788 If enabled, sys_bfin_spinlock function is linked
789 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700790
791config IP_CHECKSUM_L1
792 bool "Locate IP Checksum function in L1 Memory"
793 default n
794 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200795 If enabled, the IP Checksum function is linked
796 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700797
798config CACHELINE_ALIGNED_L1
799 bool "Locate cacheline_aligned data to L1 Data Memory"
Michael Hennerich157cc5a2007-07-12 16:20:21 +0800800 default y if !BF54x
801 default n if BF54x
Bryan Wu1394f032007-05-06 14:50:22 -0700802 depends on !BF531
803 help
Matt LaPlante692105b2009-01-26 11:12:25 +0100804 If enabled, cacheline_aligned data is linked
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200805 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700806
807config SYSCALL_TAB_L1
808 bool "Locate Syscall Table L1 Data Memory"
809 default n
810 depends on !BF531
811 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200812 If enabled, the Syscall LUT is linked
813 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700814
815config CPLB_SWITCH_TAB_L1
816 bool "Locate CPLB Switch Tables L1 Data Memory"
817 default n
818 depends on !BF531
819 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200820 If enabled, the CPLB Switch Tables are linked
821 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700822
Graf Yangca87b7a2008-10-08 17:30:01 +0800823config APP_STACK_L1
824 bool "Support locating application stack in L1 Scratch Memory"
825 default y
826 help
827 If enabled the application stack can be located in L1
828 scratch memory (less latency).
829
830 Currently only works with FLAT binaries.
831
Mike Frysinger6ad2b842008-10-28 11:03:09 +0800832config EXCEPTION_L1_SCRATCH
833 bool "Locate exception stack in L1 Scratch Memory"
834 default n
Graf Yangf82e0a02009-04-08 08:30:22 +0000835 depends on !APP_STACK_L1
Mike Frysinger6ad2b842008-10-28 11:03:09 +0800836 help
837 Whenever an exception occurs, use the L1 Scratch memory for
838 stack storage. You cannot place the stacks of FLAT binaries
839 in L1 when using this option.
840
841 If you don't use L1 Scratch, then you should say Y here.
842
Robin Getz251383c2008-08-14 15:12:55 +0800843comment "Speed Optimizations"
844config BFIN_INS_LOWOVERHEAD
845 bool "ins[bwl] low overhead, higher interrupt latency"
846 default y
847 help
848 Reads on the Blackfin are speculative. In Blackfin terms, this means
849 they can be interrupted at any time (even after they have been issued
850 on to the external bus), and re-issued after the interrupt occurs.
851 For memory - this is not a big deal, since memory does not change if
852 it sees a read.
853
854 If a FIFO is sitting on the end of the read, it will see two reads,
855 when the core only sees one since the FIFO receives both the read
856 which is cancelled (and not delivered to the core) and the one which
857 is re-issued (which is delivered to the core).
858
859 To solve this, interrupts are turned off before reads occur to
860 I/O space. This option controls which the overhead/latency of
861 controlling interrupts during this time
862 "n" turns interrupts off every read
863 (higher overhead, but lower interrupt latency)
864 "y" turns interrupts off every loop
865 (low overhead, but longer interrupt latency)
866
867 default behavior is to leave this set to on (type "Y"). If you are experiencing
868 interrupt latency issues, it is safe and OK to turn this off.
869
Bryan Wu1394f032007-05-06 14:50:22 -0700870endmenu
871
Bryan Wu1394f032007-05-06 14:50:22 -0700872choice
873 prompt "Kernel executes from"
874 help
875 Choose the memory type that the kernel will be running in.
876
877config RAMKERNEL
878 bool "RAM"
879 help
880 The kernel will be resident in RAM when running.
881
882config ROMKERNEL
883 bool "ROM"
884 help
885 The kernel will be resident in FLASH/ROM when running.
886
887endchoice
888
889source "mm/Kconfig"
890
Mike Frysinger780431e2007-10-21 23:37:54 +0800891config BFIN_GPTIMERS
892 tristate "Enable Blackfin General Purpose Timers API"
893 default n
894 help
895 Enable support for the General Purpose Timers API. If you
896 are unsure, say N.
897
898 To compile this driver as a module, choose M here: the module
Pavel Machek4737f092009-06-05 00:44:53 +0200899 will be called gptimers.
Mike Frysinger780431e2007-10-21 23:37:54 +0800900
Bryan Wu1394f032007-05-06 14:50:22 -0700901choice
Mike Frysingerd292b002008-10-28 11:15:36 +0800902 prompt "Uncached DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -0700903 default DMA_UNCACHED_1M
Cliff Cai86ad7932008-05-17 16:36:52 +0800904config DMA_UNCACHED_4M
905 bool "Enable 4M DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -0700906config DMA_UNCACHED_2M
907 bool "Enable 2M DMA region"
908config DMA_UNCACHED_1M
909 bool "Enable 1M DMA region"
910config DMA_UNCACHED_NONE
911 bool "Disable DMA region"
912endchoice
913
914
915comment "Cache Support"
Jie Zhang41ba6532009-06-16 09:48:33 +0000916
Robin Getz3bebca22007-10-10 23:55:26 +0800917config BFIN_ICACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700918 bool "Enable ICACHE"
Jie Zhang41ba6532009-06-16 09:48:33 +0000919 default y
920config BFIN_ICACHE_LOCK
921 bool "Enable Instruction Cache Locking"
922 depends on BFIN_ICACHE
923 default n
924config BFIN_EXTMEM_ICACHEABLE
925 bool "Enable ICACHE for external memory"
926 depends on BFIN_ICACHE
927 default y
928config BFIN_L2_ICACHEABLE
929 bool "Enable ICACHE for L2 SRAM"
930 depends on BFIN_ICACHE
931 depends on BF54x || BF561
932 default n
933
Robin Getz3bebca22007-10-10 23:55:26 +0800934config BFIN_DCACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700935 bool "Enable DCACHE"
Jie Zhang41ba6532009-06-16 09:48:33 +0000936 default y
Robin Getz3bebca22007-10-10 23:55:26 +0800937config BFIN_DCACHE_BANKA
Bryan Wu1394f032007-05-06 14:50:22 -0700938 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
Robin Getz3bebca22007-10-10 23:55:26 +0800939 depends on BFIN_DCACHE && !BF531
Bryan Wu1394f032007-05-06 14:50:22 -0700940 default n
Jie Zhang41ba6532009-06-16 09:48:33 +0000941config BFIN_EXTMEM_DCACHEABLE
942 bool "Enable DCACHE for external memory"
Robin Getz3bebca22007-10-10 23:55:26 +0800943 depends on BFIN_DCACHE
Jie Zhang41ba6532009-06-16 09:48:33 +0000944 default y
Graf Yang5ba76672009-05-07 04:09:15 +0000945choice
Jie Zhang41ba6532009-06-16 09:48:33 +0000946 prompt "External memory DCACHE policy"
947 depends on BFIN_EXTMEM_DCACHEABLE
948 default BFIN_EXTMEM_WRITEBACK if !SMP
949 default BFIN_EXTMEM_WRITETHROUGH if SMP
950config BFIN_EXTMEM_WRITEBACK
Graf Yang5ba76672009-05-07 04:09:15 +0000951 bool "Write back"
952 depends on !SMP
Jie Zhang41ba6532009-06-16 09:48:33 +0000953 help
954 Write Back Policy:
955 Cached data will be written back to SDRAM only when needed.
956 This can give a nice increase in performance, but beware of
957 broken drivers that do not properly invalidate/flush their
958 cache.
Graf Yang5ba76672009-05-07 04:09:15 +0000959
Jie Zhang41ba6532009-06-16 09:48:33 +0000960 Write Through Policy:
961 Cached data will always be written back to SDRAM when the
962 cache is updated. This is a completely safe setting, but
963 performance is worse than Write Back.
964
965 If you are unsure of the options and you want to be safe,
966 then go with Write Through.
967
968config BFIN_EXTMEM_WRITETHROUGH
Graf Yang5ba76672009-05-07 04:09:15 +0000969 bool "Write through"
Jie Zhang41ba6532009-06-16 09:48:33 +0000970 help
971 Write Back Policy:
972 Cached data will be written back to SDRAM only when needed.
973 This can give a nice increase in performance, but beware of
974 broken drivers that do not properly invalidate/flush their
975 cache.
Graf Yang5ba76672009-05-07 04:09:15 +0000976
Jie Zhang41ba6532009-06-16 09:48:33 +0000977 Write Through Policy:
978 Cached data will always be written back to SDRAM when the
979 cache is updated. This is a completely safe setting, but
980 performance is worse than Write Back.
981
982 If you are unsure of the options and you want to be safe,
983 then go with Write Through.
Graf Yang5ba76672009-05-07 04:09:15 +0000984
985endchoice
Sonic Zhangf099f392008-10-09 14:11:57 +0800986
Jie Zhang41ba6532009-06-16 09:48:33 +0000987config BFIN_L2_DCACHEABLE
988 bool "Enable DCACHE for L2 SRAM"
989 depends on BFIN_DCACHE
990 depends on BF54x || BF561
991 default n
992choice
993 prompt "L2 SRAM DCACHE policy"
994 depends on BFIN_L2_DCACHEABLE
995 default BFIN_L2_WRITEBACK
996config BFIN_L2_WRITEBACK
997 bool "Write back"
998 depends on !SMP
999
1000config BFIN_L2_WRITETHROUGH
1001 bool "Write through"
1002 depends on !SMP
1003endchoice
1004
1005
1006comment "Memory Protection Unit"
Bernd Schmidtb97b8a92008-01-27 18:39:16 +08001007config MPU
1008 bool "Enable the memory protection unit (EXPERIMENTAL)"
1009 default n
1010 help
1011 Use the processor's MPU to protect applications from accessing
1012 memory they do not own. This comes at a performance penalty
1013 and is recommended only for debugging.
1014
Matt LaPlante692105b2009-01-26 11:12:25 +01001015comment "Asynchronous Memory Configuration"
Bryan Wu1394f032007-05-06 14:50:22 -07001016
Mike Frysingerddf416b2007-10-10 18:06:47 +08001017menu "EBIU_AMGCTL Global Control"
Bryan Wu1394f032007-05-06 14:50:22 -07001018config C_AMCKEN
1019 bool "Enable CLKOUT"
1020 default y
1021
1022config C_CDPRIO
1023 bool "DMA has priority over core for ext. accesses"
1024 default n
1025
1026config C_B0PEN
1027 depends on BF561
1028 bool "Bank 0 16 bit packing enable"
1029 default y
1030
1031config C_B1PEN
1032 depends on BF561
1033 bool "Bank 1 16 bit packing enable"
1034 default y
1035
1036config C_B2PEN
1037 depends on BF561
1038 bool "Bank 2 16 bit packing enable"
1039 default y
1040
1041config C_B3PEN
1042 depends on BF561
1043 bool "Bank 3 16 bit packing enable"
1044 default n
1045
1046choice
Matt LaPlante692105b2009-01-26 11:12:25 +01001047 prompt "Enable Asynchronous Memory Banks"
Bryan Wu1394f032007-05-06 14:50:22 -07001048 default C_AMBEN_ALL
1049
1050config C_AMBEN
1051 bool "Disable All Banks"
1052
1053config C_AMBEN_B0
1054 bool "Enable Bank 0"
1055
1056config C_AMBEN_B0_B1
1057 bool "Enable Bank 0 & 1"
1058
1059config C_AMBEN_B0_B1_B2
1060 bool "Enable Bank 0 & 1 & 2"
1061
1062config C_AMBEN_ALL
1063 bool "Enable All Banks"
1064endchoice
1065endmenu
1066
1067menu "EBIU_AMBCTL Control"
1068config BANK_0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001069 hex "Bank 0 (AMBCTL0.L)"
Bryan Wu1394f032007-05-06 14:50:22 -07001070 default 0x7BB0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001071 help
1072 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1073 used to control the Asynchronous Memory Bank 0 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001074
1075config BANK_1
Mike Frysingerc8342f82009-03-31 00:18:35 +00001076 hex "Bank 1 (AMBCTL0.H)"
Bryan Wu1394f032007-05-06 14:50:22 -07001077 default 0x7BB0
Michael Hennerich197fba52008-05-07 17:03:27 +08001078 default 0x5558 if BF54x
Mike Frysingerc8342f82009-03-31 00:18:35 +00001079 help
1080 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1081 used to control the Asynchronous Memory Bank 1 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001082
1083config BANK_2
Mike Frysingerc8342f82009-03-31 00:18:35 +00001084 hex "Bank 2 (AMBCTL1.L)"
Bryan Wu1394f032007-05-06 14:50:22 -07001085 default 0x7BB0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001086 help
1087 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1088 used to control the Asynchronous Memory Bank 2 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001089
1090config BANK_3
Mike Frysingerc8342f82009-03-31 00:18:35 +00001091 hex "Bank 3 (AMBCTL1.H)"
Bryan Wu1394f032007-05-06 14:50:22 -07001092 default 0x99B3
Mike Frysingerc8342f82009-03-31 00:18:35 +00001093 help
1094 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1095 used to control the Asynchronous Memory Bank 3 settings.
1096
Bryan Wu1394f032007-05-06 14:50:22 -07001097endmenu
1098
Sonic Zhange40540b2007-11-21 23:49:52 +08001099config EBIU_MBSCTLVAL
1100 hex "EBIU Bank Select Control Register"
1101 depends on BF54x
1102 default 0
1103
1104config EBIU_MODEVAL
1105 hex "Flash Memory Mode Control Register"
1106 depends on BF54x
1107 default 1
1108
1109config EBIU_FCTLVAL
1110 hex "Flash Memory Bank Control Register"
1111 depends on BF54x
1112 default 6
Bryan Wu1394f032007-05-06 14:50:22 -07001113endmenu
1114
1115#############################################################################
1116menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1117
1118config PCI
1119 bool "PCI support"
Adrian Bunka95ca3b2008-08-27 10:55:05 +08001120 depends on BROKEN
Bryan Wu1394f032007-05-06 14:50:22 -07001121 help
1122 Support for PCI bus.
1123
1124source "drivers/pci/Kconfig"
1125
1126config HOTPLUG
1127 bool "Support for hot-pluggable device"
1128 help
1129 Say Y here if you want to plug devices into your computer while
1130 the system is running, and be able to use them quickly. In many
1131 cases, the devices can likewise be unplugged at any time too.
1132
1133 One well known example of this is PCMCIA- or PC-cards, credit-card
1134 size devices such as network cards, modems or hard drives which are
1135 plugged into slots found on all modern laptop computers. Another
1136 example, used on modern desktops as well as laptops, is USB.
1137
Johannes Berga81792f2008-07-08 19:00:25 +02001138 Enable HOTPLUG and build a modular kernel. Get agent software
1139 (from <http://linux-hotplug.sourceforge.net/>) and install it.
Bryan Wu1394f032007-05-06 14:50:22 -07001140 Then your kernel will automatically call out to a user mode "policy
1141 agent" (/sbin/hotplug) to load modules and set up software needed
1142 to use devices as you hotplug them.
1143
1144source "drivers/pcmcia/Kconfig"
1145
1146source "drivers/pci/hotplug/Kconfig"
1147
1148endmenu
1149
1150menu "Executable file formats"
1151
1152source "fs/Kconfig.binfmt"
1153
1154endmenu
1155
1156menu "Power management options"
1157source "kernel/power/Kconfig"
1158
Johannes Bergf4cb5702007-12-08 02:14:00 +01001159config ARCH_SUSPEND_POSSIBLE
1160 def_bool y
1161 depends on !SMP
1162
Bryan Wu1394f032007-05-06 14:50:22 -07001163choice
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001164 prompt "Standby Power Saving Mode"
Bryan Wu1394f032007-05-06 14:50:22 -07001165 depends on PM
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001166 default PM_BFIN_SLEEP_DEEPER
1167config PM_BFIN_SLEEP_DEEPER
1168 bool "Sleep Deeper"
Bryan Wu1394f032007-05-06 14:50:22 -07001169 help
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001170 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1171 power dissipation by disabling the clock to the processor core (CCLK).
1172 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1173 to 0.85 V to provide the greatest power savings, while preserving the
1174 processor state.
1175 The PLL and system clock (SCLK) continue to operate at a very low
1176 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1177 the SDRAM is put into Self Refresh Mode. Typically an external event
1178 such as GPIO interrupt or RTC activity wakes up the processor.
1179 Various Peripherals such as UART, SPORT, PPI may not function as
1180 normal during Sleep Deeper, due to the reduced SCLK frequency.
1181 When in the sleep mode, system DMA access to L1 memory is not supported.
Bryan Wu1394f032007-05-06 14:50:22 -07001182
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001183 If unsure, select "Sleep Deeper".
1184
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001185config PM_BFIN_SLEEP
1186 bool "Sleep"
1187 help
1188 Sleep Mode (High Power Savings) - The sleep mode reduces power
1189 dissipation by disabling the clock to the processor core (CCLK).
1190 The PLL and system clock (SCLK), however, continue to operate in
1191 this mode. Typically an external event or RTC activity will wake
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001192 up the processor. When in the sleep mode, system DMA access to L1
1193 memory is not supported.
1194
1195 If unsure, select "Sleep Deeper".
Bryan Wu1394f032007-05-06 14:50:22 -07001196endchoice
1197
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001198config PM_WAKEUP_BY_GPIO
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001199 bool "Allow Wakeup from Standby by GPIO"
Michael Hennerichff19fed2009-03-04 17:35:51 +08001200 depends on PM && !BF54x
Bryan Wu1394f032007-05-06 14:50:22 -07001201
1202config PM_WAKEUP_GPIO_NUMBER
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001203 int "GPIO number"
Bryan Wu1394f032007-05-06 14:50:22 -07001204 range 0 47
1205 depends on PM_WAKEUP_BY_GPIO
Mike Frysingerd1a33362008-11-18 17:48:22 +08001206 default 2
Bryan Wu1394f032007-05-06 14:50:22 -07001207
1208choice
1209 prompt "GPIO Polarity"
1210 depends on PM_WAKEUP_BY_GPIO
1211 default PM_WAKEUP_GPIO_POLAR_H
1212config PM_WAKEUP_GPIO_POLAR_H
1213 bool "Active High"
1214config PM_WAKEUP_GPIO_POLAR_L
1215 bool "Active Low"
1216config PM_WAKEUP_GPIO_POLAR_EDGE_F
1217 bool "Falling EDGE"
1218config PM_WAKEUP_GPIO_POLAR_EDGE_R
1219 bool "Rising EDGE"
1220config PM_WAKEUP_GPIO_POLAR_EDGE_B
1221 bool "Both EDGE"
1222endchoice
1223
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001224comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1225 depends on PM
1226
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001227config PM_BFIN_WAKE_PH6
1228 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001229 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001230 default n
1231 help
1232 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1233
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001234config PM_BFIN_WAKE_GP
1235 bool "Allow Wake-Up from GPIOs"
1236 depends on PM && BF54x
1237 default n
1238 help
1239 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
Michael Hennerich19986282009-03-05 16:45:55 +08001240 (all processors, except ADSP-BF549). This option sets
1241 the general-purpose wake-up enable (GPWE) control bit to enable
1242 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1243 On ADSP-BF549 this option enables the the same functionality on the
1244 /MRXON pin also PH7.
1245
Bryan Wu1394f032007-05-06 14:50:22 -07001246endmenu
1247
Bryan Wu1394f032007-05-06 14:50:22 -07001248menu "CPU Frequency scaling"
1249
1250source "drivers/cpufreq/Kconfig"
1251
Michael Hennerich5ad2ca52008-11-18 17:48:22 +08001252config BFIN_CPU_FREQ
1253 bool
1254 depends on CPU_FREQ
1255 select CPU_FREQ_TABLE
1256 default y
1257
Michael Hennerich14b03202008-05-07 11:41:26 +08001258config CPU_VOLTAGE
1259 bool "CPU Voltage scaling"
Michael Hennerich73feb5c2009-01-07 23:14:39 +08001260 depends on EXPERIMENTAL
Michael Hennerich14b03202008-05-07 11:41:26 +08001261 depends on CPU_FREQ
1262 default n
1263 help
1264 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1265 This option violates the PLL BYPASS recommendation in the Blackfin Processor
Michael Hennerich73feb5c2009-01-07 23:14:39 +08001266 manuals. There is a theoretical risk that during VDDINT transitions
Michael Hennerich14b03202008-05-07 11:41:26 +08001267 the PLL may unlock.
1268
Bryan Wu1394f032007-05-06 14:50:22 -07001269endmenu
1270
Bryan Wu1394f032007-05-06 14:50:22 -07001271source "net/Kconfig"
1272
1273source "drivers/Kconfig"
1274
1275source "fs/Kconfig"
1276
Mike Frysinger74ce8322007-11-21 23:50:49 +08001277source "arch/blackfin/Kconfig.debug"
Bryan Wu1394f032007-05-06 14:50:22 -07001278
1279source "security/Kconfig"
1280
1281source "crypto/Kconfig"
1282
1283source "lib/Kconfig"