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Ben Skeggs4b223ee2010-08-03 10:00:56 +10001/*
Ben Skeggsebb945a2012-07-20 08:17:34 +10002 * Copyright 2012 Red Hat Inc.
Ben Skeggs4b223ee2010-08-03 10:00:56 +10003 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
Ben Skeggs05c71452015-01-14 15:28:47 +100024#include <engine/fifo.h>
Ben Skeggs4b223ee2010-08-03 10:00:56 +100025
Ben Skeggsebb945a2012-07-20 08:17:34 +100026#include <core/client.h>
Ben Skeggsebb945a2012-07-20 08:17:34 +100027#include <core/engctx.h>
Ben Skeggsebb945a2012-07-20 08:17:34 +100028#include <core/enum.h>
Ben Skeggs05c71452015-01-14 15:28:47 +100029#include <core/handle.h>
Ben Skeggsebb945a2012-07-20 08:17:34 +100030#include <subdev/bar.h>
Ben Skeggs52225552013-12-23 01:51:16 +100031#include <subdev/fb.h>
Ben Skeggs5ce3bf32015-01-14 09:57:36 +100032#include <subdev/mmu.h>
Ben Skeggs05c71452015-01-14 15:28:47 +100033#include <subdev/timer.h>
Ben Skeggsebb945a2012-07-20 08:17:34 +100034
Ben Skeggs05c71452015-01-14 15:28:47 +100035#include <nvif/class.h>
36#include <nvif/unpack.h>
Ben Skeggsb2b09932010-11-24 10:47:15 +100037
Ben Skeggs6189f1b2015-08-20 14:54:07 +100038struct gf100_fifo {
Ben Skeggs05c71452015-01-14 15:28:47 +100039 struct nvkm_fifo base;
Ben Skeggs24e83412014-02-05 11:18:38 +100040
41 struct work_struct fault;
42 u64 mask;
43
Ben Skeggsa07d0e72014-02-22 00:28:47 +100044 struct {
Ben Skeggs05c71452015-01-14 15:28:47 +100045 struct nvkm_gpuobj *mem[2];
Ben Skeggsa07d0e72014-02-22 00:28:47 +100046 int active;
47 wait_queue_head_t wait;
48 } runlist;
Ben Skeggs24e83412014-02-05 11:18:38 +100049
Ben Skeggs9da226f2012-07-13 16:54:45 +100050 struct {
Ben Skeggs05c71452015-01-14 15:28:47 +100051 struct nvkm_gpuobj *mem;
52 struct nvkm_vma bar;
Ben Skeggs9da226f2012-07-13 16:54:45 +100053 } user;
Ben Skeggsec9c0882010-12-31 12:10:49 +100054 int spoon_nr;
Ben Skeggsb2b09932010-11-24 10:47:15 +100055};
56
Ben Skeggs05c71452015-01-14 15:28:47 +100057struct gf100_fifo_base {
58 struct nvkm_fifo_base base;
59 struct nvkm_gpuobj *pgd;
60 struct nvkm_vm *vm;
Ben Skeggsebb945a2012-07-20 08:17:34 +100061};
62
Ben Skeggs05c71452015-01-14 15:28:47 +100063struct gf100_fifo_chan {
64 struct nvkm_fifo_chan base;
Ben Skeggse2822b72014-02-22 00:52:45 +100065 enum {
66 STOPPED,
67 RUNNING,
68 KILLED
69 } state;
Ben Skeggsb2b09932010-11-24 10:47:15 +100070};
71
Ben Skeggsebb945a2012-07-20 08:17:34 +100072/*******************************************************************************
73 * FIFO channel objects
74 ******************************************************************************/
75
Ben Skeggsb2b09932010-11-24 10:47:15 +100076static void
Ben Skeggs6189f1b2015-08-20 14:54:07 +100077gf100_fifo_runlist_update(struct gf100_fifo *fifo)
Ben Skeggsb2b09932010-11-24 10:47:15 +100078{
Ben Skeggs87744402015-08-20 14:54:10 +100079 struct nvkm_device *device = fifo->base.engine.subdev.device;
80 struct nvkm_bar *bar = device->bar;
Ben Skeggs05c71452015-01-14 15:28:47 +100081 struct nvkm_gpuobj *cur;
Ben Skeggsb2b09932010-11-24 10:47:15 +100082 int i, p;
83
Ben Skeggs6189f1b2015-08-20 14:54:07 +100084 mutex_lock(&nv_subdev(fifo)->mutex);
85 cur = fifo->runlist.mem[fifo->runlist.active];
86 fifo->runlist.active = !fifo->runlist.active;
Ben Skeggsb2b09932010-11-24 10:47:15 +100087
88 for (i = 0, p = 0; i < 128; i++) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +100089 struct gf100_fifo_chan *chan = (void *)fifo->base.channel[i];
Ben Skeggse2822b72014-02-22 00:52:45 +100090 if (chan && chan->state == RUNNING) {
91 nv_wo32(cur, p + 0, i);
92 nv_wo32(cur, p + 4, 0x00000004);
93 p += 8;
94 }
Ben Skeggsb2b09932010-11-24 10:47:15 +100095 }
Ben Skeggsebb945a2012-07-20 08:17:34 +100096 bar->flush(bar);
Ben Skeggsb2b09932010-11-24 10:47:15 +100097
Ben Skeggs87744402015-08-20 14:54:10 +100098 nvkm_wr32(device, 0x002270, cur->addr >> 12);
99 nvkm_wr32(device, 0x002274, 0x01f00000 | (p >> 3));
Ben Skeggse2822b72014-02-22 00:52:45 +1000100
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000101 if (wait_event_timeout(fifo->runlist.wait,
Ben Skeggs87744402015-08-20 14:54:10 +1000102 !(nvkm_rd32(device, 0x00227c) & 0x00100000),
Ben Skeggs3cf62902014-02-22 01:05:01 +1000103 msecs_to_jiffies(2000)) == 0)
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000104 nv_error(fifo, "runlist update timeout\n");
105 mutex_unlock(&nv_subdev(fifo)->mutex);
Ben Skeggsb2b09932010-11-24 10:47:15 +1000106}
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000107
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000108static int
Ben Skeggs05c71452015-01-14 15:28:47 +1000109gf100_fifo_context_attach(struct nvkm_object *parent,
110 struct nvkm_object *object)
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000111{
Ben Skeggs05c71452015-01-14 15:28:47 +1000112 struct nvkm_bar *bar = nvkm_bar(parent);
113 struct gf100_fifo_base *base = (void *)parent->parent;
114 struct nvkm_engctx *ectx = (void *)object;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000115 u32 addr;
116 int ret;
Ben Skeggsb2b09932010-11-24 10:47:15 +1000117
Ben Skeggsebb945a2012-07-20 08:17:34 +1000118 switch (nv_engidx(object->engine)) {
Ben Skeggs37a5d022015-01-14 12:50:04 +1000119 case NVDEV_ENGINE_SW : return 0;
120 case NVDEV_ENGINE_GR : addr = 0x0210; break;
121 case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
122 case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
123 case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
124 case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
125 case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000126 default:
127 return -EINVAL;
Ben Skeggsb2b09932010-11-24 10:47:15 +1000128 }
129
Ben Skeggsebb945a2012-07-20 08:17:34 +1000130 if (!ectx->vma.node) {
Ben Skeggs05c71452015-01-14 15:28:47 +1000131 ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
132 NV_MEM_ACCESS_RW, &ectx->vma);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000133 if (ret)
134 return ret;
Ben Skeggs4c2d4222012-08-10 15:10:34 +1000135
136 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000137 }
Ben Skeggsb2b09932010-11-24 10:47:15 +1000138
Ben Skeggsebb945a2012-07-20 08:17:34 +1000139 nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
140 nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
141 bar->flush(bar);
142 return 0;
143}
Ben Skeggsb2b09932010-11-24 10:47:15 +1000144
Ben Skeggsebb945a2012-07-20 08:17:34 +1000145static int
Ben Skeggs05c71452015-01-14 15:28:47 +1000146gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend,
147 struct nvkm_object *object)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000148{
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000149 struct gf100_fifo *fifo = (void *)parent->engine;
Ben Skeggs05c71452015-01-14 15:28:47 +1000150 struct gf100_fifo_base *base = (void *)parent->parent;
151 struct gf100_fifo_chan *chan = (void *)parent;
Ben Skeggs87744402015-08-20 14:54:10 +1000152 struct nvkm_device *device = fifo->base.engine.subdev.device;
153 struct nvkm_bar *bar = device->bar;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000154 u32 addr;
155
156 switch (nv_engidx(object->engine)) {
Ben Skeggs37a5d022015-01-14 12:50:04 +1000157 case NVDEV_ENGINE_SW : return 0;
158 case NVDEV_ENGINE_GR : addr = 0x0210; break;
159 case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
160 case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
161 case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
162 case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
163 case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000164 default:
165 return -EINVAL;
166 }
167
Ben Skeggs87744402015-08-20 14:54:10 +1000168 nvkm_wr32(device, 0x002634, chan->base.chid);
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000169 if (!nv_wait(fifo, 0x002634, 0xffffffff, chan->base.chid)) {
170 nv_error(fifo, "channel %d [%s] kick timeout\n",
Ben Skeggs05c71452015-01-14 15:28:47 +1000171 chan->base.chid, nvkm_client_name(chan));
Ben Skeggsebb945a2012-07-20 08:17:34 +1000172 if (suspend)
173 return -EBUSY;
174 }
175
Ben Skeggsedc260d2012-11-27 11:05:36 +1000176 nv_wo32(base, addr + 0x00, 0x00000000);
177 nv_wo32(base, addr + 0x04, 0x00000000);
178 bar->flush(bar);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000179 return 0;
180}
181
182static int
Ben Skeggs05c71452015-01-14 15:28:47 +1000183gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
184 struct nvkm_oclass *oclass, void *data, u32 size,
185 struct nvkm_object **pobject)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000186{
Ben Skeggsbbf89062014-08-10 04:10:25 +1000187 union {
188 struct nv50_channel_gpfifo_v0 v0;
189 } *args = data;
Ben Skeggs05c71452015-01-14 15:28:47 +1000190 struct nvkm_bar *bar = nvkm_bar(parent);
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000191 struct gf100_fifo *fifo = (void *)engine;
Ben Skeggs05c71452015-01-14 15:28:47 +1000192 struct gf100_fifo_base *base = (void *)parent;
193 struct gf100_fifo_chan *chan;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000194 u64 usermem, ioffset, ilength;
195 int ret, i;
196
Ben Skeggsbbf89062014-08-10 04:10:25 +1000197 nv_ioctl(parent, "create channel gpfifo size %d\n", size);
198 if (nvif_unpack(args->v0, 0, 0, false)) {
199 nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
200 "ioffset %016llx ilength %08x\n",
201 args->v0.version, args->v0.pushbuf, args->v0.ioffset,
202 args->v0.ilength);
203 } else
204 return ret;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000205
Ben Skeggs05c71452015-01-14 15:28:47 +1000206 ret = nvkm_fifo_channel_create(parent, engine, oclass, 1,
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000207 fifo->user.bar.offset, 0x1000,
Ben Skeggs05c71452015-01-14 15:28:47 +1000208 args->v0.pushbuf,
209 (1ULL << NVDEV_ENGINE_SW) |
210 (1ULL << NVDEV_ENGINE_GR) |
211 (1ULL << NVDEV_ENGINE_CE0) |
212 (1ULL << NVDEV_ENGINE_CE1) |
213 (1ULL << NVDEV_ENGINE_MSVLD) |
214 (1ULL << NVDEV_ENGINE_MSPDEC) |
215 (1ULL << NVDEV_ENGINE_MSPPP), &chan);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000216 *pobject = nv_object(chan);
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000217 if (ret)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000218 return ret;
219
Ben Skeggsbbf89062014-08-10 04:10:25 +1000220 args->v0.chid = chan->base.chid;
221
Ben Skeggs05c71452015-01-14 15:28:47 +1000222 nv_parent(chan)->context_attach = gf100_fifo_context_attach;
223 nv_parent(chan)->context_detach = gf100_fifo_context_detach;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000224
225 usermem = chan->base.chid * 0x1000;
Ben Skeggsbbf89062014-08-10 04:10:25 +1000226 ioffset = args->v0.ioffset;
227 ilength = order_base_2(args->v0.ilength / 8);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000228
229 for (i = 0; i < 0x1000; i += 4)
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000230 nv_wo32(fifo->user.mem, usermem + i, 0x00000000);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000231
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000232 nv_wo32(base, 0x08, lower_32_bits(fifo->user.mem->addr + usermem));
233 nv_wo32(base, 0x0c, upper_32_bits(fifo->user.mem->addr + usermem));
Ben Skeggsebb945a2012-07-20 08:17:34 +1000234 nv_wo32(base, 0x10, 0x0000face);
235 nv_wo32(base, 0x30, 0xfffff902);
236 nv_wo32(base, 0x48, lower_32_bits(ioffset));
237 nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
238 nv_wo32(base, 0x54, 0x00000002);
239 nv_wo32(base, 0x84, 0x20400000);
240 nv_wo32(base, 0x94, 0x30000001);
241 nv_wo32(base, 0x9c, 0x00000100);
242 nv_wo32(base, 0xa4, 0x1f1f1f1f);
243 nv_wo32(base, 0xa8, 0x1f1f1f1f);
244 nv_wo32(base, 0xac, 0x0000001f);
245 nv_wo32(base, 0xb8, 0xf8000000);
246 nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
247 nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
248 bar->flush(bar);
249 return 0;
250}
251
252static int
Ben Skeggs05c71452015-01-14 15:28:47 +1000253gf100_fifo_chan_init(struct nvkm_object *object)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000254{
Ben Skeggs05c71452015-01-14 15:28:47 +1000255 struct nvkm_gpuobj *base = nv_gpuobj(object->parent);
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000256 struct gf100_fifo *fifo = (void *)object->engine;
Ben Skeggs05c71452015-01-14 15:28:47 +1000257 struct gf100_fifo_chan *chan = (void *)object;
Ben Skeggs87744402015-08-20 14:54:10 +1000258 struct nvkm_device *device = fifo->base.engine.subdev.device;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000259 u32 chid = chan->base.chid;
260 int ret;
261
Ben Skeggs05c71452015-01-14 15:28:47 +1000262 ret = nvkm_fifo_channel_init(&chan->base);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000263 if (ret)
264 return ret;
265
Ben Skeggs87744402015-08-20 14:54:10 +1000266 nvkm_wr32(device, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
Ben Skeggse2822b72014-02-22 00:52:45 +1000267
268 if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
Ben Skeggs87744402015-08-20 14:54:10 +1000269 nvkm_wr32(device, 0x003004 + (chid * 8), 0x001f0001);
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000270 gf100_fifo_runlist_update(fifo);
Ben Skeggse2822b72014-02-22 00:52:45 +1000271 }
272
Ben Skeggsebb945a2012-07-20 08:17:34 +1000273 return 0;
274}
275
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000276static void gf100_fifo_intr_engine(struct gf100_fifo *fifo);
Ben Skeggse99bf012014-02-22 00:18:17 +1000277
Ben Skeggsebb945a2012-07-20 08:17:34 +1000278static int
Ben Skeggs05c71452015-01-14 15:28:47 +1000279gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000280{
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000281 struct gf100_fifo *fifo = (void *)object->engine;
Ben Skeggs05c71452015-01-14 15:28:47 +1000282 struct gf100_fifo_chan *chan = (void *)object;
Ben Skeggs87744402015-08-20 14:54:10 +1000283 struct nvkm_device *device = fifo->base.engine.subdev.device;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000284 u32 chid = chan->base.chid;
285
Ben Skeggse2822b72014-02-22 00:52:45 +1000286 if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
Ben Skeggs87744402015-08-20 14:54:10 +1000287 nvkm_mask(device, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000288 gf100_fifo_runlist_update(fifo);
Ben Skeggse2822b72014-02-22 00:52:45 +1000289 }
Ben Skeggse99bf012014-02-22 00:18:17 +1000290
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000291 gf100_fifo_intr_engine(fifo);
Ben Skeggse99bf012014-02-22 00:18:17 +1000292
Ben Skeggs87744402015-08-20 14:54:10 +1000293 nvkm_wr32(device, 0x003000 + (chid * 8), 0x00000000);
Ben Skeggs05c71452015-01-14 15:28:47 +1000294 return nvkm_fifo_channel_fini(&chan->base, suspend);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000295}
296
Ben Skeggs05c71452015-01-14 15:28:47 +1000297static struct nvkm_ofuncs
298gf100_fifo_ofuncs = {
299 .ctor = gf100_fifo_chan_ctor,
300 .dtor = _nvkm_fifo_channel_dtor,
301 .init = gf100_fifo_chan_init,
302 .fini = gf100_fifo_chan_fini,
303 .map = _nvkm_fifo_channel_map,
304 .rd32 = _nvkm_fifo_channel_rd32,
305 .wr32 = _nvkm_fifo_channel_wr32,
306 .ntfy = _nvkm_fifo_channel_ntfy
Ben Skeggsebb945a2012-07-20 08:17:34 +1000307};
308
Ben Skeggs05c71452015-01-14 15:28:47 +1000309static struct nvkm_oclass
310gf100_fifo_sclass[] = {
311 { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs },
Ben Skeggsebb945a2012-07-20 08:17:34 +1000312 {}
313};
314
315/*******************************************************************************
316 * FIFO context - instmem heap and vm setup
317 ******************************************************************************/
318
319static int
Ben Skeggs05c71452015-01-14 15:28:47 +1000320gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
321 struct nvkm_oclass *oclass, void *data, u32 size,
322 struct nvkm_object **pobject)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000323{
Ben Skeggs05c71452015-01-14 15:28:47 +1000324 struct gf100_fifo_base *base;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000325 int ret;
326
Ben Skeggs05c71452015-01-14 15:28:47 +1000327 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
328 0x1000, NVOBJ_FLAG_ZERO_ALLOC |
329 NVOBJ_FLAG_HEAP, &base);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000330 *pobject = nv_object(base);
331 if (ret)
332 return ret;
333
Ben Skeggs05c71452015-01-14 15:28:47 +1000334 ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
335 &base->pgd);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000336 if (ret)
337 return ret;
338
339 nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
340 nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
341 nv_wo32(base, 0x0208, 0xffffffff);
342 nv_wo32(base, 0x020c, 0x000000ff);
343
Ben Skeggs05c71452015-01-14 15:28:47 +1000344 ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000345 if (ret)
346 return ret;
347
348 return 0;
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000349}
350
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000351static void
Ben Skeggs05c71452015-01-14 15:28:47 +1000352gf100_fifo_context_dtor(struct nvkm_object *object)
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000353{
Ben Skeggs05c71452015-01-14 15:28:47 +1000354 struct gf100_fifo_base *base = (void *)object;
355 nvkm_vm_ref(NULL, &base->vm, base->pgd);
356 nvkm_gpuobj_ref(NULL, &base->pgd);
357 nvkm_fifo_context_destroy(&base->base);
Ben Skeggsb2b09932010-11-24 10:47:15 +1000358}
359
Ben Skeggs05c71452015-01-14 15:28:47 +1000360static struct nvkm_oclass
361gf100_fifo_cclass = {
Ben Skeggsebb945a2012-07-20 08:17:34 +1000362 .handle = NV_ENGCTX(FIFO, 0xc0),
Ben Skeggs05c71452015-01-14 15:28:47 +1000363 .ofuncs = &(struct nvkm_ofuncs) {
364 .ctor = gf100_fifo_context_ctor,
365 .dtor = gf100_fifo_context_dtor,
366 .init = _nvkm_fifo_context_init,
367 .fini = _nvkm_fifo_context_fini,
368 .rd32 = _nvkm_fifo_context_rd32,
369 .wr32 = _nvkm_fifo_context_wr32,
Ben Skeggsebb945a2012-07-20 08:17:34 +1000370 },
371};
Ben Skeggsb2b09932010-11-24 10:47:15 +1000372
Ben Skeggsebb945a2012-07-20 08:17:34 +1000373/*******************************************************************************
374 * PFIFO engine
375 ******************************************************************************/
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000376
Ben Skeggs24e83412014-02-05 11:18:38 +1000377static inline int
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000378gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn)
Ben Skeggs24e83412014-02-05 11:18:38 +1000379{
380 switch (engn) {
Ben Skeggs37a5d022015-01-14 12:50:04 +1000381 case NVDEV_ENGINE_GR : engn = 0; break;
382 case NVDEV_ENGINE_MSVLD : engn = 1; break;
383 case NVDEV_ENGINE_MSPPP : engn = 2; break;
384 case NVDEV_ENGINE_MSPDEC: engn = 3; break;
385 case NVDEV_ENGINE_CE0 : engn = 4; break;
386 case NVDEV_ENGINE_CE1 : engn = 5; break;
Ben Skeggs24e83412014-02-05 11:18:38 +1000387 default:
388 return -1;
389 }
390
391 return engn;
392}
393
Ben Skeggs05c71452015-01-14 15:28:47 +1000394static inline struct nvkm_engine *
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000395gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
Ben Skeggs24e83412014-02-05 11:18:38 +1000396{
397 switch (engn) {
398 case 0: engn = NVDEV_ENGINE_GR; break;
Ben Skeggseccf7e8a2015-01-14 10:09:24 +1000399 case 1: engn = NVDEV_ENGINE_MSVLD; break;
Ben Skeggsfd8666f2015-01-14 12:26:28 +1000400 case 2: engn = NVDEV_ENGINE_MSPPP; break;
Ben Skeggs37a5d022015-01-14 12:50:04 +1000401 case 3: engn = NVDEV_ENGINE_MSPDEC; break;
Ben Skeggsaedf24f2015-01-14 11:50:20 +1000402 case 4: engn = NVDEV_ENGINE_CE0; break;
403 case 5: engn = NVDEV_ENGINE_CE1; break;
Ben Skeggs24e83412014-02-05 11:18:38 +1000404 default:
405 return NULL;
406 }
407
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000408 return nvkm_engine(fifo, engn);
Ben Skeggs24e83412014-02-05 11:18:38 +1000409}
410
411static void
Ben Skeggs05c71452015-01-14 15:28:47 +1000412gf100_fifo_recover_work(struct work_struct *work)
Ben Skeggs24e83412014-02-05 11:18:38 +1000413{
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000414 struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault);
Ben Skeggs87744402015-08-20 14:54:10 +1000415 struct nvkm_device *device = fifo->base.engine.subdev.device;
Ben Skeggs05c71452015-01-14 15:28:47 +1000416 struct nvkm_object *engine;
Ben Skeggs24e83412014-02-05 11:18:38 +1000417 unsigned long flags;
418 u32 engn, engm = 0;
419 u64 mask, todo;
420
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000421 spin_lock_irqsave(&fifo->base.lock, flags);
422 mask = fifo->mask;
423 fifo->mask = 0ULL;
424 spin_unlock_irqrestore(&fifo->base.lock, flags);
Ben Skeggs24e83412014-02-05 11:18:38 +1000425
426 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000427 engm |= 1 << gf100_fifo_engidx(fifo, engn);
Ben Skeggs87744402015-08-20 14:54:10 +1000428 nvkm_mask(device, 0x002630, engm, engm);
Ben Skeggs24e83412014-02-05 11:18:38 +1000429
430 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000431 if ((engine = (void *)nvkm_engine(fifo, engn))) {
Ben Skeggs24e83412014-02-05 11:18:38 +1000432 nv_ofuncs(engine)->fini(engine, false);
433 WARN_ON(nv_ofuncs(engine)->init(engine));
434 }
435 }
436
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000437 gf100_fifo_runlist_update(fifo);
Ben Skeggs87744402015-08-20 14:54:10 +1000438 nvkm_wr32(device, 0x00262c, engm);
439 nvkm_mask(device, 0x002630, engm, 0x00000000);
Ben Skeggs24e83412014-02-05 11:18:38 +1000440}
441
442static void
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000443gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
Ben Skeggs05c71452015-01-14 15:28:47 +1000444 struct gf100_fifo_chan *chan)
Ben Skeggs24e83412014-02-05 11:18:38 +1000445{
Ben Skeggs87744402015-08-20 14:54:10 +1000446 struct nvkm_device *device = fifo->base.engine.subdev.device;
Ben Skeggs24e83412014-02-05 11:18:38 +1000447 u32 chid = chan->base.chid;
448 unsigned long flags;
449
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000450 nv_error(fifo, "%s engine fault on channel %d, recovering...\n",
Ben Skeggs24e83412014-02-05 11:18:38 +1000451 nv_subdev(engine)->name, chid);
452
Ben Skeggs87744402015-08-20 14:54:10 +1000453 nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
Ben Skeggs24e83412014-02-05 11:18:38 +1000454 chan->state = KILLED;
455
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000456 spin_lock_irqsave(&fifo->base.lock, flags);
457 fifo->mask |= 1ULL << nv_engidx(engine);
458 spin_unlock_irqrestore(&fifo->base.lock, flags);
459 schedule_work(&fifo->fault);
Ben Skeggs24e83412014-02-05 11:18:38 +1000460}
461
Ben Skeggs083c2142014-02-22 00:31:29 +1000462static int
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000463gf100_fifo_swmthd(struct gf100_fifo *fifo, u32 chid, u32 mthd, u32 data)
Ben Skeggs083c2142014-02-22 00:31:29 +1000464{
Ben Skeggs05c71452015-01-14 15:28:47 +1000465 struct gf100_fifo_chan *chan = NULL;
466 struct nvkm_handle *bind;
Ben Skeggs083c2142014-02-22 00:31:29 +1000467 unsigned long flags;
468 int ret = -EINVAL;
469
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000470 spin_lock_irqsave(&fifo->base.lock, flags);
471 if (likely(chid >= fifo->base.min && chid <= fifo->base.max))
472 chan = (void *)fifo->base.channel[chid];
Ben Skeggs083c2142014-02-22 00:31:29 +1000473 if (unlikely(!chan))
474 goto out;
475
Ben Skeggs05c71452015-01-14 15:28:47 +1000476 bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e);
Ben Skeggs083c2142014-02-22 00:31:29 +1000477 if (likely(bind)) {
478 if (!mthd || !nv_call(bind->object, mthd, data))
479 ret = 0;
Ben Skeggs05c71452015-01-14 15:28:47 +1000480 nvkm_namedb_put(bind);
Ben Skeggs083c2142014-02-22 00:31:29 +1000481 }
482
483out:
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000484 spin_unlock_irqrestore(&fifo->base.lock, flags);
Ben Skeggs083c2142014-02-22 00:31:29 +1000485 return ret;
486}
487
Ben Skeggs05c71452015-01-14 15:28:47 +1000488static const struct nvkm_enum
489gf100_fifo_sched_reason[] = {
Ben Skeggs40476532014-02-22 01:18:46 +1000490 { 0x0a, "CTXSW_TIMEOUT" },
491 {}
492};
493
494static void
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000495gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo)
Ben Skeggs61fdf622014-02-22 12:44:23 +1000496{
Ben Skeggs87744402015-08-20 14:54:10 +1000497 struct nvkm_device *device = fifo->base.engine.subdev.device;
Ben Skeggs05c71452015-01-14 15:28:47 +1000498 struct nvkm_engine *engine;
499 struct gf100_fifo_chan *chan;
Ben Skeggs61fdf622014-02-22 12:44:23 +1000500 u32 engn;
501
502 for (engn = 0; engn < 6; engn++) {
Ben Skeggs87744402015-08-20 14:54:10 +1000503 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));
Ben Skeggs61fdf622014-02-22 12:44:23 +1000504 u32 busy = (stat & 0x80000000);
505 u32 save = (stat & 0x00100000); /* maybe? */
506 u32 unk0 = (stat & 0x00040000);
507 u32 unk1 = (stat & 0x00001000);
508 u32 chid = (stat & 0x0000007f);
509 (void)save;
510
511 if (busy && unk0 && unk1) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000512 if (!(chan = (void *)fifo->base.channel[chid]))
Ben Skeggs61fdf622014-02-22 12:44:23 +1000513 continue;
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000514 if (!(engine = gf100_fifo_engine(fifo, engn)))
Ben Skeggs61fdf622014-02-22 12:44:23 +1000515 continue;
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000516 gf100_fifo_recover(fifo, engine, chan);
Ben Skeggs61fdf622014-02-22 12:44:23 +1000517 }
518 }
519}
520
521static void
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000522gf100_fifo_intr_sched(struct gf100_fifo *fifo)
Ben Skeggs40476532014-02-22 01:18:46 +1000523{
Ben Skeggs87744402015-08-20 14:54:10 +1000524 struct nvkm_device *device = fifo->base.engine.subdev.device;
525 u32 intr = nvkm_rd32(device, 0x00254c);
Ben Skeggs40476532014-02-22 01:18:46 +1000526 u32 code = intr & 0x000000ff;
Ben Skeggs05c71452015-01-14 15:28:47 +1000527 const struct nvkm_enum *en;
Ben Skeggs40476532014-02-22 01:18:46 +1000528 char enunk[6] = "";
529
Ben Skeggs05c71452015-01-14 15:28:47 +1000530 en = nvkm_enum_find(gf100_fifo_sched_reason, code);
Ben Skeggs40476532014-02-22 01:18:46 +1000531 if (!en)
532 snprintf(enunk, sizeof(enunk), "UNK%02x", code);
533
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000534 nv_error(fifo, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk);
Ben Skeggs61fdf622014-02-22 12:44:23 +1000535
536 switch (code) {
537 case 0x0a:
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000538 gf100_fifo_intr_sched_ctxsw(fifo);
Ben Skeggs61fdf622014-02-22 12:44:23 +1000539 break;
540 default:
541 break;
542 }
Ben Skeggs40476532014-02-22 01:18:46 +1000543}
544
Ben Skeggs05c71452015-01-14 15:28:47 +1000545static const struct nvkm_enum
546gf100_fifo_fault_engine[] = {
Marcin Slusarz93260d32012-12-09 23:00:34 +0100547 { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
Ben Skeggs33f8c6d2014-02-22 01:29:26 +1000548 { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB },
549 { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
550 { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
Marcin Slusarz93260d32012-12-09 23:00:34 +0100551 { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
Ben Skeggseccf7e8a2015-01-14 10:09:24 +1000552 { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
Ben Skeggsfd8666f2015-01-14 12:26:28 +1000553 { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
Ben Skeggs7a313472011-03-29 00:52:59 +1000554 { 0x13, "PCOUNTER" },
Ben Skeggs37a5d022015-01-14 12:50:04 +1000555 { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC },
Ben Skeggsaedf24f2015-01-14 11:50:20 +1000556 { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
557 { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 },
Ben Skeggs7a313472011-03-29 00:52:59 +1000558 { 0x17, "PDAEMON" },
Ben Skeggsb2b09932010-11-24 10:47:15 +1000559 {}
560};
561
Ben Skeggs05c71452015-01-14 15:28:47 +1000562static const struct nvkm_enum
563gf100_fifo_fault_reason[] = {
Ben Skeggse2966632011-03-29 08:57:34 +1000564 { 0x00, "PT_NOT_PRESENT" },
565 { 0x01, "PT_TOO_SHORT" },
566 { 0x02, "PAGE_NOT_PRESENT" },
567 { 0x03, "VM_LIMIT_EXCEEDED" },
568 { 0x04, "NO_CHANNEL" },
569 { 0x05, "PAGE_SYSTEM_ONLY" },
570 { 0x06, "PAGE_READ_ONLY" },
571 { 0x0a, "COMPRESSED_SYSRAM" },
572 { 0x0c, "INVALID_STORAGE_TYPE" },
Ben Skeggsb2b09932010-11-24 10:47:15 +1000573 {}
574};
575
Ben Skeggs05c71452015-01-14 15:28:47 +1000576static const struct nvkm_enum
577gf100_fifo_fault_hubclient[] = {
Ben Skeggs7795bee2011-03-29 09:28:24 +1000578 { 0x01, "PCOPY0" },
579 { 0x02, "PCOPY1" },
580 { 0x04, "DISPATCH" },
581 { 0x05, "CTXCTL" },
582 { 0x06, "PFIFO" },
583 { 0x07, "BAR_READ" },
584 { 0x08, "BAR_WRITE" },
585 { 0x0b, "PVP" },
Ben Skeggsfd8666f2015-01-14 12:26:28 +1000586 { 0x0c, "PMSPPP" },
Ben Skeggseccf7e8a2015-01-14 10:09:24 +1000587 { 0x0d, "PMSVLD" },
Ben Skeggs7795bee2011-03-29 09:28:24 +1000588 { 0x11, "PCOUNTER" },
589 { 0x12, "PDAEMON" },
590 { 0x14, "CCACHE" },
591 { 0x15, "CCACHE_POST" },
592 {}
593};
594
Ben Skeggs05c71452015-01-14 15:28:47 +1000595static const struct nvkm_enum
596gf100_fifo_fault_gpcclient[] = {
Ben Skeggs7795bee2011-03-29 09:28:24 +1000597 { 0x01, "TEX" },
598 { 0x0c, "ESETUP" },
599 { 0x0e, "CTXCTL" },
600 { 0x0f, "PROP" },
601 {}
602};
603
Ben Skeggsb2b09932010-11-24 10:47:15 +1000604static void
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000605gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit)
Ben Skeggsb2b09932010-11-24 10:47:15 +1000606{
Ben Skeggs87744402015-08-20 14:54:10 +1000607 struct nvkm_device *device = fifo->base.engine.subdev.device;
608 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
609 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
610 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
611 u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10));
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000612 u32 gpc = (stat & 0x1f000000) >> 24;
Ben Skeggs7795bee2011-03-29 09:28:24 +1000613 u32 client = (stat & 0x00001f00) >> 8;
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000614 u32 write = (stat & 0x00000080);
615 u32 hub = (stat & 0x00000040);
616 u32 reason = (stat & 0x0000000f);
Ben Skeggs05c71452015-01-14 15:28:47 +1000617 struct nvkm_object *engctx = NULL, *object;
618 struct nvkm_engine *engine = NULL;
619 const struct nvkm_enum *er, *eu, *ec;
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000620 char erunk[6] = "";
621 char euunk[6] = "";
622 char ecunk[6] = "";
623 char gpcid[3] = "";
Ben Skeggsb2b09932010-11-24 10:47:15 +1000624
Ben Skeggs05c71452015-01-14 15:28:47 +1000625 er = nvkm_enum_find(gf100_fifo_fault_reason, reason);
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000626 if (!er)
627 snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
628
Ben Skeggs05c71452015-01-14 15:28:47 +1000629 eu = nvkm_enum_find(gf100_fifo_fault_engine, unit);
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000630 if (eu) {
Ben Skeggs33f8c6d2014-02-22 01:29:26 +1000631 switch (eu->data2) {
632 case NVDEV_SUBDEV_BAR:
Ben Skeggs87744402015-08-20 14:54:10 +1000633 nvkm_mask(device, 0x001704, 0x00000000, 0x00000000);
Ben Skeggs33f8c6d2014-02-22 01:29:26 +1000634 break;
635 case NVDEV_SUBDEV_INSTMEM:
Ben Skeggs87744402015-08-20 14:54:10 +1000636 nvkm_mask(device, 0x001714, 0x00000000, 0x00000000);
Ben Skeggs33f8c6d2014-02-22 01:29:26 +1000637 break;
638 case NVDEV_ENGINE_IFB:
Ben Skeggs87744402015-08-20 14:54:10 +1000639 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
Ben Skeggs33f8c6d2014-02-22 01:29:26 +1000640 break;
641 default:
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000642 engine = nvkm_engine(fifo, eu->data2);
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000643 if (engine)
Ben Skeggs05c71452015-01-14 15:28:47 +1000644 engctx = nvkm_engctx_get(engine, inst);
Ben Skeggs33f8c6d2014-02-22 01:29:26 +1000645 break;
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000646 }
Ben Skeggs7795bee2011-03-29 09:28:24 +1000647 } else {
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000648 snprintf(euunk, sizeof(euunk), "UNK%02x", unit);
Ben Skeggs7795bee2011-03-29 09:28:24 +1000649 }
Marcin Slusarz93260d32012-12-09 23:00:34 +0100650
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000651 if (hub) {
Ben Skeggs05c71452015-01-14 15:28:47 +1000652 ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client);
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000653 } else {
Ben Skeggs05c71452015-01-14 15:28:47 +1000654 ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client);
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000655 snprintf(gpcid, sizeof(gpcid), "%d", gpc);
Marcin Slusarz93260d32012-12-09 23:00:34 +0100656 }
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000657
658 if (!ec)
659 snprintf(ecunk, sizeof(ecunk), "UNK%02x", client);
660
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000661 nv_error(fifo, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on "
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000662 "channel 0x%010llx [%s]\n", write ? "write" : "read",
663 (u64)vahi << 32 | valo, er ? er->name : erunk,
664 eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
665 ec ? ec->name : ecunk, (u64)inst << 12,
Ben Skeggs05c71452015-01-14 15:28:47 +1000666 nvkm_client_name(engctx));
Marcin Slusarz93260d32012-12-09 23:00:34 +0100667
Ben Skeggs24e83412014-02-05 11:18:38 +1000668 object = engctx;
669 while (object) {
670 switch (nv_mclass(object)) {
Ben Skeggsbbf89062014-08-10 04:10:25 +1000671 case FERMI_CHANNEL_GPFIFO:
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000672 gf100_fifo_recover(fifo, engine, (void *)object);
Ben Skeggs24e83412014-02-05 11:18:38 +1000673 break;
674 }
675 object = object->parent;
676 }
677
Ben Skeggs05c71452015-01-14 15:28:47 +1000678 nvkm_engctx_put(engctx);
Ben Skeggsb2b09932010-11-24 10:47:15 +1000679}
680
Ben Skeggs05c71452015-01-14 15:28:47 +1000681static const struct nvkm_bitfield
682gf100_fifo_pbdma_intr[] = {
Ben Skeggs083c2142014-02-22 00:31:29 +1000683/* { 0x00008000, "" } seen with null ib push */
684 { 0x00200000, "ILLEGAL_MTHD" },
685 { 0x00800000, "EMPTY_SUBC" },
686 {}
687};
Ben Skeggsd5316e22012-03-21 13:53:49 +1000688
Ben Skeggsb2b09932010-11-24 10:47:15 +1000689static void
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000690gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit)
Ben Skeggsb2b09932010-11-24 10:47:15 +1000691{
Ben Skeggs87744402015-08-20 14:54:10 +1000692 struct nvkm_device *device = fifo->base.engine.subdev.device;
693 u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000));
694 u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000));
695 u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000));
696 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000697 u32 subc = (addr & 0x00070000) >> 16;
Ben Skeggsb2b09932010-11-24 10:47:15 +1000698 u32 mthd = (addr & 0x00003ffc);
Ben Skeggsd5316e22012-03-21 13:53:49 +1000699 u32 show = stat;
Ben Skeggsb2b09932010-11-24 10:47:15 +1000700
Ben Skeggsebb945a2012-07-20 08:17:34 +1000701 if (stat & 0x00800000) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000702 if (!gf100_fifo_swmthd(fifo, chid, mthd, data))
Ben Skeggsebb945a2012-07-20 08:17:34 +1000703 show &= ~0x00800000;
Ben Skeggsd5316e22012-03-21 13:53:49 +1000704 }
Ben Skeggsb2b09932010-11-24 10:47:15 +1000705
Ben Skeggsebb945a2012-07-20 08:17:34 +1000706 if (show) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000707 nv_error(fifo, "PBDMA%d:", unit);
Ben Skeggs05c71452015-01-14 15:28:47 +1000708 nvkm_bitfield_print(gf100_fifo_pbdma_intr, show);
Marcin Slusarzf533da12012-12-09 15:45:20 +0100709 pr_cont("\n");
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000710 nv_error(fifo,
Ben Skeggs03574662014-01-28 11:47:46 +1000711 "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
Marcin Slusarz93260d32012-12-09 23:00:34 +0100712 unit, chid,
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000713 nvkm_client_name_for_fifo_chid(&fifo->base, chid),
Marcin Slusarz93260d32012-12-09 23:00:34 +0100714 subc, mthd, data);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000715 }
716
Ben Skeggs87744402015-08-20 14:54:10 +1000717 nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
718 nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);
Ben Skeggsb2b09932010-11-24 10:47:15 +1000719}
720
721static void
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000722gf100_fifo_intr_runlist(struct gf100_fifo *fifo)
Ben Skeggsa07d0e72014-02-22 00:28:47 +1000723{
Ben Skeggs87744402015-08-20 14:54:10 +1000724 struct nvkm_device *device = fifo->base.engine.subdev.device;
725 u32 intr = nvkm_rd32(device, 0x002a00);
Ben Skeggsa07d0e72014-02-22 00:28:47 +1000726
727 if (intr & 0x10000000) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000728 wake_up(&fifo->runlist.wait);
Ben Skeggs87744402015-08-20 14:54:10 +1000729 nvkm_wr32(device, 0x002a00, 0x10000000);
Ben Skeggsa07d0e72014-02-22 00:28:47 +1000730 intr &= ~0x10000000;
731 }
732
733 if (intr) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000734 nv_error(fifo, "RUNLIST 0x%08x\n", intr);
Ben Skeggs87744402015-08-20 14:54:10 +1000735 nvkm_wr32(device, 0x002a00, intr);
Ben Skeggsa07d0e72014-02-22 00:28:47 +1000736 }
737}
738
739static void
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000740gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn)
Ben Skeggse99bf012014-02-22 00:18:17 +1000741{
Ben Skeggs87744402015-08-20 14:54:10 +1000742 struct nvkm_device *device = fifo->base.engine.subdev.device;
743 u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04));
744 u32 inte = nvkm_rd32(device, 0x002628);
Ben Skeggse99bf012014-02-22 00:18:17 +1000745 u32 unkn;
746
Ben Skeggs87744402015-08-20 14:54:10 +1000747 nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr);
Ben Skeggs19a10822014-12-01 11:44:27 +1000748
Ben Skeggse99bf012014-02-22 00:18:17 +1000749 for (unkn = 0; unkn < 8; unkn++) {
750 u32 ints = (intr >> (unkn * 0x04)) & inte;
751 if (ints & 0x1) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000752 nvkm_fifo_uevent(&fifo->base);
Ben Skeggse99bf012014-02-22 00:18:17 +1000753 ints &= ~1;
754 }
755 if (ints) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000756 nv_error(fifo, "ENGINE %d %d %01x", engn, unkn, ints);
Ben Skeggs87744402015-08-20 14:54:10 +1000757 nvkm_mask(device, 0x002628, ints, 0);
Ben Skeggse99bf012014-02-22 00:18:17 +1000758 }
759 }
Ben Skeggse99bf012014-02-22 00:18:17 +1000760}
761
762static void
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000763gf100_fifo_intr_engine(struct gf100_fifo *fifo)
Ben Skeggse99bf012014-02-22 00:18:17 +1000764{
Ben Skeggs87744402015-08-20 14:54:10 +1000765 struct nvkm_device *device = fifo->base.engine.subdev.device;
766 u32 mask = nvkm_rd32(device, 0x0025a4);
Ben Skeggse99bf012014-02-22 00:18:17 +1000767 while (mask) {
768 u32 unit = __ffs(mask);
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000769 gf100_fifo_intr_engine_unit(fifo, unit);
Ben Skeggse99bf012014-02-22 00:18:17 +1000770 mask &= ~(1 << unit);
771 }
772}
773
774static void
Ben Skeggs05c71452015-01-14 15:28:47 +1000775gf100_fifo_intr(struct nvkm_subdev *subdev)
Ben Skeggsb2b09932010-11-24 10:47:15 +1000776{
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000777 struct gf100_fifo *fifo = (void *)subdev;
Ben Skeggs87744402015-08-20 14:54:10 +1000778 struct nvkm_device *device = fifo->base.engine.subdev.device;
779 u32 mask = nvkm_rd32(device, 0x002140);
780 u32 stat = nvkm_rd32(device, 0x002100) & mask;
Ben Skeggsb2b09932010-11-24 10:47:15 +1000781
Ben Skeggs32256c82013-01-31 19:49:33 -0500782 if (stat & 0x00000001) {
Ben Skeggs87744402015-08-20 14:54:10 +1000783 u32 intr = nvkm_rd32(device, 0x00252c);
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000784 nv_warn(fifo, "INTR 0x00000001: 0x%08x\n", intr);
Ben Skeggs87744402015-08-20 14:54:10 +1000785 nvkm_wr32(device, 0x002100, 0x00000001);
Ben Skeggs32256c82013-01-31 19:49:33 -0500786 stat &= ~0x00000001;
787 }
788
Ben Skeggscc8cd642011-01-28 13:42:16 +1000789 if (stat & 0x00000100) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000790 gf100_fifo_intr_sched(fifo);
Ben Skeggs87744402015-08-20 14:54:10 +1000791 nvkm_wr32(device, 0x002100, 0x00000100);
Ben Skeggscc8cd642011-01-28 13:42:16 +1000792 stat &= ~0x00000100;
793 }
794
Ben Skeggs32256c82013-01-31 19:49:33 -0500795 if (stat & 0x00010000) {
Ben Skeggs87744402015-08-20 14:54:10 +1000796 u32 intr = nvkm_rd32(device, 0x00256c);
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000797 nv_warn(fifo, "INTR 0x00010000: 0x%08x\n", intr);
Ben Skeggs87744402015-08-20 14:54:10 +1000798 nvkm_wr32(device, 0x002100, 0x00010000);
Ben Skeggs32256c82013-01-31 19:49:33 -0500799 stat &= ~0x00010000;
800 }
801
802 if (stat & 0x01000000) {
Ben Skeggs87744402015-08-20 14:54:10 +1000803 u32 intr = nvkm_rd32(device, 0x00258c);
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000804 nv_warn(fifo, "INTR 0x01000000: 0x%08x\n", intr);
Ben Skeggs87744402015-08-20 14:54:10 +1000805 nvkm_wr32(device, 0x002100, 0x01000000);
Ben Skeggs32256c82013-01-31 19:49:33 -0500806 stat &= ~0x01000000;
807 }
808
Ben Skeggsb2b09932010-11-24 10:47:15 +1000809 if (stat & 0x10000000) {
Ben Skeggs87744402015-08-20 14:54:10 +1000810 u32 mask = nvkm_rd32(device, 0x00259c);
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000811 while (mask) {
812 u32 unit = __ffs(mask);
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000813 gf100_fifo_intr_fault(fifo, unit);
Ben Skeggs87744402015-08-20 14:54:10 +1000814 nvkm_wr32(device, 0x00259c, (1 << unit));
Ben Skeggsd439a5a2014-02-22 00:39:36 +1000815 mask &= ~(1 << unit);
Ben Skeggsb2b09932010-11-24 10:47:15 +1000816 }
Ben Skeggsb2b09932010-11-24 10:47:15 +1000817 stat &= ~0x10000000;
818 }
819
820 if (stat & 0x20000000) {
Ben Skeggs87744402015-08-20 14:54:10 +1000821 u32 mask = nvkm_rd32(device, 0x0025a0);
Ben Skeggs083c2142014-02-22 00:31:29 +1000822 while (mask) {
823 u32 unit = __ffs(mask);
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000824 gf100_fifo_intr_pbdma(fifo, unit);
Ben Skeggs87744402015-08-20 14:54:10 +1000825 nvkm_wr32(device, 0x0025a0, (1 << unit));
Ben Skeggs083c2142014-02-22 00:31:29 +1000826 mask &= ~(1 << unit);
Ben Skeggsb2b09932010-11-24 10:47:15 +1000827 }
Ben Skeggsb2b09932010-11-24 10:47:15 +1000828 stat &= ~0x20000000;
829 }
830
Ben Skeggscc8cd642011-01-28 13:42:16 +1000831 if (stat & 0x40000000) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000832 gf100_fifo_intr_runlist(fifo);
Ben Skeggscc8cd642011-01-28 13:42:16 +1000833 stat &= ~0x40000000;
834 }
835
Ben Skeggs32256c82013-01-31 19:49:33 -0500836 if (stat & 0x80000000) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000837 gf100_fifo_intr_engine(fifo);
Ben Skeggs32256c82013-01-31 19:49:33 -0500838 stat &= ~0x80000000;
839 }
840
Ben Skeggsb2b09932010-11-24 10:47:15 +1000841 if (stat) {
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000842 nv_error(fifo, "INTR 0x%08x\n", stat);
Ben Skeggs87744402015-08-20 14:54:10 +1000843 nvkm_mask(device, 0x002140, stat, 0x00000000);
844 nvkm_wr32(device, 0x002100, stat);
Ben Skeggsb2b09932010-11-24 10:47:15 +1000845 }
Ben Skeggsb2b09932010-11-24 10:47:15 +1000846}
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000847
Ben Skeggs9bd2ddb2013-01-31 13:51:20 +1000848static void
Ben Skeggs05c71452015-01-14 15:28:47 +1000849gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index)
Ben Skeggs9bd2ddb2013-01-31 13:51:20 +1000850{
Ben Skeggs05c71452015-01-14 15:28:47 +1000851 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
Ben Skeggs87744402015-08-20 14:54:10 +1000852 struct nvkm_device *device = fifo->engine.subdev.device;
853 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
Ben Skeggs9bd2ddb2013-01-31 13:51:20 +1000854}
855
856static void
Ben Skeggs05c71452015-01-14 15:28:47 +1000857gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
Ben Skeggs9bd2ddb2013-01-31 13:51:20 +1000858{
Ben Skeggs05c71452015-01-14 15:28:47 +1000859 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
Ben Skeggs87744402015-08-20 14:54:10 +1000860 struct nvkm_device *device = fifo->engine.subdev.device;
861 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
Ben Skeggs9bd2ddb2013-01-31 13:51:20 +1000862}
863
Ben Skeggs79ca2772014-08-10 04:10:20 +1000864static const struct nvkm_event_func
Ben Skeggs05c71452015-01-14 15:28:47 +1000865gf100_fifo_uevent_func = {
866 .ctor = nvkm_fifo_uevent_ctor,
867 .init = gf100_fifo_uevent_init,
868 .fini = gf100_fifo_uevent_fini,
Ben Skeggs79ca2772014-08-10 04:10:20 +1000869};
870
871static int
Ben Skeggs05c71452015-01-14 15:28:47 +1000872gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
873 struct nvkm_oclass *oclass, void *data, u32 size,
874 struct nvkm_object **pobject)
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000875{
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000876 struct gf100_fifo *fifo;
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000877 int ret;
878
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000879 ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo);
880 *pobject = nv_object(fifo);
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000881 if (ret)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000882 return ret;
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000883
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000884 INIT_WORK(&fifo->fault, gf100_fifo_recover_work);
Ben Skeggs24e83412014-02-05 11:18:38 +1000885
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000886 ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0,
887 &fifo->runlist.mem[0]);
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000888 if (ret)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000889 return ret;
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000890
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000891 ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0,
892 &fifo->runlist.mem[1]);
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000893 if (ret)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000894 return ret;
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000895
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000896 init_waitqueue_head(&fifo->runlist.wait);
Ben Skeggsa07d0e72014-02-22 00:28:47 +1000897
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000898 ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 0x1000, 0x1000, 0,
899 &fifo->user.mem);
Ben Skeggs9da226f2012-07-13 16:54:45 +1000900 if (ret)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000901 return ret;
Ben Skeggs9da226f2012-07-13 16:54:45 +1000902
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000903 ret = nvkm_gpuobj_map(fifo->user.mem, NV_MEM_ACCESS_RW,
904 &fifo->user.bar);
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000905 if (ret)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000906 return ret;
907
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000908 ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent);
Ben Skeggs79ca2772014-08-10 04:10:20 +1000909 if (ret)
910 return ret;
Ben Skeggs9bd2ddb2013-01-31 13:51:20 +1000911
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000912 nv_subdev(fifo)->unit = 0x00000100;
913 nv_subdev(fifo)->intr = gf100_fifo_intr;
914 nv_engine(fifo)->cclass = &gf100_fifo_cclass;
915 nv_engine(fifo)->sclass = gf100_fifo_sclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000916 return 0;
Ben Skeggsc420b2d2012-05-01 20:48:08 +1000917}
Ben Skeggsebb945a2012-07-20 08:17:34 +1000918
919static void
Ben Skeggs05c71452015-01-14 15:28:47 +1000920gf100_fifo_dtor(struct nvkm_object *object)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000921{
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000922 struct gf100_fifo *fifo = (void *)object;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000923
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000924 nvkm_gpuobj_unmap(&fifo->user.bar);
925 nvkm_gpuobj_ref(NULL, &fifo->user.mem);
926 nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[0]);
927 nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[1]);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000928
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000929 nvkm_fifo_destroy(&fifo->base);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000930}
931
932static int
Ben Skeggs05c71452015-01-14 15:28:47 +1000933gf100_fifo_init(struct nvkm_object *object)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000934{
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000935 struct gf100_fifo *fifo = (void *)object;
Ben Skeggs87744402015-08-20 14:54:10 +1000936 struct nvkm_device *device = fifo->base.engine.subdev.device;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000937 int ret, i;
938
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000939 ret = nvkm_fifo_init(&fifo->base);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000940 if (ret)
941 return ret;
942
Ben Skeggs87744402015-08-20 14:54:10 +1000943 nvkm_wr32(device, 0x000204, 0xffffffff);
944 nvkm_wr32(device, 0x002204, 0xffffffff);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000945
Ben Skeggs87744402015-08-20 14:54:10 +1000946 fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204));
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000947 nv_debug(fifo, "%d PBDMA unit(s)\n", fifo->spoon_nr);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000948
Ben Skeggs03574662014-01-28 11:47:46 +1000949 /* assign engines to PBDMAs */
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000950 if (fifo->spoon_nr >= 3) {
Ben Skeggs87744402015-08-20 14:54:10 +1000951 nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */
952 nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */
953 nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */
954 nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */
955 nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */
956 nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */
Ben Skeggsebb945a2012-07-20 08:17:34 +1000957 }
958
Ben Skeggs03574662014-01-28 11:47:46 +1000959 /* PBDMA[n] */
Ben Skeggs6189f1b2015-08-20 14:54:07 +1000960 for (i = 0; i < fifo->spoon_nr; i++) {
Ben Skeggs87744402015-08-20 14:54:10 +1000961 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
962 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
963 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
Ben Skeggsebb945a2012-07-20 08:17:34 +1000964 }
965
Ben Skeggs87744402015-08-20 14:54:10 +1000966 nvkm_mask(device, 0x002200, 0x00000001, 0x00000001);
967 nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000968
Ben Skeggs87744402015-08-20 14:54:10 +1000969 nvkm_wr32(device, 0x002100, 0xffffffff);
970 nvkm_wr32(device, 0x002140, 0x7fffffff);
971 nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
Ben Skeggsebb945a2012-07-20 08:17:34 +1000972 return 0;
973}
974
Ben Skeggs05c71452015-01-14 15:28:47 +1000975struct nvkm_oclass *
976gf100_fifo_oclass = &(struct nvkm_oclass) {
Ben Skeggsebb945a2012-07-20 08:17:34 +1000977 .handle = NV_ENGINE(FIFO, 0xc0),
Ben Skeggs05c71452015-01-14 15:28:47 +1000978 .ofuncs = &(struct nvkm_ofuncs) {
979 .ctor = gf100_fifo_ctor,
980 .dtor = gf100_fifo_dtor,
981 .init = gf100_fifo_init,
982 .fini = _nvkm_fifo_fini,
Ben Skeggsebb945a2012-07-20 08:17:34 +1000983 },
984};