Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 1 | /* |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 2 | * Copyright 2012 Red Hat Inc. |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 24 | #include <engine/fifo.h> |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 25 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 26 | #include <core/client.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 27 | #include <core/engctx.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 28 | #include <core/enum.h> |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 29 | #include <core/handle.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 30 | #include <subdev/bar.h> |
Ben Skeggs | 5222555 | 2013-12-23 01:51:16 +1000 | [diff] [blame] | 31 | #include <subdev/fb.h> |
Ben Skeggs | 5ce3bf3 | 2015-01-14 09:57:36 +1000 | [diff] [blame] | 32 | #include <subdev/mmu.h> |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 33 | #include <subdev/timer.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 34 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 35 | #include <nvif/class.h> |
| 36 | #include <nvif/unpack.h> |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 37 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 38 | struct gf100_fifo { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 39 | struct nvkm_fifo base; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 40 | |
| 41 | struct work_struct fault; |
| 42 | u64 mask; |
| 43 | |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 44 | struct { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 45 | struct nvkm_gpuobj *mem[2]; |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 46 | int active; |
| 47 | wait_queue_head_t wait; |
| 48 | } runlist; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 49 | |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 50 | struct { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 51 | struct nvkm_gpuobj *mem; |
| 52 | struct nvkm_vma bar; |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 53 | } user; |
Ben Skeggs | ec9c088 | 2010-12-31 12:10:49 +1000 | [diff] [blame] | 54 | int spoon_nr; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 55 | }; |
| 56 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 57 | struct gf100_fifo_base { |
| 58 | struct nvkm_fifo_base base; |
| 59 | struct nvkm_gpuobj *pgd; |
| 60 | struct nvkm_vm *vm; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 61 | }; |
| 62 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 63 | struct gf100_fifo_chan { |
| 64 | struct nvkm_fifo_chan base; |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 65 | enum { |
| 66 | STOPPED, |
| 67 | RUNNING, |
| 68 | KILLED |
| 69 | } state; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 70 | }; |
| 71 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 72 | /******************************************************************************* |
| 73 | * FIFO channel objects |
| 74 | ******************************************************************************/ |
| 75 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 76 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 77 | gf100_fifo_runlist_update(struct gf100_fifo *fifo) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 78 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 79 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 80 | struct nvkm_bar *bar = device->bar; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 81 | struct nvkm_gpuobj *cur; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 82 | int i, p; |
| 83 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 84 | mutex_lock(&nv_subdev(fifo)->mutex); |
| 85 | cur = fifo->runlist.mem[fifo->runlist.active]; |
| 86 | fifo->runlist.active = !fifo->runlist.active; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 87 | |
| 88 | for (i = 0, p = 0; i < 128; i++) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 89 | struct gf100_fifo_chan *chan = (void *)fifo->base.channel[i]; |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 90 | if (chan && chan->state == RUNNING) { |
| 91 | nv_wo32(cur, p + 0, i); |
| 92 | nv_wo32(cur, p + 4, 0x00000004); |
| 93 | p += 8; |
| 94 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 95 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 96 | bar->flush(bar); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 97 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 98 | nvkm_wr32(device, 0x002270, cur->addr >> 12); |
| 99 | nvkm_wr32(device, 0x002274, 0x01f00000 | (p >> 3)); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 100 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 101 | if (wait_event_timeout(fifo->runlist.wait, |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 102 | !(nvkm_rd32(device, 0x00227c) & 0x00100000), |
Ben Skeggs | 3cf6290 | 2014-02-22 01:05:01 +1000 | [diff] [blame] | 103 | msecs_to_jiffies(2000)) == 0) |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 104 | nv_error(fifo, "runlist update timeout\n"); |
| 105 | mutex_unlock(&nv_subdev(fifo)->mutex); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 106 | } |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 107 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 108 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 109 | gf100_fifo_context_attach(struct nvkm_object *parent, |
| 110 | struct nvkm_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 111 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 112 | struct nvkm_bar *bar = nvkm_bar(parent); |
| 113 | struct gf100_fifo_base *base = (void *)parent->parent; |
| 114 | struct nvkm_engctx *ectx = (void *)object; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 115 | u32 addr; |
| 116 | int ret; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 117 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 118 | switch (nv_engidx(object->engine)) { |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 119 | case NVDEV_ENGINE_SW : return 0; |
| 120 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 121 | case NVDEV_ENGINE_CE0 : addr = 0x0230; break; |
| 122 | case NVDEV_ENGINE_CE1 : addr = 0x0240; break; |
| 123 | case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; |
| 124 | case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; |
| 125 | case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 126 | default: |
| 127 | return -EINVAL; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 128 | } |
| 129 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 130 | if (!ectx->vma.node) { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 131 | ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, |
| 132 | NV_MEM_ACCESS_RW, &ectx->vma); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 133 | if (ret) |
| 134 | return ret; |
Ben Skeggs | 4c2d422 | 2012-08-10 15:10:34 +1000 | [diff] [blame] | 135 | |
| 136 | nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 137 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 138 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 139 | nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); |
| 140 | nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); |
| 141 | bar->flush(bar); |
| 142 | return 0; |
| 143 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 144 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 145 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 146 | gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, |
| 147 | struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 148 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 149 | struct gf100_fifo *fifo = (void *)parent->engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 150 | struct gf100_fifo_base *base = (void *)parent->parent; |
| 151 | struct gf100_fifo_chan *chan = (void *)parent; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 152 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 153 | struct nvkm_bar *bar = device->bar; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 154 | u32 addr; |
| 155 | |
| 156 | switch (nv_engidx(object->engine)) { |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 157 | case NVDEV_ENGINE_SW : return 0; |
| 158 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 159 | case NVDEV_ENGINE_CE0 : addr = 0x0230; break; |
| 160 | case NVDEV_ENGINE_CE1 : addr = 0x0240; break; |
| 161 | case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; |
| 162 | case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; |
| 163 | case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 164 | default: |
| 165 | return -EINVAL; |
| 166 | } |
| 167 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 168 | nvkm_wr32(device, 0x002634, chan->base.chid); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 169 | if (!nv_wait(fifo, 0x002634, 0xffffffff, chan->base.chid)) { |
| 170 | nv_error(fifo, "channel %d [%s] kick timeout\n", |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 171 | chan->base.chid, nvkm_client_name(chan)); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 172 | if (suspend) |
| 173 | return -EBUSY; |
| 174 | } |
| 175 | |
Ben Skeggs | edc260d | 2012-11-27 11:05:36 +1000 | [diff] [blame] | 176 | nv_wo32(base, addr + 0x00, 0x00000000); |
| 177 | nv_wo32(base, addr + 0x04, 0x00000000); |
| 178 | bar->flush(bar); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 179 | return 0; |
| 180 | } |
| 181 | |
| 182 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 183 | gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
| 184 | struct nvkm_oclass *oclass, void *data, u32 size, |
| 185 | struct nvkm_object **pobject) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 186 | { |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 187 | union { |
| 188 | struct nv50_channel_gpfifo_v0 v0; |
| 189 | } *args = data; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 190 | struct nvkm_bar *bar = nvkm_bar(parent); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 191 | struct gf100_fifo *fifo = (void *)engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 192 | struct gf100_fifo_base *base = (void *)parent; |
| 193 | struct gf100_fifo_chan *chan; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 194 | u64 usermem, ioffset, ilength; |
| 195 | int ret, i; |
| 196 | |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 197 | nv_ioctl(parent, "create channel gpfifo size %d\n", size); |
| 198 | if (nvif_unpack(args->v0, 0, 0, false)) { |
| 199 | nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x " |
| 200 | "ioffset %016llx ilength %08x\n", |
| 201 | args->v0.version, args->v0.pushbuf, args->v0.ioffset, |
| 202 | args->v0.ilength); |
| 203 | } else |
| 204 | return ret; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 205 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 206 | ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 207 | fifo->user.bar.offset, 0x1000, |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 208 | args->v0.pushbuf, |
| 209 | (1ULL << NVDEV_ENGINE_SW) | |
| 210 | (1ULL << NVDEV_ENGINE_GR) | |
| 211 | (1ULL << NVDEV_ENGINE_CE0) | |
| 212 | (1ULL << NVDEV_ENGINE_CE1) | |
| 213 | (1ULL << NVDEV_ENGINE_MSVLD) | |
| 214 | (1ULL << NVDEV_ENGINE_MSPDEC) | |
| 215 | (1ULL << NVDEV_ENGINE_MSPPP), &chan); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 216 | *pobject = nv_object(chan); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 217 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 218 | return ret; |
| 219 | |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 220 | args->v0.chid = chan->base.chid; |
| 221 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 222 | nv_parent(chan)->context_attach = gf100_fifo_context_attach; |
| 223 | nv_parent(chan)->context_detach = gf100_fifo_context_detach; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 224 | |
| 225 | usermem = chan->base.chid * 0x1000; |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 226 | ioffset = args->v0.ioffset; |
| 227 | ilength = order_base_2(args->v0.ilength / 8); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 228 | |
| 229 | for (i = 0; i < 0x1000; i += 4) |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 230 | nv_wo32(fifo->user.mem, usermem + i, 0x00000000); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 231 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 232 | nv_wo32(base, 0x08, lower_32_bits(fifo->user.mem->addr + usermem)); |
| 233 | nv_wo32(base, 0x0c, upper_32_bits(fifo->user.mem->addr + usermem)); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 234 | nv_wo32(base, 0x10, 0x0000face); |
| 235 | nv_wo32(base, 0x30, 0xfffff902); |
| 236 | nv_wo32(base, 0x48, lower_32_bits(ioffset)); |
| 237 | nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); |
| 238 | nv_wo32(base, 0x54, 0x00000002); |
| 239 | nv_wo32(base, 0x84, 0x20400000); |
| 240 | nv_wo32(base, 0x94, 0x30000001); |
| 241 | nv_wo32(base, 0x9c, 0x00000100); |
| 242 | nv_wo32(base, 0xa4, 0x1f1f1f1f); |
| 243 | nv_wo32(base, 0xa8, 0x1f1f1f1f); |
| 244 | nv_wo32(base, 0xac, 0x0000001f); |
| 245 | nv_wo32(base, 0xb8, 0xf8000000); |
| 246 | nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */ |
| 247 | nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */ |
| 248 | bar->flush(bar); |
| 249 | return 0; |
| 250 | } |
| 251 | |
| 252 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 253 | gf100_fifo_chan_init(struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 254 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 255 | struct nvkm_gpuobj *base = nv_gpuobj(object->parent); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 256 | struct gf100_fifo *fifo = (void *)object->engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 257 | struct gf100_fifo_chan *chan = (void *)object; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 258 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 259 | u32 chid = chan->base.chid; |
| 260 | int ret; |
| 261 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 262 | ret = nvkm_fifo_channel_init(&chan->base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 263 | if (ret) |
| 264 | return ret; |
| 265 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 266 | nvkm_wr32(device, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 267 | |
| 268 | if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 269 | nvkm_wr32(device, 0x003004 + (chid * 8), 0x001f0001); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 270 | gf100_fifo_runlist_update(fifo); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 271 | } |
| 272 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 273 | return 0; |
| 274 | } |
| 275 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 276 | static void gf100_fifo_intr_engine(struct gf100_fifo *fifo); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 277 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 278 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 279 | gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 280 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 281 | struct gf100_fifo *fifo = (void *)object->engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 282 | struct gf100_fifo_chan *chan = (void *)object; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 283 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 284 | u32 chid = chan->base.chid; |
| 285 | |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 286 | if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 287 | nvkm_mask(device, 0x003004 + (chid * 8), 0x00000001, 0x00000000); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 288 | gf100_fifo_runlist_update(fifo); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 289 | } |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 290 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 291 | gf100_fifo_intr_engine(fifo); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 292 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 293 | nvkm_wr32(device, 0x003000 + (chid * 8), 0x00000000); |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 294 | return nvkm_fifo_channel_fini(&chan->base, suspend); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 295 | } |
| 296 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 297 | static struct nvkm_ofuncs |
| 298 | gf100_fifo_ofuncs = { |
| 299 | .ctor = gf100_fifo_chan_ctor, |
| 300 | .dtor = _nvkm_fifo_channel_dtor, |
| 301 | .init = gf100_fifo_chan_init, |
| 302 | .fini = gf100_fifo_chan_fini, |
| 303 | .map = _nvkm_fifo_channel_map, |
| 304 | .rd32 = _nvkm_fifo_channel_rd32, |
| 305 | .wr32 = _nvkm_fifo_channel_wr32, |
| 306 | .ntfy = _nvkm_fifo_channel_ntfy |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 307 | }; |
| 308 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 309 | static struct nvkm_oclass |
| 310 | gf100_fifo_sclass[] = { |
| 311 | { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs }, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 312 | {} |
| 313 | }; |
| 314 | |
| 315 | /******************************************************************************* |
| 316 | * FIFO context - instmem heap and vm setup |
| 317 | ******************************************************************************/ |
| 318 | |
| 319 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 320 | gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
| 321 | struct nvkm_oclass *oclass, void *data, u32 size, |
| 322 | struct nvkm_object **pobject) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 323 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 324 | struct gf100_fifo_base *base; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 325 | int ret; |
| 326 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 327 | ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, |
| 328 | 0x1000, NVOBJ_FLAG_ZERO_ALLOC | |
| 329 | NVOBJ_FLAG_HEAP, &base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 330 | *pobject = nv_object(base); |
| 331 | if (ret) |
| 332 | return ret; |
| 333 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 334 | ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, |
| 335 | &base->pgd); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 336 | if (ret) |
| 337 | return ret; |
| 338 | |
| 339 | nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr)); |
| 340 | nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr)); |
| 341 | nv_wo32(base, 0x0208, 0xffffffff); |
| 342 | nv_wo32(base, 0x020c, 0x000000ff); |
| 343 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 344 | ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 345 | if (ret) |
| 346 | return ret; |
| 347 | |
| 348 | return 0; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 349 | } |
| 350 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 351 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 352 | gf100_fifo_context_dtor(struct nvkm_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 353 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 354 | struct gf100_fifo_base *base = (void *)object; |
| 355 | nvkm_vm_ref(NULL, &base->vm, base->pgd); |
| 356 | nvkm_gpuobj_ref(NULL, &base->pgd); |
| 357 | nvkm_fifo_context_destroy(&base->base); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 358 | } |
| 359 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 360 | static struct nvkm_oclass |
| 361 | gf100_fifo_cclass = { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 362 | .handle = NV_ENGCTX(FIFO, 0xc0), |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 363 | .ofuncs = &(struct nvkm_ofuncs) { |
| 364 | .ctor = gf100_fifo_context_ctor, |
| 365 | .dtor = gf100_fifo_context_dtor, |
| 366 | .init = _nvkm_fifo_context_init, |
| 367 | .fini = _nvkm_fifo_context_fini, |
| 368 | .rd32 = _nvkm_fifo_context_rd32, |
| 369 | .wr32 = _nvkm_fifo_context_wr32, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 370 | }, |
| 371 | }; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 372 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 373 | /******************************************************************************* |
| 374 | * PFIFO engine |
| 375 | ******************************************************************************/ |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 376 | |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 377 | static inline int |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 378 | gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 379 | { |
| 380 | switch (engn) { |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 381 | case NVDEV_ENGINE_GR : engn = 0; break; |
| 382 | case NVDEV_ENGINE_MSVLD : engn = 1; break; |
| 383 | case NVDEV_ENGINE_MSPPP : engn = 2; break; |
| 384 | case NVDEV_ENGINE_MSPDEC: engn = 3; break; |
| 385 | case NVDEV_ENGINE_CE0 : engn = 4; break; |
| 386 | case NVDEV_ENGINE_CE1 : engn = 5; break; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 387 | default: |
| 388 | return -1; |
| 389 | } |
| 390 | |
| 391 | return engn; |
| 392 | } |
| 393 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 394 | static inline struct nvkm_engine * |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 395 | gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 396 | { |
| 397 | switch (engn) { |
| 398 | case 0: engn = NVDEV_ENGINE_GR; break; |
Ben Skeggs | eccf7e8a | 2015-01-14 10:09:24 +1000 | [diff] [blame] | 399 | case 1: engn = NVDEV_ENGINE_MSVLD; break; |
Ben Skeggs | fd8666f | 2015-01-14 12:26:28 +1000 | [diff] [blame] | 400 | case 2: engn = NVDEV_ENGINE_MSPPP; break; |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 401 | case 3: engn = NVDEV_ENGINE_MSPDEC; break; |
Ben Skeggs | aedf24f | 2015-01-14 11:50:20 +1000 | [diff] [blame] | 402 | case 4: engn = NVDEV_ENGINE_CE0; break; |
| 403 | case 5: engn = NVDEV_ENGINE_CE1; break; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 404 | default: |
| 405 | return NULL; |
| 406 | } |
| 407 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 408 | return nvkm_engine(fifo, engn); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 409 | } |
| 410 | |
| 411 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 412 | gf100_fifo_recover_work(struct work_struct *work) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 413 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 414 | struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 415 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 416 | struct nvkm_object *engine; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 417 | unsigned long flags; |
| 418 | u32 engn, engm = 0; |
| 419 | u64 mask, todo; |
| 420 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 421 | spin_lock_irqsave(&fifo->base.lock, flags); |
| 422 | mask = fifo->mask; |
| 423 | fifo->mask = 0ULL; |
| 424 | spin_unlock_irqrestore(&fifo->base.lock, flags); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 425 | |
| 426 | for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 427 | engm |= 1 << gf100_fifo_engidx(fifo, engn); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 428 | nvkm_mask(device, 0x002630, engm, engm); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 429 | |
| 430 | for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 431 | if ((engine = (void *)nvkm_engine(fifo, engn))) { |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 432 | nv_ofuncs(engine)->fini(engine, false); |
| 433 | WARN_ON(nv_ofuncs(engine)->init(engine)); |
| 434 | } |
| 435 | } |
| 436 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 437 | gf100_fifo_runlist_update(fifo); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 438 | nvkm_wr32(device, 0x00262c, engm); |
| 439 | nvkm_mask(device, 0x002630, engm, 0x00000000); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 440 | } |
| 441 | |
| 442 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 443 | gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 444 | struct gf100_fifo_chan *chan) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 445 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 446 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 447 | u32 chid = chan->base.chid; |
| 448 | unsigned long flags; |
| 449 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 450 | nv_error(fifo, "%s engine fault on channel %d, recovering...\n", |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 451 | nv_subdev(engine)->name, chid); |
| 452 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 453 | nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 454 | chan->state = KILLED; |
| 455 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 456 | spin_lock_irqsave(&fifo->base.lock, flags); |
| 457 | fifo->mask |= 1ULL << nv_engidx(engine); |
| 458 | spin_unlock_irqrestore(&fifo->base.lock, flags); |
| 459 | schedule_work(&fifo->fault); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 460 | } |
| 461 | |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 462 | static int |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 463 | gf100_fifo_swmthd(struct gf100_fifo *fifo, u32 chid, u32 mthd, u32 data) |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 464 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 465 | struct gf100_fifo_chan *chan = NULL; |
| 466 | struct nvkm_handle *bind; |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 467 | unsigned long flags; |
| 468 | int ret = -EINVAL; |
| 469 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 470 | spin_lock_irqsave(&fifo->base.lock, flags); |
| 471 | if (likely(chid >= fifo->base.min && chid <= fifo->base.max)) |
| 472 | chan = (void *)fifo->base.channel[chid]; |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 473 | if (unlikely(!chan)) |
| 474 | goto out; |
| 475 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 476 | bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 477 | if (likely(bind)) { |
| 478 | if (!mthd || !nv_call(bind->object, mthd, data)) |
| 479 | ret = 0; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 480 | nvkm_namedb_put(bind); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 481 | } |
| 482 | |
| 483 | out: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 484 | spin_unlock_irqrestore(&fifo->base.lock, flags); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 485 | return ret; |
| 486 | } |
| 487 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 488 | static const struct nvkm_enum |
| 489 | gf100_fifo_sched_reason[] = { |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 490 | { 0x0a, "CTXSW_TIMEOUT" }, |
| 491 | {} |
| 492 | }; |
| 493 | |
| 494 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 495 | gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 496 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 497 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 498 | struct nvkm_engine *engine; |
| 499 | struct gf100_fifo_chan *chan; |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 500 | u32 engn; |
| 501 | |
| 502 | for (engn = 0; engn < 6; engn++) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 503 | u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 504 | u32 busy = (stat & 0x80000000); |
| 505 | u32 save = (stat & 0x00100000); /* maybe? */ |
| 506 | u32 unk0 = (stat & 0x00040000); |
| 507 | u32 unk1 = (stat & 0x00001000); |
| 508 | u32 chid = (stat & 0x0000007f); |
| 509 | (void)save; |
| 510 | |
| 511 | if (busy && unk0 && unk1) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 512 | if (!(chan = (void *)fifo->base.channel[chid])) |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 513 | continue; |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 514 | if (!(engine = gf100_fifo_engine(fifo, engn))) |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 515 | continue; |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 516 | gf100_fifo_recover(fifo, engine, chan); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 517 | } |
| 518 | } |
| 519 | } |
| 520 | |
| 521 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 522 | gf100_fifo_intr_sched(struct gf100_fifo *fifo) |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 523 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 524 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 525 | u32 intr = nvkm_rd32(device, 0x00254c); |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 526 | u32 code = intr & 0x000000ff; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 527 | const struct nvkm_enum *en; |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 528 | char enunk[6] = ""; |
| 529 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 530 | en = nvkm_enum_find(gf100_fifo_sched_reason, code); |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 531 | if (!en) |
| 532 | snprintf(enunk, sizeof(enunk), "UNK%02x", code); |
| 533 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 534 | nv_error(fifo, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 535 | |
| 536 | switch (code) { |
| 537 | case 0x0a: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 538 | gf100_fifo_intr_sched_ctxsw(fifo); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 539 | break; |
| 540 | default: |
| 541 | break; |
| 542 | } |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 543 | } |
| 544 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 545 | static const struct nvkm_enum |
| 546 | gf100_fifo_fault_engine[] = { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 547 | { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 548 | { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB }, |
| 549 | { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, |
| 550 | { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 551 | { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO }, |
Ben Skeggs | eccf7e8a | 2015-01-14 10:09:24 +1000 | [diff] [blame] | 552 | { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD }, |
Ben Skeggs | fd8666f | 2015-01-14 12:26:28 +1000 | [diff] [blame] | 553 | { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 554 | { 0x13, "PCOUNTER" }, |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 555 | { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC }, |
Ben Skeggs | aedf24f | 2015-01-14 11:50:20 +1000 | [diff] [blame] | 556 | { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 }, |
| 557 | { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 558 | { 0x17, "PDAEMON" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 559 | {} |
| 560 | }; |
| 561 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 562 | static const struct nvkm_enum |
| 563 | gf100_fifo_fault_reason[] = { |
Ben Skeggs | e296663 | 2011-03-29 08:57:34 +1000 | [diff] [blame] | 564 | { 0x00, "PT_NOT_PRESENT" }, |
| 565 | { 0x01, "PT_TOO_SHORT" }, |
| 566 | { 0x02, "PAGE_NOT_PRESENT" }, |
| 567 | { 0x03, "VM_LIMIT_EXCEEDED" }, |
| 568 | { 0x04, "NO_CHANNEL" }, |
| 569 | { 0x05, "PAGE_SYSTEM_ONLY" }, |
| 570 | { 0x06, "PAGE_READ_ONLY" }, |
| 571 | { 0x0a, "COMPRESSED_SYSRAM" }, |
| 572 | { 0x0c, "INVALID_STORAGE_TYPE" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 573 | {} |
| 574 | }; |
| 575 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 576 | static const struct nvkm_enum |
| 577 | gf100_fifo_fault_hubclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 578 | { 0x01, "PCOPY0" }, |
| 579 | { 0x02, "PCOPY1" }, |
| 580 | { 0x04, "DISPATCH" }, |
| 581 | { 0x05, "CTXCTL" }, |
| 582 | { 0x06, "PFIFO" }, |
| 583 | { 0x07, "BAR_READ" }, |
| 584 | { 0x08, "BAR_WRITE" }, |
| 585 | { 0x0b, "PVP" }, |
Ben Skeggs | fd8666f | 2015-01-14 12:26:28 +1000 | [diff] [blame] | 586 | { 0x0c, "PMSPPP" }, |
Ben Skeggs | eccf7e8a | 2015-01-14 10:09:24 +1000 | [diff] [blame] | 587 | { 0x0d, "PMSVLD" }, |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 588 | { 0x11, "PCOUNTER" }, |
| 589 | { 0x12, "PDAEMON" }, |
| 590 | { 0x14, "CCACHE" }, |
| 591 | { 0x15, "CCACHE_POST" }, |
| 592 | {} |
| 593 | }; |
| 594 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 595 | static const struct nvkm_enum |
| 596 | gf100_fifo_fault_gpcclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 597 | { 0x01, "TEX" }, |
| 598 | { 0x0c, "ESETUP" }, |
| 599 | { 0x0e, "CTXCTL" }, |
| 600 | { 0x0f, "PROP" }, |
| 601 | {} |
| 602 | }; |
| 603 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 604 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 605 | gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 606 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 607 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 608 | u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); |
| 609 | u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); |
| 610 | u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); |
| 611 | u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10)); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 612 | u32 gpc = (stat & 0x1f000000) >> 24; |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 613 | u32 client = (stat & 0x00001f00) >> 8; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 614 | u32 write = (stat & 0x00000080); |
| 615 | u32 hub = (stat & 0x00000040); |
| 616 | u32 reason = (stat & 0x0000000f); |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 617 | struct nvkm_object *engctx = NULL, *object; |
| 618 | struct nvkm_engine *engine = NULL; |
| 619 | const struct nvkm_enum *er, *eu, *ec; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 620 | char erunk[6] = ""; |
| 621 | char euunk[6] = ""; |
| 622 | char ecunk[6] = ""; |
| 623 | char gpcid[3] = ""; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 624 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 625 | er = nvkm_enum_find(gf100_fifo_fault_reason, reason); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 626 | if (!er) |
| 627 | snprintf(erunk, sizeof(erunk), "UNK%02X", reason); |
| 628 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 629 | eu = nvkm_enum_find(gf100_fifo_fault_engine, unit); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 630 | if (eu) { |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 631 | switch (eu->data2) { |
| 632 | case NVDEV_SUBDEV_BAR: |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 633 | nvkm_mask(device, 0x001704, 0x00000000, 0x00000000); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 634 | break; |
| 635 | case NVDEV_SUBDEV_INSTMEM: |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 636 | nvkm_mask(device, 0x001714, 0x00000000, 0x00000000); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 637 | break; |
| 638 | case NVDEV_ENGINE_IFB: |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 639 | nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 640 | break; |
| 641 | default: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 642 | engine = nvkm_engine(fifo, eu->data2); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 643 | if (engine) |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 644 | engctx = nvkm_engctx_get(engine, inst); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 645 | break; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 646 | } |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 647 | } else { |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 648 | snprintf(euunk, sizeof(euunk), "UNK%02x", unit); |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 649 | } |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 650 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 651 | if (hub) { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 652 | ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 653 | } else { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 654 | ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 655 | snprintf(gpcid, sizeof(gpcid), "%d", gpc); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 656 | } |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 657 | |
| 658 | if (!ec) |
| 659 | snprintf(ecunk, sizeof(ecunk), "UNK%02x", client); |
| 660 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 661 | nv_error(fifo, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on " |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 662 | "channel 0x%010llx [%s]\n", write ? "write" : "read", |
| 663 | (u64)vahi << 32 | valo, er ? er->name : erunk, |
| 664 | eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/", |
| 665 | ec ? ec->name : ecunk, (u64)inst << 12, |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 666 | nvkm_client_name(engctx)); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 667 | |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 668 | object = engctx; |
| 669 | while (object) { |
| 670 | switch (nv_mclass(object)) { |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 671 | case FERMI_CHANNEL_GPFIFO: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 672 | gf100_fifo_recover(fifo, engine, (void *)object); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 673 | break; |
| 674 | } |
| 675 | object = object->parent; |
| 676 | } |
| 677 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 678 | nvkm_engctx_put(engctx); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 679 | } |
| 680 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 681 | static const struct nvkm_bitfield |
| 682 | gf100_fifo_pbdma_intr[] = { |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 683 | /* { 0x00008000, "" } seen with null ib push */ |
| 684 | { 0x00200000, "ILLEGAL_MTHD" }, |
| 685 | { 0x00800000, "EMPTY_SUBC" }, |
| 686 | {} |
| 687 | }; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 688 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 689 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 690 | gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 691 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 692 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 693 | u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)); |
| 694 | u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000)); |
| 695 | u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000)); |
| 696 | u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 697 | u32 subc = (addr & 0x00070000) >> 16; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 698 | u32 mthd = (addr & 0x00003ffc); |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 699 | u32 show = stat; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 700 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 701 | if (stat & 0x00800000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 702 | if (!gf100_fifo_swmthd(fifo, chid, mthd, data)) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 703 | show &= ~0x00800000; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 704 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 705 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 706 | if (show) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 707 | nv_error(fifo, "PBDMA%d:", unit); |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 708 | nvkm_bitfield_print(gf100_fifo_pbdma_intr, show); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 709 | pr_cont("\n"); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 710 | nv_error(fifo, |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 711 | "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 712 | unit, chid, |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 713 | nvkm_client_name_for_fifo_chid(&fifo->base, chid), |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 714 | subc, mthd, data); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 715 | } |
| 716 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 717 | nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008); |
| 718 | nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 719 | } |
| 720 | |
| 721 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 722 | gf100_fifo_intr_runlist(struct gf100_fifo *fifo) |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 723 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 724 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 725 | u32 intr = nvkm_rd32(device, 0x002a00); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 726 | |
| 727 | if (intr & 0x10000000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 728 | wake_up(&fifo->runlist.wait); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 729 | nvkm_wr32(device, 0x002a00, 0x10000000); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 730 | intr &= ~0x10000000; |
| 731 | } |
| 732 | |
| 733 | if (intr) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 734 | nv_error(fifo, "RUNLIST 0x%08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 735 | nvkm_wr32(device, 0x002a00, intr); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 736 | } |
| 737 | } |
| 738 | |
| 739 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 740 | gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn) |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 741 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 742 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 743 | u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04)); |
| 744 | u32 inte = nvkm_rd32(device, 0x002628); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 745 | u32 unkn; |
| 746 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 747 | nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr); |
Ben Skeggs | 19a1082 | 2014-12-01 11:44:27 +1000 | [diff] [blame] | 748 | |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 749 | for (unkn = 0; unkn < 8; unkn++) { |
| 750 | u32 ints = (intr >> (unkn * 0x04)) & inte; |
| 751 | if (ints & 0x1) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 752 | nvkm_fifo_uevent(&fifo->base); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 753 | ints &= ~1; |
| 754 | } |
| 755 | if (ints) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 756 | nv_error(fifo, "ENGINE %d %d %01x", engn, unkn, ints); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 757 | nvkm_mask(device, 0x002628, ints, 0); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 758 | } |
| 759 | } |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 760 | } |
| 761 | |
| 762 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 763 | gf100_fifo_intr_engine(struct gf100_fifo *fifo) |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 764 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 765 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 766 | u32 mask = nvkm_rd32(device, 0x0025a4); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 767 | while (mask) { |
| 768 | u32 unit = __ffs(mask); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 769 | gf100_fifo_intr_engine_unit(fifo, unit); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 770 | mask &= ~(1 << unit); |
| 771 | } |
| 772 | } |
| 773 | |
| 774 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 775 | gf100_fifo_intr(struct nvkm_subdev *subdev) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 776 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 777 | struct gf100_fifo *fifo = (void *)subdev; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 778 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 779 | u32 mask = nvkm_rd32(device, 0x002140); |
| 780 | u32 stat = nvkm_rd32(device, 0x002100) & mask; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 781 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 782 | if (stat & 0x00000001) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 783 | u32 intr = nvkm_rd32(device, 0x00252c); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 784 | nv_warn(fifo, "INTR 0x00000001: 0x%08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 785 | nvkm_wr32(device, 0x002100, 0x00000001); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 786 | stat &= ~0x00000001; |
| 787 | } |
| 788 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 789 | if (stat & 0x00000100) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 790 | gf100_fifo_intr_sched(fifo); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 791 | nvkm_wr32(device, 0x002100, 0x00000100); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 792 | stat &= ~0x00000100; |
| 793 | } |
| 794 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 795 | if (stat & 0x00010000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 796 | u32 intr = nvkm_rd32(device, 0x00256c); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 797 | nv_warn(fifo, "INTR 0x00010000: 0x%08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 798 | nvkm_wr32(device, 0x002100, 0x00010000); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 799 | stat &= ~0x00010000; |
| 800 | } |
| 801 | |
| 802 | if (stat & 0x01000000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 803 | u32 intr = nvkm_rd32(device, 0x00258c); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 804 | nv_warn(fifo, "INTR 0x01000000: 0x%08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 805 | nvkm_wr32(device, 0x002100, 0x01000000); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 806 | stat &= ~0x01000000; |
| 807 | } |
| 808 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 809 | if (stat & 0x10000000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 810 | u32 mask = nvkm_rd32(device, 0x00259c); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 811 | while (mask) { |
| 812 | u32 unit = __ffs(mask); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 813 | gf100_fifo_intr_fault(fifo, unit); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 814 | nvkm_wr32(device, 0x00259c, (1 << unit)); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 815 | mask &= ~(1 << unit); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 816 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 817 | stat &= ~0x10000000; |
| 818 | } |
| 819 | |
| 820 | if (stat & 0x20000000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 821 | u32 mask = nvkm_rd32(device, 0x0025a0); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 822 | while (mask) { |
| 823 | u32 unit = __ffs(mask); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 824 | gf100_fifo_intr_pbdma(fifo, unit); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 825 | nvkm_wr32(device, 0x0025a0, (1 << unit)); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 826 | mask &= ~(1 << unit); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 827 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 828 | stat &= ~0x20000000; |
| 829 | } |
| 830 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 831 | if (stat & 0x40000000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 832 | gf100_fifo_intr_runlist(fifo); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 833 | stat &= ~0x40000000; |
| 834 | } |
| 835 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 836 | if (stat & 0x80000000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 837 | gf100_fifo_intr_engine(fifo); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 838 | stat &= ~0x80000000; |
| 839 | } |
| 840 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 841 | if (stat) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 842 | nv_error(fifo, "INTR 0x%08x\n", stat); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 843 | nvkm_mask(device, 0x002140, stat, 0x00000000); |
| 844 | nvkm_wr32(device, 0x002100, stat); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 845 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 846 | } |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 847 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 848 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 849 | gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index) |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 850 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 851 | struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 852 | struct nvkm_device *device = fifo->engine.subdev.device; |
| 853 | nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 854 | } |
| 855 | |
| 856 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 857 | gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index) |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 858 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 859 | struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 860 | struct nvkm_device *device = fifo->engine.subdev.device; |
| 861 | nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 862 | } |
| 863 | |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 864 | static const struct nvkm_event_func |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 865 | gf100_fifo_uevent_func = { |
| 866 | .ctor = nvkm_fifo_uevent_ctor, |
| 867 | .init = gf100_fifo_uevent_init, |
| 868 | .fini = gf100_fifo_uevent_fini, |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 869 | }; |
| 870 | |
| 871 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 872 | gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
| 873 | struct nvkm_oclass *oclass, void *data, u32 size, |
| 874 | struct nvkm_object **pobject) |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 875 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 876 | struct gf100_fifo *fifo; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 877 | int ret; |
| 878 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 879 | ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo); |
| 880 | *pobject = nv_object(fifo); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 881 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 882 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 883 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 884 | INIT_WORK(&fifo->fault, gf100_fifo_recover_work); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 885 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 886 | ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0, |
| 887 | &fifo->runlist.mem[0]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 888 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 889 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 890 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 891 | ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0, |
| 892 | &fifo->runlist.mem[1]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 893 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 894 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 895 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 896 | init_waitqueue_head(&fifo->runlist.wait); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 897 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 898 | ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 0x1000, 0x1000, 0, |
| 899 | &fifo->user.mem); |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 900 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 901 | return ret; |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 902 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 903 | ret = nvkm_gpuobj_map(fifo->user.mem, NV_MEM_ACCESS_RW, |
| 904 | &fifo->user.bar); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 905 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 906 | return ret; |
| 907 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 908 | ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent); |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 909 | if (ret) |
| 910 | return ret; |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 911 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 912 | nv_subdev(fifo)->unit = 0x00000100; |
| 913 | nv_subdev(fifo)->intr = gf100_fifo_intr; |
| 914 | nv_engine(fifo)->cclass = &gf100_fifo_cclass; |
| 915 | nv_engine(fifo)->sclass = gf100_fifo_sclass; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 916 | return 0; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 917 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 918 | |
| 919 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 920 | gf100_fifo_dtor(struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 921 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 922 | struct gf100_fifo *fifo = (void *)object; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 923 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 924 | nvkm_gpuobj_unmap(&fifo->user.bar); |
| 925 | nvkm_gpuobj_ref(NULL, &fifo->user.mem); |
| 926 | nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[0]); |
| 927 | nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[1]); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 928 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 929 | nvkm_fifo_destroy(&fifo->base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 930 | } |
| 931 | |
| 932 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 933 | gf100_fifo_init(struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 934 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 935 | struct gf100_fifo *fifo = (void *)object; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 936 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 937 | int ret, i; |
| 938 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 939 | ret = nvkm_fifo_init(&fifo->base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 940 | if (ret) |
| 941 | return ret; |
| 942 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 943 | nvkm_wr32(device, 0x000204, 0xffffffff); |
| 944 | nvkm_wr32(device, 0x002204, 0xffffffff); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 945 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 946 | fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204)); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 947 | nv_debug(fifo, "%d PBDMA unit(s)\n", fifo->spoon_nr); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 948 | |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 949 | /* assign engines to PBDMAs */ |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 950 | if (fifo->spoon_nr >= 3) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 951 | nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */ |
| 952 | nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */ |
| 953 | nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */ |
| 954 | nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */ |
| 955 | nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */ |
| 956 | nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 957 | } |
| 958 | |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 959 | /* PBDMA[n] */ |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 960 | for (i = 0; i < fifo->spoon_nr; i++) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 961 | nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); |
| 962 | nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ |
| 963 | nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 964 | } |
| 965 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 966 | nvkm_mask(device, 0x002200, 0x00000001, 0x00000001); |
| 967 | nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 968 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame^] | 969 | nvkm_wr32(device, 0x002100, 0xffffffff); |
| 970 | nvkm_wr32(device, 0x002140, 0x7fffffff); |
| 971 | nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 972 | return 0; |
| 973 | } |
| 974 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 975 | struct nvkm_oclass * |
| 976 | gf100_fifo_oclass = &(struct nvkm_oclass) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 977 | .handle = NV_ENGINE(FIFO, 0xc0), |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 978 | .ofuncs = &(struct nvkm_ofuncs) { |
| 979 | .ctor = gf100_fifo_ctor, |
| 980 | .dtor = gf100_fifo_dtor, |
| 981 | .init = gf100_fifo_init, |
| 982 | .fini = _nvkm_fifo_fini, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 983 | }, |
| 984 | }; |