Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/omap2/dss/dsi.c |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published by |
| 9 | * the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #define DSS_SUBSYS_NAME "DSI" |
| 21 | |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/clk.h> |
| 25 | #include <linux/device.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/interrupt.h> |
| 28 | #include <linux/delay.h> |
| 29 | #include <linux/mutex.h> |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 30 | #include <linux/semaphore.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 31 | #include <linux/seq_file.h> |
| 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/regulator/consumer.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 34 | #include <linux/wait.h> |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 35 | #include <linux/workqueue.h> |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 36 | #include <linux/sched.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 37 | |
Tomi Valkeinen | a0b38cc | 2011-05-11 14:05:07 +0300 | [diff] [blame] | 38 | #include <video/omapdss.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 39 | #include <plat/clock.h> |
| 40 | |
| 41 | #include "dss.h" |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 42 | #include "dss_features.h" |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 43 | |
| 44 | /*#define VERBOSE_IRQ*/ |
| 45 | #define DSI_CATCH_MISSING_TE |
| 46 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 47 | struct dsi_reg { u16 idx; }; |
| 48 | |
| 49 | #define DSI_REG(idx) ((const struct dsi_reg) { idx }) |
| 50 | |
| 51 | #define DSI_SZ_REGS SZ_1K |
| 52 | /* DSI Protocol Engine */ |
| 53 | |
| 54 | #define DSI_REVISION DSI_REG(0x0000) |
| 55 | #define DSI_SYSCONFIG DSI_REG(0x0010) |
| 56 | #define DSI_SYSSTATUS DSI_REG(0x0014) |
| 57 | #define DSI_IRQSTATUS DSI_REG(0x0018) |
| 58 | #define DSI_IRQENABLE DSI_REG(0x001C) |
| 59 | #define DSI_CTRL DSI_REG(0x0040) |
| 60 | #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) |
| 61 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) |
| 62 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) |
| 63 | #define DSI_CLK_CTRL DSI_REG(0x0054) |
| 64 | #define DSI_TIMING1 DSI_REG(0x0058) |
| 65 | #define DSI_TIMING2 DSI_REG(0x005C) |
| 66 | #define DSI_VM_TIMING1 DSI_REG(0x0060) |
| 67 | #define DSI_VM_TIMING2 DSI_REG(0x0064) |
| 68 | #define DSI_VM_TIMING3 DSI_REG(0x0068) |
| 69 | #define DSI_CLK_TIMING DSI_REG(0x006C) |
| 70 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) |
| 71 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) |
| 72 | #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) |
| 73 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) |
| 74 | #define DSI_VM_TIMING4 DSI_REG(0x0080) |
| 75 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) |
| 76 | #define DSI_VM_TIMING5 DSI_REG(0x0088) |
| 77 | #define DSI_VM_TIMING6 DSI_REG(0x008C) |
| 78 | #define DSI_VM_TIMING7 DSI_REG(0x0090) |
| 79 | #define DSI_STOPCLK_TIMING DSI_REG(0x0094) |
| 80 | #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) |
| 81 | #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) |
| 82 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) |
| 83 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) |
| 84 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) |
| 85 | #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) |
| 86 | #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) |
| 87 | |
| 88 | /* DSIPHY_SCP */ |
| 89 | |
| 90 | #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) |
| 91 | #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) |
| 92 | #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) |
| 93 | #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 94 | #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 95 | |
| 96 | /* DSI_PLL_CTRL_SCP */ |
| 97 | |
| 98 | #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) |
| 99 | #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) |
| 100 | #define DSI_PLL_GO DSI_REG(0x300 + 0x0008) |
| 101 | #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) |
| 102 | #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) |
| 103 | |
| 104 | #define REG_GET(idx, start, end) \ |
| 105 | FLD_GET(dsi_read_reg(idx), start, end) |
| 106 | |
| 107 | #define REG_FLD_MOD(idx, val, start, end) \ |
| 108 | dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end)) |
| 109 | |
| 110 | /* Global interrupts */ |
| 111 | #define DSI_IRQ_VC0 (1 << 0) |
| 112 | #define DSI_IRQ_VC1 (1 << 1) |
| 113 | #define DSI_IRQ_VC2 (1 << 2) |
| 114 | #define DSI_IRQ_VC3 (1 << 3) |
| 115 | #define DSI_IRQ_WAKEUP (1 << 4) |
| 116 | #define DSI_IRQ_RESYNC (1 << 5) |
| 117 | #define DSI_IRQ_PLL_LOCK (1 << 7) |
| 118 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) |
| 119 | #define DSI_IRQ_PLL_RECALL (1 << 9) |
| 120 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) |
| 121 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) |
| 122 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) |
| 123 | #define DSI_IRQ_TE_TRIGGER (1 << 16) |
| 124 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) |
| 125 | #define DSI_IRQ_SYNC_LOST (1 << 18) |
| 126 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) |
| 127 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) |
| 128 | #define DSI_IRQ_ERROR_MASK \ |
| 129 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ |
| 130 | DSI_IRQ_TA_TIMEOUT) |
| 131 | #define DSI_IRQ_CHANNEL_MASK 0xf |
| 132 | |
| 133 | /* Virtual channel interrupts */ |
| 134 | #define DSI_VC_IRQ_CS (1 << 0) |
| 135 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) |
| 136 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) |
| 137 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) |
| 138 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) |
| 139 | #define DSI_VC_IRQ_BTA (1 << 5) |
| 140 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) |
| 141 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) |
| 142 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) |
| 143 | #define DSI_VC_IRQ_ERROR_MASK \ |
| 144 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ |
| 145 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ |
| 146 | DSI_VC_IRQ_FIFO_TX_UDF) |
| 147 | |
| 148 | /* ComplexIO interrupts */ |
| 149 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) |
| 150 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) |
| 151 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) |
| 152 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) |
| 153 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) |
| 154 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) |
| 155 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
| 156 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) |
| 157 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) |
| 158 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
| 159 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) |
| 160 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) |
| 161 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
| 162 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) |
| 163 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) |
| 164 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) |
| 165 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) |
| 166 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) |
| 167 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
| 168 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame] | 169 | #define DSI_CIO_IRQ_ERROR_MASK \ |
| 170 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ |
| 171 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ |
| 172 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \ |
| 173 | DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \ |
| 174 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ |
| 175 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ |
| 176 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 177 | |
| 178 | #define DSI_DT_DCS_SHORT_WRITE_0 0x05 |
| 179 | #define DSI_DT_DCS_SHORT_WRITE_1 0x15 |
| 180 | #define DSI_DT_DCS_READ 0x06 |
| 181 | #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37 |
| 182 | #define DSI_DT_NULL_PACKET 0x09 |
| 183 | #define DSI_DT_DCS_LONG_WRITE 0x39 |
| 184 | |
| 185 | #define DSI_DT_RX_ACK_WITH_ERR 0x02 |
| 186 | #define DSI_DT_RX_DCS_LONG_READ 0x1c |
| 187 | #define DSI_DT_RX_SHORT_READ_1 0x21 |
| 188 | #define DSI_DT_RX_SHORT_READ_2 0x22 |
| 189 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 190 | typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); |
| 191 | |
| 192 | #define DSI_MAX_NR_ISRS 2 |
| 193 | |
| 194 | struct dsi_isr_data { |
| 195 | omap_dsi_isr_t isr; |
| 196 | void *arg; |
| 197 | u32 mask; |
| 198 | }; |
| 199 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 200 | enum fifo_size { |
| 201 | DSI_FIFO_SIZE_0 = 0, |
| 202 | DSI_FIFO_SIZE_32 = 1, |
| 203 | DSI_FIFO_SIZE_64 = 2, |
| 204 | DSI_FIFO_SIZE_96 = 3, |
| 205 | DSI_FIFO_SIZE_128 = 4, |
| 206 | }; |
| 207 | |
| 208 | enum dsi_vc_mode { |
| 209 | DSI_VC_MODE_L4 = 0, |
| 210 | DSI_VC_MODE_VP, |
| 211 | }; |
| 212 | |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 213 | enum dsi_lane { |
| 214 | DSI_CLK_P = 1 << 0, |
| 215 | DSI_CLK_N = 1 << 1, |
| 216 | DSI_DATA1_P = 1 << 2, |
| 217 | DSI_DATA1_N = 1 << 3, |
| 218 | DSI_DATA2_P = 1 << 4, |
| 219 | DSI_DATA2_N = 1 << 5, |
| 220 | }; |
| 221 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 222 | struct dsi_update_region { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 223 | u16 x, y, w, h; |
| 224 | struct omap_dss_device *device; |
| 225 | }; |
| 226 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 227 | struct dsi_irq_stats { |
| 228 | unsigned long last_reset; |
| 229 | unsigned irq_count; |
| 230 | unsigned dsi_irqs[32]; |
| 231 | unsigned vc_irqs[4][32]; |
| 232 | unsigned cio_irqs[32]; |
| 233 | }; |
| 234 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 235 | struct dsi_isr_tables { |
| 236 | struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; |
| 237 | struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; |
| 238 | struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; |
| 239 | }; |
| 240 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 241 | static struct |
| 242 | { |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 243 | struct platform_device *pdev; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 244 | void __iomem *base; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 245 | int irq; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 246 | |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 247 | void (*dsi_mux_pads)(bool enable); |
| 248 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 249 | struct dsi_clock_info current_cinfo; |
| 250 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 251 | bool vdds_dsi_enabled; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 252 | struct regulator *vdds_dsi_reg; |
| 253 | |
| 254 | struct { |
| 255 | enum dsi_vc_mode mode; |
| 256 | struct omap_dss_device *dssdev; |
| 257 | enum fifo_size fifo_size; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 258 | int vc_id; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 259 | } vc[4]; |
| 260 | |
| 261 | struct mutex lock; |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 262 | struct semaphore bus_lock; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 263 | |
| 264 | unsigned pll_locked; |
| 265 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 266 | spinlock_t irq_lock; |
| 267 | struct dsi_isr_tables isr_tables; |
| 268 | /* space for a copy used by the interrupt handler */ |
| 269 | struct dsi_isr_tables isr_tables_copy; |
| 270 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 271 | int update_channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 272 | struct dsi_update_region update_region; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 273 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 274 | bool te_enabled; |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 275 | bool ulps_enabled; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 276 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 277 | struct workqueue_struct *workqueue; |
| 278 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 279 | void (*framedone_callback)(int, void *); |
| 280 | void *framedone_data; |
| 281 | |
| 282 | struct delayed_work framedone_timeout_work; |
| 283 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 284 | #ifdef DSI_CATCH_MISSING_TE |
| 285 | struct timer_list te_timer; |
| 286 | #endif |
| 287 | |
| 288 | unsigned long cache_req_pck; |
| 289 | unsigned long cache_clk_freq; |
| 290 | struct dsi_clock_info cache_cinfo; |
| 291 | |
| 292 | u32 errors; |
| 293 | spinlock_t errors_lock; |
| 294 | #ifdef DEBUG |
| 295 | ktime_t perf_setup_time; |
| 296 | ktime_t perf_start_time; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 297 | #endif |
| 298 | int debug_read; |
| 299 | int debug_write; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 300 | |
| 301 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 302 | spinlock_t irq_stats_lock; |
| 303 | struct dsi_irq_stats irq_stats; |
| 304 | #endif |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 305 | /* DSI PLL Parameter Ranges */ |
| 306 | unsigned long regm_max, regn_max; |
| 307 | unsigned long regm_dispc_max, regm_dsi_max; |
| 308 | unsigned long fint_min, fint_max; |
| 309 | unsigned long lpdiv_max; |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 310 | |
| 311 | unsigned scp_clk_refcount; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 312 | } dsi; |
| 313 | |
| 314 | #ifdef DEBUG |
| 315 | static unsigned int dsi_perf; |
| 316 | module_param_named(dsi_perf, dsi_perf, bool, 0644); |
| 317 | #endif |
| 318 | |
| 319 | static inline void dsi_write_reg(const struct dsi_reg idx, u32 val) |
| 320 | { |
| 321 | __raw_writel(val, dsi.base + idx.idx); |
| 322 | } |
| 323 | |
| 324 | static inline u32 dsi_read_reg(const struct dsi_reg idx) |
| 325 | { |
| 326 | return __raw_readl(dsi.base + idx.idx); |
| 327 | } |
| 328 | |
| 329 | |
| 330 | void dsi_save_context(void) |
| 331 | { |
| 332 | } |
| 333 | |
| 334 | void dsi_restore_context(void) |
| 335 | { |
| 336 | } |
| 337 | |
| 338 | void dsi_bus_lock(void) |
| 339 | { |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 340 | down(&dsi.bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 341 | } |
| 342 | EXPORT_SYMBOL(dsi_bus_lock); |
| 343 | |
| 344 | void dsi_bus_unlock(void) |
| 345 | { |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 346 | up(&dsi.bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 347 | } |
| 348 | EXPORT_SYMBOL(dsi_bus_unlock); |
| 349 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 350 | static bool dsi_bus_is_locked(void) |
| 351 | { |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 352 | return dsi.bus_lock.count == 0; |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 353 | } |
| 354 | |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 355 | static void dsi_completion_handler(void *data, u32 mask) |
| 356 | { |
| 357 | complete((struct completion *)data); |
| 358 | } |
| 359 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 360 | static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum, |
| 361 | int value) |
| 362 | { |
| 363 | int t = 100000; |
| 364 | |
| 365 | while (REG_GET(idx, bitnum, bitnum) != value) { |
| 366 | if (--t == 0) |
| 367 | return !value; |
| 368 | } |
| 369 | |
| 370 | return value; |
| 371 | } |
| 372 | |
| 373 | #ifdef DEBUG |
| 374 | static void dsi_perf_mark_setup(void) |
| 375 | { |
| 376 | dsi.perf_setup_time = ktime_get(); |
| 377 | } |
| 378 | |
| 379 | static void dsi_perf_mark_start(void) |
| 380 | { |
| 381 | dsi.perf_start_time = ktime_get(); |
| 382 | } |
| 383 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 384 | static void dsi_perf_show(const char *name) |
| 385 | { |
| 386 | ktime_t t, setup_time, trans_time; |
| 387 | u32 total_bytes; |
| 388 | u32 setup_us, trans_us, total_us; |
| 389 | |
| 390 | if (!dsi_perf) |
| 391 | return; |
| 392 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 393 | t = ktime_get(); |
| 394 | |
| 395 | setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time); |
| 396 | setup_us = (u32)ktime_to_us(setup_time); |
| 397 | if (setup_us == 0) |
| 398 | setup_us = 1; |
| 399 | |
| 400 | trans_time = ktime_sub(t, dsi.perf_start_time); |
| 401 | trans_us = (u32)ktime_to_us(trans_time); |
| 402 | if (trans_us == 0) |
| 403 | trans_us = 1; |
| 404 | |
| 405 | total_us = setup_us + trans_us; |
| 406 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 407 | total_bytes = dsi.update_region.w * |
| 408 | dsi.update_region.h * |
| 409 | dsi.update_region.device->ctrl.pixel_size / 8; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 410 | |
Tomi Valkeinen | 1bbb275 | 2010-01-11 16:41:10 +0200 | [diff] [blame] | 411 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " |
| 412 | "%u bytes, %u kbytes/sec\n", |
| 413 | name, |
| 414 | setup_us, |
| 415 | trans_us, |
| 416 | total_us, |
| 417 | 1000*1000 / total_us, |
| 418 | total_bytes, |
| 419 | total_bytes * 1000 / total_us); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 420 | } |
| 421 | #else |
| 422 | #define dsi_perf_mark_setup() |
| 423 | #define dsi_perf_mark_start() |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 424 | #define dsi_perf_show(x) |
| 425 | #endif |
| 426 | |
| 427 | static void print_irq_status(u32 status) |
| 428 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 429 | if (status == 0) |
| 430 | return; |
| 431 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 432 | #ifndef VERBOSE_IRQ |
| 433 | if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) |
| 434 | return; |
| 435 | #endif |
| 436 | printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); |
| 437 | |
| 438 | #define PIS(x) \ |
| 439 | if (status & DSI_IRQ_##x) \ |
| 440 | printk(#x " "); |
| 441 | #ifdef VERBOSE_IRQ |
| 442 | PIS(VC0); |
| 443 | PIS(VC1); |
| 444 | PIS(VC2); |
| 445 | PIS(VC3); |
| 446 | #endif |
| 447 | PIS(WAKEUP); |
| 448 | PIS(RESYNC); |
| 449 | PIS(PLL_LOCK); |
| 450 | PIS(PLL_UNLOCK); |
| 451 | PIS(PLL_RECALL); |
| 452 | PIS(COMPLEXIO_ERR); |
| 453 | PIS(HS_TX_TIMEOUT); |
| 454 | PIS(LP_RX_TIMEOUT); |
| 455 | PIS(TE_TRIGGER); |
| 456 | PIS(ACK_TRIGGER); |
| 457 | PIS(SYNC_LOST); |
| 458 | PIS(LDO_POWER_GOOD); |
| 459 | PIS(TA_TIMEOUT); |
| 460 | #undef PIS |
| 461 | |
| 462 | printk("\n"); |
| 463 | } |
| 464 | |
| 465 | static void print_irq_status_vc(int channel, u32 status) |
| 466 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 467 | if (status == 0) |
| 468 | return; |
| 469 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 470 | #ifndef VERBOSE_IRQ |
| 471 | if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) |
| 472 | return; |
| 473 | #endif |
| 474 | printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); |
| 475 | |
| 476 | #define PIS(x) \ |
| 477 | if (status & DSI_VC_IRQ_##x) \ |
| 478 | printk(#x " "); |
| 479 | PIS(CS); |
| 480 | PIS(ECC_CORR); |
| 481 | #ifdef VERBOSE_IRQ |
| 482 | PIS(PACKET_SENT); |
| 483 | #endif |
| 484 | PIS(FIFO_TX_OVF); |
| 485 | PIS(FIFO_RX_OVF); |
| 486 | PIS(BTA); |
| 487 | PIS(ECC_NO_CORR); |
| 488 | PIS(FIFO_TX_UDF); |
| 489 | PIS(PP_BUSY_CHANGE); |
| 490 | #undef PIS |
| 491 | printk("\n"); |
| 492 | } |
| 493 | |
| 494 | static void print_irq_status_cio(u32 status) |
| 495 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 496 | if (status == 0) |
| 497 | return; |
| 498 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 499 | printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); |
| 500 | |
| 501 | #define PIS(x) \ |
| 502 | if (status & DSI_CIO_IRQ_##x) \ |
| 503 | printk(#x " "); |
| 504 | PIS(ERRSYNCESC1); |
| 505 | PIS(ERRSYNCESC2); |
| 506 | PIS(ERRSYNCESC3); |
| 507 | PIS(ERRESC1); |
| 508 | PIS(ERRESC2); |
| 509 | PIS(ERRESC3); |
| 510 | PIS(ERRCONTROL1); |
| 511 | PIS(ERRCONTROL2); |
| 512 | PIS(ERRCONTROL3); |
| 513 | PIS(STATEULPS1); |
| 514 | PIS(STATEULPS2); |
| 515 | PIS(STATEULPS3); |
| 516 | PIS(ERRCONTENTIONLP0_1); |
| 517 | PIS(ERRCONTENTIONLP1_1); |
| 518 | PIS(ERRCONTENTIONLP0_2); |
| 519 | PIS(ERRCONTENTIONLP1_2); |
| 520 | PIS(ERRCONTENTIONLP0_3); |
| 521 | PIS(ERRCONTENTIONLP1_3); |
| 522 | PIS(ULPSACTIVENOT_ALL0); |
| 523 | PIS(ULPSACTIVENOT_ALL1); |
| 524 | #undef PIS |
| 525 | |
| 526 | printk("\n"); |
| 527 | } |
| 528 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 529 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 530 | static void dsi_collect_irq_stats(u32 irqstatus, u32 *vcstatus, u32 ciostatus) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 531 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 532 | int i; |
| 533 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 534 | spin_lock(&dsi.irq_stats_lock); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 535 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 536 | dsi.irq_stats.irq_count++; |
| 537 | dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 538 | |
| 539 | for (i = 0; i < 4; ++i) |
| 540 | dss_collect_irq_stats(vcstatus[i], dsi.irq_stats.vc_irqs[i]); |
| 541 | |
| 542 | dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs); |
| 543 | |
| 544 | spin_unlock(&dsi.irq_stats_lock); |
| 545 | } |
| 546 | #else |
| 547 | #define dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus) |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 548 | #endif |
| 549 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 550 | static int debug_irq; |
| 551 | |
| 552 | static void dsi_handle_irq_errors(u32 irqstatus, u32 *vcstatus, u32 ciostatus) |
| 553 | { |
| 554 | int i; |
| 555 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 556 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
| 557 | DSSERR("DSI error, irqstatus %x\n", irqstatus); |
| 558 | print_irq_status(irqstatus); |
| 559 | spin_lock(&dsi.errors_lock); |
| 560 | dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK; |
| 561 | spin_unlock(&dsi.errors_lock); |
| 562 | } else if (debug_irq) { |
| 563 | print_irq_status(irqstatus); |
| 564 | } |
| 565 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 566 | for (i = 0; i < 4; ++i) { |
| 567 | if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { |
| 568 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", |
| 569 | i, vcstatus[i]); |
| 570 | print_irq_status_vc(i, vcstatus[i]); |
| 571 | } else if (debug_irq) { |
| 572 | print_irq_status_vc(i, vcstatus[i]); |
| 573 | } |
| 574 | } |
| 575 | |
| 576 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
| 577 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); |
| 578 | print_irq_status_cio(ciostatus); |
| 579 | } else if (debug_irq) { |
| 580 | print_irq_status_cio(ciostatus); |
| 581 | } |
| 582 | } |
| 583 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 584 | static void dsi_call_isrs(struct dsi_isr_data *isr_array, |
| 585 | unsigned isr_array_size, u32 irqstatus) |
| 586 | { |
| 587 | struct dsi_isr_data *isr_data; |
| 588 | int i; |
| 589 | |
| 590 | for (i = 0; i < isr_array_size; i++) { |
| 591 | isr_data = &isr_array[i]; |
| 592 | if (isr_data->isr && isr_data->mask & irqstatus) |
| 593 | isr_data->isr(isr_data->arg, irqstatus); |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, |
| 598 | u32 irqstatus, u32 *vcstatus, u32 ciostatus) |
| 599 | { |
| 600 | int i; |
| 601 | |
| 602 | dsi_call_isrs(isr_tables->isr_table, |
| 603 | ARRAY_SIZE(isr_tables->isr_table), |
| 604 | irqstatus); |
| 605 | |
| 606 | for (i = 0; i < 4; ++i) { |
| 607 | if (vcstatus[i] == 0) |
| 608 | continue; |
| 609 | dsi_call_isrs(isr_tables->isr_table_vc[i], |
| 610 | ARRAY_SIZE(isr_tables->isr_table_vc[i]), |
| 611 | vcstatus[i]); |
| 612 | } |
| 613 | |
| 614 | if (ciostatus != 0) |
| 615 | dsi_call_isrs(isr_tables->isr_table_cio, |
| 616 | ARRAY_SIZE(isr_tables->isr_table_cio), |
| 617 | ciostatus); |
| 618 | } |
| 619 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 620 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) |
| 621 | { |
| 622 | u32 irqstatus, vcstatus[4], ciostatus; |
| 623 | int i; |
| 624 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 625 | spin_lock(&dsi.irq_lock); |
| 626 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 627 | irqstatus = dsi_read_reg(DSI_IRQSTATUS); |
| 628 | |
| 629 | /* IRQ is not for us */ |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 630 | if (!irqstatus) { |
| 631 | spin_unlock(&dsi.irq_lock); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 632 | return IRQ_NONE; |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 633 | } |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 634 | |
| 635 | dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
| 636 | /* flush posted write */ |
| 637 | dsi_read_reg(DSI_IRQSTATUS); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 638 | |
| 639 | for (i = 0; i < 4; ++i) { |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 640 | if ((irqstatus & (1 << i)) == 0) { |
| 641 | vcstatus[i] = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 642 | continue; |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 643 | } |
| 644 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 645 | vcstatus[i] = dsi_read_reg(DSI_VC_IRQSTATUS(i)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 646 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 647 | dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus[i]); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 648 | /* flush posted write */ |
| 649 | dsi_read_reg(DSI_VC_IRQSTATUS(i)); |
| 650 | } |
| 651 | |
| 652 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { |
| 653 | ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); |
| 654 | |
| 655 | dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus); |
| 656 | /* flush posted write */ |
| 657 | dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 658 | } else { |
| 659 | ciostatus = 0; |
| 660 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 661 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 662 | #ifdef DSI_CATCH_MISSING_TE |
| 663 | if (irqstatus & DSI_IRQ_TE_TRIGGER) |
| 664 | del_timer(&dsi.te_timer); |
| 665 | #endif |
| 666 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 667 | /* make a copy and unlock, so that isrs can unregister |
| 668 | * themselves */ |
| 669 | memcpy(&dsi.isr_tables_copy, &dsi.isr_tables, sizeof(dsi.isr_tables)); |
| 670 | |
| 671 | spin_unlock(&dsi.irq_lock); |
| 672 | |
| 673 | dsi_handle_isrs(&dsi.isr_tables_copy, irqstatus, vcstatus, ciostatus); |
| 674 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 675 | dsi_handle_irq_errors(irqstatus, vcstatus, ciostatus); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 676 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 677 | dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus); |
| 678 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 679 | return IRQ_HANDLED; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 680 | } |
| 681 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 682 | /* dsi.irq_lock has to be locked by the caller */ |
| 683 | static void _omap_dsi_configure_irqs(struct dsi_isr_data *isr_array, |
| 684 | unsigned isr_array_size, u32 default_mask, |
| 685 | const struct dsi_reg enable_reg, |
| 686 | const struct dsi_reg status_reg) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 687 | { |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 688 | struct dsi_isr_data *isr_data; |
| 689 | u32 mask; |
| 690 | u32 old_mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 691 | int i; |
| 692 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 693 | mask = default_mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 694 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 695 | for (i = 0; i < isr_array_size; i++) { |
| 696 | isr_data = &isr_array[i]; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 697 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 698 | if (isr_data->isr == NULL) |
| 699 | continue; |
| 700 | |
| 701 | mask |= isr_data->mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 702 | } |
| 703 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 704 | old_mask = dsi_read_reg(enable_reg); |
| 705 | /* clear the irqstatus for newly enabled irqs */ |
| 706 | dsi_write_reg(status_reg, (mask ^ old_mask) & mask); |
| 707 | dsi_write_reg(enable_reg, mask); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 708 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 709 | /* flush posted writes */ |
| 710 | dsi_read_reg(enable_reg); |
| 711 | dsi_read_reg(status_reg); |
| 712 | } |
| 713 | |
| 714 | /* dsi.irq_lock has to be locked by the caller */ |
| 715 | static void _omap_dsi_set_irqs(void) |
| 716 | { |
| 717 | u32 mask = DSI_IRQ_ERROR_MASK; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 718 | #ifdef DSI_CATCH_MISSING_TE |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 719 | mask |= DSI_IRQ_TE_TRIGGER; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 720 | #endif |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 721 | _omap_dsi_configure_irqs(dsi.isr_tables.isr_table, |
| 722 | ARRAY_SIZE(dsi.isr_tables.isr_table), mask, |
| 723 | DSI_IRQENABLE, DSI_IRQSTATUS); |
| 724 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 725 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 726 | /* dsi.irq_lock has to be locked by the caller */ |
| 727 | static void _omap_dsi_set_irqs_vc(int vc) |
| 728 | { |
| 729 | _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_vc[vc], |
| 730 | ARRAY_SIZE(dsi.isr_tables.isr_table_vc[vc]), |
| 731 | DSI_VC_IRQ_ERROR_MASK, |
| 732 | DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); |
| 733 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 734 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 735 | /* dsi.irq_lock has to be locked by the caller */ |
| 736 | static void _omap_dsi_set_irqs_cio(void) |
| 737 | { |
| 738 | _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_cio, |
| 739 | ARRAY_SIZE(dsi.isr_tables.isr_table_cio), |
| 740 | DSI_CIO_IRQ_ERROR_MASK, |
| 741 | DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); |
| 742 | } |
| 743 | |
| 744 | static void _dsi_initialize_irq(void) |
| 745 | { |
| 746 | unsigned long flags; |
| 747 | int vc; |
| 748 | |
| 749 | spin_lock_irqsave(&dsi.irq_lock, flags); |
| 750 | |
| 751 | memset(&dsi.isr_tables, 0, sizeof(dsi.isr_tables)); |
| 752 | |
| 753 | _omap_dsi_set_irqs(); |
| 754 | for (vc = 0; vc < 4; ++vc) |
| 755 | _omap_dsi_set_irqs_vc(vc); |
| 756 | _omap_dsi_set_irqs_cio(); |
| 757 | |
| 758 | spin_unlock_irqrestore(&dsi.irq_lock, flags); |
| 759 | } |
| 760 | |
| 761 | static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
| 762 | struct dsi_isr_data *isr_array, unsigned isr_array_size) |
| 763 | { |
| 764 | struct dsi_isr_data *isr_data; |
| 765 | int free_idx; |
| 766 | int i; |
| 767 | |
| 768 | BUG_ON(isr == NULL); |
| 769 | |
| 770 | /* check for duplicate entry and find a free slot */ |
| 771 | free_idx = -1; |
| 772 | for (i = 0; i < isr_array_size; i++) { |
| 773 | isr_data = &isr_array[i]; |
| 774 | |
| 775 | if (isr_data->isr == isr && isr_data->arg == arg && |
| 776 | isr_data->mask == mask) { |
| 777 | return -EINVAL; |
| 778 | } |
| 779 | |
| 780 | if (isr_data->isr == NULL && free_idx == -1) |
| 781 | free_idx = i; |
| 782 | } |
| 783 | |
| 784 | if (free_idx == -1) |
| 785 | return -EBUSY; |
| 786 | |
| 787 | isr_data = &isr_array[free_idx]; |
| 788 | isr_data->isr = isr; |
| 789 | isr_data->arg = arg; |
| 790 | isr_data->mask = mask; |
| 791 | |
| 792 | return 0; |
| 793 | } |
| 794 | |
| 795 | static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
| 796 | struct dsi_isr_data *isr_array, unsigned isr_array_size) |
| 797 | { |
| 798 | struct dsi_isr_data *isr_data; |
| 799 | int i; |
| 800 | |
| 801 | for (i = 0; i < isr_array_size; i++) { |
| 802 | isr_data = &isr_array[i]; |
| 803 | if (isr_data->isr != isr || isr_data->arg != arg || |
| 804 | isr_data->mask != mask) |
| 805 | continue; |
| 806 | |
| 807 | isr_data->isr = NULL; |
| 808 | isr_data->arg = NULL; |
| 809 | isr_data->mask = 0; |
| 810 | |
| 811 | return 0; |
| 812 | } |
| 813 | |
| 814 | return -EINVAL; |
| 815 | } |
| 816 | |
| 817 | static int dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask) |
| 818 | { |
| 819 | unsigned long flags; |
| 820 | int r; |
| 821 | |
| 822 | spin_lock_irqsave(&dsi.irq_lock, flags); |
| 823 | |
| 824 | r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table, |
| 825 | ARRAY_SIZE(dsi.isr_tables.isr_table)); |
| 826 | |
| 827 | if (r == 0) |
| 828 | _omap_dsi_set_irqs(); |
| 829 | |
| 830 | spin_unlock_irqrestore(&dsi.irq_lock, flags); |
| 831 | |
| 832 | return r; |
| 833 | } |
| 834 | |
| 835 | static int dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask) |
| 836 | { |
| 837 | unsigned long flags; |
| 838 | int r; |
| 839 | |
| 840 | spin_lock_irqsave(&dsi.irq_lock, flags); |
| 841 | |
| 842 | r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table, |
| 843 | ARRAY_SIZE(dsi.isr_tables.isr_table)); |
| 844 | |
| 845 | if (r == 0) |
| 846 | _omap_dsi_set_irqs(); |
| 847 | |
| 848 | spin_unlock_irqrestore(&dsi.irq_lock, flags); |
| 849 | |
| 850 | return r; |
| 851 | } |
| 852 | |
| 853 | static int dsi_register_isr_vc(int channel, omap_dsi_isr_t isr, void *arg, |
| 854 | u32 mask) |
| 855 | { |
| 856 | unsigned long flags; |
| 857 | int r; |
| 858 | |
| 859 | spin_lock_irqsave(&dsi.irq_lock, flags); |
| 860 | |
| 861 | r = _dsi_register_isr(isr, arg, mask, |
| 862 | dsi.isr_tables.isr_table_vc[channel], |
| 863 | ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel])); |
| 864 | |
| 865 | if (r == 0) |
| 866 | _omap_dsi_set_irqs_vc(channel); |
| 867 | |
| 868 | spin_unlock_irqrestore(&dsi.irq_lock, flags); |
| 869 | |
| 870 | return r; |
| 871 | } |
| 872 | |
| 873 | static int dsi_unregister_isr_vc(int channel, omap_dsi_isr_t isr, void *arg, |
| 874 | u32 mask) |
| 875 | { |
| 876 | unsigned long flags; |
| 877 | int r; |
| 878 | |
| 879 | spin_lock_irqsave(&dsi.irq_lock, flags); |
| 880 | |
| 881 | r = _dsi_unregister_isr(isr, arg, mask, |
| 882 | dsi.isr_tables.isr_table_vc[channel], |
| 883 | ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel])); |
| 884 | |
| 885 | if (r == 0) |
| 886 | _omap_dsi_set_irqs_vc(channel); |
| 887 | |
| 888 | spin_unlock_irqrestore(&dsi.irq_lock, flags); |
| 889 | |
| 890 | return r; |
| 891 | } |
| 892 | |
| 893 | static int dsi_register_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask) |
| 894 | { |
| 895 | unsigned long flags; |
| 896 | int r; |
| 897 | |
| 898 | spin_lock_irqsave(&dsi.irq_lock, flags); |
| 899 | |
| 900 | r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio, |
| 901 | ARRAY_SIZE(dsi.isr_tables.isr_table_cio)); |
| 902 | |
| 903 | if (r == 0) |
| 904 | _omap_dsi_set_irqs_cio(); |
| 905 | |
| 906 | spin_unlock_irqrestore(&dsi.irq_lock, flags); |
| 907 | |
| 908 | return r; |
| 909 | } |
| 910 | |
| 911 | static int dsi_unregister_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask) |
| 912 | { |
| 913 | unsigned long flags; |
| 914 | int r; |
| 915 | |
| 916 | spin_lock_irqsave(&dsi.irq_lock, flags); |
| 917 | |
| 918 | r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio, |
| 919 | ARRAY_SIZE(dsi.isr_tables.isr_table_cio)); |
| 920 | |
| 921 | if (r == 0) |
| 922 | _omap_dsi_set_irqs_cio(); |
| 923 | |
| 924 | spin_unlock_irqrestore(&dsi.irq_lock, flags); |
| 925 | |
| 926 | return r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 927 | } |
| 928 | |
| 929 | static u32 dsi_get_errors(void) |
| 930 | { |
| 931 | unsigned long flags; |
| 932 | u32 e; |
| 933 | spin_lock_irqsave(&dsi.errors_lock, flags); |
| 934 | e = dsi.errors; |
| 935 | dsi.errors = 0; |
| 936 | spin_unlock_irqrestore(&dsi.errors_lock, flags); |
| 937 | return e; |
| 938 | } |
| 939 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 940 | /* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 941 | static inline void enable_clocks(bool enable) |
| 942 | { |
| 943 | if (enable) |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 944 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 945 | else |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 946 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 947 | } |
| 948 | |
| 949 | /* source clock for DSI PLL. this could also be PCLKFREE */ |
| 950 | static inline void dsi_enable_pll_clock(bool enable) |
| 951 | { |
| 952 | if (enable) |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 953 | dss_clk_enable(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 954 | else |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 955 | dss_clk_disable(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 956 | |
| 957 | if (enable && dsi.pll_locked) { |
| 958 | if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) |
| 959 | DSSERR("cannot lock PLL when enabling clocks\n"); |
| 960 | } |
| 961 | } |
| 962 | |
| 963 | #ifdef DEBUG |
| 964 | static void _dsi_print_reset_status(void) |
| 965 | { |
| 966 | u32 l; |
Tomi Valkeinen | c335cbf | 2010-10-07 13:27:42 +0300 | [diff] [blame] | 967 | int b0, b1, b2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 968 | |
| 969 | if (!dss_debug) |
| 970 | return; |
| 971 | |
| 972 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 973 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 974 | * I/O. */ |
| 975 | l = dsi_read_reg(DSI_DSIPHY_CFG5); |
| 976 | |
| 977 | printk(KERN_DEBUG "DSI resets: "); |
| 978 | |
| 979 | l = dsi_read_reg(DSI_PLL_STATUS); |
| 980 | printk("PLL (%d) ", FLD_GET(l, 0, 0)); |
| 981 | |
| 982 | l = dsi_read_reg(DSI_COMPLEXIO_CFG1); |
| 983 | printk("CIO (%d) ", FLD_GET(l, 29, 29)); |
| 984 | |
Tomi Valkeinen | c335cbf | 2010-10-07 13:27:42 +0300 | [diff] [blame] | 985 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { |
| 986 | b0 = 28; |
| 987 | b1 = 27; |
| 988 | b2 = 26; |
| 989 | } else { |
| 990 | b0 = 24; |
| 991 | b1 = 25; |
| 992 | b2 = 26; |
| 993 | } |
| 994 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 995 | l = dsi_read_reg(DSI_DSIPHY_CFG5); |
Tomi Valkeinen | c335cbf | 2010-10-07 13:27:42 +0300 | [diff] [blame] | 996 | printk("PHY (%x%x%x, %d, %d, %d)\n", |
| 997 | FLD_GET(l, b0, b0), |
| 998 | FLD_GET(l, b1, b1), |
| 999 | FLD_GET(l, b2, b2), |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1000 | FLD_GET(l, 29, 29), |
| 1001 | FLD_GET(l, 30, 30), |
| 1002 | FLD_GET(l, 31, 31)); |
| 1003 | } |
| 1004 | #else |
| 1005 | #define _dsi_print_reset_status() |
| 1006 | #endif |
| 1007 | |
| 1008 | static inline int dsi_if_enable(bool enable) |
| 1009 | { |
| 1010 | DSSDBG("dsi_if_enable(%d)\n", enable); |
| 1011 | |
| 1012 | enable = enable ? 1 : 0; |
| 1013 | REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */ |
| 1014 | |
| 1015 | if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) { |
| 1016 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); |
| 1017 | return -EIO; |
| 1018 | } |
| 1019 | |
| 1020 | return 0; |
| 1021 | } |
| 1022 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1023 | unsigned long dsi_get_pll_hsdiv_dispc_rate(void) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1024 | { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1025 | return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1026 | } |
| 1027 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1028 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(void) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1029 | { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1030 | return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1031 | } |
| 1032 | |
| 1033 | static unsigned long dsi_get_txbyteclkhs(void) |
| 1034 | { |
| 1035 | return dsi.current_cinfo.clkin4ddr / 16; |
| 1036 | } |
| 1037 | |
| 1038 | static unsigned long dsi_fclk_rate(void) |
| 1039 | { |
| 1040 | unsigned long r; |
| 1041 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1042 | if (dss_get_dsi_clk_source() == OMAP_DSS_CLK_SRC_FCK) { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1043 | /* DSI FCLK source is DSS_CLK_FCK */ |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1044 | r = dss_clk_get_rate(DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1045 | } else { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1046 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ |
| 1047 | r = dsi_get_pll_hsdiv_dsi_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1048 | } |
| 1049 | |
| 1050 | return r; |
| 1051 | } |
| 1052 | |
| 1053 | static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) |
| 1054 | { |
| 1055 | unsigned long dsi_fclk; |
| 1056 | unsigned lp_clk_div; |
| 1057 | unsigned long lp_clk; |
| 1058 | |
Tomi Valkeinen | c6940a3 | 2011-02-22 13:36:10 +0200 | [diff] [blame] | 1059 | lp_clk_div = dssdev->clocks.dsi.lp_clk_div; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1060 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1061 | if (lp_clk_div == 0 || lp_clk_div > dsi.lpdiv_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1062 | return -EINVAL; |
| 1063 | |
| 1064 | dsi_fclk = dsi_fclk_rate(); |
| 1065 | |
| 1066 | lp_clk = dsi_fclk / 2 / lp_clk_div; |
| 1067 | |
| 1068 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); |
| 1069 | dsi.current_cinfo.lp_clk = lp_clk; |
| 1070 | dsi.current_cinfo.lp_clk_div = lp_clk_div; |
| 1071 | |
| 1072 | REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */ |
| 1073 | |
| 1074 | REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, |
| 1075 | 21, 21); /* LP_RX_SYNCHRO_ENABLE */ |
| 1076 | |
| 1077 | return 0; |
| 1078 | } |
| 1079 | |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1080 | static void dsi_enable_scp_clk(void) |
| 1081 | { |
| 1082 | if (dsi.scp_clk_refcount++ == 0) |
| 1083 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ |
| 1084 | } |
| 1085 | |
| 1086 | static void dsi_disable_scp_clk(void) |
| 1087 | { |
| 1088 | WARN_ON(dsi.scp_clk_refcount == 0); |
| 1089 | if (--dsi.scp_clk_refcount == 0) |
| 1090 | REG_FLD_MOD(DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ |
| 1091 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1092 | |
| 1093 | enum dsi_pll_power_state { |
| 1094 | DSI_PLL_POWER_OFF = 0x0, |
| 1095 | DSI_PLL_POWER_ON_HSCLK = 0x1, |
| 1096 | DSI_PLL_POWER_ON_ALL = 0x2, |
| 1097 | DSI_PLL_POWER_ON_DIV = 0x3, |
| 1098 | }; |
| 1099 | |
| 1100 | static int dsi_pll_power(enum dsi_pll_power_state state) |
| 1101 | { |
| 1102 | int t = 0; |
| 1103 | |
Tomi Valkeinen | c94dfe0 | 2011-04-15 10:42:59 +0300 | [diff] [blame] | 1104 | /* DSI-PLL power command 0x3 is not working */ |
| 1105 | if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && |
| 1106 | state == DSI_PLL_POWER_ON_DIV) |
| 1107 | state = DSI_PLL_POWER_ON_ALL; |
| 1108 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1109 | REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */ |
| 1110 | |
| 1111 | /* PLL_PWR_STATUS */ |
| 1112 | while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1113 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1114 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
| 1115 | state); |
| 1116 | return -ENODEV; |
| 1117 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1118 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1119 | } |
| 1120 | |
| 1121 | return 0; |
| 1122 | } |
| 1123 | |
| 1124 | /* calculate clock rates using dividers in cinfo */ |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 1125 | static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, |
| 1126 | struct dsi_clock_info *cinfo) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1127 | { |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1128 | if (cinfo->regn == 0 || cinfo->regn > dsi.regn_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1129 | return -EINVAL; |
| 1130 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1131 | if (cinfo->regm == 0 || cinfo->regm > dsi.regm_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1132 | return -EINVAL; |
| 1133 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1134 | if (cinfo->regm_dispc > dsi.regm_dispc_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1135 | return -EINVAL; |
| 1136 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1137 | if (cinfo->regm_dsi > dsi.regm_dsi_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1138 | return -EINVAL; |
| 1139 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1140 | if (cinfo->use_sys_clk) { |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1141 | cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1142 | /* XXX it is unclear if highfreq should be used |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1143 | * with DSS_SYS_CLK source also */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1144 | cinfo->highfreq = 0; |
| 1145 | } else { |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 1146 | cinfo->clkin = dispc_pclk_rate(dssdev->manager->id); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1147 | |
| 1148 | if (cinfo->clkin < 32000000) |
| 1149 | cinfo->highfreq = 0; |
| 1150 | else |
| 1151 | cinfo->highfreq = 1; |
| 1152 | } |
| 1153 | |
| 1154 | cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1)); |
| 1155 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1156 | if (cinfo->fint > dsi.fint_max || cinfo->fint < dsi.fint_min) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1157 | return -EINVAL; |
| 1158 | |
| 1159 | cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; |
| 1160 | |
| 1161 | if (cinfo->clkin4ddr > 1800 * 1000 * 1000) |
| 1162 | return -EINVAL; |
| 1163 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1164 | if (cinfo->regm_dispc > 0) |
| 1165 | cinfo->dsi_pll_hsdiv_dispc_clk = |
| 1166 | cinfo->clkin4ddr / cinfo->regm_dispc; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1167 | else |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1168 | cinfo->dsi_pll_hsdiv_dispc_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1169 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1170 | if (cinfo->regm_dsi > 0) |
| 1171 | cinfo->dsi_pll_hsdiv_dsi_clk = |
| 1172 | cinfo->clkin4ddr / cinfo->regm_dsi; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1173 | else |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1174 | cinfo->dsi_pll_hsdiv_dsi_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1175 | |
| 1176 | return 0; |
| 1177 | } |
| 1178 | |
| 1179 | int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, |
| 1180 | struct dsi_clock_info *dsi_cinfo, |
| 1181 | struct dispc_clock_info *dispc_cinfo) |
| 1182 | { |
| 1183 | struct dsi_clock_info cur, best; |
| 1184 | struct dispc_clock_info best_dispc; |
| 1185 | int min_fck_per_pck; |
| 1186 | int match = 0; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1187 | unsigned long dss_sys_clk, max_dss_fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1188 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1189 | dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1190 | |
Taneja, Archit | 31ef823 | 2011-03-14 23:28:22 -0500 | [diff] [blame] | 1191 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 1192 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1193 | if (req_pck == dsi.cache_req_pck && |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1194 | dsi.cache_cinfo.clkin == dss_sys_clk) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1195 | DSSDBG("DSI clock info found from cache\n"); |
| 1196 | *dsi_cinfo = dsi.cache_cinfo; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1197 | dispc_find_clk_divs(is_tft, req_pck, |
| 1198 | dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1199 | return 0; |
| 1200 | } |
| 1201 | |
| 1202 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; |
| 1203 | |
| 1204 | if (min_fck_per_pck && |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 1205 | req_pck * min_fck_per_pck > max_dss_fck) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1206 | DSSERR("Requested pixel clock not possible with the current " |
| 1207 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " |
| 1208 | "the constraint off.\n"); |
| 1209 | min_fck_per_pck = 0; |
| 1210 | } |
| 1211 | |
| 1212 | DSSDBG("dsi_pll_calc\n"); |
| 1213 | |
| 1214 | retry: |
| 1215 | memset(&best, 0, sizeof(best)); |
| 1216 | memset(&best_dispc, 0, sizeof(best_dispc)); |
| 1217 | |
| 1218 | memset(&cur, 0, sizeof(cur)); |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1219 | cur.clkin = dss_sys_clk; |
| 1220 | cur.use_sys_clk = 1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1221 | cur.highfreq = 0; |
| 1222 | |
| 1223 | /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ |
| 1224 | /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ |
| 1225 | /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1226 | for (cur.regn = 1; cur.regn < dsi.regn_max; ++cur.regn) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1227 | if (cur.highfreq == 0) |
| 1228 | cur.fint = cur.clkin / cur.regn; |
| 1229 | else |
| 1230 | cur.fint = cur.clkin / (2 * cur.regn); |
| 1231 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1232 | if (cur.fint > dsi.fint_max || cur.fint < dsi.fint_min) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1233 | continue; |
| 1234 | |
| 1235 | /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1236 | for (cur.regm = 1; cur.regm < dsi.regm_max; ++cur.regm) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1237 | unsigned long a, b; |
| 1238 | |
| 1239 | a = 2 * cur.regm * (cur.clkin/1000); |
| 1240 | b = cur.regn * (cur.highfreq + 1); |
| 1241 | cur.clkin4ddr = a / b * 1000; |
| 1242 | |
| 1243 | if (cur.clkin4ddr > 1800 * 1000 * 1000) |
| 1244 | break; |
| 1245 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1246 | /* dsi_pll_hsdiv_dispc_clk(MHz) = |
| 1247 | * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1248 | for (cur.regm_dispc = 1; cur.regm_dispc < dsi.regm_dispc_max; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1249 | ++cur.regm_dispc) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1250 | struct dispc_clock_info cur_dispc; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1251 | cur.dsi_pll_hsdiv_dispc_clk = |
| 1252 | cur.clkin4ddr / cur.regm_dispc; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1253 | |
| 1254 | /* this will narrow down the search a bit, |
| 1255 | * but still give pixclocks below what was |
| 1256 | * requested */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1257 | if (cur.dsi_pll_hsdiv_dispc_clk < req_pck) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1258 | break; |
| 1259 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1260 | if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1261 | continue; |
| 1262 | |
| 1263 | if (min_fck_per_pck && |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1264 | cur.dsi_pll_hsdiv_dispc_clk < |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1265 | req_pck * min_fck_per_pck) |
| 1266 | continue; |
| 1267 | |
| 1268 | match = 1; |
| 1269 | |
| 1270 | dispc_find_clk_divs(is_tft, req_pck, |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1271 | cur.dsi_pll_hsdiv_dispc_clk, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1272 | &cur_dispc); |
| 1273 | |
| 1274 | if (abs(cur_dispc.pck - req_pck) < |
| 1275 | abs(best_dispc.pck - req_pck)) { |
| 1276 | best = cur; |
| 1277 | best_dispc = cur_dispc; |
| 1278 | |
| 1279 | if (cur_dispc.pck == req_pck) |
| 1280 | goto found; |
| 1281 | } |
| 1282 | } |
| 1283 | } |
| 1284 | } |
| 1285 | found: |
| 1286 | if (!match) { |
| 1287 | if (min_fck_per_pck) { |
| 1288 | DSSERR("Could not find suitable clock settings.\n" |
| 1289 | "Turning FCK/PCK constraint off and" |
| 1290 | "trying again.\n"); |
| 1291 | min_fck_per_pck = 0; |
| 1292 | goto retry; |
| 1293 | } |
| 1294 | |
| 1295 | DSSERR("Could not find suitable clock settings.\n"); |
| 1296 | |
| 1297 | return -EINVAL; |
| 1298 | } |
| 1299 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1300 | /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */ |
| 1301 | best.regm_dsi = 0; |
| 1302 | best.dsi_pll_hsdiv_dsi_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1303 | |
| 1304 | if (dsi_cinfo) |
| 1305 | *dsi_cinfo = best; |
| 1306 | if (dispc_cinfo) |
| 1307 | *dispc_cinfo = best_dispc; |
| 1308 | |
| 1309 | dsi.cache_req_pck = req_pck; |
| 1310 | dsi.cache_clk_freq = 0; |
| 1311 | dsi.cache_cinfo = best; |
| 1312 | |
| 1313 | return 0; |
| 1314 | } |
| 1315 | |
| 1316 | int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) |
| 1317 | { |
| 1318 | int r = 0; |
| 1319 | u32 l; |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 1320 | int f = 0; |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1321 | u8 regn_start, regn_end, regm_start, regm_end; |
| 1322 | u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1323 | |
| 1324 | DSSDBGF(); |
| 1325 | |
Tomi Valkeinen | b276509 | 2011-04-07 15:28:47 +0300 | [diff] [blame] | 1326 | dsi.current_cinfo.use_sys_clk = cinfo->use_sys_clk; |
| 1327 | dsi.current_cinfo.highfreq = cinfo->highfreq; |
| 1328 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1329 | dsi.current_cinfo.fint = cinfo->fint; |
| 1330 | dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1331 | dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk = |
| 1332 | cinfo->dsi_pll_hsdiv_dispc_clk; |
| 1333 | dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk = |
| 1334 | cinfo->dsi_pll_hsdiv_dsi_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1335 | |
| 1336 | dsi.current_cinfo.regn = cinfo->regn; |
| 1337 | dsi.current_cinfo.regm = cinfo->regm; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1338 | dsi.current_cinfo.regm_dispc = cinfo->regm_dispc; |
| 1339 | dsi.current_cinfo.regm_dsi = cinfo->regm_dsi; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1340 | |
| 1341 | DSSDBG("DSI Fint %ld\n", cinfo->fint); |
| 1342 | |
| 1343 | DSSDBG("clkin (%s) rate %ld, highfreq %d\n", |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1344 | cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1345 | cinfo->clkin, |
| 1346 | cinfo->highfreq); |
| 1347 | |
| 1348 | /* DSIPHY == CLKIN4DDR */ |
| 1349 | DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n", |
| 1350 | cinfo->regm, |
| 1351 | cinfo->regn, |
| 1352 | cinfo->clkin, |
| 1353 | cinfo->highfreq + 1, |
| 1354 | cinfo->clkin4ddr); |
| 1355 | |
| 1356 | DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", |
| 1357 | cinfo->clkin4ddr / 1000 / 1000 / 2); |
| 1358 | |
| 1359 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); |
| 1360 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1361 | DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1362 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
| 1363 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1364 | cinfo->dsi_pll_hsdiv_dispc_clk); |
| 1365 | DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1366 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
| 1367 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1368 | cinfo->dsi_pll_hsdiv_dsi_clk); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1369 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1370 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end); |
| 1371 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end); |
| 1372 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start, |
| 1373 | ®m_dispc_end); |
| 1374 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start, |
| 1375 | ®m_dsi_end); |
| 1376 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1377 | REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ |
| 1378 | |
| 1379 | l = dsi_read_reg(DSI_PLL_CONFIGURATION1); |
| 1380 | l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1381 | /* DSI_PLL_REGN */ |
| 1382 | l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end); |
| 1383 | /* DSI_PLL_REGM */ |
| 1384 | l = FLD_MOD(l, cinfo->regm, regm_start, regm_end); |
| 1385 | /* DSI_CLOCK_DIV */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1386 | l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1387 | regm_dispc_start, regm_dispc_end); |
| 1388 | /* DSIPROTO_CLOCK_DIV */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1389 | l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1390 | regm_dsi_start, regm_dsi_end); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1391 | dsi_write_reg(DSI_PLL_CONFIGURATION1, l); |
| 1392 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1393 | BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max); |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 1394 | |
| 1395 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) { |
| 1396 | f = cinfo->fint < 1000000 ? 0x3 : |
| 1397 | cinfo->fint < 1250000 ? 0x4 : |
| 1398 | cinfo->fint < 1500000 ? 0x5 : |
| 1399 | cinfo->fint < 1750000 ? 0x6 : |
| 1400 | 0x7; |
| 1401 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1402 | |
| 1403 | l = dsi_read_reg(DSI_PLL_CONFIGURATION2); |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 1404 | |
| 1405 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) |
| 1406 | l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1407 | l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1408 | 11, 11); /* DSI_PLL_CLKSEL */ |
| 1409 | l = FLD_MOD(l, cinfo->highfreq, |
| 1410 | 12, 12); /* DSI_PLL_HIGHFREQ */ |
| 1411 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
| 1412 | l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ |
| 1413 | l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ |
| 1414 | dsi_write_reg(DSI_PLL_CONFIGURATION2, l); |
| 1415 | |
| 1416 | REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ |
| 1417 | |
| 1418 | if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) { |
| 1419 | DSSERR("dsi pll go bit not going down.\n"); |
| 1420 | r = -EIO; |
| 1421 | goto err; |
| 1422 | } |
| 1423 | |
| 1424 | if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) { |
| 1425 | DSSERR("cannot lock PLL\n"); |
| 1426 | r = -EIO; |
| 1427 | goto err; |
| 1428 | } |
| 1429 | |
| 1430 | dsi.pll_locked = 1; |
| 1431 | |
| 1432 | l = dsi_read_reg(DSI_PLL_CONFIGURATION2); |
| 1433 | l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ |
| 1434 | l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ |
| 1435 | l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ |
| 1436 | l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ |
| 1437 | l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ |
| 1438 | l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ |
| 1439 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
| 1440 | l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ |
| 1441 | l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ |
| 1442 | l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ |
| 1443 | l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ |
| 1444 | l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ |
| 1445 | l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ |
| 1446 | l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ |
| 1447 | dsi_write_reg(DSI_PLL_CONFIGURATION2, l); |
| 1448 | |
| 1449 | DSSDBG("PLL config done\n"); |
| 1450 | err: |
| 1451 | return r; |
| 1452 | } |
| 1453 | |
| 1454 | int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk, |
| 1455 | bool enable_hsdiv) |
| 1456 | { |
| 1457 | int r = 0; |
| 1458 | enum dsi_pll_power_state pwstate; |
| 1459 | |
| 1460 | DSSDBG("PLL init\n"); |
| 1461 | |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1462 | if (dsi.vdds_dsi_reg == NULL) { |
| 1463 | struct regulator *vdds_dsi; |
| 1464 | |
| 1465 | vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); |
| 1466 | |
| 1467 | if (IS_ERR(vdds_dsi)) { |
| 1468 | DSSERR("can't get VDDS_DSI regulator\n"); |
| 1469 | return PTR_ERR(vdds_dsi); |
| 1470 | } |
| 1471 | |
| 1472 | dsi.vdds_dsi_reg = vdds_dsi; |
| 1473 | } |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1474 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1475 | enable_clocks(1); |
| 1476 | dsi_enable_pll_clock(1); |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1477 | /* |
| 1478 | * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. |
| 1479 | */ |
| 1480 | dsi_enable_scp_clk(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1481 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1482 | if (!dsi.vdds_dsi_enabled) { |
| 1483 | r = regulator_enable(dsi.vdds_dsi_reg); |
| 1484 | if (r) |
| 1485 | goto err0; |
| 1486 | dsi.vdds_dsi_enabled = true; |
| 1487 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1488 | |
| 1489 | /* XXX PLL does not come out of reset without this... */ |
| 1490 | dispc_pck_free_enable(1); |
| 1491 | |
| 1492 | if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) { |
| 1493 | DSSERR("PLL not coming out of reset.\n"); |
| 1494 | r = -ENODEV; |
Ville Syrjälä | 481dfa0 | 2010-04-22 22:50:04 +0200 | [diff] [blame] | 1495 | dispc_pck_free_enable(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1496 | goto err1; |
| 1497 | } |
| 1498 | |
| 1499 | /* XXX ... but if left on, we get problems when planes do not |
| 1500 | * fill the whole display. No idea about this */ |
| 1501 | dispc_pck_free_enable(0); |
| 1502 | |
| 1503 | if (enable_hsclk && enable_hsdiv) |
| 1504 | pwstate = DSI_PLL_POWER_ON_ALL; |
| 1505 | else if (enable_hsclk) |
| 1506 | pwstate = DSI_PLL_POWER_ON_HSCLK; |
| 1507 | else if (enable_hsdiv) |
| 1508 | pwstate = DSI_PLL_POWER_ON_DIV; |
| 1509 | else |
| 1510 | pwstate = DSI_PLL_POWER_OFF; |
| 1511 | |
| 1512 | r = dsi_pll_power(pwstate); |
| 1513 | |
| 1514 | if (r) |
| 1515 | goto err1; |
| 1516 | |
| 1517 | DSSDBG("PLL init done\n"); |
| 1518 | |
| 1519 | return 0; |
| 1520 | err1: |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1521 | if (dsi.vdds_dsi_enabled) { |
| 1522 | regulator_disable(dsi.vdds_dsi_reg); |
| 1523 | dsi.vdds_dsi_enabled = false; |
| 1524 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1525 | err0: |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1526 | dsi_disable_scp_clk(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1527 | enable_clocks(0); |
| 1528 | dsi_enable_pll_clock(0); |
| 1529 | return r; |
| 1530 | } |
| 1531 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1532 | void dsi_pll_uninit(bool disconnect_lanes) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1533 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1534 | dsi.pll_locked = 0; |
| 1535 | dsi_pll_power(DSI_PLL_POWER_OFF); |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1536 | if (disconnect_lanes) { |
| 1537 | WARN_ON(!dsi.vdds_dsi_enabled); |
| 1538 | regulator_disable(dsi.vdds_dsi_reg); |
| 1539 | dsi.vdds_dsi_enabled = false; |
| 1540 | } |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1541 | |
| 1542 | dsi_disable_scp_clk(); |
| 1543 | enable_clocks(0); |
| 1544 | dsi_enable_pll_clock(0); |
| 1545 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1546 | DSSDBG("PLL uninit done\n"); |
| 1547 | } |
| 1548 | |
| 1549 | void dsi_dump_clocks(struct seq_file *s) |
| 1550 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1551 | struct dsi_clock_info *cinfo = &dsi.current_cinfo; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1552 | enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1553 | |
| 1554 | dispc_clk_src = dss_get_dispc_clk_source(); |
| 1555 | dsi_clk_src = dss_get_dsi_clk_source(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1556 | |
| 1557 | enable_clocks(1); |
| 1558 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1559 | seq_printf(s, "- DSI PLL -\n"); |
| 1560 | |
| 1561 | seq_printf(s, "dsi pll source = %s\n", |
Tomi Valkeinen | a9a6500 | 2011-04-04 10:02:53 +0300 | [diff] [blame] | 1562 | cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1563 | |
| 1564 | seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); |
| 1565 | |
| 1566 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", |
| 1567 | cinfo->clkin4ddr, cinfo->regm); |
| 1568 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1569 | seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n", |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1570 | dss_get_generic_clk_source_name(dispc_clk_src), |
| 1571 | dss_feat_get_clk_source_name(dispc_clk_src), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1572 | cinfo->dsi_pll_hsdiv_dispc_clk, |
| 1573 | cinfo->regm_dispc, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1574 | dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1575 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1576 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1577 | seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n", |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1578 | dss_get_generic_clk_source_name(dsi_clk_src), |
| 1579 | dss_feat_get_clk_source_name(dsi_clk_src), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1580 | cinfo->dsi_pll_hsdiv_dsi_clk, |
| 1581 | cinfo->regm_dsi, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1582 | dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1583 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1584 | |
| 1585 | seq_printf(s, "- DSI -\n"); |
| 1586 | |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1587 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
| 1588 | dss_get_generic_clk_source_name(dsi_clk_src), |
| 1589 | dss_feat_get_clk_source_name(dsi_clk_src)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1590 | |
| 1591 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); |
| 1592 | |
| 1593 | seq_printf(s, "DDR_CLK\t\t%lu\n", |
| 1594 | cinfo->clkin4ddr / 4); |
| 1595 | |
| 1596 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs()); |
| 1597 | |
| 1598 | seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk); |
| 1599 | |
| 1600 | seq_printf(s, "VP_CLK\t\t%lu\n" |
| 1601 | "VP_PCLK\t\t%lu\n", |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 1602 | dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), |
| 1603 | dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1604 | |
| 1605 | enable_clocks(0); |
| 1606 | } |
| 1607 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1608 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 1609 | void dsi_dump_irqs(struct seq_file *s) |
| 1610 | { |
| 1611 | unsigned long flags; |
| 1612 | struct dsi_irq_stats stats; |
| 1613 | |
| 1614 | spin_lock_irqsave(&dsi.irq_stats_lock, flags); |
| 1615 | |
| 1616 | stats = dsi.irq_stats; |
| 1617 | memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats)); |
| 1618 | dsi.irq_stats.last_reset = jiffies; |
| 1619 | |
| 1620 | spin_unlock_irqrestore(&dsi.irq_stats_lock, flags); |
| 1621 | |
| 1622 | seq_printf(s, "period %u ms\n", |
| 1623 | jiffies_to_msecs(jiffies - stats.last_reset)); |
| 1624 | |
| 1625 | seq_printf(s, "irqs %d\n", stats.irq_count); |
| 1626 | #define PIS(x) \ |
| 1627 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); |
| 1628 | |
| 1629 | seq_printf(s, "-- DSI interrupts --\n"); |
| 1630 | PIS(VC0); |
| 1631 | PIS(VC1); |
| 1632 | PIS(VC2); |
| 1633 | PIS(VC3); |
| 1634 | PIS(WAKEUP); |
| 1635 | PIS(RESYNC); |
| 1636 | PIS(PLL_LOCK); |
| 1637 | PIS(PLL_UNLOCK); |
| 1638 | PIS(PLL_RECALL); |
| 1639 | PIS(COMPLEXIO_ERR); |
| 1640 | PIS(HS_TX_TIMEOUT); |
| 1641 | PIS(LP_RX_TIMEOUT); |
| 1642 | PIS(TE_TRIGGER); |
| 1643 | PIS(ACK_TRIGGER); |
| 1644 | PIS(SYNC_LOST); |
| 1645 | PIS(LDO_POWER_GOOD); |
| 1646 | PIS(TA_TIMEOUT); |
| 1647 | #undef PIS |
| 1648 | |
| 1649 | #define PIS(x) \ |
| 1650 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ |
| 1651 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1652 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1653 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1654 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); |
| 1655 | |
| 1656 | seq_printf(s, "-- VC interrupts --\n"); |
| 1657 | PIS(CS); |
| 1658 | PIS(ECC_CORR); |
| 1659 | PIS(PACKET_SENT); |
| 1660 | PIS(FIFO_TX_OVF); |
| 1661 | PIS(FIFO_RX_OVF); |
| 1662 | PIS(BTA); |
| 1663 | PIS(ECC_NO_CORR); |
| 1664 | PIS(FIFO_TX_UDF); |
| 1665 | PIS(PP_BUSY_CHANGE); |
| 1666 | #undef PIS |
| 1667 | |
| 1668 | #define PIS(x) \ |
| 1669 | seq_printf(s, "%-20s %10d\n", #x, \ |
| 1670 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); |
| 1671 | |
| 1672 | seq_printf(s, "-- CIO interrupts --\n"); |
| 1673 | PIS(ERRSYNCESC1); |
| 1674 | PIS(ERRSYNCESC2); |
| 1675 | PIS(ERRSYNCESC3); |
| 1676 | PIS(ERRESC1); |
| 1677 | PIS(ERRESC2); |
| 1678 | PIS(ERRESC3); |
| 1679 | PIS(ERRCONTROL1); |
| 1680 | PIS(ERRCONTROL2); |
| 1681 | PIS(ERRCONTROL3); |
| 1682 | PIS(STATEULPS1); |
| 1683 | PIS(STATEULPS2); |
| 1684 | PIS(STATEULPS3); |
| 1685 | PIS(ERRCONTENTIONLP0_1); |
| 1686 | PIS(ERRCONTENTIONLP1_1); |
| 1687 | PIS(ERRCONTENTIONLP0_2); |
| 1688 | PIS(ERRCONTENTIONLP1_2); |
| 1689 | PIS(ERRCONTENTIONLP0_3); |
| 1690 | PIS(ERRCONTENTIONLP1_3); |
| 1691 | PIS(ULPSACTIVENOT_ALL0); |
| 1692 | PIS(ULPSACTIVENOT_ALL1); |
| 1693 | #undef PIS |
| 1694 | } |
| 1695 | #endif |
| 1696 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1697 | void dsi_dump_regs(struct seq_file *s) |
| 1698 | { |
| 1699 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r)) |
| 1700 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1701 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1702 | |
| 1703 | DUMPREG(DSI_REVISION); |
| 1704 | DUMPREG(DSI_SYSCONFIG); |
| 1705 | DUMPREG(DSI_SYSSTATUS); |
| 1706 | DUMPREG(DSI_IRQSTATUS); |
| 1707 | DUMPREG(DSI_IRQENABLE); |
| 1708 | DUMPREG(DSI_CTRL); |
| 1709 | DUMPREG(DSI_COMPLEXIO_CFG1); |
| 1710 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); |
| 1711 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); |
| 1712 | DUMPREG(DSI_CLK_CTRL); |
| 1713 | DUMPREG(DSI_TIMING1); |
| 1714 | DUMPREG(DSI_TIMING2); |
| 1715 | DUMPREG(DSI_VM_TIMING1); |
| 1716 | DUMPREG(DSI_VM_TIMING2); |
| 1717 | DUMPREG(DSI_VM_TIMING3); |
| 1718 | DUMPREG(DSI_CLK_TIMING); |
| 1719 | DUMPREG(DSI_TX_FIFO_VC_SIZE); |
| 1720 | DUMPREG(DSI_RX_FIFO_VC_SIZE); |
| 1721 | DUMPREG(DSI_COMPLEXIO_CFG2); |
| 1722 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); |
| 1723 | DUMPREG(DSI_VM_TIMING4); |
| 1724 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); |
| 1725 | DUMPREG(DSI_VM_TIMING5); |
| 1726 | DUMPREG(DSI_VM_TIMING6); |
| 1727 | DUMPREG(DSI_VM_TIMING7); |
| 1728 | DUMPREG(DSI_STOPCLK_TIMING); |
| 1729 | |
| 1730 | DUMPREG(DSI_VC_CTRL(0)); |
| 1731 | DUMPREG(DSI_VC_TE(0)); |
| 1732 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); |
| 1733 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); |
| 1734 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); |
| 1735 | DUMPREG(DSI_VC_IRQSTATUS(0)); |
| 1736 | DUMPREG(DSI_VC_IRQENABLE(0)); |
| 1737 | |
| 1738 | DUMPREG(DSI_VC_CTRL(1)); |
| 1739 | DUMPREG(DSI_VC_TE(1)); |
| 1740 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); |
| 1741 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); |
| 1742 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); |
| 1743 | DUMPREG(DSI_VC_IRQSTATUS(1)); |
| 1744 | DUMPREG(DSI_VC_IRQENABLE(1)); |
| 1745 | |
| 1746 | DUMPREG(DSI_VC_CTRL(2)); |
| 1747 | DUMPREG(DSI_VC_TE(2)); |
| 1748 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); |
| 1749 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); |
| 1750 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); |
| 1751 | DUMPREG(DSI_VC_IRQSTATUS(2)); |
| 1752 | DUMPREG(DSI_VC_IRQENABLE(2)); |
| 1753 | |
| 1754 | DUMPREG(DSI_VC_CTRL(3)); |
| 1755 | DUMPREG(DSI_VC_TE(3)); |
| 1756 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); |
| 1757 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); |
| 1758 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); |
| 1759 | DUMPREG(DSI_VC_IRQSTATUS(3)); |
| 1760 | DUMPREG(DSI_VC_IRQENABLE(3)); |
| 1761 | |
| 1762 | DUMPREG(DSI_DSIPHY_CFG0); |
| 1763 | DUMPREG(DSI_DSIPHY_CFG1); |
| 1764 | DUMPREG(DSI_DSIPHY_CFG2); |
| 1765 | DUMPREG(DSI_DSIPHY_CFG5); |
| 1766 | |
| 1767 | DUMPREG(DSI_PLL_CONTROL); |
| 1768 | DUMPREG(DSI_PLL_STATUS); |
| 1769 | DUMPREG(DSI_PLL_GO); |
| 1770 | DUMPREG(DSI_PLL_CONFIGURATION1); |
| 1771 | DUMPREG(DSI_PLL_CONFIGURATION2); |
| 1772 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1773 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1774 | #undef DUMPREG |
| 1775 | } |
| 1776 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 1777 | enum dsi_cio_power_state { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1778 | DSI_COMPLEXIO_POWER_OFF = 0x0, |
| 1779 | DSI_COMPLEXIO_POWER_ON = 0x1, |
| 1780 | DSI_COMPLEXIO_POWER_ULPS = 0x2, |
| 1781 | }; |
| 1782 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 1783 | static int dsi_cio_power(enum dsi_cio_power_state state) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1784 | { |
| 1785 | int t = 0; |
| 1786 | |
| 1787 | /* PWR_CMD */ |
| 1788 | REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27); |
| 1789 | |
| 1790 | /* PWR_STATUS */ |
| 1791 | while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1792 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1793 | DSSERR("failed to set complexio power state to " |
| 1794 | "%d\n", state); |
| 1795 | return -ENODEV; |
| 1796 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1797 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1798 | } |
| 1799 | |
| 1800 | return 0; |
| 1801 | } |
| 1802 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 1803 | static void dsi_set_lane_config(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1804 | { |
| 1805 | u32 r; |
| 1806 | |
| 1807 | int clk_lane = dssdev->phy.dsi.clk_lane; |
| 1808 | int data1_lane = dssdev->phy.dsi.data1_lane; |
| 1809 | int data2_lane = dssdev->phy.dsi.data2_lane; |
| 1810 | int clk_pol = dssdev->phy.dsi.clk_pol; |
| 1811 | int data1_pol = dssdev->phy.dsi.data1_pol; |
| 1812 | int data2_pol = dssdev->phy.dsi.data2_pol; |
| 1813 | |
| 1814 | r = dsi_read_reg(DSI_COMPLEXIO_CFG1); |
| 1815 | r = FLD_MOD(r, clk_lane, 2, 0); |
| 1816 | r = FLD_MOD(r, clk_pol, 3, 3); |
| 1817 | r = FLD_MOD(r, data1_lane, 6, 4); |
| 1818 | r = FLD_MOD(r, data1_pol, 7, 7); |
| 1819 | r = FLD_MOD(r, data2_lane, 10, 8); |
| 1820 | r = FLD_MOD(r, data2_pol, 11, 11); |
| 1821 | dsi_write_reg(DSI_COMPLEXIO_CFG1, r); |
| 1822 | |
| 1823 | /* The configuration of the DSI complex I/O (number of data lanes, |
| 1824 | position, differential order) should not be changed while |
| 1825 | DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for |
| 1826 | the hardware to take into account a new configuration of the complex |
| 1827 | I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to |
| 1828 | follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, |
| 1829 | then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set |
| 1830 | DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the |
| 1831 | DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the |
| 1832 | DSI complex I/O configuration is unknown. */ |
| 1833 | |
| 1834 | /* |
| 1835 | REG_FLD_MOD(DSI_CTRL, 1, 0, 0); |
| 1836 | REG_FLD_MOD(DSI_CTRL, 0, 0, 0); |
| 1837 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); |
| 1838 | REG_FLD_MOD(DSI_CTRL, 1, 0, 0); |
| 1839 | */ |
| 1840 | } |
| 1841 | |
| 1842 | static inline unsigned ns2ddr(unsigned ns) |
| 1843 | { |
| 1844 | /* convert time in ns to ddr ticks, rounding up */ |
| 1845 | unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4; |
| 1846 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; |
| 1847 | } |
| 1848 | |
| 1849 | static inline unsigned ddr2ns(unsigned ddr) |
| 1850 | { |
| 1851 | unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4; |
| 1852 | return ddr * 1000 * 1000 / (ddr_clk / 1000); |
| 1853 | } |
| 1854 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 1855 | static void dsi_cio_timings(void) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1856 | { |
| 1857 | u32 r; |
| 1858 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; |
| 1859 | u32 tlpx_half, tclk_trail, tclk_zero; |
| 1860 | u32 tclk_prepare; |
| 1861 | |
| 1862 | /* calculate timings */ |
| 1863 | |
| 1864 | /* 1 * DDR_CLK = 2 * UI */ |
| 1865 | |
| 1866 | /* min 40ns + 4*UI max 85ns + 6*UI */ |
| 1867 | ths_prepare = ns2ddr(70) + 2; |
| 1868 | |
| 1869 | /* min 145ns + 10*UI */ |
| 1870 | ths_prepare_ths_zero = ns2ddr(175) + 2; |
| 1871 | |
| 1872 | /* min max(8*UI, 60ns+4*UI) */ |
| 1873 | ths_trail = ns2ddr(60) + 5; |
| 1874 | |
| 1875 | /* min 100ns */ |
| 1876 | ths_exit = ns2ddr(145); |
| 1877 | |
| 1878 | /* tlpx min 50n */ |
| 1879 | tlpx_half = ns2ddr(25); |
| 1880 | |
| 1881 | /* min 60ns */ |
| 1882 | tclk_trail = ns2ddr(60) + 2; |
| 1883 | |
| 1884 | /* min 38ns, max 95ns */ |
| 1885 | tclk_prepare = ns2ddr(65); |
| 1886 | |
| 1887 | /* min tclk-prepare + tclk-zero = 300ns */ |
| 1888 | tclk_zero = ns2ddr(260); |
| 1889 | |
| 1890 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", |
| 1891 | ths_prepare, ddr2ns(ths_prepare), |
| 1892 | ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero)); |
| 1893 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", |
| 1894 | ths_trail, ddr2ns(ths_trail), |
| 1895 | ths_exit, ddr2ns(ths_exit)); |
| 1896 | |
| 1897 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " |
| 1898 | "tclk_zero %u (%uns)\n", |
| 1899 | tlpx_half, ddr2ns(tlpx_half), |
| 1900 | tclk_trail, ddr2ns(tclk_trail), |
| 1901 | tclk_zero, ddr2ns(tclk_zero)); |
| 1902 | DSSDBG("tclk_prepare %u (%uns)\n", |
| 1903 | tclk_prepare, ddr2ns(tclk_prepare)); |
| 1904 | |
| 1905 | /* program timings */ |
| 1906 | |
| 1907 | r = dsi_read_reg(DSI_DSIPHY_CFG0); |
| 1908 | r = FLD_MOD(r, ths_prepare, 31, 24); |
| 1909 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); |
| 1910 | r = FLD_MOD(r, ths_trail, 15, 8); |
| 1911 | r = FLD_MOD(r, ths_exit, 7, 0); |
| 1912 | dsi_write_reg(DSI_DSIPHY_CFG0, r); |
| 1913 | |
| 1914 | r = dsi_read_reg(DSI_DSIPHY_CFG1); |
| 1915 | r = FLD_MOD(r, tlpx_half, 22, 16); |
| 1916 | r = FLD_MOD(r, tclk_trail, 15, 8); |
| 1917 | r = FLD_MOD(r, tclk_zero, 7, 0); |
| 1918 | dsi_write_reg(DSI_DSIPHY_CFG1, r); |
| 1919 | |
| 1920 | r = dsi_read_reg(DSI_DSIPHY_CFG2); |
| 1921 | r = FLD_MOD(r, tclk_prepare, 7, 0); |
| 1922 | dsi_write_reg(DSI_DSIPHY_CFG2, r); |
| 1923 | } |
| 1924 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 1925 | static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 1926 | enum dsi_lane lanes) |
| 1927 | { |
| 1928 | int clk_lane = dssdev->phy.dsi.clk_lane; |
| 1929 | int data1_lane = dssdev->phy.dsi.data1_lane; |
| 1930 | int data2_lane = dssdev->phy.dsi.data2_lane; |
| 1931 | int clk_pol = dssdev->phy.dsi.clk_pol; |
| 1932 | int data1_pol = dssdev->phy.dsi.data1_pol; |
| 1933 | int data2_pol = dssdev->phy.dsi.data2_pol; |
| 1934 | |
| 1935 | u32 l = 0; |
| 1936 | |
| 1937 | if (lanes & DSI_CLK_P) |
| 1938 | l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1)); |
| 1939 | if (lanes & DSI_CLK_N) |
| 1940 | l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0)); |
| 1941 | |
| 1942 | if (lanes & DSI_DATA1_P) |
| 1943 | l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1)); |
| 1944 | if (lanes & DSI_DATA1_N) |
| 1945 | l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0)); |
| 1946 | |
| 1947 | if (lanes & DSI_DATA2_P) |
| 1948 | l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1)); |
| 1949 | if (lanes & DSI_DATA2_N) |
| 1950 | l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0)); |
| 1951 | |
| 1952 | /* |
| 1953 | * Bits in REGLPTXSCPDAT4TO0DXDY: |
| 1954 | * 17: DY0 18: DX0 |
| 1955 | * 19: DY1 20: DX1 |
| 1956 | * 21: DY2 22: DX2 |
| 1957 | */ |
| 1958 | |
| 1959 | /* Set the lane override configuration */ |
| 1960 | REG_FLD_MOD(DSI_DSIPHY_CFG10, l, 22, 17); /* REGLPTXSCPDAT4TO0DXDY */ |
| 1961 | |
| 1962 | /* Enable lane override */ |
| 1963 | REG_FLD_MOD(DSI_DSIPHY_CFG10, 1, 27, 27); /* ENLPTXSCPDAT */ |
| 1964 | } |
| 1965 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 1966 | static void dsi_cio_disable_lane_override(void) |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 1967 | { |
| 1968 | /* Disable lane override */ |
| 1969 | REG_FLD_MOD(DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ |
| 1970 | /* Reset the lane override configuration */ |
| 1971 | REG_FLD_MOD(DSI_DSIPHY_CFG10, 0, 22, 17); /* REGLPTXSCPDAT4TO0DXDY */ |
| 1972 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1973 | |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 1974 | static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev) |
| 1975 | { |
| 1976 | int t; |
| 1977 | int bits[3]; |
| 1978 | bool in_use[3]; |
| 1979 | |
| 1980 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { |
| 1981 | bits[0] = 28; |
| 1982 | bits[1] = 27; |
| 1983 | bits[2] = 26; |
| 1984 | } else { |
| 1985 | bits[0] = 24; |
| 1986 | bits[1] = 25; |
| 1987 | bits[2] = 26; |
| 1988 | } |
| 1989 | |
| 1990 | in_use[0] = false; |
| 1991 | in_use[1] = false; |
| 1992 | in_use[2] = false; |
| 1993 | |
| 1994 | if (dssdev->phy.dsi.clk_lane != 0) |
| 1995 | in_use[dssdev->phy.dsi.clk_lane - 1] = true; |
| 1996 | if (dssdev->phy.dsi.data1_lane != 0) |
| 1997 | in_use[dssdev->phy.dsi.data1_lane - 1] = true; |
| 1998 | if (dssdev->phy.dsi.data2_lane != 0) |
| 1999 | in_use[dssdev->phy.dsi.data2_lane - 1] = true; |
| 2000 | |
| 2001 | t = 100000; |
| 2002 | while (true) { |
| 2003 | u32 l; |
| 2004 | int i; |
| 2005 | int ok; |
| 2006 | |
| 2007 | l = dsi_read_reg(DSI_DSIPHY_CFG5); |
| 2008 | |
| 2009 | ok = 0; |
| 2010 | for (i = 0; i < 3; ++i) { |
| 2011 | if (!in_use[i] || (l & (1 << bits[i]))) |
| 2012 | ok++; |
| 2013 | } |
| 2014 | |
| 2015 | if (ok == 3) |
| 2016 | break; |
| 2017 | |
| 2018 | if (--t == 0) { |
| 2019 | for (i = 0; i < 3; ++i) { |
| 2020 | if (!in_use[i] || (l & (1 << bits[i]))) |
| 2021 | continue; |
| 2022 | |
| 2023 | DSSERR("CIO TXCLKESC%d domain not coming " \ |
| 2024 | "out of reset\n", i); |
| 2025 | } |
| 2026 | return -EIO; |
| 2027 | } |
| 2028 | } |
| 2029 | |
| 2030 | return 0; |
| 2031 | } |
| 2032 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2033 | static int dsi_cio_init(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2034 | { |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2035 | int r; |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2036 | u32 l; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2037 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2038 | DSSDBGF(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2039 | |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 2040 | if (dsi.dsi_mux_pads) |
| 2041 | dsi.dsi_mux_pads(true); |
| 2042 | |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2043 | dsi_enable_scp_clk(); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2044 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2045 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 2046 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 2047 | * I/O. */ |
| 2048 | dsi_read_reg(DSI_DSIPHY_CFG5); |
| 2049 | |
| 2050 | if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) { |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2051 | DSSERR("CIO SCP Clock domain not coming out of reset.\n"); |
| 2052 | r = -EIO; |
| 2053 | goto err_scp_clk_dom; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2054 | } |
| 2055 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2056 | dsi_set_lane_config(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2057 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2058 | /* set TX STOP MODE timer to maximum for this operation */ |
| 2059 | l = dsi_read_reg(DSI_TIMING1); |
| 2060 | l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
| 2061 | l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ |
| 2062 | l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ |
| 2063 | l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ |
| 2064 | dsi_write_reg(DSI_TIMING1, l); |
| 2065 | |
| 2066 | if (dsi.ulps_enabled) { |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2067 | DSSDBG("manual ulps exit\n"); |
| 2068 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2069 | /* ULPS is exited by Mark-1 state for 1ms, followed by |
| 2070 | * stop state. DSS HW cannot do this via the normal |
| 2071 | * ULPS exit sequence, as after reset the DSS HW thinks |
| 2072 | * that we are not in ULPS mode, and refuses to send the |
| 2073 | * sequence. So we need to send the ULPS exit sequence |
| 2074 | * manually. |
| 2075 | */ |
| 2076 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2077 | dsi_cio_enable_lane_override(dssdev, |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2078 | DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P); |
| 2079 | } |
| 2080 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2081 | r = dsi_cio_power(DSI_COMPLEXIO_POWER_ON); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2082 | if (r) |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2083 | goto err_cio_pwr; |
| 2084 | |
| 2085 | if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) { |
| 2086 | DSSERR("CIO PWR clock domain not coming out of reset.\n"); |
| 2087 | r = -ENODEV; |
| 2088 | goto err_cio_pwr_dom; |
| 2089 | } |
| 2090 | |
| 2091 | dsi_if_enable(true); |
| 2092 | dsi_if_enable(false); |
| 2093 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2094 | |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2095 | r = dsi_cio_wait_tx_clk_esc_reset(dssdev); |
| 2096 | if (r) |
| 2097 | goto err_tx_clk_esc_rst; |
| 2098 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2099 | if (dsi.ulps_enabled) { |
| 2100 | /* Keep Mark-1 state for 1ms (as per DSI spec) */ |
| 2101 | ktime_t wait = ns_to_ktime(1000 * 1000); |
| 2102 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 2103 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); |
| 2104 | |
| 2105 | /* Disable the override. The lanes should be set to Mark-11 |
| 2106 | * state by the HW */ |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2107 | dsi_cio_disable_lane_override(); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2108 | } |
| 2109 | |
| 2110 | /* FORCE_TX_STOP_MODE_IO */ |
| 2111 | REG_FLD_MOD(DSI_TIMING1, 0, 15, 15); |
| 2112 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2113 | dsi_cio_timings(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2114 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2115 | dsi.ulps_enabled = false; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2116 | |
| 2117 | DSSDBG("CIO init done\n"); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2118 | |
| 2119 | return 0; |
| 2120 | |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2121 | err_tx_clk_esc_rst: |
| 2122 | REG_FLD_MOD(DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2123 | err_cio_pwr_dom: |
| 2124 | dsi_cio_power(DSI_COMPLEXIO_POWER_OFF); |
| 2125 | err_cio_pwr: |
| 2126 | if (dsi.ulps_enabled) |
| 2127 | dsi_cio_disable_lane_override(); |
| 2128 | err_scp_clk_dom: |
| 2129 | dsi_disable_scp_clk(); |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 2130 | if (dsi.dsi_mux_pads) |
| 2131 | dsi.dsi_mux_pads(false); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2132 | return r; |
| 2133 | } |
| 2134 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2135 | static void dsi_cio_uninit(void) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2136 | { |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2137 | dsi_cio_power(DSI_COMPLEXIO_POWER_OFF); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2138 | dsi_disable_scp_clk(); |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 2139 | if (dsi.dsi_mux_pads) |
| 2140 | dsi.dsi_mux_pads(false); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2141 | } |
| 2142 | |
| 2143 | static int _dsi_wait_reset(void) |
| 2144 | { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 2145 | int t = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2146 | |
| 2147 | while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 2148 | if (++t > 5) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2149 | DSSERR("soft reset failed\n"); |
| 2150 | return -ENODEV; |
| 2151 | } |
| 2152 | udelay(1); |
| 2153 | } |
| 2154 | |
| 2155 | return 0; |
| 2156 | } |
| 2157 | |
| 2158 | static int _dsi_reset(void) |
| 2159 | { |
| 2160 | /* Soft reset */ |
| 2161 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1); |
| 2162 | return _dsi_wait_reset(); |
| 2163 | } |
| 2164 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2165 | static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2, |
| 2166 | enum fifo_size size3, enum fifo_size size4) |
| 2167 | { |
| 2168 | u32 r = 0; |
| 2169 | int add = 0; |
| 2170 | int i; |
| 2171 | |
| 2172 | dsi.vc[0].fifo_size = size1; |
| 2173 | dsi.vc[1].fifo_size = size2; |
| 2174 | dsi.vc[2].fifo_size = size3; |
| 2175 | dsi.vc[3].fifo_size = size4; |
| 2176 | |
| 2177 | for (i = 0; i < 4; i++) { |
| 2178 | u8 v; |
| 2179 | int size = dsi.vc[i].fifo_size; |
| 2180 | |
| 2181 | if (add + size > 4) { |
| 2182 | DSSERR("Illegal FIFO configuration\n"); |
| 2183 | BUG(); |
| 2184 | } |
| 2185 | |
| 2186 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 2187 | r |= v << (8 * i); |
| 2188 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 2189 | add += size; |
| 2190 | } |
| 2191 | |
| 2192 | dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r); |
| 2193 | } |
| 2194 | |
| 2195 | static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2, |
| 2196 | enum fifo_size size3, enum fifo_size size4) |
| 2197 | { |
| 2198 | u32 r = 0; |
| 2199 | int add = 0; |
| 2200 | int i; |
| 2201 | |
| 2202 | dsi.vc[0].fifo_size = size1; |
| 2203 | dsi.vc[1].fifo_size = size2; |
| 2204 | dsi.vc[2].fifo_size = size3; |
| 2205 | dsi.vc[3].fifo_size = size4; |
| 2206 | |
| 2207 | for (i = 0; i < 4; i++) { |
| 2208 | u8 v; |
| 2209 | int size = dsi.vc[i].fifo_size; |
| 2210 | |
| 2211 | if (add + size > 4) { |
| 2212 | DSSERR("Illegal FIFO configuration\n"); |
| 2213 | BUG(); |
| 2214 | } |
| 2215 | |
| 2216 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 2217 | r |= v << (8 * i); |
| 2218 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 2219 | add += size; |
| 2220 | } |
| 2221 | |
| 2222 | dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r); |
| 2223 | } |
| 2224 | |
| 2225 | static int dsi_force_tx_stop_mode_io(void) |
| 2226 | { |
| 2227 | u32 r; |
| 2228 | |
| 2229 | r = dsi_read_reg(DSI_TIMING1); |
| 2230 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
| 2231 | dsi_write_reg(DSI_TIMING1, r); |
| 2232 | |
| 2233 | if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) { |
| 2234 | DSSERR("TX_STOP bit not going down\n"); |
| 2235 | return -EIO; |
| 2236 | } |
| 2237 | |
| 2238 | return 0; |
| 2239 | } |
| 2240 | |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2241 | static bool dsi_vc_is_enabled(int channel) |
| 2242 | { |
| 2243 | return REG_GET(DSI_VC_CTRL(channel), 0, 0); |
| 2244 | } |
| 2245 | |
| 2246 | static void dsi_packet_sent_handler_vp(void *data, u32 mask) |
| 2247 | { |
| 2248 | const int channel = dsi.update_channel; |
| 2249 | u8 bit = dsi.te_enabled ? 30 : 31; |
| 2250 | |
| 2251 | if (REG_GET(DSI_VC_TE(channel), bit, bit) == 0) |
| 2252 | complete((struct completion *)data); |
| 2253 | } |
| 2254 | |
| 2255 | static int dsi_sync_vc_vp(int channel) |
| 2256 | { |
| 2257 | int r = 0; |
| 2258 | u8 bit; |
| 2259 | |
| 2260 | DECLARE_COMPLETION_ONSTACK(completion); |
| 2261 | |
| 2262 | bit = dsi.te_enabled ? 30 : 31; |
| 2263 | |
| 2264 | r = dsi_register_isr_vc(channel, dsi_packet_sent_handler_vp, |
| 2265 | &completion, DSI_VC_IRQ_PACKET_SENT); |
| 2266 | if (r) |
| 2267 | goto err0; |
| 2268 | |
| 2269 | /* Wait for completion only if TE_EN/TE_START is still set */ |
| 2270 | if (REG_GET(DSI_VC_TE(channel), bit, bit)) { |
| 2271 | if (wait_for_completion_timeout(&completion, |
| 2272 | msecs_to_jiffies(10)) == 0) { |
| 2273 | DSSERR("Failed to complete previous frame transfer\n"); |
| 2274 | r = -EIO; |
| 2275 | goto err1; |
| 2276 | } |
| 2277 | } |
| 2278 | |
| 2279 | dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_vp, |
| 2280 | &completion, DSI_VC_IRQ_PACKET_SENT); |
| 2281 | |
| 2282 | return 0; |
| 2283 | err1: |
| 2284 | dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_vp, &completion, |
| 2285 | DSI_VC_IRQ_PACKET_SENT); |
| 2286 | err0: |
| 2287 | return r; |
| 2288 | } |
| 2289 | |
| 2290 | static void dsi_packet_sent_handler_l4(void *data, u32 mask) |
| 2291 | { |
| 2292 | const int channel = dsi.update_channel; |
| 2293 | |
| 2294 | if (REG_GET(DSI_VC_CTRL(channel), 5, 5) == 0) |
| 2295 | complete((struct completion *)data); |
| 2296 | } |
| 2297 | |
| 2298 | static int dsi_sync_vc_l4(int channel) |
| 2299 | { |
| 2300 | int r = 0; |
| 2301 | |
| 2302 | DECLARE_COMPLETION_ONSTACK(completion); |
| 2303 | |
| 2304 | r = dsi_register_isr_vc(channel, dsi_packet_sent_handler_l4, |
| 2305 | &completion, DSI_VC_IRQ_PACKET_SENT); |
| 2306 | if (r) |
| 2307 | goto err0; |
| 2308 | |
| 2309 | /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ |
| 2310 | if (REG_GET(DSI_VC_CTRL(channel), 5, 5)) { |
| 2311 | if (wait_for_completion_timeout(&completion, |
| 2312 | msecs_to_jiffies(10)) == 0) { |
| 2313 | DSSERR("Failed to complete previous l4 transfer\n"); |
| 2314 | r = -EIO; |
| 2315 | goto err1; |
| 2316 | } |
| 2317 | } |
| 2318 | |
| 2319 | dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_l4, |
| 2320 | &completion, DSI_VC_IRQ_PACKET_SENT); |
| 2321 | |
| 2322 | return 0; |
| 2323 | err1: |
| 2324 | dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_l4, |
| 2325 | &completion, DSI_VC_IRQ_PACKET_SENT); |
| 2326 | err0: |
| 2327 | return r; |
| 2328 | } |
| 2329 | |
| 2330 | static int dsi_sync_vc(int channel) |
| 2331 | { |
| 2332 | WARN_ON(!dsi_bus_is_locked()); |
| 2333 | |
| 2334 | WARN_ON(in_interrupt()); |
| 2335 | |
| 2336 | if (!dsi_vc_is_enabled(channel)) |
| 2337 | return 0; |
| 2338 | |
| 2339 | switch (dsi.vc[channel].mode) { |
| 2340 | case DSI_VC_MODE_VP: |
| 2341 | return dsi_sync_vc_vp(channel); |
| 2342 | case DSI_VC_MODE_L4: |
| 2343 | return dsi_sync_vc_l4(channel); |
| 2344 | default: |
| 2345 | BUG(); |
| 2346 | } |
| 2347 | } |
| 2348 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2349 | static int dsi_vc_enable(int channel, bool enable) |
| 2350 | { |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 2351 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
| 2352 | channel, enable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2353 | |
| 2354 | enable = enable ? 1 : 0; |
| 2355 | |
| 2356 | REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0); |
| 2357 | |
| 2358 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) { |
| 2359 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); |
| 2360 | return -EIO; |
| 2361 | } |
| 2362 | |
| 2363 | return 0; |
| 2364 | } |
| 2365 | |
| 2366 | static void dsi_vc_initial_config(int channel) |
| 2367 | { |
| 2368 | u32 r; |
| 2369 | |
| 2370 | DSSDBGF("%d", channel); |
| 2371 | |
| 2372 | r = dsi_read_reg(DSI_VC_CTRL(channel)); |
| 2373 | |
| 2374 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ |
| 2375 | DSSERR("VC(%d) busy when trying to configure it!\n", |
| 2376 | channel); |
| 2377 | |
| 2378 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ |
| 2379 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ |
| 2380 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ |
| 2381 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ |
| 2382 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ |
| 2383 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ |
| 2384 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2385 | if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) |
| 2386 | r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2387 | |
| 2388 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ |
| 2389 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ |
| 2390 | |
| 2391 | dsi_write_reg(DSI_VC_CTRL(channel), r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2392 | } |
| 2393 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2394 | static int dsi_vc_config_l4(int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2395 | { |
| 2396 | if (dsi.vc[channel].mode == DSI_VC_MODE_L4) |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2397 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2398 | |
| 2399 | DSSDBGF("%d", channel); |
| 2400 | |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2401 | dsi_sync_vc(channel); |
| 2402 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2403 | dsi_vc_enable(channel, 0); |
| 2404 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2405 | /* VC_BUSY */ |
| 2406 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2407 | DSSERR("vc(%d) busy when trying to config for L4\n", channel); |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2408 | return -EIO; |
| 2409 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2410 | |
| 2411 | REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */ |
| 2412 | |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2413 | /* DCS_CMD_ENABLE */ |
| 2414 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) |
| 2415 | REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 30, 30); |
| 2416 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2417 | dsi_vc_enable(channel, 1); |
| 2418 | |
| 2419 | dsi.vc[channel].mode = DSI_VC_MODE_L4; |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2420 | |
| 2421 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2422 | } |
| 2423 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2424 | static int dsi_vc_config_vp(int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2425 | { |
| 2426 | if (dsi.vc[channel].mode == DSI_VC_MODE_VP) |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2427 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2428 | |
| 2429 | DSSDBGF("%d", channel); |
| 2430 | |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2431 | dsi_sync_vc(channel); |
| 2432 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2433 | dsi_vc_enable(channel, 0); |
| 2434 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2435 | /* VC_BUSY */ |
| 2436 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2437 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2438 | return -EIO; |
| 2439 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2440 | |
| 2441 | REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */ |
| 2442 | |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2443 | /* DCS_CMD_ENABLE */ |
| 2444 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) |
| 2445 | REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 30, 30); |
| 2446 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2447 | dsi_vc_enable(channel, 1); |
| 2448 | |
| 2449 | dsi.vc[channel].mode = DSI_VC_MODE_VP; |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2450 | |
| 2451 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2452 | } |
| 2453 | |
| 2454 | |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 2455 | void omapdss_dsi_vc_enable_hs(int channel, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2456 | { |
| 2457 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); |
| 2458 | |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 2459 | WARN_ON(!dsi_bus_is_locked()); |
| 2460 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2461 | dsi_vc_enable(channel, 0); |
| 2462 | dsi_if_enable(0); |
| 2463 | |
| 2464 | REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9); |
| 2465 | |
| 2466 | dsi_vc_enable(channel, 1); |
| 2467 | dsi_if_enable(1); |
| 2468 | |
| 2469 | dsi_force_tx_stop_mode_io(); |
| 2470 | } |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 2471 | EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2472 | |
| 2473 | static void dsi_vc_flush_long_data(int channel) |
| 2474 | { |
| 2475 | while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { |
| 2476 | u32 val; |
| 2477 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
| 2478 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", |
| 2479 | (val >> 0) & 0xff, |
| 2480 | (val >> 8) & 0xff, |
| 2481 | (val >> 16) & 0xff, |
| 2482 | (val >> 24) & 0xff); |
| 2483 | } |
| 2484 | } |
| 2485 | |
| 2486 | static void dsi_show_rx_ack_with_err(u16 err) |
| 2487 | { |
| 2488 | DSSERR("\tACK with ERROR (%#x):\n", err); |
| 2489 | if (err & (1 << 0)) |
| 2490 | DSSERR("\t\tSoT Error\n"); |
| 2491 | if (err & (1 << 1)) |
| 2492 | DSSERR("\t\tSoT Sync Error\n"); |
| 2493 | if (err & (1 << 2)) |
| 2494 | DSSERR("\t\tEoT Sync Error\n"); |
| 2495 | if (err & (1 << 3)) |
| 2496 | DSSERR("\t\tEscape Mode Entry Command Error\n"); |
| 2497 | if (err & (1 << 4)) |
| 2498 | DSSERR("\t\tLP Transmit Sync Error\n"); |
| 2499 | if (err & (1 << 5)) |
| 2500 | DSSERR("\t\tHS Receive Timeout Error\n"); |
| 2501 | if (err & (1 << 6)) |
| 2502 | DSSERR("\t\tFalse Control Error\n"); |
| 2503 | if (err & (1 << 7)) |
| 2504 | DSSERR("\t\t(reserved7)\n"); |
| 2505 | if (err & (1 << 8)) |
| 2506 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); |
| 2507 | if (err & (1 << 9)) |
| 2508 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); |
| 2509 | if (err & (1 << 10)) |
| 2510 | DSSERR("\t\tChecksum Error\n"); |
| 2511 | if (err & (1 << 11)) |
| 2512 | DSSERR("\t\tData type not recognized\n"); |
| 2513 | if (err & (1 << 12)) |
| 2514 | DSSERR("\t\tInvalid VC ID\n"); |
| 2515 | if (err & (1 << 13)) |
| 2516 | DSSERR("\t\tInvalid Transmission Length\n"); |
| 2517 | if (err & (1 << 14)) |
| 2518 | DSSERR("\t\t(reserved14)\n"); |
| 2519 | if (err & (1 << 15)) |
| 2520 | DSSERR("\t\tDSI Protocol Violation\n"); |
| 2521 | } |
| 2522 | |
| 2523 | static u16 dsi_vc_flush_receive_data(int channel) |
| 2524 | { |
| 2525 | /* RX_FIFO_NOT_EMPTY */ |
| 2526 | while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { |
| 2527 | u32 val; |
| 2528 | u8 dt; |
| 2529 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2530 | DSSERR("\trawval %#08x\n", val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2531 | dt = FLD_GET(val, 5, 0); |
| 2532 | if (dt == DSI_DT_RX_ACK_WITH_ERR) { |
| 2533 | u16 err = FLD_GET(val, 23, 8); |
| 2534 | dsi_show_rx_ack_with_err(err); |
| 2535 | } else if (dt == DSI_DT_RX_SHORT_READ_1) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2536 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2537 | FLD_GET(val, 23, 8)); |
| 2538 | } else if (dt == DSI_DT_RX_SHORT_READ_2) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2539 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2540 | FLD_GET(val, 23, 8)); |
| 2541 | } else if (dt == DSI_DT_RX_DCS_LONG_READ) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2542 | DSSERR("\tDCS long response, len %d\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2543 | FLD_GET(val, 23, 8)); |
| 2544 | dsi_vc_flush_long_data(channel); |
| 2545 | } else { |
| 2546 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
| 2547 | } |
| 2548 | } |
| 2549 | return 0; |
| 2550 | } |
| 2551 | |
| 2552 | static int dsi_vc_send_bta(int channel) |
| 2553 | { |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 2554 | if (dsi.debug_write || dsi.debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2555 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
| 2556 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 2557 | WARN_ON(!dsi_bus_is_locked()); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2558 | |
| 2559 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */ |
| 2560 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); |
| 2561 | dsi_vc_flush_receive_data(channel); |
| 2562 | } |
| 2563 | |
| 2564 | REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ |
| 2565 | |
| 2566 | return 0; |
| 2567 | } |
| 2568 | |
| 2569 | int dsi_vc_send_bta_sync(int channel) |
| 2570 | { |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2571 | DECLARE_COMPLETION_ONSTACK(completion); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2572 | int r = 0; |
| 2573 | u32 err; |
| 2574 | |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2575 | r = dsi_register_isr_vc(channel, dsi_completion_handler, |
| 2576 | &completion, DSI_VC_IRQ_BTA); |
| 2577 | if (r) |
| 2578 | goto err0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2579 | |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2580 | r = dsi_register_isr(dsi_completion_handler, &completion, |
| 2581 | DSI_IRQ_ERROR_MASK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2582 | if (r) |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2583 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2584 | |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2585 | r = dsi_vc_send_bta(channel); |
| 2586 | if (r) |
| 2587 | goto err2; |
| 2588 | |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2589 | if (wait_for_completion_timeout(&completion, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2590 | msecs_to_jiffies(500)) == 0) { |
| 2591 | DSSERR("Failed to receive BTA\n"); |
| 2592 | r = -EIO; |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2593 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2594 | } |
| 2595 | |
| 2596 | err = dsi_get_errors(); |
| 2597 | if (err) { |
| 2598 | DSSERR("Error while sending BTA: %x\n", err); |
| 2599 | r = -EIO; |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2600 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2601 | } |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2602 | err2: |
| 2603 | dsi_unregister_isr(dsi_completion_handler, &completion, |
| 2604 | DSI_IRQ_ERROR_MASK); |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2605 | err1: |
| 2606 | dsi_unregister_isr_vc(channel, dsi_completion_handler, |
| 2607 | &completion, DSI_VC_IRQ_BTA); |
| 2608 | err0: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2609 | return r; |
| 2610 | } |
| 2611 | EXPORT_SYMBOL(dsi_vc_send_bta_sync); |
| 2612 | |
| 2613 | static inline void dsi_vc_write_long_header(int channel, u8 data_type, |
| 2614 | u16 len, u8 ecc) |
| 2615 | { |
| 2616 | u32 val; |
| 2617 | u8 data_id; |
| 2618 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 2619 | WARN_ON(!dsi_bus_is_locked()); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2620 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 2621 | data_id = data_type | dsi.vc[channel].vc_id << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2622 | |
| 2623 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | |
| 2624 | FLD_VAL(ecc, 31, 24); |
| 2625 | |
| 2626 | dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val); |
| 2627 | } |
| 2628 | |
| 2629 | static inline void dsi_vc_write_long_payload(int channel, |
| 2630 | u8 b1, u8 b2, u8 b3, u8 b4) |
| 2631 | { |
| 2632 | u32 val; |
| 2633 | |
| 2634 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; |
| 2635 | |
| 2636 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", |
| 2637 | b1, b2, b3, b4, val); */ |
| 2638 | |
| 2639 | dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val); |
| 2640 | } |
| 2641 | |
| 2642 | static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len, |
| 2643 | u8 ecc) |
| 2644 | { |
| 2645 | /*u32 val; */ |
| 2646 | int i; |
| 2647 | u8 *p; |
| 2648 | int r = 0; |
| 2649 | u8 b1, b2, b3, b4; |
| 2650 | |
| 2651 | if (dsi.debug_write) |
| 2652 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
| 2653 | |
| 2654 | /* len + header */ |
| 2655 | if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) { |
| 2656 | DSSERR("unable to send long packet: packet too long.\n"); |
| 2657 | return -EINVAL; |
| 2658 | } |
| 2659 | |
| 2660 | dsi_vc_config_l4(channel); |
| 2661 | |
| 2662 | dsi_vc_write_long_header(channel, data_type, len, ecc); |
| 2663 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2664 | p = data; |
| 2665 | for (i = 0; i < len >> 2; i++) { |
| 2666 | if (dsi.debug_write) |
| 2667 | DSSDBG("\tsending full packet %d\n", i); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2668 | |
| 2669 | b1 = *p++; |
| 2670 | b2 = *p++; |
| 2671 | b3 = *p++; |
| 2672 | b4 = *p++; |
| 2673 | |
| 2674 | dsi_vc_write_long_payload(channel, b1, b2, b3, b4); |
| 2675 | } |
| 2676 | |
| 2677 | i = len % 4; |
| 2678 | if (i) { |
| 2679 | b1 = 0; b2 = 0; b3 = 0; |
| 2680 | |
| 2681 | if (dsi.debug_write) |
| 2682 | DSSDBG("\tsending remainder bytes %d\n", i); |
| 2683 | |
| 2684 | switch (i) { |
| 2685 | case 3: |
| 2686 | b1 = *p++; |
| 2687 | b2 = *p++; |
| 2688 | b3 = *p++; |
| 2689 | break; |
| 2690 | case 2: |
| 2691 | b1 = *p++; |
| 2692 | b2 = *p++; |
| 2693 | break; |
| 2694 | case 1: |
| 2695 | b1 = *p++; |
| 2696 | break; |
| 2697 | } |
| 2698 | |
| 2699 | dsi_vc_write_long_payload(channel, b1, b2, b3, 0); |
| 2700 | } |
| 2701 | |
| 2702 | return r; |
| 2703 | } |
| 2704 | |
| 2705 | static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc) |
| 2706 | { |
| 2707 | u32 r; |
| 2708 | u8 data_id; |
| 2709 | |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 2710 | WARN_ON(!dsi_bus_is_locked()); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2711 | |
| 2712 | if (dsi.debug_write) |
| 2713 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", |
| 2714 | channel, |
| 2715 | data_type, data & 0xff, (data >> 8) & 0xff); |
| 2716 | |
| 2717 | dsi_vc_config_l4(channel); |
| 2718 | |
| 2719 | if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) { |
| 2720 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); |
| 2721 | return -EINVAL; |
| 2722 | } |
| 2723 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 2724 | data_id = data_type | dsi.vc[channel].vc_id << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2725 | |
| 2726 | r = (data_id << 0) | (data << 8) | (ecc << 24); |
| 2727 | |
| 2728 | dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r); |
| 2729 | |
| 2730 | return 0; |
| 2731 | } |
| 2732 | |
| 2733 | int dsi_vc_send_null(int channel) |
| 2734 | { |
| 2735 | u8 nullpkg[] = {0, 0, 0, 0}; |
Tomi Valkeinen | 397bb3c | 2009-12-03 13:37:31 +0200 | [diff] [blame] | 2736 | return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2737 | } |
| 2738 | EXPORT_SYMBOL(dsi_vc_send_null); |
| 2739 | |
| 2740 | int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len) |
| 2741 | { |
| 2742 | int r; |
| 2743 | |
| 2744 | BUG_ON(len == 0); |
| 2745 | |
| 2746 | if (len == 1) { |
| 2747 | r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0, |
| 2748 | data[0], 0); |
| 2749 | } else if (len == 2) { |
| 2750 | r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1, |
| 2751 | data[0] | (data[1] << 8), 0); |
| 2752 | } else { |
| 2753 | /* 0x39 = DCS Long Write */ |
| 2754 | r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE, |
| 2755 | data, len, 0); |
| 2756 | } |
| 2757 | |
| 2758 | return r; |
| 2759 | } |
| 2760 | EXPORT_SYMBOL(dsi_vc_dcs_write_nosync); |
| 2761 | |
| 2762 | int dsi_vc_dcs_write(int channel, u8 *data, int len) |
| 2763 | { |
| 2764 | int r; |
| 2765 | |
| 2766 | r = dsi_vc_dcs_write_nosync(channel, data, len); |
| 2767 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2768 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2769 | |
| 2770 | r = dsi_vc_send_bta_sync(channel); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2771 | if (r) |
| 2772 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2773 | |
Tomi Valkeinen | b63ac1e | 2010-04-09 13:20:57 +0300 | [diff] [blame] | 2774 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */ |
| 2775 | DSSERR("rx fifo not empty after write, dumping data:\n"); |
| 2776 | dsi_vc_flush_receive_data(channel); |
| 2777 | r = -EIO; |
| 2778 | goto err; |
| 2779 | } |
| 2780 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2781 | return 0; |
| 2782 | err: |
| 2783 | DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n", |
| 2784 | channel, data[0], len); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2785 | return r; |
| 2786 | } |
| 2787 | EXPORT_SYMBOL(dsi_vc_dcs_write); |
| 2788 | |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 2789 | int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd) |
| 2790 | { |
| 2791 | return dsi_vc_dcs_write(channel, &dcs_cmd, 1); |
| 2792 | } |
| 2793 | EXPORT_SYMBOL(dsi_vc_dcs_write_0); |
| 2794 | |
| 2795 | int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param) |
| 2796 | { |
| 2797 | u8 buf[2]; |
| 2798 | buf[0] = dcs_cmd; |
| 2799 | buf[1] = param; |
| 2800 | return dsi_vc_dcs_write(channel, buf, 2); |
| 2801 | } |
| 2802 | EXPORT_SYMBOL(dsi_vc_dcs_write_1); |
| 2803 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2804 | int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen) |
| 2805 | { |
| 2806 | u32 val; |
| 2807 | u8 dt; |
| 2808 | int r; |
| 2809 | |
| 2810 | if (dsi.debug_read) |
Tomi Valkeinen | ff90a34 | 2009-12-03 13:38:04 +0200 | [diff] [blame] | 2811 | DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2812 | |
| 2813 | r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0); |
| 2814 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2815 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2816 | |
| 2817 | r = dsi_vc_send_bta_sync(channel); |
| 2818 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2819 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2820 | |
| 2821 | /* RX_FIFO_NOT_EMPTY */ |
| 2822 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) { |
| 2823 | DSSERR("RX fifo empty when trying to read.\n"); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2824 | r = -EIO; |
| 2825 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2826 | } |
| 2827 | |
| 2828 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
| 2829 | if (dsi.debug_read) |
| 2830 | DSSDBG("\theader: %08x\n", val); |
| 2831 | dt = FLD_GET(val, 5, 0); |
| 2832 | if (dt == DSI_DT_RX_ACK_WITH_ERR) { |
| 2833 | u16 err = FLD_GET(val, 23, 8); |
| 2834 | dsi_show_rx_ack_with_err(err); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2835 | r = -EIO; |
| 2836 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2837 | |
| 2838 | } else if (dt == DSI_DT_RX_SHORT_READ_1) { |
| 2839 | u8 data = FLD_GET(val, 15, 8); |
| 2840 | if (dsi.debug_read) |
| 2841 | DSSDBG("\tDCS short response, 1 byte: %02x\n", data); |
| 2842 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2843 | if (buflen < 1) { |
| 2844 | r = -EIO; |
| 2845 | goto err; |
| 2846 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2847 | |
| 2848 | buf[0] = data; |
| 2849 | |
| 2850 | return 1; |
| 2851 | } else if (dt == DSI_DT_RX_SHORT_READ_2) { |
| 2852 | u16 data = FLD_GET(val, 23, 8); |
| 2853 | if (dsi.debug_read) |
| 2854 | DSSDBG("\tDCS short response, 2 byte: %04x\n", data); |
| 2855 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2856 | if (buflen < 2) { |
| 2857 | r = -EIO; |
| 2858 | goto err; |
| 2859 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2860 | |
| 2861 | buf[0] = data & 0xff; |
| 2862 | buf[1] = (data >> 8) & 0xff; |
| 2863 | |
| 2864 | return 2; |
| 2865 | } else if (dt == DSI_DT_RX_DCS_LONG_READ) { |
| 2866 | int w; |
| 2867 | int len = FLD_GET(val, 23, 8); |
| 2868 | if (dsi.debug_read) |
| 2869 | DSSDBG("\tDCS long response, len %d\n", len); |
| 2870 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2871 | if (len > buflen) { |
| 2872 | r = -EIO; |
| 2873 | goto err; |
| 2874 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2875 | |
| 2876 | /* two byte checksum ends the packet, not included in len */ |
| 2877 | for (w = 0; w < len + 2;) { |
| 2878 | int b; |
| 2879 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); |
| 2880 | if (dsi.debug_read) |
| 2881 | DSSDBG("\t\t%02x %02x %02x %02x\n", |
| 2882 | (val >> 0) & 0xff, |
| 2883 | (val >> 8) & 0xff, |
| 2884 | (val >> 16) & 0xff, |
| 2885 | (val >> 24) & 0xff); |
| 2886 | |
| 2887 | for (b = 0; b < 4; ++b) { |
| 2888 | if (w < len) |
| 2889 | buf[w] = (val >> (b * 8)) & 0xff; |
| 2890 | /* we discard the 2 byte checksum */ |
| 2891 | ++w; |
| 2892 | } |
| 2893 | } |
| 2894 | |
| 2895 | return len; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2896 | } else { |
| 2897 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2898 | r = -EIO; |
| 2899 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2900 | } |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2901 | |
| 2902 | BUG(); |
| 2903 | err: |
| 2904 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", |
| 2905 | channel, dcs_cmd); |
| 2906 | return r; |
| 2907 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2908 | } |
| 2909 | EXPORT_SYMBOL(dsi_vc_dcs_read); |
| 2910 | |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 2911 | int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data) |
| 2912 | { |
| 2913 | int r; |
| 2914 | |
| 2915 | r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1); |
| 2916 | |
| 2917 | if (r < 0) |
| 2918 | return r; |
| 2919 | |
| 2920 | if (r != 1) |
| 2921 | return -EIO; |
| 2922 | |
| 2923 | return 0; |
| 2924 | } |
| 2925 | EXPORT_SYMBOL(dsi_vc_dcs_read_1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2926 | |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2927 | int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2) |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2928 | { |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2929 | u8 buf[2]; |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2930 | int r; |
| 2931 | |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2932 | r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2); |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2933 | |
| 2934 | if (r < 0) |
| 2935 | return r; |
| 2936 | |
| 2937 | if (r != 2) |
| 2938 | return -EIO; |
| 2939 | |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 2940 | *data1 = buf[0]; |
| 2941 | *data2 = buf[1]; |
| 2942 | |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 2943 | return 0; |
| 2944 | } |
| 2945 | EXPORT_SYMBOL(dsi_vc_dcs_read_2); |
| 2946 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2947 | int dsi_vc_set_max_rx_packet_size(int channel, u16 len) |
| 2948 | { |
Tomi Valkeinen | fa15c79 | 2010-05-14 17:42:07 +0300 | [diff] [blame] | 2949 | return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2950 | len, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2951 | } |
| 2952 | EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); |
| 2953 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2954 | static int dsi_enter_ulps(void) |
| 2955 | { |
| 2956 | DECLARE_COMPLETION_ONSTACK(completion); |
| 2957 | int r; |
| 2958 | |
| 2959 | DSSDBGF(); |
| 2960 | |
| 2961 | WARN_ON(!dsi_bus_is_locked()); |
| 2962 | |
| 2963 | WARN_ON(dsi.ulps_enabled); |
| 2964 | |
| 2965 | if (dsi.ulps_enabled) |
| 2966 | return 0; |
| 2967 | |
| 2968 | if (REG_GET(DSI_CLK_CTRL, 13, 13)) { |
| 2969 | DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n"); |
| 2970 | return -EIO; |
| 2971 | } |
| 2972 | |
| 2973 | dsi_sync_vc(0); |
| 2974 | dsi_sync_vc(1); |
| 2975 | dsi_sync_vc(2); |
| 2976 | dsi_sync_vc(3); |
| 2977 | |
| 2978 | dsi_force_tx_stop_mode_io(); |
| 2979 | |
| 2980 | dsi_vc_enable(0, false); |
| 2981 | dsi_vc_enable(1, false); |
| 2982 | dsi_vc_enable(2, false); |
| 2983 | dsi_vc_enable(3, false); |
| 2984 | |
| 2985 | if (REG_GET(DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ |
| 2986 | DSSERR("HS busy when enabling ULPS\n"); |
| 2987 | return -EIO; |
| 2988 | } |
| 2989 | |
| 2990 | if (REG_GET(DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ |
| 2991 | DSSERR("LP busy when enabling ULPS\n"); |
| 2992 | return -EIO; |
| 2993 | } |
| 2994 | |
| 2995 | r = dsi_register_isr_cio(dsi_completion_handler, &completion, |
| 2996 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 2997 | if (r) |
| 2998 | return r; |
| 2999 | |
| 3000 | /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ |
| 3001 | /* LANEx_ULPS_SIG2 */ |
| 3002 | REG_FLD_MOD(DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2), 7, 5); |
| 3003 | |
| 3004 | if (wait_for_completion_timeout(&completion, |
| 3005 | msecs_to_jiffies(1000)) == 0) { |
| 3006 | DSSERR("ULPS enable timeout\n"); |
| 3007 | r = -EIO; |
| 3008 | goto err; |
| 3009 | } |
| 3010 | |
| 3011 | dsi_unregister_isr_cio(dsi_completion_handler, &completion, |
| 3012 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 3013 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 3014 | dsi_cio_power(DSI_COMPLEXIO_POWER_ULPS); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3015 | |
| 3016 | dsi_if_enable(false); |
| 3017 | |
| 3018 | dsi.ulps_enabled = true; |
| 3019 | |
| 3020 | return 0; |
| 3021 | |
| 3022 | err: |
| 3023 | dsi_unregister_isr_cio(dsi_completion_handler, &completion, |
| 3024 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 3025 | return r; |
| 3026 | } |
| 3027 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3028 | static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3029 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3030 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3031 | unsigned long total_ticks; |
| 3032 | u32 r; |
| 3033 | |
| 3034 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3035 | |
| 3036 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3037 | fck = dsi_fclk_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3038 | |
| 3039 | r = dsi_read_reg(DSI_TIMING2); |
| 3040 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3041 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
| 3042 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3043 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
| 3044 | dsi_write_reg(DSI_TIMING2, r); |
| 3045 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3046 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3047 | |
| 3048 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3049 | total_ticks, |
| 3050 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 3051 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3052 | } |
| 3053 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3054 | static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3055 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3056 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3057 | unsigned long total_ticks; |
| 3058 | u32 r; |
| 3059 | |
| 3060 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3061 | |
| 3062 | /* ticks in DSI_FCK */ |
| 3063 | fck = dsi_fclk_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3064 | |
| 3065 | r = dsi_read_reg(DSI_TIMING1); |
| 3066 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3067 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
| 3068 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3069 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
| 3070 | dsi_write_reg(DSI_TIMING1, r); |
| 3071 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3072 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
| 3073 | |
| 3074 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3075 | total_ticks, |
| 3076 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", |
| 3077 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3078 | } |
| 3079 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3080 | static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3081 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3082 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3083 | unsigned long total_ticks; |
| 3084 | u32 r; |
| 3085 | |
| 3086 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3087 | |
| 3088 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3089 | fck = dsi_fclk_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3090 | |
| 3091 | r = dsi_read_reg(DSI_TIMING1); |
| 3092 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3093 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
| 3094 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3095 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
| 3096 | dsi_write_reg(DSI_TIMING1, r); |
| 3097 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3098 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3099 | |
| 3100 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", |
| 3101 | total_ticks, |
| 3102 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 3103 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3104 | } |
| 3105 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3106 | static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3107 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3108 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3109 | unsigned long total_ticks; |
| 3110 | u32 r; |
| 3111 | |
| 3112 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3113 | |
| 3114 | /* ticks in TxByteClkHS */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3115 | fck = dsi_get_txbyteclkhs(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3116 | |
| 3117 | r = dsi_read_reg(DSI_TIMING2); |
| 3118 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3119 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
| 3120 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3121 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
| 3122 | dsi_write_reg(DSI_TIMING2, r); |
| 3123 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3124 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3125 | |
| 3126 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3127 | total_ticks, |
| 3128 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 3129 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3130 | } |
| 3131 | static int dsi_proto_config(struct omap_dss_device *dssdev) |
| 3132 | { |
| 3133 | u32 r; |
| 3134 | int buswidth = 0; |
| 3135 | |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3136 | dsi_config_tx_fifo(DSI_FIFO_SIZE_32, |
| 3137 | DSI_FIFO_SIZE_32, |
| 3138 | DSI_FIFO_SIZE_32, |
| 3139 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3140 | |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3141 | dsi_config_rx_fifo(DSI_FIFO_SIZE_32, |
| 3142 | DSI_FIFO_SIZE_32, |
| 3143 | DSI_FIFO_SIZE_32, |
| 3144 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3145 | |
| 3146 | /* XXX what values for the timeouts? */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3147 | dsi_set_stop_state_counter(0x1000, false, false); |
| 3148 | dsi_set_ta_timeout(0x1fff, true, true); |
| 3149 | dsi_set_lp_rx_timeout(0x1fff, true, true); |
| 3150 | dsi_set_hs_tx_timeout(0x1fff, true, true); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3151 | |
| 3152 | switch (dssdev->ctrl.pixel_size) { |
| 3153 | case 16: |
| 3154 | buswidth = 0; |
| 3155 | break; |
| 3156 | case 18: |
| 3157 | buswidth = 1; |
| 3158 | break; |
| 3159 | case 24: |
| 3160 | buswidth = 2; |
| 3161 | break; |
| 3162 | default: |
| 3163 | BUG(); |
| 3164 | } |
| 3165 | |
| 3166 | r = dsi_read_reg(DSI_CTRL); |
| 3167 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ |
| 3168 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ |
| 3169 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ |
| 3170 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ |
| 3171 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ |
| 3172 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ |
| 3173 | r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */ |
| 3174 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ |
| 3175 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 3176 | if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
| 3177 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ |
| 3178 | /* DCS_CMD_CODE, 1=start, 0=continue */ |
| 3179 | r = FLD_MOD(r, 0, 25, 25); |
| 3180 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3181 | |
| 3182 | dsi_write_reg(DSI_CTRL, r); |
| 3183 | |
| 3184 | dsi_vc_initial_config(0); |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3185 | dsi_vc_initial_config(1); |
| 3186 | dsi_vc_initial_config(2); |
| 3187 | dsi_vc_initial_config(3); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3188 | |
| 3189 | return 0; |
| 3190 | } |
| 3191 | |
| 3192 | static void dsi_proto_timings(struct omap_dss_device *dssdev) |
| 3193 | { |
| 3194 | unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; |
| 3195 | unsigned tclk_pre, tclk_post; |
| 3196 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; |
| 3197 | unsigned ths_trail, ths_exit; |
| 3198 | unsigned ddr_clk_pre, ddr_clk_post; |
| 3199 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; |
| 3200 | unsigned ths_eot; |
| 3201 | u32 r; |
| 3202 | |
| 3203 | r = dsi_read_reg(DSI_DSIPHY_CFG0); |
| 3204 | ths_prepare = FLD_GET(r, 31, 24); |
| 3205 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); |
| 3206 | ths_zero = ths_prepare_ths_zero - ths_prepare; |
| 3207 | ths_trail = FLD_GET(r, 15, 8); |
| 3208 | ths_exit = FLD_GET(r, 7, 0); |
| 3209 | |
| 3210 | r = dsi_read_reg(DSI_DSIPHY_CFG1); |
| 3211 | tlpx = FLD_GET(r, 22, 16) * 2; |
| 3212 | tclk_trail = FLD_GET(r, 15, 8); |
| 3213 | tclk_zero = FLD_GET(r, 7, 0); |
| 3214 | |
| 3215 | r = dsi_read_reg(DSI_DSIPHY_CFG2); |
| 3216 | tclk_prepare = FLD_GET(r, 7, 0); |
| 3217 | |
| 3218 | /* min 8*UI */ |
| 3219 | tclk_pre = 20; |
| 3220 | /* min 60ns + 52*UI */ |
| 3221 | tclk_post = ns2ddr(60) + 26; |
| 3222 | |
| 3223 | /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */ |
| 3224 | if (dssdev->phy.dsi.data1_lane != 0 && |
| 3225 | dssdev->phy.dsi.data2_lane != 0) |
| 3226 | ths_eot = 2; |
| 3227 | else |
| 3228 | ths_eot = 4; |
| 3229 | |
| 3230 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, |
| 3231 | 4); |
| 3232 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; |
| 3233 | |
| 3234 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); |
| 3235 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); |
| 3236 | |
| 3237 | r = dsi_read_reg(DSI_CLK_TIMING); |
| 3238 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); |
| 3239 | r = FLD_MOD(r, ddr_clk_post, 7, 0); |
| 3240 | dsi_write_reg(DSI_CLK_TIMING, r); |
| 3241 | |
| 3242 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", |
| 3243 | ddr_clk_pre, |
| 3244 | ddr_clk_post); |
| 3245 | |
| 3246 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + |
| 3247 | DIV_ROUND_UP(ths_prepare, 4) + |
| 3248 | DIV_ROUND_UP(ths_zero + 3, 4); |
| 3249 | |
| 3250 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; |
| 3251 | |
| 3252 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | |
| 3253 | FLD_VAL(exit_hs_mode_lat, 15, 0); |
| 3254 | dsi_write_reg(DSI_VM_TIMING7, r); |
| 3255 | |
| 3256 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", |
| 3257 | enter_hs_mode_lat, exit_hs_mode_lat); |
| 3258 | } |
| 3259 | |
| 3260 | |
| 3261 | #define DSI_DECL_VARS \ |
| 3262 | int __dsi_cb = 0; u32 __dsi_cv = 0; |
| 3263 | |
| 3264 | #define DSI_FLUSH(ch) \ |
| 3265 | if (__dsi_cb > 0) { \ |
| 3266 | /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \ |
| 3267 | dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \ |
| 3268 | __dsi_cb = __dsi_cv = 0; \ |
| 3269 | } |
| 3270 | |
| 3271 | #define DSI_PUSH(ch, data) \ |
| 3272 | do { \ |
| 3273 | __dsi_cv |= (data) << (__dsi_cb * 8); \ |
| 3274 | /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \ |
| 3275 | if (++__dsi_cb > 3) \ |
| 3276 | DSI_FLUSH(ch); \ |
| 3277 | } while (0) |
| 3278 | |
| 3279 | static int dsi_update_screen_l4(struct omap_dss_device *dssdev, |
| 3280 | int x, int y, int w, int h) |
| 3281 | { |
| 3282 | /* Note: supports only 24bit colors in 32bit container */ |
| 3283 | int first = 1; |
| 3284 | int fifo_stalls = 0; |
| 3285 | int max_dsi_packet_size; |
| 3286 | int max_data_per_packet; |
| 3287 | int max_pixels_per_packet; |
| 3288 | int pixels_left; |
| 3289 | int bytespp = dssdev->ctrl.pixel_size / 8; |
| 3290 | int scr_width; |
| 3291 | u32 __iomem *data; |
| 3292 | int start_offset; |
| 3293 | int horiz_inc; |
| 3294 | int current_x; |
| 3295 | struct omap_overlay *ovl; |
| 3296 | |
| 3297 | debug_irq = 0; |
| 3298 | |
| 3299 | DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n", |
| 3300 | x, y, w, h); |
| 3301 | |
| 3302 | ovl = dssdev->manager->overlays[0]; |
| 3303 | |
| 3304 | if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U) |
| 3305 | return -EINVAL; |
| 3306 | |
| 3307 | if (dssdev->ctrl.pixel_size != 24) |
| 3308 | return -EINVAL; |
| 3309 | |
| 3310 | scr_width = ovl->info.screen_width; |
| 3311 | data = ovl->info.vaddr; |
| 3312 | |
| 3313 | start_offset = scr_width * y + x; |
| 3314 | horiz_inc = scr_width - w; |
| 3315 | current_x = x; |
| 3316 | |
| 3317 | /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes |
| 3318 | * in fifo */ |
| 3319 | |
| 3320 | /* When using CPU, max long packet size is TX buffer size */ |
| 3321 | max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4; |
| 3322 | |
| 3323 | /* we seem to get better perf if we divide the tx fifo to half, |
| 3324 | and while the other half is being sent, we fill the other half |
| 3325 | max_dsi_packet_size /= 2; */ |
| 3326 | |
| 3327 | max_data_per_packet = max_dsi_packet_size - 4 - 1; |
| 3328 | |
| 3329 | max_pixels_per_packet = max_data_per_packet / bytespp; |
| 3330 | |
| 3331 | DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet); |
| 3332 | |
| 3333 | pixels_left = w * h; |
| 3334 | |
| 3335 | DSSDBG("total pixels %d\n", pixels_left); |
| 3336 | |
| 3337 | data += start_offset; |
| 3338 | |
| 3339 | while (pixels_left > 0) { |
| 3340 | /* 0x2c = write_memory_start */ |
| 3341 | /* 0x3c = write_memory_continue */ |
| 3342 | u8 dcs_cmd = first ? 0x2c : 0x3c; |
| 3343 | int pixels; |
| 3344 | DSI_DECL_VARS; |
| 3345 | first = 0; |
| 3346 | |
| 3347 | #if 1 |
| 3348 | /* using fifo not empty */ |
| 3349 | /* TX_FIFO_NOT_EMPTY */ |
| 3350 | while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3351 | fifo_stalls++; |
| 3352 | if (fifo_stalls > 0xfffff) { |
| 3353 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 3354 | pixels_left); |
| 3355 | dsi_if_enable(0); |
| 3356 | return -EIO; |
| 3357 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 3358 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3359 | } |
| 3360 | #elif 1 |
| 3361 | /* using fifo emptiness */ |
| 3362 | while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 < |
| 3363 | max_dsi_packet_size) { |
| 3364 | fifo_stalls++; |
| 3365 | if (fifo_stalls > 0xfffff) { |
| 3366 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 3367 | pixels_left); |
| 3368 | dsi_if_enable(0); |
| 3369 | return -EIO; |
| 3370 | } |
| 3371 | } |
| 3372 | #else |
| 3373 | while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) { |
| 3374 | fifo_stalls++; |
| 3375 | if (fifo_stalls > 0xfffff) { |
| 3376 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 3377 | pixels_left); |
| 3378 | dsi_if_enable(0); |
| 3379 | return -EIO; |
| 3380 | } |
| 3381 | } |
| 3382 | #endif |
| 3383 | pixels = min(max_pixels_per_packet, pixels_left); |
| 3384 | |
| 3385 | pixels_left -= pixels; |
| 3386 | |
| 3387 | dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE, |
| 3388 | 1 + pixels * bytespp, 0); |
| 3389 | |
| 3390 | DSI_PUSH(0, dcs_cmd); |
| 3391 | |
| 3392 | while (pixels-- > 0) { |
| 3393 | u32 pix = __raw_readl(data++); |
| 3394 | |
| 3395 | DSI_PUSH(0, (pix >> 16) & 0xff); |
| 3396 | DSI_PUSH(0, (pix >> 8) & 0xff); |
| 3397 | DSI_PUSH(0, (pix >> 0) & 0xff); |
| 3398 | |
| 3399 | current_x++; |
| 3400 | if (current_x == x+w) { |
| 3401 | current_x = x; |
| 3402 | data += horiz_inc; |
| 3403 | } |
| 3404 | } |
| 3405 | |
| 3406 | DSI_FLUSH(0); |
| 3407 | } |
| 3408 | |
| 3409 | return 0; |
| 3410 | } |
| 3411 | |
| 3412 | static void dsi_update_screen_dispc(struct omap_dss_device *dssdev, |
| 3413 | u16 x, u16 y, u16 w, u16 h) |
| 3414 | { |
| 3415 | unsigned bytespp; |
| 3416 | unsigned bytespl; |
| 3417 | unsigned bytespf; |
| 3418 | unsigned total_len; |
| 3419 | unsigned packet_payload; |
| 3420 | unsigned packet_len; |
| 3421 | u32 l; |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3422 | int r; |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3423 | const unsigned channel = dsi.update_channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3424 | /* line buffer is 1024 x 24bits */ |
| 3425 | /* XXX: for some reason using full buffer size causes considerable TX |
| 3426 | * slowdown with update sizes that fill the whole buffer */ |
| 3427 | const unsigned line_buf_size = 1023 * 3; |
| 3428 | |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 3429 | DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n", |
| 3430 | x, y, w, h); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3431 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3432 | dsi_vc_config_vp(channel); |
| 3433 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3434 | bytespp = dssdev->ctrl.pixel_size / 8; |
| 3435 | bytespl = w * bytespp; |
| 3436 | bytespf = bytespl * h; |
| 3437 | |
| 3438 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is |
| 3439 | * number of lines in a packet. See errata about VP_CLK_RATIO */ |
| 3440 | |
| 3441 | if (bytespf < line_buf_size) |
| 3442 | packet_payload = bytespf; |
| 3443 | else |
| 3444 | packet_payload = (line_buf_size) / bytespl * bytespl; |
| 3445 | |
| 3446 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ |
| 3447 | total_len = (bytespf / packet_payload) * packet_len; |
| 3448 | |
| 3449 | if (bytespf % packet_payload) |
| 3450 | total_len += (bytespf % packet_payload) + 1; |
| 3451 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3452 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
| 3453 | dsi_write_reg(DSI_VC_TE(channel), l); |
| 3454 | |
| 3455 | dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0); |
| 3456 | |
Tomi Valkeinen | 942a91a | 2010-02-10 17:27:39 +0200 | [diff] [blame] | 3457 | if (dsi.te_enabled) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3458 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
| 3459 | else |
| 3460 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ |
| 3461 | dsi_write_reg(DSI_VC_TE(channel), l); |
| 3462 | |
| 3463 | /* We put SIDLEMODE to no-idle for the duration of the transfer, |
| 3464 | * because DSS interrupts are not capable of waking up the CPU and the |
| 3465 | * framedone interrupt could be delayed for quite a long time. I think |
| 3466 | * the same goes for any DSS interrupts, but for some reason I have not |
| 3467 | * seen the problem anywhere else than here. |
| 3468 | */ |
| 3469 | dispc_disable_sidle(); |
| 3470 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3471 | dsi_perf_mark_start(); |
| 3472 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3473 | r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work, |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3474 | msecs_to_jiffies(250)); |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3475 | BUG_ON(r == 0); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3476 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3477 | dss_start_update(dssdev); |
| 3478 | |
Tomi Valkeinen | 942a91a | 2010-02-10 17:27:39 +0200 | [diff] [blame] | 3479 | if (dsi.te_enabled) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3480 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
| 3481 | * for TE is longer than the timer allows */ |
| 3482 | REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ |
| 3483 | |
| 3484 | dsi_vc_send_bta(channel); |
| 3485 | |
| 3486 | #ifdef DSI_CATCH_MISSING_TE |
| 3487 | mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250)); |
| 3488 | #endif |
| 3489 | } |
| 3490 | } |
| 3491 | |
| 3492 | #ifdef DSI_CATCH_MISSING_TE |
| 3493 | static void dsi_te_timeout(unsigned long arg) |
| 3494 | { |
| 3495 | DSSERR("TE not received for 250ms!\n"); |
| 3496 | } |
| 3497 | #endif |
| 3498 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3499 | static void dsi_handle_framedone(int error) |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3500 | { |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3501 | /* SIDLEMODE back to smart-idle */ |
| 3502 | dispc_enable_sidle(); |
| 3503 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3504 | if (dsi.te_enabled) { |
| 3505 | /* enable LP_RX_TO again after the TE */ |
| 3506 | REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
| 3507 | } |
| 3508 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3509 | dsi.framedone_callback(error, dsi.framedone_data); |
| 3510 | |
| 3511 | if (!error) |
| 3512 | dsi_perf_show("DISPC"); |
| 3513 | } |
| 3514 | |
| 3515 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
| 3516 | { |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3517 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
| 3518 | * 250ms which would conflict with this timeout work. What should be |
| 3519 | * done is first cancel the transfer on the HW, and then cancel the |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3520 | * possibly scheduled framedone work. However, cancelling the transfer |
| 3521 | * on the HW is buggy, and would probably require resetting the whole |
| 3522 | * DSI */ |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3523 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3524 | DSSERR("Framedone not received for 250ms!\n"); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3525 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3526 | dsi_handle_framedone(-ETIMEDOUT); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3527 | } |
| 3528 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3529 | static void dsi_framedone_irq_callback(void *data, u32 mask) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3530 | { |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3531 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
| 3532 | * turns itself off. However, DSI still has the pixels in its buffers, |
| 3533 | * and is sending the data. |
| 3534 | */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3535 | |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 3536 | __cancel_delayed_work(&dsi.framedone_timeout_work); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3537 | |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 3538 | dsi_handle_framedone(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3539 | |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 3540 | #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC |
| 3541 | dispc_fake_vsync_irq(); |
| 3542 | #endif |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3543 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3544 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3545 | int omap_dsi_prepare_update(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 26a8c25 | 2010-06-09 15:31:34 +0300 | [diff] [blame] | 3546 | u16 *x, u16 *y, u16 *w, u16 *h, |
| 3547 | bool enlarge_update_area) |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3548 | { |
| 3549 | u16 dw, dh; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3550 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3551 | dssdev->driver->get_resolution(dssdev, &dw, &dh); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3552 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3553 | if (*x > dw || *y > dh) |
| 3554 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3555 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3556 | if (*x + *w > dw) |
| 3557 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3558 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3559 | if (*y + *h > dh) |
| 3560 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3561 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3562 | if (*w == 1) |
| 3563 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3564 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3565 | if (*w == 0 || *h == 0) |
| 3566 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3567 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3568 | dsi_perf_mark_setup(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3569 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3570 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { |
Tomi Valkeinen | 26a8c25 | 2010-06-09 15:31:34 +0300 | [diff] [blame] | 3571 | dss_setup_partial_planes(dssdev, x, y, w, h, |
| 3572 | enlarge_update_area); |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 3573 | dispc_set_lcd_size(dssdev->manager->id, *w, *h); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3574 | } |
| 3575 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3576 | return 0; |
| 3577 | } |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3578 | EXPORT_SYMBOL(omap_dsi_prepare_update); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3579 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3580 | int omap_dsi_update(struct omap_dss_device *dssdev, |
| 3581 | int channel, |
| 3582 | u16 x, u16 y, u16 w, u16 h, |
| 3583 | void (*callback)(int, void *), void *data) |
| 3584 | { |
| 3585 | dsi.update_channel = channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3586 | |
Tomi Valkeinen | a602771 | 2010-05-25 17:01:28 +0300 | [diff] [blame] | 3587 | /* OMAP DSS cannot send updates of odd widths. |
| 3588 | * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON |
| 3589 | * here to make sure we catch erroneous updates. Otherwise we'll only |
| 3590 | * see rather obscure HW error happening, as DSS halts. */ |
| 3591 | BUG_ON(x % 2 == 1); |
| 3592 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3593 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { |
| 3594 | dsi.framedone_callback = callback; |
| 3595 | dsi.framedone_data = data; |
| 3596 | |
| 3597 | dsi.update_region.x = x; |
| 3598 | dsi.update_region.y = y; |
| 3599 | dsi.update_region.w = w; |
| 3600 | dsi.update_region.h = h; |
| 3601 | dsi.update_region.device = dssdev; |
| 3602 | |
| 3603 | dsi_update_screen_dispc(dssdev, x, y, w, h); |
| 3604 | } else { |
Archit Taneja | e9c31af | 2010-07-14 14:11:50 +0200 | [diff] [blame] | 3605 | int r; |
| 3606 | |
| 3607 | r = dsi_update_screen_l4(dssdev, x, y, w, h); |
| 3608 | if (r) |
| 3609 | return r; |
| 3610 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3611 | dsi_perf_show("L4"); |
| 3612 | callback(0, data); |
| 3613 | } |
| 3614 | |
| 3615 | return 0; |
| 3616 | } |
| 3617 | EXPORT_SYMBOL(omap_dsi_update); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3618 | |
| 3619 | /* Display funcs */ |
| 3620 | |
| 3621 | static int dsi_display_init_dispc(struct omap_dss_device *dssdev) |
| 3622 | { |
| 3623 | int r; |
| 3624 | |
| 3625 | r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL, |
| 3626 | DISPC_IRQ_FRAMEDONE); |
| 3627 | if (r) { |
| 3628 | DSSERR("can't get FRAMEDONE irq\n"); |
| 3629 | return r; |
| 3630 | } |
| 3631 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 3632 | dispc_set_lcd_display_type(dssdev->manager->id, |
| 3633 | OMAP_DSS_LCD_DISPLAY_TFT); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3634 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 3635 | dispc_set_parallel_interface_mode(dssdev->manager->id, |
| 3636 | OMAP_DSS_PARALLELMODE_DSI); |
| 3637 | dispc_enable_fifohandcheck(dssdev->manager->id, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3638 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 3639 | dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3640 | |
| 3641 | { |
| 3642 | struct omap_video_timings timings = { |
| 3643 | .hsw = 1, |
| 3644 | .hfp = 1, |
| 3645 | .hbp = 1, |
| 3646 | .vsw = 1, |
| 3647 | .vfp = 0, |
| 3648 | .vbp = 0, |
| 3649 | }; |
| 3650 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 3651 | dispc_set_lcd_timings(dssdev->manager->id, &timings); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3652 | } |
| 3653 | |
| 3654 | return 0; |
| 3655 | } |
| 3656 | |
| 3657 | static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev) |
| 3658 | { |
| 3659 | omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL, |
| 3660 | DISPC_IRQ_FRAMEDONE); |
| 3661 | } |
| 3662 | |
| 3663 | static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) |
| 3664 | { |
| 3665 | struct dsi_clock_info cinfo; |
| 3666 | int r; |
| 3667 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 3668 | /* we always use DSS_CLK_SYSCK as input clock */ |
| 3669 | cinfo.use_sys_clk = true; |
Tomi Valkeinen | c6940a3 | 2011-02-22 13:36:10 +0200 | [diff] [blame] | 3670 | cinfo.regn = dssdev->clocks.dsi.regn; |
| 3671 | cinfo.regm = dssdev->clocks.dsi.regm; |
| 3672 | cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc; |
| 3673 | cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi; |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 3674 | r = dsi_calc_clock_rates(dssdev, &cinfo); |
Ville Syrjälä | ebf0a3f | 2010-04-22 22:50:05 +0200 | [diff] [blame] | 3675 | if (r) { |
| 3676 | DSSERR("Failed to calc dsi clocks\n"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3677 | return r; |
Ville Syrjälä | ebf0a3f | 2010-04-22 22:50:05 +0200 | [diff] [blame] | 3678 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3679 | |
| 3680 | r = dsi_pll_set_clock_div(&cinfo); |
| 3681 | if (r) { |
| 3682 | DSSERR("Failed to set dsi clocks\n"); |
| 3683 | return r; |
| 3684 | } |
| 3685 | |
| 3686 | return 0; |
| 3687 | } |
| 3688 | |
| 3689 | static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev) |
| 3690 | { |
| 3691 | struct dispc_clock_info dispc_cinfo; |
| 3692 | int r; |
| 3693 | unsigned long long fck; |
| 3694 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 3695 | fck = dsi_get_pll_hsdiv_dispc_rate(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3696 | |
Archit Taneja | e888166 | 2011-04-12 13:52:24 +0530 | [diff] [blame] | 3697 | dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div; |
| 3698 | dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3699 | |
| 3700 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); |
| 3701 | if (r) { |
| 3702 | DSSERR("Failed to calc dispc clocks\n"); |
| 3703 | return r; |
| 3704 | } |
| 3705 | |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 3706 | r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3707 | if (r) { |
| 3708 | DSSERR("Failed to set dispc clocks\n"); |
| 3709 | return r; |
| 3710 | } |
| 3711 | |
| 3712 | return 0; |
| 3713 | } |
| 3714 | |
| 3715 | static int dsi_display_init_dsi(struct omap_dss_device *dssdev) |
| 3716 | { |
| 3717 | int r; |
| 3718 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3719 | r = dsi_pll_init(dssdev, true, true); |
| 3720 | if (r) |
| 3721 | goto err0; |
| 3722 | |
| 3723 | r = dsi_configure_dsi_clocks(dssdev); |
| 3724 | if (r) |
| 3725 | goto err1; |
| 3726 | |
Archit Taneja | e888166 | 2011-04-12 13:52:24 +0530 | [diff] [blame] | 3727 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
| 3728 | dss_select_dsi_clk_source(dssdev->clocks.dsi.dsi_fclk_src); |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 3729 | dss_select_lcd_clk_source(dssdev->manager->id, |
Archit Taneja | e888166 | 2011-04-12 13:52:24 +0530 | [diff] [blame] | 3730 | dssdev->clocks.dispc.channel.lcd_clk_src); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3731 | |
| 3732 | DSSDBG("PLL OK\n"); |
| 3733 | |
| 3734 | r = dsi_configure_dispc_clocks(dssdev); |
| 3735 | if (r) |
| 3736 | goto err2; |
| 3737 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 3738 | r = dsi_cio_init(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3739 | if (r) |
| 3740 | goto err2; |
| 3741 | |
| 3742 | _dsi_print_reset_status(); |
| 3743 | |
| 3744 | dsi_proto_timings(dssdev); |
| 3745 | dsi_set_lp_clk_divisor(dssdev); |
| 3746 | |
| 3747 | if (1) |
| 3748 | _dsi_print_reset_status(); |
| 3749 | |
| 3750 | r = dsi_proto_config(dssdev); |
| 3751 | if (r) |
| 3752 | goto err3; |
| 3753 | |
| 3754 | /* enable interface */ |
| 3755 | dsi_vc_enable(0, 1); |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3756 | dsi_vc_enable(1, 1); |
| 3757 | dsi_vc_enable(2, 1); |
| 3758 | dsi_vc_enable(3, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3759 | dsi_if_enable(1); |
| 3760 | dsi_force_tx_stop_mode_io(); |
| 3761 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3762 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3763 | err3: |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 3764 | dsi_cio_uninit(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3765 | err2: |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 3766 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
| 3767 | dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3768 | err1: |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 3769 | dsi_pll_uninit(true); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3770 | err0: |
| 3771 | return r; |
| 3772 | } |
| 3773 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 3774 | static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 3775 | bool disconnect_lanes, bool enter_ulps) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3776 | { |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 3777 | if (enter_ulps && !dsi.ulps_enabled) |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3778 | dsi_enter_ulps(); |
| 3779 | |
Ville Syrjälä | d737010 | 2010-04-22 22:50:09 +0200 | [diff] [blame] | 3780 | /* disable interface */ |
| 3781 | dsi_if_enable(0); |
| 3782 | dsi_vc_enable(0, 0); |
| 3783 | dsi_vc_enable(1, 0); |
| 3784 | dsi_vc_enable(2, 0); |
| 3785 | dsi_vc_enable(3, 0); |
| 3786 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 3787 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
| 3788 | dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK); |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 3789 | dsi_cio_uninit(); |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 3790 | dsi_pll_uninit(disconnect_lanes); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3791 | } |
| 3792 | |
| 3793 | static int dsi_core_init(void) |
| 3794 | { |
| 3795 | /* Autoidle */ |
| 3796 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0); |
| 3797 | |
| 3798 | /* ENWAKEUP */ |
| 3799 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2); |
| 3800 | |
| 3801 | /* SIDLEMODE smart-idle */ |
| 3802 | REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3); |
| 3803 | |
| 3804 | _dsi_initialize_irq(); |
| 3805 | |
| 3806 | return 0; |
| 3807 | } |
| 3808 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3809 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3810 | { |
| 3811 | int r = 0; |
| 3812 | |
| 3813 | DSSDBG("dsi_display_enable\n"); |
| 3814 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3815 | WARN_ON(!dsi_bus_is_locked()); |
| 3816 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3817 | mutex_lock(&dsi.lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3818 | |
| 3819 | r = omap_dss_start_device(dssdev); |
| 3820 | if (r) { |
| 3821 | DSSERR("failed to start device\n"); |
| 3822 | goto err0; |
| 3823 | } |
| 3824 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3825 | enable_clocks(1); |
| 3826 | dsi_enable_pll_clock(1); |
| 3827 | |
| 3828 | r = _dsi_reset(); |
| 3829 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3830 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3831 | |
| 3832 | dsi_core_init(); |
| 3833 | |
| 3834 | r = dsi_display_init_dispc(dssdev); |
| 3835 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3836 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3837 | |
| 3838 | r = dsi_display_init_dsi(dssdev); |
| 3839 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3840 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3841 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3842 | mutex_unlock(&dsi.lock); |
| 3843 | |
| 3844 | return 0; |
| 3845 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3846 | err2: |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3847 | dsi_display_uninit_dispc(dssdev); |
| 3848 | err1: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3849 | enable_clocks(0); |
| 3850 | dsi_enable_pll_clock(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3851 | omap_dss_stop_device(dssdev); |
| 3852 | err0: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3853 | mutex_unlock(&dsi.lock); |
| 3854 | DSSDBG("dsi_display_enable FAILED\n"); |
| 3855 | return r; |
| 3856 | } |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3857 | EXPORT_SYMBOL(omapdss_dsi_display_enable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3858 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 3859 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 3860 | bool disconnect_lanes, bool enter_ulps) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3861 | { |
| 3862 | DSSDBG("dsi_display_disable\n"); |
| 3863 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3864 | WARN_ON(!dsi_bus_is_locked()); |
| 3865 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3866 | mutex_lock(&dsi.lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3867 | |
| 3868 | dsi_display_uninit_dispc(dssdev); |
| 3869 | |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 3870 | dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3871 | |
| 3872 | enable_clocks(0); |
| 3873 | dsi_enable_pll_clock(0); |
| 3874 | |
| 3875 | omap_dss_stop_device(dssdev); |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3876 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3877 | mutex_unlock(&dsi.lock); |
| 3878 | } |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 3879 | EXPORT_SYMBOL(omapdss_dsi_display_disable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3880 | |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 3881 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3882 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3883 | dsi.te_enabled = enable; |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 3884 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3885 | } |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 3886 | EXPORT_SYMBOL(omapdss_dsi_enable_te); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3887 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3888 | void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, |
| 3889 | u32 fifo_size, enum omap_burst_size *burst_size, |
| 3890 | u32 *fifo_low, u32 *fifo_high) |
| 3891 | { |
| 3892 | unsigned burst_size_bytes; |
| 3893 | |
| 3894 | *burst_size = OMAP_DSS_BURST_16x32; |
| 3895 | burst_size_bytes = 16 * 32 / 8; |
| 3896 | |
| 3897 | *fifo_high = fifo_size - burst_size_bytes; |
Tomi Valkeinen | 36194b4 | 2010-05-18 13:35:37 +0300 | [diff] [blame] | 3898 | *fifo_low = fifo_size - burst_size_bytes * 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3899 | } |
| 3900 | |
| 3901 | int dsi_init_display(struct omap_dss_device *dssdev) |
| 3902 | { |
| 3903 | DSSDBG("DSI init\n"); |
| 3904 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3905 | /* XXX these should be figured out dynamically */ |
| 3906 | dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | |
| 3907 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; |
| 3908 | |
Tomi Valkeinen | 5f42f2c | 2011-02-22 15:53:46 +0200 | [diff] [blame] | 3909 | if (dsi.vdds_dsi_reg == NULL) { |
| 3910 | struct regulator *vdds_dsi; |
| 3911 | |
| 3912 | vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); |
| 3913 | |
| 3914 | if (IS_ERR(vdds_dsi)) { |
| 3915 | DSSERR("can't get VDDS_DSI regulator\n"); |
| 3916 | return PTR_ERR(vdds_dsi); |
| 3917 | } |
| 3918 | |
| 3919 | dsi.vdds_dsi_reg = vdds_dsi; |
| 3920 | } |
| 3921 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3922 | return 0; |
| 3923 | } |
| 3924 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 3925 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel) |
| 3926 | { |
| 3927 | int i; |
| 3928 | |
| 3929 | for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { |
| 3930 | if (!dsi.vc[i].dssdev) { |
| 3931 | dsi.vc[i].dssdev = dssdev; |
| 3932 | *channel = i; |
| 3933 | return 0; |
| 3934 | } |
| 3935 | } |
| 3936 | |
| 3937 | DSSERR("cannot get VC for display %s", dssdev->name); |
| 3938 | return -ENOSPC; |
| 3939 | } |
| 3940 | EXPORT_SYMBOL(omap_dsi_request_vc); |
| 3941 | |
| 3942 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) |
| 3943 | { |
| 3944 | if (vc_id < 0 || vc_id > 3) { |
| 3945 | DSSERR("VC ID out of range\n"); |
| 3946 | return -EINVAL; |
| 3947 | } |
| 3948 | |
| 3949 | if (channel < 0 || channel > 3) { |
| 3950 | DSSERR("Virtual Channel out of range\n"); |
| 3951 | return -EINVAL; |
| 3952 | } |
| 3953 | |
| 3954 | if (dsi.vc[channel].dssdev != dssdev) { |
| 3955 | DSSERR("Virtual Channel not allocated to display %s\n", |
| 3956 | dssdev->name); |
| 3957 | return -EINVAL; |
| 3958 | } |
| 3959 | |
| 3960 | dsi.vc[channel].vc_id = vc_id; |
| 3961 | |
| 3962 | return 0; |
| 3963 | } |
| 3964 | EXPORT_SYMBOL(omap_dsi_set_vc_id); |
| 3965 | |
| 3966 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel) |
| 3967 | { |
| 3968 | if ((channel >= 0 && channel <= 3) && |
| 3969 | dsi.vc[channel].dssdev == dssdev) { |
| 3970 | dsi.vc[channel].dssdev = NULL; |
| 3971 | dsi.vc[channel].vc_id = 0; |
| 3972 | } |
| 3973 | } |
| 3974 | EXPORT_SYMBOL(omap_dsi_release_vc); |
| 3975 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 3976 | void dsi_wait_pll_hsdiv_dispc_active(void) |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 3977 | { |
| 3978 | if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 3979 | DSSERR("%s (%s) not active\n", |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 3980 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
| 3981 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 3982 | } |
| 3983 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 3984 | void dsi_wait_pll_hsdiv_dsi_active(void) |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 3985 | { |
| 3986 | if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 3987 | DSSERR("%s (%s) not active\n", |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 3988 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
| 3989 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 3990 | } |
| 3991 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 3992 | static void dsi_calc_clock_param_ranges(void) |
| 3993 | { |
| 3994 | dsi.regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN); |
| 3995 | dsi.regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM); |
| 3996 | dsi.regm_dispc_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC); |
| 3997 | dsi.regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI); |
| 3998 | dsi.fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT); |
| 3999 | dsi.fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT); |
| 4000 | dsi.lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); |
| 4001 | } |
| 4002 | |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4003 | static int dsi_init(struct platform_device *pdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4004 | { |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 4005 | struct omap_display_platform_data *dss_plat_data; |
| 4006 | struct omap_dss_board_info *board_info; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4007 | u32 rev; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4008 | int r, i; |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 4009 | struct resource *dsi_mem; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4010 | |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 4011 | dss_plat_data = pdev->dev.platform_data; |
| 4012 | board_info = dss_plat_data->board_data; |
| 4013 | dsi.dsi_mux_pads = board_info->dsi_mux_pads; |
| 4014 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 4015 | spin_lock_init(&dsi.irq_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4016 | spin_lock_init(&dsi.errors_lock); |
| 4017 | dsi.errors = 0; |
| 4018 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 4019 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 4020 | spin_lock_init(&dsi.irq_stats_lock); |
| 4021 | dsi.irq_stats.last_reset = jiffies; |
| 4022 | #endif |
| 4023 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4024 | mutex_init(&dsi.lock); |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 4025 | sema_init(&dsi.bus_lock, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4026 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 4027 | dsi.workqueue = create_singlethread_workqueue("dsi"); |
| 4028 | if (dsi.workqueue == NULL) |
| 4029 | return -ENOMEM; |
| 4030 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4031 | INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work, |
| 4032 | dsi_framedone_timeout_work_callback); |
| 4033 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4034 | #ifdef DSI_CATCH_MISSING_TE |
| 4035 | init_timer(&dsi.te_timer); |
| 4036 | dsi.te_timer.function = dsi_te_timeout; |
| 4037 | dsi.te_timer.data = 0; |
| 4038 | #endif |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 4039 | dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0); |
| 4040 | if (!dsi_mem) { |
| 4041 | DSSERR("can't get IORESOURCE_MEM DSI\n"); |
| 4042 | r = -EINVAL; |
| 4043 | goto err1; |
| 4044 | } |
| 4045 | dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4046 | if (!dsi.base) { |
| 4047 | DSSERR("can't ioremap DSI\n"); |
| 4048 | r = -ENOMEM; |
| 4049 | goto err1; |
| 4050 | } |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4051 | dsi.irq = platform_get_irq(dsi.pdev, 0); |
| 4052 | if (dsi.irq < 0) { |
| 4053 | DSSERR("platform_get_irq failed\n"); |
| 4054 | r = -ENODEV; |
| 4055 | goto err2; |
| 4056 | } |
| 4057 | |
| 4058 | r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED, |
| 4059 | "OMAP DSI1", dsi.pdev); |
| 4060 | if (r < 0) { |
| 4061 | DSSERR("request_irq failed\n"); |
| 4062 | goto err2; |
| 4063 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4064 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4065 | /* DSI VCs initialization */ |
| 4066 | for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { |
| 4067 | dsi.vc[i].mode = DSI_VC_MODE_L4; |
| 4068 | dsi.vc[i].dssdev = NULL; |
| 4069 | dsi.vc[i].vc_id = 0; |
| 4070 | } |
| 4071 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 4072 | dsi_calc_clock_param_ranges(); |
| 4073 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4074 | enable_clocks(1); |
| 4075 | |
| 4076 | rev = dsi_read_reg(DSI_REVISION); |
Sumit Semwal | a06b62f | 2011-01-24 06:22:03 +0000 | [diff] [blame] | 4077 | dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4078 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
| 4079 | |
| 4080 | enable_clocks(0); |
| 4081 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4082 | return 0; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4083 | err2: |
| 4084 | iounmap(dsi.base); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4085 | err1: |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 4086 | destroy_workqueue(dsi.workqueue); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4087 | return r; |
| 4088 | } |
| 4089 | |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4090 | static void dsi_exit(void) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4091 | { |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4092 | if (dsi.vdds_dsi_reg != NULL) { |
Tomi Valkeinen | 88257b2 | 2010-12-20 16:26:22 +0200 | [diff] [blame^] | 4093 | if (dsi.vdds_dsi_enabled) { |
| 4094 | regulator_disable(dsi.vdds_dsi_reg); |
| 4095 | dsi.vdds_dsi_enabled = false; |
| 4096 | } |
| 4097 | |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4098 | regulator_put(dsi.vdds_dsi_reg); |
| 4099 | dsi.vdds_dsi_reg = NULL; |
| 4100 | } |
| 4101 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4102 | free_irq(dsi.irq, dsi.pdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4103 | iounmap(dsi.base); |
| 4104 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 4105 | destroy_workqueue(dsi.workqueue); |
| 4106 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4107 | DSSDBG("omap_dsi_exit\n"); |
| 4108 | } |
| 4109 | |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4110 | /* DSI1 HW IP initialisation */ |
| 4111 | static int omap_dsi1hw_probe(struct platform_device *pdev) |
| 4112 | { |
| 4113 | int r; |
| 4114 | dsi.pdev = pdev; |
| 4115 | r = dsi_init(pdev); |
| 4116 | if (r) { |
| 4117 | DSSERR("Failed to initialize DSI\n"); |
| 4118 | goto err_dsi; |
| 4119 | } |
| 4120 | err_dsi: |
| 4121 | return r; |
| 4122 | } |
| 4123 | |
| 4124 | static int omap_dsi1hw_remove(struct platform_device *pdev) |
| 4125 | { |
| 4126 | dsi_exit(); |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 4127 | WARN_ON(dsi.scp_clk_refcount > 0); |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4128 | return 0; |
| 4129 | } |
| 4130 | |
| 4131 | static struct platform_driver omap_dsi1hw_driver = { |
| 4132 | .probe = omap_dsi1hw_probe, |
| 4133 | .remove = omap_dsi1hw_remove, |
| 4134 | .driver = { |
| 4135 | .name = "omapdss_dsi1", |
| 4136 | .owner = THIS_MODULE, |
| 4137 | }, |
| 4138 | }; |
| 4139 | |
| 4140 | int dsi_init_platform_driver(void) |
| 4141 | { |
| 4142 | return platform_driver_register(&omap_dsi1hw_driver); |
| 4143 | } |
| 4144 | |
| 4145 | void dsi_uninit_platform_driver(void) |
| 4146 | { |
| 4147 | return platform_driver_unregister(&omap_dsi1hw_driver); |
| 4148 | } |