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gerrit-public.fairphone.software / kernel / msm-4.9 / 97b108f9a4aa8649be3816fcb8bc83614b76d6c6 / . / arch / arm / boot / dts / imx6qdl.dtsi
blob: 7707f2e200f0ac045437c5cea2f5e830d1246ac3 [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]31 intc: interrupt-controller@00a01000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 reg = <0x00a01000 0x1000>,
38 <0x00a00100 0x100>;
39 };
40
41 clocks {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 ckil {
46 compatible = "fsl,imx-ckil", "fixed-clock";
47 clock-frequency = <32768>;
48 };
49
50 ckih1 {
51 compatible = "fsl,imx-ckih1", "fixed-clock";
52 clock-frequency = <0>;
53 };
54
55 osc {
56 compatible = "fsl,imx-osc", "fixed-clock";
57 clock-frequency = <24000000>;
58 };
59 };
60
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
66 ranges;
67
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]68 dma_apbh: dma-apbh@00110000 {
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]71 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
72 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
73 #dma-cells = <1>;
74 dma-channels = <4>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]75 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]76 };
77
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]78 gpmi: gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]79 compatible = "fsl,imx6q-gpmi-nand";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
83 reg-names = "gpmi-nand", "bch";
84 interrupts = <0 13 0x04>, <0 15 0x04>;
85 interrupt-names = "gpmi-dma", "bch";
86 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
87 <&clks 150>, <&clks 149>;
88 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
89 "gpmi_bch_apb", "per1_bch";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]90 dmas = <&dma_apbh 0>;
91 dma-names = "rx-tx";
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]92 fsl,gpmi-dma-channel = <0>;
93 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]94 };
95
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]96 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]97 compatible = "arm,cortex-a9-twd-timer";
98 reg = <0x00a00600 0x20>;
99 interrupts = <1 13 0xf01>;
Shawn Guo2bb4b702013-04-03 23:50:09 +0800[diff] [blame]100 clocks = <&clks 15>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]101 };
102
103 L2: l2-cache@00a02000 {
104 compatible = "arm,pl310-cache";
105 reg = <0x00a02000 0x1000>;
106 interrupts = <0 92 0x04>;
107 cache-unified;
108 cache-level = <2>;
Dirk Behme5a5ca562013-04-26 10:13:55 +0200[diff] [blame]109 arm,tag-latency = <4 2 3>;
110 arm,data-latency = <4 2 3>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]111 };
112
Dirk Behme218abe62013-02-15 15:10:01 +0100[diff] [blame]113 pmu {
114 compatible = "arm,cortex-a9-pmu";
115 interrupts = <0 94 0x04>;
116 };
117
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]118 aips-bus@02000000 { /* AIPS1 */
119 compatible = "fsl,aips-bus", "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 reg = <0x02000000 0x100000>;
123 ranges;
124
125 spba-bus@02000000 {
126 compatible = "fsl,spba-bus", "simple-bus";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 reg = <0x02000000 0x40000>;
130 ranges;
131
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]132 spdif: spdif@02004000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]133 reg = <0x02004000 0x4000>;
134 interrupts = <0 52 0x04>;
135 };
136
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]137 ecspi1: ecspi@02008000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]138 #address-cells = <1>;
139 #size-cells = <0>;
140 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
141 reg = <0x02008000 0x4000>;
142 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]143 clocks = <&clks 112>, <&clks 112>;
144 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]145 status = "disabled";
146 };
147
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]148 ecspi2: ecspi@0200c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]149 #address-cells = <1>;
150 #size-cells = <0>;
151 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
152 reg = <0x0200c000 0x4000>;
153 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]154 clocks = <&clks 113>, <&clks 113>;
155 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]156 status = "disabled";
157 };
158
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]159 ecspi3: ecspi@02010000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
163 reg = <0x02010000 0x4000>;
164 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]165 clocks = <&clks 114>, <&clks 114>;
166 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]167 status = "disabled";
168 };
169
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]170 ecspi4: ecspi@02014000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
174 reg = <0x02014000 0x4000>;
175 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]176 clocks = <&clks 115>, <&clks 115>;
177 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]178 status = "disabled";
179 };
180
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]181 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]182 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
183 reg = <0x02020000 0x4000>;
184 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]185 clocks = <&clks 160>, <&clks 161>;
186 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]187 status = "disabled";
188 };
189
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]190 esai: esai@02024000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]191 reg = <0x02024000 0x4000>;
192 interrupts = <0 51 0x04>;
193 };
194
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]195 ssi1: ssi@02028000 {
196 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]197 reg = <0x02028000 0x4000>;
198 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]199 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]200 fsl,fifo-depth = <15>;
201 fsl,ssi-dma-events = <38 37>;
202 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]203 };
204
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]205 ssi2: ssi@0202c000 {
206 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]207 reg = <0x0202c000 0x4000>;
208 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]209 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]210 fsl,fifo-depth = <15>;
211 fsl,ssi-dma-events = <42 41>;
212 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]213 };
214
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]215 ssi3: ssi@02030000 {
216 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]217 reg = <0x02030000 0x4000>;
218 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]219 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]220 fsl,fifo-depth = <15>;
221 fsl,ssi-dma-events = <46 45>;
222 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]223 };
224
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]225 asrc: asrc@02034000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]226 reg = <0x02034000 0x4000>;
227 interrupts = <0 50 0x04>;
228 };
229
230 spba@0203c000 {
231 reg = <0x0203c000 0x4000>;
232 };
233 };
234
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]235 vpu: vpu@02040000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]236 reg = <0x02040000 0x3c000>;
237 interrupts = <0 3 0x04 0 12 0x04>;
238 };
239
240 aipstz@0207c000 { /* AIPSTZ1 */
241 reg = <0x0207c000 0x4000>;
242 };
243
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]244 pwm1: pwm@02080000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]245 #pwm-cells = <2>;
246 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]247 reg = <0x02080000 0x4000>;
248 interrupts = <0 83 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]249 clocks = <&clks 62>, <&clks 145>;
250 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]251 };
252
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]253 pwm2: pwm@02084000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]254 #pwm-cells = <2>;
255 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]256 reg = <0x02084000 0x4000>;
257 interrupts = <0 84 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]258 clocks = <&clks 62>, <&clks 146>;
259 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]260 };
261
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]262 pwm3: pwm@02088000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]263 #pwm-cells = <2>;
264 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]265 reg = <0x02088000 0x4000>;
266 interrupts = <0 85 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]267 clocks = <&clks 62>, <&clks 147>;
268 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]269 };
270
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]271 pwm4: pwm@0208c000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]272 #pwm-cells = <2>;
273 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]274 reg = <0x0208c000 0x4000>;
275 interrupts = <0 86 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]276 clocks = <&clks 62>, <&clks 148>;
277 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]278 };
279
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]280 can1: flexcan@02090000 {
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]281 compatible = "fsl,imx6q-flexcan";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]282 reg = <0x02090000 0x4000>;
283 interrupts = <0 110 0x04>;
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]284 clocks = <&clks 108>, <&clks 109>;
285 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]286 };
287
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]288 can2: flexcan@02094000 {
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]289 compatible = "fsl,imx6q-flexcan";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]290 reg = <0x02094000 0x4000>;
291 interrupts = <0 111 0x04>;
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]292 clocks = <&clks 110>, <&clks 111>;
293 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]294 };
295
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]296 gpt: gpt@02098000 {
Sascha Hauer97b108f2013-06-25 15:51:47 +0200[diff] [blame^]297 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]298 reg = <0x02098000 0x4000>;
299 interrupts = <0 55 0x04>;
Sascha Hauer4efccad2013-03-14 13:09:01 +0100[diff] [blame]300 clocks = <&clks 119>, <&clks 120>;
301 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]302 };
303
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]304 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]305 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]306 reg = <0x0209c000 0x4000>;
307 interrupts = <0 66 0x04 0 67 0x04>;
308 gpio-controller;
309 #gpio-cells = <2>;
310 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]311 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]312 };
313
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]314 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]315 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]316 reg = <0x020a0000 0x4000>;
317 interrupts = <0 68 0x04 0 69 0x04>;
318 gpio-controller;
319 #gpio-cells = <2>;
320 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]321 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]322 };
323
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]324 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]325 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]326 reg = <0x020a4000 0x4000>;
327 interrupts = <0 70 0x04 0 71 0x04>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]331 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]332 };
333
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]334 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]335 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]336 reg = <0x020a8000 0x4000>;
337 interrupts = <0 72 0x04 0 73 0x04>;
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]341 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]342 };
343
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]344 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]345 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]346 reg = <0x020ac000 0x4000>;
347 interrupts = <0 74 0x04 0 75 0x04>;
348 gpio-controller;
349 #gpio-cells = <2>;
350 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]351 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]352 };
353
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]354 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]355 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]356 reg = <0x020b0000 0x4000>;
357 interrupts = <0 76 0x04 0 77 0x04>;
358 gpio-controller;
359 #gpio-cells = <2>;
360 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]361 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]362 };
363
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]364 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]365 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]366 reg = <0x020b4000 0x4000>;
367 interrupts = <0 78 0x04 0 79 0x04>;
368 gpio-controller;
369 #gpio-cells = <2>;
370 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]371 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]372 };
373
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]374 kpp: kpp@020b8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]375 reg = <0x020b8000 0x4000>;
376 interrupts = <0 82 0x04>;
377 };
378
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]379 wdog1: wdog@020bc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]380 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
381 reg = <0x020bc000 0x4000>;
382 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]383 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]384 };
385
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]386 wdog2: wdog@020c0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]387 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
388 reg = <0x020c0000 0x4000>;
389 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]390 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]391 status = "disabled";
392 };
393
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]394 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]395 compatible = "fsl,imx6q-ccm";
396 reg = <0x020c4000 0x4000>;
397 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]398 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]399 };
400
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]401 anatop: anatop@020c8000 {
402 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]403 reg = <0x020c8000 0x1000>;
404 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]405
406 regulator-1p1@110 {
407 compatible = "fsl,anatop-regulator";
408 regulator-name = "vdd1p1";
409 regulator-min-microvolt = <800000>;
410 regulator-max-microvolt = <1375000>;
411 regulator-always-on;
412 anatop-reg-offset = <0x110>;
413 anatop-vol-bit-shift = <8>;
414 anatop-vol-bit-width = <5>;
415 anatop-min-bit-val = <4>;
416 anatop-min-voltage = <800000>;
417 anatop-max-voltage = <1375000>;
418 };
419
420 regulator-3p0@120 {
421 compatible = "fsl,anatop-regulator";
422 regulator-name = "vdd3p0";
423 regulator-min-microvolt = <2800000>;
424 regulator-max-microvolt = <3150000>;
425 regulator-always-on;
426 anatop-reg-offset = <0x120>;
427 anatop-vol-bit-shift = <8>;
428 anatop-vol-bit-width = <5>;
429 anatop-min-bit-val = <0>;
430 anatop-min-voltage = <2625000>;
431 anatop-max-voltage = <3400000>;
432 };
433
434 regulator-2p5@130 {
435 compatible = "fsl,anatop-regulator";
436 regulator-name = "vdd2p5";
437 regulator-min-microvolt = <2000000>;
438 regulator-max-microvolt = <2750000>;
439 regulator-always-on;
440 anatop-reg-offset = <0x130>;
441 anatop-vol-bit-shift = <8>;
442 anatop-vol-bit-width = <5>;
443 anatop-min-bit-val = <0>;
444 anatop-min-voltage = <2000000>;
445 anatop-max-voltage = <2750000>;
446 };
447
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]448 reg_arm: regulator-vddcore@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]449 compatible = "fsl,anatop-regulator";
450 regulator-name = "cpu";
451 regulator-min-microvolt = <725000>;
452 regulator-max-microvolt = <1450000>;
453 regulator-always-on;
454 anatop-reg-offset = <0x140>;
455 anatop-vol-bit-shift = <0>;
456 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]457 anatop-delay-reg-offset = <0x170>;
458 anatop-delay-bit-shift = <24>;
459 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]460 anatop-min-bit-val = <1>;
461 anatop-min-voltage = <725000>;
462 anatop-max-voltage = <1450000>;
463 };
464
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]465 reg_pu: regulator-vddpu@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]466 compatible = "fsl,anatop-regulator";
467 regulator-name = "vddpu";
468 regulator-min-microvolt = <725000>;
469 regulator-max-microvolt = <1450000>;
470 regulator-always-on;
471 anatop-reg-offset = <0x140>;
472 anatop-vol-bit-shift = <9>;
473 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]474 anatop-delay-reg-offset = <0x170>;
475 anatop-delay-bit-shift = <26>;
476 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]477 anatop-min-bit-val = <1>;
478 anatop-min-voltage = <725000>;
479 anatop-max-voltage = <1450000>;
480 };
481
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]482 reg_soc: regulator-vddsoc@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]483 compatible = "fsl,anatop-regulator";
484 regulator-name = "vddsoc";
485 regulator-min-microvolt = <725000>;
486 regulator-max-microvolt = <1450000>;
487 regulator-always-on;
488 anatop-reg-offset = <0x140>;
489 anatop-vol-bit-shift = <18>;
490 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]491 anatop-delay-reg-offset = <0x170>;
492 anatop-delay-bit-shift = <28>;
493 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]494 anatop-min-bit-val = <1>;
495 anatop-min-voltage = <725000>;
496 anatop-max-voltage = <1450000>;
497 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]498 };
499
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]500 usbphy1: usbphy@020c9000 {
501 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]502 reg = <0x020c9000 0x1000>;
503 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]504 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]505 };
506
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]507 usbphy2: usbphy@020ca000 {
508 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]509 reg = <0x020ca000 0x1000>;
510 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]511 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]512 };
513
514 snvs@020cc000 {
Shawn Guoc9250382012-07-02 20:13:03 +0800[diff] [blame]515 compatible = "fsl,sec-v4.0-mon", "simple-bus";
516 #address-cells = <1>;
517 #size-cells = <1>;
518 ranges = <0 0x020cc000 0x4000>;
519
520 snvs-rtc-lp@34 {
521 compatible = "fsl,sec-v4.0-mon-rtc-lp";
522 reg = <0x34 0x58>;
523 interrupts = <0 19 0x04 0 20 0x04>;
524 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]525 };
526
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]527 epit1: epit@020d0000 { /* EPIT1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]528 reg = <0x020d0000 0x4000>;
529 interrupts = <0 56 0x04>;
530 };
531
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]532 epit2: epit@020d4000 { /* EPIT2 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]533 reg = <0x020d4000 0x4000>;
534 interrupts = <0 57 0x04>;
535 };
536
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]537 src: src@020d8000 {
Philipp Zabelbd3d9242013-03-28 17:35:22 +0100[diff] [blame]538 compatible = "fsl,imx6q-src", "fsl,imx51-src";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]539 reg = <0x020d8000 0x4000>;
540 interrupts = <0 91 0x04 0 96 0x04>;
Philipp Zabel09ebf362013-03-28 17:35:20 +0100[diff] [blame]541 #reset-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]542 };
543
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]544 gpc: gpc@020dc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]545 compatible = "fsl,imx6q-gpc";
546 reg = <0x020dc000 0x4000>;
547 interrupts = <0 89 0x04 0 90 0x04>;
548 };
549
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]550 gpr: iomuxc-gpr@020e0000 {
551 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
552 reg = <0x020e0000 0x38>;
553 };
554
Steffen Trumtrar41c04342013-03-28 16:23:35 +0100[diff] [blame]555 ldb: ldb@020e0008 {
556 #address-cells = <1>;
557 #size-cells = <0>;
558 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
559 gpr = <&gpr>;
560 status = "disabled";
561
562 lvds-channel@0 {
563 reg = <0>;
564 crtcs = <&ipu1 0>;
565 status = "disabled";
566 };
567
568 lvds-channel@1 {
569 reg = <1>;
570 crtcs = <&ipu1 1>;
571 status = "disabled";
572 };
573 };
574
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]575 dcic1: dcic@020e4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]576 reg = <0x020e4000 0x4000>;
577 interrupts = <0 124 0x04>;
578 };
579
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]580 dcic2: dcic@020e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]581 reg = <0x020e8000 0x4000>;
582 interrupts = <0 125 0x04>;
583 };
584
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]585 sdma: sdma@020ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]586 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
587 reg = <0x020ec000 0x4000>;
588 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]589 clocks = <&clks 155>, <&clks 155>;
590 clock-names = "ipg", "ahb";
Fabio Estevamd6b9c592013-01-17 12:13:25 -0200[diff] [blame]591 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]592 };
593 };
594
595 aips-bus@02100000 { /* AIPS2 */
596 compatible = "fsl,aips-bus", "simple-bus";
597 #address-cells = <1>;
598 #size-cells = <1>;
599 reg = <0x02100000 0x100000>;
600 ranges;
601
602 caam@02100000 {
603 reg = <0x02100000 0x40000>;
604 interrupts = <0 105 0x04 0 106 0x04>;
605 };
606
607 aipstz@0217c000 { /* AIPSTZ2 */
608 reg = <0x0217c000 0x4000>;
609 };
610
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]611 usbotg: usb@02184000 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]612 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
613 reg = <0x02184000 0x200>;
614 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]615 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]616 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]617 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]618 status = "disabled";
619 };
620
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]621 usbh1: usb@02184200 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]622 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
623 reg = <0x02184200 0x200>;
624 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]625 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]626 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]627 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]628 status = "disabled";
629 };
630
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]631 usbh2: usb@02184400 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]632 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
633 reg = <0x02184400 0x200>;
634 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]635 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]636 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]637 status = "disabled";
638 };
639
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]640 usbh3: usb@02184600 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]641 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
642 reg = <0x02184600 0x200>;
643 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]644 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]645 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]646 status = "disabled";
647 };
648
Shawn Guo60984bd2013-04-28 09:59:54 +0800[diff] [blame]649 usbmisc: usbmisc@02184800 {
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]650 #index-cells = <1>;
651 compatible = "fsl,imx6q-usbmisc";
652 reg = <0x02184800 0x200>;
653 clocks = <&clks 162>;
654 };
655
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]656 fec: ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]657 compatible = "fsl,imx6q-fec";
658 reg = <0x02188000 0x4000>;
659 interrupts = <0 118 0x04 0 119 0x04>;
Frank Li8dd5c662013-02-05 14:21:06 +0800[diff] [blame]660 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame]661 clock-names = "ipg", "ahb", "ptp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]662 status = "disabled";
663 };
664
665 mlb@0218c000 {
666 reg = <0x0218c000 0x4000>;
667 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
668 };
669
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]670 usdhc1: usdhc@02190000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]671 compatible = "fsl,imx6q-usdhc";
672 reg = <0x02190000 0x4000>;
673 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]674 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
675 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]676 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]677 status = "disabled";
678 };
679
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]680 usdhc2: usdhc@02194000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]681 compatible = "fsl,imx6q-usdhc";
682 reg = <0x02194000 0x4000>;
683 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]684 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
685 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]686 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]687 status = "disabled";
688 };
689
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]690 usdhc3: usdhc@02198000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]691 compatible = "fsl,imx6q-usdhc";
692 reg = <0x02198000 0x4000>;
693 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]694 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
695 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]696 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]697 status = "disabled";
698 };
699
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]700 usdhc4: usdhc@0219c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]701 compatible = "fsl,imx6q-usdhc";
702 reg = <0x0219c000 0x4000>;
703 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]704 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
705 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]706 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]707 status = "disabled";
708 };
709
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]710 i2c1: i2c@021a0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]711 #address-cells = <1>;
712 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]713 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]714 reg = <0x021a0000 0x4000>;
715 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]716 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]717 status = "disabled";
718 };
719
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]720 i2c2: i2c@021a4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]721 #address-cells = <1>;
722 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]723 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]724 reg = <0x021a4000 0x4000>;
725 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]726 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]727 status = "disabled";
728 };
729
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]730 i2c3: i2c@021a8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]731 #address-cells = <1>;
732 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]733 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]734 reg = <0x021a8000 0x4000>;
735 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]736 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]737 status = "disabled";
738 };
739
740 romcp@021ac000 {
741 reg = <0x021ac000 0x4000>;
742 };
743
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]744 mmdc0: mmdc@021b0000 { /* MMDC0 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]745 compatible = "fsl,imx6q-mmdc";
746 reg = <0x021b0000 0x4000>;
747 };
748
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]749 mmdc1: mmdc@021b4000 { /* MMDC1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]750 reg = <0x021b4000 0x4000>;
751 };
752
Huang Shijie05e3f8e2013-05-28 14:20:09 +0800[diff] [blame]753 weim: weim@021b8000 {
754 compatible = "fsl,imx6q-weim";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]755 reg = <0x021b8000 0x4000>;
756 interrupts = <0 14 0x04>;
Huang Shijie05e3f8e2013-05-28 14:20:09 +0800[diff] [blame]757 clocks = <&clks 196>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]758 };
759
760 ocotp@021bc000 {
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]761 compatible = "fsl,imx6q-ocotp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]762 reg = <0x021bc000 0x4000>;
763 };
764
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]765 tzasc@021d0000 { /* TZASC1 */
766 reg = <0x021d0000 0x4000>;
767 interrupts = <0 108 0x04>;
768 };
769
770 tzasc@021d4000 { /* TZASC2 */
771 reg = <0x021d4000 0x4000>;
772 interrupts = <0 109 0x04>;
773 };
774
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]775 audmux: audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]776 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]777 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]778 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]779 };
780
781 mipi@021dc000 { /* MIPI-CSI */
782 reg = <0x021dc000 0x4000>;
783 };
784
785 mipi@021e0000 { /* MIPI-DSI */
786 reg = <0x021e0000 0x4000>;
787 };
788
789 vdoa@021e4000 {
790 reg = <0x021e4000 0x4000>;
791 interrupts = <0 18 0x04>;
792 };
793
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]794 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]795 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
796 reg = <0x021e8000 0x4000>;
797 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]798 clocks = <&clks 160>, <&clks 161>;
799 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]800 status = "disabled";
801 };
802
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]803 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]804 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
805 reg = <0x021ec000 0x4000>;
806 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]807 clocks = <&clks 160>, <&clks 161>;
808 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]809 status = "disabled";
810 };
811
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]812 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]813 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
814 reg = <0x021f0000 0x4000>;
815 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]816 clocks = <&clks 160>, <&clks 161>;
817 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]818 status = "disabled";
819 };
820
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]821 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]822 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
823 reg = <0x021f4000 0x4000>;
824 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]825 clocks = <&clks 160>, <&clks 161>;
826 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]827 status = "disabled";
828 };
829 };
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]830
831 ipu1: ipu@02400000 {
832 #crtc-cells = <1>;
833 compatible = "fsl,imx6q-ipu";
834 reg = <0x02400000 0x400000>;
835 interrupts = <0 6 0x4 0 5 0x4>;
836 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
837 clock-names = "bus", "di0", "di1";
Philipp Zabel09ebf362013-03-28 17:35:20 +0100[diff] [blame]838 resets = <&src 2>;
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]839 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]840 };
841};