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gerrit-public.fairphone.software / kernel / msm-4.9 / 9c096da775af00af83a929769a6ac74bd291b3fe / . / arch / arm / boot / dts / imx28.dtsi
blob: 0ad893bf5f431c545199a04dafb4d894940ea0c3 [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Michael Heimpold25fc2282014-03-27 23:51:29 +0100[diff] [blame]12#include <dt-bindings/gpio/gpio.h>
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]13#include "skeleton.dtsi"
14#include "imx28-pinfunc.h"
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]15
16/ {
17 interrupt-parent = <&icoll>;
18
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]19 aliases {
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]20 ethernet0 = &mac0;
21 ethernet1 = &mac1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]27 saif0 = &saif0;
28 saif1 = &saif1;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]29 serial0 = &auart0;
30 serial1 = &auart1;
31 serial2 = &auart2;
32 serial3 = &auart3;
33 serial4 = &auart4;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]34 spi0 = &ssp1;
35 spi1 = &ssp2;
Peter Chen1f35cc62013-12-20 15:52:05 +0800[diff] [blame]36 usbphy0 = &usbphy0;
37 usbphy1 = &usbphy1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]38 };
39
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]40 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]41 #address-cells = <0>;
42 #size-cells = <0>;
43
44 cpu {
45 compatible = "arm,arm926ej-s";
46 device_type = "cpu";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]47 };
48 };
49
50 apb@80000000 {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 reg = <0x80000000 0x80000>;
55 ranges;
56
57 apbh@80000000 {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0x80000000 0x3c900>;
62 ranges;
63
64 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]65 compatible = "fsl,imx28-icoll", "fsl,icoll";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]66 interrupt-controller;
67 #interrupt-cells = <1>;
68 reg = <0x80000000 0x2000>;
69 };
70
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]71 hsadc: hsadc@80002000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]72 reg = <0x80002000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]73 interrupts = <13>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]74 dmas = <&dma_apbh 12>;
75 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]76 status = "disabled";
77 };
78
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]79 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]80 compatible = "fsl,imx28-dma-apbh";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]81 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]82 interrupts = <82 83 84 85
83 88 88 88 88
84 88 88 88 88
85 87 86 0 0>;
86 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
87 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
88 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
89 "hsadc", "lcdif", "empty", "empty";
90 #dma-cells = <1>;
91 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]92 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]93 };
94
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]95 perfmon: perfmon@80006000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]96 reg = <0x80006000 0x800>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]97 interrupts = <27>;
98 status = "disabled";
99 };
100
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]101 gpmi: gpmi-nand@8000c000 {
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]102 compatible = "fsl,imx28-gpmi-nand";
103 #address-cells = <1>;
104 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]105 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]106 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]107 interrupts = <41>;
108 interrupt-names = "bch";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]109 clocks = <&clks 50>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]110 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]111 dmas = <&dma_apbh 4>;
112 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]113 status = "disabled";
114 };
115
116 ssp0: ssp@80010000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]117 #address-cells = <1>;
118 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]119 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]120 interrupts = <96>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]121 clocks = <&clks 46>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]122 dmas = <&dma_apbh 0>;
123 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]124 status = "disabled";
125 };
126
127 ssp1: ssp@80012000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]128 #address-cells = <1>;
129 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]130 reg = <0x80012000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]131 interrupts = <97>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]132 clocks = <&clks 47>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]133 dmas = <&dma_apbh 1>;
134 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]135 status = "disabled";
136 };
137
138 ssp2: ssp@80014000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]139 #address-cells = <1>;
140 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]141 reg = <0x80014000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]142 interrupts = <98>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]143 clocks = <&clks 48>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]144 dmas = <&dma_apbh 2>;
145 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]146 status = "disabled";
147 };
148
149 ssp3: ssp@80016000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]150 #address-cells = <1>;
151 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]152 reg = <0x80016000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]153 interrupts = <99>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]154 clocks = <&clks 49>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]155 dmas = <&dma_apbh 3>;
156 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]157 status = "disabled";
158 };
159
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]160 pinctrl: pinctrl@80018000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]161 #address-cells = <1>;
162 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]163 compatible = "fsl,imx28-pinctrl", "simple-bus";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]164 reg = <0x80018000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]165
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]166 gpio0: gpio@0 {
167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]168 reg = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]169 interrupts = <127>;
170 gpio-controller;
171 #gpio-cells = <2>;
172 interrupt-controller;
173 #interrupt-cells = <2>;
174 };
175
176 gpio1: gpio@1 {
177 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]178 reg = <1>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]179 interrupts = <126>;
180 gpio-controller;
181 #gpio-cells = <2>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 };
185
186 gpio2: gpio@2 {
187 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]188 reg = <2>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]189 interrupts = <125>;
190 gpio-controller;
191 #gpio-cells = <2>;
192 interrupt-controller;
193 #interrupt-cells = <2>;
194 };
195
196 gpio3: gpio@3 {
197 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]198 reg = <3>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]199 interrupts = <124>;
200 gpio-controller;
201 #gpio-cells = <2>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 };
205
206 gpio4: gpio@4 {
207 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]208 reg = <4>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]209 interrupts = <123>;
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 };
215
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]216 duart_pins_a: duart@0 {
217 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]218 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]219 MX28_PAD_PWM0__DUART_RX
220 MX28_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]221 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]222 fsl,drive-strength = <MXS_DRIVE_4mA>;
223 fsl,voltage = <MXS_VOLTAGE_HIGH>;
224 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]225 };
226
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]227 duart_pins_b: duart@1 {
228 reg = <1>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]229 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]230 MX28_PAD_AUART0_CTS__DUART_RX
231 MX28_PAD_AUART0_RTS__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]232 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]233 fsl,drive-strength = <MXS_DRIVE_4mA>;
234 fsl,voltage = <MXS_VOLTAGE_HIGH>;
235 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]236 };
237
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]238 duart_4pins_a: duart-4pins@0 {
239 reg = <0>;
240 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]241 MX28_PAD_AUART0_CTS__DUART_RX
242 MX28_PAD_AUART0_RTS__DUART_TX
243 MX28_PAD_AUART0_RX__DUART_CTS
244 MX28_PAD_AUART0_TX__DUART_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]245 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]246 fsl,drive-strength = <MXS_DRIVE_4mA>;
247 fsl,voltage = <MXS_VOLTAGE_HIGH>;
248 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]249 };
250
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]251 gpmi_pins_a: gpmi-nand@0 {
252 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]253 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]254 MX28_PAD_GPMI_D00__GPMI_D0
255 MX28_PAD_GPMI_D01__GPMI_D1
256 MX28_PAD_GPMI_D02__GPMI_D2
257 MX28_PAD_GPMI_D03__GPMI_D3
258 MX28_PAD_GPMI_D04__GPMI_D4
259 MX28_PAD_GPMI_D05__GPMI_D5
260 MX28_PAD_GPMI_D06__GPMI_D6
261 MX28_PAD_GPMI_D07__GPMI_D7
262 MX28_PAD_GPMI_CE0N__GPMI_CE0N
263 MX28_PAD_GPMI_RDY0__GPMI_READY0
264 MX28_PAD_GPMI_RDN__GPMI_RDN
265 MX28_PAD_GPMI_WRN__GPMI_WRN
266 MX28_PAD_GPMI_ALE__GPMI_ALE
267 MX28_PAD_GPMI_CLE__GPMI_CLE
268 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]269 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]270 fsl,drive-strength = <MXS_DRIVE_4mA>;
271 fsl,voltage = <MXS_VOLTAGE_HIGH>;
272 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]273 };
274
275 gpmi_status_cfg: gpmi-status-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]276 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]277 MX28_PAD_GPMI_RDN__GPMI_RDN
278 MX28_PAD_GPMI_WRN__GPMI_WRN
279 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]280 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]281 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]282 };
283
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]284 auart0_pins_a: auart0@0 {
285 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]286 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]287 MX28_PAD_AUART0_RX__AUART0_RX
288 MX28_PAD_AUART0_TX__AUART0_TX
289 MX28_PAD_AUART0_CTS__AUART0_CTS
290 MX28_PAD_AUART0_RTS__AUART0_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]291 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]292 fsl,drive-strength = <MXS_DRIVE_4mA>;
293 fsl,voltage = <MXS_VOLTAGE_HIGH>;
294 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]295 };
296
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]297 auart0_2pins_a: auart0-2pins@0 {
298 reg = <0>;
299 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]300 MX28_PAD_AUART0_RX__AUART0_RX
301 MX28_PAD_AUART0_TX__AUART0_TX
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]302 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]303 fsl,drive-strength = <MXS_DRIVE_4mA>;
304 fsl,voltage = <MXS_VOLTAGE_HIGH>;
305 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]306 };
307
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]308 auart1_pins_a: auart1@0 {
309 reg = <0>;
310 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]311 MX28_PAD_AUART1_RX__AUART1_RX
312 MX28_PAD_AUART1_TX__AUART1_TX
313 MX28_PAD_AUART1_CTS__AUART1_CTS
314 MX28_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]315 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]316 fsl,drive-strength = <MXS_DRIVE_4mA>;
317 fsl,voltage = <MXS_VOLTAGE_HIGH>;
318 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]319 };
320
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]321 auart1_2pins_a: auart1-2pins@0 {
322 reg = <0>;
323 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]324 MX28_PAD_AUART1_RX__AUART1_RX
325 MX28_PAD_AUART1_TX__AUART1_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]326 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]327 fsl,drive-strength = <MXS_DRIVE_4mA>;
328 fsl,voltage = <MXS_VOLTAGE_HIGH>;
329 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]330 };
331
332 auart2_2pins_a: auart2-2pins@0 {
333 reg = <0>;
334 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]335 MX28_PAD_SSP2_SCK__AUART2_RX
336 MX28_PAD_SSP2_MOSI__AUART2_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]337 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]338 fsl,drive-strength = <MXS_DRIVE_4mA>;
339 fsl,voltage = <MXS_VOLTAGE_HIGH>;
340 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]341 };
342
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]343 auart2_2pins_b: auart2-2pins@1 {
344 reg = <1>;
345 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]346 MX28_PAD_AUART2_RX__AUART2_RX
347 MX28_PAD_AUART2_TX__AUART2_TX
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]348 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]349 fsl,drive-strength = <MXS_DRIVE_4mA>;
350 fsl,voltage = <MXS_VOLTAGE_HIGH>;
351 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]352 };
353
Aida Mynzhasovacd0214c2013-10-23 10:58:57 +0400[diff] [blame]354 auart2_pins_a: auart2-pins@0 {
355 reg = <0>;
356 fsl,pinmux-ids = <
357 MX28_PAD_AUART2_RX__AUART2_RX
358 MX28_PAD_AUART2_TX__AUART2_TX
359 MX28_PAD_AUART2_CTS__AUART2_CTS
360 MX28_PAD_AUART2_RTS__AUART2_RTS
361 >;
362 fsl,drive-strength = <MXS_DRIVE_4mA>;
363 fsl,voltage = <MXS_VOLTAGE_HIGH>;
364 fsl,pull-up = <MXS_PULL_DISABLE>;
365 };
366
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]367 auart3_pins_a: auart3@0 {
368 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]369 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]370 MX28_PAD_AUART3_RX__AUART3_RX
371 MX28_PAD_AUART3_TX__AUART3_TX
372 MX28_PAD_AUART3_CTS__AUART3_CTS
373 MX28_PAD_AUART3_RTS__AUART3_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]374 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]375 fsl,drive-strength = <MXS_DRIVE_4mA>;
376 fsl,voltage = <MXS_VOLTAGE_HIGH>;
377 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]378 };
379
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]380 auart3_2pins_a: auart3-2pins@0 {
381 reg = <0>;
382 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]383 MX28_PAD_SSP2_MISO__AUART3_RX
384 MX28_PAD_SSP2_SS0__AUART3_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]385 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]386 fsl,drive-strength = <MXS_DRIVE_4mA>;
387 fsl,voltage = <MXS_VOLTAGE_HIGH>;
388 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]389 };
390
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]391 auart3_2pins_b: auart3-2pins@1 {
392 reg = <1>;
393 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]394 MX28_PAD_AUART3_RX__AUART3_RX
395 MX28_PAD_AUART3_TX__AUART3_TX
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]396 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]397 fsl,drive-strength = <MXS_DRIVE_4mA>;
398 fsl,voltage = <MXS_VOLTAGE_HIGH>;
399 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]400 };
401
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]402 auart4_2pins_a: auart4@0 {
403 reg = <0>;
404 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]405 MX28_PAD_SSP3_SCK__AUART4_TX
406 MX28_PAD_SSP3_MOSI__AUART4_RX
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]407 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]408 fsl,drive-strength = <MXS_DRIVE_4mA>;
409 fsl,voltage = <MXS_VOLTAGE_HIGH>;
410 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]411 };
412
Mans Rullgardcfa1dd92015-12-11 13:36:26 +0000[diff] [blame]413 auart4_2pins_b: auart4@1 {
414 reg = <1>;
415 fsl,pinmux-ids = <
416 MX28_PAD_AUART0_CTS__AUART4_RX
417 MX28_PAD_AUART0_RTS__AUART4_TX
418 >;
419 fsl,drive-strength = <MXS_DRIVE_4mA>;
420 fsl,voltage = <MXS_VOLTAGE_HIGH>;
421 fsl,pull-up = <MXS_PULL_DISABLE>;
422 };
423
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]424 mac0_pins_a: mac0@0 {
425 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]426 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]427 MX28_PAD_ENET0_MDC__ENET0_MDC
428 MX28_PAD_ENET0_MDIO__ENET0_MDIO
429 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
430 MX28_PAD_ENET0_RXD0__ENET0_RXD0
431 MX28_PAD_ENET0_RXD1__ENET0_RXD1
432 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
433 MX28_PAD_ENET0_TXD0__ENET0_TXD0
434 MX28_PAD_ENET0_TXD1__ENET0_TXD1
435 MX28_PAD_ENET_CLK__CLKCTRL_ENET
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]436 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]437 fsl,drive-strength = <MXS_DRIVE_8mA>;
438 fsl,voltage = <MXS_VOLTAGE_HIGH>;
439 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]440 };
441
Uwe Kleine-König9eb7db12016-04-06 09:32:59 +0200[diff] [blame]442 mac0_pins_b: mac0@1 {
443 reg = <1>;
444 fsl,pinmux-ids = <
445 MX28_PAD_ENET0_MDC__ENET0_MDC
446 MX28_PAD_ENET0_MDIO__ENET0_MDIO
447 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
448 MX28_PAD_ENET0_RXD0__ENET0_RXD0
449 MX28_PAD_ENET0_RXD1__ENET0_RXD1
450 MX28_PAD_ENET0_RXD2__ENET0_RXD2
451 MX28_PAD_ENET0_RXD3__ENET0_RXD3
452 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
453 MX28_PAD_ENET0_TXD0__ENET0_TXD0
454 MX28_PAD_ENET0_TXD1__ENET0_TXD1
455 MX28_PAD_ENET0_TXD2__ENET0_TXD2
456 MX28_PAD_ENET0_TXD3__ENET0_TXD3
457 MX28_PAD_ENET_CLK__CLKCTRL_ENET
458 MX28_PAD_ENET0_COL__ENET0_COL
459 MX28_PAD_ENET0_CRS__ENET0_CRS
460 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
461 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
462 >;
463 fsl,drive-strength = <MXS_DRIVE_8mA>;
464 fsl,voltage = <MXS_VOLTAGE_HIGH>;
465 fsl,pull-up = <MXS_PULL_ENABLE>;
466 };
467
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]468 mac1_pins_a: mac1@0 {
469 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]470 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]471 MX28_PAD_ENET0_CRS__ENET1_RX_EN
472 MX28_PAD_ENET0_RXD2__ENET1_RXD0
473 MX28_PAD_ENET0_RXD3__ENET1_RXD1
474 MX28_PAD_ENET0_COL__ENET1_TX_EN
475 MX28_PAD_ENET0_TXD2__ENET1_TXD0
476 MX28_PAD_ENET0_TXD3__ENET1_TXD1
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]477 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]478 fsl,drive-strength = <MXS_DRIVE_8mA>;
479 fsl,voltage = <MXS_VOLTAGE_HIGH>;
480 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]481 };
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]482
483 mmc0_8bit_pins_a: mmc0-8bit@0 {
484 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]485 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]486 MX28_PAD_SSP0_DATA0__SSP0_D0
487 MX28_PAD_SSP0_DATA1__SSP0_D1
488 MX28_PAD_SSP0_DATA2__SSP0_D2
489 MX28_PAD_SSP0_DATA3__SSP0_D3
490 MX28_PAD_SSP0_DATA4__SSP0_D4
491 MX28_PAD_SSP0_DATA5__SSP0_D5
492 MX28_PAD_SSP0_DATA6__SSP0_D6
493 MX28_PAD_SSP0_DATA7__SSP0_D7
494 MX28_PAD_SSP0_CMD__SSP0_CMD
495 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
496 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]497 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]498 fsl,drive-strength = <MXS_DRIVE_8mA>;
499 fsl,voltage = <MXS_VOLTAGE_HIGH>;
500 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]501 };
502
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]503 mmc0_4bit_pins_a: mmc0-4bit@0 {
504 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]505 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]506 MX28_PAD_SSP0_DATA0__SSP0_D0
507 MX28_PAD_SSP0_DATA1__SSP0_D1
508 MX28_PAD_SSP0_DATA2__SSP0_D2
509 MX28_PAD_SSP0_DATA3__SSP0_D3
510 MX28_PAD_SSP0_CMD__SSP0_CMD
511 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
512 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]513 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]514 fsl,drive-strength = <MXS_DRIVE_8mA>;
515 fsl,voltage = <MXS_VOLTAGE_HIGH>;
516 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]517 };
518
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]519 mmc0_cd_cfg: mmc0-cd-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]520 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]521 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]522 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]523 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]524 };
525
526 mmc0_sck_cfg: mmc0-sck-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]527 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]528 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]529 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]530 fsl,drive-strength = <MXS_DRIVE_12mA>;
531 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]532 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]533
Marc Kleine-Budde77d63862014-08-08 11:24:21 +0200[diff] [blame]534 mmc1_4bit_pins_a: mmc1-4bit@0 {
535 reg = <0>;
536 fsl,pinmux-ids = <
537 MX28_PAD_GPMI_D00__SSP1_D0
538 MX28_PAD_GPMI_D01__SSP1_D1
539 MX28_PAD_GPMI_D02__SSP1_D2
540 MX28_PAD_GPMI_D03__SSP1_D3
541 MX28_PAD_GPMI_RDY1__SSP1_CMD
542 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
543 MX28_PAD_GPMI_WRN__SSP1_SCK
544 >;
545 fsl,drive-strength = <MXS_DRIVE_8mA>;
546 fsl,voltage = <MXS_VOLTAGE_HIGH>;
547 fsl,pull-up = <MXS_PULL_ENABLE>;
548 };
549
550 mmc1_cd_cfg: mmc1-cd-cfg {
551 fsl,pinmux-ids = <
552 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
553 >;
554 fsl,pull-up = <MXS_PULL_DISABLE>;
555 };
556
557 mmc1_sck_cfg: mmc1-sck-cfg {
558 fsl,pinmux-ids = <
559 MX28_PAD_GPMI_WRN__SSP1_SCK
560 >;
561 fsl,drive-strength = <MXS_DRIVE_12mA>;
562 fsl,pull-up = <MXS_PULL_DISABLE>;
563 };
564
565
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]566 mmc2_4bit_pins_a: mmc2-4bit@0 {
567 reg = <0>;
568 fsl,pinmux-ids = <
569 MX28_PAD_SSP0_DATA4__SSP2_D0
570 MX28_PAD_SSP1_SCK__SSP2_D1
571 MX28_PAD_SSP1_CMD__SSP2_D2
572 MX28_PAD_SSP0_DATA5__SSP2_D3
573 MX28_PAD_SSP0_DATA6__SSP2_CMD
574 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
575 MX28_PAD_SSP0_DATA7__SSP2_SCK
576 >;
577 fsl,drive-strength = <MXS_DRIVE_8mA>;
578 fsl,voltage = <MXS_VOLTAGE_HIGH>;
579 fsl,pull-up = <MXS_PULL_ENABLE>;
580 };
581
582 mmc2_cd_cfg: mmc2-cd-cfg {
583 fsl,pinmux-ids = <
584 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
585 >;
586 fsl,pull-up = <MXS_PULL_DISABLE>;
587 };
588
589 mmc2_sck_cfg: mmc2-sck-cfg {
590 fsl,pinmux-ids = <
591 MX28_PAD_SSP0_DATA7__SSP2_SCK
592 >;
593 fsl,drive-strength = <MXS_DRIVE_12mA>;
594 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]595 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]596
597 i2c0_pins_a: i2c0@0 {
598 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]599 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]600 MX28_PAD_I2C0_SCL__I2C0_SCL
601 MX28_PAD_I2C0_SDA__I2C0_SDA
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]602 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]603 fsl,drive-strength = <MXS_DRIVE_8mA>;
604 fsl,voltage = <MXS_VOLTAGE_HIGH>;
605 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]606 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]607
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]608 i2c0_pins_b: i2c0@1 {
609 reg = <1>;
610 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]611 MX28_PAD_AUART0_RX__I2C0_SCL
612 MX28_PAD_AUART0_TX__I2C0_SDA
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]613 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]614 fsl,drive-strength = <MXS_DRIVE_8mA>;
615 fsl,voltage = <MXS_VOLTAGE_HIGH>;
616 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]617 };
618
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]619 i2c1_pins_a: i2c1@0 {
620 reg = <0>;
621 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]622 MX28_PAD_PWM0__I2C1_SCL
623 MX28_PAD_PWM1__I2C1_SDA
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]624 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]625 fsl,drive-strength = <MXS_DRIVE_8mA>;
626 fsl,voltage = <MXS_VOLTAGE_HIGH>;
627 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]628 };
629
Uwe Kleine-König17c63dd2014-08-08 11:24:22 +0200[diff] [blame]630 i2c1_pins_b: i2c1@1 {
631 reg = <1>;
632 fsl,pinmux-ids = <
633 MX28_PAD_AUART2_CTS__I2C1_SCL
634 MX28_PAD_AUART2_RTS__I2C1_SDA
635 >;
636 fsl,drive-strength = <MXS_DRIVE_8mA>;
637 fsl,voltage = <MXS_VOLTAGE_HIGH>;
638 fsl,pull-up = <MXS_PULL_ENABLE>;
639 };
640
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]641 saif0_pins_a: saif0@0 {
642 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]643 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]644 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
645 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
646 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
647 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]648 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]649 fsl,drive-strength = <MXS_DRIVE_12mA>;
650 fsl,voltage = <MXS_VOLTAGE_HIGH>;
651 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]652 };
653
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]654 saif0_pins_b: saif0@1 {
655 reg = <1>;
656 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]657 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
658 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
659 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]660 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]661 fsl,drive-strength = <MXS_DRIVE_12mA>;
662 fsl,voltage = <MXS_VOLTAGE_HIGH>;
663 fsl,pull-up = <MXS_PULL_ENABLE>;
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]664 };
665
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]666 saif1_pins_a: saif1@0 {
667 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]668 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]669 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]670 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]671 fsl,drive-strength = <MXS_DRIVE_12mA>;
672 fsl,voltage = <MXS_VOLTAGE_HIGH>;
673 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]674 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]675
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]676 pwm0_pins_a: pwm0@0 {
677 reg = <0>;
678 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]679 MX28_PAD_PWM0__PWM_0
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]680 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]681 fsl,drive-strength = <MXS_DRIVE_4mA>;
682 fsl,voltage = <MXS_VOLTAGE_HIGH>;
683 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]684 };
685
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]686 pwm2_pins_a: pwm2@0 {
687 reg = <0>;
688 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]689 MX28_PAD_PWM2__PWM_2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]690 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]691 fsl,drive-strength = <MXS_DRIVE_4mA>;
692 fsl,voltage = <MXS_VOLTAGE_HIGH>;
693 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]694 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]695
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]696 pwm3_pins_a: pwm3@0 {
697 reg = <0>;
698 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]699 MX28_PAD_PWM3__PWM_3
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]700 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]701 fsl,drive-strength = <MXS_DRIVE_4mA>;
702 fsl,voltage = <MXS_VOLTAGE_HIGH>;
703 fsl,pull-up = <MXS_PULL_DISABLE>;
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]704 };
705
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]706 pwm3_pins_b: pwm3@1 {
707 reg = <1>;
708 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]709 MX28_PAD_SAIF0_MCLK__PWM_3
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]710 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]711 fsl,drive-strength = <MXS_DRIVE_4mA>;
712 fsl,voltage = <MXS_VOLTAGE_HIGH>;
713 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]714 };
715
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]716 pwm4_pins_a: pwm4@0 {
717 reg = <0>;
718 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]719 MX28_PAD_PWM4__PWM_4
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]720 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]721 fsl,drive-strength = <MXS_DRIVE_4mA>;
722 fsl,voltage = <MXS_VOLTAGE_HIGH>;
723 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]724 };
725
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]726 lcdif_24bit_pins_a: lcdif-24bit@0 {
727 reg = <0>;
728 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]729 MX28_PAD_LCD_D00__LCD_D0
730 MX28_PAD_LCD_D01__LCD_D1
731 MX28_PAD_LCD_D02__LCD_D2
732 MX28_PAD_LCD_D03__LCD_D3
733 MX28_PAD_LCD_D04__LCD_D4
734 MX28_PAD_LCD_D05__LCD_D5
735 MX28_PAD_LCD_D06__LCD_D6
736 MX28_PAD_LCD_D07__LCD_D7
737 MX28_PAD_LCD_D08__LCD_D8
738 MX28_PAD_LCD_D09__LCD_D9
739 MX28_PAD_LCD_D10__LCD_D10
740 MX28_PAD_LCD_D11__LCD_D11
741 MX28_PAD_LCD_D12__LCD_D12
742 MX28_PAD_LCD_D13__LCD_D13
743 MX28_PAD_LCD_D14__LCD_D14
744 MX28_PAD_LCD_D15__LCD_D15
745 MX28_PAD_LCD_D16__LCD_D16
746 MX28_PAD_LCD_D17__LCD_D17
747 MX28_PAD_LCD_D18__LCD_D18
748 MX28_PAD_LCD_D19__LCD_D19
749 MX28_PAD_LCD_D20__LCD_D20
750 MX28_PAD_LCD_D21__LCD_D21
751 MX28_PAD_LCD_D22__LCD_D22
752 MX28_PAD_LCD_D23__LCD_D23
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]753 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]754 fsl,drive-strength = <MXS_DRIVE_4mA>;
755 fsl,voltage = <MXS_VOLTAGE_HIGH>;
756 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]757 };
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]758
Denis Carikliec985eb2013-12-05 14:28:04 +0100[diff] [blame]759 lcdif_18bit_pins_a: lcdif-18bit@0 {
760 reg = <0>;
761 fsl,pinmux-ids = <
762 MX28_PAD_LCD_D00__LCD_D0
763 MX28_PAD_LCD_D01__LCD_D1
764 MX28_PAD_LCD_D02__LCD_D2
765 MX28_PAD_LCD_D03__LCD_D3
766 MX28_PAD_LCD_D04__LCD_D4
767 MX28_PAD_LCD_D05__LCD_D5
768 MX28_PAD_LCD_D06__LCD_D6
769 MX28_PAD_LCD_D07__LCD_D7
770 MX28_PAD_LCD_D08__LCD_D8
771 MX28_PAD_LCD_D09__LCD_D9
772 MX28_PAD_LCD_D10__LCD_D10
773 MX28_PAD_LCD_D11__LCD_D11
774 MX28_PAD_LCD_D12__LCD_D12
775 MX28_PAD_LCD_D13__LCD_D13
776 MX28_PAD_LCD_D14__LCD_D14
777 MX28_PAD_LCD_D15__LCD_D15
778 MX28_PAD_LCD_D16__LCD_D16
779 MX28_PAD_LCD_D17__LCD_D17
780 >;
781 fsl,drive-strength = <MXS_DRIVE_4mA>;
782 fsl,voltage = <MXS_VOLTAGE_HIGH>;
783 fsl,pull-up = <MXS_PULL_DISABLE>;
784 };
785
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]786 lcdif_16bit_pins_a: lcdif-16bit@0 {
787 reg = <0>;
788 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]789 MX28_PAD_LCD_D00__LCD_D0
790 MX28_PAD_LCD_D01__LCD_D1
791 MX28_PAD_LCD_D02__LCD_D2
792 MX28_PAD_LCD_D03__LCD_D3
793 MX28_PAD_LCD_D04__LCD_D4
794 MX28_PAD_LCD_D05__LCD_D5
795 MX28_PAD_LCD_D06__LCD_D6
796 MX28_PAD_LCD_D07__LCD_D7
797 MX28_PAD_LCD_D08__LCD_D8
798 MX28_PAD_LCD_D09__LCD_D9
799 MX28_PAD_LCD_D10__LCD_D10
800 MX28_PAD_LCD_D11__LCD_D11
801 MX28_PAD_LCD_D12__LCD_D12
802 MX28_PAD_LCD_D13__LCD_D13
803 MX28_PAD_LCD_D14__LCD_D14
804 MX28_PAD_LCD_D15__LCD_D15
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]805 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]806 fsl,drive-strength = <MXS_DRIVE_4mA>;
807 fsl,voltage = <MXS_VOLTAGE_HIGH>;
808 fsl,pull-up = <MXS_PULL_DISABLE>;
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]809 };
810
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]811 lcdif_sync_pins_a: lcdif-sync@0 {
812 reg = <0>;
813 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]814 MX28_PAD_LCD_RS__LCD_DOTCLK
815 MX28_PAD_LCD_CS__LCD_ENABLE
816 MX28_PAD_LCD_RD_E__LCD_VSYNC
817 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]818 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]819 fsl,drive-strength = <MXS_DRIVE_4mA>;
820 fsl,voltage = <MXS_VOLTAGE_HIGH>;
821 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]822 };
823
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]824 can0_pins_a: can0@0 {
825 reg = <0>;
826 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]827 MX28_PAD_GPMI_RDY2__CAN0_TX
828 MX28_PAD_GPMI_RDY3__CAN0_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]829 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]830 fsl,drive-strength = <MXS_DRIVE_4mA>;
831 fsl,voltage = <MXS_VOLTAGE_HIGH>;
832 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]833 };
834
835 can1_pins_a: can1@0 {
836 reg = <0>;
837 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]838 MX28_PAD_GPMI_CE2N__CAN1_TX
839 MX28_PAD_GPMI_CE3N__CAN1_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]840 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]841 fsl,drive-strength = <MXS_DRIVE_4mA>;
842 fsl,voltage = <MXS_VOLTAGE_HIGH>;
843 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]844 };
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]845
846 spi2_pins_a: spi2@0 {
847 reg = <0>;
848 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]849 MX28_PAD_SSP2_SCK__SSP2_SCK
850 MX28_PAD_SSP2_MOSI__SSP2_CMD
851 MX28_PAD_SSP2_MISO__SSP2_D0
852 MX28_PAD_SSP2_SS0__SSP2_D3
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]853 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]854 fsl,drive-strength = <MXS_DRIVE_8mA>;
855 fsl,voltage = <MXS_VOLTAGE_HIGH>;
856 fsl,pull-up = <MXS_PULL_ENABLE>;
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]857 };
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]858
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]859 spi3_pins_a: spi3@0 {
860 reg = <0>;
861 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]862 MX28_PAD_AUART2_RX__SSP3_D4
863 MX28_PAD_AUART2_TX__SSP3_D5
864 MX28_PAD_SSP3_SCK__SSP3_SCK
865 MX28_PAD_SSP3_MOSI__SSP3_CMD
866 MX28_PAD_SSP3_MISO__SSP3_D0
867 MX28_PAD_SSP3_SS0__SSP3_D3
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]868 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]869 fsl,drive-strength = <MXS_DRIVE_8mA>;
870 fsl,voltage = <MXS_VOLTAGE_HIGH>;
871 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]872 };
873
Uwe Kleine-König8f0b07a2015-03-19 10:55:47 +0100[diff] [blame]874 spi3_pins_b: spi3@1 {
875 reg = <1>;
876 fsl,pinmux-ids = <
877 MX28_PAD_SSP3_SCK__SSP3_SCK
878 MX28_PAD_SSP3_MOSI__SSP3_CMD
879 MX28_PAD_SSP3_MISO__SSP3_D0
880 MX28_PAD_SSP3_SS0__SSP3_D3
881 >;
882 fsl,drive-strength = <MXS_DRIVE_8mA>;
883 fsl,voltage = <MXS_VOLTAGE_HIGH>;
884 fsl,pull-up = <MXS_PULL_ENABLE>;
885 };
886
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]887 usb0_pins_a: usb0@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]888 reg = <0>;
889 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]890 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]891 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]892 fsl,drive-strength = <MXS_DRIVE_12mA>;
893 fsl,voltage = <MXS_VOLTAGE_HIGH>;
894 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]895 };
896
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]897 usb0_pins_b: usb0@1 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]898 reg = <1>;
899 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]900 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]901 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]902 fsl,drive-strength = <MXS_DRIVE_12mA>;
903 fsl,voltage = <MXS_VOLTAGE_HIGH>;
904 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]905 };
906
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]907 usb1_pins_a: usb1@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]908 reg = <0>;
909 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]910 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]911 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]912 fsl,drive-strength = <MXS_DRIVE_12mA>;
913 fsl,voltage = <MXS_VOLTAGE_HIGH>;
914 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]915 };
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]916
917 usb0_id_pins_a: usb0id@0 {
918 reg = <0>;
919 fsl,pinmux-ids = <
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]920 MX28_PAD_AUART1_RTS__USB0_ID
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]921 >;
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]922 fsl,drive-strength = <MXS_DRIVE_12mA>;
923 fsl,voltage = <MXS_VOLTAGE_HIGH>;
924 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]925 };
Denis Cariklibb89b8d2013-12-05 14:28:05 +0100[diff] [blame]926
927 usb0_id_pins_b: usb0id1@0 {
928 reg = <0>;
929 fsl,pinmux-ids = <
930 MX28_PAD_PWM2__USB0_ID
931 >;
932 fsl,drive-strength = <MXS_DRIVE_12mA>;
933 fsl,voltage = <MXS_VOLTAGE_HIGH>;
934 fsl,pull-up = <MXS_PULL_ENABLE>;
935 };
936
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]937 };
938
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]939 digctl: digctl@8001c000 {
Fabio Estevam115581c2013-06-04 10:18:44 -0300[diff] [blame]940 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]941 reg = <0x8001c000 0x2000>;
942 interrupts = <89>;
943 status = "disabled";
944 };
945
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]946 etm: etm@80022000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]947 reg = <0x80022000 0x2000>;
948 status = "disabled";
949 };
950
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]951 dma_apbx: dma-apbx@80024000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]952 compatible = "fsl,imx28-dma-apbx";
953 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]954 interrupts = <78 79 66 0
955 80 81 68 69
956 70 71 72 73
957 74 75 76 77>;
Marek Vasut4ada77e2015-04-24 13:29:47 +0200[diff] [blame]958 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]959 "saif0", "saif1", "i2c0", "i2c1",
960 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
961 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
962 #dma-cells = <1>;
963 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]964 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]965 };
966
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]967 dcp: dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]968 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]969 reg = <0x80028000 0x2000>;
970 interrupts = <52 53 54>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]971 status = "okay";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]972 };
973
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]974 pxp: pxp@8002a000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]975 reg = <0x8002a000 0x2000>;
976 interrupts = <39>;
977 status = "disabled";
978 };
979
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]980 ocotp: ocotp@8002c000 {
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]981 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
982 #address-cells = <1>;
983 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]984 reg = <0x8002c000 0x2000>;
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]985 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]986 };
987
988 axi-ahb@8002e000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]989 reg = <0x8002e000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]990 status = "disabled";
991 };
992
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]993 lcdif: lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]994 compatible = "fsl,imx28-lcdif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]995 reg = <0x80030000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]996 interrupts = <38>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]997 clocks = <&clks 55>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]998 dmas = <&dma_apbh 13>;
999 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1000 status = "disabled";
1001 };
1002
1003 can0: can@80032000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]1004 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1005 reg = <0x80032000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1006 interrupts = <8>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1007 clocks = <&clks 58>, <&clks 58>;
1008 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1009 status = "disabled";
1010 };
1011
1012 can1: can@80034000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]1013 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1014 reg = <0x80034000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1015 interrupts = <9>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1016 clocks = <&clks 59>, <&clks 59>;
1017 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1018 status = "disabled";
1019 };
1020
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1021 simdbg: simdbg@8003c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1022 reg = <0x8003c000 0x200>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1023 status = "disabled";
1024 };
1025
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1026 simgpmisel: simgpmisel@8003c200 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1027 reg = <0x8003c200 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1028 status = "disabled";
1029 };
1030
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1031 simsspsel: simsspsel@8003c300 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1032 reg = <0x8003c300 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1033 status = "disabled";
1034 };
1035
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1036 simmemsel: simmemsel@8003c400 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1037 reg = <0x8003c400 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1038 status = "disabled";
1039 };
1040
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1041 gpiomon: gpiomon@8003c500 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1042 reg = <0x8003c500 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1043 status = "disabled";
1044 };
1045
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1046 simenet: simenet@8003c700 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1047 reg = <0x8003c700 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1048 status = "disabled";
1049 };
1050
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1051 armjtag: armjtag@8003c800 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1052 reg = <0x8003c800 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1053 status = "disabled";
1054 };
Lothar Waßmann07a3ce72013-08-08 14:51:20 +0200[diff] [blame]1055 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1056
1057 apbx@80040000 {
1058 compatible = "simple-bus";
1059 #address-cells = <1>;
1060 #size-cells = <1>;
1061 reg = <0x80040000 0x40000>;
1062 ranges;
1063
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1064 clks: clkctrl@80040000 {
Shawn Guo8f7cf8812013-03-29 09:33:09 +0800[diff] [blame]1065 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1066 reg = <0x80040000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1067 #clock-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1068 };
1069
1070 saif0: saif@80042000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1071 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1072 reg = <0x80042000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1073 interrupts = <59>;
Shawn Guo66acaf32013-07-01 15:46:05 +0800[diff] [blame]1074 #clock-cells = <0>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1075 clocks = <&clks 53>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1076 dmas = <&dma_apbx 4>;
1077 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1078 status = "disabled";
1079 };
1080
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1081 power: power@80044000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1082 reg = <0x80044000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1083 status = "disabled";
1084 };
1085
1086 saif1: saif@80046000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1087 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1088 reg = <0x80046000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1089 interrupts = <58>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1090 clocks = <&clks 54>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1091 dmas = <&dma_apbx 5>;
1092 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1093 status = "disabled";
1094 };
1095
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1096 lradc: lradc@80050000 {
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1097 compatible = "fsl,imx28-lradc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1098 reg = <0x80050000 0x2000>;
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1099 interrupts = <10 14 15 16 17 18 19
1100 20 21 22 23 24 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1101 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]1102 clocks = <&clks 41>;
Alexandre Belloni40dde682013-12-06 21:20:31 +0100[diff] [blame]1103 #io-channel-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1104 };
1105
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1106 spdif: spdif@80054000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1107 reg = <0x80054000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1108 interrupts = <45>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1109 dmas = <&dma_apbx 2>;
1110 dma-names = "tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1111 status = "disabled";
1112 };
1113
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1114 mxs_rtc: rtc@80056000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1115 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1116 reg = <0x80056000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1117 interrupts = <29>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1118 };
1119
1120 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1124 reg = <0x80058000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1125 interrupts = <111>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1126 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1127 dmas = <&dma_apbx 6>;
1128 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1129 status = "disabled";
1130 };
1131
1132 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1133 #address-cells = <1>;
1134 #size-cells = <0>;
1135 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1136 reg = <0x8005a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1137 interrupts = <110>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1138 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1139 dmas = <&dma_apbx 7>;
1140 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1141 status = "disabled";
1142 };
1143
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1144 pwm: pwm@80064000 {
1145 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1146 reg = <0x80064000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1147 clocks = <&clks 44>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1148 #pwm-cells = <2>;
1149 fsl,pwm-number = <8>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1150 status = "disabled";
1151 };
1152
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1153 timer: timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1154 compatible = "fsl,imx28-timrot", "fsl,timrot";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1155 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1156 interrupts = <48 49 50 51>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]1157 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1158 };
1159
1160 auart0: serial@8006a000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1161 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1162 reg = <0x8006a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1163 interrupts = <112>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1164 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1165 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1166 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1167 status = "disabled";
1168 };
1169
1170 auart1: serial@8006c000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1171 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1172 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1173 interrupts = <113>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1174 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1175 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1176 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1177 status = "disabled";
1178 };
1179
1180 auart2: serial@8006e000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1181 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1182 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1183 interrupts = <114>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1184 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1185 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1186 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1187 status = "disabled";
1188 };
1189
1190 auart3: serial@80070000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1191 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1192 reg = <0x80070000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1193 interrupts = <115>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1194 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1195 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1196 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1197 status = "disabled";
1198 };
1199
1200 auart4: serial@80072000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1201 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1202 reg = <0x80072000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1203 interrupts = <116>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1204 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1205 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1206 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1207 status = "disabled";
1208 };
1209
1210 duart: serial@80074000 {
1211 compatible = "arm,pl011", "arm,primecell";
1212 reg = <0x80074000 0x1000>;
1213 interrupts = <47>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1214 clocks = <&clks 45>, <&clks 26>;
1215 clock-names = "uart", "apb_pclk";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1216 status = "disabled";
1217 };
1218
1219 usbphy0: usbphy@8007c000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1220 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1221 reg = <0x8007c000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1222 clocks = <&clks 62>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1223 status = "disabled";
1224 };
1225
1226 usbphy1: usbphy@8007e000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1227 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1228 reg = <0x8007e000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1229 clocks = <&clks 63>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1230 status = "disabled";
1231 };
1232 };
1233 };
1234
1235 ahb@80080000 {
1236 compatible = "simple-bus";
1237 #address-cells = <1>;
1238 #size-cells = <1>;
1239 reg = <0x80080000 0x80000>;
1240 ranges;
1241
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1242 usb0: usb@80080000 {
1243 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1244 reg = <0x80080000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1245 interrupts = <93>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1246 clocks = <&clks 60>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1247 fsl,usbphy = <&usbphy0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1248 status = "disabled";
1249 };
1250
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1251 usb1: usb@80090000 {
1252 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1253 reg = <0x80090000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1254 interrupts = <92>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1255 clocks = <&clks 61>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1256 fsl,usbphy = <&usbphy1>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]1257 dr_mode = "host";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1258 status = "disabled";
1259 };
1260
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1261 dflpt: dflpt@800c0000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1262 reg = <0x800c0000 0x10000>;
1263 status = "disabled";
1264 };
1265
1266 mac0: ethernet@800f0000 {
1267 compatible = "fsl,imx28-fec";
1268 reg = <0x800f0000 0x4000>;
1269 interrupts = <101>;
Wolfram Sangf231a9f2013-01-29 15:46:12 +0100[diff] [blame]1270 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1271 clock-names = "ipg", "ahb", "enet_out";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1272 status = "disabled";
1273 };
1274
1275 mac1: ethernet@800f4000 {
1276 compatible = "fsl,imx28-fec";
1277 reg = <0x800f4000 0x4000>;
1278 interrupts = <102>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1279 clocks = <&clks 57>, <&clks 57>;
1280 clock-names = "ipg", "ahb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1281 status = "disabled";
1282 };
1283
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1284 etn_switch: switch@800f8000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1285 reg = <0x800f8000 0x8000>;
1286 status = "disabled";
1287 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1288 };
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1289
Sanchayan Maity0b452cc2016-02-16 10:30:54 +0530[diff] [blame]1290 iio-hwmon {
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1291 compatible = "iio-hwmon";
1292 io-channels = <&lradc 8>;
1293 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1294};