Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 27 | #include <linux/module.h> |
| 28 | #include <linux/input.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 29 | #include <linux/i2c.h> |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 30 | #include <linux/kernel.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 31 | #include <linux/slab.h> |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 32 | #include <linux/vgaarb.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 33 | #include "drmP.h" |
| 34 | #include "intel_drv.h" |
| 35 | #include "i915_drm.h" |
| 36 | #include "i915_drv.h" |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 37 | #include "i915_trace.h" |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 38 | #include "drm_dp_helper.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 39 | |
| 40 | #include "drm_crtc_helper.h" |
| 41 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 42 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
| 43 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 44 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 45 | static void intel_update_watermarks(struct drm_device *dev); |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 46 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 47 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 48 | |
| 49 | typedef struct { |
| 50 | /* given values */ |
| 51 | int n; |
| 52 | int m1, m2; |
| 53 | int p1, p2; |
| 54 | /* derived values */ |
| 55 | int dot; |
| 56 | int vco; |
| 57 | int m; |
| 58 | int p; |
| 59 | } intel_clock_t; |
| 60 | |
| 61 | typedef struct { |
| 62 | int min, max; |
| 63 | } intel_range_t; |
| 64 | |
| 65 | typedef struct { |
| 66 | int dot_limit; |
| 67 | int p2_slow, p2_fast; |
| 68 | } intel_p2_t; |
| 69 | |
| 70 | #define INTEL_P2_NUM 2 |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 71 | typedef struct intel_limit intel_limit_t; |
| 72 | struct intel_limit { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 73 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
| 74 | intel_p2_t p2; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 75 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
| 76 | int, int, intel_clock_t *); |
| 77 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 78 | |
| 79 | #define I8XX_DOT_MIN 25000 |
| 80 | #define I8XX_DOT_MAX 350000 |
| 81 | #define I8XX_VCO_MIN 930000 |
| 82 | #define I8XX_VCO_MAX 1400000 |
| 83 | #define I8XX_N_MIN 3 |
| 84 | #define I8XX_N_MAX 16 |
| 85 | #define I8XX_M_MIN 96 |
| 86 | #define I8XX_M_MAX 140 |
| 87 | #define I8XX_M1_MIN 18 |
| 88 | #define I8XX_M1_MAX 26 |
| 89 | #define I8XX_M2_MIN 6 |
| 90 | #define I8XX_M2_MAX 16 |
| 91 | #define I8XX_P_MIN 4 |
| 92 | #define I8XX_P_MAX 128 |
| 93 | #define I8XX_P1_MIN 2 |
| 94 | #define I8XX_P1_MAX 33 |
| 95 | #define I8XX_P1_LVDS_MIN 1 |
| 96 | #define I8XX_P1_LVDS_MAX 6 |
| 97 | #define I8XX_P2_SLOW 4 |
| 98 | #define I8XX_P2_FAST 2 |
| 99 | #define I8XX_P2_LVDS_SLOW 14 |
ling.ma@intel.com | 0c2e395 | 2009-07-17 11:44:30 +0800 | [diff] [blame] | 100 | #define I8XX_P2_LVDS_FAST 7 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 101 | #define I8XX_P2_SLOW_LIMIT 165000 |
| 102 | |
| 103 | #define I9XX_DOT_MIN 20000 |
| 104 | #define I9XX_DOT_MAX 400000 |
| 105 | #define I9XX_VCO_MIN 1400000 |
| 106 | #define I9XX_VCO_MAX 2800000 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 107 | #define PINEVIEW_VCO_MIN 1700000 |
| 108 | #define PINEVIEW_VCO_MAX 3500000 |
Kristian Høgsberg | f3cade5 | 2009-02-13 20:56:50 -0500 | [diff] [blame] | 109 | #define I9XX_N_MIN 1 |
| 110 | #define I9XX_N_MAX 6 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 111 | /* Pineview's Ncounter is a ring counter */ |
| 112 | #define PINEVIEW_N_MIN 3 |
| 113 | #define PINEVIEW_N_MAX 6 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 114 | #define I9XX_M_MIN 70 |
| 115 | #define I9XX_M_MAX 120 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 116 | #define PINEVIEW_M_MIN 2 |
| 117 | #define PINEVIEW_M_MAX 256 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 118 | #define I9XX_M1_MIN 10 |
Kristian Høgsberg | f3cade5 | 2009-02-13 20:56:50 -0500 | [diff] [blame] | 119 | #define I9XX_M1_MAX 22 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 120 | #define I9XX_M2_MIN 5 |
| 121 | #define I9XX_M2_MAX 9 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 122 | /* Pineview M1 is reserved, and must be 0 */ |
| 123 | #define PINEVIEW_M1_MIN 0 |
| 124 | #define PINEVIEW_M1_MAX 0 |
| 125 | #define PINEVIEW_M2_MIN 0 |
| 126 | #define PINEVIEW_M2_MAX 254 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 127 | #define I9XX_P_SDVO_DAC_MIN 5 |
| 128 | #define I9XX_P_SDVO_DAC_MAX 80 |
| 129 | #define I9XX_P_LVDS_MIN 7 |
| 130 | #define I9XX_P_LVDS_MAX 98 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 131 | #define PINEVIEW_P_LVDS_MIN 7 |
| 132 | #define PINEVIEW_P_LVDS_MAX 112 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 133 | #define I9XX_P1_MIN 1 |
| 134 | #define I9XX_P1_MAX 8 |
| 135 | #define I9XX_P2_SDVO_DAC_SLOW 10 |
| 136 | #define I9XX_P2_SDVO_DAC_FAST 5 |
| 137 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 |
| 138 | #define I9XX_P2_LVDS_SLOW 14 |
| 139 | #define I9XX_P2_LVDS_FAST 7 |
| 140 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 |
| 141 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 142 | /*The parameter is for SDVO on G4x platform*/ |
| 143 | #define G4X_DOT_SDVO_MIN 25000 |
| 144 | #define G4X_DOT_SDVO_MAX 270000 |
| 145 | #define G4X_VCO_MIN 1750000 |
| 146 | #define G4X_VCO_MAX 3500000 |
| 147 | #define G4X_N_SDVO_MIN 1 |
| 148 | #define G4X_N_SDVO_MAX 4 |
| 149 | #define G4X_M_SDVO_MIN 104 |
| 150 | #define G4X_M_SDVO_MAX 138 |
| 151 | #define G4X_M1_SDVO_MIN 17 |
| 152 | #define G4X_M1_SDVO_MAX 23 |
| 153 | #define G4X_M2_SDVO_MIN 5 |
| 154 | #define G4X_M2_SDVO_MAX 11 |
| 155 | #define G4X_P_SDVO_MIN 10 |
| 156 | #define G4X_P_SDVO_MAX 30 |
| 157 | #define G4X_P1_SDVO_MIN 1 |
| 158 | #define G4X_P1_SDVO_MAX 3 |
| 159 | #define G4X_P2_SDVO_SLOW 10 |
| 160 | #define G4X_P2_SDVO_FAST 10 |
| 161 | #define G4X_P2_SDVO_LIMIT 270000 |
| 162 | |
| 163 | /*The parameter is for HDMI_DAC on G4x platform*/ |
| 164 | #define G4X_DOT_HDMI_DAC_MIN 22000 |
| 165 | #define G4X_DOT_HDMI_DAC_MAX 400000 |
| 166 | #define G4X_N_HDMI_DAC_MIN 1 |
| 167 | #define G4X_N_HDMI_DAC_MAX 4 |
| 168 | #define G4X_M_HDMI_DAC_MIN 104 |
| 169 | #define G4X_M_HDMI_DAC_MAX 138 |
| 170 | #define G4X_M1_HDMI_DAC_MIN 16 |
| 171 | #define G4X_M1_HDMI_DAC_MAX 23 |
| 172 | #define G4X_M2_HDMI_DAC_MIN 5 |
| 173 | #define G4X_M2_HDMI_DAC_MAX 11 |
| 174 | #define G4X_P_HDMI_DAC_MIN 5 |
| 175 | #define G4X_P_HDMI_DAC_MAX 80 |
| 176 | #define G4X_P1_HDMI_DAC_MIN 1 |
| 177 | #define G4X_P1_HDMI_DAC_MAX 8 |
| 178 | #define G4X_P2_HDMI_DAC_SLOW 10 |
| 179 | #define G4X_P2_HDMI_DAC_FAST 5 |
| 180 | #define G4X_P2_HDMI_DAC_LIMIT 165000 |
| 181 | |
| 182 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ |
| 183 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 |
| 184 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 |
| 185 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 |
| 186 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 |
| 187 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 |
| 188 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 |
| 189 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 |
| 190 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 |
| 191 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 |
| 192 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 |
| 193 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 |
| 194 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 |
| 195 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 |
| 196 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 |
| 197 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 |
| 198 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 |
| 199 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 |
| 200 | |
| 201 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ |
| 202 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 |
| 203 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 |
| 204 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 |
| 205 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 |
| 206 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 |
| 207 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 |
| 208 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 |
| 209 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 |
| 210 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 |
| 211 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 |
| 212 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 |
| 213 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 |
| 214 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 |
| 215 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 |
| 216 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 |
| 217 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 |
| 218 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 |
| 219 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 220 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
| 221 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 |
| 222 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 |
| 223 | #define G4X_N_DISPLAY_PORT_MIN 1 |
| 224 | #define G4X_N_DISPLAY_PORT_MAX 2 |
| 225 | #define G4X_M_DISPLAY_PORT_MIN 97 |
| 226 | #define G4X_M_DISPLAY_PORT_MAX 108 |
| 227 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 |
| 228 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 |
| 229 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 |
| 230 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 |
| 231 | #define G4X_P_DISPLAY_PORT_MIN 10 |
| 232 | #define G4X_P_DISPLAY_PORT_MAX 20 |
| 233 | #define G4X_P1_DISPLAY_PORT_MIN 1 |
| 234 | #define G4X_P1_DISPLAY_PORT_MAX 2 |
| 235 | #define G4X_P2_DISPLAY_PORT_SLOW 10 |
| 236 | #define G4X_P2_DISPLAY_PORT_FAST 10 |
| 237 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 |
| 238 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 239 | /* Ironlake / Sandybridge */ |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 240 | /* as we calculate clock using (register_value + 2) for |
| 241 | N/M1/M2, so here the range value for them is (actual_value-2). |
| 242 | */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 243 | #define IRONLAKE_DOT_MIN 25000 |
| 244 | #define IRONLAKE_DOT_MAX 350000 |
| 245 | #define IRONLAKE_VCO_MIN 1760000 |
| 246 | #define IRONLAKE_VCO_MAX 3510000 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 247 | #define IRONLAKE_M1_MIN 12 |
Zhao Yakui | a59e385 | 2010-01-06 22:05:57 +0800 | [diff] [blame] | 248 | #define IRONLAKE_M1_MAX 22 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 249 | #define IRONLAKE_M2_MIN 5 |
| 250 | #define IRONLAKE_M2_MAX 9 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 251 | #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 252 | |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 253 | /* We have parameter ranges for different type of outputs. */ |
| 254 | |
| 255 | /* DAC & HDMI Refclk 120Mhz */ |
| 256 | #define IRONLAKE_DAC_N_MIN 1 |
| 257 | #define IRONLAKE_DAC_N_MAX 5 |
| 258 | #define IRONLAKE_DAC_M_MIN 79 |
| 259 | #define IRONLAKE_DAC_M_MAX 127 |
| 260 | #define IRONLAKE_DAC_P_MIN 5 |
| 261 | #define IRONLAKE_DAC_P_MAX 80 |
| 262 | #define IRONLAKE_DAC_P1_MIN 1 |
| 263 | #define IRONLAKE_DAC_P1_MAX 8 |
| 264 | #define IRONLAKE_DAC_P2_SLOW 10 |
| 265 | #define IRONLAKE_DAC_P2_FAST 5 |
| 266 | |
| 267 | /* LVDS single-channel 120Mhz refclk */ |
| 268 | #define IRONLAKE_LVDS_S_N_MIN 1 |
| 269 | #define IRONLAKE_LVDS_S_N_MAX 3 |
| 270 | #define IRONLAKE_LVDS_S_M_MIN 79 |
| 271 | #define IRONLAKE_LVDS_S_M_MAX 118 |
| 272 | #define IRONLAKE_LVDS_S_P_MIN 28 |
| 273 | #define IRONLAKE_LVDS_S_P_MAX 112 |
| 274 | #define IRONLAKE_LVDS_S_P1_MIN 2 |
| 275 | #define IRONLAKE_LVDS_S_P1_MAX 8 |
| 276 | #define IRONLAKE_LVDS_S_P2_SLOW 14 |
| 277 | #define IRONLAKE_LVDS_S_P2_FAST 14 |
| 278 | |
| 279 | /* LVDS dual-channel 120Mhz refclk */ |
| 280 | #define IRONLAKE_LVDS_D_N_MIN 1 |
| 281 | #define IRONLAKE_LVDS_D_N_MAX 3 |
| 282 | #define IRONLAKE_LVDS_D_M_MIN 79 |
| 283 | #define IRONLAKE_LVDS_D_M_MAX 127 |
| 284 | #define IRONLAKE_LVDS_D_P_MIN 14 |
| 285 | #define IRONLAKE_LVDS_D_P_MAX 56 |
| 286 | #define IRONLAKE_LVDS_D_P1_MIN 2 |
| 287 | #define IRONLAKE_LVDS_D_P1_MAX 8 |
| 288 | #define IRONLAKE_LVDS_D_P2_SLOW 7 |
| 289 | #define IRONLAKE_LVDS_D_P2_FAST 7 |
| 290 | |
| 291 | /* LVDS single-channel 100Mhz refclk */ |
| 292 | #define IRONLAKE_LVDS_S_SSC_N_MIN 1 |
| 293 | #define IRONLAKE_LVDS_S_SSC_N_MAX 2 |
| 294 | #define IRONLAKE_LVDS_S_SSC_M_MIN 79 |
| 295 | #define IRONLAKE_LVDS_S_SSC_M_MAX 126 |
| 296 | #define IRONLAKE_LVDS_S_SSC_P_MIN 28 |
| 297 | #define IRONLAKE_LVDS_S_SSC_P_MAX 112 |
| 298 | #define IRONLAKE_LVDS_S_SSC_P1_MIN 2 |
| 299 | #define IRONLAKE_LVDS_S_SSC_P1_MAX 8 |
| 300 | #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14 |
| 301 | #define IRONLAKE_LVDS_S_SSC_P2_FAST 14 |
| 302 | |
| 303 | /* LVDS dual-channel 100Mhz refclk */ |
| 304 | #define IRONLAKE_LVDS_D_SSC_N_MIN 1 |
| 305 | #define IRONLAKE_LVDS_D_SSC_N_MAX 3 |
| 306 | #define IRONLAKE_LVDS_D_SSC_M_MIN 79 |
| 307 | #define IRONLAKE_LVDS_D_SSC_M_MAX 126 |
| 308 | #define IRONLAKE_LVDS_D_SSC_P_MIN 14 |
| 309 | #define IRONLAKE_LVDS_D_SSC_P_MAX 42 |
| 310 | #define IRONLAKE_LVDS_D_SSC_P1_MIN 2 |
| 311 | #define IRONLAKE_LVDS_D_SSC_P1_MAX 6 |
| 312 | #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7 |
| 313 | #define IRONLAKE_LVDS_D_SSC_P2_FAST 7 |
| 314 | |
| 315 | /* DisplayPort */ |
| 316 | #define IRONLAKE_DP_N_MIN 1 |
| 317 | #define IRONLAKE_DP_N_MAX 2 |
| 318 | #define IRONLAKE_DP_M_MIN 81 |
| 319 | #define IRONLAKE_DP_M_MAX 90 |
| 320 | #define IRONLAKE_DP_P_MIN 10 |
| 321 | #define IRONLAKE_DP_P_MAX 20 |
| 322 | #define IRONLAKE_DP_P2_FAST 10 |
| 323 | #define IRONLAKE_DP_P2_SLOW 10 |
| 324 | #define IRONLAKE_DP_P2_LIMIT 0 |
| 325 | #define IRONLAKE_DP_P1_MIN 1 |
| 326 | #define IRONLAKE_DP_P1_MAX 2 |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 327 | |
Jesse Barnes | 2377b74 | 2010-07-07 14:06:43 -0700 | [diff] [blame] | 328 | /* FDI */ |
| 329 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
| 330 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 331 | static bool |
| 332 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 333 | int target, int refclk, intel_clock_t *best_clock); |
| 334 | static bool |
| 335 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 336 | int target, int refclk, intel_clock_t *best_clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 337 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 338 | static bool |
| 339 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, |
| 340 | int target, int refclk, intel_clock_t *best_clock); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 341 | static bool |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 342 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
| 343 | int target, int refclk, intel_clock_t *best_clock); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 344 | |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 345 | static inline u32 /* units of 100MHz */ |
| 346 | intel_fdi_link_freq(struct drm_device *dev) |
| 347 | { |
| 348 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 349 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
| 350 | } |
| 351 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 352 | static const intel_limit_t intel_limits_i8xx_dvo = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 353 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
| 354 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, |
| 355 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, |
| 356 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, |
| 357 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, |
| 358 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, |
| 359 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, |
| 360 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, |
| 361 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, |
| 362 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 363 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 364 | }; |
| 365 | |
| 366 | static const intel_limit_t intel_limits_i8xx_lvds = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 367 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
| 368 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, |
| 369 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, |
| 370 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, |
| 371 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, |
| 372 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, |
| 373 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, |
| 374 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, |
| 375 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, |
| 376 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 377 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 378 | }; |
| 379 | |
| 380 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 381 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
| 382 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, |
| 383 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, |
| 384 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, |
| 385 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, |
| 386 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, |
| 387 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
| 388 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
| 389 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, |
| 390 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 391 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 392 | }; |
| 393 | |
| 394 | static const intel_limit_t intel_limits_i9xx_lvds = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 395 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
| 396 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, |
| 397 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, |
| 398 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, |
| 399 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, |
| 400 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, |
| 401 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, |
| 402 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
| 403 | /* The single-channel range is 25-112Mhz, and dual-channel |
| 404 | * is 80-224Mhz. Prefer single channel as much as possible. |
| 405 | */ |
| 406 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
| 407 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 408 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 409 | }; |
| 410 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 411 | /* below parameter and function is for G4X Chipset Family*/ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 412 | static const intel_limit_t intel_limits_g4x_sdvo = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 413 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
| 414 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, |
| 415 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, |
| 416 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, |
| 417 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, |
| 418 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, |
| 419 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, |
| 420 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, |
| 421 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, |
| 422 | .p2_slow = G4X_P2_SDVO_SLOW, |
| 423 | .p2_fast = G4X_P2_SDVO_FAST |
| 424 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 425 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 426 | }; |
| 427 | |
| 428 | static const intel_limit_t intel_limits_g4x_hdmi = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 429 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
| 430 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, |
| 431 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, |
| 432 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, |
| 433 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, |
| 434 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, |
| 435 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, |
| 436 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, |
| 437 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, |
| 438 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, |
| 439 | .p2_fast = G4X_P2_HDMI_DAC_FAST |
| 440 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 441 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 442 | }; |
| 443 | |
| 444 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 445 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
| 446 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, |
| 447 | .vco = { .min = G4X_VCO_MIN, |
| 448 | .max = G4X_VCO_MAX }, |
| 449 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, |
| 450 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, |
| 451 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, |
| 452 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, |
| 453 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, |
| 454 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, |
| 455 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, |
| 456 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, |
| 457 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, |
| 458 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, |
| 459 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, |
| 460 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, |
| 461 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, |
| 462 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, |
| 463 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST |
| 464 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 465 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 466 | }; |
| 467 | |
| 468 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 469 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
| 470 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, |
| 471 | .vco = { .min = G4X_VCO_MIN, |
| 472 | .max = G4X_VCO_MAX }, |
| 473 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, |
| 474 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, |
| 475 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, |
| 476 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, |
| 477 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, |
| 478 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, |
| 479 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, |
| 480 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, |
| 481 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, |
| 482 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, |
| 483 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, |
| 484 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, |
| 485 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, |
| 486 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, |
| 487 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST |
| 488 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 489 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 490 | }; |
| 491 | |
| 492 | static const intel_limit_t intel_limits_g4x_display_port = { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 493 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
| 494 | .max = G4X_DOT_DISPLAY_PORT_MAX }, |
| 495 | .vco = { .min = G4X_VCO_MIN, |
| 496 | .max = G4X_VCO_MAX}, |
| 497 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, |
| 498 | .max = G4X_N_DISPLAY_PORT_MAX }, |
| 499 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, |
| 500 | .max = G4X_M_DISPLAY_PORT_MAX }, |
| 501 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, |
| 502 | .max = G4X_M1_DISPLAY_PORT_MAX }, |
| 503 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, |
| 504 | .max = G4X_M2_DISPLAY_PORT_MAX }, |
| 505 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, |
| 506 | .max = G4X_P_DISPLAY_PORT_MAX }, |
| 507 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, |
| 508 | .max = G4X_P1_DISPLAY_PORT_MAX}, |
| 509 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, |
| 510 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, |
| 511 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, |
| 512 | .find_pll = intel_find_pll_g4x_dp, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 513 | }; |
| 514 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 515 | static const intel_limit_t intel_limits_pineview_sdvo = { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 516 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 517 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
| 518 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, |
| 519 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, |
| 520 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, |
| 521 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 522 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
| 523 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
| 524 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, |
| 525 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, |
Shaohua Li | 6115707 | 2009-04-03 15:24:43 +0800 | [diff] [blame] | 526 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 527 | }; |
| 528 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 529 | static const intel_limit_t intel_limits_pineview_lvds = { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 530 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 531 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
| 532 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, |
| 533 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, |
| 534 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, |
| 535 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, |
| 536 | .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX }, |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 537 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 538 | /* Pineview only supports single-channel mode. */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 539 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
| 540 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, |
Shaohua Li | 6115707 | 2009-04-03 15:24:43 +0800 | [diff] [blame] | 541 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 542 | }; |
| 543 | |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 544 | static const intel_limit_t intel_limits_ironlake_dac = { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 545 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
| 546 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 547 | .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX }, |
| 548 | .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 549 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
| 550 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 551 | .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX }, |
| 552 | .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 553 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 554 | .p2_slow = IRONLAKE_DAC_P2_SLOW, |
| 555 | .p2_fast = IRONLAKE_DAC_P2_FAST }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 556 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 557 | }; |
| 558 | |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 559 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 560 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
| 561 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 562 | .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX }, |
| 563 | .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 564 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
| 565 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 566 | .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX }, |
| 567 | .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 568 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 569 | .p2_slow = IRONLAKE_LVDS_S_P2_SLOW, |
| 570 | .p2_fast = IRONLAKE_LVDS_S_P2_FAST }, |
| 571 | .find_pll = intel_g4x_find_best_PLL, |
| 572 | }; |
| 573 | |
| 574 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
| 575 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
| 576 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, |
| 577 | .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX }, |
| 578 | .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX }, |
| 579 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
| 580 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, |
| 581 | .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX }, |
| 582 | .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX }, |
| 583 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
| 584 | .p2_slow = IRONLAKE_LVDS_D_P2_SLOW, |
| 585 | .p2_fast = IRONLAKE_LVDS_D_P2_FAST }, |
| 586 | .find_pll = intel_g4x_find_best_PLL, |
| 587 | }; |
| 588 | |
| 589 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
| 590 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
| 591 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, |
| 592 | .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX }, |
| 593 | .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX }, |
| 594 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
| 595 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, |
| 596 | .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX }, |
| 597 | .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX }, |
| 598 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
| 599 | .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW, |
| 600 | .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST }, |
| 601 | .find_pll = intel_g4x_find_best_PLL, |
| 602 | }; |
| 603 | |
| 604 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
| 605 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
| 606 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, |
| 607 | .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX }, |
| 608 | .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX }, |
| 609 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
| 610 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, |
| 611 | .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX }, |
| 612 | .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX }, |
| 613 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
| 614 | .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW, |
| 615 | .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 616 | .find_pll = intel_g4x_find_best_PLL, |
| 617 | }; |
| 618 | |
| 619 | static const intel_limit_t intel_limits_ironlake_display_port = { |
| 620 | .dot = { .min = IRONLAKE_DOT_MIN, |
| 621 | .max = IRONLAKE_DOT_MAX }, |
| 622 | .vco = { .min = IRONLAKE_VCO_MIN, |
| 623 | .max = IRONLAKE_VCO_MAX}, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 624 | .n = { .min = IRONLAKE_DP_N_MIN, |
| 625 | .max = IRONLAKE_DP_N_MAX }, |
| 626 | .m = { .min = IRONLAKE_DP_M_MIN, |
| 627 | .max = IRONLAKE_DP_M_MAX }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 628 | .m1 = { .min = IRONLAKE_M1_MIN, |
| 629 | .max = IRONLAKE_M1_MAX }, |
| 630 | .m2 = { .min = IRONLAKE_M2_MIN, |
| 631 | .max = IRONLAKE_M2_MAX }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 632 | .p = { .min = IRONLAKE_DP_P_MIN, |
| 633 | .max = IRONLAKE_DP_P_MAX }, |
| 634 | .p1 = { .min = IRONLAKE_DP_P1_MIN, |
| 635 | .max = IRONLAKE_DP_P1_MAX}, |
| 636 | .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT, |
| 637 | .p2_slow = IRONLAKE_DP_P2_SLOW, |
| 638 | .p2_fast = IRONLAKE_DP_P2_FAST }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 639 | .find_pll = intel_find_pll_ironlake_dp, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 640 | }; |
| 641 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 642 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 643 | { |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 644 | struct drm_device *dev = crtc->dev; |
| 645 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 646 | const intel_limit_t *limit; |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 647 | int refclk = 120; |
| 648 | |
| 649 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 650 | if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100) |
| 651 | refclk = 100; |
| 652 | |
| 653 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
| 654 | LVDS_CLKB_POWER_UP) { |
| 655 | /* LVDS dual channel */ |
| 656 | if (refclk == 100) |
| 657 | limit = &intel_limits_ironlake_dual_lvds_100m; |
| 658 | else |
| 659 | limit = &intel_limits_ironlake_dual_lvds; |
| 660 | } else { |
| 661 | if (refclk == 100) |
| 662 | limit = &intel_limits_ironlake_single_lvds_100m; |
| 663 | else |
| 664 | limit = &intel_limits_ironlake_single_lvds; |
| 665 | } |
| 666 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 667 | HAS_eDP) |
| 668 | limit = &intel_limits_ironlake_display_port; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 669 | else |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 670 | limit = &intel_limits_ironlake_dac; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 671 | |
| 672 | return limit; |
| 673 | } |
| 674 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 675 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
| 676 | { |
| 677 | struct drm_device *dev = crtc->dev; |
| 678 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 679 | const intel_limit_t *limit; |
| 680 | |
| 681 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 682 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 683 | LVDS_CLKB_POWER_UP) |
| 684 | /* LVDS with dual channel */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 685 | limit = &intel_limits_g4x_dual_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 686 | else |
| 687 | /* LVDS with dual channel */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 688 | limit = &intel_limits_g4x_single_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 689 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
| 690 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 691 | limit = &intel_limits_g4x_hdmi; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 692 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 693 | limit = &intel_limits_g4x_sdvo; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 694 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 695 | limit = &intel_limits_g4x_display_port; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 696 | } else /* The option is for other outputs */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 697 | limit = &intel_limits_i9xx_sdvo; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 698 | |
| 699 | return limit; |
| 700 | } |
| 701 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 702 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) |
| 703 | { |
| 704 | struct drm_device *dev = crtc->dev; |
| 705 | const intel_limit_t *limit; |
| 706 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 707 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 708 | limit = intel_ironlake_limit(crtc); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 709 | else if (IS_G4X(dev)) { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 710 | limit = intel_g4x_limit(crtc); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 711 | } else if (IS_PINEVIEW(dev)) { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 712 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 713 | limit = &intel_limits_pineview_lvds; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 714 | else |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 715 | limit = &intel_limits_pineview_sdvo; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 716 | } else if (!IS_GEN2(dev)) { |
| 717 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
| 718 | limit = &intel_limits_i9xx_lvds; |
| 719 | else |
| 720 | limit = &intel_limits_i9xx_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 721 | } else { |
| 722 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 723 | limit = &intel_limits_i8xx_lvds; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 724 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 725 | limit = &intel_limits_i8xx_dvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 726 | } |
| 727 | return limit; |
| 728 | } |
| 729 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 730 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
| 731 | static void pineview_clock(int refclk, intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 732 | { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 733 | clock->m = clock->m2 + 2; |
| 734 | clock->p = clock->p1 * clock->p2; |
| 735 | clock->vco = refclk * clock->m / clock->n; |
| 736 | clock->dot = clock->vco / clock->p; |
| 737 | } |
| 738 | |
| 739 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) |
| 740 | { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 741 | if (IS_PINEVIEW(dev)) { |
| 742 | pineview_clock(refclk, clock); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 743 | return; |
| 744 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 745 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
| 746 | clock->p = clock->p1 * clock->p2; |
| 747 | clock->vco = refclk * clock->m / (clock->n + 2); |
| 748 | clock->dot = clock->vco / clock->p; |
| 749 | } |
| 750 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 751 | /** |
| 752 | * Returns whether any output on the specified pipe is of the specified type |
| 753 | */ |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 754 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 755 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 756 | struct drm_device *dev = crtc->dev; |
| 757 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 758 | struct intel_encoder *encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 759 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 760 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
| 761 | if (encoder->base.crtc == crtc && encoder->type == type) |
| 762 | return true; |
| 763 | |
| 764 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 765 | } |
| 766 | |
Jesse Barnes | 7c04d1d | 2009-02-23 15:36:40 -0800 | [diff] [blame] | 767 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 768 | /** |
| 769 | * Returns whether the given set of divisors are valid for a given refclk with |
| 770 | * the given connectors. |
| 771 | */ |
| 772 | |
| 773 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) |
| 774 | { |
| 775 | const intel_limit_t *limit = intel_limit (crtc); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 776 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 777 | |
| 778 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
| 779 | INTELPllInvalid ("p1 out of range\n"); |
| 780 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
| 781 | INTELPllInvalid ("p out of range\n"); |
| 782 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
| 783 | INTELPllInvalid ("m2 out of range\n"); |
| 784 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
| 785 | INTELPllInvalid ("m1 out of range\n"); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 786 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 787 | INTELPllInvalid ("m1 <= m2\n"); |
| 788 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
| 789 | INTELPllInvalid ("m out of range\n"); |
| 790 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
| 791 | INTELPllInvalid ("n out of range\n"); |
| 792 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
| 793 | INTELPllInvalid ("vco out of range\n"); |
| 794 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
| 795 | * connector, etc., rather than just a single range. |
| 796 | */ |
| 797 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
| 798 | INTELPllInvalid ("dot out of range\n"); |
| 799 | |
| 800 | return true; |
| 801 | } |
| 802 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 803 | static bool |
| 804 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 805 | int target, int refclk, intel_clock_t *best_clock) |
| 806 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 807 | { |
| 808 | struct drm_device *dev = crtc->dev; |
| 809 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 810 | intel_clock_t clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 811 | int err = target; |
| 812 | |
Bruno Prémont | bc5e571 | 2009-08-08 13:01:17 +0200 | [diff] [blame] | 813 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
Florian Mickler | 832cc28 | 2009-07-13 18:40:32 +0800 | [diff] [blame] | 814 | (I915_READ(LVDS)) != 0) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 815 | /* |
| 816 | * For LVDS, if the panel is on, just rely on its current |
| 817 | * settings for dual-channel. We haven't figured out how to |
| 818 | * reliably set up different single/dual channel state, if we |
| 819 | * even can. |
| 820 | */ |
| 821 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 822 | LVDS_CLKB_POWER_UP) |
| 823 | clock.p2 = limit->p2.p2_fast; |
| 824 | else |
| 825 | clock.p2 = limit->p2.p2_slow; |
| 826 | } else { |
| 827 | if (target < limit->p2.dot_limit) |
| 828 | clock.p2 = limit->p2.p2_slow; |
| 829 | else |
| 830 | clock.p2 = limit->p2.p2_fast; |
| 831 | } |
| 832 | |
| 833 | memset (best_clock, 0, sizeof (*best_clock)); |
| 834 | |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 835 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 836 | clock.m1++) { |
| 837 | for (clock.m2 = limit->m2.min; |
| 838 | clock.m2 <= limit->m2.max; clock.m2++) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 839 | /* m1 is always 0 in Pineview */ |
| 840 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 841 | break; |
| 842 | for (clock.n = limit->n.min; |
| 843 | clock.n <= limit->n.max; clock.n++) { |
| 844 | for (clock.p1 = limit->p1.min; |
| 845 | clock.p1 <= limit->p1.max; clock.p1++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 846 | int this_err; |
| 847 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 848 | intel_clock(dev, refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 849 | |
| 850 | if (!intel_PLL_is_valid(crtc, &clock)) |
| 851 | continue; |
| 852 | |
| 853 | this_err = abs(clock.dot - target); |
| 854 | if (this_err < err) { |
| 855 | *best_clock = clock; |
| 856 | err = this_err; |
| 857 | } |
| 858 | } |
| 859 | } |
| 860 | } |
| 861 | } |
| 862 | |
| 863 | return (err != target); |
| 864 | } |
| 865 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 866 | static bool |
| 867 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 868 | int target, int refclk, intel_clock_t *best_clock) |
| 869 | { |
| 870 | struct drm_device *dev = crtc->dev; |
| 871 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 872 | intel_clock_t clock; |
| 873 | int max_n; |
| 874 | bool found; |
Adam Jackson | 6ba770d | 2010-07-02 16:43:30 -0400 | [diff] [blame] | 875 | /* approximately equals target * 0.00585 */ |
| 876 | int err_most = (target >> 8) + (target >> 9); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 877 | found = false; |
| 878 | |
| 879 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 880 | int lvds_reg; |
| 881 | |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 882 | if (HAS_PCH_SPLIT(dev)) |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 883 | lvds_reg = PCH_LVDS; |
| 884 | else |
| 885 | lvds_reg = LVDS; |
| 886 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 887 | LVDS_CLKB_POWER_UP) |
| 888 | clock.p2 = limit->p2.p2_fast; |
| 889 | else |
| 890 | clock.p2 = limit->p2.p2_slow; |
| 891 | } else { |
| 892 | if (target < limit->p2.dot_limit) |
| 893 | clock.p2 = limit->p2.p2_slow; |
| 894 | else |
| 895 | clock.p2 = limit->p2.p2_fast; |
| 896 | } |
| 897 | |
| 898 | memset(best_clock, 0, sizeof(*best_clock)); |
| 899 | max_n = limit->n.max; |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 900 | /* based on hardware requirement, prefer smaller n to precision */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 901 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 902 | /* based on hardware requirement, prefere larger m1,m2 */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 903 | for (clock.m1 = limit->m1.max; |
| 904 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 905 | for (clock.m2 = limit->m2.max; |
| 906 | clock.m2 >= limit->m2.min; clock.m2--) { |
| 907 | for (clock.p1 = limit->p1.max; |
| 908 | clock.p1 >= limit->p1.min; clock.p1--) { |
| 909 | int this_err; |
| 910 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 911 | intel_clock(dev, refclk, &clock); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 912 | if (!intel_PLL_is_valid(crtc, &clock)) |
| 913 | continue; |
| 914 | this_err = abs(clock.dot - target) ; |
| 915 | if (this_err < err_most) { |
| 916 | *best_clock = clock; |
| 917 | err_most = this_err; |
| 918 | max_n = clock.n; |
| 919 | found = true; |
| 920 | } |
| 921 | } |
| 922 | } |
| 923 | } |
| 924 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 925 | return found; |
| 926 | } |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 927 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 928 | static bool |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 929 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 930 | int target, int refclk, intel_clock_t *best_clock) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 931 | { |
| 932 | struct drm_device *dev = crtc->dev; |
| 933 | intel_clock_t clock; |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 934 | |
| 935 | /* return directly when it is eDP */ |
| 936 | if (HAS_eDP) |
| 937 | return true; |
| 938 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 939 | if (target < 200000) { |
| 940 | clock.n = 1; |
| 941 | clock.p1 = 2; |
| 942 | clock.p2 = 10; |
| 943 | clock.m1 = 12; |
| 944 | clock.m2 = 9; |
| 945 | } else { |
| 946 | clock.n = 2; |
| 947 | clock.p1 = 1; |
| 948 | clock.p2 = 10; |
| 949 | clock.m1 = 14; |
| 950 | clock.m2 = 8; |
| 951 | } |
| 952 | intel_clock(dev, refclk, &clock); |
| 953 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
| 954 | return true; |
| 955 | } |
| 956 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 957 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
| 958 | static bool |
| 959 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 960 | int target, int refclk, intel_clock_t *best_clock) |
| 961 | { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 962 | intel_clock_t clock; |
| 963 | if (target < 200000) { |
| 964 | clock.p1 = 2; |
| 965 | clock.p2 = 10; |
| 966 | clock.n = 2; |
| 967 | clock.m1 = 23; |
| 968 | clock.m2 = 8; |
| 969 | } else { |
| 970 | clock.p1 = 1; |
| 971 | clock.p2 = 10; |
| 972 | clock.n = 1; |
| 973 | clock.m1 = 14; |
| 974 | clock.m2 = 2; |
| 975 | } |
| 976 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); |
| 977 | clock.p = (clock.p1 * clock.p2); |
| 978 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; |
| 979 | clock.vco = 0; |
| 980 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
| 981 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 982 | } |
| 983 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 984 | /** |
| 985 | * intel_wait_for_vblank - wait for vblank on a given pipe |
| 986 | * @dev: drm device |
| 987 | * @pipe: pipe to wait for |
| 988 | * |
| 989 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
| 990 | * mode setting code. |
| 991 | */ |
| 992 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 993 | { |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 994 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 995 | int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT); |
| 996 | |
Chris Wilson | 300387c | 2010-09-05 20:25:43 +0100 | [diff] [blame] | 997 | /* Clear existing vblank status. Note this will clear any other |
| 998 | * sticky status fields as well. |
| 999 | * |
| 1000 | * This races with i915_driver_irq_handler() with the result |
| 1001 | * that either function could miss a vblank event. Here it is not |
| 1002 | * fatal, as we will either wait upon the next vblank interrupt or |
| 1003 | * timeout. Generally speaking intel_wait_for_vblank() is only |
| 1004 | * called during modeset at which time the GPU should be idle and |
| 1005 | * should *not* be performing page flips and thus not waiting on |
| 1006 | * vblanks... |
| 1007 | * Currently, the result of us stealing a vblank from the irq |
| 1008 | * handler is that a single frame will be skipped during swapbuffers. |
| 1009 | */ |
| 1010 | I915_WRITE(pipestat_reg, |
| 1011 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
| 1012 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1013 | /* Wait for vblank interrupt bit to set */ |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 1014 | if (wait_for(I915_READ(pipestat_reg) & |
| 1015 | PIPE_VBLANK_INTERRUPT_STATUS, |
| 1016 | 50)) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1017 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
| 1018 | } |
| 1019 | |
| 1020 | /** |
| 1021 | * intel_wait_for_vblank_off - wait for vblank after disabling a pipe |
| 1022 | * @dev: drm device |
| 1023 | * @pipe: pipe to wait for |
| 1024 | * |
| 1025 | * After disabling a pipe, we can't wait for vblank in the usual way, |
| 1026 | * spinning on the vblank interrupt status bit, since we won't actually |
| 1027 | * see an interrupt when the pipe is disabled. |
| 1028 | * |
| 1029 | * So this function waits for the display line value to settle (it |
| 1030 | * usually ends up stopping at the start of the next frame). |
| 1031 | */ |
| 1032 | void intel_wait_for_vblank_off(struct drm_device *dev, int pipe) |
| 1033 | { |
| 1034 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1035 | int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL); |
| 1036 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
Chris Wilson | ec5da01 | 2010-09-12 13:34:08 +0100 | [diff] [blame] | 1037 | u32 last_line, line; |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1038 | |
| 1039 | /* Wait for the display line to settle */ |
Chris Wilson | ec5da01 | 2010-09-12 13:34:08 +0100 | [diff] [blame] | 1040 | line = I915_READ(pipedsl_reg) & DSL_LINEMASK; |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1041 | do { |
Chris Wilson | ec5da01 | 2010-09-12 13:34:08 +0100 | [diff] [blame] | 1042 | last_line = line; |
| 1043 | MSLEEP(5); |
| 1044 | line = I915_READ(pipedsl_reg) & DSL_LINEMASK; |
| 1045 | } while (line != last_line && time_after(timeout, jiffies)); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1046 | |
Chris Wilson | ec5da01 | 2010-09-12 13:34:08 +0100 | [diff] [blame] | 1047 | if (line != last_line) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1048 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1049 | } |
| 1050 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1051 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 1052 | { |
| 1053 | struct drm_device *dev = crtc->dev; |
| 1054 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1055 | struct drm_framebuffer *fb = crtc->fb; |
| 1056 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1057 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1058 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1059 | int plane, i; |
| 1060 | u32 fbc_ctl, fbc_ctl2; |
| 1061 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1062 | if (fb->pitch == dev_priv->cfb_pitch && |
| 1063 | obj_priv->fence_reg == dev_priv->cfb_fence && |
| 1064 | intel_crtc->plane == dev_priv->cfb_plane && |
| 1065 | I915_READ(FBC_CONTROL) & FBC_CTL_EN) |
| 1066 | return; |
| 1067 | |
| 1068 | i8xx_disable_fbc(dev); |
| 1069 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1070 | dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
| 1071 | |
| 1072 | if (fb->pitch < dev_priv->cfb_pitch) |
| 1073 | dev_priv->cfb_pitch = fb->pitch; |
| 1074 | |
| 1075 | /* FBC_CTL wants 64B units */ |
| 1076 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
| 1077 | dev_priv->cfb_fence = obj_priv->fence_reg; |
| 1078 | dev_priv->cfb_plane = intel_crtc->plane; |
| 1079 | plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; |
| 1080 | |
| 1081 | /* Clear old tags */ |
| 1082 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
| 1083 | I915_WRITE(FBC_TAG + (i * 4), 0); |
| 1084 | |
| 1085 | /* Set it up... */ |
| 1086 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane; |
| 1087 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1088 | fbc_ctl2 |= FBC_CTL_CPU_FENCE; |
| 1089 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
| 1090 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
| 1091 | |
| 1092 | /* enable it... */ |
| 1093 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; |
Jesse Barnes | ee25df2 | 2010-02-06 10:41:53 -0800 | [diff] [blame] | 1094 | if (IS_I945GM(dev)) |
Priit Laes | 4967790 | 2010-03-02 11:37:00 +0200 | [diff] [blame] | 1095 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1096 | fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
| 1097 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
| 1098 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1099 | fbc_ctl |= dev_priv->cfb_fence; |
| 1100 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 1101 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1102 | DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ", |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1103 | dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1104 | } |
| 1105 | |
| 1106 | void i8xx_disable_fbc(struct drm_device *dev) |
| 1107 | { |
| 1108 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1109 | u32 fbc_ctl; |
| 1110 | |
| 1111 | /* Disable compression */ |
| 1112 | fbc_ctl = I915_READ(FBC_CONTROL); |
Chris Wilson | a5cad62 | 2010-09-22 13:15:10 +0100 | [diff] [blame^] | 1113 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
| 1114 | return; |
| 1115 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1116 | fbc_ctl &= ~FBC_CTL_EN; |
| 1117 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 1118 | |
| 1119 | /* Wait for compressing bit to clear */ |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 1120 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 1121 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
| 1122 | return; |
Jesse Barnes | 9517a92 | 2010-05-21 09:40:45 -0700 | [diff] [blame] | 1123 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1124 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1125 | DRM_DEBUG_KMS("disabled FBC\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1126 | } |
| 1127 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1128 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1129 | { |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1130 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1131 | |
| 1132 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
| 1133 | } |
| 1134 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1135 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 1136 | { |
| 1137 | struct drm_device *dev = crtc->dev; |
| 1138 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1139 | struct drm_framebuffer *fb = crtc->fb; |
| 1140 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1141 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1143 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1144 | unsigned long stall_watermark = 200; |
| 1145 | u32 dpfc_ctl; |
| 1146 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1147 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
| 1148 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 1149 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && |
| 1150 | dev_priv->cfb_fence == obj_priv->fence_reg && |
| 1151 | dev_priv->cfb_plane == intel_crtc->plane && |
| 1152 | dev_priv->cfb_y == crtc->y) |
| 1153 | return; |
| 1154 | |
| 1155 | I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); |
| 1156 | POSTING_READ(DPFC_CONTROL); |
| 1157 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 1158 | } |
| 1159 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1160 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
| 1161 | dev_priv->cfb_fence = obj_priv->fence_reg; |
| 1162 | dev_priv->cfb_plane = intel_crtc->plane; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1163 | dev_priv->cfb_y = crtc->y; |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1164 | |
| 1165 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
| 1166 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
| 1167 | dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence; |
| 1168 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
| 1169 | } else { |
| 1170 | I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY); |
| 1171 | } |
| 1172 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1173 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
| 1174 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
| 1175 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
| 1176 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
| 1177 | |
| 1178 | /* enable it... */ |
| 1179 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); |
| 1180 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1181 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1182 | } |
| 1183 | |
| 1184 | void g4x_disable_fbc(struct drm_device *dev) |
| 1185 | { |
| 1186 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1187 | u32 dpfc_ctl; |
| 1188 | |
| 1189 | /* Disable compression */ |
| 1190 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1191 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 1192 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 1193 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1194 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1195 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 1196 | } |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1197 | } |
| 1198 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1199 | static bool g4x_fbc_enabled(struct drm_device *dev) |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1200 | { |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1201 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1202 | |
| 1203 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
| 1204 | } |
| 1205 | |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1206 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 1207 | { |
| 1208 | struct drm_device *dev = crtc->dev; |
| 1209 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1210 | struct drm_framebuffer *fb = crtc->fb; |
| 1211 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 1212 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
| 1213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1214 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1215 | unsigned long stall_watermark = 200; |
| 1216 | u32 dpfc_ctl; |
| 1217 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1218 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
| 1219 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 1220 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && |
| 1221 | dev_priv->cfb_fence == obj_priv->fence_reg && |
| 1222 | dev_priv->cfb_plane == intel_crtc->plane && |
| 1223 | dev_priv->cfb_offset == obj_priv->gtt_offset && |
| 1224 | dev_priv->cfb_y == crtc->y) |
| 1225 | return; |
| 1226 | |
| 1227 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); |
| 1228 | POSTING_READ(ILK_DPFC_CONTROL); |
| 1229 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 1230 | } |
| 1231 | |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1232 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
| 1233 | dev_priv->cfb_fence = obj_priv->fence_reg; |
| 1234 | dev_priv->cfb_plane = intel_crtc->plane; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1235 | dev_priv->cfb_offset = obj_priv->gtt_offset; |
| 1236 | dev_priv->cfb_y = crtc->y; |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1237 | |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1238 | dpfc_ctl &= DPFC_RESERVED; |
| 1239 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); |
| 1240 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
| 1241 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence); |
| 1242 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
| 1243 | } else { |
| 1244 | I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY); |
| 1245 | } |
| 1246 | |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1247 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
| 1248 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
| 1249 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
| 1250 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
| 1251 | I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID); |
| 1252 | /* enable it... */ |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1253 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1254 | |
| 1255 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
| 1256 | } |
| 1257 | |
| 1258 | void ironlake_disable_fbc(struct drm_device *dev) |
| 1259 | { |
| 1260 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1261 | u32 dpfc_ctl; |
| 1262 | |
| 1263 | /* Disable compression */ |
| 1264 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1265 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 1266 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 1267 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1268 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1269 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 1270 | } |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1271 | } |
| 1272 | |
| 1273 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
| 1274 | { |
| 1275 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1276 | |
| 1277 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
| 1278 | } |
| 1279 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1280 | bool intel_fbc_enabled(struct drm_device *dev) |
| 1281 | { |
| 1282 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1283 | |
| 1284 | if (!dev_priv->display.fbc_enabled) |
| 1285 | return false; |
| 1286 | |
| 1287 | return dev_priv->display.fbc_enabled(dev); |
| 1288 | } |
| 1289 | |
| 1290 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 1291 | { |
| 1292 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 1293 | |
| 1294 | if (!dev_priv->display.enable_fbc) |
| 1295 | return; |
| 1296 | |
| 1297 | dev_priv->display.enable_fbc(crtc, interval); |
| 1298 | } |
| 1299 | |
| 1300 | void intel_disable_fbc(struct drm_device *dev) |
| 1301 | { |
| 1302 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1303 | |
| 1304 | if (!dev_priv->display.disable_fbc) |
| 1305 | return; |
| 1306 | |
| 1307 | dev_priv->display.disable_fbc(dev); |
| 1308 | } |
| 1309 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1310 | /** |
| 1311 | * intel_update_fbc - enable/disable FBC as needed |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1312 | * @dev: the drm_device |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1313 | * |
| 1314 | * Set up the framebuffer compression hardware at mode set time. We |
| 1315 | * enable it if possible: |
| 1316 | * - plane A only (on pre-965) |
| 1317 | * - no pixel mulitply/line duplication |
| 1318 | * - no alpha buffer discard |
| 1319 | * - no dual wide |
| 1320 | * - framebuffer <= 2048 in width, 1536 in height |
| 1321 | * |
| 1322 | * We can't assume that any compression will take place (worst case), |
| 1323 | * so the compressed buffer has to be the same size as the uncompressed |
| 1324 | * one. It also must reside (along with the line length buffer) in |
| 1325 | * stolen memory. |
| 1326 | * |
| 1327 | * We need to enable/disable FBC on a global basis. |
| 1328 | */ |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1329 | static void intel_update_fbc(struct drm_device *dev) |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1330 | { |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1331 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1332 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
| 1333 | struct intel_crtc *intel_crtc; |
| 1334 | struct drm_framebuffer *fb; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1335 | struct intel_framebuffer *intel_fb; |
| 1336 | struct drm_i915_gem_object *obj_priv; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1337 | |
| 1338 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1339 | |
| 1340 | if (!i915_powersave) |
| 1341 | return; |
| 1342 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1343 | if (!I915_HAS_FBC(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1344 | return; |
| 1345 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1346 | /* |
| 1347 | * If FBC is already on, we just have to verify that we can |
| 1348 | * keep it that way... |
| 1349 | * Need to disable if: |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1350 | * - more than one pipe is active |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1351 | * - changing FBC params (stride, fence, mode) |
| 1352 | * - new fb is too large to fit in compressed buffer |
| 1353 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
| 1354 | */ |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1355 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1356 | if (tmp_crtc->enabled) { |
| 1357 | if (crtc) { |
| 1358 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); |
| 1359 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; |
| 1360 | goto out_disable; |
| 1361 | } |
| 1362 | crtc = tmp_crtc; |
| 1363 | } |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1364 | } |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1365 | |
| 1366 | if (!crtc || crtc->fb == NULL) { |
| 1367 | DRM_DEBUG_KMS("no output, disabling\n"); |
| 1368 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1369 | goto out_disable; |
| 1370 | } |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1371 | |
| 1372 | intel_crtc = to_intel_crtc(crtc); |
| 1373 | fb = crtc->fb; |
| 1374 | intel_fb = to_intel_framebuffer(fb); |
| 1375 | obj_priv = to_intel_bo(intel_fb->obj); |
| 1376 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1377 | if (intel_fb->obj->size > dev_priv->cfb_size) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1378 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1379 | "compression\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1380 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1381 | goto out_disable; |
| 1382 | } |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1383 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
| 1384 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1385 | DRM_DEBUG_KMS("mode incompatible with compression, " |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1386 | "disabling\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1387 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1388 | goto out_disable; |
| 1389 | } |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1390 | if ((crtc->mode.hdisplay > 2048) || |
| 1391 | (crtc->mode.vdisplay > 1536)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1392 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1393 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1394 | goto out_disable; |
| 1395 | } |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1396 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1397 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1398 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1399 | goto out_disable; |
| 1400 | } |
| 1401 | if (obj_priv->tiling_mode != I915_TILING_X) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1402 | DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1403 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1404 | goto out_disable; |
| 1405 | } |
| 1406 | |
Jason Wessel | c924b93 | 2010-08-05 09:22:32 -0500 | [diff] [blame] | 1407 | /* If the kernel debugger is active, always disable compression */ |
| 1408 | if (in_dbg_master()) |
| 1409 | goto out_disable; |
| 1410 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1411 | intel_enable_fbc(crtc, 500); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1412 | return; |
| 1413 | |
| 1414 | out_disable: |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1415 | /* Multiple disables should be harmless */ |
Chris Wilson | a939406 | 2010-05-27 13:18:16 +0100 | [diff] [blame] | 1416 | if (intel_fbc_enabled(dev)) { |
| 1417 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1418 | intel_disable_fbc(dev); |
Chris Wilson | a939406 | 2010-05-27 13:18:16 +0100 | [diff] [blame] | 1419 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1420 | } |
| 1421 | |
Chris Wilson | 127bd2a | 2010-07-23 23:32:05 +0100 | [diff] [blame] | 1422 | int |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 1423 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
| 1424 | struct drm_gem_object *obj, |
| 1425 | bool pipelined) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1426 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1427 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1428 | u32 alignment; |
| 1429 | int ret; |
| 1430 | |
| 1431 | switch (obj_priv->tiling_mode) { |
| 1432 | case I915_TILING_NONE: |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 1433 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
| 1434 | alignment = 128 * 1024; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1435 | else if (INTEL_INFO(dev)->gen >= 4) |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 1436 | alignment = 4 * 1024; |
| 1437 | else |
| 1438 | alignment = 64 * 1024; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1439 | break; |
| 1440 | case I915_TILING_X: |
| 1441 | /* pin() will align the object as required by fence */ |
| 1442 | alignment = 0; |
| 1443 | break; |
| 1444 | case I915_TILING_Y: |
| 1445 | /* FIXME: Is this true? */ |
| 1446 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); |
| 1447 | return -EINVAL; |
| 1448 | default: |
| 1449 | BUG(); |
| 1450 | } |
| 1451 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1452 | ret = i915_gem_object_pin(obj, alignment); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 1453 | if (ret) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1454 | return ret; |
| 1455 | |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 1456 | ret = i915_gem_object_set_to_display_plane(obj, pipelined); |
| 1457 | if (ret) |
| 1458 | goto err_unpin; |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 1459 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1460 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
| 1461 | * fence, whereas 965+ only requires a fence if using |
| 1462 | * framebuffer compression. For simplicity, we always install |
| 1463 | * a fence as the cost is not that onerous. |
| 1464 | */ |
| 1465 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE && |
| 1466 | obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1467 | ret = i915_gem_object_get_fence_reg(obj, false); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 1468 | if (ret) |
| 1469 | goto err_unpin; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1470 | } |
| 1471 | |
| 1472 | return 0; |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 1473 | |
| 1474 | err_unpin: |
| 1475 | i915_gem_object_unpin(obj); |
| 1476 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1477 | } |
| 1478 | |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1479 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
| 1480 | static int |
| 1481 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 1482 | int x, int y) |
| 1483 | { |
| 1484 | struct drm_device *dev = crtc->dev; |
| 1485 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1486 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1487 | struct intel_framebuffer *intel_fb; |
| 1488 | struct drm_i915_gem_object *obj_priv; |
| 1489 | struct drm_gem_object *obj; |
| 1490 | int plane = intel_crtc->plane; |
| 1491 | unsigned long Start, Offset; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1492 | u32 dspcntr; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1493 | u32 reg; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1494 | |
| 1495 | switch (plane) { |
| 1496 | case 0: |
| 1497 | case 1: |
| 1498 | break; |
| 1499 | default: |
| 1500 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
| 1501 | return -EINVAL; |
| 1502 | } |
| 1503 | |
| 1504 | intel_fb = to_intel_framebuffer(fb); |
| 1505 | obj = intel_fb->obj; |
| 1506 | obj_priv = to_intel_bo(obj); |
| 1507 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1508 | reg = DSPCNTR(plane); |
| 1509 | dspcntr = I915_READ(reg); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1510 | /* Mask out pixel format bits in case we change it */ |
| 1511 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
| 1512 | switch (fb->bits_per_pixel) { |
| 1513 | case 8: |
| 1514 | dspcntr |= DISPPLANE_8BPP; |
| 1515 | break; |
| 1516 | case 16: |
| 1517 | if (fb->depth == 15) |
| 1518 | dspcntr |= DISPPLANE_15_16BPP; |
| 1519 | else |
| 1520 | dspcntr |= DISPPLANE_16BPP; |
| 1521 | break; |
| 1522 | case 24: |
| 1523 | case 32: |
| 1524 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
| 1525 | break; |
| 1526 | default: |
| 1527 | DRM_ERROR("Unknown color depth\n"); |
| 1528 | return -EINVAL; |
| 1529 | } |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1530 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1531 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1532 | dspcntr |= DISPPLANE_TILED; |
| 1533 | else |
| 1534 | dspcntr &= ~DISPPLANE_TILED; |
| 1535 | } |
| 1536 | |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 1537 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1538 | /* must disable */ |
| 1539 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| 1540 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1541 | I915_WRITE(reg, dspcntr); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1542 | |
| 1543 | Start = obj_priv->gtt_offset; |
| 1544 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); |
| 1545 | |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 1546 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
| 1547 | Start, Offset, x, y, fb->pitch); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1548 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1549 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1550 | I915_WRITE(DSPSURF(plane), Start); |
| 1551 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
| 1552 | I915_WRITE(DSPADDR(plane), Offset); |
| 1553 | } else |
| 1554 | I915_WRITE(DSPADDR(plane), Start + Offset); |
| 1555 | POSTING_READ(reg); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1556 | |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1557 | intel_update_fbc(dev); |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 1558 | intel_increase_pllclock(crtc); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1559 | |
| 1560 | return 0; |
| 1561 | } |
| 1562 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1563 | static int |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1564 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
| 1565 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1566 | { |
| 1567 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1568 | struct drm_i915_master_private *master_priv; |
| 1569 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1570 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1571 | |
| 1572 | /* no fb bound */ |
| 1573 | if (!crtc->fb) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1574 | DRM_DEBUG_KMS("No FB bound\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1575 | return 0; |
| 1576 | } |
| 1577 | |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 1578 | switch (intel_crtc->plane) { |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1579 | case 0: |
| 1580 | case 1: |
| 1581 | break; |
| 1582 | default: |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1583 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1584 | } |
| 1585 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1586 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 1587 | ret = intel_pin_and_fence_fb_obj(dev, |
| 1588 | to_intel_framebuffer(crtc->fb)->obj, |
| 1589 | false); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1590 | if (ret != 0) { |
| 1591 | mutex_unlock(&dev->struct_mutex); |
| 1592 | return ret; |
| 1593 | } |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1594 | |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 1595 | if (old_fb) { |
| 1596 | struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
| 1597 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 1598 | |
| 1599 | if (atomic_read(&obj_priv->pending_flip)) { |
| 1600 | ret = i915_gem_wait_for_pending_flip(dev, &obj, 1); |
| 1601 | if (ret) { |
| 1602 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
| 1603 | mutex_unlock(&dev->struct_mutex); |
| 1604 | return ret; |
| 1605 | } |
| 1606 | } |
| 1607 | } |
| 1608 | |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 1609 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y); |
| 1610 | if (ret) { |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 1611 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1612 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 1613 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1614 | } |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1615 | |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 1616 | if (old_fb) |
| 1617 | i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1618 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1619 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1620 | |
| 1621 | if (!dev->primary->master) |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1622 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1623 | |
| 1624 | master_priv = dev->primary->master->driver_priv; |
| 1625 | if (!master_priv->sarea_priv) |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1626 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1627 | |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 1628 | if (intel_crtc->pipe) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1629 | master_priv->sarea_priv->pipeB_x = x; |
| 1630 | master_priv->sarea_priv->pipeB_y = y; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1631 | } else { |
| 1632 | master_priv->sarea_priv->pipeA_x = x; |
| 1633 | master_priv->sarea_priv->pipeA_y = y; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1634 | } |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1635 | |
| 1636 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1637 | } |
| 1638 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1639 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1640 | { |
| 1641 | struct drm_device *dev = crtc->dev; |
| 1642 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1643 | u32 dpa_ctl; |
| 1644 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1645 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1646 | dpa_ctl = I915_READ(DP_A); |
| 1647 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
| 1648 | |
| 1649 | if (clock < 200000) { |
| 1650 | u32 temp; |
| 1651 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
| 1652 | /* workaround for 160Mhz: |
| 1653 | 1) program 0x4600c bits 15:0 = 0x8124 |
| 1654 | 2) program 0x46010 bit 0 = 1 |
| 1655 | 3) program 0x46034 bit 24 = 1 |
| 1656 | 4) program 0x64000 bit 14 = 1 |
| 1657 | */ |
| 1658 | temp = I915_READ(0x4600c); |
| 1659 | temp &= 0xffff0000; |
| 1660 | I915_WRITE(0x4600c, temp | 0x8124); |
| 1661 | |
| 1662 | temp = I915_READ(0x46010); |
| 1663 | I915_WRITE(0x46010, temp | 1); |
| 1664 | |
| 1665 | temp = I915_READ(0x46034); |
| 1666 | I915_WRITE(0x46034, temp | (1 << 24)); |
| 1667 | } else { |
| 1668 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
| 1669 | } |
| 1670 | I915_WRITE(DP_A, dpa_ctl); |
| 1671 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1672 | POSTING_READ(DP_A); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1673 | udelay(500); |
| 1674 | } |
| 1675 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1676 | /* The FDI link training functions for ILK/Ibexpeak. */ |
| 1677 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
| 1678 | { |
| 1679 | struct drm_device *dev = crtc->dev; |
| 1680 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1681 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1682 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1683 | u32 reg, temp, tries; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1684 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 1685 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 1686 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1687 | reg = FDI_RX_IMR(pipe); |
| 1688 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 1689 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 1690 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1691 | I915_WRITE(reg, temp); |
| 1692 | I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 1693 | udelay(150); |
| 1694 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1695 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1696 | reg = FDI_TX_CTL(pipe); |
| 1697 | temp = I915_READ(reg); |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 1698 | temp &= ~(7 << 19); |
| 1699 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1700 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1701 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1702 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1703 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1704 | reg = FDI_RX_CTL(pipe); |
| 1705 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1706 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1707 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1708 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 1709 | |
| 1710 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1711 | udelay(150); |
| 1712 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1713 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 1714 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1715 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1716 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 1717 | |
| 1718 | if ((temp & FDI_RX_BIT_LOCK)) { |
| 1719 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1720 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1721 | break; |
| 1722 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1723 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 1724 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1725 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1726 | |
| 1727 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1728 | reg = FDI_TX_CTL(pipe); |
| 1729 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1730 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1731 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1732 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1733 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1734 | reg = FDI_RX_CTL(pipe); |
| 1735 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1736 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1737 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1738 | I915_WRITE(reg, temp); |
| 1739 | |
| 1740 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1741 | udelay(150); |
| 1742 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1743 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 1744 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1745 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1746 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 1747 | |
| 1748 | if (temp & FDI_RX_SYMBOL_LOCK) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1749 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1750 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 1751 | break; |
| 1752 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1753 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 1754 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1755 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1756 | |
| 1757 | DRM_DEBUG_KMS("FDI train done\n"); |
| 1758 | } |
| 1759 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1760 | static const int const snb_b_fdi_train_param [] = { |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1761 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
| 1762 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
| 1763 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
| 1764 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
| 1765 | }; |
| 1766 | |
| 1767 | /* The FDI link training functions for SNB/Cougarpoint. */ |
| 1768 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
| 1769 | { |
| 1770 | struct drm_device *dev = crtc->dev; |
| 1771 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1773 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1774 | u32 reg, temp, i; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1775 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 1776 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 1777 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1778 | reg = FDI_RX_IMR(pipe); |
| 1779 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 1780 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 1781 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1782 | I915_WRITE(reg, temp); |
| 1783 | |
| 1784 | POSTING_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 1785 | udelay(150); |
| 1786 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1787 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1788 | reg = FDI_TX_CTL(pipe); |
| 1789 | temp = I915_READ(reg); |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 1790 | temp &= ~(7 << 19); |
| 1791 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1792 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1793 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 1794 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 1795 | /* SNB-B */ |
| 1796 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1797 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1798 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1799 | reg = FDI_RX_CTL(pipe); |
| 1800 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1801 | if (HAS_PCH_CPT(dev)) { |
| 1802 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 1803 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 1804 | } else { |
| 1805 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1806 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 1807 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1808 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 1809 | |
| 1810 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1811 | udelay(150); |
| 1812 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1813 | for (i = 0; i < 4; i++ ) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1814 | reg = FDI_TX_CTL(pipe); |
| 1815 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1816 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 1817 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1818 | I915_WRITE(reg, temp); |
| 1819 | |
| 1820 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1821 | udelay(500); |
| 1822 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1823 | reg = FDI_RX_IIR(pipe); |
| 1824 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1825 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 1826 | |
| 1827 | if (temp & FDI_RX_BIT_LOCK) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1828 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1829 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 1830 | break; |
| 1831 | } |
| 1832 | } |
| 1833 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1834 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1835 | |
| 1836 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1837 | reg = FDI_TX_CTL(pipe); |
| 1838 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1839 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1840 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 1841 | if (IS_GEN6(dev)) { |
| 1842 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 1843 | /* SNB-B */ |
| 1844 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 1845 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1846 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1847 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1848 | reg = FDI_RX_CTL(pipe); |
| 1849 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1850 | if (HAS_PCH_CPT(dev)) { |
| 1851 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 1852 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 1853 | } else { |
| 1854 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1855 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 1856 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1857 | I915_WRITE(reg, temp); |
| 1858 | |
| 1859 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1860 | udelay(150); |
| 1861 | |
| 1862 | for (i = 0; i < 4; i++ ) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1863 | reg = FDI_TX_CTL(pipe); |
| 1864 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1865 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 1866 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1867 | I915_WRITE(reg, temp); |
| 1868 | |
| 1869 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1870 | udelay(500); |
| 1871 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1872 | reg = FDI_RX_IIR(pipe); |
| 1873 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1874 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 1875 | |
| 1876 | if (temp & FDI_RX_SYMBOL_LOCK) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1877 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1878 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 1879 | break; |
| 1880 | } |
| 1881 | } |
| 1882 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1883 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1884 | |
| 1885 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 1886 | } |
| 1887 | |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 1888 | static void ironlake_fdi_enable(struct drm_crtc *crtc) |
| 1889 | { |
| 1890 | struct drm_device *dev = crtc->dev; |
| 1891 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1892 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1893 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1894 | u32 reg, temp; |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 1895 | |
Jesse Barnes | c64e311 | 2010-09-10 11:27:03 -0700 | [diff] [blame] | 1896 | /* Write the TU size bits so error detection works */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1897 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
| 1898 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
Jesse Barnes | c64e311 | 2010-09-10 11:27:03 -0700 | [diff] [blame] | 1899 | |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 1900 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1901 | reg = FDI_RX_CTL(pipe); |
| 1902 | temp = I915_READ(reg); |
| 1903 | temp &= ~((0x7 << 19) | (0x7 << 16)); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 1904 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1905 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
| 1906 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
| 1907 | |
| 1908 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 1909 | udelay(200); |
| 1910 | |
| 1911 | /* Switch from Rawclk to PCDclk */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1912 | temp = I915_READ(reg); |
| 1913 | I915_WRITE(reg, temp | FDI_PCDCLK); |
| 1914 | |
| 1915 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 1916 | udelay(200); |
| 1917 | |
| 1918 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1919 | reg = FDI_TX_CTL(pipe); |
| 1920 | temp = I915_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 1921 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1922 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
| 1923 | |
| 1924 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 1925 | udelay(100); |
| 1926 | } |
| 1927 | } |
| 1928 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1929 | static void intel_flush_display_plane(struct drm_device *dev, |
| 1930 | int plane) |
| 1931 | { |
| 1932 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1933 | u32 reg = DSPADDR(plane); |
| 1934 | I915_WRITE(reg, I915_READ(reg)); |
| 1935 | } |
| 1936 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 1937 | /* |
| 1938 | * When we disable a pipe, we need to clear any pending scanline wait events |
| 1939 | * to avoid hanging the ring, which we assume we are waiting on. |
| 1940 | */ |
| 1941 | static void intel_clear_scanline_wait(struct drm_device *dev) |
| 1942 | { |
| 1943 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1944 | u32 tmp; |
| 1945 | |
| 1946 | if (IS_GEN2(dev)) |
| 1947 | /* Can't break the hang on i8xx */ |
| 1948 | return; |
| 1949 | |
| 1950 | tmp = I915_READ(PRB0_CTL); |
| 1951 | if (tmp & RING_WAIT) { |
| 1952 | I915_WRITE(PRB0_CTL, tmp); |
| 1953 | POSTING_READ(PRB0_CTL); |
| 1954 | } |
| 1955 | } |
| 1956 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 1957 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1958 | { |
| 1959 | struct drm_device *dev = crtc->dev; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1960 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1962 | int pipe = intel_crtc->pipe; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1963 | int plane = intel_crtc->plane; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1964 | u32 reg, temp; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1965 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 1966 | if (intel_crtc->active) |
| 1967 | return; |
| 1968 | |
| 1969 | intel_crtc->active = true; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 1970 | intel_update_watermarks(dev); |
| 1971 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 1972 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 1973 | temp = I915_READ(PCH_LVDS); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1974 | if ((temp & LVDS_PORT_EN) == 0) |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 1975 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 1976 | } |
| 1977 | |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 1978 | ironlake_fdi_enable(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 1979 | |
| 1980 | /* Enable panel fitting for LVDS */ |
| 1981 | if (dev_priv->pch_pf_size && |
| 1982 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) |
| 1983 | || HAS_eDP || intel_pch_has_edp(crtc))) { |
| 1984 | /* Force use of hard-coded filter coefficients |
| 1985 | * as some pre-programmed values are broken, |
| 1986 | * e.g. x201. |
| 1987 | */ |
| 1988 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, |
| 1989 | PF_ENABLE | PF_FILTER_MED_3x3); |
| 1990 | I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS, |
| 1991 | dev_priv->pch_pf_pos); |
| 1992 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, |
| 1993 | dev_priv->pch_pf_size); |
| 1994 | } |
| 1995 | |
| 1996 | /* Enable CPU pipe */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1997 | reg = PIPECONF(pipe); |
| 1998 | temp = I915_READ(reg); |
| 1999 | if ((temp & PIPECONF_ENABLE) == 0) { |
| 2000 | I915_WRITE(reg, temp | PIPECONF_ENABLE); |
| 2001 | POSTING_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2002 | udelay(100); |
| 2003 | } |
| 2004 | |
| 2005 | /* configure and enable CPU plane */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2006 | reg = DSPCNTR(plane); |
| 2007 | temp = I915_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2008 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2009 | I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE); |
| 2010 | intel_flush_display_plane(dev, plane); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2011 | } |
| 2012 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2013 | /* For PCH output, training FDI link */ |
| 2014 | if (IS_GEN6(dev)) |
| 2015 | gen6_fdi_link_train(crtc); |
| 2016 | else |
| 2017 | ironlake_fdi_link_train(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2018 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2019 | /* enable PCH DPLL */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2020 | reg = PCH_DPLL(pipe); |
| 2021 | temp = I915_READ(reg); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2022 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2023 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); |
| 2024 | POSTING_READ(reg); |
Chris Wilson | 8c4223b | 2010-09-10 22:33:42 +0100 | [diff] [blame] | 2025 | udelay(200); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2026 | } |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2027 | |
| 2028 | if (HAS_PCH_CPT(dev)) { |
| 2029 | /* Be sure PCH DPLL SEL is set */ |
| 2030 | temp = I915_READ(PCH_DPLL_SEL); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2031 | if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0) |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2032 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2033 | else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0) |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2034 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
| 2035 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2036 | } |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2037 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2038 | /* set transcoder timing */ |
| 2039 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
| 2040 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); |
| 2041 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); |
| 2042 | |
| 2043 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
| 2044 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); |
| 2045 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2046 | |
| 2047 | /* enable normal train */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2048 | reg = FDI_TX_CTL(pipe); |
| 2049 | temp = I915_READ(reg); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2050 | temp &= ~FDI_LINK_TRAIN_NONE; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2051 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
| 2052 | I915_WRITE(reg, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2053 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2054 | reg = FDI_RX_CTL(pipe); |
| 2055 | temp = I915_READ(reg); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2056 | if (HAS_PCH_CPT(dev)) { |
| 2057 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2058 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
| 2059 | } else { |
| 2060 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2061 | temp |= FDI_LINK_TRAIN_NONE; |
| 2062 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2063 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2064 | |
| 2065 | /* wait one idle pattern time */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2066 | POSTING_READ(reg); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2067 | udelay(100); |
| 2068 | |
| 2069 | /* For PCH DP, enable TRANS_DP_CTL */ |
| 2070 | if (HAS_PCH_CPT(dev) && |
| 2071 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2072 | reg = TRANS_DP_CTL(pipe); |
| 2073 | temp = I915_READ(reg); |
| 2074 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
| 2075 | TRANS_DP_SYNC_MASK); |
| 2076 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
| 2077 | TRANS_DP_ENH_FRAMING); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2078 | |
| 2079 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2080 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2081 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2082 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2083 | |
| 2084 | switch (intel_trans_dp_port_sel(crtc)) { |
| 2085 | case PCH_DP_B: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2086 | temp |= TRANS_DP_PORT_SEL_B; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2087 | break; |
| 2088 | case PCH_DP_C: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2089 | temp |= TRANS_DP_PORT_SEL_C; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2090 | break; |
| 2091 | case PCH_DP_D: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2092 | temp |= TRANS_DP_PORT_SEL_D; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2093 | break; |
| 2094 | default: |
| 2095 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2096 | temp |= TRANS_DP_PORT_SEL_B; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2097 | break; |
| 2098 | } |
| 2099 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2100 | I915_WRITE(reg, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2101 | } |
| 2102 | |
| 2103 | /* enable PCH transcoder */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2104 | reg = TRANSCONF(pipe); |
| 2105 | temp = I915_READ(reg); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2106 | /* |
| 2107 | * make the BPC in transcoder be consistent with |
| 2108 | * that in pipeconf reg. |
| 2109 | */ |
| 2110 | temp &= ~PIPE_BPC_MASK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2111 | temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; |
| 2112 | I915_WRITE(reg, temp | TRANS_ENABLE); |
| 2113 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2114 | DRM_ERROR("failed to enable transcoder\n"); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2115 | |
| 2116 | intel_crtc_load_lut(crtc); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 2117 | intel_update_fbc(dev); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2118 | intel_crtc_update_cursor(crtc, true); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2119 | } |
| 2120 | |
| 2121 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
| 2122 | { |
| 2123 | struct drm_device *dev = crtc->dev; |
| 2124 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2125 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2126 | int pipe = intel_crtc->pipe; |
| 2127 | int plane = intel_crtc->plane; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2128 | u32 reg, temp; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2129 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 2130 | if (!intel_crtc->active) |
| 2131 | return; |
| 2132 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2133 | drm_vblank_off(dev, pipe); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2134 | intel_crtc_update_cursor(crtc, false); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2135 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2136 | /* Disable display plane */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2137 | reg = DSPCNTR(plane); |
| 2138 | temp = I915_READ(reg); |
| 2139 | if (temp & DISPLAY_PLANE_ENABLE) { |
| 2140 | I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE); |
| 2141 | intel_flush_display_plane(dev, plane); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2142 | } |
| 2143 | |
| 2144 | if (dev_priv->cfb_plane == plane && |
| 2145 | dev_priv->display.disable_fbc) |
| 2146 | dev_priv->display.disable_fbc(dev); |
| 2147 | |
| 2148 | /* disable cpu pipe, disable after all planes disabled */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2149 | reg = PIPECONF(pipe); |
| 2150 | temp = I915_READ(reg); |
| 2151 | if (temp & PIPECONF_ENABLE) { |
| 2152 | I915_WRITE(reg, temp & ~PIPECONF_ENABLE); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2153 | /* wait for cpu pipe off, pipe state */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2154 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50)) |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2155 | DRM_ERROR("failed to turn off cpu pipe\n"); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2156 | } |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2157 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2158 | /* Disable PF */ |
| 2159 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0); |
| 2160 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0); |
| 2161 | |
| 2162 | /* disable CPU FDI tx and PCH FDI rx */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2163 | reg = FDI_TX_CTL(pipe); |
| 2164 | temp = I915_READ(reg); |
| 2165 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
| 2166 | POSTING_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2167 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2168 | reg = FDI_RX_CTL(pipe); |
| 2169 | temp = I915_READ(reg); |
| 2170 | temp &= ~(0x7 << 16); |
| 2171 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
| 2172 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2173 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2174 | POSTING_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2175 | udelay(100); |
| 2176 | |
| 2177 | /* still set train pattern 1 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2178 | reg = FDI_TX_CTL(pipe); |
| 2179 | temp = I915_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2180 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2181 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2182 | I915_WRITE(reg, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2183 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2184 | reg = FDI_RX_CTL(pipe); |
| 2185 | temp = I915_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2186 | if (HAS_PCH_CPT(dev)) { |
| 2187 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2188 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 2189 | } else { |
| 2190 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2191 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2192 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2193 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
| 2194 | temp &= ~(0x07 << 16); |
| 2195 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
| 2196 | I915_WRITE(reg, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2197 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2198 | POSTING_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2199 | udelay(100); |
| 2200 | |
| 2201 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 2202 | temp = I915_READ(PCH_LVDS); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2203 | if (temp & LVDS_PORT_EN) { |
| 2204 | I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN); |
| 2205 | POSTING_READ(PCH_LVDS); |
| 2206 | udelay(100); |
| 2207 | } |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2208 | } |
| 2209 | |
| 2210 | /* disable PCH transcoder */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2211 | reg = TRANSCONF(plane); |
| 2212 | temp = I915_READ(reg); |
| 2213 | if (temp & TRANS_ENABLE) { |
| 2214 | I915_WRITE(reg, temp & ~TRANS_ENABLE); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2215 | /* wait for PCH transcoder off, transcoder state */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2216 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2217 | DRM_ERROR("failed to disable transcoder\n"); |
| 2218 | } |
| 2219 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2220 | if (HAS_PCH_CPT(dev)) { |
| 2221 | /* disable TRANS_DP_CTL */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2222 | reg = TRANS_DP_CTL(pipe); |
| 2223 | temp = I915_READ(reg); |
| 2224 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); |
| 2225 | I915_WRITE(reg, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2226 | |
| 2227 | /* disable DPLL_SEL */ |
| 2228 | temp = I915_READ(PCH_DPLL_SEL); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2229 | if (pipe == 0) |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2230 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
| 2231 | else |
| 2232 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
| 2233 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2234 | } |
| 2235 | |
| 2236 | /* disable PCH DPLL */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2237 | reg = PCH_DPLL(pipe); |
| 2238 | temp = I915_READ(reg); |
| 2239 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2240 | |
| 2241 | /* Switch from PCDclk to Rawclk */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2242 | reg = FDI_RX_CTL(pipe); |
| 2243 | temp = I915_READ(reg); |
| 2244 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2245 | |
| 2246 | /* Disable CPU FDI TX PLL */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2247 | reg = FDI_TX_CTL(pipe); |
| 2248 | temp = I915_READ(reg); |
| 2249 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
| 2250 | |
| 2251 | POSTING_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2252 | udelay(100); |
| 2253 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2254 | reg = FDI_RX_CTL(pipe); |
| 2255 | temp = I915_READ(reg); |
| 2256 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2257 | |
| 2258 | /* Wait for the clocks to turn off. */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2259 | POSTING_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2260 | udelay(100); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2261 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 2262 | intel_crtc->active = false; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2263 | intel_update_watermarks(dev); |
| 2264 | intel_update_fbc(dev); |
| 2265 | intel_clear_scanline_wait(dev); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2266 | } |
| 2267 | |
| 2268 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 2269 | { |
| 2270 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2271 | int pipe = intel_crtc->pipe; |
| 2272 | int plane = intel_crtc->plane; |
| 2273 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2274 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 2275 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 2276 | */ |
| 2277 | switch (mode) { |
| 2278 | case DRM_MODE_DPMS_ON: |
| 2279 | case DRM_MODE_DPMS_STANDBY: |
| 2280 | case DRM_MODE_DPMS_SUSPEND: |
Chris Wilson | 868dc58 | 2010-08-07 11:01:31 +0100 | [diff] [blame] | 2281 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2282 | ironlake_crtc_enable(crtc); |
Chris Wilson | 868dc58 | 2010-08-07 11:01:31 +0100 | [diff] [blame] | 2283 | break; |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 2284 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2285 | case DRM_MODE_DPMS_OFF: |
Chris Wilson | 868dc58 | 2010-08-07 11:01:31 +0100 | [diff] [blame] | 2286 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2287 | ironlake_crtc_disable(crtc); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2288 | break; |
| 2289 | } |
| 2290 | } |
| 2291 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2292 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
| 2293 | { |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2294 | if (!enable && intel_crtc->overlay) { |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 2295 | struct drm_device *dev = intel_crtc->base.dev; |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 2296 | |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 2297 | mutex_lock(&dev->struct_mutex); |
| 2298 | (void) intel_overlay_switch_off(intel_crtc->overlay, false); |
| 2299 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2300 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2301 | |
Chris Wilson | 5dcdbcb | 2010-08-12 13:50:28 +0100 | [diff] [blame] | 2302 | /* Let userspace switch the overlay on again. In most cases userspace |
| 2303 | * has to recompute where to put it anyway. |
| 2304 | */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2305 | } |
| 2306 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2307 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2308 | { |
| 2309 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2310 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2311 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2312 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2313 | int plane = intel_crtc->plane; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2314 | u32 reg, temp; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2315 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 2316 | if (intel_crtc->active) |
| 2317 | return; |
| 2318 | |
| 2319 | intel_crtc->active = true; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2320 | intel_update_watermarks(dev); |
| 2321 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2322 | /* Enable the DPLL */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2323 | reg = DPLL(pipe); |
| 2324 | temp = I915_READ(reg); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2325 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2326 | I915_WRITE(reg, temp); |
| 2327 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2328 | /* Wait for the clocks to stabilize. */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2329 | POSTING_READ(reg); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2330 | udelay(150); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2331 | |
| 2332 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); |
| 2333 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2334 | /* Wait for the clocks to stabilize. */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2335 | POSTING_READ(reg); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2336 | udelay(150); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2337 | |
| 2338 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); |
| 2339 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2340 | /* Wait for the clocks to stabilize. */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2341 | POSTING_READ(reg); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2342 | udelay(150); |
| 2343 | } |
| 2344 | |
| 2345 | /* Enable the pipe */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2346 | reg = PIPECONF(pipe); |
| 2347 | temp = I915_READ(reg); |
| 2348 | if ((temp & PIPECONF_ENABLE) == 0) |
| 2349 | I915_WRITE(reg, temp | PIPECONF_ENABLE); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2350 | |
| 2351 | /* Enable the plane */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2352 | reg = DSPCNTR(plane); |
| 2353 | temp = I915_READ(reg); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2354 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2355 | I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE); |
| 2356 | intel_flush_display_plane(dev, plane); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2357 | } |
| 2358 | |
| 2359 | intel_crtc_load_lut(crtc); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 2360 | intel_update_fbc(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2361 | |
| 2362 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
| 2363 | intel_crtc_dpms_overlay(intel_crtc, true); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2364 | intel_crtc_update_cursor(crtc, true); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2365 | } |
| 2366 | |
| 2367 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
| 2368 | { |
| 2369 | struct drm_device *dev = crtc->dev; |
| 2370 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2372 | int pipe = intel_crtc->pipe; |
| 2373 | int plane = intel_crtc->plane; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2374 | u32 reg, temp; |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2375 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 2376 | if (!intel_crtc->active) |
| 2377 | return; |
| 2378 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2379 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
| 2380 | intel_crtc_dpms_overlay(intel_crtc, false); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2381 | intel_crtc_update_cursor(crtc, false); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2382 | drm_vblank_off(dev, pipe); |
| 2383 | |
| 2384 | if (dev_priv->cfb_plane == plane && |
| 2385 | dev_priv->display.disable_fbc) |
| 2386 | dev_priv->display.disable_fbc(dev); |
| 2387 | |
| 2388 | /* Disable display plane */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2389 | reg = DSPCNTR(plane); |
| 2390 | temp = I915_READ(reg); |
| 2391 | if (temp & DISPLAY_PLANE_ENABLE) { |
| 2392 | I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2393 | /* Flush the plane changes */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2394 | intel_flush_display_plane(dev, plane); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2395 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2396 | /* Wait for vblank for the disable to take effect */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2397 | if (IS_GEN2(dev)) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2398 | intel_wait_for_vblank_off(dev, pipe); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2399 | } |
| 2400 | |
| 2401 | /* Don't disable pipe A or pipe A PLLs if needed */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2402 | if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2403 | goto done; |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2404 | |
| 2405 | /* Next, disable display pipes */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2406 | reg = PIPECONF(pipe); |
| 2407 | temp = I915_READ(reg); |
| 2408 | if (temp & PIPECONF_ENABLE) { |
| 2409 | I915_WRITE(reg, temp & ~PIPECONF_ENABLE); |
| 2410 | |
| 2411 | /* Wait for vblank for the disable to take effect. */ |
| 2412 | POSTING_READ(reg); |
| 2413 | intel_wait_for_vblank_off(dev, pipe); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2414 | } |
| 2415 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2416 | reg = DPLL(pipe); |
| 2417 | temp = I915_READ(reg); |
| 2418 | if (temp & DPLL_VCO_ENABLE) { |
| 2419 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2420 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2421 | /* Wait for the clocks to turn off. */ |
| 2422 | POSTING_READ(reg); |
| 2423 | udelay(150); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2424 | } |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2425 | |
| 2426 | done: |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 2427 | intel_crtc->active = false; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2428 | intel_update_fbc(dev); |
| 2429 | intel_update_watermarks(dev); |
| 2430 | intel_clear_scanline_wait(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2431 | } |
| 2432 | |
| 2433 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 2434 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2435 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 2436 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 2437 | */ |
| 2438 | switch (mode) { |
| 2439 | case DRM_MODE_DPMS_ON: |
| 2440 | case DRM_MODE_DPMS_STANDBY: |
| 2441 | case DRM_MODE_DPMS_SUSPEND: |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2442 | i9xx_crtc_enable(crtc); |
| 2443 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2444 | case DRM_MODE_DPMS_OFF: |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2445 | i9xx_crtc_disable(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2446 | break; |
| 2447 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2448 | } |
| 2449 | |
| 2450 | /** |
| 2451 | * Sets the power management mode of the pipe and plane. |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2452 | */ |
| 2453 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 2454 | { |
| 2455 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2456 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2457 | struct drm_i915_master_private *master_priv; |
| 2458 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2459 | int pipe = intel_crtc->pipe; |
| 2460 | bool enabled; |
| 2461 | |
Chris Wilson | 032d2a0 | 2010-09-06 16:17:22 +0100 | [diff] [blame] | 2462 | if (intel_crtc->dpms_mode == mode) |
| 2463 | return; |
| 2464 | |
Chris Wilson | debcadd | 2010-08-07 11:01:33 +0100 | [diff] [blame] | 2465 | intel_crtc->dpms_mode = mode; |
Chris Wilson | debcadd | 2010-08-07 11:01:33 +0100 | [diff] [blame] | 2466 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2467 | dev_priv->display.dpms(crtc, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2468 | |
| 2469 | if (!dev->primary->master) |
| 2470 | return; |
| 2471 | |
| 2472 | master_priv = dev->primary->master->driver_priv; |
| 2473 | if (!master_priv->sarea_priv) |
| 2474 | return; |
| 2475 | |
| 2476 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; |
| 2477 | |
| 2478 | switch (pipe) { |
| 2479 | case 0: |
| 2480 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
| 2481 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
| 2482 | break; |
| 2483 | case 1: |
| 2484 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
| 2485 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
| 2486 | break; |
| 2487 | default: |
| 2488 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); |
| 2489 | break; |
| 2490 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2491 | } |
| 2492 | |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 2493 | static void intel_crtc_disable(struct drm_crtc *crtc) |
| 2494 | { |
| 2495 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 2496 | struct drm_device *dev = crtc->dev; |
| 2497 | |
| 2498 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); |
| 2499 | |
| 2500 | if (crtc->fb) { |
| 2501 | mutex_lock(&dev->struct_mutex); |
| 2502 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
| 2503 | mutex_unlock(&dev->struct_mutex); |
| 2504 | } |
| 2505 | } |
| 2506 | |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 2507 | /* Prepare for a mode set. |
| 2508 | * |
| 2509 | * Note we could be a lot smarter here. We need to figure out which outputs |
| 2510 | * will be enabled, which disabled (in short, how the config will changes) |
| 2511 | * and perform the minimum necessary steps to accomplish that, e.g. updating |
| 2512 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, |
| 2513 | * panel fitting is in the proper state, etc. |
| 2514 | */ |
| 2515 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2516 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 2517 | i9xx_crtc_disable(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2518 | } |
| 2519 | |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 2520 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2521 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 2522 | i9xx_crtc_enable(crtc); |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 2523 | } |
| 2524 | |
| 2525 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) |
| 2526 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 2527 | ironlake_crtc_disable(crtc); |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 2528 | } |
| 2529 | |
| 2530 | static void ironlake_crtc_commit(struct drm_crtc *crtc) |
| 2531 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 2532 | ironlake_crtc_enable(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2533 | } |
| 2534 | |
| 2535 | void intel_encoder_prepare (struct drm_encoder *encoder) |
| 2536 | { |
| 2537 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 2538 | /* lvds has its own version of prepare see intel_lvds_prepare */ |
| 2539 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); |
| 2540 | } |
| 2541 | |
| 2542 | void intel_encoder_commit (struct drm_encoder *encoder) |
| 2543 | { |
| 2544 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 2545 | /* lvds has its own version of commit see intel_lvds_commit */ |
| 2546 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
| 2547 | } |
| 2548 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2549 | void intel_encoder_destroy(struct drm_encoder *encoder) |
| 2550 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2551 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2552 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2553 | drm_encoder_cleanup(encoder); |
| 2554 | kfree(intel_encoder); |
| 2555 | } |
| 2556 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2557 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
| 2558 | struct drm_display_mode *mode, |
| 2559 | struct drm_display_mode *adjusted_mode) |
| 2560 | { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2561 | struct drm_device *dev = crtc->dev; |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 2562 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 2563 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2564 | /* FDI link clock is fixed at 2.7G */ |
Jesse Barnes | 2377b74 | 2010-07-07 14:06:43 -0700 | [diff] [blame] | 2565 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
| 2566 | return false; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2567 | } |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 2568 | |
| 2569 | /* XXX some encoders set the crtcinfo, others don't. |
| 2570 | * Obviously we need some form of conflict resolution here... |
| 2571 | */ |
| 2572 | if (adjusted_mode->crtc_htotal == 0) |
| 2573 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| 2574 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2575 | return true; |
| 2576 | } |
| 2577 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2578 | static int i945_get_display_clock_speed(struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2579 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2580 | return 400000; |
| 2581 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2582 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2583 | static int i915_get_display_clock_speed(struct drm_device *dev) |
| 2584 | { |
| 2585 | return 333000; |
| 2586 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2587 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2588 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
| 2589 | { |
| 2590 | return 200000; |
| 2591 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2592 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2593 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
| 2594 | { |
| 2595 | u16 gcfgc = 0; |
| 2596 | |
| 2597 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 2598 | |
| 2599 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2600 | return 133000; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2601 | else { |
| 2602 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 2603 | case GC_DISPLAY_CLOCK_333_MHZ: |
| 2604 | return 333000; |
| 2605 | default: |
| 2606 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 2607 | return 190000; |
| 2608 | } |
| 2609 | } |
| 2610 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2611 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2612 | static int i865_get_display_clock_speed(struct drm_device *dev) |
| 2613 | { |
| 2614 | return 266000; |
| 2615 | } |
| 2616 | |
| 2617 | static int i855_get_display_clock_speed(struct drm_device *dev) |
| 2618 | { |
| 2619 | u16 hpllcc = 0; |
| 2620 | /* Assume that the hardware is in the high speed state. This |
| 2621 | * should be the default. |
| 2622 | */ |
| 2623 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
| 2624 | case GC_CLOCK_133_200: |
| 2625 | case GC_CLOCK_100_200: |
| 2626 | return 200000; |
| 2627 | case GC_CLOCK_166_250: |
| 2628 | return 250000; |
| 2629 | case GC_CLOCK_100_133: |
| 2630 | return 133000; |
| 2631 | } |
| 2632 | |
| 2633 | /* Shouldn't happen */ |
| 2634 | return 0; |
| 2635 | } |
| 2636 | |
| 2637 | static int i830_get_display_clock_speed(struct drm_device *dev) |
| 2638 | { |
| 2639 | return 133000; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2640 | } |
| 2641 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2642 | struct fdi_m_n { |
| 2643 | u32 tu; |
| 2644 | u32 gmch_m; |
| 2645 | u32 gmch_n; |
| 2646 | u32 link_m; |
| 2647 | u32 link_n; |
| 2648 | }; |
| 2649 | |
| 2650 | static void |
| 2651 | fdi_reduce_ratio(u32 *num, u32 *den) |
| 2652 | { |
| 2653 | while (*num > 0xffffff || *den > 0xffffff) { |
| 2654 | *num >>= 1; |
| 2655 | *den >>= 1; |
| 2656 | } |
| 2657 | } |
| 2658 | |
| 2659 | #define DATA_N 0x800000 |
| 2660 | #define LINK_N 0x80000 |
| 2661 | |
| 2662 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2663 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
| 2664 | int link_clock, struct fdi_m_n *m_n) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2665 | { |
| 2666 | u64 temp; |
| 2667 | |
| 2668 | m_n->tu = 64; /* default size */ |
| 2669 | |
| 2670 | temp = (u64) DATA_N * pixel_clock; |
| 2671 | temp = div_u64(temp, link_clock); |
Zhenyu Wang | 58a2747 | 2009-09-25 08:01:28 +0000 | [diff] [blame] | 2672 | m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes); |
| 2673 | m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */ |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2674 | m_n->gmch_n = DATA_N; |
| 2675 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
| 2676 | |
| 2677 | temp = (u64) LINK_N * pixel_clock; |
| 2678 | m_n->link_m = div_u64(temp, link_clock); |
| 2679 | m_n->link_n = LINK_N; |
| 2680 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
| 2681 | } |
| 2682 | |
| 2683 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2684 | struct intel_watermark_params { |
| 2685 | unsigned long fifo_size; |
| 2686 | unsigned long max_wm; |
| 2687 | unsigned long default_wm; |
| 2688 | unsigned long guard_size; |
| 2689 | unsigned long cacheline_size; |
| 2690 | }; |
| 2691 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2692 | /* Pineview has different values for various configs */ |
| 2693 | static struct intel_watermark_params pineview_display_wm = { |
| 2694 | PINEVIEW_DISPLAY_FIFO, |
| 2695 | PINEVIEW_MAX_WM, |
| 2696 | PINEVIEW_DFT_WM, |
| 2697 | PINEVIEW_GUARD_WM, |
| 2698 | PINEVIEW_FIFO_LINE_SIZE |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2699 | }; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2700 | static struct intel_watermark_params pineview_display_hplloff_wm = { |
| 2701 | PINEVIEW_DISPLAY_FIFO, |
| 2702 | PINEVIEW_MAX_WM, |
| 2703 | PINEVIEW_DFT_HPLLOFF_WM, |
| 2704 | PINEVIEW_GUARD_WM, |
| 2705 | PINEVIEW_FIFO_LINE_SIZE |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2706 | }; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2707 | static struct intel_watermark_params pineview_cursor_wm = { |
| 2708 | PINEVIEW_CURSOR_FIFO, |
| 2709 | PINEVIEW_CURSOR_MAX_WM, |
| 2710 | PINEVIEW_CURSOR_DFT_WM, |
| 2711 | PINEVIEW_CURSOR_GUARD_WM, |
| 2712 | PINEVIEW_FIFO_LINE_SIZE, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2713 | }; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2714 | static struct intel_watermark_params pineview_cursor_hplloff_wm = { |
| 2715 | PINEVIEW_CURSOR_FIFO, |
| 2716 | PINEVIEW_CURSOR_MAX_WM, |
| 2717 | PINEVIEW_CURSOR_DFT_WM, |
| 2718 | PINEVIEW_CURSOR_GUARD_WM, |
| 2719 | PINEVIEW_FIFO_LINE_SIZE |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2720 | }; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2721 | static struct intel_watermark_params g4x_wm_info = { |
| 2722 | G4X_FIFO_SIZE, |
| 2723 | G4X_MAX_WM, |
| 2724 | G4X_MAX_WM, |
| 2725 | 2, |
| 2726 | G4X_FIFO_LINE_SIZE, |
| 2727 | }; |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 2728 | static struct intel_watermark_params g4x_cursor_wm_info = { |
| 2729 | I965_CURSOR_FIFO, |
| 2730 | I965_CURSOR_MAX_WM, |
| 2731 | I965_CURSOR_DFT_WM, |
| 2732 | 2, |
| 2733 | G4X_FIFO_LINE_SIZE, |
| 2734 | }; |
| 2735 | static struct intel_watermark_params i965_cursor_wm_info = { |
| 2736 | I965_CURSOR_FIFO, |
| 2737 | I965_CURSOR_MAX_WM, |
| 2738 | I965_CURSOR_DFT_WM, |
| 2739 | 2, |
| 2740 | I915_FIFO_LINE_SIZE, |
| 2741 | }; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2742 | static struct intel_watermark_params i945_wm_info = { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2743 | I945_FIFO_SIZE, |
| 2744 | I915_MAX_WM, |
| 2745 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2746 | 2, |
| 2747 | I915_FIFO_LINE_SIZE |
| 2748 | }; |
| 2749 | static struct intel_watermark_params i915_wm_info = { |
| 2750 | I915_FIFO_SIZE, |
| 2751 | I915_MAX_WM, |
| 2752 | 1, |
| 2753 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2754 | I915_FIFO_LINE_SIZE |
| 2755 | }; |
| 2756 | static struct intel_watermark_params i855_wm_info = { |
| 2757 | I855GM_FIFO_SIZE, |
| 2758 | I915_MAX_WM, |
| 2759 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2760 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2761 | I830_FIFO_LINE_SIZE |
| 2762 | }; |
| 2763 | static struct intel_watermark_params i830_wm_info = { |
| 2764 | I830_FIFO_SIZE, |
| 2765 | I915_MAX_WM, |
| 2766 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2767 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2768 | I830_FIFO_LINE_SIZE |
| 2769 | }; |
| 2770 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 2771 | static struct intel_watermark_params ironlake_display_wm_info = { |
| 2772 | ILK_DISPLAY_FIFO, |
| 2773 | ILK_DISPLAY_MAXWM, |
| 2774 | ILK_DISPLAY_DFTWM, |
| 2775 | 2, |
| 2776 | ILK_FIFO_LINE_SIZE |
| 2777 | }; |
| 2778 | |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 2779 | static struct intel_watermark_params ironlake_cursor_wm_info = { |
| 2780 | ILK_CURSOR_FIFO, |
| 2781 | ILK_CURSOR_MAXWM, |
| 2782 | ILK_CURSOR_DFTWM, |
| 2783 | 2, |
| 2784 | ILK_FIFO_LINE_SIZE |
| 2785 | }; |
| 2786 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 2787 | static struct intel_watermark_params ironlake_display_srwm_info = { |
| 2788 | ILK_DISPLAY_SR_FIFO, |
| 2789 | ILK_DISPLAY_MAX_SRWM, |
| 2790 | ILK_DISPLAY_DFT_SRWM, |
| 2791 | 2, |
| 2792 | ILK_FIFO_LINE_SIZE |
| 2793 | }; |
| 2794 | |
| 2795 | static struct intel_watermark_params ironlake_cursor_srwm_info = { |
| 2796 | ILK_CURSOR_SR_FIFO, |
| 2797 | ILK_CURSOR_MAX_SRWM, |
| 2798 | ILK_CURSOR_DFT_SRWM, |
| 2799 | 2, |
| 2800 | ILK_FIFO_LINE_SIZE |
| 2801 | }; |
| 2802 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2803 | /** |
| 2804 | * intel_calculate_wm - calculate watermark level |
| 2805 | * @clock_in_khz: pixel clock |
| 2806 | * @wm: chip FIFO params |
| 2807 | * @pixel_size: display pixel size |
| 2808 | * @latency_ns: memory latency for the platform |
| 2809 | * |
| 2810 | * Calculate the watermark level (the level at which the display plane will |
| 2811 | * start fetching from memory again). Each chip has a different display |
| 2812 | * FIFO size and allocation, so the caller needs to figure that out and pass |
| 2813 | * in the correct intel_watermark_params structure. |
| 2814 | * |
| 2815 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
| 2816 | * on the pixel size. When it reaches the watermark level, it'll start |
| 2817 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
| 2818 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
| 2819 | * will occur, and a display engine hang could result. |
| 2820 | */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2821 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
| 2822 | struct intel_watermark_params *wm, |
| 2823 | int pixel_size, |
| 2824 | unsigned long latency_ns) |
| 2825 | { |
Jesse Barnes | 390c4dd | 2009-07-16 13:01:01 -0700 | [diff] [blame] | 2826 | long entries_required, wm_size; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2827 | |
Jesse Barnes | d660467 | 2009-09-11 12:25:56 -0700 | [diff] [blame] | 2828 | /* |
| 2829 | * Note: we need to make sure we don't overflow for various clock & |
| 2830 | * latency values. |
| 2831 | * clocks go from a few thousand to several hundred thousand. |
| 2832 | * latency is usually a few thousand |
| 2833 | */ |
| 2834 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
| 2835 | 1000; |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 2836 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2837 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2838 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2839 | |
| 2840 | wm_size = wm->fifo_size - (entries_required + wm->guard_size); |
| 2841 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2842 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2843 | |
Jesse Barnes | 390c4dd | 2009-07-16 13:01:01 -0700 | [diff] [blame] | 2844 | /* Don't promote wm_size to unsigned... */ |
| 2845 | if (wm_size > (long)wm->max_wm) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2846 | wm_size = wm->max_wm; |
Chris Wilson | c3add4b | 2010-09-08 09:14:08 +0100 | [diff] [blame] | 2847 | if (wm_size <= 0) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2848 | wm_size = wm->default_wm; |
| 2849 | return wm_size; |
| 2850 | } |
| 2851 | |
| 2852 | struct cxsr_latency { |
| 2853 | int is_desktop; |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2854 | int is_ddr3; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2855 | unsigned long fsb_freq; |
| 2856 | unsigned long mem_freq; |
| 2857 | unsigned long display_sr; |
| 2858 | unsigned long display_hpll_disable; |
| 2859 | unsigned long cursor_sr; |
| 2860 | unsigned long cursor_hpll_disable; |
| 2861 | }; |
| 2862 | |
Chris Wilson | 403c89f | 2010-08-04 15:25:31 +0100 | [diff] [blame] | 2863 | static const struct cxsr_latency cxsr_latency_table[] = { |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2864 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
| 2865 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
| 2866 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
| 2867 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
| 2868 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2869 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2870 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
| 2871 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
| 2872 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
| 2873 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
| 2874 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2875 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2876 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
| 2877 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
| 2878 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
| 2879 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
| 2880 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2881 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2882 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
| 2883 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
| 2884 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
| 2885 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
| 2886 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2887 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2888 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
| 2889 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
| 2890 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
| 2891 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
| 2892 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2893 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2894 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
| 2895 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
| 2896 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
| 2897 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
| 2898 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2899 | }; |
| 2900 | |
Chris Wilson | 403c89f | 2010-08-04 15:25:31 +0100 | [diff] [blame] | 2901 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
| 2902 | int is_ddr3, |
| 2903 | int fsb, |
| 2904 | int mem) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2905 | { |
Chris Wilson | 403c89f | 2010-08-04 15:25:31 +0100 | [diff] [blame] | 2906 | const struct cxsr_latency *latency; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2907 | int i; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2908 | |
| 2909 | if (fsb == 0 || mem == 0) |
| 2910 | return NULL; |
| 2911 | |
| 2912 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
| 2913 | latency = &cxsr_latency_table[i]; |
| 2914 | if (is_desktop == latency->is_desktop && |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2915 | is_ddr3 == latency->is_ddr3 && |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 2916 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
| 2917 | return latency; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2918 | } |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 2919 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2920 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 2921 | |
| 2922 | return NULL; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2923 | } |
| 2924 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2925 | static void pineview_disable_cxsr(struct drm_device *dev) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2926 | { |
| 2927 | struct drm_i915_private *dev_priv = dev->dev_private; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2928 | |
| 2929 | /* deactivate cxsr */ |
Chris Wilson | 3e33d94 | 2010-08-04 11:17:25 +0100 | [diff] [blame] | 2930 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2931 | } |
| 2932 | |
Jesse Barnes | bcc24fb | 2009-08-31 10:24:31 -0700 | [diff] [blame] | 2933 | /* |
| 2934 | * Latency for FIFO fetches is dependent on several factors: |
| 2935 | * - memory configuration (speed, channels) |
| 2936 | * - chipset |
| 2937 | * - current MCH state |
| 2938 | * It can be fairly high in some situations, so here we assume a fairly |
| 2939 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
| 2940 | * set this value too high, the FIFO will fetch frequently to stay full) |
| 2941 | * and power consumption (set it too low to save power and we might see |
| 2942 | * FIFO underruns and display "flicker"). |
| 2943 | * |
| 2944 | * A value of 5us seems to be a good balance; safe for very low end |
| 2945 | * platforms but not overly aggressive on lower latency configs. |
| 2946 | */ |
Tobias Klauser | 69e302a | 2009-12-23 14:14:34 +0100 | [diff] [blame] | 2947 | static const int latency_ns = 5000; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2948 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2949 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2950 | { |
| 2951 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2952 | uint32_t dsparb = I915_READ(DSPARB); |
| 2953 | int size; |
| 2954 | |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 2955 | size = dsparb & 0x7f; |
| 2956 | if (plane) |
| 2957 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2958 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2959 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2960 | plane ? "B" : "A", size); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2961 | |
| 2962 | return size; |
| 2963 | } |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2964 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2965 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
| 2966 | { |
| 2967 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2968 | uint32_t dsparb = I915_READ(DSPARB); |
| 2969 | int size; |
| 2970 | |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 2971 | size = dsparb & 0x1ff; |
| 2972 | if (plane) |
| 2973 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2974 | size >>= 1; /* Convert to cachelines */ |
| 2975 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2976 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2977 | plane ? "B" : "A", size); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2978 | |
| 2979 | return size; |
| 2980 | } |
| 2981 | |
| 2982 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
| 2983 | { |
| 2984 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2985 | uint32_t dsparb = I915_READ(DSPARB); |
| 2986 | int size; |
| 2987 | |
| 2988 | size = dsparb & 0x7f; |
| 2989 | size >>= 2; /* Convert to cachelines */ |
| 2990 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2991 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2992 | plane ? "B" : "A", |
| 2993 | size); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2994 | |
| 2995 | return size; |
| 2996 | } |
| 2997 | |
| 2998 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
| 2999 | { |
| 3000 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3001 | uint32_t dsparb = I915_READ(DSPARB); |
| 3002 | int size; |
| 3003 | |
| 3004 | size = dsparb & 0x7f; |
| 3005 | size >>= 1; /* Convert to cachelines */ |
| 3006 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3007 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3008 | plane ? "B" : "A", size); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3009 | |
| 3010 | return size; |
| 3011 | } |
| 3012 | |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3013 | static void pineview_update_wm(struct drm_device *dev, int planea_clock, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3014 | int planeb_clock, int sr_hdisplay, int unused, |
| 3015 | int pixel_size) |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3016 | { |
| 3017 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 403c89f | 2010-08-04 15:25:31 +0100 | [diff] [blame] | 3018 | const struct cxsr_latency *latency; |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3019 | u32 reg; |
| 3020 | unsigned long wm; |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3021 | int sr_clock; |
| 3022 | |
Chris Wilson | 403c89f | 2010-08-04 15:25:31 +0100 | [diff] [blame] | 3023 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 3024 | dev_priv->fsb_freq, dev_priv->mem_freq); |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3025 | if (!latency) { |
| 3026 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 3027 | pineview_disable_cxsr(dev); |
| 3028 | return; |
| 3029 | } |
| 3030 | |
| 3031 | if (!planea_clock || !planeb_clock) { |
| 3032 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
| 3033 | |
| 3034 | /* Display SR */ |
| 3035 | wm = intel_calculate_wm(sr_clock, &pineview_display_wm, |
| 3036 | pixel_size, latency->display_sr); |
| 3037 | reg = I915_READ(DSPFW1); |
| 3038 | reg &= ~DSPFW_SR_MASK; |
| 3039 | reg |= wm << DSPFW_SR_SHIFT; |
| 3040 | I915_WRITE(DSPFW1, reg); |
| 3041 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
| 3042 | |
| 3043 | /* cursor SR */ |
| 3044 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm, |
| 3045 | pixel_size, latency->cursor_sr); |
| 3046 | reg = I915_READ(DSPFW3); |
| 3047 | reg &= ~DSPFW_CURSOR_SR_MASK; |
| 3048 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
| 3049 | I915_WRITE(DSPFW3, reg); |
| 3050 | |
| 3051 | /* Display HPLL off SR */ |
| 3052 | wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm, |
| 3053 | pixel_size, latency->display_hpll_disable); |
| 3054 | reg = I915_READ(DSPFW3); |
| 3055 | reg &= ~DSPFW_HPLL_SR_MASK; |
| 3056 | reg |= wm & DSPFW_HPLL_SR_MASK; |
| 3057 | I915_WRITE(DSPFW3, reg); |
| 3058 | |
| 3059 | /* cursor HPLL off SR */ |
| 3060 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm, |
| 3061 | pixel_size, latency->cursor_hpll_disable); |
| 3062 | reg = I915_READ(DSPFW3); |
| 3063 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
| 3064 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
| 3065 | I915_WRITE(DSPFW3, reg); |
| 3066 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
| 3067 | |
| 3068 | /* activate cxsr */ |
Chris Wilson | 3e33d94 | 2010-08-04 11:17:25 +0100 | [diff] [blame] | 3069 | I915_WRITE(DSPFW3, |
| 3070 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 3071 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
| 3072 | } else { |
| 3073 | pineview_disable_cxsr(dev); |
| 3074 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); |
| 3075 | } |
| 3076 | } |
| 3077 | |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3078 | static void g4x_update_wm(struct drm_device *dev, int planea_clock, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3079 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
| 3080 | int pixel_size) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3081 | { |
| 3082 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3083 | int total_size, cacheline_size; |
| 3084 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr; |
| 3085 | struct intel_watermark_params planea_params, planeb_params; |
| 3086 | unsigned long line_time_us; |
| 3087 | int sr_clock, sr_entries = 0, entries_required; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3088 | |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3089 | /* Create copies of the base settings for each pipe */ |
| 3090 | planea_params = planeb_params = g4x_wm_info; |
| 3091 | |
| 3092 | /* Grab a couple of global values before we overwrite them */ |
| 3093 | total_size = planea_params.fifo_size; |
| 3094 | cacheline_size = planea_params.cacheline_size; |
| 3095 | |
| 3096 | /* |
| 3097 | * Note: we need to make sure we don't overflow for various clock & |
| 3098 | * latency values. |
| 3099 | * clocks go from a few thousand to several hundred thousand. |
| 3100 | * latency is usually a few thousand |
| 3101 | */ |
| 3102 | entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) / |
| 3103 | 1000; |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 3104 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3105 | planea_wm = entries_required + planea_params.guard_size; |
| 3106 | |
| 3107 | entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) / |
| 3108 | 1000; |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 3109 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3110 | planeb_wm = entries_required + planeb_params.guard_size; |
| 3111 | |
| 3112 | cursora_wm = cursorb_wm = 16; |
| 3113 | cursor_sr = 32; |
| 3114 | |
| 3115 | DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
| 3116 | |
| 3117 | /* Calc sr entries for one plane configs */ |
| 3118 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { |
| 3119 | /* self-refresh has much higher latency */ |
Tobias Klauser | 69e302a | 2009-12-23 14:14:34 +0100 | [diff] [blame] | 3120 | static const int sr_latency_ns = 12000; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3121 | |
| 3122 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3123 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3124 | |
| 3125 | /* Use ns/us then divide to preserve precision */ |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3126 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3127 | pixel_size * sr_hdisplay; |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 3128 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3129 | |
| 3130 | entries_required = (((sr_latency_ns / line_time_us) + |
| 3131 | 1000) / 1000) * pixel_size * 64; |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 3132 | entries_required = DIV_ROUND_UP(entries_required, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3133 | g4x_cursor_wm_info.cacheline_size); |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3134 | cursor_sr = entries_required + g4x_cursor_wm_info.guard_size; |
| 3135 | |
| 3136 | if (cursor_sr > g4x_cursor_wm_info.max_wm) |
| 3137 | cursor_sr = g4x_cursor_wm_info.max_wm; |
| 3138 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 3139 | "cursor %d\n", sr_entries, cursor_sr); |
| 3140 | |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3141 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
David John | 33c5fd1 | 2010-01-27 15:19:08 +0530 | [diff] [blame] | 3142 | } else { |
| 3143 | /* Turn off self refresh if both pipes are enabled */ |
| 3144 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3145 | & ~FW_BLC_SELF_EN); |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3146 | } |
| 3147 | |
| 3148 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", |
| 3149 | planea_wm, planeb_wm, sr_entries); |
| 3150 | |
| 3151 | planea_wm &= 0x3f; |
| 3152 | planeb_wm &= 0x3f; |
| 3153 | |
| 3154 | I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) | |
| 3155 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 3156 | (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm); |
| 3157 | I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | |
| 3158 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 3159 | /* HPLL off in SR has some issues on G4x... disable it */ |
| 3160 | I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | |
| 3161 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3162 | } |
| 3163 | |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3164 | static void i965_update_wm(struct drm_device *dev, int planea_clock, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3165 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
| 3166 | int pixel_size) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3167 | { |
| 3168 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3169 | unsigned long line_time_us; |
| 3170 | int sr_clock, sr_entries, srwm = 1; |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3171 | int cursor_sr = 16; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3172 | |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3173 | /* Calc sr entries for one plane configs */ |
| 3174 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { |
| 3175 | /* self-refresh has much higher latency */ |
Tobias Klauser | 69e302a | 2009-12-23 14:14:34 +0100 | [diff] [blame] | 3176 | static const int sr_latency_ns = 12000; |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3177 | |
| 3178 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3179 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3180 | |
| 3181 | /* Use ns/us then divide to preserve precision */ |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3182 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3183 | pixel_size * sr_hdisplay; |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 3184 | sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE); |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3185 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
Zhao Yakui | 1b07e04 | 2010-06-12 14:32:24 +0800 | [diff] [blame] | 3186 | srwm = I965_FIFO_SIZE - sr_entries; |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3187 | if (srwm < 0) |
| 3188 | srwm = 1; |
Zhao Yakui | 1b07e04 | 2010-06-12 14:32:24 +0800 | [diff] [blame] | 3189 | srwm &= 0x1ff; |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3190 | |
| 3191 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3192 | pixel_size * 64; |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 3193 | sr_entries = DIV_ROUND_UP(sr_entries, |
| 3194 | i965_cursor_wm_info.cacheline_size); |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3195 | cursor_sr = i965_cursor_wm_info.fifo_size - |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3196 | (sr_entries + i965_cursor_wm_info.guard_size); |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3197 | |
| 3198 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
| 3199 | cursor_sr = i965_cursor_wm_info.max_wm; |
| 3200 | |
| 3201 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 3202 | "cursor %d\n", srwm, cursor_sr); |
| 3203 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3204 | if (IS_CRESTLINE(dev)) |
Jesse Barnes | adcdbc6 | 2010-06-30 13:49:37 -0700 | [diff] [blame] | 3205 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
David John | 33c5fd1 | 2010-01-27 15:19:08 +0530 | [diff] [blame] | 3206 | } else { |
| 3207 | /* Turn off self refresh if both pipes are enabled */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3208 | if (IS_CRESTLINE(dev)) |
Jesse Barnes | adcdbc6 | 2010-06-30 13:49:37 -0700 | [diff] [blame] | 3209 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
| 3210 | & ~FW_BLC_SELF_EN); |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3211 | } |
| 3212 | |
| 3213 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
| 3214 | srwm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3215 | |
| 3216 | /* 965 has limitations... */ |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3217 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) | |
| 3218 | (8 << 0)); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3219 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3220 | /* update cursor SR watermark */ |
| 3221 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3222 | } |
| 3223 | |
| 3224 | static void i9xx_update_wm(struct drm_device *dev, int planea_clock, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3225 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
| 3226 | int pixel_size) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3227 | { |
| 3228 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3229 | uint32_t fwater_lo; |
| 3230 | uint32_t fwater_hi; |
| 3231 | int total_size, cacheline_size, cwm, srwm = 1; |
| 3232 | int planea_wm, planeb_wm; |
| 3233 | struct intel_watermark_params planea_params, planeb_params; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3234 | unsigned long line_time_us; |
| 3235 | int sr_clock, sr_entries = 0; |
| 3236 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3237 | /* Create copies of the base settings for each pipe */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3238 | if (IS_CRESTLINE(dev) || IS_I945GM(dev)) |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3239 | planea_params = planeb_params = i945_wm_info; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3240 | else if (!IS_GEN2(dev)) |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3241 | planea_params = planeb_params = i915_wm_info; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3242 | else |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3243 | planea_params = planeb_params = i855_wm_info; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3244 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3245 | /* Grab a couple of global values before we overwrite them */ |
| 3246 | total_size = planea_params.fifo_size; |
| 3247 | cacheline_size = planea_params.cacheline_size; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3248 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3249 | /* Update per-plane FIFO sizes */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3250 | planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
| 3251 | planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3252 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3253 | planea_wm = intel_calculate_wm(planea_clock, &planea_params, |
| 3254 | pixel_size, latency_ns); |
| 3255 | planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, |
| 3256 | pixel_size, latency_ns); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3257 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3258 | |
| 3259 | /* |
| 3260 | * Overlay gets an aggressive default since video jitter is bad. |
| 3261 | */ |
| 3262 | cwm = 2; |
| 3263 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3264 | /* Calc sr entries for one plane configs */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3265 | if (HAS_FW_BLC(dev) && sr_hdisplay && |
| 3266 | (!planea_clock || !planeb_clock)) { |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3267 | /* self-refresh has much higher latency */ |
Tobias Klauser | 69e302a | 2009-12-23 14:14:34 +0100 | [diff] [blame] | 3268 | static const int sr_latency_ns = 6000; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3269 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3270 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3271 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3272 | |
| 3273 | /* Use ns/us then divide to preserve precision */ |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3274 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3275 | pixel_size * sr_hdisplay; |
Chris Wilson | 8de9b31 | 2010-07-19 19:59:52 +0100 | [diff] [blame] | 3276 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3277 | DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3278 | srwm = total_size - sr_entries; |
| 3279 | if (srwm < 0) |
| 3280 | srwm = 1; |
Li Peng | ee980b8 | 2010-01-27 19:01:11 +0800 | [diff] [blame] | 3281 | |
| 3282 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 3283 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
| 3284 | else if (IS_I915GM(dev)) { |
| 3285 | /* 915M has a smaller SRWM field */ |
| 3286 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
| 3287 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); |
| 3288 | } |
David John | 33c5fd1 | 2010-01-27 15:19:08 +0530 | [diff] [blame] | 3289 | } else { |
| 3290 | /* Turn off self refresh if both pipes are enabled */ |
Li Peng | ee980b8 | 2010-01-27 19:01:11 +0800 | [diff] [blame] | 3291 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
| 3292 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
| 3293 | & ~FW_BLC_SELF_EN); |
| 3294 | } else if (IS_I915GM(dev)) { |
| 3295 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); |
| 3296 | } |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3297 | } |
| 3298 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3299 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3300 | planea_wm, planeb_wm, cwm, srwm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3301 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3302 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
| 3303 | fwater_hi = (cwm & 0x1f); |
| 3304 | |
| 3305 | /* Set request length to 8 cachelines per fetch */ |
| 3306 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
| 3307 | fwater_hi = fwater_hi | (1 << 8); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3308 | |
| 3309 | I915_WRITE(FW_BLC, fwater_lo); |
| 3310 | I915_WRITE(FW_BLC2, fwater_hi); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3311 | } |
| 3312 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3313 | static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3314 | int unused2, int unused3, int pixel_size) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3315 | { |
| 3316 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | f360132 | 2009-07-22 12:54:59 -0700 | [diff] [blame] | 3317 | uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3318 | int planea_wm; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3319 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3320 | i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3321 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3322 | planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, |
| 3323 | pixel_size, latency_ns); |
Jesse Barnes | f360132 | 2009-07-22 12:54:59 -0700 | [diff] [blame] | 3324 | fwater_lo |= (3<<8) | planea_wm; |
| 3325 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3326 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3327 | |
| 3328 | I915_WRITE(FW_BLC, fwater_lo); |
| 3329 | } |
| 3330 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3331 | #define ILK_LP0_PLANE_LATENCY 700 |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 3332 | #define ILK_LP0_CURSOR_LATENCY 1300 |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3333 | |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3334 | static bool ironlake_compute_wm0(struct drm_device *dev, |
| 3335 | int pipe, |
| 3336 | int *plane_wm, |
| 3337 | int *cursor_wm) |
| 3338 | { |
| 3339 | struct drm_crtc *crtc; |
| 3340 | int htotal, hdisplay, clock, pixel_size = 0; |
| 3341 | int line_time_us, line_count, entries; |
| 3342 | |
| 3343 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
| 3344 | if (crtc->fb == NULL || !crtc->enabled) |
| 3345 | return false; |
| 3346 | |
| 3347 | htotal = crtc->mode.htotal; |
| 3348 | hdisplay = crtc->mode.hdisplay; |
| 3349 | clock = crtc->mode.clock; |
| 3350 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 3351 | |
| 3352 | /* Use the small buffer method to calculate plane watermark */ |
| 3353 | entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000; |
| 3354 | entries = DIV_ROUND_UP(entries, |
| 3355 | ironlake_display_wm_info.cacheline_size); |
| 3356 | *plane_wm = entries + ironlake_display_wm_info.guard_size; |
| 3357 | if (*plane_wm > (int)ironlake_display_wm_info.max_wm) |
| 3358 | *plane_wm = ironlake_display_wm_info.max_wm; |
| 3359 | |
| 3360 | /* Use the large buffer method to calculate cursor watermark */ |
| 3361 | line_time_us = ((htotal * 1000) / clock); |
| 3362 | line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000; |
| 3363 | entries = line_count * 64 * pixel_size; |
| 3364 | entries = DIV_ROUND_UP(entries, |
| 3365 | ironlake_cursor_wm_info.cacheline_size); |
| 3366 | *cursor_wm = entries + ironlake_cursor_wm_info.guard_size; |
| 3367 | if (*cursor_wm > ironlake_cursor_wm_info.max_wm) |
| 3368 | *cursor_wm = ironlake_cursor_wm_info.max_wm; |
| 3369 | |
| 3370 | return true; |
| 3371 | } |
| 3372 | |
| 3373 | static void ironlake_update_wm(struct drm_device *dev, |
| 3374 | int planea_clock, int planeb_clock, |
| 3375 | int sr_hdisplay, int sr_htotal, |
| 3376 | int pixel_size) |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3377 | { |
| 3378 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3379 | int plane_wm, cursor_wm, enabled; |
| 3380 | int tmp; |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 3381 | |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3382 | enabled = 0; |
| 3383 | if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) { |
| 3384 | I915_WRITE(WM0_PIPEA_ILK, |
| 3385 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
| 3386 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
| 3387 | " plane %d, " "cursor: %d\n", |
| 3388 | plane_wm, cursor_wm); |
| 3389 | enabled++; |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 3390 | } |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3391 | |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3392 | if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) { |
| 3393 | I915_WRITE(WM0_PIPEB_ILK, |
| 3394 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
| 3395 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
| 3396 | " plane %d, cursor: %d\n", |
| 3397 | plane_wm, cursor_wm); |
| 3398 | enabled++; |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3399 | } |
| 3400 | |
| 3401 | /* |
| 3402 | * Calculate and update the self-refresh watermark only when one |
| 3403 | * display plane is used. |
| 3404 | */ |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3405 | tmp = 0; |
| 3406 | if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) { |
| 3407 | unsigned long line_time_us; |
| 3408 | int small, large, plane_fbc; |
| 3409 | int sr_clock, entries; |
| 3410 | int line_count, line_size; |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3411 | /* Read the self-refresh latency. The unit is 0.5us */ |
| 3412 | int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK; |
| 3413 | |
| 3414 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3415 | line_time_us = (sr_htotal * 1000) / sr_clock; |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3416 | |
| 3417 | /* Use ns/us then divide to preserve precision */ |
| 3418 | line_count = ((ilk_sr_latency * 500) / line_time_us + 1000) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3419 | / 1000; |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3420 | line_size = sr_hdisplay * pixel_size; |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3421 | |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3422 | /* Use the minimum of the small and large buffer method for primary */ |
| 3423 | small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000; |
| 3424 | large = line_count * line_size; |
| 3425 | |
| 3426 | entries = DIV_ROUND_UP(min(small, large), |
| 3427 | ironlake_display_srwm_info.cacheline_size); |
| 3428 | |
| 3429 | plane_fbc = entries * 64; |
| 3430 | plane_fbc = DIV_ROUND_UP(plane_fbc, line_size); |
| 3431 | |
| 3432 | plane_wm = entries + ironlake_display_srwm_info.guard_size; |
| 3433 | if (plane_wm > (int)ironlake_display_srwm_info.max_wm) |
| 3434 | plane_wm = ironlake_display_srwm_info.max_wm; |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3435 | |
| 3436 | /* calculate the self-refresh watermark for display cursor */ |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3437 | entries = line_count * pixel_size * 64; |
| 3438 | entries = DIV_ROUND_UP(entries, |
| 3439 | ironlake_cursor_srwm_info.cacheline_size); |
| 3440 | |
| 3441 | cursor_wm = entries + ironlake_cursor_srwm_info.guard_size; |
| 3442 | if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm) |
| 3443 | cursor_wm = ironlake_cursor_srwm_info.max_wm; |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3444 | |
| 3445 | /* configure watermark and enable self-refresh */ |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3446 | tmp = (WM1_LP_SR_EN | |
| 3447 | (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | |
| 3448 | (plane_fbc << WM1_LP_FBC_SHIFT) | |
| 3449 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 3450 | cursor_wm); |
| 3451 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d," |
| 3452 | " cursor %d\n", plane_wm, plane_fbc, cursor_wm); |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3453 | } |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3454 | I915_WRITE(WM1_LP_ILK, tmp); |
| 3455 | /* XXX setup WM2 and WM3 */ |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3456 | } |
Chris Wilson | 4ed765f | 2010-09-11 10:46:47 +0100 | [diff] [blame] | 3457 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3458 | /** |
| 3459 | * intel_update_watermarks - update FIFO watermark values based on current modes |
| 3460 | * |
| 3461 | * Calculate watermark values for the various WM regs based on current mode |
| 3462 | * and plane configuration. |
| 3463 | * |
| 3464 | * There are several cases to deal with here: |
| 3465 | * - normal (i.e. non-self-refresh) |
| 3466 | * - self-refresh (SR) mode |
| 3467 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
| 3468 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
| 3469 | * lines), so need to account for TLB latency |
| 3470 | * |
| 3471 | * The normal calculation is: |
| 3472 | * watermark = dotclock * bytes per pixel * latency |
| 3473 | * where latency is platform & configuration dependent (we assume pessimal |
| 3474 | * values here). |
| 3475 | * |
| 3476 | * The SR calculation is: |
| 3477 | * watermark = (trunc(latency/line time)+1) * surface width * |
| 3478 | * bytes per pixel |
| 3479 | * where |
| 3480 | * line time = htotal / dotclock |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3481 | * surface width = hdisplay for normal plane and 64 for cursor |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3482 | * and latency is assumed to be high, as above. |
| 3483 | * |
| 3484 | * The final value programmed to the register should always be rounded up, |
| 3485 | * and include an extra 2 entries to account for clock crossings. |
| 3486 | * |
| 3487 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
| 3488 | * to set the non-SR watermarks to 8. |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3489 | */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3490 | static void intel_update_watermarks(struct drm_device *dev) |
| 3491 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3492 | struct drm_i915_private *dev_priv = dev->dev_private; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3493 | struct drm_crtc *crtc; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3494 | int sr_hdisplay = 0; |
| 3495 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; |
| 3496 | int enabled = 0, pixel_size = 0; |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3497 | int sr_htotal = 0; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3498 | |
Zhenyu Wang | c03342f | 2009-09-29 11:01:23 +0800 | [diff] [blame] | 3499 | if (!dev_priv->display.update_wm) |
| 3500 | return; |
| 3501 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3502 | /* Get the clock config from both planes */ |
| 3503 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
Chris Wilson | debcadd | 2010-08-07 11:01:33 +0100 | [diff] [blame] | 3504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 3505 | if (intel_crtc->active) { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3506 | enabled++; |
| 3507 | if (intel_crtc->plane == 0) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3508 | DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3509 | intel_crtc->pipe, crtc->mode.clock); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3510 | planea_clock = crtc->mode.clock; |
| 3511 | } else { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3512 | DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n", |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3513 | intel_crtc->pipe, crtc->mode.clock); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3514 | planeb_clock = crtc->mode.clock; |
| 3515 | } |
| 3516 | sr_hdisplay = crtc->mode.hdisplay; |
| 3517 | sr_clock = crtc->mode.clock; |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3518 | sr_htotal = crtc->mode.htotal; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3519 | if (crtc->fb) |
| 3520 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 3521 | else |
| 3522 | pixel_size = 4; /* by default */ |
| 3523 | } |
| 3524 | } |
| 3525 | |
| 3526 | if (enabled <= 0) |
| 3527 | return; |
| 3528 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3529 | dev_priv->display.update_wm(dev, planea_clock, planeb_clock, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3530 | sr_hdisplay, sr_htotal, pixel_size); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3531 | } |
| 3532 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 3533 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
| 3534 | struct drm_display_mode *mode, |
| 3535 | struct drm_display_mode *adjusted_mode, |
| 3536 | int x, int y, |
| 3537 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3538 | { |
| 3539 | struct drm_device *dev = crtc->dev; |
| 3540 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3541 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3542 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 3543 | int plane = intel_crtc->plane; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3544 | u32 fp_reg, dpll_reg; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 3545 | int refclk, num_connectors = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3546 | intel_clock_t clock, reduced_clock; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3547 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3548 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3549 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
Chris Wilson | 8e647a2 | 2010-08-22 10:54:23 +0100 | [diff] [blame] | 3550 | struct intel_encoder *has_edp_encoder = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3551 | struct drm_mode_config *mode_config = &dev->mode_config; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3552 | struct intel_encoder *encoder; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 3553 | const intel_limit_t *limit; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 3554 | int ret; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3555 | struct fdi_m_n m_n = {0}; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3556 | u32 reg, temp; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3557 | int target_clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3558 | |
| 3559 | drm_vblank_pre_modeset(dev, pipe); |
| 3560 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3561 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
| 3562 | if (encoder->base.crtc != crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3563 | continue; |
| 3564 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3565 | switch (encoder->type) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3566 | case INTEL_OUTPUT_LVDS: |
| 3567 | is_lvds = true; |
| 3568 | break; |
| 3569 | case INTEL_OUTPUT_SDVO: |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 3570 | case INTEL_OUTPUT_HDMI: |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3571 | is_sdvo = true; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3572 | if (encoder->needs_tv_clock) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 3573 | is_tv = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3574 | break; |
| 3575 | case INTEL_OUTPUT_DVO: |
| 3576 | is_dvo = true; |
| 3577 | break; |
| 3578 | case INTEL_OUTPUT_TVOUT: |
| 3579 | is_tv = true; |
| 3580 | break; |
| 3581 | case INTEL_OUTPUT_ANALOG: |
| 3582 | is_crt = true; |
| 3583 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3584 | case INTEL_OUTPUT_DISPLAYPORT: |
| 3585 | is_dp = true; |
| 3586 | break; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3587 | case INTEL_OUTPUT_EDP: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3588 | has_edp_encoder = encoder; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3589 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3590 | } |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3591 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 3592 | num_connectors++; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3593 | } |
| 3594 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 3595 | if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) { |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3596 | refclk = dev_priv->lvds_ssc_freq * 1000; |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3597 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3598 | refclk / 1000); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3599 | } else if (!IS_GEN2(dev)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3600 | refclk = 96000; |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3601 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3602 | refclk = 120000; /* 120Mhz refclk */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3603 | } else { |
| 3604 | refclk = 48000; |
| 3605 | } |
| 3606 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 3607 | /* |
| 3608 | * Returns a set of divisors for the desired target clock with the given |
| 3609 | * refclk, or FALSE. The returned values represent the clock equation: |
| 3610 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 3611 | */ |
| 3612 | limit = intel_limit(crtc); |
| 3613 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3614 | if (!ok) { |
| 3615 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
Chris Wilson | 1f803ee | 2009-06-06 09:45:59 +0100 | [diff] [blame] | 3616 | drm_vblank_post_modeset(dev, pipe); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 3617 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3618 | } |
| 3619 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 3620 | /* Ensure that the cursor is valid for the new mode before changing... */ |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 3621 | intel_crtc_update_cursor(crtc, true); |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 3622 | |
Zhao Yakui | ddc9003 | 2010-01-06 22:05:56 +0800 | [diff] [blame] | 3623 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
| 3624 | has_reduced_clock = limit->find_pll(limit, crtc, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3625 | dev_priv->lvds_downclock, |
| 3626 | refclk, |
| 3627 | &reduced_clock); |
Zhao Yakui | 18f9ed1 | 2009-11-20 03:24:16 +0000 | [diff] [blame] | 3628 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
| 3629 | /* |
| 3630 | * If the different P is found, it means that we can't |
| 3631 | * switch the display clock by using the FP0/FP1. |
| 3632 | * In such case we will disable the LVDS downclock |
| 3633 | * feature. |
| 3634 | */ |
| 3635 | DRM_DEBUG_KMS("Different P is found for " |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3636 | "LVDS clock/downclock\n"); |
Zhao Yakui | 18f9ed1 | 2009-11-20 03:24:16 +0000 | [diff] [blame] | 3637 | has_reduced_clock = 0; |
| 3638 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3639 | } |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 3640 | /* SDVO TV has fixed PLL values depend on its clock range, |
| 3641 | this mirrors vbios setting. */ |
| 3642 | if (is_sdvo && is_tv) { |
| 3643 | if (adjusted_mode->clock >= 100000 |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3644 | && adjusted_mode->clock < 140500) { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 3645 | clock.p1 = 2; |
| 3646 | clock.p2 = 10; |
| 3647 | clock.n = 3; |
| 3648 | clock.m1 = 16; |
| 3649 | clock.m2 = 8; |
| 3650 | } else if (adjusted_mode->clock >= 140500 |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3651 | && adjusted_mode->clock <= 200000) { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 3652 | clock.p1 = 1; |
| 3653 | clock.p2 = 10; |
| 3654 | clock.n = 6; |
| 3655 | clock.m1 = 12; |
| 3656 | clock.m2 = 8; |
| 3657 | } |
| 3658 | } |
| 3659 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3660 | /* FDI link */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3661 | if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 3662 | int lane = 0, link_bw, bpp; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3663 | /* eDP doesn't require FDI link, so just set DP M/N |
| 3664 | according to current link config */ |
Chris Wilson | 8e647a2 | 2010-08-22 10:54:23 +0100 | [diff] [blame] | 3665 | if (has_edp_encoder) { |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3666 | target_clock = mode->clock; |
Chris Wilson | 8e647a2 | 2010-08-22 10:54:23 +0100 | [diff] [blame] | 3667 | intel_edp_link_config(has_edp_encoder, |
| 3668 | &lane, &link_bw); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3669 | } else { |
| 3670 | /* DP over FDI requires target mode clock |
| 3671 | instead of link clock */ |
| 3672 | if (is_dp) |
| 3673 | target_clock = mode->clock; |
| 3674 | else |
| 3675 | target_clock = adjusted_mode->clock; |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 3676 | |
| 3677 | /* FDI is a binary signal running at ~2.7GHz, encoding |
| 3678 | * each output octet as 10 bits. The actual frequency |
| 3679 | * is stored as a divider into a 100MHz clock, and the |
| 3680 | * mode pixel clock is stored in units of 1KHz. |
| 3681 | * Hence the bw of each lane in terms of the mode signal |
| 3682 | * is: |
| 3683 | */ |
| 3684 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3685 | } |
Zhenyu Wang | 58a2747 | 2009-09-25 08:01:28 +0000 | [diff] [blame] | 3686 | |
| 3687 | /* determine panel color depth */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3688 | temp = I915_READ(PIPECONF(pipe)); |
Zhao Yakui | e5a95eb | 2010-01-04 16:29:32 +0800 | [diff] [blame] | 3689 | temp &= ~PIPE_BPC_MASK; |
| 3690 | if (is_lvds) { |
Zhao Yakui | e5a95eb | 2010-01-04 16:29:32 +0800 | [diff] [blame] | 3691 | /* the BPC will be 6 if it is 18-bit LVDS panel */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3692 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) |
Zhao Yakui | e5a95eb | 2010-01-04 16:29:32 +0800 | [diff] [blame] | 3693 | temp |= PIPE_8BPC; |
| 3694 | else |
| 3695 | temp |= PIPE_6BPC; |
Chris Wilson | 8e647a2 | 2010-08-22 10:54:23 +0100 | [diff] [blame] | 3696 | } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) { |
Zhenyu Wang | 885a5fb | 2010-01-12 05:38:31 +0800 | [diff] [blame] | 3697 | switch (dev_priv->edp_bpp/3) { |
| 3698 | case 8: |
| 3699 | temp |= PIPE_8BPC; |
| 3700 | break; |
| 3701 | case 10: |
| 3702 | temp |= PIPE_10BPC; |
| 3703 | break; |
| 3704 | case 6: |
| 3705 | temp |= PIPE_6BPC; |
| 3706 | break; |
| 3707 | case 12: |
| 3708 | temp |= PIPE_12BPC; |
| 3709 | break; |
| 3710 | } |
Zhao Yakui | e5a95eb | 2010-01-04 16:29:32 +0800 | [diff] [blame] | 3711 | } else |
| 3712 | temp |= PIPE_8BPC; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3713 | I915_WRITE(PIPECONF(pipe), temp); |
Zhenyu Wang | 58a2747 | 2009-09-25 08:01:28 +0000 | [diff] [blame] | 3714 | |
| 3715 | switch (temp & PIPE_BPC_MASK) { |
| 3716 | case PIPE_8BPC: |
| 3717 | bpp = 24; |
| 3718 | break; |
| 3719 | case PIPE_10BPC: |
| 3720 | bpp = 30; |
| 3721 | break; |
| 3722 | case PIPE_6BPC: |
| 3723 | bpp = 18; |
| 3724 | break; |
| 3725 | case PIPE_12BPC: |
| 3726 | bpp = 36; |
| 3727 | break; |
| 3728 | default: |
| 3729 | DRM_ERROR("unknown pipe bpc value\n"); |
| 3730 | bpp = 24; |
| 3731 | } |
| 3732 | |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 3733 | if (!lane) { |
| 3734 | /* |
| 3735 | * Account for spread spectrum to avoid |
| 3736 | * oversubscribing the link. Max center spread |
| 3737 | * is 2.5%; use 5% for safety's sake. |
| 3738 | */ |
| 3739 | u32 bps = target_clock * bpp * 21 / 20; |
| 3740 | lane = bps / (link_bw * 8) + 1; |
| 3741 | } |
| 3742 | |
| 3743 | intel_crtc->fdi_lanes = lane; |
| 3744 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3745 | ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3746 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3747 | |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3748 | /* Ironlake: try to setup display ref clock before DPLL |
| 3749 | * enabling. This is only under driver's control after |
| 3750 | * PCH B stepping, previous chipset stepping should be |
| 3751 | * ignoring this setting. |
| 3752 | */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3753 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3754 | temp = I915_READ(PCH_DREF_CONTROL); |
| 3755 | /* Always enable nonspread source */ |
| 3756 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; |
| 3757 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3758 | temp &= ~DREF_SSC_SOURCE_MASK; |
| 3759 | temp |= DREF_SSC_SOURCE_ENABLE; |
| 3760 | I915_WRITE(PCH_DREF_CONTROL, temp); |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3761 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3762 | POSTING_READ(PCH_DREF_CONTROL); |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3763 | udelay(200); |
| 3764 | |
Chris Wilson | 8e647a2 | 2010-08-22 10:54:23 +0100 | [diff] [blame] | 3765 | if (has_edp_encoder) { |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3766 | if (dev_priv->lvds_use_ssc) { |
| 3767 | temp |= DREF_SSC1_ENABLE; |
| 3768 | I915_WRITE(PCH_DREF_CONTROL, temp); |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3769 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3770 | POSTING_READ(PCH_DREF_CONTROL); |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3771 | udelay(200); |
| 3772 | |
| 3773 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 3774 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3775 | } else { |
| 3776 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3777 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3778 | I915_WRITE(PCH_DREF_CONTROL, temp); |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3779 | } |
| 3780 | } |
| 3781 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3782 | if (IS_PINEVIEW(dev)) { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3783 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3784 | if (has_reduced_clock) |
| 3785 | fp2 = (1 << reduced_clock.n) << 16 | |
| 3786 | reduced_clock.m1 << 8 | reduced_clock.m2; |
| 3787 | } else { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3788 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3789 | if (has_reduced_clock) |
| 3790 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | |
| 3791 | reduced_clock.m2; |
| 3792 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3793 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3794 | dpll = 0; |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3795 | if (!HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3796 | dpll = DPLL_VGA_MODE_DIS; |
| 3797 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3798 | if (!IS_GEN2(dev)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3799 | if (is_lvds) |
| 3800 | dpll |= DPLLB_MODE_LVDS; |
| 3801 | else |
| 3802 | dpll |= DPLLB_MODE_DAC_SERIAL; |
| 3803 | if (is_sdvo) { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 3804 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 3805 | if (pixel_multiplier > 1) { |
| 3806 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 3807 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
| 3808 | else if (HAS_PCH_SPLIT(dev)) |
| 3809 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
| 3810 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3811 | dpll |= DPLL_DVO_HIGH_SPEED; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3812 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3813 | if (is_dp) |
| 3814 | dpll |= DPLL_DVO_HIGH_SPEED; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3815 | |
| 3816 | /* compute bitmask from p1 value */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3817 | if (IS_PINEVIEW(dev)) |
| 3818 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3819 | else { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3820 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3821 | /* also FPA1 */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3822 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3823 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3824 | if (IS_G4X(dev) && has_reduced_clock) |
| 3825 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3826 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3827 | switch (clock.p2) { |
| 3828 | case 5: |
| 3829 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 3830 | break; |
| 3831 | case 7: |
| 3832 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 3833 | break; |
| 3834 | case 10: |
| 3835 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 3836 | break; |
| 3837 | case 14: |
| 3838 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 3839 | break; |
| 3840 | } |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3841 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3842 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
| 3843 | } else { |
| 3844 | if (is_lvds) { |
| 3845 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 3846 | } else { |
| 3847 | if (clock.p1 == 2) |
| 3848 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
| 3849 | else |
| 3850 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 3851 | if (clock.p2 == 4) |
| 3852 | dpll |= PLL_P2_DIVIDE_BY_4; |
| 3853 | } |
| 3854 | } |
| 3855 | |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3856 | if (is_sdvo && is_tv) |
| 3857 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
| 3858 | else if (is_tv) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3859 | /* XXX: just matching BIOS for now */ |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3860 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3861 | dpll |= 3; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 3862 | else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3863 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3864 | else |
| 3865 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 3866 | |
| 3867 | /* setup pipeconf */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3868 | pipeconf = I915_READ(PIPECONF(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3869 | |
| 3870 | /* Set up the display plane register */ |
| 3871 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 3872 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3873 | /* Ironlake's plane is forced to pipe, bit 24 is to |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3874 | enable color space conversion */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3875 | if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3876 | if (pipe == 0) |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 3877 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3878 | else |
| 3879 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
| 3880 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3881 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3882 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3883 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
| 3884 | * core speed. |
| 3885 | * |
| 3886 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
| 3887 | * pipe == 0 check? |
| 3888 | */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3889 | if (mode->clock > |
| 3890 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3891 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3892 | else |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3893 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3894 | } |
| 3895 | |
Linus Torvalds | 8d86dc6 | 2010-06-08 20:16:28 -0700 | [diff] [blame] | 3896 | dspcntr |= DISPLAY_PLANE_ENABLE; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3897 | pipeconf |= PIPECONF_ENABLE; |
Linus Torvalds | 8d86dc6 | 2010-06-08 20:16:28 -0700 | [diff] [blame] | 3898 | dpll |= DPLL_VCO_ENABLE; |
| 3899 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3900 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3901 | drm_mode_debug_printmodeline(mode); |
| 3902 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3903 | /* assign to Ironlake registers */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3904 | if (HAS_PCH_SPLIT(dev)) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3905 | fp_reg = PCH_FP0(pipe); |
| 3906 | dpll_reg = PCH_DPLL(pipe); |
| 3907 | } else { |
| 3908 | fp_reg = FP0(pipe); |
| 3909 | dpll_reg = DPLL(pipe); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3910 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3911 | |
Chris Wilson | 8e647a2 | 2010-08-22 10:54:23 +0100 | [diff] [blame] | 3912 | if (!has_edp_encoder) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3913 | I915_WRITE(fp_reg, fp); |
| 3914 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3915 | |
| 3916 | POSTING_READ(dpll_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3917 | udelay(150); |
| 3918 | } |
| 3919 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3920 | /* enable transcoder DPLL */ |
| 3921 | if (HAS_PCH_CPT(dev)) { |
| 3922 | temp = I915_READ(PCH_DPLL_SEL); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3923 | if (pipe == 0) |
| 3924 | temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3925 | else |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3926 | temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3927 | I915_WRITE(PCH_DPLL_SEL, temp); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3928 | |
| 3929 | POSTING_READ(PCH_DPLL_SEL); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3930 | udelay(150); |
| 3931 | } |
| 3932 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3933 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
| 3934 | * This is an exception to the general rule that mode_set doesn't turn |
| 3935 | * things on. |
| 3936 | */ |
| 3937 | if (is_lvds) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3938 | reg = LVDS; |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3939 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3940 | reg = PCH_LVDS; |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 3941 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3942 | temp = I915_READ(reg); |
| 3943 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
Zhenyu Wang | b3b095b | 2010-04-07 16:15:56 +0800 | [diff] [blame] | 3944 | if (pipe == 1) { |
| 3945 | if (HAS_PCH_CPT(dev)) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3946 | temp |= PORT_TRANS_B_SEL_CPT; |
Zhenyu Wang | b3b095b | 2010-04-07 16:15:56 +0800 | [diff] [blame] | 3947 | else |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3948 | temp |= LVDS_PIPEB_SELECT; |
Zhenyu Wang | b3b095b | 2010-04-07 16:15:56 +0800 | [diff] [blame] | 3949 | } else { |
| 3950 | if (HAS_PCH_CPT(dev)) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3951 | temp &= ~PORT_TRANS_SEL_MASK; |
Zhenyu Wang | b3b095b | 2010-04-07 16:15:56 +0800 | [diff] [blame] | 3952 | else |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3953 | temp &= ~LVDS_PIPEB_SELECT; |
Zhenyu Wang | b3b095b | 2010-04-07 16:15:56 +0800 | [diff] [blame] | 3954 | } |
Zhao Yakui | a3e17eb | 2009-10-10 10:42:37 +0800 | [diff] [blame] | 3955 | /* set the corresponsding LVDS_BORDER bit */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3956 | temp |= dev_priv->lvds_border_bits; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3957 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
| 3958 | * set the DPLLs for dual-channel mode or not. |
| 3959 | */ |
| 3960 | if (clock.p2 == 7) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3961 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3962 | else |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3963 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3964 | |
| 3965 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
| 3966 | * appropriately here, but we need to look more thoroughly into how |
| 3967 | * panels behave in the two modes. |
| 3968 | */ |
Jesse Barnes | 434ed09 | 2010-09-07 14:48:06 -0700 | [diff] [blame] | 3969 | /* set the dithering flag on non-PCH LVDS as needed */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3970 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 434ed09 | 2010-09-07 14:48:06 -0700 | [diff] [blame] | 3971 | if (dev_priv->lvds_dither) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3972 | temp |= LVDS_ENABLE_DITHER; |
Jesse Barnes | 434ed09 | 2010-09-07 14:48:06 -0700 | [diff] [blame] | 3973 | else |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3974 | temp &= ~LVDS_ENABLE_DITHER; |
Zhao Yakui | 898822c | 2010-01-04 16:29:30 +0800 | [diff] [blame] | 3975 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3976 | I915_WRITE(reg, temp); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3977 | } |
Jesse Barnes | 434ed09 | 2010-09-07 14:48:06 -0700 | [diff] [blame] | 3978 | |
| 3979 | /* set the dithering flag and clear for anything other than a panel. */ |
| 3980 | if (HAS_PCH_SPLIT(dev)) { |
| 3981 | pipeconf &= ~PIPECONF_DITHER_EN; |
| 3982 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; |
| 3983 | if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) { |
| 3984 | pipeconf |= PIPECONF_DITHER_EN; |
| 3985 | pipeconf |= PIPECONF_DITHER_TYPE_ST1; |
| 3986 | } |
| 3987 | } |
| 3988 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3989 | if (is_dp) |
| 3990 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3991 | else if (HAS_PCH_SPLIT(dev)) { |
| 3992 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
| 3993 | if (pipe == 0) { |
| 3994 | I915_WRITE(TRANSA_DATA_M1, 0); |
| 3995 | I915_WRITE(TRANSA_DATA_N1, 0); |
| 3996 | I915_WRITE(TRANSA_DP_LINK_M1, 0); |
| 3997 | I915_WRITE(TRANSA_DP_LINK_N1, 0); |
| 3998 | } else { |
| 3999 | I915_WRITE(TRANSB_DATA_M1, 0); |
| 4000 | I915_WRITE(TRANSB_DATA_N1, 0); |
| 4001 | I915_WRITE(TRANSB_DP_LINK_M1, 0); |
| 4002 | I915_WRITE(TRANSB_DP_LINK_N1, 0); |
| 4003 | } |
| 4004 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4005 | |
Chris Wilson | 8e647a2 | 2010-08-22 10:54:23 +0100 | [diff] [blame] | 4006 | if (!has_edp_encoder) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4007 | I915_WRITE(fp_reg, fp); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4008 | I915_WRITE(dpll_reg, dpll); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4009 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4010 | /* Wait for the clocks to stabilize. */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4011 | POSTING_READ(dpll_reg); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4012 | udelay(150); |
| 4013 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4014 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4015 | temp = 0; |
Zhao Yakui | bb66c51 | 2009-09-10 15:45:49 +0800 | [diff] [blame] | 4016 | if (is_sdvo) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4017 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 4018 | if (temp > 1) |
| 4019 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 4020 | else |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4021 | temp = 0; |
| 4022 | } |
| 4023 | I915_WRITE(DPLL_MD(pipe), temp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4024 | } else { |
| 4025 | /* write it again -- the BIOS does, after all */ |
| 4026 | I915_WRITE(dpll_reg, dpll); |
| 4027 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4028 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4029 | /* Wait for the clocks to stabilize. */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4030 | POSTING_READ(dpll_reg); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4031 | udelay(150); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4032 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4033 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4034 | intel_crtc->lowfreq_avail = false; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4035 | if (is_lvds && has_reduced_clock && i915_powersave) { |
| 4036 | I915_WRITE(fp_reg + 4, fp2); |
| 4037 | intel_crtc->lowfreq_avail = true; |
| 4038 | if (HAS_PIPE_CXSR(dev)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4039 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4040 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
| 4041 | } |
| 4042 | } else { |
| 4043 | I915_WRITE(fp_reg + 4, fp); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4044 | if (HAS_PIPE_CXSR(dev)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4045 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4046 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
| 4047 | } |
| 4048 | } |
| 4049 | |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 4050 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 4051 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
| 4052 | /* the chip adds 2 halflines automatically */ |
| 4053 | adjusted_mode->crtc_vdisplay -= 1; |
| 4054 | adjusted_mode->crtc_vtotal -= 1; |
| 4055 | adjusted_mode->crtc_vblank_start -= 1; |
| 4056 | adjusted_mode->crtc_vblank_end -= 1; |
| 4057 | adjusted_mode->crtc_vsync_end -= 1; |
| 4058 | adjusted_mode->crtc_vsync_start -= 1; |
| 4059 | } else |
| 4060 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ |
| 4061 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4062 | I915_WRITE(HTOTAL(pipe), |
| 4063 | (adjusted_mode->crtc_hdisplay - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4064 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4065 | I915_WRITE(HBLANK(pipe), |
| 4066 | (adjusted_mode->crtc_hblank_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4067 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4068 | I915_WRITE(HSYNC(pipe), |
| 4069 | (adjusted_mode->crtc_hsync_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4070 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4071 | |
| 4072 | I915_WRITE(VTOTAL(pipe), |
| 4073 | (adjusted_mode->crtc_vdisplay - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4074 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4075 | I915_WRITE(VBLANK(pipe), |
| 4076 | (adjusted_mode->crtc_vblank_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4077 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4078 | I915_WRITE(VSYNC(pipe), |
| 4079 | (adjusted_mode->crtc_vsync_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4080 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4081 | |
| 4082 | /* pipesrc and dspsize control the size that is scaled from, |
| 4083 | * which should always be the user's requested size. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4084 | */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 4085 | if (!HAS_PCH_SPLIT(dev)) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4086 | I915_WRITE(DSPSIZE(plane), |
| 4087 | ((mode->vdisplay - 1) << 16) | |
| 4088 | (mode->hdisplay - 1)); |
| 4089 | I915_WRITE(DSPPOS(plane), 0); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4090 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4091 | I915_WRITE(PIPESRC(pipe), |
| 4092 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4093 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 4094 | if (HAS_PCH_SPLIT(dev)) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4095 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
| 4096 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); |
| 4097 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); |
| 4098 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4099 | |
Chris Wilson | 8e647a2 | 2010-08-22 10:54:23 +0100 | [diff] [blame] | 4100 | if (has_edp_encoder) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 4101 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4102 | } else { |
| 4103 | /* enable FDI RX PLL too */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4104 | reg = FDI_RX_CTL(pipe); |
| 4105 | temp = I915_READ(reg); |
| 4106 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
| 4107 | |
| 4108 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 4109 | udelay(200); |
| 4110 | |
| 4111 | /* enable FDI TX PLL too */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4112 | reg = FDI_TX_CTL(pipe); |
| 4113 | temp = I915_READ(reg); |
| 4114 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 4115 | |
| 4116 | /* enable FDI RX PCDCLK */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4117 | reg = FDI_RX_CTL(pipe); |
| 4118 | temp = I915_READ(reg); |
| 4119 | I915_WRITE(reg, temp | FDI_PCDCLK); |
| 4120 | |
| 4121 | POSTING_READ(reg); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4122 | udelay(200); |
| 4123 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4124 | } |
| 4125 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4126 | I915_WRITE(PIPECONF(pipe), pipeconf); |
| 4127 | POSTING_READ(PIPECONF(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4128 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 4129 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4130 | |
Eric Anholt | c2416fc | 2009-11-05 15:30:35 -0800 | [diff] [blame] | 4131 | if (IS_IRONLAKE(dev)) { |
Zhenyu Wang | 553bd14 | 2009-09-02 10:57:52 +0800 | [diff] [blame] | 4132 | /* enable address swizzle for tiling buffer */ |
| 4133 | temp = I915_READ(DISP_ARB_CTL); |
| 4134 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); |
| 4135 | } |
| 4136 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4137 | I915_WRITE(DSPCNTR(plane), dspcntr); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4138 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 4139 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4140 | |
| 4141 | intel_update_watermarks(dev); |
| 4142 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4143 | drm_vblank_post_modeset(dev, pipe); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 4144 | |
Chris Wilson | 1f803ee | 2009-06-06 09:45:59 +0100 | [diff] [blame] | 4145 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4146 | } |
| 4147 | |
| 4148 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
| 4149 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
| 4150 | { |
| 4151 | struct drm_device *dev = crtc->dev; |
| 4152 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4153 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4154 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; |
| 4155 | int i; |
| 4156 | |
| 4157 | /* The clocks have to be on to load the palette. */ |
| 4158 | if (!crtc->enabled) |
| 4159 | return; |
| 4160 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 4161 | /* use legacy palette for Ironlake */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 4162 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4163 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : |
| 4164 | LGC_PALETTE_B; |
| 4165 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4166 | for (i = 0; i < 256; i++) { |
| 4167 | I915_WRITE(palreg + 4 * i, |
| 4168 | (intel_crtc->lut_r[i] << 16) | |
| 4169 | (intel_crtc->lut_g[i] << 8) | |
| 4170 | intel_crtc->lut_b[i]); |
| 4171 | } |
| 4172 | } |
| 4173 | |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4174 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
| 4175 | { |
| 4176 | struct drm_device *dev = crtc->dev; |
| 4177 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4178 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4179 | bool visible = base != 0; |
| 4180 | u32 cntl; |
| 4181 | |
| 4182 | if (intel_crtc->cursor_visible == visible) |
| 4183 | return; |
| 4184 | |
| 4185 | cntl = I915_READ(CURACNTR); |
| 4186 | if (visible) { |
| 4187 | /* On these chipsets we can only modify the base whilst |
| 4188 | * the cursor is disabled. |
| 4189 | */ |
| 4190 | I915_WRITE(CURABASE, base); |
| 4191 | |
| 4192 | cntl &= ~(CURSOR_FORMAT_MASK); |
| 4193 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
| 4194 | cntl |= CURSOR_ENABLE | |
| 4195 | CURSOR_GAMMA_ENABLE | |
| 4196 | CURSOR_FORMAT_ARGB; |
| 4197 | } else |
| 4198 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
| 4199 | I915_WRITE(CURACNTR, cntl); |
| 4200 | |
| 4201 | intel_crtc->cursor_visible = visible; |
| 4202 | } |
| 4203 | |
| 4204 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
| 4205 | { |
| 4206 | struct drm_device *dev = crtc->dev; |
| 4207 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4208 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4209 | int pipe = intel_crtc->pipe; |
| 4210 | bool visible = base != 0; |
| 4211 | |
| 4212 | if (intel_crtc->cursor_visible != visible) { |
| 4213 | uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); |
| 4214 | if (base) { |
| 4215 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
| 4216 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
| 4217 | cntl |= pipe << 28; /* Connect to correct pipe */ |
| 4218 | } else { |
| 4219 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
| 4220 | cntl |= CURSOR_MODE_DISABLE; |
| 4221 | } |
| 4222 | I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl); |
| 4223 | |
| 4224 | intel_crtc->cursor_visible = visible; |
| 4225 | } |
| 4226 | /* and commit changes on next vblank */ |
| 4227 | I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base); |
| 4228 | } |
| 4229 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4230 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4231 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
| 4232 | bool on) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4233 | { |
| 4234 | struct drm_device *dev = crtc->dev; |
| 4235 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4236 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4237 | int pipe = intel_crtc->pipe; |
| 4238 | int x = intel_crtc->cursor_x; |
| 4239 | int y = intel_crtc->cursor_y; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4240 | u32 base, pos; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4241 | bool visible; |
| 4242 | |
| 4243 | pos = 0; |
| 4244 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4245 | if (on && crtc->enabled && crtc->fb) { |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4246 | base = intel_crtc->cursor_addr; |
| 4247 | if (x > (int) crtc->fb->width) |
| 4248 | base = 0; |
| 4249 | |
| 4250 | if (y > (int) crtc->fb->height) |
| 4251 | base = 0; |
| 4252 | } else |
| 4253 | base = 0; |
| 4254 | |
| 4255 | if (x < 0) { |
| 4256 | if (x + intel_crtc->cursor_width < 0) |
| 4257 | base = 0; |
| 4258 | |
| 4259 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
| 4260 | x = -x; |
| 4261 | } |
| 4262 | pos |= x << CURSOR_X_SHIFT; |
| 4263 | |
| 4264 | if (y < 0) { |
| 4265 | if (y + intel_crtc->cursor_height < 0) |
| 4266 | base = 0; |
| 4267 | |
| 4268 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
| 4269 | y = -y; |
| 4270 | } |
| 4271 | pos |= y << CURSOR_Y_SHIFT; |
| 4272 | |
| 4273 | visible = base != 0; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4274 | if (!visible && !intel_crtc->cursor_visible) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4275 | return; |
| 4276 | |
| 4277 | I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4278 | if (IS_845G(dev) || IS_I865G(dev)) |
| 4279 | i845_update_cursor(crtc, base); |
| 4280 | else |
| 4281 | i9xx_update_cursor(crtc, base); |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4282 | |
| 4283 | if (visible) |
| 4284 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); |
| 4285 | } |
| 4286 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4287 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
| 4288 | struct drm_file *file_priv, |
| 4289 | uint32_t handle, |
| 4290 | uint32_t width, uint32_t height) |
| 4291 | { |
| 4292 | struct drm_device *dev = crtc->dev; |
| 4293 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4294 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4295 | struct drm_gem_object *bo; |
| 4296 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4297 | uint32_t addr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4298 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4299 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4300 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4301 | |
| 4302 | /* if we want to turn off the cursor ignore width and height */ |
| 4303 | if (!handle) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4304 | DRM_DEBUG_KMS("cursor off\n"); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4305 | addr = 0; |
| 4306 | bo = NULL; |
Pierre Willenbrock | 5004417 | 2009-02-23 10:12:15 +1000 | [diff] [blame] | 4307 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4308 | goto finish; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4309 | } |
| 4310 | |
| 4311 | /* Currently we only support 64x64 cursors */ |
| 4312 | if (width != 64 || height != 64) { |
| 4313 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
| 4314 | return -EINVAL; |
| 4315 | } |
| 4316 | |
| 4317 | bo = drm_gem_object_lookup(dev, file_priv, handle); |
| 4318 | if (!bo) |
| 4319 | return -ENOENT; |
| 4320 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4321 | obj_priv = to_intel_bo(bo); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4322 | |
| 4323 | if (bo->size < width * height * 4) { |
| 4324 | DRM_ERROR("buffer is to small\n"); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 4325 | ret = -ENOMEM; |
| 4326 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4327 | } |
| 4328 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4329 | /* we only need to pin inside GTT if cursor is non-phy */ |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4330 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 4331 | if (!dev_priv->info->cursor_needs_physical) { |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4332 | ret = i915_gem_object_pin(bo, PAGE_SIZE); |
| 4333 | if (ret) { |
| 4334 | DRM_ERROR("failed to pin cursor bo\n"); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4335 | goto fail_locked; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4336 | } |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 4337 | |
| 4338 | ret = i915_gem_object_set_to_gtt_domain(bo, 0); |
| 4339 | if (ret) { |
| 4340 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
| 4341 | goto fail_unpin; |
| 4342 | } |
| 4343 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4344 | addr = obj_priv->gtt_offset; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4345 | } else { |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4346 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4347 | ret = i915_gem_attach_phys_object(dev, bo, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4348 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
| 4349 | align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4350 | if (ret) { |
| 4351 | DRM_ERROR("failed to attach phys object\n"); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4352 | goto fail_locked; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4353 | } |
| 4354 | addr = obj_priv->phys_obj->handle->busaddr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4355 | } |
| 4356 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4357 | if (IS_GEN2(dev)) |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 4358 | I915_WRITE(CURSIZE, (height << 12) | width); |
| 4359 | |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4360 | finish: |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4361 | if (intel_crtc->cursor_bo) { |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 4362 | if (dev_priv->info->cursor_needs_physical) { |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4363 | if (intel_crtc->cursor_bo != bo) |
| 4364 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
| 4365 | } else |
| 4366 | i915_gem_object_unpin(intel_crtc->cursor_bo); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4367 | drm_gem_object_unreference(intel_crtc->cursor_bo); |
| 4368 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 4369 | |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4370 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4371 | |
| 4372 | intel_crtc->cursor_addr = addr; |
| 4373 | intel_crtc->cursor_bo = bo; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4374 | intel_crtc->cursor_width = width; |
| 4375 | intel_crtc->cursor_height = height; |
| 4376 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4377 | intel_crtc_update_cursor(crtc, true); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4378 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4379 | return 0; |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 4380 | fail_unpin: |
| 4381 | i915_gem_object_unpin(bo); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4382 | fail_locked: |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 4383 | mutex_unlock(&dev->struct_mutex); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 4384 | fail: |
| 4385 | drm_gem_object_unreference_unlocked(bo); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 4386 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4387 | } |
| 4388 | |
| 4389 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 4390 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4391 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4392 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4393 | intel_crtc->cursor_x = x; |
| 4394 | intel_crtc->cursor_y = y; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4395 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4396 | intel_crtc_update_cursor(crtc, true); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4397 | |
| 4398 | return 0; |
| 4399 | } |
| 4400 | |
| 4401 | /** Sets the color ramps on behalf of RandR */ |
| 4402 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| 4403 | u16 blue, int regno) |
| 4404 | { |
| 4405 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4406 | |
| 4407 | intel_crtc->lut_r[regno] = red >> 8; |
| 4408 | intel_crtc->lut_g[regno] = green >> 8; |
| 4409 | intel_crtc->lut_b[regno] = blue >> 8; |
| 4410 | } |
| 4411 | |
Dave Airlie | b8c00ac | 2009-10-06 13:54:01 +1000 | [diff] [blame] | 4412 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 4413 | u16 *blue, int regno) |
| 4414 | { |
| 4415 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4416 | |
| 4417 | *red = intel_crtc->lut_r[regno] << 8; |
| 4418 | *green = intel_crtc->lut_g[regno] << 8; |
| 4419 | *blue = intel_crtc->lut_b[regno] << 8; |
| 4420 | } |
| 4421 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4422 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 4423 | u16 *blue, uint32_t start, uint32_t size) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4424 | { |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 4425 | int end = (start + size > 256) ? 256 : start + size, i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4426 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4427 | |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 4428 | for (i = start; i < end; i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4429 | intel_crtc->lut_r[i] = red[i] >> 8; |
| 4430 | intel_crtc->lut_g[i] = green[i] >> 8; |
| 4431 | intel_crtc->lut_b[i] = blue[i] >> 8; |
| 4432 | } |
| 4433 | |
| 4434 | intel_crtc_load_lut(crtc); |
| 4435 | } |
| 4436 | |
| 4437 | /** |
| 4438 | * Get a pipe with a simple mode set on it for doing load-based monitor |
| 4439 | * detection. |
| 4440 | * |
| 4441 | * It will be up to the load-detect code to adjust the pipe as appropriate for |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 4442 | * its requirements. The pipe will be connected to no other encoders. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4443 | * |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 4444 | * Currently this code will only succeed if there is a pipe with no encoders |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4445 | * configured for it. In the future, it could choose to temporarily disable |
| 4446 | * some outputs to free up a pipe for its use. |
| 4447 | * |
| 4448 | * \return crtc, or NULL if no pipes are available. |
| 4449 | */ |
| 4450 | |
| 4451 | /* VESA 640x480x72Hz mode to set on the pipe */ |
| 4452 | static struct drm_display_mode load_detect_mode = { |
| 4453 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
| 4454 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
| 4455 | }; |
| 4456 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 4457 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 4458 | struct drm_connector *connector, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4459 | struct drm_display_mode *mode, |
| 4460 | int *dpms_mode) |
| 4461 | { |
| 4462 | struct intel_crtc *intel_crtc; |
| 4463 | struct drm_crtc *possible_crtc; |
| 4464 | struct drm_crtc *supported_crtc =NULL; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 4465 | struct drm_encoder *encoder = &intel_encoder->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4466 | struct drm_crtc *crtc = NULL; |
| 4467 | struct drm_device *dev = encoder->dev; |
| 4468 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 4469 | struct drm_crtc_helper_funcs *crtc_funcs; |
| 4470 | int i = -1; |
| 4471 | |
| 4472 | /* |
| 4473 | * Algorithm gets a little messy: |
| 4474 | * - if the connector already has an assigned crtc, use it (but make |
| 4475 | * sure it's on first) |
| 4476 | * - try to find the first unused crtc that can drive this connector, |
| 4477 | * and use that if we find one |
| 4478 | * - if there are no unused crtcs available, try to use the first |
| 4479 | * one we found that supports the connector |
| 4480 | */ |
| 4481 | |
| 4482 | /* See if we already have a CRTC for this connector */ |
| 4483 | if (encoder->crtc) { |
| 4484 | crtc = encoder->crtc; |
| 4485 | /* Make sure the crtc and connector are running */ |
| 4486 | intel_crtc = to_intel_crtc(crtc); |
| 4487 | *dpms_mode = intel_crtc->dpms_mode; |
| 4488 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
| 4489 | crtc_funcs = crtc->helper_private; |
| 4490 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
| 4491 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
| 4492 | } |
| 4493 | return crtc; |
| 4494 | } |
| 4495 | |
| 4496 | /* Find an unused one (if possible) */ |
| 4497 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
| 4498 | i++; |
| 4499 | if (!(encoder->possible_crtcs & (1 << i))) |
| 4500 | continue; |
| 4501 | if (!possible_crtc->enabled) { |
| 4502 | crtc = possible_crtc; |
| 4503 | break; |
| 4504 | } |
| 4505 | if (!supported_crtc) |
| 4506 | supported_crtc = possible_crtc; |
| 4507 | } |
| 4508 | |
| 4509 | /* |
| 4510 | * If we didn't find an unused CRTC, don't use any. |
| 4511 | */ |
| 4512 | if (!crtc) { |
| 4513 | return NULL; |
| 4514 | } |
| 4515 | |
| 4516 | encoder->crtc = crtc; |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 4517 | connector->encoder = encoder; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 4518 | intel_encoder->load_detect_temp = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4519 | |
| 4520 | intel_crtc = to_intel_crtc(crtc); |
| 4521 | *dpms_mode = intel_crtc->dpms_mode; |
| 4522 | |
| 4523 | if (!crtc->enabled) { |
| 4524 | if (!mode) |
| 4525 | mode = &load_detect_mode; |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 4526 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4527 | } else { |
| 4528 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
| 4529 | crtc_funcs = crtc->helper_private; |
| 4530 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
| 4531 | } |
| 4532 | |
| 4533 | /* Add this connector to the crtc */ |
| 4534 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); |
| 4535 | encoder_funcs->commit(encoder); |
| 4536 | } |
| 4537 | /* let the connector get through one full cycle before testing */ |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 4538 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4539 | |
| 4540 | return crtc; |
| 4541 | } |
| 4542 | |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 4543 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
| 4544 | struct drm_connector *connector, int dpms_mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4545 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 4546 | struct drm_encoder *encoder = &intel_encoder->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4547 | struct drm_device *dev = encoder->dev; |
| 4548 | struct drm_crtc *crtc = encoder->crtc; |
| 4549 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 4550 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 4551 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 4552 | if (intel_encoder->load_detect_temp) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4553 | encoder->crtc = NULL; |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 4554 | connector->encoder = NULL; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 4555 | intel_encoder->load_detect_temp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4556 | crtc->enabled = drm_helper_crtc_in_use(crtc); |
| 4557 | drm_helper_disable_unused_functions(dev); |
| 4558 | } |
| 4559 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 4560 | /* Switch crtc and encoder back off if necessary */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4561 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { |
| 4562 | if (encoder->crtc == crtc) |
| 4563 | encoder_funcs->dpms(encoder, dpms_mode); |
| 4564 | crtc_funcs->dpms(crtc, dpms_mode); |
| 4565 | } |
| 4566 | } |
| 4567 | |
| 4568 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
| 4569 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) |
| 4570 | { |
| 4571 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4572 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4573 | int pipe = intel_crtc->pipe; |
| 4574 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); |
| 4575 | u32 fp; |
| 4576 | intel_clock_t clock; |
| 4577 | |
| 4578 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
| 4579 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); |
| 4580 | else |
| 4581 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); |
| 4582 | |
| 4583 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 4584 | if (IS_PINEVIEW(dev)) { |
| 4585 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
| 4586 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4587 | } else { |
| 4588 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 4589 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 4590 | } |
| 4591 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4592 | if (!IS_GEN2(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 4593 | if (IS_PINEVIEW(dev)) |
| 4594 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
| 4595 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4596 | else |
| 4597 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4598 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 4599 | |
| 4600 | switch (dpll & DPLL_MODE_MASK) { |
| 4601 | case DPLLB_MODE_DAC_SERIAL: |
| 4602 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
| 4603 | 5 : 10; |
| 4604 | break; |
| 4605 | case DPLLB_MODE_LVDS: |
| 4606 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
| 4607 | 7 : 14; |
| 4608 | break; |
| 4609 | default: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4610 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4611 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
| 4612 | return 0; |
| 4613 | } |
| 4614 | |
| 4615 | /* XXX: Handle the 100Mhz refclk */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4616 | intel_clock(dev, 96000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4617 | } else { |
| 4618 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
| 4619 | |
| 4620 | if (is_lvds) { |
| 4621 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 4622 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 4623 | clock.p2 = 14; |
| 4624 | |
| 4625 | if ((dpll & PLL_REF_INPUT_MASK) == |
| 4626 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
| 4627 | /* XXX: might not be 66MHz */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4628 | intel_clock(dev, 66000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4629 | } else |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4630 | intel_clock(dev, 48000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4631 | } else { |
| 4632 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 4633 | clock.p1 = 2; |
| 4634 | else { |
| 4635 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 4636 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 4637 | } |
| 4638 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 4639 | clock.p2 = 4; |
| 4640 | else |
| 4641 | clock.p2 = 2; |
| 4642 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4643 | intel_clock(dev, 48000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4644 | } |
| 4645 | } |
| 4646 | |
| 4647 | /* XXX: It would be nice to validate the clocks, but we can't reuse |
| 4648 | * i830PllIsValid() because it relies on the xf86_config connector |
| 4649 | * configuration being accurate, which it isn't necessarily. |
| 4650 | */ |
| 4651 | |
| 4652 | return clock.dot; |
| 4653 | } |
| 4654 | |
| 4655 | /** Returns the currently programmed mode of the given pipe. */ |
| 4656 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 4657 | struct drm_crtc *crtc) |
| 4658 | { |
| 4659 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4660 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4661 | int pipe = intel_crtc->pipe; |
| 4662 | struct drm_display_mode *mode; |
| 4663 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); |
| 4664 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); |
| 4665 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); |
| 4666 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); |
| 4667 | |
| 4668 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 4669 | if (!mode) |
| 4670 | return NULL; |
| 4671 | |
| 4672 | mode->clock = intel_crtc_clock_get(dev, crtc); |
| 4673 | mode->hdisplay = (htot & 0xffff) + 1; |
| 4674 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 4675 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 4676 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 4677 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 4678 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 4679 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 4680 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 4681 | |
| 4682 | drm_mode_set_name(mode); |
| 4683 | drm_mode_set_crtcinfo(mode, 0); |
| 4684 | |
| 4685 | return mode; |
| 4686 | } |
| 4687 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4688 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
| 4689 | |
| 4690 | /* When this timer fires, we've been idle for awhile */ |
| 4691 | static void intel_gpu_idle_timer(unsigned long arg) |
| 4692 | { |
| 4693 | struct drm_device *dev = (struct drm_device *)arg; |
| 4694 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4695 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4696 | DRM_DEBUG_DRIVER("idle timer fired, downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4697 | |
| 4698 | dev_priv->busy = false; |
| 4699 | |
Eric Anholt | 01dfba9 | 2009-09-06 15:18:53 -0700 | [diff] [blame] | 4700 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4701 | } |
| 4702 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4703 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
| 4704 | |
| 4705 | static void intel_crtc_idle_timer(unsigned long arg) |
| 4706 | { |
| 4707 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; |
| 4708 | struct drm_crtc *crtc = &intel_crtc->base; |
| 4709 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; |
| 4710 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4711 | DRM_DEBUG_DRIVER("idle timer fired, downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4712 | |
| 4713 | intel_crtc->busy = false; |
| 4714 | |
Eric Anholt | 01dfba9 | 2009-09-06 15:18:53 -0700 | [diff] [blame] | 4715 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4716 | } |
| 4717 | |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 4718 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4719 | { |
| 4720 | struct drm_device *dev = crtc->dev; |
| 4721 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4723 | int pipe = intel_crtc->pipe; |
| 4724 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
| 4725 | int dpll = I915_READ(dpll_reg); |
| 4726 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 4727 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4728 | return; |
| 4729 | |
| 4730 | if (!dev_priv->lvds_downclock_avail) |
| 4731 | return; |
| 4732 | |
| 4733 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4734 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4735 | |
| 4736 | /* Unlock panel regs */ |
Jesse Barnes | 4a655f0 | 2010-07-22 13:18:18 -0700 | [diff] [blame] | 4737 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
| 4738 | PANEL_UNLOCK_REGS); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4739 | |
| 4740 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
| 4741 | I915_WRITE(dpll_reg, dpll); |
| 4742 | dpll = I915_READ(dpll_reg); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 4743 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4744 | dpll = I915_READ(dpll_reg); |
| 4745 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4746 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4747 | |
| 4748 | /* ...and lock them again */ |
| 4749 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); |
| 4750 | } |
| 4751 | |
| 4752 | /* Schedule downclock */ |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 4753 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 4754 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4755 | } |
| 4756 | |
| 4757 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
| 4758 | { |
| 4759 | struct drm_device *dev = crtc->dev; |
| 4760 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4762 | int pipe = intel_crtc->pipe; |
| 4763 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
| 4764 | int dpll = I915_READ(dpll_reg); |
| 4765 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 4766 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4767 | return; |
| 4768 | |
| 4769 | if (!dev_priv->lvds_downclock_avail) |
| 4770 | return; |
| 4771 | |
| 4772 | /* |
| 4773 | * Since this is called by a timer, we should never get here in |
| 4774 | * the manual case. |
| 4775 | */ |
| 4776 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4777 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4778 | |
| 4779 | /* Unlock panel regs */ |
Jesse Barnes | 4a655f0 | 2010-07-22 13:18:18 -0700 | [diff] [blame] | 4780 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
| 4781 | PANEL_UNLOCK_REGS); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4782 | |
| 4783 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
| 4784 | I915_WRITE(dpll_reg, dpll); |
| 4785 | dpll = I915_READ(dpll_reg); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 4786 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4787 | dpll = I915_READ(dpll_reg); |
| 4788 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4789 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4790 | |
| 4791 | /* ...and lock them again */ |
| 4792 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); |
| 4793 | } |
| 4794 | |
| 4795 | } |
| 4796 | |
| 4797 | /** |
| 4798 | * intel_idle_update - adjust clocks for idleness |
| 4799 | * @work: work struct |
| 4800 | * |
| 4801 | * Either the GPU or display (or both) went idle. Check the busy status |
| 4802 | * here and adjust the CRTC and GPU clocks as necessary. |
| 4803 | */ |
| 4804 | static void intel_idle_update(struct work_struct *work) |
| 4805 | { |
| 4806 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 4807 | idle_work); |
| 4808 | struct drm_device *dev = dev_priv->dev; |
| 4809 | struct drm_crtc *crtc; |
| 4810 | struct intel_crtc *intel_crtc; |
Li Peng | 45ac22c | 2010-06-12 23:38:35 +0800 | [diff] [blame] | 4811 | int enabled = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4812 | |
| 4813 | if (!i915_powersave) |
| 4814 | return; |
| 4815 | |
| 4816 | mutex_lock(&dev->struct_mutex); |
| 4817 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 4818 | i915_update_gfx_val(dev_priv); |
| 4819 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4820 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 4821 | /* Skip inactive CRTCs */ |
| 4822 | if (!crtc->fb) |
| 4823 | continue; |
| 4824 | |
Li Peng | 45ac22c | 2010-06-12 23:38:35 +0800 | [diff] [blame] | 4825 | enabled++; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4826 | intel_crtc = to_intel_crtc(crtc); |
| 4827 | if (!intel_crtc->busy) |
| 4828 | intel_decrease_pllclock(crtc); |
| 4829 | } |
| 4830 | |
Li Peng | 45ac22c | 2010-06-12 23:38:35 +0800 | [diff] [blame] | 4831 | if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) { |
| 4832 | DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); |
| 4833 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); |
| 4834 | } |
| 4835 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4836 | mutex_unlock(&dev->struct_mutex); |
| 4837 | } |
| 4838 | |
| 4839 | /** |
| 4840 | * intel_mark_busy - mark the GPU and possibly the display busy |
| 4841 | * @dev: drm device |
| 4842 | * @obj: object we're operating on |
| 4843 | * |
| 4844 | * Callers can use this function to indicate that the GPU is busy processing |
| 4845 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout |
| 4846 | * buffer), we'll also mark the display as busy, so we know to increase its |
| 4847 | * clock frequency. |
| 4848 | */ |
| 4849 | void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) |
| 4850 | { |
| 4851 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4852 | struct drm_crtc *crtc = NULL; |
| 4853 | struct intel_framebuffer *intel_fb; |
| 4854 | struct intel_crtc *intel_crtc; |
| 4855 | |
Zhenyu Wang | 5e17ee7 | 2009-09-03 09:30:06 +0800 | [diff] [blame] | 4856 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4857 | return; |
| 4858 | |
Li Peng | 060e645 | 2010-02-10 01:54:24 +0800 | [diff] [blame] | 4859 | if (!dev_priv->busy) { |
| 4860 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
| 4861 | u32 fw_blc_self; |
Li Peng | ee980b8 | 2010-01-27 19:01:11 +0800 | [diff] [blame] | 4862 | |
Li Peng | 060e645 | 2010-02-10 01:54:24 +0800 | [diff] [blame] | 4863 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); |
| 4864 | fw_blc_self = I915_READ(FW_BLC_SELF); |
| 4865 | fw_blc_self &= ~FW_BLC_SELF_EN; |
| 4866 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); |
| 4867 | } |
Chris Wilson | 28cf798 | 2009-11-30 01:08:56 +0000 | [diff] [blame] | 4868 | dev_priv->busy = true; |
Li Peng | 060e645 | 2010-02-10 01:54:24 +0800 | [diff] [blame] | 4869 | } else |
Chris Wilson | 28cf798 | 2009-11-30 01:08:56 +0000 | [diff] [blame] | 4870 | mod_timer(&dev_priv->idle_timer, jiffies + |
| 4871 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4872 | |
| 4873 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 4874 | if (!crtc->fb) |
| 4875 | continue; |
| 4876 | |
| 4877 | intel_crtc = to_intel_crtc(crtc); |
| 4878 | intel_fb = to_intel_framebuffer(crtc->fb); |
| 4879 | if (intel_fb->obj == obj) { |
| 4880 | if (!intel_crtc->busy) { |
Li Peng | 060e645 | 2010-02-10 01:54:24 +0800 | [diff] [blame] | 4881 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
| 4882 | u32 fw_blc_self; |
| 4883 | |
| 4884 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); |
| 4885 | fw_blc_self = I915_READ(FW_BLC_SELF); |
| 4886 | fw_blc_self &= ~FW_BLC_SELF_EN; |
| 4887 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); |
| 4888 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4889 | /* Non-busy -> busy, upclock */ |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 4890 | intel_increase_pllclock(crtc); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4891 | intel_crtc->busy = true; |
| 4892 | } else { |
| 4893 | /* Busy -> busy, put off timer */ |
| 4894 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 4895 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
| 4896 | } |
| 4897 | } |
| 4898 | } |
| 4899 | } |
| 4900 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4901 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
| 4902 | { |
| 4903 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 4904 | struct drm_device *dev = crtc->dev; |
| 4905 | struct intel_unpin_work *work; |
| 4906 | unsigned long flags; |
| 4907 | |
| 4908 | spin_lock_irqsave(&dev->event_lock, flags); |
| 4909 | work = intel_crtc->unpin_work; |
| 4910 | intel_crtc->unpin_work = NULL; |
| 4911 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 4912 | |
| 4913 | if (work) { |
| 4914 | cancel_work_sync(&work->work); |
| 4915 | kfree(work); |
| 4916 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4917 | |
| 4918 | drm_crtc_cleanup(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 4919 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4920 | kfree(intel_crtc); |
| 4921 | } |
| 4922 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4923 | static void intel_unpin_work_fn(struct work_struct *__work) |
| 4924 | { |
| 4925 | struct intel_unpin_work *work = |
| 4926 | container_of(__work, struct intel_unpin_work, work); |
| 4927 | |
| 4928 | mutex_lock(&work->dev->struct_mutex); |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 4929 | i915_gem_object_unpin(work->old_fb_obj); |
Jesse Barnes | 75dfca8 | 2010-02-10 15:09:44 -0800 | [diff] [blame] | 4930 | drm_gem_object_unreference(work->pending_flip_obj); |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 4931 | drm_gem_object_unreference(work->old_fb_obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4932 | mutex_unlock(&work->dev->struct_mutex); |
| 4933 | kfree(work); |
| 4934 | } |
| 4935 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 4936 | static void do_intel_finish_page_flip(struct drm_device *dev, |
| 4937 | struct drm_crtc *crtc) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4938 | { |
| 4939 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4940 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4941 | struct intel_unpin_work *work; |
| 4942 | struct drm_i915_gem_object *obj_priv; |
| 4943 | struct drm_pending_vblank_event *e; |
| 4944 | struct timeval now; |
| 4945 | unsigned long flags; |
| 4946 | |
| 4947 | /* Ignore early vblank irqs */ |
| 4948 | if (intel_crtc == NULL) |
| 4949 | return; |
| 4950 | |
| 4951 | spin_lock_irqsave(&dev->event_lock, flags); |
| 4952 | work = intel_crtc->unpin_work; |
| 4953 | if (work == NULL || !work->pending) { |
| 4954 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 4955 | return; |
| 4956 | } |
| 4957 | |
| 4958 | intel_crtc->unpin_work = NULL; |
| 4959 | drm_vblank_put(dev, intel_crtc->pipe); |
| 4960 | |
| 4961 | if (work->event) { |
| 4962 | e = work->event; |
| 4963 | do_gettimeofday(&now); |
| 4964 | e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe); |
| 4965 | e->event.tv_sec = now.tv_sec; |
| 4966 | e->event.tv_usec = now.tv_usec; |
| 4967 | list_add_tail(&e->base.link, |
| 4968 | &e->base.file_priv->event_list); |
| 4969 | wake_up_interruptible(&e->base.file_priv->event_wait); |
| 4970 | } |
| 4971 | |
| 4972 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 4973 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4974 | obj_priv = to_intel_bo(work->pending_flip_obj); |
Jesse Barnes | de3f440 | 2010-01-14 13:18:02 -0800 | [diff] [blame] | 4975 | |
| 4976 | /* Initial scanout buffer will have a 0 pending flip count */ |
| 4977 | if ((atomic_read(&obj_priv->pending_flip) == 0) || |
| 4978 | atomic_dec_and_test(&obj_priv->pending_flip)) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4979 | DRM_WAKEUP(&dev_priv->pending_flip_queue); |
| 4980 | schedule_work(&work->work); |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 4981 | |
| 4982 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4983 | } |
| 4984 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 4985 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
| 4986 | { |
| 4987 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4988 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 4989 | |
| 4990 | do_intel_finish_page_flip(dev, crtc); |
| 4991 | } |
| 4992 | |
| 4993 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
| 4994 | { |
| 4995 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4996 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
| 4997 | |
| 4998 | do_intel_finish_page_flip(dev, crtc); |
| 4999 | } |
| 5000 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5001 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
| 5002 | { |
| 5003 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5004 | struct intel_crtc *intel_crtc = |
| 5005 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
| 5006 | unsigned long flags; |
| 5007 | |
| 5008 | spin_lock_irqsave(&dev->event_lock, flags); |
Jesse Barnes | de3f440 | 2010-01-14 13:18:02 -0800 | [diff] [blame] | 5009 | if (intel_crtc->unpin_work) { |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 5010 | if ((++intel_crtc->unpin_work->pending) > 1) |
| 5011 | DRM_ERROR("Prepared flip multiple times\n"); |
Jesse Barnes | de3f440 | 2010-01-14 13:18:02 -0800 | [diff] [blame] | 5012 | } else { |
| 5013 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); |
| 5014 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5015 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 5016 | } |
| 5017 | |
| 5018 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
| 5019 | struct drm_framebuffer *fb, |
| 5020 | struct drm_pending_vblank_event *event) |
| 5021 | { |
| 5022 | struct drm_device *dev = crtc->dev; |
| 5023 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5024 | struct intel_framebuffer *intel_fb; |
| 5025 | struct drm_i915_gem_object *obj_priv; |
| 5026 | struct drm_gem_object *obj; |
| 5027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5028 | struct intel_unpin_work *work; |
Jesse Barnes | be9a3db | 2010-07-23 12:03:37 -0700 | [diff] [blame] | 5029 | unsigned long flags, offset; |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 5030 | int pipe = intel_crtc->pipe; |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 5031 | u32 was_dirty, pf, pipesrc; |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 5032 | int ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5033 | |
| 5034 | work = kzalloc(sizeof *work, GFP_KERNEL); |
| 5035 | if (work == NULL) |
| 5036 | return -ENOMEM; |
| 5037 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5038 | work->event = event; |
| 5039 | work->dev = crtc->dev; |
| 5040 | intel_fb = to_intel_framebuffer(crtc->fb); |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 5041 | work->old_fb_obj = intel_fb->obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5042 | INIT_WORK(&work->work, intel_unpin_work_fn); |
| 5043 | |
| 5044 | /* We borrow the event spin lock for protecting unpin_work */ |
| 5045 | spin_lock_irqsave(&dev->event_lock, flags); |
| 5046 | if (intel_crtc->unpin_work) { |
| 5047 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 5048 | kfree(work); |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 5049 | |
| 5050 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5051 | return -EBUSY; |
| 5052 | } |
| 5053 | intel_crtc->unpin_work = work; |
| 5054 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 5055 | |
| 5056 | intel_fb = to_intel_framebuffer(fb); |
| 5057 | obj = intel_fb->obj; |
| 5058 | |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 5059 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 5060 | was_dirty = obj->write_domain & I915_GEM_GPU_DOMAINS; |
| 5061 | ret = intel_pin_and_fence_fb_obj(dev, obj, true); |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 5062 | if (ret) |
| 5063 | goto cleanup_work; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5064 | |
Jesse Barnes | 75dfca8 | 2010-02-10 15:09:44 -0800 | [diff] [blame] | 5065 | /* Reference the objects for the scheduled work. */ |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 5066 | drm_gem_object_reference(work->old_fb_obj); |
Jesse Barnes | 75dfca8 | 2010-02-10 15:09:44 -0800 | [diff] [blame] | 5067 | drm_gem_object_reference(obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5068 | |
| 5069 | crtc->fb = fb; |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 5070 | |
| 5071 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
| 5072 | if (ret) |
| 5073 | goto cleanup_objs; |
| 5074 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 5075 | obj_priv = to_intel_bo(obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5076 | atomic_inc(&obj_priv->pending_flip); |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 5077 | work->pending_flip_obj = obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5078 | |
Chris Wilson | c7f9f9a | 2010-09-19 15:05:13 +0100 | [diff] [blame] | 5079 | /* Schedule the pipelined flush */ |
| 5080 | if (was_dirty) |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 5081 | i915_gem_flush_ring(dev, NULL, obj_priv->ring, 0, was_dirty); |
Chris Wilson | c7f9f9a | 2010-09-19 15:05:13 +0100 | [diff] [blame] | 5082 | |
| 5083 | if (IS_GEN3(dev) || IS_GEN2(dev)) { |
| 5084 | u32 flip_mask; |
| 5085 | |
| 5086 | /* Can't queue multiple flips, so wait for the previous |
| 5087 | * one to finish before executing the next. |
| 5088 | */ |
Daniel Vetter | 6146b3d | 2010-08-04 21:22:10 +0200 | [diff] [blame] | 5089 | BEGIN_LP_RING(2); |
Chris Wilson | c7f9f9a | 2010-09-19 15:05:13 +0100 | [diff] [blame] | 5090 | if (intel_crtc->plane) |
| 5091 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 5092 | else |
| 5093 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 5094 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); |
| 5095 | OUT_RING(MI_NOOP); |
Daniel Vetter | 6146b3d | 2010-08-04 21:22:10 +0200 | [diff] [blame] | 5096 | ADVANCE_LP_RING(); |
| 5097 | } |
Jesse Barnes | 83f7fd0 | 2010-04-05 14:03:51 -0700 | [diff] [blame] | 5098 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 5099 | work->enable_stall_check = true; |
| 5100 | |
Jesse Barnes | be9a3db | 2010-07-23 12:03:37 -0700 | [diff] [blame] | 5101 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 5102 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; |
Jesse Barnes | be9a3db | 2010-07-23 12:03:37 -0700 | [diff] [blame] | 5103 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5104 | BEGIN_LP_RING(4); |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 5105 | switch(INTEL_INFO(dev)->gen) { |
| 5106 | case 2: |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 5107 | OUT_RING(MI_DISPLAY_FLIP | |
| 5108 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 5109 | OUT_RING(fb->pitch); |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 5110 | OUT_RING(obj_priv->gtt_offset + offset); |
| 5111 | OUT_RING(MI_NOOP); |
| 5112 | break; |
| 5113 | |
| 5114 | case 3: |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 5115 | OUT_RING(MI_DISPLAY_FLIP_I915 | |
| 5116 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 5117 | OUT_RING(fb->pitch); |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 5118 | OUT_RING(obj_priv->gtt_offset + offset); |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 5119 | OUT_RING(MI_NOOP); |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 5120 | break; |
| 5121 | |
| 5122 | case 4: |
| 5123 | case 5: |
| 5124 | /* i965+ uses the linear or tiled offsets from the |
| 5125 | * Display Registers (which do not change across a page-flip) |
| 5126 | * so we need only reprogram the base address. |
| 5127 | */ |
Daniel Vetter | 69d0b96 | 2010-08-04 21:22:09 +0200 | [diff] [blame] | 5128 | OUT_RING(MI_DISPLAY_FLIP | |
| 5129 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 5130 | OUT_RING(fb->pitch); |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 5131 | OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode); |
| 5132 | |
| 5133 | /* XXX Enabling the panel-fitter across page-flip is so far |
| 5134 | * untested on non-native modes, so ignore it for now. |
| 5135 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
| 5136 | */ |
| 5137 | pf = 0; |
| 5138 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; |
| 5139 | OUT_RING(pf | pipesrc); |
| 5140 | break; |
| 5141 | |
| 5142 | case 6: |
| 5143 | OUT_RING(MI_DISPLAY_FLIP | |
| 5144 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 5145 | OUT_RING(fb->pitch | obj_priv->tiling_mode); |
| 5146 | OUT_RING(obj_priv->gtt_offset); |
| 5147 | |
| 5148 | pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
| 5149 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; |
| 5150 | OUT_RING(pf | pipesrc); |
| 5151 | break; |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 5152 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5153 | ADVANCE_LP_RING(); |
| 5154 | |
| 5155 | mutex_unlock(&dev->struct_mutex); |
| 5156 | |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 5157 | trace_i915_flip_request(intel_crtc->plane, obj); |
| 5158 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5159 | return 0; |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 5160 | |
| 5161 | cleanup_objs: |
| 5162 | drm_gem_object_unreference(work->old_fb_obj); |
| 5163 | drm_gem_object_unreference(obj); |
| 5164 | cleanup_work: |
| 5165 | mutex_unlock(&dev->struct_mutex); |
| 5166 | |
| 5167 | spin_lock_irqsave(&dev->event_lock, flags); |
| 5168 | intel_crtc->unpin_work = NULL; |
| 5169 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 5170 | |
| 5171 | kfree(work); |
| 5172 | |
| 5173 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5174 | } |
| 5175 | |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 5176 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5177 | .dpms = intel_crtc_dpms, |
| 5178 | .mode_fixup = intel_crtc_mode_fixup, |
| 5179 | .mode_set = intel_crtc_mode_set, |
| 5180 | .mode_set_base = intel_pipe_set_base, |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 5181 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
Dave Airlie | 068143d | 2009-10-05 09:58:02 +1000 | [diff] [blame] | 5182 | .load_lut = intel_crtc_load_lut, |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 5183 | .disable = intel_crtc_disable, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5184 | }; |
| 5185 | |
| 5186 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
| 5187 | .cursor_set = intel_crtc_cursor_set, |
| 5188 | .cursor_move = intel_crtc_cursor_move, |
| 5189 | .gamma_set = intel_crtc_gamma_set, |
| 5190 | .set_config = drm_crtc_helper_set_config, |
| 5191 | .destroy = intel_crtc_destroy, |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5192 | .page_flip = intel_crtc_page_flip, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5193 | }; |
| 5194 | |
| 5195 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 5196 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5197 | { |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 5198 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5199 | struct intel_crtc *intel_crtc; |
| 5200 | int i; |
| 5201 | |
| 5202 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
| 5203 | if (intel_crtc == NULL) |
| 5204 | return; |
| 5205 | |
| 5206 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
| 5207 | |
| 5208 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5209 | for (i = 0; i < 256; i++) { |
| 5210 | intel_crtc->lut_r[i] = i; |
| 5211 | intel_crtc->lut_g[i] = i; |
| 5212 | intel_crtc->lut_b[i] = i; |
| 5213 | } |
| 5214 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 5215 | /* Swap pipes & planes for FBC on pre-965 */ |
| 5216 | intel_crtc->pipe = pipe; |
| 5217 | intel_crtc->plane = pipe; |
Chris Wilson | e2e767a | 2010-09-13 16:53:12 +0100 | [diff] [blame] | 5218 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 5219 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
Chris Wilson | e2e767a | 2010-09-13 16:53:12 +0100 | [diff] [blame] | 5220 | intel_crtc->plane = !pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 5221 | } |
| 5222 | |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 5223 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
| 5224 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
| 5225 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
| 5226 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
| 5227 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5228 | intel_crtc->cursor_addr = 0; |
Chris Wilson | 032d2a0 | 2010-09-06 16:17:22 +0100 | [diff] [blame] | 5229 | intel_crtc->dpms_mode = -1; |
Chris Wilson | e65d930 | 2010-09-13 16:58:39 +0100 | [diff] [blame] | 5230 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 5231 | |
| 5232 | if (HAS_PCH_SPLIT(dev)) { |
| 5233 | intel_helper_funcs.prepare = ironlake_crtc_prepare; |
| 5234 | intel_helper_funcs.commit = ironlake_crtc_commit; |
| 5235 | } else { |
| 5236 | intel_helper_funcs.prepare = i9xx_crtc_prepare; |
| 5237 | intel_helper_funcs.commit = i9xx_crtc_commit; |
| 5238 | } |
| 5239 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5240 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
| 5241 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5242 | intel_crtc->busy = false; |
| 5243 | |
| 5244 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, |
| 5245 | (unsigned long)intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5246 | } |
| 5247 | |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5248 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| 5249 | struct drm_file *file_priv) |
| 5250 | { |
| 5251 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5252 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 5253 | struct drm_mode_object *drmmode_obj; |
| 5254 | struct intel_crtc *crtc; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5255 | |
| 5256 | if (!dev_priv) { |
| 5257 | DRM_ERROR("called with no initialization\n"); |
| 5258 | return -EINVAL; |
| 5259 | } |
| 5260 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 5261 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
| 5262 | DRM_MODE_OBJECT_CRTC); |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5263 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 5264 | if (!drmmode_obj) { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5265 | DRM_ERROR("no such CRTC id\n"); |
| 5266 | return -EINVAL; |
| 5267 | } |
| 5268 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 5269 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
| 5270 | pipe_from_crtc_id->pipe = crtc->pipe; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5271 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 5272 | return 0; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5273 | } |
| 5274 | |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 5275 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5276 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 5277 | struct intel_encoder *encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5278 | int index_mask = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5279 | int entry = 0; |
| 5280 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 5281 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
| 5282 | if (type_mask & encoder->clone_mask) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5283 | index_mask |= (1 << entry); |
| 5284 | entry++; |
| 5285 | } |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 5286 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5287 | return index_mask; |
| 5288 | } |
| 5289 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5290 | static void intel_setup_outputs(struct drm_device *dev) |
| 5291 | { |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5292 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 5293 | struct intel_encoder *encoder; |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 5294 | bool dpd_is_edp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5295 | |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 5296 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5297 | intel_lvds_init(dev); |
| 5298 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 5299 | if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 5300 | dpd_is_edp = intel_dpd_is_edp(dev); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 5301 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 5302 | if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED)) |
| 5303 | intel_dp_init(dev, DP_A); |
| 5304 | |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 5305 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
| 5306 | intel_dp_init(dev, PCH_DP_D); |
| 5307 | } |
| 5308 | |
| 5309 | intel_crt_init(dev); |
| 5310 | |
| 5311 | if (HAS_PCH_SPLIT(dev)) { |
| 5312 | int found; |
| 5313 | |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 5314 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 5315 | /* PCH SDVOB multiplex with HDMIB */ |
| 5316 | found = intel_sdvo_init(dev, PCH_SDVOB); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 5317 | if (!found) |
| 5318 | intel_hdmi_init(dev, HDMIB); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 5319 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
| 5320 | intel_dp_init(dev, PCH_DP_B); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 5321 | } |
| 5322 | |
| 5323 | if (I915_READ(HDMIC) & PORT_DETECTED) |
| 5324 | intel_hdmi_init(dev, HDMIC); |
| 5325 | |
| 5326 | if (I915_READ(HDMID) & PORT_DETECTED) |
| 5327 | intel_hdmi_init(dev, HDMID); |
| 5328 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 5329 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
| 5330 | intel_dp_init(dev, PCH_DP_C); |
| 5331 | |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 5332 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 5333 | intel_dp_init(dev, PCH_DP_D); |
| 5334 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 5335 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 5336 | bool found = false; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 5337 | |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5338 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5339 | DRM_DEBUG_KMS("probing SDVOB\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5340 | found = intel_sdvo_init(dev, SDVOB); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5341 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 5342 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5343 | intel_hdmi_init(dev, SDVOB); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5344 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 5345 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5346 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
| 5347 | DRM_DEBUG_KMS("probing DP_B\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5348 | intel_dp_init(dev, DP_B); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5349 | } |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5350 | } |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 5351 | |
| 5352 | /* Before G4X SDVOC doesn't have its own detect register */ |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 5353 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5354 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
| 5355 | DRM_DEBUG_KMS("probing SDVOC\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5356 | found = intel_sdvo_init(dev, SDVOC); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5357 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 5358 | |
| 5359 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { |
| 5360 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5361 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 5362 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5363 | intel_hdmi_init(dev, SDVOC); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5364 | } |
| 5365 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
| 5366 | DRM_DEBUG_KMS("probing DP_C\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5367 | intel_dp_init(dev, DP_C); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5368 | } |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5369 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 5370 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5371 | if (SUPPORTS_INTEGRATED_DP(dev) && |
| 5372 | (I915_READ(DP_D) & DP_DETECTED)) { |
| 5373 | DRM_DEBUG_KMS("probing DP_D\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5374 | intel_dp_init(dev, DP_D); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5375 | } |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 5376 | } else if (IS_GEN2(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5377 | intel_dvo_init(dev); |
| 5378 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 5379 | if (SUPPORTS_TV(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5380 | intel_tv_init(dev); |
| 5381 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 5382 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
| 5383 | encoder->base.possible_crtcs = encoder->crtc_mask; |
| 5384 | encoder->base.possible_clones = |
| 5385 | intel_encoder_clones(dev, encoder->clone_mask); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5386 | } |
| 5387 | } |
| 5388 | |
| 5389 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 5390 | { |
| 5391 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5392 | |
| 5393 | drm_framebuffer_cleanup(fb); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 5394 | drm_gem_object_unreference_unlocked(intel_fb->obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5395 | |
| 5396 | kfree(intel_fb); |
| 5397 | } |
| 5398 | |
| 5399 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
| 5400 | struct drm_file *file_priv, |
| 5401 | unsigned int *handle) |
| 5402 | { |
| 5403 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 5404 | struct drm_gem_object *object = intel_fb->obj; |
| 5405 | |
| 5406 | return drm_gem_handle_create(file_priv, object, handle); |
| 5407 | } |
| 5408 | |
| 5409 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 5410 | .destroy = intel_user_framebuffer_destroy, |
| 5411 | .create_handle = intel_user_framebuffer_create_handle, |
| 5412 | }; |
| 5413 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5414 | int intel_framebuffer_init(struct drm_device *dev, |
| 5415 | struct intel_framebuffer *intel_fb, |
| 5416 | struct drm_mode_fb_cmd *mode_cmd, |
| 5417 | struct drm_gem_object *obj) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5418 | { |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 5419 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5420 | int ret; |
| 5421 | |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 5422 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 5423 | return -EINVAL; |
| 5424 | |
| 5425 | if (mode_cmd->pitch & 63) |
| 5426 | return -EINVAL; |
| 5427 | |
| 5428 | switch (mode_cmd->bpp) { |
| 5429 | case 8: |
| 5430 | case 16: |
| 5431 | case 24: |
| 5432 | case 32: |
| 5433 | break; |
| 5434 | default: |
| 5435 | return -EINVAL; |
| 5436 | } |
| 5437 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5438 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
| 5439 | if (ret) { |
| 5440 | DRM_ERROR("framebuffer init failed %d\n", ret); |
| 5441 | return ret; |
| 5442 | } |
| 5443 | |
| 5444 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5445 | intel_fb->obj = obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5446 | return 0; |
| 5447 | } |
| 5448 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5449 | static struct drm_framebuffer * |
| 5450 | intel_user_framebuffer_create(struct drm_device *dev, |
| 5451 | struct drm_file *filp, |
| 5452 | struct drm_mode_fb_cmd *mode_cmd) |
| 5453 | { |
| 5454 | struct drm_gem_object *obj; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5455 | struct intel_framebuffer *intel_fb; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5456 | int ret; |
| 5457 | |
| 5458 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); |
| 5459 | if (!obj) |
Chris Wilson | cce13ff | 2010-08-08 13:36:38 +0100 | [diff] [blame] | 5460 | return ERR_PTR(-ENOENT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5461 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5462 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
| 5463 | if (!intel_fb) |
Chris Wilson | cce13ff | 2010-08-08 13:36:38 +0100 | [diff] [blame] | 5464 | return ERR_PTR(-ENOMEM); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5465 | |
| 5466 | ret = intel_framebuffer_init(dev, intel_fb, |
| 5467 | mode_cmd, obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5468 | if (ret) { |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 5469 | drm_gem_object_unreference_unlocked(obj); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5470 | kfree(intel_fb); |
Chris Wilson | cce13ff | 2010-08-08 13:36:38 +0100 | [diff] [blame] | 5471 | return ERR_PTR(ret); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5472 | } |
| 5473 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5474 | return &intel_fb->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5475 | } |
| 5476 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5477 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5478 | .fb_create = intel_user_framebuffer_create, |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 5479 | .output_poll_changed = intel_fb_output_poll_changed, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5480 | }; |
| 5481 | |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5482 | static struct drm_gem_object * |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5483 | intel_alloc_context_page(struct drm_device *dev) |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5484 | { |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5485 | struct drm_gem_object *ctx; |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5486 | int ret; |
| 5487 | |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5488 | ctx = i915_gem_alloc_object(dev, 4096); |
| 5489 | if (!ctx) { |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5490 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
| 5491 | return NULL; |
| 5492 | } |
| 5493 | |
| 5494 | mutex_lock(&dev->struct_mutex); |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5495 | ret = i915_gem_object_pin(ctx, 4096); |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5496 | if (ret) { |
| 5497 | DRM_ERROR("failed to pin power context: %d\n", ret); |
| 5498 | goto err_unref; |
| 5499 | } |
| 5500 | |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5501 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5502 | if (ret) { |
| 5503 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
| 5504 | goto err_unpin; |
| 5505 | } |
| 5506 | mutex_unlock(&dev->struct_mutex); |
| 5507 | |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5508 | return ctx; |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5509 | |
| 5510 | err_unpin: |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5511 | i915_gem_object_unpin(ctx); |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5512 | err_unref: |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5513 | drm_gem_object_unreference(ctx); |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5514 | mutex_unlock(&dev->struct_mutex); |
| 5515 | return NULL; |
| 5516 | } |
| 5517 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5518 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
| 5519 | { |
| 5520 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5521 | u16 rgvswctl; |
| 5522 | |
| 5523 | rgvswctl = I915_READ16(MEMSWCTL); |
| 5524 | if (rgvswctl & MEMCTL_CMD_STS) { |
| 5525 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
| 5526 | return false; /* still busy with another command */ |
| 5527 | } |
| 5528 | |
| 5529 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
| 5530 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
| 5531 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 5532 | POSTING_READ16(MEMSWCTL); |
| 5533 | |
| 5534 | rgvswctl |= MEMCTL_CMD_STS; |
| 5535 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 5536 | |
| 5537 | return true; |
| 5538 | } |
| 5539 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5540 | void ironlake_enable_drps(struct drm_device *dev) |
| 5541 | { |
| 5542 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5543 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5544 | u8 fmax, fmin, fstart, vstart; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5545 | |
Jesse Barnes | ea056c1 | 2010-09-10 10:02:13 -0700 | [diff] [blame] | 5546 | /* Enable temp reporting */ |
| 5547 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
| 5548 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
| 5549 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5550 | /* 100ms RC evaluation intervals */ |
| 5551 | I915_WRITE(RCUPEI, 100000); |
| 5552 | I915_WRITE(RCDNEI, 100000); |
| 5553 | |
| 5554 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
| 5555 | I915_WRITE(RCBMAXAVG, 90000); |
| 5556 | I915_WRITE(RCBMINAVG, 80000); |
| 5557 | |
| 5558 | I915_WRITE(MEMIHYST, 1); |
| 5559 | |
| 5560 | /* Set up min, max, and cur for interrupt handling */ |
| 5561 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
| 5562 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
| 5563 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
| 5564 | MEMMODE_FSTART_SHIFT; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5565 | fstart = fmax; |
| 5566 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5567 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
| 5568 | PXVFREQ_PX_SHIFT; |
| 5569 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5570 | dev_priv->fmax = fstart; /* IPS callback will increase this */ |
| 5571 | dev_priv->fstart = fstart; |
| 5572 | |
| 5573 | dev_priv->max_delay = fmax; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5574 | dev_priv->min_delay = fmin; |
| 5575 | dev_priv->cur_delay = fstart; |
| 5576 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5577 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin, |
| 5578 | fstart); |
| 5579 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5580 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
| 5581 | |
| 5582 | /* |
| 5583 | * Interrupts will be enabled in ironlake_irq_postinstall |
| 5584 | */ |
| 5585 | |
| 5586 | I915_WRITE(VIDSTART, vstart); |
| 5587 | POSTING_READ(VIDSTART); |
| 5588 | |
| 5589 | rgvmodectl |= MEMMODE_SWMODE_EN; |
| 5590 | I915_WRITE(MEMMODECTL, rgvmodectl); |
| 5591 | |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 5592 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 5593 | DRM_ERROR("stuck trying to change perf mode\n"); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5594 | msleep(1); |
| 5595 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5596 | ironlake_set_drps(dev, fstart); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5597 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5598 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
| 5599 | I915_READ(0x112e0); |
| 5600 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); |
| 5601 | dev_priv->last_count2 = I915_READ(0x112f4); |
| 5602 | getrawmonotonic(&dev_priv->last_time2); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5603 | } |
| 5604 | |
| 5605 | void ironlake_disable_drps(struct drm_device *dev) |
| 5606 | { |
| 5607 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5608 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5609 | |
| 5610 | /* Ack interrupts, disable EFC interrupt */ |
| 5611 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
| 5612 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
| 5613 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
| 5614 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 5615 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
| 5616 | |
| 5617 | /* Go back to the starting frequency */ |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5618 | ironlake_set_drps(dev, dev_priv->fstart); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5619 | msleep(1); |
| 5620 | rgvswctl |= MEMCTL_CMD_STS; |
| 5621 | I915_WRITE(MEMSWCTL, rgvswctl); |
| 5622 | msleep(1); |
| 5623 | |
| 5624 | } |
| 5625 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5626 | static unsigned long intel_pxfreq(u32 vidfreq) |
| 5627 | { |
| 5628 | unsigned long freq; |
| 5629 | int div = (vidfreq & 0x3f0000) >> 16; |
| 5630 | int post = (vidfreq & 0x3000) >> 12; |
| 5631 | int pre = (vidfreq & 0x7); |
| 5632 | |
| 5633 | if (!pre) |
| 5634 | return 0; |
| 5635 | |
| 5636 | freq = ((div * 133333) / ((1<<post) * pre)); |
| 5637 | |
| 5638 | return freq; |
| 5639 | } |
| 5640 | |
| 5641 | void intel_init_emon(struct drm_device *dev) |
| 5642 | { |
| 5643 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5644 | u32 lcfuse; |
| 5645 | u8 pxw[16]; |
| 5646 | int i; |
| 5647 | |
| 5648 | /* Disable to program */ |
| 5649 | I915_WRITE(ECR, 0); |
| 5650 | POSTING_READ(ECR); |
| 5651 | |
| 5652 | /* Program energy weights for various events */ |
| 5653 | I915_WRITE(SDEW, 0x15040d00); |
| 5654 | I915_WRITE(CSIEW0, 0x007f0000); |
| 5655 | I915_WRITE(CSIEW1, 0x1e220004); |
| 5656 | I915_WRITE(CSIEW2, 0x04000004); |
| 5657 | |
| 5658 | for (i = 0; i < 5; i++) |
| 5659 | I915_WRITE(PEW + (i * 4), 0); |
| 5660 | for (i = 0; i < 3; i++) |
| 5661 | I915_WRITE(DEW + (i * 4), 0); |
| 5662 | |
| 5663 | /* Program P-state weights to account for frequency power adjustment */ |
| 5664 | for (i = 0; i < 16; i++) { |
| 5665 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
| 5666 | unsigned long freq = intel_pxfreq(pxvidfreq); |
| 5667 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
| 5668 | PXVFREQ_PX_SHIFT; |
| 5669 | unsigned long val; |
| 5670 | |
| 5671 | val = vid * vid; |
| 5672 | val *= (freq / 1000); |
| 5673 | val *= 255; |
| 5674 | val /= (127*127*900); |
| 5675 | if (val > 0xff) |
| 5676 | DRM_ERROR("bad pxval: %ld\n", val); |
| 5677 | pxw[i] = val; |
| 5678 | } |
| 5679 | /* Render standby states get 0 weight */ |
| 5680 | pxw[14] = 0; |
| 5681 | pxw[15] = 0; |
| 5682 | |
| 5683 | for (i = 0; i < 4; i++) { |
| 5684 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
| 5685 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
| 5686 | I915_WRITE(PXW + (i * 4), val); |
| 5687 | } |
| 5688 | |
| 5689 | /* Adjust magic regs to magic values (more experimental results) */ |
| 5690 | I915_WRITE(OGW0, 0); |
| 5691 | I915_WRITE(OGW1, 0); |
| 5692 | I915_WRITE(EG0, 0x00007f00); |
| 5693 | I915_WRITE(EG1, 0x0000000e); |
| 5694 | I915_WRITE(EG2, 0x000e0000); |
| 5695 | I915_WRITE(EG3, 0x68000300); |
| 5696 | I915_WRITE(EG4, 0x42000000); |
| 5697 | I915_WRITE(EG5, 0x00140031); |
| 5698 | I915_WRITE(EG6, 0); |
| 5699 | I915_WRITE(EG7, 0); |
| 5700 | |
| 5701 | for (i = 0; i < 8; i++) |
| 5702 | I915_WRITE(PXWL + (i * 4), 0); |
| 5703 | |
| 5704 | /* Enable PMON + select events */ |
| 5705 | I915_WRITE(ECR, 0x80000019); |
| 5706 | |
| 5707 | lcfuse = I915_READ(LCFUSE02); |
| 5708 | |
| 5709 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); |
| 5710 | } |
| 5711 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5712 | void intel_init_clock_gating(struct drm_device *dev) |
| 5713 | { |
| 5714 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5715 | |
| 5716 | /* |
| 5717 | * Disable clock gating reported to work incorrectly according to the |
| 5718 | * specs, but enable as much else as we can. |
| 5719 | */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 5720 | if (HAS_PCH_SPLIT(dev)) { |
Eric Anholt | 8956c8b | 2010-03-18 13:21:14 -0700 | [diff] [blame] | 5721 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
| 5722 | |
| 5723 | if (IS_IRONLAKE(dev)) { |
| 5724 | /* Required for FBC */ |
| 5725 | dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; |
| 5726 | /* Required for CxSR */ |
| 5727 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; |
| 5728 | |
| 5729 | I915_WRITE(PCH_3DCGDIS0, |
| 5730 | MARIUNIT_CLOCK_GATE_DISABLE | |
| 5731 | SVSMUNIT_CLOCK_GATE_DISABLE); |
| 5732 | } |
| 5733 | |
| 5734 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 5735 | |
| 5736 | /* |
| 5737 | * According to the spec the following bits should be set in |
| 5738 | * order to enable memory self-refresh |
| 5739 | * The bit 22/21 of 0x42004 |
| 5740 | * The bit 5 of 0x42020 |
| 5741 | * The bit 15 of 0x45000 |
| 5742 | */ |
| 5743 | if (IS_IRONLAKE(dev)) { |
| 5744 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5745 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5746 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
| 5747 | I915_WRITE(ILK_DSPCLK_GATE, |
| 5748 | (I915_READ(ILK_DSPCLK_GATE) | |
| 5749 | ILK_DPARB_CLK_GATE)); |
| 5750 | I915_WRITE(DISP_ARB_CTL, |
| 5751 | (I915_READ(DISP_ARB_CTL) | |
| 5752 | DISP_FBC_WM_DIS)); |
Jesse Barnes | dd8849c | 2010-09-09 11:58:02 -0700 | [diff] [blame] | 5753 | I915_WRITE(WM3_LP_ILK, 0); |
| 5754 | I915_WRITE(WM2_LP_ILK, 0); |
| 5755 | I915_WRITE(WM1_LP_ILK, 0); |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 5756 | } |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 5757 | /* |
| 5758 | * Based on the document from hardware guys the following bits |
| 5759 | * should be set unconditionally in order to enable FBC. |
| 5760 | * The bit 22 of 0x42000 |
| 5761 | * The bit 22 of 0x42004 |
| 5762 | * The bit 7,8,9 of 0x42020. |
| 5763 | */ |
| 5764 | if (IS_IRONLAKE_M(dev)) { |
| 5765 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 5766 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 5767 | ILK_FBCQ_DIS); |
| 5768 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5769 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5770 | ILK_DPARB_GATE); |
| 5771 | I915_WRITE(ILK_DSPCLK_GATE, |
| 5772 | I915_READ(ILK_DSPCLK_GATE) | |
| 5773 | ILK_DPFC_DIS1 | |
| 5774 | ILK_DPFC_DIS2 | |
| 5775 | ILK_CLK_FBC); |
| 5776 | } |
Chris Wilson | bc41606 | 2010-09-07 21:51:02 +0100 | [diff] [blame] | 5777 | return; |
Zhenyu Wang | c03342f | 2009-09-29 11:01:23 +0800 | [diff] [blame] | 5778 | } else if (IS_G4X(dev)) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5779 | uint32_t dspclk_gate; |
| 5780 | I915_WRITE(RENCLK_GATE_D1, 0); |
| 5781 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
| 5782 | GS_UNIT_CLOCK_GATE_DISABLE | |
| 5783 | CL_UNIT_CLOCK_GATE_DISABLE); |
| 5784 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 5785 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
| 5786 | OVRUNIT_CLOCK_GATE_DISABLE | |
| 5787 | OVCUNIT_CLOCK_GATE_DISABLE; |
| 5788 | if (IS_GM45(dev)) |
| 5789 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
| 5790 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 5791 | } else if (IS_CRESTLINE(dev)) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5792 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
| 5793 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 5794 | I915_WRITE(DSPCLK_GATE_D, 0); |
| 5795 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 5796 | I915_WRITE16(DEUC, 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 5797 | } else if (IS_BROADWATER(dev)) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5798 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
| 5799 | I965_RCC_CLOCK_GATE_DISABLE | |
| 5800 | I965_RCPB_CLOCK_GATE_DISABLE | |
| 5801 | I965_ISC_CLOCK_GATE_DISABLE | |
| 5802 | I965_FBC_CLOCK_GATE_DISABLE); |
| 5803 | I915_WRITE(RENCLK_GATE_D2, 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 5804 | } else if (IS_GEN3(dev)) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5805 | u32 dstate = I915_READ(D_STATE); |
| 5806 | |
| 5807 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
| 5808 | DSTATE_DOT_CLOCK_GATING; |
| 5809 | I915_WRITE(D_STATE, dstate); |
Daniel Vetter | f0f8a9c | 2009-09-15 22:57:33 +0200 | [diff] [blame] | 5810 | } else if (IS_I85X(dev) || IS_I865G(dev)) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5811 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
| 5812 | } else if (IS_I830(dev)) { |
| 5813 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
| 5814 | } |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 5815 | |
| 5816 | /* |
| 5817 | * GPU can automatically power down the render unit if given a page |
| 5818 | * to save state. |
| 5819 | */ |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5820 | if (IS_IRONLAKE_M(dev)) { |
| 5821 | if (dev_priv->renderctx == NULL) |
| 5822 | dev_priv->renderctx = intel_alloc_context_page(dev); |
| 5823 | if (dev_priv->renderctx) { |
| 5824 | struct drm_i915_gem_object *obj_priv; |
| 5825 | obj_priv = to_intel_bo(dev_priv->renderctx); |
| 5826 | if (obj_priv) { |
| 5827 | BEGIN_LP_RING(4); |
| 5828 | OUT_RING(MI_SET_CONTEXT); |
| 5829 | OUT_RING(obj_priv->gtt_offset | |
| 5830 | MI_MM_SPACE_GTT | |
| 5831 | MI_SAVE_EXT_STATE_EN | |
| 5832 | MI_RESTORE_EXT_STATE_EN | |
| 5833 | MI_RESTORE_INHIBIT); |
| 5834 | OUT_RING(MI_NOOP); |
| 5835 | OUT_RING(MI_FLUSH); |
| 5836 | ADVANCE_LP_RING(); |
| 5837 | } |
Chris Wilson | bc41606 | 2010-09-07 21:51:02 +0100 | [diff] [blame] | 5838 | } else |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5839 | DRM_DEBUG_KMS("Failed to allocate render context." |
Chris Wilson | bc41606 | 2010-09-07 21:51:02 +0100 | [diff] [blame] | 5840 | "Disable RC6\n"); |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5841 | } |
| 5842 | |
Andrew Lutomirski | 1d3c36ad | 2009-12-21 10:10:22 -0500 | [diff] [blame] | 5843 | if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5844 | struct drm_i915_gem_object *obj_priv = NULL; |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 5845 | |
Andrew Lutomirski | 7e8b60f | 2009-11-08 13:49:51 -0500 | [diff] [blame] | 5846 | if (dev_priv->pwrctx) { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 5847 | obj_priv = to_intel_bo(dev_priv->pwrctx); |
Andrew Lutomirski | 7e8b60f | 2009-11-08 13:49:51 -0500 | [diff] [blame] | 5848 | } else { |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5849 | struct drm_gem_object *pwrctx; |
| 5850 | |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 5851 | pwrctx = intel_alloc_context_page(dev); |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5852 | if (pwrctx) { |
| 5853 | dev_priv->pwrctx = pwrctx; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 5854 | obj_priv = to_intel_bo(pwrctx); |
Andrew Lutomirski | 7e8b60f | 2009-11-08 13:49:51 -0500 | [diff] [blame] | 5855 | } |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 5856 | } |
| 5857 | |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5858 | if (obj_priv) { |
| 5859 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); |
| 5860 | I915_WRITE(MCHBAR_RENDER_STANDBY, |
| 5861 | I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); |
| 5862 | } |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 5863 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5864 | } |
| 5865 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5866 | /* Set up chip specific display functions */ |
| 5867 | static void intel_init_display(struct drm_device *dev) |
| 5868 | { |
| 5869 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5870 | |
| 5871 | /* We always want a DPMS function */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 5872 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 5873 | dev_priv->display.dpms = ironlake_crtc_dpms; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5874 | else |
| 5875 | dev_priv->display.dpms = i9xx_crtc_dpms; |
| 5876 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 5877 | if (I915_HAS_FBC(dev)) { |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 5878 | if (IS_IRONLAKE_M(dev)) { |
| 5879 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
| 5880 | dev_priv->display.enable_fbc = ironlake_enable_fbc; |
| 5881 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
| 5882 | } else if (IS_GM45(dev)) { |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 5883 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
| 5884 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
| 5885 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 5886 | } else if (IS_CRESTLINE(dev)) { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5887 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
| 5888 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
| 5889 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
| 5890 | } |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 5891 | /* 855GM needs testing */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5892 | } |
| 5893 | |
| 5894 | /* Returns the core display clock speed */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 5895 | if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev))) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5896 | dev_priv->display.get_display_clock_speed = |
| 5897 | i945_get_display_clock_speed; |
| 5898 | else if (IS_I915G(dev)) |
| 5899 | dev_priv->display.get_display_clock_speed = |
| 5900 | i915_get_display_clock_speed; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 5901 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5902 | dev_priv->display.get_display_clock_speed = |
| 5903 | i9xx_misc_get_display_clock_speed; |
| 5904 | else if (IS_I915GM(dev)) |
| 5905 | dev_priv->display.get_display_clock_speed = |
| 5906 | i915gm_get_display_clock_speed; |
| 5907 | else if (IS_I865G(dev)) |
| 5908 | dev_priv->display.get_display_clock_speed = |
| 5909 | i865_get_display_clock_speed; |
Daniel Vetter | f0f8a9c | 2009-09-15 22:57:33 +0200 | [diff] [blame] | 5910 | else if (IS_I85X(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5911 | dev_priv->display.get_display_clock_speed = |
| 5912 | i855_get_display_clock_speed; |
| 5913 | else /* 852, 830 */ |
| 5914 | dev_priv->display.get_display_clock_speed = |
| 5915 | i830_get_display_clock_speed; |
| 5916 | |
| 5917 | /* For FIFO watermark updates */ |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 5918 | if (HAS_PCH_SPLIT(dev)) { |
| 5919 | if (IS_IRONLAKE(dev)) { |
| 5920 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
| 5921 | dev_priv->display.update_wm = ironlake_update_wm; |
| 5922 | else { |
| 5923 | DRM_DEBUG_KMS("Failed to get proper latency. " |
| 5924 | "Disable CxSR\n"); |
| 5925 | dev_priv->display.update_wm = NULL; |
| 5926 | } |
| 5927 | } else |
| 5928 | dev_priv->display.update_wm = NULL; |
| 5929 | } else if (IS_PINEVIEW(dev)) { |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 5930 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 5931 | dev_priv->is_ddr3, |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 5932 | dev_priv->fsb_freq, |
| 5933 | dev_priv->mem_freq)) { |
| 5934 | DRM_INFO("failed to find known CxSR latency " |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 5935 | "(found ddr%s fsb freq %d, mem freq %d), " |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 5936 | "disabling CxSR\n", |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 5937 | (dev_priv->is_ddr3 == 1) ? "3": "2", |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 5938 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 5939 | /* Disable CxSR and never update its watermark again */ |
| 5940 | pineview_disable_cxsr(dev); |
| 5941 | dev_priv->display.update_wm = NULL; |
| 5942 | } else |
| 5943 | dev_priv->display.update_wm = pineview_update_wm; |
| 5944 | } else if (IS_G4X(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5945 | dev_priv->display.update_wm = g4x_update_wm; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 5946 | else if (IS_GEN4(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5947 | dev_priv->display.update_wm = i965_update_wm; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 5948 | else if (IS_GEN3(dev)) { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5949 | dev_priv->display.update_wm = i9xx_update_wm; |
| 5950 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
Adam Jackson | 8f4695e | 2010-04-16 18:20:57 -0400 | [diff] [blame] | 5951 | } else if (IS_I85X(dev)) { |
| 5952 | dev_priv->display.update_wm = i9xx_update_wm; |
| 5953 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5954 | } else { |
Adam Jackson | 8f4695e | 2010-04-16 18:20:57 -0400 | [diff] [blame] | 5955 | dev_priv->display.update_wm = i830_update_wm; |
| 5956 | if (IS_845G(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5957 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
| 5958 | else |
| 5959 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5960 | } |
| 5961 | } |
| 5962 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 5963 | /* |
| 5964 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
| 5965 | * resume, or other times. This quirk makes sure that's the case for |
| 5966 | * affected systems. |
| 5967 | */ |
| 5968 | static void quirk_pipea_force (struct drm_device *dev) |
| 5969 | { |
| 5970 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5971 | |
| 5972 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
| 5973 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); |
| 5974 | } |
| 5975 | |
| 5976 | struct intel_quirk { |
| 5977 | int device; |
| 5978 | int subsystem_vendor; |
| 5979 | int subsystem_device; |
| 5980 | void (*hook)(struct drm_device *dev); |
| 5981 | }; |
| 5982 | |
| 5983 | struct intel_quirk intel_quirks[] = { |
| 5984 | /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ |
| 5985 | { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, |
| 5986 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
| 5987 | { 0x27ae,0x103c, 0x361a, quirk_pipea_force }, |
| 5988 | |
| 5989 | /* Thinkpad R31 needs pipe A force quirk */ |
| 5990 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, |
| 5991 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
| 5992 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
| 5993 | |
| 5994 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ |
| 5995 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, |
| 5996 | /* ThinkPad X40 needs pipe A force quirk */ |
| 5997 | |
| 5998 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
| 5999 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
| 6000 | |
| 6001 | /* 855 & before need to leave pipe A & dpll A up */ |
| 6002 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
| 6003 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
| 6004 | }; |
| 6005 | |
| 6006 | static void intel_init_quirks(struct drm_device *dev) |
| 6007 | { |
| 6008 | struct pci_dev *d = dev->pdev; |
| 6009 | int i; |
| 6010 | |
| 6011 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
| 6012 | struct intel_quirk *q = &intel_quirks[i]; |
| 6013 | |
| 6014 | if (d->device == q->device && |
| 6015 | (d->subsystem_vendor == q->subsystem_vendor || |
| 6016 | q->subsystem_vendor == PCI_ANY_ID) && |
| 6017 | (d->subsystem_device == q->subsystem_device || |
| 6018 | q->subsystem_device == PCI_ANY_ID)) |
| 6019 | q->hook(dev); |
| 6020 | } |
| 6021 | } |
| 6022 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 6023 | /* Disable the VGA plane that we never use */ |
| 6024 | static void i915_disable_vga(struct drm_device *dev) |
| 6025 | { |
| 6026 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6027 | u8 sr1; |
| 6028 | u32 vga_reg; |
| 6029 | |
| 6030 | if (HAS_PCH_SPLIT(dev)) |
| 6031 | vga_reg = CPU_VGACNTRL; |
| 6032 | else |
| 6033 | vga_reg = VGACNTRL; |
| 6034 | |
| 6035 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 6036 | outb(1, VGA_SR_INDEX); |
| 6037 | sr1 = inb(VGA_SR_DATA); |
| 6038 | outb(sr1 | 1<<5, VGA_SR_DATA); |
| 6039 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 6040 | udelay(300); |
| 6041 | |
| 6042 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
| 6043 | POSTING_READ(vga_reg); |
| 6044 | } |
| 6045 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6046 | void intel_modeset_init(struct drm_device *dev) |
| 6047 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6048 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6049 | int i; |
| 6050 | |
| 6051 | drm_mode_config_init(dev); |
| 6052 | |
| 6053 | dev->mode_config.min_width = 0; |
| 6054 | dev->mode_config.min_height = 0; |
| 6055 | |
| 6056 | dev->mode_config.funcs = (void *)&intel_mode_funcs; |
| 6057 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 6058 | intel_init_quirks(dev); |
| 6059 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6060 | intel_init_display(dev); |
| 6061 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 6062 | if (IS_GEN2(dev)) { |
| 6063 | dev->mode_config.max_width = 2048; |
| 6064 | dev->mode_config.max_height = 2048; |
| 6065 | } else if (IS_GEN3(dev)) { |
Keith Packard | 5e4d6fa | 2009-07-12 23:53:17 -0700 | [diff] [blame] | 6066 | dev->mode_config.max_width = 4096; |
| 6067 | dev->mode_config.max_height = 4096; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6068 | } else { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 6069 | dev->mode_config.max_width = 8192; |
| 6070 | dev->mode_config.max_height = 8192; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6071 | } |
| 6072 | |
| 6073 | /* set memory base */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 6074 | if (IS_GEN2(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6075 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 6076 | else |
| 6077 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6078 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 6079 | if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 6080 | dev_priv->num_pipe = 2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6081 | else |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 6082 | dev_priv->num_pipe = 1; |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 6083 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 6084 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6085 | |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 6086 | for (i = 0; i < dev_priv->num_pipe; i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6087 | intel_crtc_init(dev, i); |
| 6088 | } |
| 6089 | |
| 6090 | intel_setup_outputs(dev); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6091 | |
| 6092 | intel_init_clock_gating(dev); |
| 6093 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 6094 | /* Just disable it once at startup */ |
| 6095 | i915_disable_vga(dev); |
| 6096 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 6097 | if (IS_IRONLAKE_M(dev)) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 6098 | ironlake_enable_drps(dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 6099 | intel_init_emon(dev); |
| 6100 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 6101 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6102 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
| 6103 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, |
| 6104 | (unsigned long)dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 6105 | |
| 6106 | intel_setup_overlay(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6107 | } |
| 6108 | |
| 6109 | void intel_modeset_cleanup(struct drm_device *dev) |
| 6110 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6111 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6112 | struct drm_crtc *crtc; |
| 6113 | struct intel_crtc *intel_crtc; |
| 6114 | |
| 6115 | mutex_lock(&dev->struct_mutex); |
| 6116 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 6117 | drm_kms_helper_poll_fini(dev); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 6118 | intel_fbdev_fini(dev); |
| 6119 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6120 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 6121 | /* Skip inactive CRTCs */ |
| 6122 | if (!crtc->fb) |
| 6123 | continue; |
| 6124 | |
| 6125 | intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 6126 | intel_increase_pllclock(crtc); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6127 | } |
| 6128 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6129 | if (dev_priv->display.disable_fbc) |
| 6130 | dev_priv->display.disable_fbc(dev); |
| 6131 | |
Zou Nan hai | aa40d6b | 2010-06-25 13:40:23 +0800 | [diff] [blame] | 6132 | if (dev_priv->renderctx) { |
| 6133 | struct drm_i915_gem_object *obj_priv; |
| 6134 | |
| 6135 | obj_priv = to_intel_bo(dev_priv->renderctx); |
| 6136 | I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN); |
| 6137 | I915_READ(CCID); |
| 6138 | i915_gem_object_unpin(dev_priv->renderctx); |
| 6139 | drm_gem_object_unreference(dev_priv->renderctx); |
| 6140 | } |
| 6141 | |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 6142 | if (dev_priv->pwrctx) { |
Kristian Høgsberg | c1b5dea | 2009-11-11 12:19:18 -0500 | [diff] [blame] | 6143 | struct drm_i915_gem_object *obj_priv; |
| 6144 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 6145 | obj_priv = to_intel_bo(dev_priv->pwrctx); |
Kristian Høgsberg | c1b5dea | 2009-11-11 12:19:18 -0500 | [diff] [blame] | 6146 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN); |
| 6147 | I915_READ(PWRCTXA); |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 6148 | i915_gem_object_unpin(dev_priv->pwrctx); |
| 6149 | drm_gem_object_unreference(dev_priv->pwrctx); |
| 6150 | } |
| 6151 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 6152 | if (IS_IRONLAKE_M(dev)) |
| 6153 | ironlake_disable_drps(dev); |
| 6154 | |
Kristian Høgsberg | 69341a5 | 2009-11-11 12:19:17 -0500 | [diff] [blame] | 6155 | mutex_unlock(&dev->struct_mutex); |
| 6156 | |
Daniel Vetter | 6c0d9350 | 2010-08-20 18:26:46 +0200 | [diff] [blame] | 6157 | /* Disable the irq before mode object teardown, for the irq might |
| 6158 | * enqueue unpin/hotplug work. */ |
| 6159 | drm_irq_uninstall(dev); |
| 6160 | cancel_work_sync(&dev_priv->hotplug_work); |
| 6161 | |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 6162 | /* Shut off idle work before the crtcs get freed. */ |
| 6163 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 6164 | intel_crtc = to_intel_crtc(crtc); |
| 6165 | del_timer_sync(&intel_crtc->idle_timer); |
| 6166 | } |
| 6167 | del_timer_sync(&dev_priv->idle_timer); |
| 6168 | cancel_work_sync(&dev_priv->idle_work); |
| 6169 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6170 | drm_mode_config_cleanup(dev); |
| 6171 | } |
| 6172 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 6173 | /* |
Zhenyu Wang | f1c79df | 2010-03-30 14:39:29 +0800 | [diff] [blame] | 6174 | * Return which encoder is currently attached for connector. |
| 6175 | */ |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 6176 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6177 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 6178 | return &intel_attached_encoder(connector)->base; |
| 6179 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6180 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 6181 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 6182 | struct intel_encoder *encoder) |
| 6183 | { |
| 6184 | connector->encoder = encoder; |
| 6185 | drm_mode_connector_attach_encoder(&connector->base, |
| 6186 | &encoder->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6187 | } |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 6188 | |
| 6189 | /* |
| 6190 | * set vga decode state - true == enable VGA decode |
| 6191 | */ |
| 6192 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
| 6193 | { |
| 6194 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6195 | u16 gmch_ctrl; |
| 6196 | |
| 6197 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
| 6198 | if (state) |
| 6199 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
| 6200 | else |
| 6201 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
| 6202 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
| 6203 | return 0; |
| 6204 | } |